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ath9k: Use bitfields to store tid's state in a single variable
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.h
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/version.h>
21#include <linux/autoconf.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/in.h>
32#include <linux/delay.h>
33#include <linux/wait.h>
34#include <linux/pci.h>
35#include <linux/interrupt.h>
36#include <linux/sched.h>
37#include <linux/list.h>
38#include <asm/byteorder.h>
39#include <linux/scatterlist.h>
40#include <asm/page.h>
41#include <net/mac80211.h>
c83be688 42#include <linux/leds.h>
500c064d 43#include <linux/rfkill.h>
f078f209
LR		 44
45#include "ath9k.h"
46#include "rc.h"
47
48struct ath_node;
49
50/******************/
51/* Utility macros */
52/******************/
53
54/* Macro to expand scalars to 64-bit objects */
55
f22f558d
S		 56#define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
58 (sizeof(x) == 16) ? \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
f078f209 61 (((unsigned long long int)(x)) & 0xffffffff) : \
f22f558d 62 (unsigned long long int)(x))
f078f209
LR		 63
64/* increment with wrap-around */
f22f558d
S		 65#define INCR(_l, _sz) do { \
66 (_l)++; \
67 (_l) &= ((_sz) - 1); \
f078f209
LR		 68 } while (0)
69
70/* decrement with wrap-around */
f22f558d
S		 71#define DECR(_l, _sz) do { \
72 (_l)--; \
73 (_l) &= ((_sz) - 1); \
f078f209
LR		 74 } while (0)
75
76#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
77
78#define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
80 BUG(); \
81 } \
82 } while (0)
83
19b73c7f
S		 84#define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
86
f078f209
LR		 87#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
88
89static inline unsigned long get_timestamp(void)
90{
91 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
92}
93
7dcfdcd9
S		 94static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
95
f078f209
LR		 96/*************/
97/* Debugging */
98/*************/
99
100enum ATH_DEBUG {
101 ATH_DBG_RESET = 0x00000001,
102 ATH_DBG_PHY_IO = 0x00000002,
103 ATH_DBG_REG_IO = 0x00000004,
104 ATH_DBG_QUEUE = 0x00000008,
105 ATH_DBG_EEPROM = 0x00000010,
106 ATH_DBG_NF_CAL = 0x00000020,
107 ATH_DBG_CALIBRATE = 0x00000040,
108 ATH_DBG_CHANNEL = 0x00000080,
109 ATH_DBG_INTERRUPT = 0x00000100,
110 ATH_DBG_REGULATORY = 0x00000200,
111 ATH_DBG_ANI = 0x00000400,
112 ATH_DBG_POWER_MGMT = 0x00000800,
113 ATH_DBG_XMIT = 0x00001000,
114 ATH_DBG_BEACON = 0x00002000,
115 ATH_DBG_RATE = 0x00004000,
116 ATH_DBG_CONFIG = 0x00008000,
117 ATH_DBG_KEYCACHE = 0x00010000,
118 ATH_DBG_AGGR = 0x00020000,
119 ATH_DBG_FATAL = 0x00040000,
120 ATH_DBG_ANY = 0xffffffff
121};
122
123#define DBG_DEFAULT (ATH_DBG_FATAL)
124
125#define DPRINTF(sc, _m, _fmt, ...) do { \
126 if (sc->sc_debug & (_m)) \
127 printk(_fmt , ##__VA_ARGS__); \
128 } while (0)
129
130/***************************/
131/* Load-time Configuration */
132/***************************/
133
134/* Per-instance load-time (note: NOT run-time) configurations
135 * for Atheros Device */
136struct ath_config {
f22f558d
S		 137 u32 ath_aggr_prot;
138 u16 txpowlimit;
139 u16 txpowlimit_override;
140 u8 cabqReadytime; /* Cabq Readytime % */
141 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
f078f209
LR		 142};
143
144/***********************/
145/* Chainmask Selection */
146/***********************/
147
148#define ATH_CHAINMASK_SEL_TIMEOUT 6000
149/* Default - Number of last RSSI values that is used for
150 * chainmask selection */
151#define ATH_CHAINMASK_SEL_RSSI_CNT 10
152/* Means use 3x3 chainmask instead of configured chainmask */
153#define ATH_CHAINMASK_SEL_3X3 7
154/* Default - Rssi threshold below which we have to switch to 3x3 */
155#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
156/* Default - Rssi threshold above which we have to switch to
157 * user configured values */
158#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
159/* Struct to store the chainmask select related info */
160struct ath_chainmask_sel {
f22f558d
S		 161 struct timer_list timer;
162 int cur_tx_mask; /* user configured or 3x3 */
163 int cur_rx_mask; /* user configured or 3x3 */
164 int tx_avgrssi;
165 u8 switch_allowed:1, /* timer will set this */
166 cm_sel_enabled : 1;
f078f209
LR		 167};
168
169int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
170void ath_update_chainmask(struct ath_softc *sc, int is_ht);
171
172/*************************/
173/* Descriptor Management */
174/*************************/
175
f078f209
LR		 176#define ATH_TXBUF_RESET(_bf) do { \
177 (_bf)->bf_status = 0; \
178 (_bf)->bf_lastbf = NULL; \
179 (_bf)->bf_lastfrm = NULL; \
180 (_bf)->bf_next = NULL; \
0345f37b 181 memset(&((_bf)->bf_state), 0, \
f078f209
LR		 182 sizeof(struct ath_buf_state)); \
183 } while (0)
184
cd3d39a6
S		 185enum buffer_type {
186 BUF_DATA = BIT(0),
187 BUF_AGGR = BIT(1),
188 BUF_AMPDU = BIT(2),
189 BUF_HT = BIT(3),
190 BUF_RETRY = BIT(4),
191 BUF_XRETRY = BIT(5),
192 BUF_SHORT_PREAMBLE = BIT(6),
193 BUF_BAR = BIT(7),
194 BUF_PSPOLL = BIT(8),
195 BUF_AGGR_BURST = BIT(9),
196 BUF_CALC_AIRTIME = BIT(10),
197};
198
f078f209 199struct ath_buf_state {
cd3d39a6
S		 200 int bfs_nframes; /* # frames in aggregate */
201 u16 bfs_al; /* length of aggregate */
202 u16 bfs_frmlen; /* length of frame */
203 int bfs_seqno; /* sequence number */
204 int bfs_tidno; /* tid of this frame */
205 int bfs_retries; /* current retries */
f078f209 206 struct ath_rc_series bfs_rcs[4]; /* rate series */
cd3d39a6 207 u32 bf_type; /* BUF_* (enum buffer_type) */
f078f209 208 /* key type use to encrypt this frame */
528f0c6b 209 u32 bfs_keyix;
f078f209
LR		 210 enum ath9k_key_type bfs_keytype;
211};
212
213#define bf_nframes bf_state.bfs_nframes
214#define bf_al bf_state.bfs_al
215#define bf_frmlen bf_state.bfs_frmlen
216#define bf_retries bf_state.bfs_retries
217#define bf_seqno bf_state.bfs_seqno
218#define bf_tidno bf_state.bfs_tidno
219#define bf_rcs bf_state.bfs_rcs
528f0c6b 220#define bf_keyix bf_state.bfs_keyix
f078f209 221#define bf_keytype bf_state.bfs_keytype
cd3d39a6
S		 222#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
223#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
224#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
225#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
226#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
227#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
228#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
229#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
230#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
231#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
f078f209
LR		 232
233/*
234 * Abstraction of a contiguous buffer to transmit/receive. There is only
235 * a single hw descriptor encapsulated here.
236 */
f078f209
LR		 237struct ath_buf {
238 struct list_head list;
239 struct list_head *last;
240 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
f22f558d 241 an aggregate) */
f078f209
LR		 242 struct ath_buf *bf_lastfrm; /* last buf of this frame */
243 struct ath_buf *bf_next; /* next subframe in the aggregate */
244 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
245 void *bf_mpdu; /* enclosing frame structure */
f078f209
LR		 246 struct ath_desc *bf_desc; /* virtual addr of desc */
247 dma_addr_t bf_daddr; /* physical addr of desc */
248 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
249 u32 bf_status;
f22f558d 250 u16 bf_flags; /* tx descriptor flags */
f078f209
LR		 251 struct ath_buf_state bf_state; /* buffer state */
252 dma_addr_t bf_dmacontext;
253};
254
255/*
256 * reset the rx buffer.
257 * any new fields added to the athbuf and require
258 * reset need to be added to this macro.
259 * currently bf_status is the only one requires that
260 * requires reset.
261 */
262#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
263
264/* hw processing complete, desc processed by hal */
265#define ATH_BUFSTATUS_DONE 0x00000001
266/* hw processing complete, desc hold for hw */
267#define ATH_BUFSTATUS_STALE 0x00000002
268/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
269#define ATH_BUFSTATUS_FREE 0x00000004
270
271/* DMA state for tx/rx descriptors */
272
273struct ath_descdma {
274 const char *dd_name;
275 struct ath_desc *dd_desc; /* descriptors */
276 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
277 u32 dd_desc_len; /* size of dd_desc */
278 struct ath_buf *dd_bufptr; /* associated buffers */
279 dma_addr_t dd_dmacontext;
280};
281
282/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
283
284struct ath_rx_context {
285 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
286};
287#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
288
289int ath_descdma_setup(struct ath_softc *sc,
290 struct ath_descdma *dd,
291 struct list_head *head,
292 const char *name,
293 int nbuf,
294 int ndesc);
295int ath_desc_alloc(struct ath_softc *sc);
296void ath_desc_free(struct ath_softc *sc);
297void ath_descdma_cleanup(struct ath_softc *sc,
298 struct ath_descdma *dd,
299 struct list_head *head);
300
301/******/
302/* RX */
303/******/
304
305#define ATH_MAX_ANTENNA 3
306#define ATH_RXBUF 512
307#define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
308#define WME_NUM_TID 16
309#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
a477e4e6 310#define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */
f078f209
LR		 311
312enum ATH_RX_TYPE {
313 ATH_RX_NON_CONSUMED = 0,
314 ATH_RX_CONSUMED
315};
316
317/* per frame rx status block */
318struct ath_recv_status {
319 u64 tsf; /* mac tsf */
320 int8_t rssi; /* RSSI (noise floor ajusted) */
321 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
322 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
323 int8_t abs_rssi; /* absolute RSSI */
f22f558d
S		 324 u8 rateieee; /* data rate received (IEEE rate code) */
325 u8 ratecode; /* phy rate code */
f078f209
LR		 326 int rateKbps; /* data rate received (Kbps) */
327 int antenna; /* rx antenna */
328 int flags; /* status of associated skb */
329#define ATH_RX_FCS_ERROR 0x01
330#define ATH_RX_MIC_ERROR 0x02
331#define ATH_RX_DECRYPT_ERROR 0x04
332#define ATH_RX_RSSI_VALID 0x08
333/* if any of ctl,extn chainrssis are valid */
334#define ATH_RX_CHAIN_RSSI_VALID 0x10
335/* if extn chain rssis are valid */
336#define ATH_RX_RSSI_EXTN_VALID 0x20
337/* set if 40Mhz, clear if 20Mhz */
338#define ATH_RX_40MHZ 0x40
339/* set if short GI, clear if full GI */
340#define ATH_RX_SHORT_GI 0x80
341};
342
343struct ath_rxbuf {
f22f558d
S		 344 struct sk_buff *rx_wbuf;
345 unsigned long rx_time; /* system time when received */
346 struct ath_recv_status rx_status; /* cached rx status */
f078f209
LR		 347};
348
349/* Per-TID aggregate receiver state for a node */
350struct ath_arx_tid {
f22f558d
S		 351 struct ath_node *an;
352 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
353 struct timer_list timer;
354 spinlock_t tidlock;
355 int baw_head; /* seq_next at head */
356 int baw_tail; /* tail of block-ack window */
357 int seq_reset; /* need to reset start sequence */
358 int addba_exchangecomplete;
359 u16 seq_next; /* next expected sequence */
360 u16 baw_size; /* block-ack window size */
f078f209
LR		 361};
362
363/* Per-node receiver aggregate state */
364struct ath_arx {
f22f558d 365 struct ath_arx_tid tid[WME_NUM_TID];
f078f209
LR		 366};
367
368int ath_startrecv(struct ath_softc *sc);
369bool ath_stoprecv(struct ath_softc *sc);
370void ath_flushrecv(struct ath_softc *sc);
371u32 ath_calcrxfilter(struct ath_softc *sc);
372void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
c5170163 373void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 374void ath_handle_rx_intr(struct ath_softc *sc);
375int ath_rx_init(struct ath_softc *sc, int nbufs);
376void ath_rx_cleanup(struct ath_softc *sc);
377int ath_rx_tasklet(struct ath_softc *sc, int flush);
378int ath_rx_input(struct ath_softc *sc,
379 struct ath_node *node,
f078f209
LR		 380 struct sk_buff *skb,
381 struct ath_recv_status *rx_status,
382 enum ATH_RX_TYPE *status);
19b73c7f
S		 383int _ath_rx_indicate(struct ath_softc *sc,
384 struct sk_buff *skb,
385 struct ath_recv_status *status,
386 u16 keyix);
f078f209
LR		 387int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
388 struct ath_recv_status *status);
389
390/******/
391/* TX */
392/******/
393
556bb8f1 394#define ATH_TXBUF 512
f078f209
LR		 395/* max number of transmit attempts (tries) */
396#define ATH_TXMAXTRY 13
397/* max number of 11n transmit attempts (tries) */
398#define ATH_11N_TXMAXTRY 10
399/* max number of tries for management and control frames */
400#define ATH_MGT_TXMAXTRY 4
401#define WME_BA_BMP_SIZE 64
402#define WME_MAX_BA WME_BA_BMP_SIZE
403#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
404#define TID_TO_WME_AC(_tid) \
405 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
406 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
407 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
408 WME_AC_VO)
409
410
411/* Wireless Multimedia Extension Defines */
412#define WME_AC_BE 0 /* best effort */
413#define WME_AC_BK 1 /* background */
414#define WME_AC_VI 2 /* video */
415#define WME_AC_VO 3 /* voice */
416#define WME_NUM_AC 4
417
f078f209
LR		 418/*
419 * Data transmit queue state. One of these exists for each
420 * hardware transmit queue. Packets sent to us from above
421 * are assigned to queues based on their priority. Not all
422 * devices support a complete set of hardware transmit queues.
423 * For those devices the array sc_ac2q will map multiple
424 * priorities to fewer hardware queues (typically all to one
425 * hardware queue).
426 */
427struct ath_txq {
f22f558d
S		 428 u32 axq_qnum; /* hardware q number */
429 u32 *axq_link; /* link ptr in last TX desc */
430 struct list_head axq_q; /* transmit queue */
431 spinlock_t axq_lock;
432 unsigned long axq_lockflags; /* intr state when must cli */
433 u32 axq_depth; /* queue depth */
434 u8 axq_aggr_depth; /* aggregates queued */
435 u32 axq_totalqueued; /* total ever queued */
436
f22f558d
S		 437 bool stopped; /* Is mac80211 queue stopped ? */
438 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
439
440 /* first desc of the last descriptor that contains CTS */
441 struct ath_desc *axq_lastdsWithCTS;
442
443 /* final desc of the gating desc that determines whether
444 lastdsWithCTS has been DMA'ed or not */
445 struct ath_desc *axq_gatingds;
446
447 struct list_head axq_acq;
f078f209
LR		 448};
449
a37c2c79
S		 450#define AGGR_CLEANUP BIT(1)
451#define AGGR_ADDBA_COMPLETE BIT(2)
452#define AGGR_ADDBA_PROGRESS BIT(3)
453
f078f209
LR		 454/* per TID aggregate tx state for a destination */
455struct ath_atx_tid {
f22f558d
S		 456 struct list_head list; /* round-robin tid entry */
457 struct list_head buf_q; /* pending buffers */
458 struct ath_node *an;
459 struct ath_atx_ac *ac;
460 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
461 u16 seq_start;
462 u16 seq_next;
463 u16 baw_size;
464 int tidno;
465 int baw_head; /* first un-acked tx buffer */
466 int baw_tail; /* next unused tx buffer slot */
467 int sched;
468 int paused;
a37c2c79 469 u8 state;
f22f558d 470 int addba_exchangeattempts;
f078f209
LR		 471};
472
473/* per access-category aggregate tx state for a destination */
474struct ath_atx_ac {
f22f558d
S		 475 int sched; /* dest-ac is scheduled */
476 int qnum; /* H/W queue number associated
477 with this AC */
478 struct list_head list; /* round-robin txq entry */
479 struct list_head tid_q; /* queue of TIDs with buffers */
f078f209
LR		 480};
481
482/* per dest tx state */
483struct ath_atx {
f22f558d
S		 484 struct ath_atx_tid tid[WME_NUM_TID];
485 struct ath_atx_ac ac[WME_NUM_AC];
f078f209
LR		 486};
487
488/* per-frame tx control block */
489struct ath_tx_control {
528f0c6b 490 struct ath_txq *txq;
f22f558d 491 int if_id;
f078f209
LR		 492};
493
494/* per frame tx status block */
495struct ath_xmit_status {
f22f558d
S		 496 int retries; /* number of retries to successufully
497 transmit this frame */
498 int flags; /* status of transmit */
f078f209
LR		 499#define ATH_TX_ERROR 0x01
500#define ATH_TX_XRETRY 0x02
501#define ATH_TX_BAR 0x04
502};
503
504struct ath_tx_stat {
505 int rssi; /* RSSI (noise floor ajusted) */
506 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
507 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
508 int rateieee; /* data rate xmitted (IEEE rate code) */
509 int rateKbps; /* data rate xmitted (Kbps) */
510 int ratecode; /* phy rate code */
511 int flags; /* validity flags */
512/* if any of ctl,extn chain rssis are valid */
513#define ATH_TX_CHAIN_RSSI_VALID 0x01
514/* if extn chain rssis are valid */
515#define ATH_TX_RSSI_EXTN_VALID 0x02
516 u32 airtime; /* time on air per final tx rate */
517};
518
519struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
520void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
521int ath_tx_setup(struct ath_softc *sc, int haltype);
522void ath_draintxq(struct ath_softc *sc, bool retry_tx);
523void ath_tx_draintxq(struct ath_softc *sc,
556bb8f1 524 struct ath_txq *txq, bool retry_tx);
f078f209 525void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
b5aa9bf9 526void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 527void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
528void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
529int ath_tx_init(struct ath_softc *sc, int nbufs);
530int ath_tx_cleanup(struct ath_softc *sc);
531int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
528f0c6b 532struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
ea9880fb
S		 533int ath_txq_update(struct ath_softc *sc, int qnum,
534 struct ath9k_tx_queue_info *q);
528f0c6b
S		 535int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
536 struct ath_tx_control *txctl);
f078f209
LR		 537void ath_tx_tasklet(struct ath_softc *sc);
538u32 ath_txq_depth(struct ath_softc *sc, int qnum);
539u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
540void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
541void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
528f0c6b 542 struct ath_xmit_status *tx_status);
e022edbd 543void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
f078f209
LR		 544
545/**********************/
546/* Node / Aggregation */
547/**********************/
548
f078f209
LR		 549#define ADDBA_EXCHANGE_ATTEMPTS 10
550#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
551#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
552/* number of delimiters for encryption padding */
553#define ATH_AGGR_ENCRYPTDELIM 10
554/* minimum h/w qdepth to be sustained to maximize aggregation */
555#define ATH_AGGR_MIN_QDEPTH 2
556#define ATH_AMPDU_SUBFRAME_DEFAULT 32
557#define IEEE80211_SEQ_SEQ_SHIFT 4
558#define IEEE80211_SEQ_MAX 4096
559#define IEEE80211_MIN_AMPDU_BUF 0x8
b5aa9bf9 560#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
f078f209
LR		 561
562/* return whether a bit at index _n in bitmap _bm is set
563 * _sz is the size of the bitmap */
564#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
565 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
566
567/* return block-ack bitmap index given sequence and starting sequence */
568#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
569
570/* returns delimiter padding required given the packet length */
571#define ATH_AGGR_GET_NDELIM(_len) \
572 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
573 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
574
575#define BAW_WITHIN(_start, _bawsz, _seqno) \
576 ((((_seqno) - (_start)) & 4095) < (_bawsz))
577
578#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
579#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
580#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
581#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
582
583enum ATH_AGGR_STATUS {
584 ATH_AGGR_DONE,
585 ATH_AGGR_BAW_CLOSED,
586 ATH_AGGR_LIMITED,
587 ATH_AGGR_SHORTPKT,
588 ATH_AGGR_8K_LIMITED,
589};
590
591enum ATH_AGGR_CHECK {
592 AGGR_NOT_REQUIRED,
593 AGGR_REQUIRED,
594 AGGR_CLEANUP_PROGRESS,
595 AGGR_EXCHANGE_PROGRESS,
596 AGGR_EXCHANGE_DONE
597};
598
599struct aggr_rifs_param {
600 int param_max_frames;
601 int param_max_len;
602 int param_rl;
603 int param_al;
604 struct ath_rc_series *param_rcs;
605};
606
607/* Per-node aggregation state */
608struct ath_node_aggr {
f22f558d
S		 609 struct ath_atx tx; /* node transmit state */
610 struct ath_arx rx; /* node receive state */
f078f209
LR		 611};
612
613/* driver-specific node state */
614struct ath_node {
f22f558d 615 struct ath_softc *an_sc;
f078f209 616 struct ath_chainmask_sel an_chainmask_sel;
f22f558d 617 struct ath_node_aggr an_aggr;
ae5eb026
JB		 618 u16 maxampdu;
619 u8 mpdudensity;
f078f209
LR		 620};
621
622void ath_tx_resume_tid(struct ath_softc *sc,
623 struct ath_atx_tid *tid);
624enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
625 struct ath_node *an, u8 tidno);
626void ath_tx_aggr_teardown(struct ath_softc *sc,
627 struct ath_node *an, u8 tidno);
628void ath_rx_aggr_teardown(struct ath_softc *sc,
629 struct ath_node *an, u8 tidno);
b5aa9bf9
S		 630int ath_rx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
631 u16 tid, u16 *ssn);
632int ath_rx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
633int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
634 u16 tid, u16 *ssn);
635int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
f078f209
LR		 636void ath_newassoc(struct ath_softc *sc,
637 struct ath_node *node, int isnew, int isuapsd);
b5aa9bf9
S		 638void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
639 int if_id);
640void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
f078f209
LR		 641
642/*******************/
643/* Beacon Handling */
644/*******************/
645
646/*
647 * Regardless of the number of beacons we stagger, (i.e. regardless of the
648 * number of BSSIDs) if a given beacon does not go out even after waiting this
649 * number of beacon intervals, the game's up.
650 */
651#define BSTUCK_THRESH (9 * ATH_BCBUF)
652#define ATH_BCBUF 4 /* number of beacon buffers */
653#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
654#define ATH_DEFAULT_BMISS_LIMIT 10
f078f209
LR		 655#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
656
657/* beacon configuration */
658struct ath_beacon_config {
659 u16 beacon_interval;
660 u16 listen_interval;
661 u16 dtim_period;
662 u16 bmiss_timeout;
663 u8 dtim_count;
664 u8 tim_offset;
665 union {
666 u64 last_tsf;
667 u8 last_tstamp[8];
668 } u; /* last received beacon/probe response timestamp of this BSS. */
669};
670
f078f209
LR		 671void ath9k_beacon_tasklet(unsigned long data);
672void ath_beacon_config(struct ath_softc *sc, int if_id);
673int ath_beaconq_setup(struct ath_hal *ah);
674int ath_beacon_alloc(struct ath_softc *sc, int if_id);
675void ath_bstuck_process(struct ath_softc *sc);
f078f209
LR		 676void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
677void ath_beacon_sync(struct ath_softc *sc, int if_id);
f078f209
LR		 678void ath_get_beaconconfig(struct ath_softc *sc,
679 int if_id,
680 struct ath_beacon_config *conf);
f078f209
LR		 681/********/
682/* VAPs */
683/********/
684
f078f209
LR		 685/*
686 * Define the scheme that we select MAC address for multiple
687 * BSS on the same radio. The very first VAP will just use the MAC
688 * address from the EEPROM. For the next 3 VAPs, we set the
689 * U/L bit (bit 1) in MAC address, and use the next two bits as the
690 * index of the VAP.
691 */
692
693#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
694 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
695
696/* VAP configuration (from protocol layer) */
697struct ath_vap_config {
698 u32 av_fixed_rateset;
699 u32 av_fixed_retryset;
700};
701
702/* driver-specific vap state */
703struct ath_vap {
f22f558d
S		 704 struct ieee80211_vif *av_if_data;
705 enum ath9k_opmode av_opmode; /* VAP operational mode */
706 struct ath_buf *av_bcbuf; /* beacon buffer */
f22f558d
S		 707 struct ath_tx_control av_btxctl; /* txctl information for beacon */
708 int av_bslot; /* beacon slot index */
f22f558d
S		 709 struct ath_vap_config av_config;/* vap configuration parameters*/
710 struct ath_rate_node *rc_node;
f078f209
LR		 711};
712
713int ath_vap_attach(struct ath_softc *sc,
714 int if_id,
715 struct ieee80211_vif *if_data,
716 enum ath9k_opmode opmode);
717int ath_vap_detach(struct ath_softc *sc, int if_id);
718int ath_vap_config(struct ath_softc *sc,
ff9b662d 719 int if_id, struct ath_vap_config *if_config);
f078f209
LR		 720
721/*********************/
722/* Antenna diversity */
723/*********************/
724
725#define ATH_ANT_DIV_MAX_CFG 2
726#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
727#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
728
729enum ATH_ANT_DIV_STATE{
730 ATH_ANT_DIV_IDLE,
731 ATH_ANT_DIV_SCAN, /* evaluating antenna */
732};
733
734struct ath_antdiv {
735 struct ath_softc *antdiv_sc;
736 u8 antdiv_start;
737 enum ATH_ANT_DIV_STATE antdiv_state;
738 u8 antdiv_num_antcfg;
739 u8 antdiv_curcfg;
740 u8 antdiv_bestcfg;
741 int32_t antdivf_rssitrig;
742 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
743 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
744 u64 antdiv_laststatetsf;
745 u8 antdiv_bssid[ETH_ALEN];
746};
747
748void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
749 struct ath_softc *sc, int32_t rssitrig);
750void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
751 u8 num_antcfg,
752 const u8 *bssid);
753void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
754void ath_slow_ant_div(struct ath_antdiv *antdiv,
755 struct ieee80211_hdr *wh,
756 struct ath_rx_status *rx_stats);
757void ath_setdefantenna(void *sc, u32 antenna);
758
6f255425
LR		 759/*******/
760/* ANI */
761/*******/
762
763/* ANI values for STA only.
764 FIXME: Add appropriate values for AP later */
765
766#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
767#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
768#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
769#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
770
771struct ath_ani {
772 bool sc_caldone;
773 int16_t sc_noise_floor;
774 unsigned int sc_longcal_timer;
775 unsigned int sc_shortcal_timer;
776 unsigned int sc_resetcal_timer;
777 unsigned int sc_checkani_timer;
778 struct timer_list timer;
779};
780
c83be688
VT		 781/********************/
782/* LED Control */
783/********************/
784
785#define ATH_LED_PIN 1
786
787enum ath_led_type {
788 ATH_LED_RADIO,
789 ATH_LED_ASSOC,
790 ATH_LED_TX,
791 ATH_LED_RX
792};
793
794struct ath_led {
795 struct ath_softc *sc;
796 struct led_classdev led_cdev;
797 enum ath_led_type led_type;
798 char name[32];
799 bool registered;
800};
801
500c064d
VT		 802/* Rfkill */
803#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
804
805struct ath_rfkill {
806 struct rfkill *rfkill;
807 struct delayed_work rfkill_poll;
808 char rfkill_name[32];
809};
810
f078f209
LR		 811/********************/
812/* Main driver core */
813/********************/
814
815/*
816 * Default cache line size, in bytes.
817 * Used when PCI device not fully initialized by bootrom/BIOS
818*/
819#define DEFAULT_CACHELINE 32
820#define ATH_DEFAULT_NOISE_FLOOR -95
821#define ATH_REGCLASSIDS_MAX 10
822#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
f078f209 823#define ATH_MAX_SW_RETRIES 10
f078f209
LR		 824#define ATH_CHAN_MAX 255
825#define IEEE80211_WEP_NKID 4 /* number of key ids */
826#define IEEE80211_RATE_VAL 0x7f
827/*
828 * The key cache is used for h/w cipher state and also for
829 * tracking station state such as the current tx antenna.
830 * We also setup a mapping table between key cache slot indices
831 * and station state to short-circuit node lookups on rx.
832 * Different parts have different size key caches. We handle
833 * up to ATH_KEYMAX entries (could dynamically allocate state).
834 */
835#define ATH_KEYMAX 128 /* max key cache size we handle */
836
f078f209 837#define ATH_IF_ID_ANY 0xff
f078f209
LR		 838#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
839
840#define RSSI_LPF_THRESHOLD -20
841#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
842#define ATH_RATE_DUMMY_MARKER 0
843#define ATH_RSSI_LPF_LEN 10
844#define ATH_RSSI_DUMMY_MARKER 0x127
845
846#define ATH_EP_MUL(x, mul) ((x) * (mul))
847#define ATH_EP_RND(x, mul) \
848 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
849#define ATH_RSSI_OUT(x) \
850 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
851 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
852#define ATH_RSSI_IN(x) \
853 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
854#define ATH_LPF_RSSI(x, y, len) \
855 ((x != ATH_RSSI_DUMMY_MARKER) ? \
856 (((x) * ((len) - 1) + (y)) / (len)) : (y))
857#define ATH_RSSI_LPF(x, y) do { \
858 if ((y) >= RSSI_LPF_THRESHOLD) \
859 x = ATH_LPF_RSSI((x), \
860 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
861 } while (0)
862
863
864enum PROT_MODE {
865 PROT_M_NONE = 0,
866 PROT_M_RTSCTS,
867 PROT_M_CTSONLY
868};
869
870enum RATE_TYPE {
871 NORMAL_RATE = 0,
872 HALF_RATE,
873 QUARTER_RATE
874};
875
876struct ath_ht_info {
877 enum ath9k_ht_macmode tx_chan_width;
f078f209
LR		 878 u8 ext_chan_offset;
879};
880
672840ac
S		 881#define SC_OP_INVALID BIT(0)
882#define SC_OP_BEACONS BIT(1)
883#define SC_OP_RXAGGR BIT(2)
884#define SC_OP_TXAGGR BIT(3)
885#define SC_OP_CHAINMASK_UPDATE BIT(4)
886#define SC_OP_FULL_RESET BIT(5)
98deeea0
S		 887#define SC_OP_NO_RESET BIT(6)
888#define SC_OP_PREAMBLE_SHORT BIT(7)
889#define SC_OP_PROTECT_ENABLE BIT(8)
890#define SC_OP_RXFLUSH BIT(9)
c83be688 891#define SC_OP_LED_ASSOCIATED BIT(10)
500c064d
VT		 892#define SC_OP_RFKILL_REGISTERED BIT(11)
893#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
894#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
672840ac 895
f078f209 896struct ath_softc {
ea9880fb
S		 897 struct ieee80211_hw *hw;
898 struct pci_dev *pdev;
ea9880fb
S		 899 struct tasklet_struct intr_tq;
900 struct tasklet_struct bcon_tasklet;
672840ac 901 struct ath_config sc_config;
ea9880fb 902 struct ath_hal *sc_ah;
672840ac 903 struct ath_rate_softc *sc_rc;
b4696c8b
S		 904 void __iomem *mem;
905
98deeea0
S		 906 u8 sc_curbssid[ETH_ALEN];
907 u8 sc_myaddr[ETH_ALEN];
908 u8 sc_bssidmask[ETH_ALEN];
909
b4696c8b 910 int sc_debug;
ea9880fb 911 u32 sc_intrstatus;
672840ac 912 u32 sc_flags; /* SC_OP_* */
7dcfdcd9 913 unsigned int rx_filter;
ea9880fb
S		 914 u16 sc_curtxpow;
915 u16 sc_curaid;
98deeea0
S		 916 u16 sc_cachelsz;
917 int sc_slotupdate; /* slot to next advance fsm */
918 int sc_slottime;
919 int sc_bslot[ATH_BCBUF];
920 u8 sc_tx_chainmask;
921 u8 sc_rx_chainmask;
922 enum ath9k_int sc_imask;
923 enum wireless_mode sc_curmode; /* current phy mode */
ea9880fb 924 enum PROT_MODE sc_protmode;
98deeea0 925
ea9880fb
S		 926 u8 sc_nbcnvaps; /* # of vaps sending beacons */
927 u16 sc_nvaps; /* # of active virtual ap's */
928 struct ath_vap *sc_vaps[ATH_BCBUF];
98deeea0
S		 929
930 u8 sc_mcastantenna;
ea9880fb
S		 931 u8 sc_defant; /* current default antenna */
932 u8 sc_rxotherant; /* rx's on non-default antenna */
98deeea0 933
ea9880fb 934 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
ea9880fb 935 struct ath_ht_info sc_ht_info;
ea9880fb 936 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
98deeea0 937
f078f209 938#ifdef CONFIG_SLOW_ANT_DIV
ea9880fb 939 struct ath_antdiv sc_antdiv;
f078f209
LR		 940#endif
941 enum {
ea9880fb
S		 942 OK, /* no change needed */
943 UPDATE, /* update pending */
944 COMMIT /* beacon sent, commit change */
945 } sc_updateslot; /* slot time update fsm */
f078f209
LR		 946
947 /* Crypto */
ea9880fb
S		 948 u32 sc_keymax; /* size of key cache */
949 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
950 u8 sc_splitmic; /* split TKIP MIC keys */
f078f209
LR		 951
952 /* RX */
ea9880fb
S		 953 struct list_head sc_rxbuf;
954 struct ath_descdma sc_rxdma;
955 int sc_rxbufsize; /* rx size based on mtu */
956 u32 *sc_rxlink; /* link ptr in last RX desc */
f078f209
LR		 957
958 /* TX */
ea9880fb
S		 959 struct list_head sc_txbuf;
960 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
961 struct ath_descdma sc_txdma;
962 u32 sc_txqsetup;
ea9880fb 963 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
147583c0 964 u16 seq_no; /* TX sequence number */
f078f209
LR		 965
966 /* Beacon */
ea9880fb
S		 967 struct ath9k_tx_queue_info sc_beacon_qi;
968 struct ath_descdma sc_bdma;
969 struct ath_txq *sc_cabq;
970 struct list_head sc_bbuf;
971 u32 sc_bhalq;
972 u32 sc_bmisscount;
973 u32 ast_be_xmit; /* beacons transmitted */
459f5f90 974 u64 bc_tstamp;
f078f209
LR		 975
976 /* Rate */
ea9880fb 977 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
ea9880fb
S		 978 const struct ath9k_rate_table *sc_currates;
979 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
ea9880fb 980 u8 sc_protrix; /* protection rate index */
f078f209 981 struct {
ea9880fb
S		 982 u32 rateKbps; /* transfer rate in kbs */
983 u8 ieeerate; /* IEEE rate */
984 } sc_hwmap[256]; /* h/w rate ix mappings */
f078f209
LR		 985
986 /* Channel, Band */
987 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
988 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
f078f209
LR		 989
990 /* Locks */
ea9880fb
S		 991 spinlock_t sc_rxflushlock;
992 spinlock_t sc_rxbuflock;
993 spinlock_t sc_txbuflock;
994 spinlock_t sc_resetlock;
c83be688
VT		 995
996 /* LEDs */
997 struct ath_led radio_led;
998 struct ath_led assoc_led;
999 struct ath_led tx_led;
1000 struct ath_led rx_led;
500c064d
VT		 1001
1002 /* Rfkill */
1003 struct ath_rfkill rf_kill;
6f255425
LR		 1004
1005 /* ANI */
1006 struct ath_ani sc_ani;
f078f209
LR		 1007};
1008
1009int ath_init(u16 devid, struct ath_softc *sc);
1010void ath_deinit(struct ath_softc *sc);
1011int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1012int ath_suspend(struct ath_softc *sc);
1013irqreturn_t ath_isr(int irq, void *dev);
f45144ef 1014int ath_reset(struct ath_softc *sc, bool retry_tx);
f078f209 1015int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
f078f209
LR		 1016
1017/*********************/
1018/* Utility Functions */
1019/*********************/
1020
1021void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1022int ath_keyset(struct ath_softc *sc,
1023 u16 keyix,
1024 struct ath9k_keyval *hk,
1025 const u8 mac[ETH_ALEN]);
1026int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1027int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1028void ath_setslottime(struct ath_softc *sc);
1029void ath_update_txpow(struct ath_softc *sc);
1030int ath_cabq_update(struct ath_softc *);
1031void ath_get_currentCountry(struct ath_softc *sc,
1032 struct ath9k_country_entry *ctry);
1033u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
f078f209
LR		 1034
1035#endif /* CORE_H */
Linux kernel - Deliverables
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