Commit | Line | Data |
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394cf0a1 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
394cf0a1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef DEBUG_H | |
18 | #define DEBUG_H | |
19 | ||
20 | enum ATH_DEBUG { | |
21 | ATH_DBG_RESET = 0x00000001, | |
22 | ATH_DBG_REG_IO = 0x00000002, | |
23 | ATH_DBG_QUEUE = 0x00000004, | |
24 | ATH_DBG_EEPROM = 0x00000008, | |
25 | ATH_DBG_CALIBRATE = 0x00000010, | |
26 | ATH_DBG_CHANNEL = 0x00000020, | |
27 | ATH_DBG_INTERRUPT = 0x00000040, | |
28 | ATH_DBG_REGULATORY = 0x00000080, | |
29 | ATH_DBG_ANI = 0x00000100, | |
30 | ATH_DBG_POWER_MGMT = 0x00000200, | |
31 | ATH_DBG_XMIT = 0x00000400, | |
32 | ATH_DBG_BEACON = 0x00001000, | |
33 | ATH_DBG_CONFIG = 0x00002000, | |
34 | ATH_DBG_KEYCACHE = 0x00004000, | |
35 | ATH_DBG_FATAL = 0x00008000, | |
36 | ATH_DBG_ANY = 0xffffffff | |
37 | }; | |
38 | ||
39 | #define DBG_DEFAULT (ATH_DBG_FATAL) | |
40 | ||
41 | #ifdef CONFIG_ATH9K_DEBUG | |
42 | ||
43 | /** | |
44 | * struct ath_interrupt_stats - Contains statistics about interrupts | |
45 | * @total: Total no. of interrupts generated so far | |
46 | * @rxok: RX with no errors | |
47 | * @rxeol: RX with no more RXDESC available | |
48 | * @rxorn: RX FIFO overrun | |
49 | * @txok: TX completed at the requested rate | |
50 | * @txurn: TX FIFO underrun | |
51 | * @mib: MIB regs reaching its threshold | |
52 | * @rxphyerr: RX with phy errors | |
53 | * @rx_keycache_miss: RX with key cache misses | |
54 | * @swba: Software Beacon Alert | |
55 | * @bmiss: Beacon Miss | |
56 | * @bnr: Beacon Not Ready | |
57 | * @cst: Carrier Sense TImeout | |
58 | * @gtt: Global TX Timeout | |
59 | * @tim: RX beacon TIM occurrence | |
60 | * @cabend: RX End of CAB traffic | |
61 | * @dtimsync: DTIM sync lossage | |
62 | * @dtim: RX Beacon with DTIM | |
63 | */ | |
64 | struct ath_interrupt_stats { | |
65 | u32 total; | |
66 | u32 rxok; | |
67 | u32 rxeol; | |
68 | u32 rxorn; | |
69 | u32 txok; | |
70 | u32 txeol; | |
71 | u32 txurn; | |
72 | u32 mib; | |
73 | u32 rxphyerr; | |
74 | u32 rx_keycache_miss; | |
75 | u32 swba; | |
76 | u32 bmiss; | |
77 | u32 bnr; | |
78 | u32 cst; | |
79 | u32 gtt; | |
80 | u32 tim; | |
81 | u32 cabend; | |
82 | u32 dtimsync; | |
83 | u32 dtim; | |
84 | }; | |
85 | ||
86 | struct ath_legacy_rc_stats { | |
87 | u32 success; | |
88 | }; | |
89 | ||
90 | struct ath_11n_rc_stats { | |
91 | u32 success; | |
92 | u32 retries; | |
93 | u32 xretries; | |
9e712790 | 94 | u8 per; |
394cf0a1 S |
95 | }; |
96 | ||
97 | struct ath_stats { | |
98 | struct ath_interrupt_stats istats; | |
9e712790 S |
99 | struct ath_legacy_rc_stats legacy_rcstats[12]; /* max(11a,11b,11g) */ |
100 | struct ath_11n_rc_stats n_rcstats[16]; /* 0..15 MCS rates */ | |
394cf0a1 S |
101 | }; |
102 | ||
103 | struct ath9k_debug { | |
104 | int debug_mask; | |
394cf0a1 S |
105 | struct dentry *debugfs_phy; |
106 | struct dentry *debugfs_dma; | |
107 | struct dentry *debugfs_interrupt; | |
108 | struct dentry *debugfs_rcstat; | |
39d89cd3 | 109 | struct dentry *debugfs_wiphy; |
394cf0a1 S |
110 | struct ath_stats stats; |
111 | }; | |
112 | ||
113 | void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); | |
114 | int ath9k_init_debug(struct ath_softc *sc); | |
115 | void ath9k_exit_debug(struct ath_softc *sc); | |
19d8bc22 GJ |
116 | int ath9k_debug_create_root(void); |
117 | void ath9k_debug_remove_root(void); | |
394cf0a1 S |
118 | void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); |
119 | void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb); | |
120 | void ath_debug_stat_retries(struct ath_softc *sc, int rix, | |
9e712790 | 121 | int xretries, int retries, u8 per); |
394cf0a1 S |
122 | |
123 | #else | |
124 | ||
125 | static inline void DPRINTF(struct ath_softc *sc, int dbg_mask, | |
126 | const char *fmt, ...) | |
127 | { | |
128 | } | |
129 | ||
130 | static inline int ath9k_init_debug(struct ath_softc *sc) | |
131 | { | |
132 | return 0; | |
133 | } | |
134 | ||
135 | static inline void ath9k_exit_debug(struct ath_softc *sc) | |
136 | { | |
137 | } | |
138 | ||
19d8bc22 GJ |
139 | static inline int ath9k_debug_create_root(void) |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static inline void ath9k_debug_remove_root(void) | |
145 | { | |
146 | } | |
147 | ||
394cf0a1 S |
148 | static inline void ath_debug_stat_interrupt(struct ath_softc *sc, |
149 | enum ath9k_int status) | |
150 | { | |
151 | } | |
152 | ||
153 | static inline void ath_debug_stat_rc(struct ath_softc *sc, | |
154 | struct sk_buff *skb) | |
155 | { | |
156 | } | |
157 | ||
158 | static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix, | |
9e712790 | 159 | int xretries, int retries, u8 per) |
394cf0a1 S |
160 | { |
161 | } | |
162 | ||
163 | #endif /* CONFIG_ATH9K_DEBUG */ | |
164 | ||
165 | #endif /* DEBUG_H */ |