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ath9k: Remove all the useless ah_ variable prefixes
[deliverable/linux.git] / drivers / net / wireless / ath9k / hw.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
394cf0a1 20#include "ath9k.h"
f078f209
LR		 21#include "initvals.h"
22
138ab2e4
VT		 23static int btcoex_enable;
24module_param(btcoex_enable, bool, 0);
25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
4febf7b8
LR		 27#define ATH9K_CLOCK_RATE_CCK 22
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 30
cbe61d8a
S		 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 33 enum ath9k_ht_macmode macmode);
cbe61d8a 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 35 struct ar5416_eeprom_def *pEepData,
f1dc5600 36 u32 reg, u32 value);
cbe61d8a
S		 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 39
f1dc5600
S		 40/********************/
41/* Helper Functions */
42/********************/
f078f209 43
cbe61d8a 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 45{
4febf7b8 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 47
2660b81a 48 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 52
4febf7b8 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 54}
f078f209 55
cbe61d8a 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 57{
4febf7b8 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 59
4febf7b8 60 if (conf_is_ht40(conf))
f1dc5600
S		 61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64}
f078f209 65
cbe61d8a 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 67{
4febf7b8 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 69
2660b81a 70 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 75}
76
cbe61d8a 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
4febf7b8 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 80
4febf7b8 81 if (conf_is_ht40(conf))
f1dc5600
S		 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85}
f078f209 86
cbe61d8a 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
f078f209
LR		 88{
89 int i;
90
91 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
92 if ((REG_READ(ah, reg) & mask) == val)
93 return true;
94
95 udelay(AH_TIME_QUANTUM);
96 }
04bd4638
S		 97
98 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
99 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
100 reg, REG_READ(ah, reg), mask, val);
f078f209 101
f1dc5600 102 return false;
f078f209
LR		 103}
104
105u32 ath9k_hw_reverse_bits(u32 val, u32 n)
106{
107 u32 retval;
108 int i;
109
110 for (i = 0, retval = 0; i < n; i++) {
111 retval = (retval << 1) | (val & 1);
112 val >>= 1;
113 }
114 return retval;
115}
116
cbe61d8a 117bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 118 u16 flags, u16 *low,
119 u16 *high)
f078f209 120{
2660b81a 121 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 122
f1dc5600
S		 123 if (flags & CHANNEL_5GHZ) {
124 *low = pCap->low_5ghz_chan;
125 *high = pCap->high_5ghz_chan;
126 return true;
f078f209 127 }
f1dc5600
S		 128 if ((flags & CHANNEL_2GHZ)) {
129 *low = pCap->low_2ghz_chan;
130 *high = pCap->high_2ghz_chan;
131 return true;
132 }
133 return false;
f078f209
LR		 134}
135
cbe61d8a 136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
e63835b0 137 struct ath_rate_table *rates,
f1dc5600
S		 138 u32 frameLen, u16 rateix,
139 bool shortPreamble)
f078f209 140{
f1dc5600
S		 141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
142 u32 kbps;
f078f209 143
e63835b0 144 kbps = rates->info[rateix].ratekbps;
f078f209 145
f1dc5600
S		 146 if (kbps == 0)
147 return 0;
f078f209 148
f1dc5600 149 switch (rates->info[rateix].phy) {
46d14a58 150 case WLAN_RC_PHY_CCK:
f1dc5600 151 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 152 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 153 phyTime >>= 1;
154 numBits = frameLen << 3;
155 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
156 break;
46d14a58 157 case WLAN_RC_PHY_OFDM:
2660b81a 158 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 159 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
160 numBits = OFDM_PLCP_BITS + (frameLen << 3);
161 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
162 txTime = OFDM_SIFS_TIME_QUARTER
163 + OFDM_PREAMBLE_TIME_QUARTER
164 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 165 } else if (ah->curchan &&
166 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_HALF +
171 OFDM_PREAMBLE_TIME_HALF
172 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
173 } else {
174 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
175 numBits = OFDM_PLCP_BITS + (frameLen << 3);
176 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
177 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
178 + (numSymbols * OFDM_SYMBOL_TIME);
179 }
180 break;
181 default:
04bd4638
S		 182 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
183 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 184 rates->info[rateix].phy, rateix);
185 txTime = 0;
186 break;
187 }
f078f209 188
f1dc5600
S		 189 return txTime;
190}
f078f209 191
cbe61d8a 192void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 193 struct ath9k_channel *chan,
194 struct chan_centers *centers)
f078f209 195{
f1dc5600 196 int8_t extoff;
f078f209 197
f1dc5600
S		 198 if (!IS_CHAN_HT40(chan)) {
199 centers->ctl_center = centers->ext_center =
200 centers->synth_center = chan->channel;
201 return;
f078f209 202 }
f078f209 203
f1dc5600
S		 204 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
205 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
206 centers->synth_center =
207 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
208 extoff = 1;
209 } else {
210 centers->synth_center =
211 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
212 extoff = -1;
213 }
f078f209 214
f1dc5600
S		 215 centers->ctl_center =
216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 centers->ext_center =
218 centers->synth_center + (extoff *
2660b81a 219 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 220 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 221}
222
f1dc5600
S		 223/******************/
224/* Chip Revisions */
225/******************/
226
cbe61d8a 227static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 228{
f1dc5600 229 u32 val;
f078f209 230
f1dc5600 231 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 232
f1dc5600
S		 233 if (val == 0xFF) {
234 val = REG_READ(ah, AR_SREV);
d535a42a
S		 235 ah->hw_version.macVersion =
236 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 238 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 239 } else {
240 if (!AR_SREV_9100(ah))
d535a42a 241 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 242
d535a42a 243 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 244
d535a42a 245 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 246 ah->is_pciexpress = true;
f1dc5600 247 }
f078f209
LR		 248}
249
cbe61d8a 250static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 251{
f1dc5600
S		 252 u32 val;
253 int i;
f078f209 254
f1dc5600 255 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 256
f1dc5600
S		 257 for (i = 0; i < 8; i++)
258 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
259 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
260 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 261
f1dc5600 262 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 263}
264
f1dc5600
S		 265/************************************/
266/* HW Attach, Detach, Init Routines */
267/************************************/
268
cbe61d8a 269static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 270{
feed029c 271 if (AR_SREV_9100(ah))
f1dc5600 272 return;
f078f209 273
f1dc5600
S		 274 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 283
f1dc5600 284 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 285}
286
cbe61d8a 287static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 288{
f1dc5600
S		 289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
290 u32 regHold[2];
291 u32 patternData[4] = { 0x55555555,
292 0xaaaaaaaa,
293 0x66666666,
294 0x99999999 };
295 int i, j;
f078f209 296
f1dc5600
S		 297 for (i = 0; i < 2; i++) {
298 u32 addr = regAddr[i];
299 u32 wrData, rdData;
f078f209 300
f1dc5600
S		 301 regHold[i] = REG_READ(ah, addr);
302 for (j = 0; j < 0x100; j++) {
303 wrData = (j << 16) | j;
304 REG_WRITE(ah, addr, wrData);
305 rdData = REG_READ(ah, addr);
306 if (rdData != wrData) {
307 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 308 "address test failed "
f1dc5600 309 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 310 addr, wrData, rdData);
f1dc5600
S		 311 return false;
312 }
313 }
314 for (j = 0; j < 4; j++) {
315 wrData = patternData[j];
316 REG_WRITE(ah, addr, wrData);
317 rdData = REG_READ(ah, addr);
318 if (wrData != rdData) {
319 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 320 "address test failed "
f1dc5600 321 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
f078f209 325 }
f1dc5600 326 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 327 }
f1dc5600 328 udelay(100);
cbe61d8a 329
f078f209
LR		 330 return true;
331}
332
f1dc5600 333static const char *ath9k_hw_devname(u16 devid)
f078f209 334{
f1dc5600
S		 335 switch (devid) {
336 case AR5416_DEVID_PCI:
f1dc5600 337 return "Atheros 5416";
392dff83
BP		 338 case AR5416_DEVID_PCIE:
339 return "Atheros 5418";
f1dc5600
S		 340 case AR9160_DEVID_PCI:
341 return "Atheros 9160";
0c1aa495
GJ		 342 case AR5416_AR9100_DEVID:
343 return "Atheros 9100";
f1dc5600
S		 344 case AR9280_DEVID_PCI:
345 case AR9280_DEVID_PCIE:
346 return "Atheros 9280";
e7594072
SB		 347 case AR9285_DEVID_PCIE:
348 return "Atheros 9285";
f078f209
LR		 349 }
350
f1dc5600
S		 351 return NULL;
352}
f078f209 353
cbe61d8a 354static void ath9k_hw_set_defaults(struct ath_hw *ah)
f1dc5600
S		 355{
356 int i;
f078f209 357
2660b81a
S		 358 ah->config.dma_beacon_response_time = 2;
359 ah->config.sw_beacon_response_time = 10;
360 ah->config.additional_swba_backoff = 0;
361 ah->config.ack_6mb = 0x0;
362 ah->config.cwm_ignore_extcca = 0;
363 ah->config.pcie_powersave_enable = 0;
364 ah->config.pcie_l1skp_enable = 0;
365 ah->config.pcie_clock_req = 0;
366 ah->config.pcie_power_reset = 0x100;
367 ah->config.pcie_restore = 0;
368 ah->config.pcie_waen = 0;
369 ah->config.analog_shiftreg = 1;
370 ah->config.ht_enable = 1;
371 ah->config.ofdm_trig_low = 200;
372 ah->config.ofdm_trig_high = 500;
373 ah->config.cck_trig_high = 200;
374 ah->config.cck_trig_low = 100;
375 ah->config.enable_ani = 1;
376 ah->config.noise_immunity_level = 4;
377 ah->config.ofdm_weaksignal_det = 1;
378 ah->config.cck_weaksignal_thr = 0;
379 ah->config.spur_immunity_level = 2;
380 ah->config.firstep_level = 0;
381 ah->config.rssi_thr_high = 40;
382 ah->config.rssi_thr_low = 7;
383 ah->config.diversity_control = 0;
384 ah->config.antenna_switch_swap = 0;
f078f209 385
f1dc5600 386 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 387 ah->config.spurchans[i][0] = AR_NO_SPUR;
388 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 389 }
390
2660b81a 391 ah->config.intr_mitigation = 1;
f078f209
LR		 392}
393
cbe61d8a
S		 394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
395 int *status)
f078f209 396{
cbe61d8a 397 struct ath_hw *ah;
f078f209 398
cbe61d8a
S		 399 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
400 if (ah == NULL) {
f078f209 401 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 402 "Cannot allocate memory for state block\n");
f078f209
LR		 403 *status = -ENOMEM;
404 return NULL;
405 }
406
f078f209 407 ah->ah_sc = sc;
d535a42a 408 ah->hw_version.magic = AR5416_MAGIC;
d6bad496 409 ah->regulatory.country_code = CTRY_DEFAULT;
d535a42a
S		 410 ah->hw_version.devid = devid;
411 ah->hw_version.subvendorid = 0;
f078f209
LR		 412
413 ah->ah_flags = 0;
414 if ((devid == AR5416_AR9100_DEVID))
d535a42a 415 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 416 if (!AR_SREV_9100(ah))
417 ah->ah_flags = AH_USE_EEPROM;
418
d6bad496
S		 419 ah->regulatory.power_limit = MAX_RATE_POWER;
420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
2660b81a
S		 421 ah->atim_window = 0;
422 ah->diversity_control = ah->config.diversity_control;
423 ah->antenna_switch_swap =
424 ah->config.antenna_switch_swap;
425 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
426 ah->beacon_interval = 100;
427 ah->enable_32kHz_clock = DONT_USE_32KHZ;
428 ah->slottime = (u32) -1;
429 ah->acktimeout = (u32) -1;
430 ah->ctstimeout = (u32) -1;
431 ah->globaltxtimeout = (u32) -1;
432
433 ah->gbeacon_rate = 0;
f078f209 434
cbe61d8a 435 return ah;
f078f209
LR		 436}
437
cbe61d8a 438static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 439{
f1dc5600
S		 440 bool rfStatus = false;
441 int ecode = 0;
f078f209 442
f1dc5600
S		 443 rfStatus = ath9k_hw_init_rf(ah, &ecode);
444 if (!rfStatus) {
445 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 446 "RF setup failed, status %u\n", ecode);
f1dc5600
S		 447 return ecode;
448 }
f078f209 449
f1dc5600 450 return 0;
f078f209
LR		 451}
452
cbe61d8a 453static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 454{
f1dc5600
S		 455 u32 val;
456
457 REG_WRITE(ah, AR_PHY(0), 0x00000007);
458
459 val = ath9k_hw_get_radiorev(ah);
460 switch (val & AR_RADIO_SREV_MAJOR) {
461 case 0:
462 val = AR_RAD5133_SREV_MAJOR;
463 break;
464 case AR_RAD5133_SREV_MAJOR:
465 case AR_RAD5122_SREV_MAJOR:
466 case AR_RAD2133_SREV_MAJOR:
467 case AR_RAD2122_SREV_MAJOR:
468 break;
f078f209 469 default:
f1dc5600 470 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 471 "5G Radio Chip Rev 0x%02X is not "
f1dc5600 472 "supported by this driver\n",
d535a42a 473 ah->hw_version.analog5GhzRev);
f1dc5600 474 return -EOPNOTSUPP;
f078f209 475 }
f078f209 476
d535a42a 477 ah->hw_version.analog5GhzRev = val;
f078f209 478
f1dc5600 479 return 0;
f078f209
LR		 480}
481
cbe61d8a 482static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209
LR		 483{
484 u32 sum;
485 int i;
486 u16 eeval;
f078f209
LR		 487
488 sum = 0;
489 for (i = 0; i < 3; i++) {
f74df6fb 490 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 491 sum += eeval;
ba52da58
S		 492 ah->macaddr[2 * i] = eeval >> 8;
493 ah->macaddr[2 * i + 1] = eeval & 0xff;
f078f209
LR		 494 }
495 if (sum == 0 || sum == 0xffff * 3) {
496 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 497 "mac address read failed: %pM\n",
ba52da58 498 ah->macaddr);
f078f209
LR		 499 return -EADDRNOTAVAIL;
500 }
501
502 return 0;
503}
504
cbe61d8a 505static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 506{
507 u32 rxgain_type;
9f804202 508
f74df6fb
S		 509 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 511
512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 513 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 514 ar9280Modes_backoff_13db_rxgain_9280_2,
515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 517 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 518 ar9280Modes_backoff_23db_rxgain_9280_2,
519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
520 else
2660b81a 521 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 522 ar9280Modes_original_rxgain_9280_2,
523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 524 } else {
2660b81a 525 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 526 ar9280Modes_original_rxgain_9280_2,
527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 528 }
9f804202
SB		 529}
530
cbe61d8a 531static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 532{
533 u32 txgain_type;
9f804202 534
f74df6fb
S		 535 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 537
538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 539 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 540 ar9280Modes_high_power_tx_gain_9280_2,
541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
542 else
2660b81a 543 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 544 ar9280Modes_original_tx_gain_9280_2,
545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 546 } else {
2660b81a 547 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 548 ar9280Modes_original_tx_gain_9280_2,
549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 550 }
9f804202
SB		 551}
552
cbe61d8a 553static int ath9k_hw_post_attach(struct ath_hw *ah)
f078f209 554{
f1dc5600 555 int ecode;
f078f209 556
f1dc5600
S		 557 if (!ath9k_hw_chip_test(ah)) {
558 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 559 "hardware self-test failed\n");
f1dc5600 560 return -ENODEV;
f078f209 561 }
f078f209 562
f1dc5600
S		 563 ecode = ath9k_hw_rf_claim(ah);
564 if (ecode != 0)
f078f209 565 return ecode;
f078f209 566
f1dc5600
S		 567 ecode = ath9k_hw_eeprom_attach(ah);
568 if (ecode != 0)
569 return ecode;
570 ecode = ath9k_hw_rfattach(ah);
571 if (ecode != 0)
572 return ecode;
f078f209 573
f1dc5600
S		 574 if (!AR_SREV_9100(ah)) {
575 ath9k_hw_ani_setup(ah);
576 ath9k_hw_ani_attach(ah);
f078f209
LR		 577 }
578
f078f209
LR		 579 return 0;
580}
581
cbe61d8a
S		 582static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
583 int *status)
f078f209 584{
cbe61d8a 585 struct ath_hw *ah;
f1dc5600 586 int ecode;
f6688cd8 587 u32 i, j;
f078f209 588
cbe61d8a
S		 589 ah = ath9k_hw_newstate(devid, sc, status);
590 if (ah == NULL)
f1dc5600 591 return NULL;
f078f209 592
f1dc5600 593 ath9k_hw_set_defaults(ah);
f078f209 594
2660b81a
S		 595 if (ah->config.intr_mitigation != 0)
596 ah->intr_mitigation = true;
f078f209 597
f1dc5600 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
cbe61d8a 599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
f1dc5600
S		 600 ecode = -EIO;
601 goto bad;
602 }
f078f209 603
f1dc5600 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
cbe61d8a 605 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
f1dc5600
S		 606 ecode = -EIO;
607 goto bad;
608 }
f078f209 609
2660b81a 610 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
d535a42a 611 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
2660b81a 612 ah->config.serialize_regmode =
f1dc5600 613 SER_REG_MODE_ON;
f078f209 614 } else {
2660b81a 615 ah->config.serialize_regmode =
f1dc5600 616 SER_REG_MODE_OFF;
f078f209
LR		 617 }
618 }
f078f209 619
cbe61d8a 620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
2660b81a 621 ah->config.serialize_regmode);
f078f209 622
d535a42a
S		 623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
625 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
e7594072 626 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
cbe61d8a 627 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 628 "Mac Chip Rev 0x%02x.%x is not supported by "
d535a42a
S		 629 "this driver\n", ah->hw_version.macVersion,
630 ah->hw_version.macRev);
f1dc5600
S		 631 ecode = -EOPNOTSUPP;
632 goto bad;
633 }
f078f209 634
f1dc5600 635 if (AR_SREV_9100(ah)) {
2660b81a
S		 636 ah->iq_caldata.calData = &iq_cal_multi_sample;
637 ah->supp_cals = IQ_MISMATCH_CAL;
638 ah->is_pciexpress = false;
f1dc5600 639 }
d535a42a 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
f078f209 641
f1dc5600
S		 642 if (AR_SREV_9160_10_OR_LATER(ah)) {
643 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 644 ah->iq_caldata.calData = &iq_cal_single_sample;
645 ah->adcgain_caldata.calData =
f1dc5600 646 &adc_gain_cal_single_sample;
2660b81a 647 ah->adcdc_caldata.calData =
f1dc5600 648 &adc_dc_cal_single_sample;
2660b81a 649 ah->adcdc_calinitdata.calData =
f1dc5600
S		 650 &adc_init_dc_cal;
651 } else {
2660b81a
S		 652 ah->iq_caldata.calData = &iq_cal_multi_sample;
653 ah->adcgain_caldata.calData =
f1dc5600 654 &adc_gain_cal_multi_sample;
2660b81a 655 ah->adcdc_caldata.calData =
f1dc5600 656 &adc_dc_cal_multi_sample;
2660b81a 657 ah->adcdc_calinitdata.calData =
f1dc5600
S		 658 &adc_init_dc_cal;
659 }
2660b81a 660 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 661 }
f078f209 662
f1dc5600 663 if (AR_SREV_9160(ah)) {
2660b81a
S		 664 ah->config.enable_ani = 1;
665 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
f1dc5600
S		 666 ATH9K_ANI_FIRSTEP_LEVEL);
667 } else {
2660b81a 668 ah->ani_function = ATH9K_ANI_ALL;
f1dc5600 669 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
f1dc5600 671 }
f078f209 672 }
f078f209 673
cbe61d8a 674 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 675 "This Mac Chip Rev 0x%02x.%x is \n",
d535a42a 676 ah->hw_version.macVersion, ah->hw_version.macRev);
f078f209 677
e7594072 678 if (AR_SREV_9285_12_OR_LATER(ah)) {
2660b81a 679 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 681 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
683
2660b81a
S		 684 if (ah->config.pcie_clock_req) {
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
688 } else {
2660b81a 689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
692 2);
693 }
694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 695 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 696 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 697 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 698 ARRAY_SIZE(ar9285Common_9285), 2);
699
2660b81a
S		 700 if (ah->config.pcie_clock_req) {
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 702 ar9285PciePhy_clkreq_off_L1_9285,
703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
704 } else {
2660b81a 705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 706 ar9285PciePhy_clkreq_always_on_L1_9285,
707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
708 }
709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 710 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 712 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 713 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 714
2660b81a
S		 715 if (ah->config.pcie_clock_req) {
716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 717 ar9280PciePhy_clkreq_off_L1_9280,
718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
719 } else {
2660b81a 720 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 721 ar9280PciePhy_clkreq_always_on_L1_9280,
722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
723 }
2660b81a 724 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 725 ar9280Modes_fast_clock_9280_2,
726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 728 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 729 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 730 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 731 ARRAY_SIZE(ar9280Common_9280), 2);
732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 733 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 734 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 735 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 736 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 737 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 738 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 739 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 741 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 742 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 743 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 744 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 745 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 746 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 747 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 748 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 749 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 751 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 752 ARRAY_SIZE(ar5416Bank7_9160), 2);
753 if (AR_SREV_9160_11(ah)) {
2660b81a 754 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 755 ar5416Addac_91601_1,
756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
757 } else {
2660b81a 758 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 759 ARRAY_SIZE(ar5416Addac_9160), 2);
760 }
761 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 762 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 763 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 764 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 765 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 766 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 767 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 768 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 770 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 771 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 772 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 773 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 775 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 777 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 781 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 782 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 783 ARRAY_SIZE(ar5416Addac_9100), 2);
784 } else {
2660b81a 785 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 786 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 787 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 788 ARRAY_SIZE(ar5416Common), 2);
2660b81a 789 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 790 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 791 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 792 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 793 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 794 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 795 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 796 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 797 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 798 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 800 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 802 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 804 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 805 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 806 ARRAY_SIZE(ar5416Addac), 2);
f078f209 807 }
f078f209 808
2660b81a 809 if (ah->is_pciexpress)
f1dc5600
S		 810 ath9k_hw_configpcipowersave(ah, 0);
811 else
812 ath9k_hw_disablepcie(ah);
f078f209 813
f1dc5600
S		 814 ecode = ath9k_hw_post_attach(ah);
815 if (ecode != 0)
816 goto bad;
f078f209 817
9f804202 818 /* rxgain table */
e7594072 819 if (AR_SREV_9280_20(ah))
9f804202
SB		 820 ath9k_hw_init_rxgain_ini(ah);
821
822 /* txgain table */
e7594072 823 if (AR_SREV_9280_20(ah))
9f804202
SB		 824 ath9k_hw_init_txgain_ini(ah);
825
d535a42a 826 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
2660b81a
S		 827 for (i = 0; i < ah->iniModes.ia_rows; i++) {
828 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 829
2660b81a
S		 830 for (j = 1; j < ah->iniModes.ia_columns; j++) {
831 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 832
2660b81a 833 INI_RA(&ah->iniModes, i, j) =
e7594072 834 ath9k_hw_ini_fixup(ah,
2660b81a 835 &ah->eeprom.def,
f1dc5600
S		 836 reg, val);
837 }
f078f209 838 }
f1dc5600 839 }
f6688cd8 840
f1dc5600 841 if (!ath9k_hw_fill_cap_info(ah)) {
cbe61d8a 842 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 843 "failed ath9k_hw_fill_cap_info\n");
f1dc5600
S		 844 ecode = -EINVAL;
845 goto bad;
f078f209
LR		 846 }
847
f1dc5600
S		 848 ecode = ath9k_hw_init_macaddr(ah);
849 if (ecode != 0) {
cbe61d8a 850 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 851 "failed initializing mac address\n");
f1dc5600 852 goto bad;
f078f209
LR		 853 }
854
f1dc5600 855 if (AR_SREV_9285(ah))
2660b81a 856 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 857 else
2660b81a 858 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 859
f1dc5600 860 ath9k_init_nfcal_hist_buffer(ah);
f078f209 861
f1dc5600
S		 862 return ah;
863bad:
cbe61d8a
S		 864 if (ah)
865 ath9k_hw_detach(ah);
f1dc5600
S		 866 if (status)
867 *status = ecode;
f078f209 868
f1dc5600 869 return NULL;
f078f209
LR		 870}
871
cbe61d8a 872static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 873 struct ath9k_channel *chan)
f078f209 874{
f1dc5600 875 u32 synthDelay;
f078f209 876
f1dc5600 877 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 878 if (IS_CHAN_B(chan))
f1dc5600
S		 879 synthDelay = (4 * synthDelay) / 22;
880 else
881 synthDelay /= 10;
f078f209 882
f1dc5600 883 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 884
f1dc5600 885 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 886}
887
cbe61d8a 888static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 889{
f1dc5600
S		 890 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
891 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 892
f1dc5600
S		 893 REG_WRITE(ah, AR_QOS_NO_ACK,
894 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
895 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
896 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
897
898 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
899 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
900 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
901 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
902 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 903}
904
cbe61d8a 905static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 906 struct ath9k_channel *chan)
f078f209 907{
f1dc5600 908 u32 pll;
f078f209 909
f1dc5600
S		 910 if (AR_SREV_9100(ah)) {
911 if (chan && IS_CHAN_5GHZ(chan))
912 pll = 0x1450;
f078f209 913 else
f1dc5600
S		 914 pll = 0x1458;
915 } else {
916 if (AR_SREV_9280_10_OR_LATER(ah)) {
917 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 918
f1dc5600
S		 919 if (chan && IS_CHAN_HALF_RATE(chan))
920 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
921 else if (chan && IS_CHAN_QUARTER_RATE(chan))
922 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 923
f1dc5600
S		 924 if (chan && IS_CHAN_5GHZ(chan)) {
925 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 926
f078f209 927
f1dc5600
S		 928 if (AR_SREV_9280_20(ah)) {
929 if (((chan->channel % 20) == 0)
930 || ((chan->channel % 10) == 0))
931 pll = 0x2850;
932 else
933 pll = 0x142c;
934 }
935 } else {
936 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
937 }
f078f209 938
f1dc5600 939 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 940
f1dc5600 941 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 942
f1dc5600
S		 943 if (chan && IS_CHAN_HALF_RATE(chan))
944 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
945 else if (chan && IS_CHAN_QUARTER_RATE(chan))
946 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 947
f1dc5600
S		 948 if (chan && IS_CHAN_5GHZ(chan))
949 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
950 else
951 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
952 } else {
953 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 954
f1dc5600
S		 955 if (chan && IS_CHAN_HALF_RATE(chan))
956 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
957 else if (chan && IS_CHAN_QUARTER_RATE(chan))
958 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 959
f1dc5600
S		 960 if (chan && IS_CHAN_5GHZ(chan))
961 pll |= SM(0xa, AR_RTC_PLL_DIV);
962 else
963 pll |= SM(0xb, AR_RTC_PLL_DIV);
964 }
965 }
d03a66c1 966 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 967
f1dc5600
S		 968 udelay(RTC_PLL_SETTLE_DELAY);
969
970 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 971}
972
cbe61d8a 973static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 974{
f078f209
LR		 975 int rx_chainmask, tx_chainmask;
976
2660b81a
S		 977 rx_chainmask = ah->rxchainmask;
978 tx_chainmask = ah->txchainmask;
f078f209
LR		 979
980 switch (rx_chainmask) {
981 case 0x5:
982 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
983 AR_PHY_SWAP_ALT_CHAIN);
984 case 0x3:
d535a42a 985 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 986 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
987 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
988 break;
989 }
990 case 0x1:
991 case 0x2:
f078f209
LR		 992 case 0x7:
993 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
994 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
995 break;
996 default:
997 break;
998 }
999
1000 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1001 if (tx_chainmask == 0x5) {
1002 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1003 AR_PHY_SWAP_ALT_CHAIN);
1004 }
1005 if (AR_SREV_9100(ah))
1006 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1007 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1008}
1009
cbe61d8a 1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1011 enum nl80211_iftype opmode)
f078f209 1012{
2660b81a 1013 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1014 AR_IMR_TXURN |
1015 AR_IMR_RXERR |
1016 AR_IMR_RXORN |
1017 AR_IMR_BCNMISC;
f078f209 1018
2660b81a
S		 1019 if (ah->intr_mitigation)
1020 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1021 else
2660b81a 1022 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1023
2660b81a 1024 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1025
d97809db 1026 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1027 ah->mask_reg |= AR_IMR_MIB;
f078f209 1028
2660b81a 1029 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1031
f1dc5600
S		 1032 if (!AR_SREV_9100(ah)) {
1033 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1034 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1035 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1036 }
f078f209
LR		 1037}
1038
cbe61d8a 1039static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1040{
f078f209 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1043 ah->acktimeout = (u32) -1;
f078f209
LR		 1044 return false;
1045 } else {
1046 REG_RMW_FIELD(ah, AR_TIME_OUT,
1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1048 ah->acktimeout = us;
f078f209
LR		 1049 return true;
1050 }
1051}
1052
cbe61d8a 1053static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1054{
f078f209 1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1057 ah->ctstimeout = (u32) -1;
f078f209
LR		 1058 return false;
1059 } else {
1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1062 ah->ctstimeout = us;
f078f209
LR		 1063 return true;
1064 }
1065}
f1dc5600 1066
cbe61d8a 1067static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1068{
f078f209
LR		 1069 if (tu > 0xFFFF) {
1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1071 "bad global tx timeout %u\n", tu);
2660b81a 1072 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1073 return false;
1074 } else {
1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1076 ah->globaltxtimeout = tu;
f078f209
LR		 1077 return true;
1078 }
1079}
1080
cbe61d8a 1081static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1082{
2660b81a
S		 1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1084 ah->misc_mode);
f078f209 1085
2660b81a 1086 if (ah->misc_mode != 0)
f1dc5600 1087 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1088 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1089 if (ah->slottime != (u32) -1)
1090 ath9k_hw_setslottime(ah, ah->slottime);
1091 if (ah->acktimeout != (u32) -1)
1092 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1093 if (ah->ctstimeout != (u32) -1)
1094 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1095 if (ah->globaltxtimeout != (u32) -1)
1096 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1097}
1098
1099const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1100{
1101 return vendorid == ATHEROS_VENDOR_ID ?
1102 ath9k_hw_devname(devid) : NULL;
1103}
1104
cbe61d8a 1105void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1106{
1107 if (!AR_SREV_9100(ah))
1108 ath9k_hw_ani_detach(ah);
1109
1110 ath9k_hw_rfdetach(ah);
1111 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1112 kfree(ah);
1113}
1114
cbe61d8a 1115struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
f1dc5600 1116{
cbe61d8a 1117 struct ath_hw *ah = NULL;
f1dc5600
S		 1118
1119 switch (devid) {
1120 case AR5416_DEVID_PCI:
1121 case AR5416_DEVID_PCIE:
0c1aa495 1122 case AR5416_AR9100_DEVID:
f1dc5600
S		 1123 case AR9160_DEVID_PCI:
1124 case AR9280_DEVID_PCI:
1125 case AR9280_DEVID_PCIE:
e7594072 1126 case AR9285_DEVID_PCIE:
cbe61d8a 1127 ah = ath9k_hw_do_attach(devid, sc, error);
f1dc5600
S		 1128 break;
1129 default:
f1dc5600
S		 1130 *error = -ENXIO;
1131 break;
f078f209 1132 }
f1dc5600
S		 1133
1134 return ah;
1135}
1136
1137/*******/
1138/* INI */
1139/*******/
1140
cbe61d8a 1141static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1142 struct ath9k_channel *chan)
1143{
8aa15e15
SB		 1144 /*
1145 * Set the RX_ABORT and RX_DIS and clear if off only after
1146 * RXE is set for MAC. This prevents frames with corrupted
1147 * descriptor status.
1148 */
1149 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1150
1151
f1dc5600
S		 1152 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1153 AR_SREV_9280_10_OR_LATER(ah))
1154 return;
1155
1156 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1157}
1158
cbe61d8a 1159static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1160 struct ar5416_eeprom_def *pEepData,
f1dc5600 1161 u32 reg, u32 value)
f078f209 1162{
f1dc5600 1163 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1164
d535a42a 1165 switch (ah->hw_version.devid) {
f1dc5600
S		 1166 case AR9280_DEVID_PCI:
1167 if (reg == 0x7894) {
1168 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1169 "ini VAL: %x EEPROM: %x\n", value,
1170 (pBase->version & 0xff));
1171
1172 if ((pBase->version & 0xff) > 0x0a) {
1173 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1174 "PWDCLKIND: %d\n",
1175 pBase->pwdclkind);
1176 value &= ~AR_AN_TOP2_PWDCLKIND;
1177 value |= AR_AN_TOP2_PWDCLKIND &
1178 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1179 } else {
1180 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1181 "PWDCLKIND Earlier Rev\n");
1182 }
1183
1184 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1185 "final ini VAL: %x\n", value);
1186 }
1187 break;
1188 }
1189
1190 return value;
f078f209
LR		 1191}
1192
cbe61d8a 1193static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1194 struct ar5416_eeprom_def *pEepData,
1195 u32 reg, u32 value)
1196{
2660b81a 1197 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1198 return value;
1199 else
1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1201}
1202
cbe61d8a 1203static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1204 struct ath9k_channel *chan,
1205 enum ath9k_ht_macmode macmode)
f078f209
LR		 1206{
1207 int i, regWrites = 0;
5f8e077c 1208 struct ieee80211_channel *channel = chan->chan;
f078f209
LR		 1209 u32 modesIndex, freqIndex;
1210 int status;
1211
1212 switch (chan->chanmode) {
1213 case CHANNEL_A:
1214 case CHANNEL_A_HT20:
1215 modesIndex = 1;
1216 freqIndex = 1;
1217 break;
1218 case CHANNEL_A_HT40PLUS:
1219 case CHANNEL_A_HT40MINUS:
1220 modesIndex = 2;
1221 freqIndex = 1;
1222 break;
1223 case CHANNEL_G:
1224 case CHANNEL_G_HT20:
1225 case CHANNEL_B:
1226 modesIndex = 4;
1227 freqIndex = 2;
1228 break;
1229 case CHANNEL_G_HT40PLUS:
1230 case CHANNEL_G_HT40MINUS:
1231 modesIndex = 3;
1232 freqIndex = 2;
1233 break;
1234
1235 default:
1236 return -EINVAL;
1237 }
1238
1239 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1240 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1241 ah->eep_ops->set_addac(ah, chan);
f078f209
LR		 1242
1243 if (AR_SREV_5416_V22_OR_LATER(ah)) {
2660b81a 1244 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1245 } else {
1246 struct ar5416IniArray temp;
1247 u32 addacSize =
2660b81a
S		 1248 sizeof(u32) * ah->iniAddac.ia_rows *
1249 ah->iniAddac.ia_columns;
f078f209 1250
2660b81a
S		 1251 memcpy(ah->addac5416_21,
1252 ah->iniAddac.ia_array, addacSize);
f078f209 1253
2660b81a 1254 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1255
2660b81a
S		 1256 temp.ia_array = ah->addac5416_21;
1257 temp.ia_columns = ah->iniAddac.ia_columns;
1258 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1259 REG_WRITE_ARRAY(&temp, 1, regWrites);
1260 }
f1dc5600 1261
f078f209
LR		 1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1263
2660b81a
S		 1264 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1265 u32 reg = INI_RA(&ah->iniModes, i, 0);
1266 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1267
f078f209
LR		 1268 REG_WRITE(ah, reg, val);
1269
1270 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1271 && ah->config.analog_shiftreg) {
f078f209
LR		 1272 udelay(100);
1273 }
1274
1275 DO_DELAY(regWrites);
1276 }
1277
e7594072 1278 if (AR_SREV_9280(ah))
2660b81a 1279 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1280
e7594072 1281 if (AR_SREV_9280(ah))
2660b81a 1282 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1283
2660b81a
S		 1284 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1285 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1286 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1287
1288 REG_WRITE(ah, reg, val);
1289
1290 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1291 && ah->config.analog_shiftreg) {
f078f209
LR		 1292 udelay(100);
1293 }
1294
1295 DO_DELAY(regWrites);
1296 }
1297
1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1299
1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1301 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1302 regWrites);
1303 }
1304
1305 ath9k_hw_override_ini(ah, chan);
1306 ath9k_hw_set_regs(ah, chan, macmode);
1307 ath9k_hw_init_chain_masks(ah);
1308
f74df6fb
S		 1309 status = ah->eep_ops->set_txpower(ah, chan,
1310 ath9k_regd_get_ctl(ah, chan),
1311 channel->max_antenna_gain * 2,
1312 channel->max_power * 2,
1313 min((u32) MAX_RATE_POWER,
1314 (u32) ah->regulatory.power_limit));
f078f209
LR		 1315 if (status != 0) {
1316 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 1317 "error init'ing transmit power\n");
f078f209
LR		 1318 return -EIO;
1319 }
1320
1321 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1322 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 1323 "ar5416SetRfRegs failed\n");
f078f209
LR		 1324 return -EIO;
1325 }
1326
1327 return 0;
1328}
1329
f1dc5600
S		 1330/****************************************/
1331/* Reset and Channel Switching Routines */
1332/****************************************/
1333
cbe61d8a 1334static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1335{
f1dc5600
S		 1336 u32 rfMode = 0;
1337
1338 if (chan == NULL)
1339 return;
1340
1341 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1342 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1343
1344 if (!AR_SREV_9280_10_OR_LATER(ah))
1345 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1346 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1347
1348 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1349 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1350
1351 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1352}
1353
cbe61d8a 1354static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1355{
1356 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1357}
1358
cbe61d8a 1359static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1360{
1361 u32 regval;
1362
1363 regval = REG_READ(ah, AR_AHB_MODE);
1364 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1365
1366 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1367 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1368
2660b81a 1369 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600
S		 1370
1371 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1372 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1373
1374 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1375
1376 if (AR_SREV_9285(ah)) {
1377 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1378 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1379 } else {
1380 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1381 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1382 }
1383}
1384
cbe61d8a 1385static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1386{
1387 u32 val;
1388
1389 val = REG_READ(ah, AR_STA_ID1);
1390 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1391 switch (opmode) {
d97809db 1392 case NL80211_IFTYPE_AP:
f1dc5600
S		 1393 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1394 | AR_STA_ID1_KSRCH_MODE);
1395 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1396 break;
d97809db 1397 case NL80211_IFTYPE_ADHOC:
f1dc5600
S		 1398 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1399 | AR_STA_ID1_KSRCH_MODE);
1400 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1401 break;
d97809db
CM		 1402 case NL80211_IFTYPE_STATION:
1403 case NL80211_IFTYPE_MONITOR:
f1dc5600 1404 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1405 break;
f1dc5600
S		 1406 }
1407}
1408
cbe61d8a 1409static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1410 u32 coef_scaled,
1411 u32 *coef_mantissa,
1412 u32 *coef_exponent)
1413{
1414 u32 coef_exp, coef_man;
1415
1416 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1417 if ((coef_scaled >> coef_exp) & 0x1)
1418 break;
1419
1420 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1421
1422 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1423
1424 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1425 *coef_exponent = coef_exp - 16;
1426}
1427
cbe61d8a 1428static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1429 struct ath9k_channel *chan)
1430{
1431 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1432 u32 clockMhzScaled = 0x64000000;
1433 struct chan_centers centers;
1434
1435 if (IS_CHAN_HALF_RATE(chan))
1436 clockMhzScaled = clockMhzScaled >> 1;
1437 else if (IS_CHAN_QUARTER_RATE(chan))
1438 clockMhzScaled = clockMhzScaled >> 2;
1439
1440 ath9k_hw_get_channel_centers(ah, chan, &centers);
1441 coef_scaled = clockMhzScaled / centers.synth_center;
1442
1443 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1444 &ds_coef_exp);
1445
1446 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1447 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1448 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1449 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1450
1451 coef_scaled = (9 * coef_scaled) / 10;
1452
1453 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1454 &ds_coef_exp);
1455
1456 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1457 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1458 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1459 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1460}
1461
cbe61d8a 1462static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1463{
1464 u32 rst_flags;
1465 u32 tmpReg;
1466
1467 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1468 AR_RTC_FORCE_WAKE_ON_INT);
1469
1470 if (AR_SREV_9100(ah)) {
1471 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1472 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1473 } else {
1474 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1475 if (tmpReg &
1476 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1477 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1478 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1479 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1480 } else {
1481 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1482 }
1483
1484 rst_flags = AR_RTC_RC_MAC_WARM;
1485 if (type == ATH9K_RESET_COLD)
1486 rst_flags |= AR_RTC_RC_MAC_COLD;
1487 }
1488
d03a66c1 1489 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1490 udelay(50);
1491
d03a66c1
GJ		 1492 REG_WRITE(ah, AR_RTC_RC, 0);
1493 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
f1dc5600 1494 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1495 "RTC stuck in MAC reset\n");
f1dc5600
S		 1496 return false;
1497 }
1498
1499 if (!AR_SREV_9100(ah))
1500 REG_WRITE(ah, AR_RC, 0);
1501
1502 ath9k_hw_init_pll(ah, NULL);
1503
1504 if (AR_SREV_9100(ah))
1505 udelay(50);
1506
1507 return true;
1508}
1509
cbe61d8a 1510static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1511{
1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1513 AR_RTC_FORCE_WAKE_ON_INT);
1514
d03a66c1
GJ		 1515 REG_WRITE(ah, AR_RTC_RESET, 0);
1516 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1517
1518 if (!ath9k_hw_wait(ah,
1519 AR_RTC_STATUS,
1520 AR_RTC_STATUS_M,
1521 AR_RTC_STATUS_ON)) {
04bd4638 1522 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1523 return false;
f078f209
LR		 1524 }
1525
f1dc5600
S		 1526 ath9k_hw_read_revisions(ah);
1527
1528 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1529}
1530
cbe61d8a 1531static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1532{
1533 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1534 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1535
1536 switch (type) {
1537 case ATH9K_RESET_POWER_ON:
1538 return ath9k_hw_set_reset_power_on(ah);
1539 break;
1540 case ATH9K_RESET_WARM:
1541 case ATH9K_RESET_COLD:
1542 return ath9k_hw_set_reset(ah, type);
1543 break;
1544 default:
1545 return false;
1546 }
f078f209
LR		 1547}
1548
cbe61d8a 1549static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1550 enum ath9k_ht_macmode macmode)
f078f209 1551{
f1dc5600 1552 u32 phymode;
e7594072 1553 u32 enableDacFifo = 0;
f078f209 1554
e7594072
SB		 1555 if (AR_SREV_9285_10_OR_LATER(ah))
1556 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1557 AR_PHY_FC_ENABLE_DAC_FIFO);
1558
f1dc5600 1559 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1560 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1561
1562 if (IS_CHAN_HT40(chan)) {
1563 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1564
f1dc5600
S		 1565 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1566 (chan->chanmode == CHANNEL_G_HT40PLUS))
1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1568
2660b81a 1569 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1571 }
f1dc5600
S		 1572 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1573
1574 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1575
f1dc5600
S		 1576 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1577 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1578}
1579
cbe61d8a 1580static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1581 struct ath9k_channel *chan)
f078f209 1582{
f1dc5600
S		 1583 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1584 return false;
f078f209 1585
f1dc5600
S		 1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1587 return false;
f078f209 1588
2660b81a 1589 ah->chip_fullsleep = false;
f1dc5600 1590 ath9k_hw_init_pll(ah, chan);
f1dc5600 1591 ath9k_hw_set_rfmode(ah, chan);
f078f209 1592
f1dc5600 1593 return true;
f078f209
LR		 1594}
1595
cbe61d8a 1596static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1597 struct ath9k_channel *chan,
1598 enum ath9k_ht_macmode macmode)
f078f209 1599{
5f8e077c 1600 struct ieee80211_channel *channel = chan->chan;
f078f209 1601 u32 synthDelay, qnum;
f078f209
LR		 1602
1603 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1604 if (ath9k_hw_numtxpending(ah, qnum)) {
1605 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1606 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1607 return false;
1608 }
1609 }
1610
1611 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1612 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1613 AR_PHY_RFBUS_GRANT_EN)) {
04bd4638
S		 1614 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1615 "Could not kill baseband RX\n");
f078f209
LR		 1616 return false;
1617 }
1618
1619 ath9k_hw_set_regs(ah, chan, macmode);
1620
1621 if (AR_SREV_9280_10_OR_LATER(ah)) {
1622 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1623 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1624 "failed to set channel\n");
f078f209
LR		 1625 return false;
1626 }
1627 } else {
1628 if (!(ath9k_hw_set_channel(ah, chan))) {
1629 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1630 "failed to set channel\n");
f078f209
LR		 1631 return false;
1632 }
1633 }
1634
f74df6fb
S		 1635 if (ah->eep_ops->set_txpower(ah, chan,
1636 ath9k_regd_get_ctl(ah, chan),
1637 channel->max_antenna_gain * 2,
1638 channel->max_power * 2,
1639 min((u32) MAX_RATE_POWER,
1640 (u32) ah->regulatory.power_limit)) != 0) {
f078f209 1641 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 1642 "error init'ing transmit power\n");
f078f209
LR		 1643 return false;
1644 }
1645
1646 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1647 if (IS_CHAN_B(chan))
f078f209
LR		 1648 synthDelay = (4 * synthDelay) / 22;
1649 else
1650 synthDelay /= 10;
1651
1652 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1653
1654 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1655
f1dc5600
S		 1656 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1657 ath9k_hw_set_delta_slope(ah, chan);
1658
1659 if (AR_SREV_9280_10_OR_LATER(ah))
1660 ath9k_hw_9280_spur_mitigate(ah, chan);
1661 else
1662 ath9k_hw_spur_mitigate(ah, chan);
1663
1664 if (!chan->oneTimeCalsDone)
1665 chan->oneTimeCalsDone = true;
1666
1667 return true;
1668}
1669
cbe61d8a 1670static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1671{
1672 int bb_spur = AR_NO_SPUR;
1673 int freq;
1674 int bin, cur_bin;
1675 int bb_spur_off, spur_subchannel_sd;
1676 int spur_freq_sd;
1677 int spur_delta_phase;
1678 int denominator;
1679 int upper, lower, cur_vit_mask;
1680 int tmp, newVal;
1681 int i;
1682 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1683 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1684 };
1685 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1686 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1687 };
1688 int inc[4] = { 0, 100, 0, 0 };
1689 struct chan_centers centers;
1690
1691 int8_t mask_m[123];
1692 int8_t mask_p[123];
1693 int8_t mask_amt;
1694 int tmp_mask;
1695 int cur_bb_spur;
1696 bool is2GHz = IS_CHAN_2GHZ(chan);
1697
1698 memset(&mask_m, 0, sizeof(int8_t) * 123);
1699 memset(&mask_p, 0, sizeof(int8_t) * 123);
1700
1701 ath9k_hw_get_channel_centers(ah, chan, &centers);
1702 freq = centers.synth_center;
1703
2660b81a 1704 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1705 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1706 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1707
1708 if (is2GHz)
1709 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1710 else
1711 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1712
1713 if (AR_NO_SPUR == cur_bb_spur)
1714 break;
1715 cur_bb_spur = cur_bb_spur - freq;
1716
1717 if (IS_CHAN_HT40(chan)) {
1718 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1719 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1720 bb_spur = cur_bb_spur;
1721 break;
1722 }
1723 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1724 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1725 bb_spur = cur_bb_spur;
1726 break;
1727 }
1728 }
1729
1730 if (AR_NO_SPUR == bb_spur) {
1731 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1732 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1733 return;
1734 } else {
1735 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1736 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1737 }
1738
1739 bin = bb_spur * 320;
1740
1741 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1742
1743 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1744 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1745 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1746 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1747 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1748
1749 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1750 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1751 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1752 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1753 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1754 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1755
1756 if (IS_CHAN_HT40(chan)) {
1757 if (bb_spur < 0) {
1758 spur_subchannel_sd = 1;
1759 bb_spur_off = bb_spur + 10;
1760 } else {
1761 spur_subchannel_sd = 0;
1762 bb_spur_off = bb_spur - 10;
1763 }
1764 } else {
1765 spur_subchannel_sd = 0;
1766 bb_spur_off = bb_spur;
1767 }
1768
1769 if (IS_CHAN_HT40(chan))
1770 spur_delta_phase =
1771 ((bb_spur * 262144) /
1772 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1773 else
1774 spur_delta_phase =
1775 ((bb_spur * 524288) /
1776 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1777
1778 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1779 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1780
1781 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1782 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1783 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1784 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1785
1786 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1787 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1788
1789 cur_bin = -6000;
1790 upper = bin + 100;
1791 lower = bin - 100;
1792
1793 for (i = 0; i < 4; i++) {
1794 int pilot_mask = 0;
1795 int chan_mask = 0;
1796 int bp = 0;
1797 for (bp = 0; bp < 30; bp++) {
1798 if ((cur_bin > lower) && (cur_bin < upper)) {
1799 pilot_mask = pilot_mask | 0x1 << bp;
1800 chan_mask = chan_mask | 0x1 << bp;
1801 }
1802 cur_bin += 100;
1803 }
1804 cur_bin += inc[i];
1805 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1806 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1807 }
1808
1809 cur_vit_mask = 6100;
1810 upper = bin + 120;
1811 lower = bin - 120;
1812
1813 for (i = 0; i < 123; i++) {
1814 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1815
1816 /* workaround for gcc bug #37014 */
a085ff71 1817 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 1818
a085ff71 1819 if (tmp_v < 75)
f1dc5600
S		 1820 mask_amt = 1;
1821 else
1822 mask_amt = 0;
1823 if (cur_vit_mask < 0)
1824 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1825 else
1826 mask_p[cur_vit_mask / 100] = mask_amt;
1827 }
1828 cur_vit_mask -= 100;
1829 }
1830
1831 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1832 | (mask_m[48] << 26) | (mask_m[49] << 24)
1833 | (mask_m[50] << 22) | (mask_m[51] << 20)
1834 | (mask_m[52] << 18) | (mask_m[53] << 16)
1835 | (mask_m[54] << 14) | (mask_m[55] << 12)
1836 | (mask_m[56] << 10) | (mask_m[57] << 8)
1837 | (mask_m[58] << 6) | (mask_m[59] << 4)
1838 | (mask_m[60] << 2) | (mask_m[61] << 0);
1839 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1840 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1841
1842 tmp_mask = (mask_m[31] << 28)
1843 | (mask_m[32] << 26) | (mask_m[33] << 24)
1844 | (mask_m[34] << 22) | (mask_m[35] << 20)
1845 | (mask_m[36] << 18) | (mask_m[37] << 16)
1846 | (mask_m[48] << 14) | (mask_m[39] << 12)
1847 | (mask_m[40] << 10) | (mask_m[41] << 8)
1848 | (mask_m[42] << 6) | (mask_m[43] << 4)
1849 | (mask_m[44] << 2) | (mask_m[45] << 0);
1850 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1851 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1852
1853 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1854 | (mask_m[18] << 26) | (mask_m[18] << 24)
1855 | (mask_m[20] << 22) | (mask_m[20] << 20)
1856 | (mask_m[22] << 18) | (mask_m[22] << 16)
1857 | (mask_m[24] << 14) | (mask_m[24] << 12)
1858 | (mask_m[25] << 10) | (mask_m[26] << 8)
1859 | (mask_m[27] << 6) | (mask_m[28] << 4)
1860 | (mask_m[29] << 2) | (mask_m[30] << 0);
1861 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1862 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1863
1864 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1865 | (mask_m[2] << 26) | (mask_m[3] << 24)
1866 | (mask_m[4] << 22) | (mask_m[5] << 20)
1867 | (mask_m[6] << 18) | (mask_m[7] << 16)
1868 | (mask_m[8] << 14) | (mask_m[9] << 12)
1869 | (mask_m[10] << 10) | (mask_m[11] << 8)
1870 | (mask_m[12] << 6) | (mask_m[13] << 4)
1871 | (mask_m[14] << 2) | (mask_m[15] << 0);
1872 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1873 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1874
1875 tmp_mask = (mask_p[15] << 28)
1876 | (mask_p[14] << 26) | (mask_p[13] << 24)
1877 | (mask_p[12] << 22) | (mask_p[11] << 20)
1878 | (mask_p[10] << 18) | (mask_p[9] << 16)
1879 | (mask_p[8] << 14) | (mask_p[7] << 12)
1880 | (mask_p[6] << 10) | (mask_p[5] << 8)
1881 | (mask_p[4] << 6) | (mask_p[3] << 4)
1882 | (mask_p[2] << 2) | (mask_p[1] << 0);
1883 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1884 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 1885
f1dc5600
S		 1886 tmp_mask = (mask_p[30] << 28)
1887 | (mask_p[29] << 26) | (mask_p[28] << 24)
1888 | (mask_p[27] << 22) | (mask_p[26] << 20)
1889 | (mask_p[25] << 18) | (mask_p[24] << 16)
1890 | (mask_p[23] << 14) | (mask_p[22] << 12)
1891 | (mask_p[21] << 10) | (mask_p[20] << 8)
1892 | (mask_p[19] << 6) | (mask_p[18] << 4)
1893 | (mask_p[17] << 2) | (mask_p[16] << 0);
1894 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1895 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 1896
f1dc5600
S		 1897 tmp_mask = (mask_p[45] << 28)
1898 | (mask_p[44] << 26) | (mask_p[43] << 24)
1899 | (mask_p[42] << 22) | (mask_p[41] << 20)
1900 | (mask_p[40] << 18) | (mask_p[39] << 16)
1901 | (mask_p[38] << 14) | (mask_p[37] << 12)
1902 | (mask_p[36] << 10) | (mask_p[35] << 8)
1903 | (mask_p[34] << 6) | (mask_p[33] << 4)
1904 | (mask_p[32] << 2) | (mask_p[31] << 0);
1905 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1906 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 1907
f1dc5600
S		 1908 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1909 | (mask_p[59] << 26) | (mask_p[58] << 24)
1910 | (mask_p[57] << 22) | (mask_p[56] << 20)
1911 | (mask_p[55] << 18) | (mask_p[54] << 16)
1912 | (mask_p[53] << 14) | (mask_p[52] << 12)
1913 | (mask_p[51] << 10) | (mask_p[50] << 8)
1914 | (mask_p[49] << 6) | (mask_p[48] << 4)
1915 | (mask_p[47] << 2) | (mask_p[46] << 0);
1916 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1917 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 1918}
1919
cbe61d8a 1920static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1921{
f1dc5600
S		 1922 int bb_spur = AR_NO_SPUR;
1923 int bin, cur_bin;
1924 int spur_freq_sd;
1925 int spur_delta_phase;
1926 int denominator;
1927 int upper, lower, cur_vit_mask;
1928 int tmp, new;
1929 int i;
1930 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1931 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1932 };
1933 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1934 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1935 };
1936 int inc[4] = { 0, 100, 0, 0 };
f078f209 1937
f1dc5600
S		 1938 int8_t mask_m[123];
1939 int8_t mask_p[123];
1940 int8_t mask_amt;
1941 int tmp_mask;
1942 int cur_bb_spur;
1943 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 1944
f1dc5600
S		 1945 memset(&mask_m, 0, sizeof(int8_t) * 123);
1946 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 1947
f1dc5600 1948 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1949 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1950 if (AR_NO_SPUR == cur_bb_spur)
1951 break;
1952 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1953 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1954 bb_spur = cur_bb_spur;
1955 break;
1956 }
1957 }
f078f209 1958
f1dc5600
S		 1959 if (AR_NO_SPUR == bb_spur)
1960 return;
f078f209 1961
f1dc5600 1962 bin = bb_spur * 32;
f078f209 1963
f1dc5600
S		 1964 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1965 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1966 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1967 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1968 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 1969
f1dc5600 1970 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 1971
f1dc5600
S		 1972 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1973 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1974 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1975 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1976 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1977 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 1978
f1dc5600
S		 1979 spur_delta_phase = ((bb_spur * 524288) / 100) &
1980 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 1981
f1dc5600
S		 1982 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1983 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 1984
f1dc5600
S		 1985 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1986 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1987 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1988 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 1989
f1dc5600
S		 1990 cur_bin = -6000;
1991 upper = bin + 100;
1992 lower = bin - 100;
f078f209 1993
f1dc5600
S		 1994 for (i = 0; i < 4; i++) {
1995 int pilot_mask = 0;
1996 int chan_mask = 0;
1997 int bp = 0;
1998 for (bp = 0; bp < 30; bp++) {
1999 if ((cur_bin > lower) && (cur_bin < upper)) {
2000 pilot_mask = pilot_mask | 0x1 << bp;
2001 chan_mask = chan_mask | 0x1 << bp;
2002 }
2003 cur_bin += 100;
2004 }
2005 cur_bin += inc[i];
2006 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2007 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2008 }
f078f209 2009
f1dc5600
S		 2010 cur_vit_mask = 6100;
2011 upper = bin + 120;
2012 lower = bin - 120;
f078f209 2013
f1dc5600
S		 2014 for (i = 0; i < 123; i++) {
2015 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2016
f1dc5600 2017 /* workaround for gcc bug #37014 */
a085ff71 2018 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2019
a085ff71 2020 if (tmp_v < 75)
f1dc5600
S		 2021 mask_amt = 1;
2022 else
2023 mask_amt = 0;
2024 if (cur_vit_mask < 0)
2025 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2026 else
2027 mask_p[cur_vit_mask / 100] = mask_amt;
2028 }
2029 cur_vit_mask -= 100;
f078f209
LR		 2030 }
2031
f1dc5600
S		 2032 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2033 | (mask_m[48] << 26) | (mask_m[49] << 24)
2034 | (mask_m[50] << 22) | (mask_m[51] << 20)
2035 | (mask_m[52] << 18) | (mask_m[53] << 16)
2036 | (mask_m[54] << 14) | (mask_m[55] << 12)
2037 | (mask_m[56] << 10) | (mask_m[57] << 8)
2038 | (mask_m[58] << 6) | (mask_m[59] << 4)
2039 | (mask_m[60] << 2) | (mask_m[61] << 0);
2040 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2041 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2042
f1dc5600
S		 2043 tmp_mask = (mask_m[31] << 28)
2044 | (mask_m[32] << 26) | (mask_m[33] << 24)
2045 | (mask_m[34] << 22) | (mask_m[35] << 20)
2046 | (mask_m[36] << 18) | (mask_m[37] << 16)
2047 | (mask_m[48] << 14) | (mask_m[39] << 12)
2048 | (mask_m[40] << 10) | (mask_m[41] << 8)
2049 | (mask_m[42] << 6) | (mask_m[43] << 4)
2050 | (mask_m[44] << 2) | (mask_m[45] << 0);
2051 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2052 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2053
f1dc5600
S		 2054 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2055 | (mask_m[18] << 26) | (mask_m[18] << 24)
2056 | (mask_m[20] << 22) | (mask_m[20] << 20)
2057 | (mask_m[22] << 18) | (mask_m[22] << 16)
2058 | (mask_m[24] << 14) | (mask_m[24] << 12)
2059 | (mask_m[25] << 10) | (mask_m[26] << 8)
2060 | (mask_m[27] << 6) | (mask_m[28] << 4)
2061 | (mask_m[29] << 2) | (mask_m[30] << 0);
2062 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2063 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2064
f1dc5600
S		 2065 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2066 | (mask_m[2] << 26) | (mask_m[3] << 24)
2067 | (mask_m[4] << 22) | (mask_m[5] << 20)
2068 | (mask_m[6] << 18) | (mask_m[7] << 16)
2069 | (mask_m[8] << 14) | (mask_m[9] << 12)
2070 | (mask_m[10] << 10) | (mask_m[11] << 8)
2071 | (mask_m[12] << 6) | (mask_m[13] << 4)
2072 | (mask_m[14] << 2) | (mask_m[15] << 0);
2073 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2074 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2075
f1dc5600
S		 2076 tmp_mask = (mask_p[15] << 28)
2077 | (mask_p[14] << 26) | (mask_p[13] << 24)
2078 | (mask_p[12] << 22) | (mask_p[11] << 20)
2079 | (mask_p[10] << 18) | (mask_p[9] << 16)
2080 | (mask_p[8] << 14) | (mask_p[7] << 12)
2081 | (mask_p[6] << 10) | (mask_p[5] << 8)
2082 | (mask_p[4] << 6) | (mask_p[3] << 4)
2083 | (mask_p[2] << 2) | (mask_p[1] << 0);
2084 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2085 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2086
f1dc5600
S		 2087 tmp_mask = (mask_p[30] << 28)
2088 | (mask_p[29] << 26) | (mask_p[28] << 24)
2089 | (mask_p[27] << 22) | (mask_p[26] << 20)
2090 | (mask_p[25] << 18) | (mask_p[24] << 16)
2091 | (mask_p[23] << 14) | (mask_p[22] << 12)
2092 | (mask_p[21] << 10) | (mask_p[20] << 8)
2093 | (mask_p[19] << 6) | (mask_p[18] << 4)
2094 | (mask_p[17] << 2) | (mask_p[16] << 0);
2095 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2096 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2097
f1dc5600
S		 2098 tmp_mask = (mask_p[45] << 28)
2099 | (mask_p[44] << 26) | (mask_p[43] << 24)
2100 | (mask_p[42] << 22) | (mask_p[41] << 20)
2101 | (mask_p[40] << 18) | (mask_p[39] << 16)
2102 | (mask_p[38] << 14) | (mask_p[37] << 12)
2103 | (mask_p[36] << 10) | (mask_p[35] << 8)
2104 | (mask_p[34] << 6) | (mask_p[33] << 4)
2105 | (mask_p[32] << 2) | (mask_p[31] << 0);
2106 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2107 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2108
f1dc5600
S		 2109 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2110 | (mask_p[59] << 26) | (mask_p[58] << 24)
2111 | (mask_p[57] << 22) | (mask_p[56] << 20)
2112 | (mask_p[55] << 18) | (mask_p[54] << 16)
2113 | (mask_p[53] << 14) | (mask_p[52] << 12)
2114 | (mask_p[51] << 10) | (mask_p[50] << 8)
2115 | (mask_p[49] << 6) | (mask_p[48] << 4)
2116 | (mask_p[47] << 2) | (mask_p[46] << 0);
2117 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2118 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2119}
2120
cbe61d8a 2121int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2122 bool bChannelChange)
f078f209 2123{
f078f209 2124 u32 saveLedState;
ae8d2858 2125 struct ath_softc *sc = ah->ah_sc;
2660b81a 2126 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2127 u32 saveDefAntenna;
2128 u32 macStaId1;
ae8d2858 2129 int i, rx_chainmask, r;
f078f209 2130
2660b81a
S		 2131 ah->extprotspacing = sc->ht_extprotspacing;
2132 ah->txchainmask = sc->tx_chainmask;
2133 ah->rxchainmask = sc->rx_chainmask;
f078f209 2134
793c5929 2135 if (AR_SREV_9285(ah)) {
2660b81a
S		 2136 ah->txchainmask &= 0x1;
2137 ah->rxchainmask &= 0x1;
793c5929 2138 } else if (AR_SREV_9280(ah)) {
2660b81a
S		 2139 ah->txchainmask &= 0x3;
2140 ah->rxchainmask &= 0x3;
f078f209
LR		 2141 }
2142
ae8d2858
LR		 2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2144 return -EIO;
f078f209
LR		 2145
2146 if (curchan)
2147 ath9k_hw_getnf(ah, curchan);
2148
2149 if (bChannelChange &&
2660b81a
S		 2150 (ah->chip_fullsleep != true) &&
2151 (ah->curchan != NULL) &&
2152 (chan->channel != ah->curchan->channel) &&
f078f209 2153 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2154 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
f078f209 2155 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2660b81a 2156 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
f078f209 2157
ae8d2858 2158 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2159 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2160 ath9k_hw_start_nfcal(ah);
ae8d2858 2161 return 0;
f078f209
LR		 2162 }
2163 }
2164
2165 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2166 if (saveDefAntenna == 0)
2167 saveDefAntenna = 1;
2168
2169 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2170
2171 saveLedState = REG_READ(ah, AR_CFG_LED) &
2172 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2173 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2174
2175 ath9k_hw_mark_phy_inactive(ah);
2176
2177 if (!ath9k_hw_chip_reset(ah, chan)) {
04bd4638 2178 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
ae8d2858 2179 return -EINVAL;
f078f209
LR		 2180 }
2181
369391db
VT		 2182 if (AR_SREV_9280_10_OR_LATER(ah))
2183 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2184
ae8d2858
LR		 2185 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2186 if (r)
2187 return r;
f078f209 2188
0ced0e17
JM		 2189 /* Setup MFP options for CCMP */
2190 if (AR_SREV_9280_20_OR_LATER(ah)) {
2191 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2192 * frames when constructing CCMP AAD. */
2193 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2194 0xc7ff);
2195 ah->sw_mgmt_crypto = false;
2196 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2197 /* Disable hardware crypto for management frames */
2198 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2199 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2200 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2201 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2202 ah->sw_mgmt_crypto = true;
2203 } else
2204 ah->sw_mgmt_crypto = true;
2205
f078f209
LR		 2206 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2207 ath9k_hw_set_delta_slope(ah, chan);
2208
2209 if (AR_SREV_9280_10_OR_LATER(ah))
2210 ath9k_hw_9280_spur_mitigate(ah, chan);
2211 else
2212 ath9k_hw_spur_mitigate(ah, chan);
2213
f74df6fb 2214 if (!ah->eep_ops->set_board_values(ah, chan)) {
f078f209 2215 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 2216 "error setting board options\n");
ae8d2858 2217 return -EIO;
f078f209
LR		 2218 }
2219
2220 ath9k_hw_decrease_chain_power(ah, chan);
2221
ba52da58
S		 2222 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2223 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
f078f209
LR		 2224 | macStaId1
2225 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2226 | (ah->config.
60b67f51 2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2228 | ah->sta_id1_defaults);
2229 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2230
ba52da58
S		 2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2232 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 2233
2234 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2235
ba52da58
S		 2236 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2237 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2238 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 2239
2240 REG_WRITE(ah, AR_ISR, ~0);
2241
2242 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2243
2244 if (AR_SREV_9280_10_OR_LATER(ah)) {
ae8d2858
LR		 2245 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2246 return -EIO;
f078f209 2247 } else {
ae8d2858
LR		 2248 if (!(ath9k_hw_set_channel(ah, chan)))
2249 return -EIO;
f078f209
LR		 2250 }
2251
2252 for (i = 0; i < AR_NUM_DCU; i++)
2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2254
2660b81a
S		 2255 ah->intr_txqs = 0;
2256 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2257 ath9k_hw_resettxqueue(ah, i);
2258
2660b81a 2259 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2260 ath9k_hw_init_qos(ah);
2261
e97275cb 2262#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2263 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 2264 ath9k_enable_rfkill(ah);
2265#endif
f078f209
LR		 2266 ath9k_hw_init_user_settings(ah);
2267
f078f209
LR		 2268 REG_WRITE(ah, AR_STA_ID1,
2269 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2270
2271 ath9k_hw_set_dma(ah);
2272
2273 REG_WRITE(ah, AR_OBS, 8);
2274
2660b81a 2275 if (ah->intr_mitigation) {
f078f209
LR		 2276
2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2279 }
2280
2281 ath9k_hw_init_bb(ah, chan);
2282
ae8d2858
LR		 2283 if (!ath9k_hw_init_cal(ah, chan))
2284 return -EIO;;
f078f209 2285
2660b81a 2286 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2290 }
2291
2292 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2293
2294 if (AR_SREV_9100(ah)) {
2295 u32 mask;
2296 mask = REG_READ(ah, AR_CFG);
2297 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2298 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2299 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2300 } else {
2301 mask =
2302 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2303 REG_WRITE(ah, AR_CFG, mask);
2304 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2305 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2306 }
2307 } else {
2308#ifdef __BIG_ENDIAN
2309 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2310#endif
2311 }
2312
ae8d2858 2313 return 0;
f078f209
LR		 2314}
2315
f1dc5600
S		 2316/************************/
2317/* Key Cache Management */
2318/************************/
f078f209 2319
cbe61d8a 2320bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2321{
f1dc5600 2322 u32 keyType;
f078f209 2323
2660b81a 2324 if (entry >= ah->caps.keycache_size) {
f1dc5600 2325 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2326 "entry %u out of range\n", entry);
f078f209
LR		 2327 return false;
2328 }
2329
f1dc5600 2330 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2331
f1dc5600
S		 2332 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2333 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2334 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2335 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2336 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2337 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2338 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2339 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2340
f1dc5600
S		 2341 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2342 u16 micentry = entry + 64;
f078f209 2343
f1dc5600
S		 2344 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2345 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2346 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2347 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2348
f078f209
LR		 2349 }
2350
2660b81a 2351 if (ah->curchan == NULL)
f1dc5600 2352 return true;
f078f209
LR		 2353
2354 return true;
2355}
2356
cbe61d8a 2357bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2358{
f1dc5600 2359 u32 macHi, macLo;
f078f209 2360
2660b81a 2361 if (entry >= ah->caps.keycache_size) {
f1dc5600 2362 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2363 "entry %u out of range\n", entry);
f1dc5600 2364 return false;
f078f209
LR		 2365 }
2366
f1dc5600
S		 2367 if (mac != NULL) {
2368 macHi = (mac[5] << 8) | mac[4];
2369 macLo = (mac[3] << 24) |
2370 (mac[2] << 16) |
2371 (mac[1] << 8) |
2372 mac[0];
2373 macLo >>= 1;
2374 macLo |= (macHi & 1) << 31;
2375 macHi >>= 1;
f078f209 2376 } else {
f1dc5600 2377 macLo = macHi = 0;
f078f209 2378 }
f1dc5600
S		 2379 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2380 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2381
f1dc5600 2382 return true;
f078f209
LR		 2383}
2384
cbe61d8a 2385bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600
S		 2386 const struct ath9k_keyval *k,
2387 const u8 *mac, int xorKey)
f078f209 2388{
2660b81a 2389 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2390 u32 key0, key1, key2, key3, key4;
2391 u32 keyType;
2392 u32 xorMask = xorKey ?
2393 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2394 | ATH9K_KEY_XOR) : 0;
f078f209 2395
f1dc5600
S		 2396 if (entry >= pCap->keycache_size) {
2397 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2398 "entry %u out of range\n", entry);
f1dc5600 2399 return false;
f078f209
LR		 2400 }
2401
f1dc5600
S		 2402 switch (k->kv_type) {
2403 case ATH9K_CIPHER_AES_OCB:
2404 keyType = AR_KEYTABLE_TYPE_AES;
2405 break;
2406 case ATH9K_CIPHER_AES_CCM:
2407 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2408 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2409 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2410 ah->hw_version.macRev);
f1dc5600
S		 2411 return false;
2412 }
2413 keyType = AR_KEYTABLE_TYPE_CCM;
2414 break;
2415 case ATH9K_CIPHER_TKIP:
2416 keyType = AR_KEYTABLE_TYPE_TKIP;
2417 if (ATH9K_IS_MIC_ENABLED(ah)
2418 && entry + 64 >= pCap->keycache_size) {
2419 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2420 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2421 return false;
2422 }
2423 break;
2424 case ATH9K_CIPHER_WEP:
2425 if (k->kv_len < LEN_WEP40) {
2426 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2427 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2428 return false;
2429 }
2430 if (k->kv_len <= LEN_WEP40)
2431 keyType = AR_KEYTABLE_TYPE_40;
2432 else if (k->kv_len <= LEN_WEP104)
2433 keyType = AR_KEYTABLE_TYPE_104;
2434 else
2435 keyType = AR_KEYTABLE_TYPE_128;
2436 break;
2437 case ATH9K_CIPHER_CLR:
2438 keyType = AR_KEYTABLE_TYPE_CLR;
2439 break;
2440 default:
2441 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2442 "cipher %u not supported\n", k->kv_type);
f1dc5600 2443 return false;
f078f209
LR		 2444 }
2445
f1dc5600
S		 2446 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2447 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2448 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2449 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2450 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2451 if (k->kv_len <= LEN_WEP104)
2452 key4 &= 0xff;
f078f209 2453
f1dc5600
S		 2454 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2455 u16 micentry = entry + 64;
f078f209 2456
f1dc5600
S		 2457 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2458 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2459 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2460 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2461 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2463 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2464
2660b81a 2465 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
f1dc5600 2466 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2467
f1dc5600
S		 2468 mic0 = get_unaligned_le32(k->kv_mic + 0);
2469 mic2 = get_unaligned_le32(k->kv_mic + 4);
2470 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2471 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2472 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2473 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2474 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2475 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2476 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2477 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2478 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2479 AR_KEYTABLE_TYPE_CLR);
f078f209 2480
f1dc5600
S		 2481 } else {
2482 u32 mic0, mic2;
f078f209 2483
f1dc5600
S		 2484 mic0 = get_unaligned_le32(k->kv_mic + 0);
2485 mic2 = get_unaligned_le32(k->kv_mic + 4);
2486 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2487 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2488 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2489 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2490 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2491 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2492 AR_KEYTABLE_TYPE_CLR);
2493 }
2494 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2495 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2496 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2497 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2498 } else {
2499 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2500 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2501 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2502 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2503 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2504 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2505
f1dc5600
S		 2506 (void) ath9k_hw_keysetmac(ah, entry, mac);
2507 }
f078f209 2508
2660b81a 2509 if (ah->curchan == NULL)
f1dc5600 2510 return true;
f078f209
LR		 2511
2512 return true;
2513}
2514
cbe61d8a 2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2516{
2660b81a 2517 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2519 if (val & AR_KEYTABLE_VALID)
2520 return true;
2521 }
2522 return false;
f078f209
LR		 2523}
2524
f1dc5600
S		 2525/******************************/
2526/* Power Management (Chipset) */
2527/******************************/
2528
cbe61d8a 2529static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2530{
f1dc5600
S		 2531 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2532 if (setChip) {
2533 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2534 AR_RTC_FORCE_WAKE_EN);
2535 if (!AR_SREV_9100(ah))
2536 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2537
d03a66c1 2538 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2539 AR_RTC_RESET_EN);
2540 }
f078f209
LR		 2541}
2542
cbe61d8a 2543static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2544{
f1dc5600
S		 2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2546 if (setChip) {
2660b81a 2547 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2548
f1dc5600
S		 2549 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2550 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2551 AR_RTC_FORCE_WAKE_ON_INT);
2552 } else {
2553 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2554 AR_RTC_FORCE_WAKE_EN);
f078f209 2555 }
f078f209 2556 }
f078f209
LR		 2557}
2558
cbe61d8a 2559static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2560{
f1dc5600
S		 2561 u32 val;
2562 int i;
f078f209 2563
f1dc5600
S		 2564 if (setChip) {
2565 if ((REG_READ(ah, AR_RTC_STATUS) &
2566 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2567 if (ath9k_hw_set_reset_reg(ah,
2568 ATH9K_RESET_POWER_ON) != true) {
2569 return false;
2570 }
2571 }
2572 if (AR_SREV_9100(ah))
2573 REG_SET_BIT(ah, AR_RTC_RESET,
2574 AR_RTC_RESET_EN);
f078f209 2575
f1dc5600
S		 2576 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2577 AR_RTC_FORCE_WAKE_EN);
2578 udelay(50);
f078f209 2579
f1dc5600
S		 2580 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2581 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2582 if (val == AR_RTC_STATUS_ON)
2583 break;
2584 udelay(50);
2585 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2586 AR_RTC_FORCE_WAKE_EN);
f078f209 2587 }
f1dc5600
S		 2588 if (i == 0) {
2589 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2590 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2591 return false;
f078f209 2592 }
f078f209
LR		 2593 }
2594
f1dc5600 2595 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2596
f1dc5600 2597 return true;
f078f209
LR		 2598}
2599
cbe61d8a 2600bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2601{
cbe61d8a 2602 int status = true, setChip = true;
f1dc5600
S		 2603 static const char *modes[] = {
2604 "AWAKE",
2605 "FULL-SLEEP",
2606 "NETWORK SLEEP",
2607 "UNDEFINED"
2608 };
f1dc5600 2609
04bd4638 2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2660b81a 2611 modes[ah->power_mode], modes[mode],
f1dc5600
S		 2612 setChip ? "set chip " : "");
2613
2614 switch (mode) {
2615 case ATH9K_PM_AWAKE:
2616 status = ath9k_hw_set_power_awake(ah, setChip);
2617 break;
2618 case ATH9K_PM_FULL_SLEEP:
2619 ath9k_set_power_sleep(ah, setChip);
2660b81a 2620 ah->chip_fullsleep = true;
f1dc5600
S		 2621 break;
2622 case ATH9K_PM_NETWORK_SLEEP:
2623 ath9k_set_power_network_sleep(ah, setChip);
2624 break;
f078f209 2625 default:
f1dc5600 2626 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2627 "Unknown power mode %u\n", mode);
f078f209
LR		 2628 return false;
2629 }
2660b81a 2630 ah->power_mode = mode;
f1dc5600
S		 2631
2632 return status;
f078f209
LR		 2633}
2634
cbe61d8a 2635void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
f078f209 2636{
f1dc5600 2637 u8 i;
f078f209 2638
2660b81a 2639 if (ah->is_pciexpress != true)
f1dc5600 2640 return;
f078f209 2641
2660b81a 2642 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2643 return;
2644
2645 if (restore)
2646 return;
2647
2648 if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a
S		 2649 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2650 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2651 INI_RA(&ah->iniPcieSerdes, i, 1));
f078f209 2652 }
f1dc5600
S		 2653 udelay(1000);
2654 } else if (AR_SREV_9280(ah) &&
d535a42a 2655 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
f1dc5600
S		 2656 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2657 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2658
2659 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2660 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2661 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2662
2660b81a 2663 if (ah->config.pcie_clock_req)
f1dc5600
S		 2664 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2665 else
2666 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2667
2668 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2669 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2670 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2671
2672 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2673
2674 udelay(1000);
2675 } else {
2676 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2677 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2678 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2679 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2680 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2681 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2682 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2683 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2684 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2685 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 2686 }
2687
f1dc5600
S		 2688 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2689
2660b81a
S		 2690 if (ah->config.pcie_waen) {
2691 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
f1dc5600 2692 } else {
e7594072
SB		 2693 if (AR_SREV_9285(ah))
2694 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2695 else if (AR_SREV_9280(ah))
2696 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 2697 else
e7594072 2698 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 2699 }
f078f209
LR		 2700}
2701
f1dc5600
S		 2702/**********************/
2703/* Interrupt Handling */
2704/**********************/
2705
cbe61d8a 2706bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 2707{
2708 u32 host_isr;
2709
2710 if (AR_SREV_9100(ah))
2711 return true;
2712
2713 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2714 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2715 return true;
2716
2717 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2718 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2719 && (host_isr != AR_INTR_SPURIOUS))
2720 return true;
2721
2722 return false;
2723}
2724
cbe61d8a 2725bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 2726{
2727 u32 isr = 0;
2728 u32 mask2 = 0;
2660b81a 2729 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 2730 u32 sync_cause = 0;
2731 bool fatal_int = false;
2732
2733 if (!AR_SREV_9100(ah)) {
2734 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2735 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2736 == AR_RTC_STATUS_ON) {
2737 isr = REG_READ(ah, AR_ISR);
2738 }
2739 }
2740
f1dc5600
S		 2741 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2742 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2743
2744 *masked = 0;
2745
2746 if (!isr && !sync_cause)
2747 return false;
2748 } else {
2749 *masked = 0;
2750 isr = REG_READ(ah, AR_ISR);
2751 }
2752
2753 if (isr) {
f078f209
LR		 2754 if (isr & AR_ISR_BCNMISC) {
2755 u32 isr2;
2756 isr2 = REG_READ(ah, AR_ISR_S2);
2757 if (isr2 & AR_ISR_S2_TIM)
2758 mask2 |= ATH9K_INT_TIM;
2759 if (isr2 & AR_ISR_S2_DTIM)
2760 mask2 |= ATH9K_INT_DTIM;
2761 if (isr2 & AR_ISR_S2_DTIMSYNC)
2762 mask2 |= ATH9K_INT_DTIMSYNC;
2763 if (isr2 & (AR_ISR_S2_CABEND))
2764 mask2 |= ATH9K_INT_CABEND;
2765 if (isr2 & AR_ISR_S2_GTT)
2766 mask2 |= ATH9K_INT_GTT;
2767 if (isr2 & AR_ISR_S2_CST)
2768 mask2 |= ATH9K_INT_CST;
2769 }
2770
2771 isr = REG_READ(ah, AR_ISR_RAC);
2772 if (isr == 0xffffffff) {
2773 *masked = 0;
2774 return false;
2775 }
2776
2777 *masked = isr & ATH9K_INT_COMMON;
2778
2660b81a 2779 if (ah->intr_mitigation) {
f078f209
LR		 2780 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2781 *masked |= ATH9K_INT_RX;
2782 }
2783
2784 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2785 *masked |= ATH9K_INT_RX;
2786 if (isr &
2787 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2788 AR_ISR_TXEOL)) {
2789 u32 s0_s, s1_s;
2790
2791 *masked |= ATH9K_INT_TX;
2792
2793 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 2794 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2795 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 2796
2797 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 2798 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2799 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 2800 }
2801
2802 if (isr & AR_ISR_RXORN) {
2803 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2804 "receive FIFO overrun interrupt\n");
f078f209
LR		 2805 }
2806
2807 if (!AR_SREV_9100(ah)) {
60b67f51 2808 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2809 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2810 if (isr5 & AR_ISR_S5_TIM_TIMER)
2811 *masked |= ATH9K_INT_TIM_TIMER;
2812 }
2813 }
2814
2815 *masked |= mask2;
2816 }
f1dc5600 2817
f078f209
LR		 2818 if (AR_SREV_9100(ah))
2819 return true;
f1dc5600 2820
f078f209
LR		 2821 if (sync_cause) {
2822 fatal_int =
2823 (sync_cause &
2824 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2825 ? true : false;
2826
2827 if (fatal_int) {
2828 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2829 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2830 "received PCI FATAL interrupt\n");
f078f209
LR		 2831 }
2832 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2833 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2834 "received PCI PERR interrupt\n");
f078f209
LR		 2835 }
2836 }
2837 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2838 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2839 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2840 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2841 REG_WRITE(ah, AR_RC, 0);
2842 *masked |= ATH9K_INT_FATAL;
2843 }
2844 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2845 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2846 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2847 }
2848
2849 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2850 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2851 }
f1dc5600 2852
f078f209
LR		 2853 return true;
2854}
2855
cbe61d8a 2856enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
f078f209 2857{
2660b81a 2858 return ah->mask_reg;
f078f209
LR		 2859}
2860
cbe61d8a 2861enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2862{
2660b81a 2863 u32 omask = ah->mask_reg;
f078f209 2864 u32 mask, mask2;
2660b81a 2865 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2866
04bd4638 2867 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2868
2869 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 2870 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2871 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2872 (void) REG_READ(ah, AR_IER);
2873 if (!AR_SREV_9100(ah)) {
2874 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2875 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2876
2877 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2878 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2879 }
2880 }
2881
2882 mask = ints & ATH9K_INT_COMMON;
2883 mask2 = 0;
2884
2885 if (ints & ATH9K_INT_TX) {
2660b81a 2886 if (ah->txok_interrupt_mask)
f078f209 2887 mask |= AR_IMR_TXOK;
2660b81a 2888 if (ah->txdesc_interrupt_mask)
f078f209 2889 mask |= AR_IMR_TXDESC;
2660b81a 2890 if (ah->txerr_interrupt_mask)
f078f209 2891 mask |= AR_IMR_TXERR;
2660b81a 2892 if (ah->txeol_interrupt_mask)
f078f209
LR		 2893 mask |= AR_IMR_TXEOL;
2894 }
2895 if (ints & ATH9K_INT_RX) {
2896 mask |= AR_IMR_RXERR;
2660b81a 2897 if (ah->intr_mitigation)
f078f209
LR		 2898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2899 else
2900 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2901 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2902 mask |= AR_IMR_GENTMR;
2903 }
2904
2905 if (ints & (ATH9K_INT_BMISC)) {
2906 mask |= AR_IMR_BCNMISC;
2907 if (ints & ATH9K_INT_TIM)
2908 mask2 |= AR_IMR_S2_TIM;
2909 if (ints & ATH9K_INT_DTIM)
2910 mask2 |= AR_IMR_S2_DTIM;
2911 if (ints & ATH9K_INT_DTIMSYNC)
2912 mask2 |= AR_IMR_S2_DTIMSYNC;
2913 if (ints & ATH9K_INT_CABEND)
2914 mask2 |= (AR_IMR_S2_CABEND);
2915 }
2916
2917 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2918 mask |= AR_IMR_BCNMISC;
2919 if (ints & ATH9K_INT_GTT)
2920 mask2 |= AR_IMR_S2_GTT;
2921 if (ints & ATH9K_INT_CST)
2922 mask2 |= AR_IMR_S2_CST;
2923 }
2924
04bd4638 2925 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 2926 REG_WRITE(ah, AR_IMR, mask);
2927 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2928 AR_IMR_S2_DTIM |
2929 AR_IMR_S2_DTIMSYNC |
2930 AR_IMR_S2_CABEND |
2931 AR_IMR_S2_CABTO |
2932 AR_IMR_S2_TSFOOR |
2933 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2934 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 2935 ah->mask_reg = ints;
f078f209 2936
60b67f51 2937 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2938 if (ints & ATH9K_INT_TIM_TIMER)
2939 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2940 else
2941 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2942 }
2943
2944 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 2945 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2946 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2947 if (!AR_SREV_9100(ah)) {
2948 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2949 AR_INTR_MAC_IRQ);
2950 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2951
2952
2953 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2954 AR_INTR_SYNC_DEFAULT);
2955 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2956 AR_INTR_SYNC_DEFAULT);
2957 }
2958 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2959 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2960 }
2961
2962 return omask;
2963}
2964
f1dc5600
S		 2965/*******************/
2966/* Beacon Handling */
2967/*******************/
2968
cbe61d8a 2969void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2970{
f078f209
LR		 2971 int flags = 0;
2972
2660b81a 2973 ah->beacon_interval = beacon_period;
f078f209 2974
2660b81a 2975 switch (ah->opmode) {
d97809db
CM		 2976 case NL80211_IFTYPE_STATION:
2977 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2979 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2980 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2981 flags |= AR_TBTT_TIMER_EN;
2982 break;
d97809db 2983 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2984 REG_SET_BIT(ah, AR_TXCFG,
2985 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2986 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2987 TU_TO_USEC(next_beacon +
2660b81a
S		 2988 (ah->atim_window ? ah->
2989 atim_window : 1)));
f078f209 2990 flags |= AR_NDP_TIMER_EN;
d97809db 2991 case NL80211_IFTYPE_AP:
f078f209
LR		 2992 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2993 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2994 TU_TO_USEC(next_beacon -
2660b81a 2995 ah->config.
60b67f51 2996 dma_beacon_response_time));
f078f209
LR		 2997 REG_WRITE(ah, AR_NEXT_SWBA,
2998 TU_TO_USEC(next_beacon -
2660b81a 2999 ah->config.
60b67f51 3000 sw_beacon_response_time));
f078f209
LR		 3001 flags |=
3002 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3003 break;
d97809db
CM		 3004 default:
3005 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3006 "%s: unsupported opmode: %d\n",
2660b81a 3007 __func__, ah->opmode);
d97809db
CM		 3008 return;
3009 break;
f078f209
LR		 3010 }
3011
3012 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3013 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3014 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3015 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3016
3017 beacon_period &= ~ATH9K_BEACON_ENA;
3018 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3019 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3020 ath9k_hw_reset_tsf(ah);
3021 }
3022
3023 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3024}
3025
cbe61d8a 3026void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3027 const struct ath9k_beacon_state *bs)
f078f209
LR		 3028{
3029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3030 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3031
3032 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3033
3034 REG_WRITE(ah, AR_BEACON_PERIOD,
3035 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3036 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3037 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3038
3039 REG_RMW_FIELD(ah, AR_RSSI_THR,
3040 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3041
3042 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3043
3044 if (bs->bs_sleepduration > beaconintval)
3045 beaconintval = bs->bs_sleepduration;
3046
3047 dtimperiod = bs->bs_dtimperiod;
3048 if (bs->bs_sleepduration > dtimperiod)
3049 dtimperiod = bs->bs_sleepduration;
3050
3051 if (beaconintval == dtimperiod)
3052 nextTbtt = bs->bs_nextdtim;
3053 else
3054 nextTbtt = bs->bs_nexttbtt;
3055
04bd4638
S		 3056 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3057 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3058 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3059 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3060
f1dc5600
S		 3061 REG_WRITE(ah, AR_NEXT_DTIM,
3062 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3063 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3064
f1dc5600
S		 3065 REG_WRITE(ah, AR_SLEEP1,
3066 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3067 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3068
f1dc5600
S		 3069 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3070 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3071 else
3072 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3073
f1dc5600
S		 3074 REG_WRITE(ah, AR_SLEEP2,
3075 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3076
f1dc5600
S		 3077 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3078 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3079
f1dc5600
S		 3080 REG_SET_BIT(ah, AR_TIMER_MODE,
3081 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3082 AR_DTIM_TIMER_EN);
f078f209 3083
f078f209
LR		 3084}
3085
f1dc5600
S		 3086/*******************/
3087/* HW Capabilities */
3088/*******************/
3089
cbe61d8a 3090bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3091{
2660b81a 3092 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600 3093 u16 capField = 0, eeval;
f078f209 3094
f74df6fb 3095 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
f078f209 3096
d6bad496 3097 ah->regulatory.current_rd = eeval;
f078f209 3098
f74df6fb 3099 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
d6bad496 3100 ah->regulatory.current_rd_ext = eeval;
f078f209 3101
f74df6fb 3102 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3103
2660b81a 3104 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3105 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
d6bad496
S		 3106 if (ah->regulatory.current_rd == 0x64 ||
3107 ah->regulatory.current_rd == 0x65)
3108 ah->regulatory.current_rd += 5;
3109 else if (ah->regulatory.current_rd == 0x41)
3110 ah->regulatory.current_rd = 0x43;
f1dc5600 3111 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
d6bad496 3112 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
f1dc5600 3113 }
f078f209 3114
f74df6fb 3115 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3116 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3117
f1dc5600
S		 3118 if (eeval & AR5416_OPFLAGS_11A) {
3119 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3120 if (ah->config.ht_enable) {
f1dc5600
S		 3121 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3122 set_bit(ATH9K_MODE_11NA_HT20,
3123 pCap->wireless_modes);
3124 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3125 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3126 pCap->wireless_modes);
3127 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3128 pCap->wireless_modes);
3129 }
f078f209 3130 }
f078f209
LR		 3131 }
3132
f1dc5600
S		 3133 if (eeval & AR5416_OPFLAGS_11G) {
3134 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3135 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3136 if (ah->config.ht_enable) {
f1dc5600
S		 3137 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3138 set_bit(ATH9K_MODE_11NG_HT20,
3139 pCap->wireless_modes);
3140 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3141 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3142 pCap->wireless_modes);
3143 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3144 pCap->wireless_modes);
3145 }
3146 }
f078f209 3147 }
f1dc5600 3148
f74df6fb 3149 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2660b81a 3150 if ((ah->is_pciexpress)
f1dc5600
S		 3151 || (eeval & AR5416_OPFLAGS_11A)) {
3152 pCap->rx_chainmask =
f74df6fb 3153 ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3154 } else {
f1dc5600
S		 3155 pCap->rx_chainmask =
3156 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
f078f209
LR		 3157 }
3158
d535a42a 3159 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3160 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3161
f1dc5600
S		 3162 pCap->low_2ghz_chan = 2312;
3163 pCap->high_2ghz_chan = 2732;
f078f209 3164
f1dc5600
S		 3165 pCap->low_5ghz_chan = 4920;
3166 pCap->high_5ghz_chan = 6100;
f078f209 3167
f1dc5600
S		 3168 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3169 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3170 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3171
f1dc5600
S		 3172 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3173 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3174 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3175
f1dc5600 3176 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
f078f209 3177
2660b81a 3178 if (ah->config.ht_enable)
f1dc5600
S		 3179 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3180 else
3181 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3182
f1dc5600
S		 3183 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3184 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3185 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3186 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3187
f1dc5600
S		 3188 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3189 pCap->total_queues =
3190 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3191 else
3192 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3193
f1dc5600
S		 3194 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3195 pCap->keycache_size =
3196 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3197 else
3198 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3199
f1dc5600
S		 3200 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3201 pCap->num_mr_retries = 4;
3202 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3203
cb33c412
SB		 3204 if (AR_SREV_9285_10_OR_LATER(ah))
3205 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3206 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3207 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3208 else
3209 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3210
f1dc5600
S		 3211 if (AR_SREV_9280_10_OR_LATER(ah)) {
3212 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3213 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3214 } else {
3215 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3216 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
f078f209
LR		 3217 }
3218
f1dc5600
S		 3219 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3220 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3221 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3222 } else {
3223 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3224 }
3225
f1dc5600
S		 3226 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3227
e97275cb 3228#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3229 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3230 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3231 ah->rfkill_gpio =
3232 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3233 ah->rfkill_polarity =
3234 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3235
3236 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3237 }
f1dc5600 3238#endif
f078f209 3239
d535a42a
S		 3240 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3241 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3242 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3243 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3244 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
f1dc5600 3245 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3246 else
f1dc5600 3247 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3248
e7594072 3249 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3250 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3251 else
3252 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3253
d6bad496 3254 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3255 pCap->reg_cap =
3256 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3257 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3258 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3259 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3260 } else {
f1dc5600
S		 3261 pCap->reg_cap =
3262 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3263 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3264 }
f078f209 3265
f1dc5600
S		 3266 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3267
3268 pCap->num_antcfg_5ghz =
f74df6fb 3269 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3270 pCap->num_antcfg_2ghz =
f74df6fb 3271 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3272
138ab2e4 3273 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
c97c92d9 3274 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
2660b81a
S		 3275 ah->btactive_gpio = 6;
3276 ah->wlanactive_gpio = 5;
c97c92d9
VT		 3277 }
3278
f1dc5600 3279 return true;
f078f209
LR		 3280}
3281
cbe61d8a 3282bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3283 u32 capability, u32 *result)
f078f209 3284{
2660b81a 3285 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3286
f1dc5600
S		 3287 switch (type) {
3288 case ATH9K_CAP_CIPHER:
3289 switch (capability) {
3290 case ATH9K_CIPHER_AES_CCM:
3291 case ATH9K_CIPHER_AES_OCB:
3292 case ATH9K_CIPHER_TKIP:
3293 case ATH9K_CIPHER_WEP:
3294 case ATH9K_CIPHER_MIC:
3295 case ATH9K_CIPHER_CLR:
3296 return true;
3297 default:
3298 return false;
3299 }
3300 case ATH9K_CAP_TKIP_MIC:
3301 switch (capability) {
3302 case 0:
3303 return true;
3304 case 1:
2660b81a 3305 return (ah->sta_id1_defaults &
f1dc5600
S		 3306 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3307 false;
3308 }
3309 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3310 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600
S		 3311 false : true;
3312 case ATH9K_CAP_WME_TKIPMIC:
3313 return 0;
3314 case ATH9K_CAP_PHYCOUNTERS:
2660b81a 3315 return ah->has_hw_phycounters ? 0 : -ENXIO;
f1dc5600
S		 3316 case ATH9K_CAP_DIVERSITY:
3317 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3318 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3319 true : false;
3320 case ATH9K_CAP_PHYDIAG:
3321 return true;
3322 case ATH9K_CAP_MCAST_KEYSRCH:
3323 switch (capability) {
3324 case 0:
3325 return true;
3326 case 1:
3327 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3328 return false;
3329 } else {
2660b81a 3330 return (ah->sta_id1_defaults &
f1dc5600
S		 3331 AR_STA_ID1_MCAST_KSRCH) ? true :
3332 false;
3333 }
3334 }
3335 return false;
3336 case ATH9K_CAP_TSF_ADJUST:
2660b81a 3337 return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ?
f1dc5600
S		 3338 true : false;
3339 case ATH9K_CAP_RFSILENT:
3340 if (capability == 3)
3341 return false;
3342 case ATH9K_CAP_ANT_CFG_2GHZ:
3343 *result = pCap->num_antcfg_2ghz;
3344 return true;
3345 case ATH9K_CAP_ANT_CFG_5GHZ:
3346 *result = pCap->num_antcfg_5ghz;
3347 return true;
3348 case ATH9K_CAP_TXPOW:
3349 switch (capability) {
3350 case 0:
3351 return 0;
3352 case 1:
d6bad496 3353 *result = ah->regulatory.power_limit;
f1dc5600
S		 3354 return 0;
3355 case 2:
d6bad496 3356 *result = ah->regulatory.max_power_level;
f1dc5600
S		 3357 return 0;
3358 case 3:
d6bad496 3359 *result = ah->regulatory.tp_scale;
f1dc5600
S		 3360 return 0;
3361 }
3362 return false;
3363 default:
3364 return false;
f078f209 3365 }
f078f209
LR		 3366}
3367
cbe61d8a 3368bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3369 u32 capability, u32 setting, int *status)
f078f209 3370{
f1dc5600 3371 u32 v;
f078f209 3372
f1dc5600
S		 3373 switch (type) {
3374 case ATH9K_CAP_TKIP_MIC:
3375 if (setting)
2660b81a 3376 ah->sta_id1_defaults |=
f1dc5600
S		 3377 AR_STA_ID1_CRPT_MIC_ENABLE;
3378 else
2660b81a 3379 ah->sta_id1_defaults &=
f1dc5600
S		 3380 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381 return true;
3382 case ATH9K_CAP_DIVERSITY:
3383 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3384 if (setting)
3385 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3386 else
3387 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3388 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3389 return true;
3390 case ATH9K_CAP_MCAST_KEYSRCH:
3391 if (setting)
2660b81a 3392 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3393 else
2660b81a 3394 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600
S		 3395 return true;
3396 case ATH9K_CAP_TSF_ADJUST:
3397 if (setting)
2660b81a 3398 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3399 else
2660b81a 3400 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600
S		 3401 return true;
3402 default:
3403 return false;
f078f209
LR		 3404 }
3405}
3406
f1dc5600
S		 3407/****************************/
3408/* GPIO / RFKILL / Antennae */
3409/****************************/
f078f209 3410
cbe61d8a 3411static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3412 u32 gpio, u32 type)
3413{
3414 int addr;
3415 u32 gpio_shift, tmp;
f078f209 3416
f1dc5600
S		 3417 if (gpio > 11)
3418 addr = AR_GPIO_OUTPUT_MUX3;
3419 else if (gpio > 5)
3420 addr = AR_GPIO_OUTPUT_MUX2;
3421 else
3422 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3423
f1dc5600 3424 gpio_shift = (gpio % 6) * 5;
f078f209 3425
f1dc5600
S		 3426 if (AR_SREV_9280_20_OR_LATER(ah)
3427 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3428 REG_RMW(ah, addr, (type << gpio_shift),
3429 (0x1f << gpio_shift));
f078f209 3430 } else {
f1dc5600
S		 3431 tmp = REG_READ(ah, addr);
3432 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3433 tmp &= ~(0x1f << gpio_shift);
3434 tmp |= (type << gpio_shift);
3435 REG_WRITE(ah, addr, tmp);
f078f209 3436 }
f078f209
LR		 3437}
3438
cbe61d8a 3439void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3440{
f1dc5600 3441 u32 gpio_shift;
f078f209 3442
2660b81a 3443 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3444
f1dc5600 3445 gpio_shift = gpio << 1;
f078f209 3446
f1dc5600
S		 3447 REG_RMW(ah,
3448 AR_GPIO_OE_OUT,
3449 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3450 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3451}
3452
cbe61d8a 3453u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3454{
cb33c412
SB		 3455#define MS_REG_READ(x, y) \
3456 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3457
2660b81a 3458 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3459 return 0xffffffff;
f078f209 3460
cb33c412
SB		 3461 if (AR_SREV_9285_10_OR_LATER(ah))
3462 return MS_REG_READ(AR9285, gpio) != 0;
3463 else if (AR_SREV_9280_10_OR_LATER(ah))
3464 return MS_REG_READ(AR928X, gpio) != 0;
3465 else
3466 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3467}
3468
cbe61d8a 3469void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3470 u32 ah_signal_type)
f078f209 3471{
f1dc5600 3472 u32 gpio_shift;
f078f209 3473
f1dc5600 3474 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3475
f1dc5600 3476 gpio_shift = 2 * gpio;
f078f209 3477
f1dc5600
S		 3478 REG_RMW(ah,
3479 AR_GPIO_OE_OUT,
3480 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3481 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3482}
3483
cbe61d8a 3484void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3485{
f1dc5600
S		 3486 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3487 AR_GPIO_BIT(gpio));
f078f209
LR		 3488}
3489
e97275cb 3490#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
cbe61d8a 3491void ath9k_enable_rfkill(struct ath_hw *ah)
f078f209 3492{
f1dc5600
S		 3493 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3494 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
f078f209 3495
f1dc5600
S		 3496 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3497 AR_GPIO_INPUT_MUX2_RFSILENT);
3498
2660b81a 3499 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
f1dc5600 3500 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
f078f209 3501}
f1dc5600 3502#endif
f078f209 3503
cbe61d8a 3504u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3505{
f1dc5600 3506 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3507}
3508
cbe61d8a 3509void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3510{
f1dc5600 3511 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3512}
3513
cbe61d8a 3514bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3515 enum ath9k_ant_setting settings,
3516 struct ath9k_channel *chan,
3517 u8 *tx_chainmask,
3518 u8 *rx_chainmask,
3519 u8 *antenna_cfgd)
f078f209 3520{
f1dc5600 3521 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3522
f1dc5600
S		 3523 if (AR_SREV_9280(ah)) {
3524 if (!tx_chainmask_cfg) {
f078f209 3525
f1dc5600
S		 3526 tx_chainmask_cfg = *tx_chainmask;
3527 rx_chainmask_cfg = *rx_chainmask;
3528 }
f078f209 3529
f1dc5600
S		 3530 switch (settings) {
3531 case ATH9K_ANT_FIXED_A:
3532 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3533 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3534 *antenna_cfgd = true;
3535 break;
3536 case ATH9K_ANT_FIXED_B:
2660b81a 3537 if (ah->caps.tx_chainmask >
f1dc5600
S		 3538 ATH9K_ANTENNA1_CHAINMASK) {
3539 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3540 }
3541 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3542 *antenna_cfgd = true;
3543 break;
3544 case ATH9K_ANT_VARIABLE:
3545 *tx_chainmask = tx_chainmask_cfg;
3546 *rx_chainmask = rx_chainmask_cfg;
3547 *antenna_cfgd = true;
3548 break;
3549 default:
3550 break;
3551 }
3552 } else {
2660b81a 3553 ah->diversity_control = settings;
f078f209 3554 }
f078f209 3555
f1dc5600 3556 return true;
f078f209
LR		 3557}
3558
f1dc5600
S		 3559/*********************/
3560/* General Operation */
3561/*********************/
3562
cbe61d8a 3563u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3564{
f1dc5600
S		 3565 u32 bits = REG_READ(ah, AR_RX_FILTER);
3566 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3567
f1dc5600
S		 3568 if (phybits & AR_PHY_ERR_RADAR)
3569 bits |= ATH9K_RX_FILTER_PHYRADAR;
3570 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3571 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3572
f1dc5600 3573 return bits;
f078f209
LR		 3574}
3575
cbe61d8a 3576void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3577{
f1dc5600 3578 u32 phybits;
f078f209 3579
f1dc5600
S		 3580 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3581 phybits = 0;
3582 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3583 phybits |= AR_PHY_ERR_RADAR;
3584 if (bits & ATH9K_RX_FILTER_PHYERR)
3585 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3586 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3587
f1dc5600
S		 3588 if (phybits)
3589 REG_WRITE(ah, AR_RXCFG,
3590 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3591 else
3592 REG_WRITE(ah, AR_RXCFG,
3593 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3594}
f078f209 3595
cbe61d8a 3596bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3597{
3598 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3599}
f078f209 3600
cbe61d8a 3601bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600
S		 3602{
3603 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3604 return false;
f078f209 3605
f1dc5600 3606 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3607}
3608
cbe61d8a 3609bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3610{
2660b81a 3611 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3612 struct ieee80211_channel *channel = chan->chan;
f078f209 3613
d6bad496 3614 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3615
f74df6fb
S		 3616 if (ah->eep_ops->set_txpower(ah, chan,
3617 ath9k_regd_get_ctl(ah, chan),
3618 channel->max_antenna_gain * 2,
3619 channel->max_power * 2,
3620 min((u32) MAX_RATE_POWER,
3621 (u32) ah->regulatory.power_limit)) != 0)
6f255425 3622 return false;
f1dc5600 3623
6f255425
LR		 3624 return true;
3625}
3626
cbe61d8a 3627void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3628{
ba52da58 3629 memcpy(ah->macaddr, mac, ETH_ALEN);
f078f209
LR		 3630}
3631
cbe61d8a 3632void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3633{
2660b81a 3634 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 3635}
3636
cbe61d8a 3637void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3638{
f1dc5600
S		 3639 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3640 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3641}
3642
ba52da58 3643void ath9k_hw_setbssidmask(struct ath_softc *sc)
f078f209 3644{
ba52da58
S		 3645 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3646 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 3647}
3648
ba52da58 3649void ath9k_hw_write_associd(struct ath_softc *sc)
f078f209 3650{
ba52da58
S		 3651 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3652 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3653 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 3654}
3655
cbe61d8a 3656u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3657{
f1dc5600 3658 u64 tsf;
f078f209 3659
f1dc5600
S		 3660 tsf = REG_READ(ah, AR_TSF_U32);
3661 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3662
f1dc5600
S		 3663 return tsf;
3664}
f078f209 3665
cbe61d8a 3666void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060
AF		 3667{
3668 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3669 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3670 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3671}
3672
cbe61d8a 3673void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600
S		 3674{
3675 int count;
f078f209 3676
f1dc5600
S		 3677 count = 0;
3678 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3679 count++;
3680 if (count > 10) {
3681 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 3682 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f1dc5600 3683 break;
f078f209 3684 }
f1dc5600
S		 3685 udelay(10);
3686 }
3687 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3688}
f078f209 3689
cbe61d8a 3690bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 3691{
f1dc5600 3692 if (setting)
2660b81a 3693 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3694 else
2660b81a 3695 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f078f209 3696
f1dc5600
S		 3697 return true;
3698}
f078f209 3699
cbe61d8a 3700bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 3701{
f1dc5600 3702 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 3703 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 3704 ah->slottime = (u32) -1;
f1dc5600
S		 3705 return false;
3706 } else {
3707 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 3708 ah->slottime = us;
f1dc5600 3709 return true;
f078f209 3710 }
f1dc5600
S		 3711}
3712
cbe61d8a 3713void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 3714{
3715 u32 macmode;
3716
3717 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 3718 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3719 macmode = AR_2040_JOINED_RX_CLEAR;
3720 else
3721 macmode = 0;
f078f209 3722
f1dc5600 3723 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3724}
c97c92d9
VT		 3725
3726/***************************/
3727/* Bluetooth Coexistence */
3728/***************************/
3729
cbe61d8a 3730void ath9k_hw_btcoex_enable(struct ath_hw *ah)
c97c92d9
VT		 3731{
3732 /* connect bt_active to baseband */
3733 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3734 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3735 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3736
3737 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3738 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3739
3740 /* Set input mux for bt_active to gpio pin */
3741 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3742 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2660b81a 3743 ah->btactive_gpio);
c97c92d9
VT		 3744
3745 /* Configure the desired gpio port for input */
2660b81a 3746 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
c97c92d9
VT		 3747
3748 /* Configure the desired GPIO port for TX_FRAME output */
2660b81a 3749 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
c97c92d9
VT		 3750 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3751}
Linux kernel - Deliverables
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