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ath9k: Add a debugfs file to show interrupt statistics
[deliverable/linux.git] / drivers / net / wireless / ath9k / hw.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
20#include "core.h"
21#include "hw.h"
22#include "reg.h"
23#include "phy.h"
24#include "initvals.h"
25
f078f209 26static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
f078f209 27
f1dc5600
S		 28extern struct hal_percal_data iq_cal_multi_sample;
29extern struct hal_percal_data iq_cal_single_sample;
30extern struct hal_percal_data adc_gain_cal_multi_sample;
31extern struct hal_percal_data adc_gain_cal_single_sample;
32extern struct hal_percal_data adc_dc_cal_multi_sample;
33extern struct hal_percal_data adc_dc_cal_single_sample;
34extern struct hal_percal_data adc_init_dc_cal;
f078f209 35
f1dc5600
S		 36static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode);
39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom *pEepData,
41 u32 reg, u32 value);
42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
f078f209 44
f1dc5600
S		 45/********************/
46/* Helper Functions */
47/********************/
f078f209 48
f1dc5600
S		 49static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
50{
51 if (ah->ah_curchan != NULL)
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
53 else
54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
55}
f078f209 56
f1dc5600
S		 57static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58{
59 struct ath9k_channel *chan = ah->ah_curchan;
f078f209 60
f1dc5600
S		 61 if (chan && IS_CHAN_HT40(chan))
62 return ath9k_hw_mac_usec(ah, clks) / 2;
63 else
64 return ath9k_hw_mac_usec(ah, clks);
65}
f078f209 66
f1dc5600
S		 67static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
68{
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
71 ah->ah_curchan)];
72 else
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
74}
75
76static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77{
78 struct ath9k_channel *chan = ah->ah_curchan;
79
80 if (chan && IS_CHAN_HT40(chan))
81 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else
83 return ath9k_hw_mac_clks(ah, usecs);
84}
f078f209 85
f1dc5600
S		 86enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
f078f209 88{
788a3d6f
S		 89 if (IS_CHAN_B(chan))
90 return ATH9K_MODE_11B;
f078f209 91 if (IS_CHAN_G(chan))
86b89eed 92 return ATH9K_MODE_11G;
788a3d6f 93
86b89eed 94 return ATH9K_MODE_11A;
f078f209
LR		 95}
96
f1dc5600 97bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
f078f209
LR		 98{
99 int i;
100
101 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
102 if ((REG_READ(ah, reg) & mask) == val)
103 return true;
104
105 udelay(AH_TIME_QUANTUM);
106 }
04bd4638
S		 107
108 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
109 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
110 reg, REG_READ(ah, reg), mask, val);
f078f209 111
f1dc5600 112 return false;
f078f209
LR		 113}
114
115u32 ath9k_hw_reverse_bits(u32 val, u32 n)
116{
117 u32 retval;
118 int i;
119
120 for (i = 0, retval = 0; i < n; i++) {
121 retval = (retval << 1) | (val & 1);
122 val >>= 1;
123 }
124 return retval;
125}
126
f1dc5600
S		 127bool ath9k_get_channel_edges(struct ath_hal *ah,
128 u16 flags, u16 *low,
129 u16 *high)
f078f209 130{
f1dc5600 131 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 132
f1dc5600
S		 133 if (flags & CHANNEL_5GHZ) {
134 *low = pCap->low_5ghz_chan;
135 *high = pCap->high_5ghz_chan;
136 return true;
f078f209 137 }
f1dc5600
S		 138 if ((flags & CHANNEL_2GHZ)) {
139 *low = pCap->low_2ghz_chan;
140 *high = pCap->high_2ghz_chan;
141 return true;
142 }
143 return false;
f078f209
LR		 144}
145
f1dc5600 146u16 ath9k_hw_computetxtime(struct ath_hal *ah,
e63835b0 147 struct ath_rate_table *rates,
f1dc5600
S		 148 u32 frameLen, u16 rateix,
149 bool shortPreamble)
f078f209 150{
f1dc5600
S		 151 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
152 u32 kbps;
f078f209 153
e63835b0 154 kbps = rates->info[rateix].ratekbps;
f078f209 155
f1dc5600
S		 156 if (kbps == 0)
157 return 0;
f078f209 158
f1dc5600 159 switch (rates->info[rateix].phy) {
46d14a58 160 case WLAN_RC_PHY_CCK:
f1dc5600 161 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 162 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 163 phyTime >>= 1;
164 numBits = frameLen << 3;
165 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
166 break;
46d14a58 167 case WLAN_RC_PHY_OFDM:
f1dc5600
S		 168 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_QUARTER
173 + OFDM_PREAMBLE_TIME_QUARTER
174 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
175 } else if (ah->ah_curchan &&
176 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_HALF +
181 OFDM_PREAMBLE_TIME_HALF
182 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
183 } else {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
188 + (numSymbols * OFDM_SYMBOL_TIME);
189 }
190 break;
191 default:
04bd4638
S		 192 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
193 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 194 rates->info[rateix].phy, rateix);
195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
f078f209 201
f1dc5600
S		 202u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
203{
204 if (flags & CHANNEL_2GHZ) {
205 if (freq == 2484)
206 return 14;
207 if (freq < 2484)
208 return (freq - 2407) / 5;
209 else
210 return 15 + ((freq - 2512) / 20);
211 } else if (flags & CHANNEL_5GHZ) {
212 if (ath9k_regd_is_public_safety_sku(ah) &&
213 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
214 return ((freq * 10) +
215 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
216 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
217 return (freq - 4000) / 5;
218 } else {
219 return (freq - 5000) / 5;
220 }
221 } else {
222 if (freq == 2484)
223 return 14;
224 if (freq < 2484)
225 return (freq - 2407) / 5;
226 if (freq < 5000) {
227 if (ath9k_regd_is_public_safety_sku(ah)
228 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
229 return ((freq * 10) +
230 (((freq % 5) ==
231 2) ? 5 : 0) - 49400) / 5;
232 } else if (freq > 4900) {
233 return (freq - 4000) / 5;
234 } else {
235 return 15 + ((freq - 2512) / 20);
236 }
237 }
238 return (freq - 5000) / 5;
239 }
f078f209
LR		 240}
241
f1dc5600
S		 242void ath9k_hw_get_channel_centers(struct ath_hal *ah,
243 struct ath9k_channel *chan,
244 struct chan_centers *centers)
f078f209 245{
f1dc5600 246 int8_t extoff;
f078f209
LR		 247 struct ath_hal_5416 *ahp = AH5416(ah);
248
f1dc5600
S		 249 if (!IS_CHAN_HT40(chan)) {
250 centers->ctl_center = centers->ext_center =
251 centers->synth_center = chan->channel;
252 return;
f078f209 253 }
f078f209 254
f1dc5600
S		 255 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
256 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
257 centers->synth_center =
258 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
259 extoff = 1;
260 } else {
261 centers->synth_center =
262 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
263 extoff = -1;
264 }
f078f209 265
f1dc5600
S		 266 centers->ctl_center =
267 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
268 centers->ext_center =
269 centers->synth_center + (extoff *
270 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
271 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209 272
f078f209
LR		 273}
274
f1dc5600
S		 275/******************/
276/* Chip Revisions */
277/******************/
278
279static void ath9k_hw_read_revisions(struct ath_hal *ah)
f078f209 280{
f1dc5600 281 u32 val;
f078f209 282
f1dc5600 283 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 284
f1dc5600
S		 285 if (val == 0xFF) {
286 val = REG_READ(ah, AR_SREV);
287 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
288 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
289 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
290 } else {
291 if (!AR_SREV_9100(ah))
292 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
f078f209 293
f1dc5600 294 ah->ah_macRev = val & AR_SREV_REVISION;
f078f209 295
f1dc5600
S		 296 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
297 ah->ah_isPciExpress = true;
298 }
f078f209
LR		 299}
300
f1dc5600 301static int ath9k_hw_get_radiorev(struct ath_hal *ah)
f078f209 302{
f1dc5600
S		 303 u32 val;
304 int i;
f078f209 305
f1dc5600 306 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 307
f1dc5600
S		 308 for (i = 0; i < 8; i++)
309 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
310 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
311 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 312
f1dc5600 313 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 314}
315
f1dc5600
S		 316/************************************/
317/* HW Attach, Detach, Init Routines */
318/************************************/
319
320static void ath9k_hw_disablepcie(struct ath_hal *ah)
f078f209 321{
f1dc5600
S		 322 if (!AR_SREV_9100(ah))
323 return;
f078f209 324
f1dc5600
S		 325 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 334
f1dc5600 335 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 336}
337
f1dc5600 338static bool ath9k_hw_chip_test(struct ath_hal *ah)
f078f209 339{
f1dc5600
S		 340 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
341 u32 regHold[2];
342 u32 patternData[4] = { 0x55555555,
343 0xaaaaaaaa,
344 0x66666666,
345 0x99999999 };
346 int i, j;
f078f209 347
f1dc5600
S		 348 for (i = 0; i < 2; i++) {
349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
f078f209 351
f1dc5600
S		 352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 359 "address test failed "
f1dc5600 360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 361 addr, wrData, rdData);
f1dc5600
S		 362 return false;
363 }
364 }
365 for (j = 0; j < 4; j++) {
366 wrData = patternData[j];
367 REG_WRITE(ah, addr, wrData);
368 rdData = REG_READ(ah, addr);
369 if (wrData != rdData) {
370 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 371 "address test failed "
f1dc5600 372 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 373 addr, wrData, rdData);
f1dc5600
S		 374 return false;
375 }
f078f209 376 }
f1dc5600 377 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 378 }
f1dc5600 379 udelay(100);
f078f209
LR		 380 return true;
381}
382
f1dc5600 383static const char *ath9k_hw_devname(u16 devid)
f078f209 384{
f1dc5600
S		 385 switch (devid) {
386 case AR5416_DEVID_PCI:
f1dc5600 387 return "Atheros 5416";
392dff83
BP		 388 case AR5416_DEVID_PCIE:
389 return "Atheros 5418";
f1dc5600
S		 390 case AR9160_DEVID_PCI:
391 return "Atheros 9160";
392 case AR9280_DEVID_PCI:
393 case AR9280_DEVID_PCIE:
394 return "Atheros 9280";
f078f209
LR		 395 }
396
f1dc5600
S		 397 return NULL;
398}
f078f209 399
f1dc5600
S		 400static void ath9k_hw_set_defaults(struct ath_hal *ah)
401{
402 int i;
f078f209 403
f1dc5600
S		 404 ah->ah_config.dma_beacon_response_time = 2;
405 ah->ah_config.sw_beacon_response_time = 10;
406 ah->ah_config.additional_swba_backoff = 0;
407 ah->ah_config.ack_6mb = 0x0;
408 ah->ah_config.cwm_ignore_extcca = 0;
409 ah->ah_config.pcie_powersave_enable = 0;
410 ah->ah_config.pcie_l1skp_enable = 0;
411 ah->ah_config.pcie_clock_req = 0;
412 ah->ah_config.pcie_power_reset = 0x100;
413 ah->ah_config.pcie_restore = 0;
414 ah->ah_config.pcie_waen = 0;
415 ah->ah_config.analog_shiftreg = 1;
416 ah->ah_config.ht_enable = 1;
417 ah->ah_config.ofdm_trig_low = 200;
418 ah->ah_config.ofdm_trig_high = 500;
419 ah->ah_config.cck_trig_high = 200;
420 ah->ah_config.cck_trig_low = 100;
421 ah->ah_config.enable_ani = 1;
422 ah->ah_config.noise_immunity_level = 4;
423 ah->ah_config.ofdm_weaksignal_det = 1;
424 ah->ah_config.cck_weaksignal_thr = 0;
425 ah->ah_config.spur_immunity_level = 2;
426 ah->ah_config.firstep_level = 0;
427 ah->ah_config.rssi_thr_high = 40;
428 ah->ah_config.rssi_thr_low = 7;
429 ah->ah_config.diversity_control = 0;
430 ah->ah_config.antenna_switch_swap = 0;
f078f209 431
f1dc5600
S		 432 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
433 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
434 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 435 }
436
f1dc5600 437 ah->ah_config.intr_mitigation = 1;
f078f209
LR		 438}
439
f078f209
LR		 440static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
441 struct ath_softc *sc,
442 void __iomem *mem,
443 int *status)
444{
445 static const u8 defbssidmask[ETH_ALEN] =
446 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
447 struct ath_hal_5416 *ahp;
448 struct ath_hal *ah;
449
450 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
451 if (ahp == NULL) {
452 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 453 "Cannot allocate memory for state block\n");
f078f209
LR		 454 *status = -ENOMEM;
455 return NULL;
456 }
457
458 ah = &ahp->ah;
f078f209
LR		 459 ah->ah_sc = sc;
460 ah->ah_sh = mem;
d2d80ee9
S		 461 ah->ah_magic = AR5416_MAGIC;
462 ah->ah_countryCode = CTRY_DEFAULT;
f078f209
LR		 463 ah->ah_devid = devid;
464 ah->ah_subvendorid = 0;
465
466 ah->ah_flags = 0;
467 if ((devid == AR5416_AR9100_DEVID))
468 ah->ah_macVersion = AR_SREV_VERSION_9100;
469 if (!AR_SREV_9100(ah))
470 ah->ah_flags = AH_USE_EEPROM;
471
472 ah->ah_powerLimit = MAX_RATE_POWER;
473 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
f078f209 474 ahp->ah_atimWindow = 0;
60b67f51 475 ahp->ah_diversityControl = ah->ah_config.diversity_control;
f078f209 476 ahp->ah_antennaSwitchSwap =
60b67f51 477 ah->ah_config.antenna_switch_swap;
f078f209
LR		 478 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
479 ahp->ah_beaconInterval = 100;
480 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
481 ahp->ah_slottime = (u32) -1;
482 ahp->ah_acktimeout = (u32) -1;
483 ahp->ah_ctstimeout = (u32) -1;
484 ahp->ah_globaltxtimeout = (u32) -1;
485 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
486
487 ahp->ah_gBeaconRate = 0;
488
489 return ahp;
490}
491
f1dc5600 492static int ath9k_hw_rfattach(struct ath_hal *ah)
f078f209 493{
f1dc5600
S		 494 bool rfStatus = false;
495 int ecode = 0;
f078f209 496
f1dc5600
S		 497 rfStatus = ath9k_hw_init_rf(ah, &ecode);
498 if (!rfStatus) {
499 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 500 "RF setup failed, status %u\n", ecode);
f1dc5600
S		 501 return ecode;
502 }
f078f209 503
f1dc5600 504 return 0;
f078f209
LR		 505}
506
f1dc5600 507static int ath9k_hw_rf_claim(struct ath_hal *ah)
f078f209 508{
f1dc5600
S		 509 u32 val;
510
511 REG_WRITE(ah, AR_PHY(0), 0x00000007);
512
513 val = ath9k_hw_get_radiorev(ah);
514 switch (val & AR_RADIO_SREV_MAJOR) {
515 case 0:
516 val = AR_RAD5133_SREV_MAJOR;
517 break;
518 case AR_RAD5133_SREV_MAJOR:
519 case AR_RAD5122_SREV_MAJOR:
520 case AR_RAD2133_SREV_MAJOR:
521 case AR_RAD2122_SREV_MAJOR:
522 break;
f078f209 523 default:
f1dc5600 524 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 525 "5G Radio Chip Rev 0x%02X is not "
f1dc5600 526 "supported by this driver\n",
04bd4638 527 ah->ah_analog5GhzRev);
f1dc5600 528 return -EOPNOTSUPP;
f078f209 529 }
f078f209 530
f1dc5600 531 ah->ah_analog5GhzRev = val;
f078f209 532
f1dc5600 533 return 0;
f078f209
LR		 534}
535
ff9b662d 536static int ath9k_hw_init_macaddr(struct ath_hal *ah)
f078f209
LR		 537{
538 u32 sum;
539 int i;
540 u16 eeval;
541 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 542
543 sum = 0;
544 for (i = 0; i < 3; i++) {
f1dc5600 545 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209
LR		 546 sum += eeval;
547 ahp->ah_macaddr[2 * i] = eeval >> 8;
548 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
549 }
550 if (sum == 0 || sum == 0xffff * 3) {
551 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 552 "mac address read failed: %pM\n",
f1dc5600 553 ahp->ah_macaddr);
f078f209
LR		 554 return -EADDRNOTAVAIL;
555 }
556
557 return 0;
558}
559
9f804202
SB		 560static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
561{
562 u32 rxgain_type;
563 struct ath_hal_5416 *ahp = AH5416(ah);
564
565 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
566 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
567
568 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
569 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
570 ar9280Modes_backoff_13db_rxgain_9280_2,
571 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
572 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
573 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
574 ar9280Modes_backoff_23db_rxgain_9280_2,
575 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
576 else
577 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
578 ar9280Modes_original_rxgain_9280_2,
579 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
580 } else
581 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
582 ar9280Modes_original_rxgain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
584}
585
586static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
587{
588 u32 txgain_type;
589 struct ath_hal_5416 *ahp = AH5416(ah);
590
591 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
592 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
593
594 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
595 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
596 ar9280Modes_high_power_tx_gain_9280_2,
597 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
598 else
599 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
600 ar9280Modes_original_tx_gain_9280_2,
601 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
602 } else
603 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
604 ar9280Modes_original_tx_gain_9280_2,
605 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
606}
607
f1dc5600 608static int ath9k_hw_post_attach(struct ath_hal *ah)
f078f209 609{
f1dc5600 610 int ecode;
f078f209 611
f1dc5600
S		 612 if (!ath9k_hw_chip_test(ah)) {
613 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 614 "hardware self-test failed\n");
f1dc5600 615 return -ENODEV;
f078f209 616 }
f078f209 617
f1dc5600
S		 618 ecode = ath9k_hw_rf_claim(ah);
619 if (ecode != 0)
f078f209 620 return ecode;
f078f209 621
f1dc5600
S		 622 ecode = ath9k_hw_eeprom_attach(ah);
623 if (ecode != 0)
624 return ecode;
625 ecode = ath9k_hw_rfattach(ah);
626 if (ecode != 0)
627 return ecode;
f078f209 628
f1dc5600
S		 629 if (!AR_SREV_9100(ah)) {
630 ath9k_hw_ani_setup(ah);
631 ath9k_hw_ani_attach(ah);
f078f209
LR		 632 }
633
f078f209
LR		 634 return 0;
635}
636
f1dc5600
S		 637static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
638 void __iomem *mem, int *status)
f078f209 639{
f1dc5600
S		 640 struct ath_hal_5416 *ahp;
641 struct ath_hal *ah;
642 int ecode;
643#ifndef CONFIG_SLOW_ANT_DIV
644 u32 i;
645 u32 j;
646#endif
f078f209 647
f1dc5600
S		 648 ahp = ath9k_hw_newstate(devid, sc, mem, status);
649 if (ahp == NULL)
650 return NULL;
f078f209 651
f1dc5600 652 ah = &ahp->ah;
f078f209 653
f1dc5600 654 ath9k_hw_set_defaults(ah);
f078f209 655
f1dc5600
S		 656 if (ah->ah_config.intr_mitigation != 0)
657 ahp->ah_intrMitigation = true;
f078f209 658
f1dc5600 659 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
04bd4638 660 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
f1dc5600
S		 661 ecode = -EIO;
662 goto bad;
663 }
f078f209 664
f1dc5600 665 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
04bd4638 666 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
f1dc5600
S		 667 ecode = -EIO;
668 goto bad;
669 }
f078f209 670
f1dc5600
S		 671 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
672 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
673 ah->ah_config.serialize_regmode =
674 SER_REG_MODE_ON;
f078f209 675 } else {
f1dc5600
S		 676 ah->ah_config.serialize_regmode =
677 SER_REG_MODE_OFF;
f078f209
LR		 678 }
679 }
f078f209 680
f1dc5600 681 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 682 "serialize_regmode is %d\n",
683 ah->ah_config.serialize_regmode);
f078f209 684
f1dc5600
S		 685 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
686 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
687 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
688 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
689 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638
S		 690 "Mac Chip Rev 0x%02x.%x is not supported by "
691 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
f1dc5600
S		 692 ecode = -EOPNOTSUPP;
693 goto bad;
694 }
f078f209 695
f1dc5600
S		 696 if (AR_SREV_9100(ah)) {
697 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
698 ahp->ah_suppCals = IQ_MISMATCH_CAL;
699 ah->ah_isPciExpress = false;
700 }
701 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
f078f209 702
f1dc5600
S		 703 if (AR_SREV_9160_10_OR_LATER(ah)) {
704 if (AR_SREV_9280_10_OR_LATER(ah)) {
705 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
706 ahp->ah_adcGainCalData.calData =
707 &adc_gain_cal_single_sample;
708 ahp->ah_adcDcCalData.calData =
709 &adc_dc_cal_single_sample;
710 ahp->ah_adcDcCalInitData.calData =
711 &adc_init_dc_cal;
712 } else {
713 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
714 ahp->ah_adcGainCalData.calData =
715 &adc_gain_cal_multi_sample;
716 ahp->ah_adcDcCalData.calData =
717 &adc_dc_cal_multi_sample;
718 ahp->ah_adcDcCalInitData.calData =
719 &adc_init_dc_cal;
720 }
721 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
722 }
f078f209 723
f1dc5600
S		 724 if (AR_SREV_9160(ah)) {
725 ah->ah_config.enable_ani = 1;
726 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
727 ATH9K_ANI_FIRSTEP_LEVEL);
728 } else {
729 ahp->ah_ani_function = ATH9K_ANI_ALL;
730 if (AR_SREV_9280_10_OR_LATER(ah)) {
731 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
732 }
f078f209 733 }
f078f209 734
f1dc5600 735 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 736 "This Mac Chip Rev 0x%02x.%x is \n",
f1dc5600 737 ah->ah_macVersion, ah->ah_macRev);
f078f209 738
f1dc5600
S		 739 if (AR_SREV_9280_20_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
741 ARRAY_SIZE(ar9280Modes_9280_2), 6);
742 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
743 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 744
f1dc5600
S		 745 if (ah->ah_config.pcie_clock_req) {
746 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
747 ar9280PciePhy_clkreq_off_L1_9280,
748 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
749 } else {
750 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
751 ar9280PciePhy_clkreq_always_on_L1_9280,
752 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
753 }
754 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
755 ar9280Modes_fast_clock_9280_2,
756 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
757 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
758 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
759 ARRAY_SIZE(ar9280Modes_9280), 6);
760 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
761 ARRAY_SIZE(ar9280Common_9280), 2);
762 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
763 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
764 ARRAY_SIZE(ar5416Modes_9160), 6);
765 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
766 ARRAY_SIZE(ar5416Common_9160), 2);
767 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
768 ARRAY_SIZE(ar5416Bank0_9160), 2);
769 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
770 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
771 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
772 ARRAY_SIZE(ar5416Bank1_9160), 2);
773 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
774 ARRAY_SIZE(ar5416Bank2_9160), 2);
775 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
776 ARRAY_SIZE(ar5416Bank3_9160), 3);
777 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
778 ARRAY_SIZE(ar5416Bank6_9160), 3);
779 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
780 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
781 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
782 ARRAY_SIZE(ar5416Bank7_9160), 2);
783 if (AR_SREV_9160_11(ah)) {
784 INIT_INI_ARRAY(&ahp->ah_iniAddac,
785 ar5416Addac_91601_1,
786 ARRAY_SIZE(ar5416Addac_91601_1), 2);
787 } else {
788 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
789 ARRAY_SIZE(ar5416Addac_9160), 2);
790 }
791 } else if (AR_SREV_9100_OR_LATER(ah)) {
792 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
793 ARRAY_SIZE(ar5416Modes_9100), 6);
794 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
795 ARRAY_SIZE(ar5416Common_9100), 2);
796 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
797 ARRAY_SIZE(ar5416Bank0_9100), 2);
798 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
799 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
800 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
801 ARRAY_SIZE(ar5416Bank1_9100), 2);
802 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
803 ARRAY_SIZE(ar5416Bank2_9100), 2);
804 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
805 ARRAY_SIZE(ar5416Bank3_9100), 3);
806 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
807 ARRAY_SIZE(ar5416Bank6_9100), 3);
808 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
809 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
810 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
811 ARRAY_SIZE(ar5416Bank7_9100), 2);
812 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
813 ARRAY_SIZE(ar5416Addac_9100), 2);
814 } else {
815 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
816 ARRAY_SIZE(ar5416Modes), 6);
817 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
818 ARRAY_SIZE(ar5416Common), 2);
819 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
820 ARRAY_SIZE(ar5416Bank0), 2);
821 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
822 ARRAY_SIZE(ar5416BB_RfGain), 3);
823 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
824 ARRAY_SIZE(ar5416Bank1), 2);
825 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
826 ARRAY_SIZE(ar5416Bank2), 2);
827 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
828 ARRAY_SIZE(ar5416Bank3), 3);
829 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
830 ARRAY_SIZE(ar5416Bank6), 3);
831 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
832 ARRAY_SIZE(ar5416Bank6TPC), 3);
833 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
834 ARRAY_SIZE(ar5416Bank7), 2);
835 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
836 ARRAY_SIZE(ar5416Addac), 2);
f078f209 837 }
f078f209 838
f1dc5600
S		 839 if (ah->ah_isPciExpress)
840 ath9k_hw_configpcipowersave(ah, 0);
841 else
842 ath9k_hw_disablepcie(ah);
f078f209 843
f1dc5600
S		 844 ecode = ath9k_hw_post_attach(ah);
845 if (ecode != 0)
846 goto bad;
f078f209 847
9f804202
SB		 848 /* rxgain table */
849 if (AR_SREV_9280_20_OR_LATER(ah))
850 ath9k_hw_init_rxgain_ini(ah);
851
852 /* txgain table */
853 if (AR_SREV_9280_20_OR_LATER(ah))
854 ath9k_hw_init_txgain_ini(ah);
855
f1dc5600
S		 856#ifndef CONFIG_SLOW_ANT_DIV
857 if (ah->ah_devid == AR9280_DEVID_PCI) {
858 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
859 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
f078f209 860
f1dc5600
S		 861 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
862 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
f078f209 863
f1dc5600
S		 864 INI_RA(&ahp->ah_iniModes, i, j) =
865 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
866 reg, val);
867 }
f078f209 868 }
f1dc5600
S		 869 }
870#endif
871 if (!ath9k_hw_fill_cap_info(ah)) {
872 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 873 "failed ath9k_hw_fill_cap_info\n");
f1dc5600
S		 874 ecode = -EINVAL;
875 goto bad;
f078f209
LR		 876 }
877
f1dc5600
S		 878 ecode = ath9k_hw_init_macaddr(ah);
879 if (ecode != 0) {
f078f209 880 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 881 "failed initializing mac address\n");
f1dc5600 882 goto bad;
f078f209
LR		 883 }
884
f1dc5600
S		 885 if (AR_SREV_9285(ah))
886 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
887 else
888 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 889
f1dc5600 890 ath9k_init_nfcal_hist_buffer(ah);
f078f209 891
f1dc5600
S		 892 return ah;
893bad:
894 if (ahp)
895 ath9k_hw_detach((struct ath_hal *) ahp);
896 if (status)
897 *status = ecode;
f078f209 898
f1dc5600 899 return NULL;
f078f209
LR		 900}
901
f1dc5600
S		 902static void ath9k_hw_init_bb(struct ath_hal *ah,
903 struct ath9k_channel *chan)
f078f209 904{
f1dc5600 905 u32 synthDelay;
f078f209 906
f1dc5600 907 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 908 if (IS_CHAN_B(chan))
f1dc5600
S		 909 synthDelay = (4 * synthDelay) / 22;
910 else
911 synthDelay /= 10;
f078f209 912
f1dc5600 913 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 914
f1dc5600 915 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 916}
917
f1dc5600 918static void ath9k_hw_init_qos(struct ath_hal *ah)
f078f209 919{
f1dc5600
S		 920 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
921 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 922
f1dc5600
S		 923 REG_WRITE(ah, AR_QOS_NO_ACK,
924 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
925 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
926 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
927
928 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
929 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
930 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
931 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
932 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 933}
934
f1dc5600
S		 935static void ath9k_hw_init_pll(struct ath_hal *ah,
936 struct ath9k_channel *chan)
f078f209 937{
f1dc5600 938 u32 pll;
f078f209 939
f1dc5600
S		 940 if (AR_SREV_9100(ah)) {
941 if (chan && IS_CHAN_5GHZ(chan))
942 pll = 0x1450;
f078f209 943 else
f1dc5600
S		 944 pll = 0x1458;
945 } else {
946 if (AR_SREV_9280_10_OR_LATER(ah)) {
947 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 948
f1dc5600
S		 949 if (chan && IS_CHAN_HALF_RATE(chan))
950 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
951 else if (chan && IS_CHAN_QUARTER_RATE(chan))
952 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 953
f1dc5600
S		 954 if (chan && IS_CHAN_5GHZ(chan)) {
955 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 956
f078f209 957
f1dc5600
S		 958 if (AR_SREV_9280_20(ah)) {
959 if (((chan->channel % 20) == 0)
960 || ((chan->channel % 10) == 0))
961 pll = 0x2850;
962 else
963 pll = 0x142c;
964 }
965 } else {
966 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
967 }
f078f209 968
f1dc5600 969 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 970
f1dc5600 971 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 972
f1dc5600
S		 973 if (chan && IS_CHAN_HALF_RATE(chan))
974 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
975 else if (chan && IS_CHAN_QUARTER_RATE(chan))
976 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 977
f1dc5600
S		 978 if (chan && IS_CHAN_5GHZ(chan))
979 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
980 else
981 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
982 } else {
983 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 984
f1dc5600
S		 985 if (chan && IS_CHAN_HALF_RATE(chan))
986 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
987 else if (chan && IS_CHAN_QUARTER_RATE(chan))
988 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 989
f1dc5600
S		 990 if (chan && IS_CHAN_5GHZ(chan))
991 pll |= SM(0xa, AR_RTC_PLL_DIV);
992 else
993 pll |= SM(0xb, AR_RTC_PLL_DIV);
994 }
995 }
996 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
f078f209 997
f1dc5600
S		 998 udelay(RTC_PLL_SETTLE_DELAY);
999
1000 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1001}
1002
ff9b662d 1003static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
f078f209
LR		 1004{
1005 struct ath_hal_5416 *ahp = AH5416(ah);
1006 int rx_chainmask, tx_chainmask;
1007
1008 rx_chainmask = ahp->ah_rxchainmask;
1009 tx_chainmask = ahp->ah_txchainmask;
1010
1011 switch (rx_chainmask) {
1012 case 0x5:
1013 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1014 AR_PHY_SWAP_ALT_CHAIN);
1015 case 0x3:
1016 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1017 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1018 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1019 break;
1020 }
1021 case 0x1:
1022 case 0x2:
1023 if (!AR_SREV_9280(ah))
1024 break;
1025 case 0x7:
1026 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1027 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1028 break;
1029 default:
1030 break;
1031 }
1032
1033 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1034 if (tx_chainmask == 0x5) {
1035 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1036 AR_PHY_SWAP_ALT_CHAIN);
1037 }
1038 if (AR_SREV_9100(ah))
1039 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1040 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1041}
1042
d97809db
CM		 1043static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1044 enum nl80211_iftype opmode)
f078f209 1045{
f078f209 1046 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1047
f1dc5600
S		 1048 ahp->ah_maskReg = AR_IMR_TXERR |
1049 AR_IMR_TXURN |
1050 AR_IMR_RXERR |
1051 AR_IMR_RXORN |
1052 AR_IMR_BCNMISC;
f078f209 1053
f1dc5600
S		 1054 if (ahp->ah_intrMitigation)
1055 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1056 else
f1dc5600 1057 ahp->ah_maskReg |= AR_IMR_RXOK;
f078f209 1058
f1dc5600 1059 ahp->ah_maskReg |= AR_IMR_TXOK;
f078f209 1060
d97809db 1061 if (opmode == NL80211_IFTYPE_AP)
f1dc5600 1062 ahp->ah_maskReg |= AR_IMR_MIB;
f078f209 1063
f1dc5600
S		 1064 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1065 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1066
f1dc5600
S		 1067 if (!AR_SREV_9100(ah)) {
1068 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1069 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1070 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1071 }
f078f209
LR		 1072}
1073
1074static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1075{
1076 struct ath_hal_5416 *ahp = AH5416(ah);
1077
1078 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1079 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
f078f209
LR		 1080 ahp->ah_acktimeout = (u32) -1;
1081 return false;
1082 } else {
1083 REG_RMW_FIELD(ah, AR_TIME_OUT,
1084 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1085 ahp->ah_acktimeout = us;
1086 return true;
1087 }
1088}
1089
1090static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1091{
1092 struct ath_hal_5416 *ahp = AH5416(ah);
1093
1094 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1095 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
f078f209
LR		 1096 ahp->ah_ctstimeout = (u32) -1;
1097 return false;
1098 } else {
1099 REG_RMW_FIELD(ah, AR_TIME_OUT,
1100 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1101 ahp->ah_ctstimeout = us;
1102 return true;
1103 }
1104}
f1dc5600
S		 1105
1106static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
f078f209
LR		 1107{
1108 struct ath_hal_5416 *ahp = AH5416(ah);
1109
1110 if (tu > 0xFFFF) {
1111 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1112 "bad global tx timeout %u\n", tu);
f078f209
LR		 1113 ahp->ah_globaltxtimeout = (u32) -1;
1114 return false;
1115 } else {
1116 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1117 ahp->ah_globaltxtimeout = tu;
1118 return true;
1119 }
1120}
1121
f1dc5600 1122static void ath9k_hw_init_user_settings(struct ath_hal *ah)
f078f209
LR		 1123{
1124 struct ath_hal_5416 *ahp = AH5416(ah);
1125
04bd4638
S		 1126 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1127 ahp->ah_miscMode);
f1dc5600
S		 1128
1129 if (ahp->ah_miscMode != 0)
1130 REG_WRITE(ah, AR_PCU_MISC,
1131 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1132 if (ahp->ah_slottime != (u32) -1)
1133 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1134 if (ahp->ah_acktimeout != (u32) -1)
1135 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1136 if (ahp->ah_ctstimeout != (u32) -1)
1137 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1138 if (ahp->ah_globaltxtimeout != (u32) -1)
1139 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1140}
1141
1142const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1143{
1144 return vendorid == ATHEROS_VENDOR_ID ?
1145 ath9k_hw_devname(devid) : NULL;
1146}
1147
1148void ath9k_hw_detach(struct ath_hal *ah)
1149{
1150 if (!AR_SREV_9100(ah))
1151 ath9k_hw_ani_detach(ah);
1152
1153 ath9k_hw_rfdetach(ah);
1154 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1155 kfree(ah);
1156}
1157
1158struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1159 void __iomem *mem, int *error)
1160{
1161 struct ath_hal *ah = NULL;
1162
1163 switch (devid) {
1164 case AR5416_DEVID_PCI:
1165 case AR5416_DEVID_PCIE:
1166 case AR9160_DEVID_PCI:
1167 case AR9280_DEVID_PCI:
1168 case AR9280_DEVID_PCIE:
1169 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1170 break;
1171 default:
1172 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 1173 "devid=0x%x not supported.\n", devid);
f1dc5600
S		 1174 ah = NULL;
1175 *error = -ENXIO;
1176 break;
f078f209 1177 }
f1dc5600
S		 1178
1179 return ah;
1180}
1181
1182/*******/
1183/* INI */
1184/*******/
1185
1186static void ath9k_hw_override_ini(struct ath_hal *ah,
1187 struct ath9k_channel *chan)
1188{
1189 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1190 AR_SREV_9280_10_OR_LATER(ah))
1191 return;
1192
1193 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1194}
1195
f1dc5600
S		 1196static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1197 struct ar5416_eeprom *pEepData,
1198 u32 reg, u32 value)
f078f209 1199{
f1dc5600 1200 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1201
f1dc5600
S		 1202 switch (ah->ah_devid) {
1203 case AR9280_DEVID_PCI:
1204 if (reg == 0x7894) {
1205 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1206 "ini VAL: %x EEPROM: %x\n", value,
1207 (pBase->version & 0xff));
1208
1209 if ((pBase->version & 0xff) > 0x0a) {
1210 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1211 "PWDCLKIND: %d\n",
1212 pBase->pwdclkind);
1213 value &= ~AR_AN_TOP2_PWDCLKIND;
1214 value |= AR_AN_TOP2_PWDCLKIND &
1215 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1216 } else {
1217 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1218 "PWDCLKIND Earlier Rev\n");
1219 }
1220
1221 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1222 "final ini VAL: %x\n", value);
1223 }
1224 break;
1225 }
1226
1227 return value;
f078f209
LR		 1228}
1229
f1dc5600
S		 1230static int ath9k_hw_process_ini(struct ath_hal *ah,
1231 struct ath9k_channel *chan,
1232 enum ath9k_ht_macmode macmode)
f078f209
LR		 1233{
1234 int i, regWrites = 0;
1235 struct ath_hal_5416 *ahp = AH5416(ah);
1236 u32 modesIndex, freqIndex;
1237 int status;
1238
1239 switch (chan->chanmode) {
1240 case CHANNEL_A:
1241 case CHANNEL_A_HT20:
1242 modesIndex = 1;
1243 freqIndex = 1;
1244 break;
1245 case CHANNEL_A_HT40PLUS:
1246 case CHANNEL_A_HT40MINUS:
1247 modesIndex = 2;
1248 freqIndex = 1;
1249 break;
1250 case CHANNEL_G:
1251 case CHANNEL_G_HT20:
1252 case CHANNEL_B:
1253 modesIndex = 4;
1254 freqIndex = 2;
1255 break;
1256 case CHANNEL_G_HT40PLUS:
1257 case CHANNEL_G_HT40MINUS:
1258 modesIndex = 3;
1259 freqIndex = 2;
1260 break;
1261
1262 default:
1263 return -EINVAL;
1264 }
1265
1266 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1267
1268 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1269
1270 ath9k_hw_set_addac(ah, chan);
1271
1272 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1273 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1274 } else {
1275 struct ar5416IniArray temp;
1276 u32 addacSize =
1277 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1278 ahp->ah_iniAddac.ia_columns;
1279
1280 memcpy(ahp->ah_addac5416_21,
1281 ahp->ah_iniAddac.ia_array, addacSize);
1282
f1dc5600 1283 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
f078f209
LR		 1284
1285 temp.ia_array = ahp->ah_addac5416_21;
1286 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1287 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1288 REG_WRITE_ARRAY(&temp, 1, regWrites);
1289 }
f1dc5600 1290
f078f209
LR		 1291 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1292
1293 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1294 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1295 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1296
1297#ifdef CONFIG_SLOW_ANT_DIV
1298 if (ah->ah_devid == AR9280_DEVID_PCI)
f1dc5600 1299 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
f078f209
LR		 1300#endif
1301
1302 REG_WRITE(ah, reg, val);
1303
1304 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1305 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1306 udelay(100);
1307 }
1308
1309 DO_DELAY(regWrites);
1310 }
1311
9f804202
SB		 1312 if (AR_SREV_9280_20_OR_LATER(ah))
1313 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1314
1315 if (AR_SREV_9280_20_OR_LATER(ah))
1316 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1317
f078f209
LR		 1318 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1319 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1320 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1321
1322 REG_WRITE(ah, reg, val);
1323
1324 if (reg >= 0x7800 && reg < 0x78a0
60b67f51 1325 && ah->ah_config.analog_shiftreg) {
f078f209
LR		 1326 udelay(100);
1327 }
1328
1329 DO_DELAY(regWrites);
1330 }
1331
1332 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1333
1334 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1335 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1336 regWrites);
1337 }
1338
1339 ath9k_hw_override_ini(ah, chan);
1340 ath9k_hw_set_regs(ah, chan, macmode);
1341 ath9k_hw_init_chain_masks(ah);
1342
f1dc5600 1343 status = ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1344 ath9k_regd_get_ctl(ah, chan),
1345 ath9k_regd_get_antenna_allowed(ah,
1346 chan),
1347 chan->maxRegTxPower * 2,
1348 min((u32) MAX_RATE_POWER,
1349 (u32) ah->ah_powerLimit));
1350 if (status != 0) {
1351 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 1352 "error init'ing transmit power\n");
f078f209
LR		 1353 return -EIO;
1354 }
1355
1356 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1357 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 1358 "ar5416SetRfRegs failed\n");
f078f209
LR		 1359 return -EIO;
1360 }
1361
1362 return 0;
1363}
1364
f1dc5600
S		 1365/****************************************/
1366/* Reset and Channel Switching Routines */
1367/****************************************/
1368
1369static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1370{
f1dc5600
S		 1371 u32 rfMode = 0;
1372
1373 if (chan == NULL)
1374 return;
1375
1376 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1377 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1378
1379 if (!AR_SREV_9280_10_OR_LATER(ah))
1380 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1381 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1382
1383 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1384 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1385
1386 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1387}
1388
1389static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1390{
1391 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1392}
1393
1394static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1395{
1396 u32 regval;
1397
1398 regval = REG_READ(ah, AR_AHB_MODE);
1399 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1400
1401 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1402 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1403
1404 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1405
1406 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1407 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1408
1409 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1410
1411 if (AR_SREV_9285(ah)) {
1412 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1413 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1414 } else {
1415 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1416 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1417 }
1418}
1419
1420static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1421{
1422 u32 val;
1423
1424 val = REG_READ(ah, AR_STA_ID1);
1425 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1426 switch (opmode) {
d97809db 1427 case NL80211_IFTYPE_AP:
f1dc5600
S		 1428 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1429 | AR_STA_ID1_KSRCH_MODE);
1430 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1431 break;
d97809db 1432 case NL80211_IFTYPE_ADHOC:
f1dc5600
S		 1433 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1434 | AR_STA_ID1_KSRCH_MODE);
1435 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1436 break;
d97809db
CM		 1437 case NL80211_IFTYPE_STATION:
1438 case NL80211_IFTYPE_MONITOR:
f1dc5600 1439 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1440 break;
f1dc5600
S		 1441 }
1442}
1443
1444static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1445 u32 coef_scaled,
1446 u32 *coef_mantissa,
1447 u32 *coef_exponent)
1448{
1449 u32 coef_exp, coef_man;
1450
1451 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1452 if ((coef_scaled >> coef_exp) & 0x1)
1453 break;
1454
1455 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1456
1457 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1458
1459 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1460 *coef_exponent = coef_exp - 16;
1461}
1462
1463static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1464 struct ath9k_channel *chan)
1465{
1466 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1467 u32 clockMhzScaled = 0x64000000;
1468 struct chan_centers centers;
1469
1470 if (IS_CHAN_HALF_RATE(chan))
1471 clockMhzScaled = clockMhzScaled >> 1;
1472 else if (IS_CHAN_QUARTER_RATE(chan))
1473 clockMhzScaled = clockMhzScaled >> 2;
1474
1475 ath9k_hw_get_channel_centers(ah, chan, &centers);
1476 coef_scaled = clockMhzScaled / centers.synth_center;
1477
1478 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1479 &ds_coef_exp);
1480
1481 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1482 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1483 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1484 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1485
1486 coef_scaled = (9 * coef_scaled) / 10;
1487
1488 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1489 &ds_coef_exp);
1490
1491 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1492 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1493 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1494 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1495}
1496
1497static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1498{
1499 u32 rst_flags;
1500 u32 tmpReg;
1501
1502 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1503 AR_RTC_FORCE_WAKE_ON_INT);
1504
1505 if (AR_SREV_9100(ah)) {
1506 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1507 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1508 } else {
1509 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1510 if (tmpReg &
1511 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1512 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1513 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1514 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1515 } else {
1516 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1517 }
1518
1519 rst_flags = AR_RTC_RC_MAC_WARM;
1520 if (type == ATH9K_RESET_COLD)
1521 rst_flags |= AR_RTC_RC_MAC_COLD;
1522 }
1523
1524 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1525 udelay(50);
1526
1527 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1528 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1529 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1530 "RTC stuck in MAC reset\n");
f1dc5600
S		 1531 return false;
1532 }
1533
1534 if (!AR_SREV_9100(ah))
1535 REG_WRITE(ah, AR_RC, 0);
1536
1537 ath9k_hw_init_pll(ah, NULL);
1538
1539 if (AR_SREV_9100(ah))
1540 udelay(50);
1541
1542 return true;
1543}
1544
1545static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1546{
1547 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1548 AR_RTC_FORCE_WAKE_ON_INT);
1549
1550 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1551 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1552
1553 if (!ath9k_hw_wait(ah,
1554 AR_RTC_STATUS,
1555 AR_RTC_STATUS_M,
1556 AR_RTC_STATUS_ON)) {
04bd4638 1557 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1558 return false;
f078f209
LR		 1559 }
1560
f1dc5600
S		 1561 ath9k_hw_read_revisions(ah);
1562
1563 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1564}
1565
1566static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1567{
1568 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1569 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1570
1571 switch (type) {
1572 case ATH9K_RESET_POWER_ON:
1573 return ath9k_hw_set_reset_power_on(ah);
1574 break;
1575 case ATH9K_RESET_WARM:
1576 case ATH9K_RESET_COLD:
1577 return ath9k_hw_set_reset(ah, type);
1578 break;
1579 default:
1580 return false;
1581 }
f078f209
LR		 1582}
1583
f1dc5600
S		 1584static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1585 enum ath9k_ht_macmode macmode)
f078f209 1586{
f1dc5600 1587 u32 phymode;
f078f209 1588 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 1589
f1dc5600
S		 1590 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1591 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1592
1593 if (IS_CHAN_HT40(chan)) {
1594 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1595
f1dc5600
S		 1596 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1597 (chan->chanmode == CHANNEL_G_HT40PLUS))
1598 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1599
f1dc5600
S		 1600 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1601 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1602 }
f1dc5600
S		 1603 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1604
1605 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1606
f1dc5600
S		 1607 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1608 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1609}
1610
f1dc5600
S		 1611static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1612 struct ath9k_channel *chan)
f078f209
LR		 1613{
1614 struct ath_hal_5416 *ahp = AH5416(ah);
1615
f1dc5600
S		 1616 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1617 return false;
f078f209 1618
f1dc5600
S		 1619 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1620 return false;
f078f209 1621
f1dc5600 1622 ahp->ah_chipFullSleep = false;
f078f209 1623
f1dc5600 1624 ath9k_hw_init_pll(ah, chan);
f078f209 1625
f1dc5600 1626 ath9k_hw_set_rfmode(ah, chan);
f078f209 1627
f1dc5600 1628 return true;
f078f209
LR		 1629}
1630
f1dc5600
S		 1631static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1632 struct ath9k_channel *chan)
f078f209 1633{
f1dc5600
S		 1634 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1635 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638
S		 1636 "invalid channel %u/0x%x; not marked as "
1637 "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
f1dc5600
S		 1638 return NULL;
1639 }
f078f209 1640
f1dc5600 1641 if (!IS_CHAN_OFDM(chan) &&
788a3d6f 1642 !IS_CHAN_B(chan) &&
f1dc5600
S		 1643 !IS_CHAN_HT20(chan) &&
1644 !IS_CHAN_HT40(chan)) {
1645 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1646 "invalid channel %u/0x%x; not marked as "
f1dc5600 1647 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
04bd4638 1648 chan->channel, chan->channelFlags);
f1dc5600 1649 return NULL;
f078f209
LR		 1650 }
1651
f1dc5600 1652 return ath9k_regd_check_channel(ah, chan);
f078f209
LR		 1653}
1654
f1dc5600
S		 1655static bool ath9k_hw_channel_change(struct ath_hal *ah,
1656 struct ath9k_channel *chan,
1657 enum ath9k_ht_macmode macmode)
f078f209
LR		 1658{
1659 u32 synthDelay, qnum;
f078f209
LR		 1660
1661 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1662 if (ath9k_hw_numtxpending(ah, qnum)) {
1663 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1664 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1665 return false;
1666 }
1667 }
1668
1669 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1670 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1671 AR_PHY_RFBUS_GRANT_EN)) {
04bd4638
S		 1672 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1673 "Could not kill baseband RX\n");
f078f209
LR		 1674 return false;
1675 }
1676
1677 ath9k_hw_set_regs(ah, chan, macmode);
1678
1679 if (AR_SREV_9280_10_OR_LATER(ah)) {
1680 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1682 "failed to set channel\n");
f078f209
LR		 1683 return false;
1684 }
1685 } else {
1686 if (!(ath9k_hw_set_channel(ah, chan))) {
1687 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1688 "failed to set channel\n");
f078f209
LR		 1689 return false;
1690 }
1691 }
1692
f1dc5600 1693 if (ath9k_hw_set_txpower(ah, chan,
f078f209
LR		 1694 ath9k_regd_get_ctl(ah, chan),
1695 ath9k_regd_get_antenna_allowed(ah, chan),
1696 chan->maxRegTxPower * 2,
1697 min((u32) MAX_RATE_POWER,
1698 (u32) ah->ah_powerLimit)) != 0) {
1699 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 1700 "error init'ing transmit power\n");
f078f209
LR		 1701 return false;
1702 }
1703
1704 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1705 if (IS_CHAN_B(chan))
f078f209
LR		 1706 synthDelay = (4 * synthDelay) / 22;
1707 else
1708 synthDelay /= 10;
1709
1710 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1711
1712 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1713
f1dc5600
S		 1714 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1715 ath9k_hw_set_delta_slope(ah, chan);
1716
1717 if (AR_SREV_9280_10_OR_LATER(ah))
1718 ath9k_hw_9280_spur_mitigate(ah, chan);
1719 else
1720 ath9k_hw_spur_mitigate(ah, chan);
1721
1722 if (!chan->oneTimeCalsDone)
1723 chan->oneTimeCalsDone = true;
1724
1725 return true;
1726}
1727
1728static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1729{
1730 int bb_spur = AR_NO_SPUR;
1731 int freq;
1732 int bin, cur_bin;
1733 int bb_spur_off, spur_subchannel_sd;
1734 int spur_freq_sd;
1735 int spur_delta_phase;
1736 int denominator;
1737 int upper, lower, cur_vit_mask;
1738 int tmp, newVal;
1739 int i;
1740 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1741 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1742 };
1743 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1744 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1745 };
1746 int inc[4] = { 0, 100, 0, 0 };
1747 struct chan_centers centers;
1748
1749 int8_t mask_m[123];
1750 int8_t mask_p[123];
1751 int8_t mask_amt;
1752 int tmp_mask;
1753 int cur_bb_spur;
1754 bool is2GHz = IS_CHAN_2GHZ(chan);
1755
1756 memset(&mask_m, 0, sizeof(int8_t) * 123);
1757 memset(&mask_p, 0, sizeof(int8_t) * 123);
1758
1759 ath9k_hw_get_channel_centers(ah, chan, &centers);
1760 freq = centers.synth_center;
1761
1762 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1763 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1764 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1765
1766 if (is2GHz)
1767 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1768 else
1769 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1770
1771 if (AR_NO_SPUR == cur_bb_spur)
1772 break;
1773 cur_bb_spur = cur_bb_spur - freq;
1774
1775 if (IS_CHAN_HT40(chan)) {
1776 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1777 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1778 bb_spur = cur_bb_spur;
1779 break;
1780 }
1781 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1782 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1783 bb_spur = cur_bb_spur;
1784 break;
1785 }
1786 }
1787
1788 if (AR_NO_SPUR == bb_spur) {
1789 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1790 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1791 return;
1792 } else {
1793 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1794 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1795 }
1796
1797 bin = bb_spur * 320;
1798
1799 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1800
1801 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1802 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1803 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1804 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1805 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1806
1807 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1808 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1809 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1810 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1811 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1812 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1813
1814 if (IS_CHAN_HT40(chan)) {
1815 if (bb_spur < 0) {
1816 spur_subchannel_sd = 1;
1817 bb_spur_off = bb_spur + 10;
1818 } else {
1819 spur_subchannel_sd = 0;
1820 bb_spur_off = bb_spur - 10;
1821 }
1822 } else {
1823 spur_subchannel_sd = 0;
1824 bb_spur_off = bb_spur;
1825 }
1826
1827 if (IS_CHAN_HT40(chan))
1828 spur_delta_phase =
1829 ((bb_spur * 262144) /
1830 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1831 else
1832 spur_delta_phase =
1833 ((bb_spur * 524288) /
1834 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1835
1836 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1837 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1838
1839 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1840 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1841 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1842 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1843
1844 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1845 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1846
1847 cur_bin = -6000;
1848 upper = bin + 100;
1849 lower = bin - 100;
1850
1851 for (i = 0; i < 4; i++) {
1852 int pilot_mask = 0;
1853 int chan_mask = 0;
1854 int bp = 0;
1855 for (bp = 0; bp < 30; bp++) {
1856 if ((cur_bin > lower) && (cur_bin < upper)) {
1857 pilot_mask = pilot_mask | 0x1 << bp;
1858 chan_mask = chan_mask | 0x1 << bp;
1859 }
1860 cur_bin += 100;
1861 }
1862 cur_bin += inc[i];
1863 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1864 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1865 }
1866
1867 cur_vit_mask = 6100;
1868 upper = bin + 120;
1869 lower = bin - 120;
1870
1871 for (i = 0; i < 123; i++) {
1872 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1873
1874 /* workaround for gcc bug #37014 */
1875 volatile int tmp = abs(cur_vit_mask - bin);
1876
1877 if (tmp < 75)
1878 mask_amt = 1;
1879 else
1880 mask_amt = 0;
1881 if (cur_vit_mask < 0)
1882 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1883 else
1884 mask_p[cur_vit_mask / 100] = mask_amt;
1885 }
1886 cur_vit_mask -= 100;
1887 }
1888
1889 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1890 | (mask_m[48] << 26) | (mask_m[49] << 24)
1891 | (mask_m[50] << 22) | (mask_m[51] << 20)
1892 | (mask_m[52] << 18) | (mask_m[53] << 16)
1893 | (mask_m[54] << 14) | (mask_m[55] << 12)
1894 | (mask_m[56] << 10) | (mask_m[57] << 8)
1895 | (mask_m[58] << 6) | (mask_m[59] << 4)
1896 | (mask_m[60] << 2) | (mask_m[61] << 0);
1897 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1898 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1899
1900 tmp_mask = (mask_m[31] << 28)
1901 | (mask_m[32] << 26) | (mask_m[33] << 24)
1902 | (mask_m[34] << 22) | (mask_m[35] << 20)
1903 | (mask_m[36] << 18) | (mask_m[37] << 16)
1904 | (mask_m[48] << 14) | (mask_m[39] << 12)
1905 | (mask_m[40] << 10) | (mask_m[41] << 8)
1906 | (mask_m[42] << 6) | (mask_m[43] << 4)
1907 | (mask_m[44] << 2) | (mask_m[45] << 0);
1908 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1909 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1910
1911 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1912 | (mask_m[18] << 26) | (mask_m[18] << 24)
1913 | (mask_m[20] << 22) | (mask_m[20] << 20)
1914 | (mask_m[22] << 18) | (mask_m[22] << 16)
1915 | (mask_m[24] << 14) | (mask_m[24] << 12)
1916 | (mask_m[25] << 10) | (mask_m[26] << 8)
1917 | (mask_m[27] << 6) | (mask_m[28] << 4)
1918 | (mask_m[29] << 2) | (mask_m[30] << 0);
1919 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1920 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1921
1922 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1923 | (mask_m[2] << 26) | (mask_m[3] << 24)
1924 | (mask_m[4] << 22) | (mask_m[5] << 20)
1925 | (mask_m[6] << 18) | (mask_m[7] << 16)
1926 | (mask_m[8] << 14) | (mask_m[9] << 12)
1927 | (mask_m[10] << 10) | (mask_m[11] << 8)
1928 | (mask_m[12] << 6) | (mask_m[13] << 4)
1929 | (mask_m[14] << 2) | (mask_m[15] << 0);
1930 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1931 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1932
1933 tmp_mask = (mask_p[15] << 28)
1934 | (mask_p[14] << 26) | (mask_p[13] << 24)
1935 | (mask_p[12] << 22) | (mask_p[11] << 20)
1936 | (mask_p[10] << 18) | (mask_p[9] << 16)
1937 | (mask_p[8] << 14) | (mask_p[7] << 12)
1938 | (mask_p[6] << 10) | (mask_p[5] << 8)
1939 | (mask_p[4] << 6) | (mask_p[3] << 4)
1940 | (mask_p[2] << 2) | (mask_p[1] << 0);
1941 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1942 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 1943
f1dc5600
S		 1944 tmp_mask = (mask_p[30] << 28)
1945 | (mask_p[29] << 26) | (mask_p[28] << 24)
1946 | (mask_p[27] << 22) | (mask_p[26] << 20)
1947 | (mask_p[25] << 18) | (mask_p[24] << 16)
1948 | (mask_p[23] << 14) | (mask_p[22] << 12)
1949 | (mask_p[21] << 10) | (mask_p[20] << 8)
1950 | (mask_p[19] << 6) | (mask_p[18] << 4)
1951 | (mask_p[17] << 2) | (mask_p[16] << 0);
1952 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1953 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 1954
f1dc5600
S		 1955 tmp_mask = (mask_p[45] << 28)
1956 | (mask_p[44] << 26) | (mask_p[43] << 24)
1957 | (mask_p[42] << 22) | (mask_p[41] << 20)
1958 | (mask_p[40] << 18) | (mask_p[39] << 16)
1959 | (mask_p[38] << 14) | (mask_p[37] << 12)
1960 | (mask_p[36] << 10) | (mask_p[35] << 8)
1961 | (mask_p[34] << 6) | (mask_p[33] << 4)
1962 | (mask_p[32] << 2) | (mask_p[31] << 0);
1963 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1964 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 1965
f1dc5600
S		 1966 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1967 | (mask_p[59] << 26) | (mask_p[58] << 24)
1968 | (mask_p[57] << 22) | (mask_p[56] << 20)
1969 | (mask_p[55] << 18) | (mask_p[54] << 16)
1970 | (mask_p[53] << 14) | (mask_p[52] << 12)
1971 | (mask_p[51] << 10) | (mask_p[50] << 8)
1972 | (mask_p[49] << 6) | (mask_p[48] << 4)
1973 | (mask_p[47] << 2) | (mask_p[46] << 0);
1974 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1975 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 1976}
1977
f1dc5600 1978static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
f078f209 1979{
f1dc5600
S		 1980 int bb_spur = AR_NO_SPUR;
1981 int bin, cur_bin;
1982 int spur_freq_sd;
1983 int spur_delta_phase;
1984 int denominator;
1985 int upper, lower, cur_vit_mask;
1986 int tmp, new;
1987 int i;
1988 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1989 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1990 };
1991 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1992 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1993 };
1994 int inc[4] = { 0, 100, 0, 0 };
f078f209 1995
f1dc5600
S		 1996 int8_t mask_m[123];
1997 int8_t mask_p[123];
1998 int8_t mask_amt;
1999 int tmp_mask;
2000 int cur_bb_spur;
2001 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2002
f1dc5600
S		 2003 memset(&mask_m, 0, sizeof(int8_t) * 123);
2004 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2005
f1dc5600
S		 2006 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2007 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2008 if (AR_NO_SPUR == cur_bb_spur)
2009 break;
2010 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2011 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2012 bb_spur = cur_bb_spur;
2013 break;
2014 }
2015 }
f078f209 2016
f1dc5600
S		 2017 if (AR_NO_SPUR == bb_spur)
2018 return;
f078f209 2019
f1dc5600 2020 bin = bb_spur * 32;
f078f209 2021
f1dc5600
S		 2022 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2023 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2024 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2025 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2026 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2027
f1dc5600 2028 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2029
f1dc5600
S		 2030 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2031 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2032 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2033 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2034 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2035 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2036
f1dc5600
S		 2037 spur_delta_phase = ((bb_spur * 524288) / 100) &
2038 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2039
f1dc5600
S		 2040 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2041 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2042
f1dc5600
S		 2043 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2044 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2045 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2046 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2047
f1dc5600
S		 2048 cur_bin = -6000;
2049 upper = bin + 100;
2050 lower = bin - 100;
f078f209 2051
f1dc5600
S		 2052 for (i = 0; i < 4; i++) {
2053 int pilot_mask = 0;
2054 int chan_mask = 0;
2055 int bp = 0;
2056 for (bp = 0; bp < 30; bp++) {
2057 if ((cur_bin > lower) && (cur_bin < upper)) {
2058 pilot_mask = pilot_mask | 0x1 << bp;
2059 chan_mask = chan_mask | 0x1 << bp;
2060 }
2061 cur_bin += 100;
2062 }
2063 cur_bin += inc[i];
2064 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2065 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2066 }
f078f209 2067
f1dc5600
S		 2068 cur_vit_mask = 6100;
2069 upper = bin + 120;
2070 lower = bin - 120;
f078f209 2071
f1dc5600
S		 2072 for (i = 0; i < 123; i++) {
2073 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2074
f1dc5600
S		 2075 /* workaround for gcc bug #37014 */
2076 volatile int tmp = abs(cur_vit_mask - bin);
f078f209 2077
f1dc5600
S		 2078 if (tmp < 75)
2079 mask_amt = 1;
2080 else
2081 mask_amt = 0;
2082 if (cur_vit_mask < 0)
2083 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2084 else
2085 mask_p[cur_vit_mask / 100] = mask_amt;
2086 }
2087 cur_vit_mask -= 100;
f078f209
LR		 2088 }
2089
f1dc5600
S		 2090 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2091 | (mask_m[48] << 26) | (mask_m[49] << 24)
2092 | (mask_m[50] << 22) | (mask_m[51] << 20)
2093 | (mask_m[52] << 18) | (mask_m[53] << 16)
2094 | (mask_m[54] << 14) | (mask_m[55] << 12)
2095 | (mask_m[56] << 10) | (mask_m[57] << 8)
2096 | (mask_m[58] << 6) | (mask_m[59] << 4)
2097 | (mask_m[60] << 2) | (mask_m[61] << 0);
2098 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2099 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2100
f1dc5600
S		 2101 tmp_mask = (mask_m[31] << 28)
2102 | (mask_m[32] << 26) | (mask_m[33] << 24)
2103 | (mask_m[34] << 22) | (mask_m[35] << 20)
2104 | (mask_m[36] << 18) | (mask_m[37] << 16)
2105 | (mask_m[48] << 14) | (mask_m[39] << 12)
2106 | (mask_m[40] << 10) | (mask_m[41] << 8)
2107 | (mask_m[42] << 6) | (mask_m[43] << 4)
2108 | (mask_m[44] << 2) | (mask_m[45] << 0);
2109 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2110 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2111
f1dc5600
S		 2112 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2113 | (mask_m[18] << 26) | (mask_m[18] << 24)
2114 | (mask_m[20] << 22) | (mask_m[20] << 20)
2115 | (mask_m[22] << 18) | (mask_m[22] << 16)
2116 | (mask_m[24] << 14) | (mask_m[24] << 12)
2117 | (mask_m[25] << 10) | (mask_m[26] << 8)
2118 | (mask_m[27] << 6) | (mask_m[28] << 4)
2119 | (mask_m[29] << 2) | (mask_m[30] << 0);
2120 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2121 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2122
f1dc5600
S		 2123 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2124 | (mask_m[2] << 26) | (mask_m[3] << 24)
2125 | (mask_m[4] << 22) | (mask_m[5] << 20)
2126 | (mask_m[6] << 18) | (mask_m[7] << 16)
2127 | (mask_m[8] << 14) | (mask_m[9] << 12)
2128 | (mask_m[10] << 10) | (mask_m[11] << 8)
2129 | (mask_m[12] << 6) | (mask_m[13] << 4)
2130 | (mask_m[14] << 2) | (mask_m[15] << 0);
2131 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2132 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2133
f1dc5600
S		 2134 tmp_mask = (mask_p[15] << 28)
2135 | (mask_p[14] << 26) | (mask_p[13] << 24)
2136 | (mask_p[12] << 22) | (mask_p[11] << 20)
2137 | (mask_p[10] << 18) | (mask_p[9] << 16)
2138 | (mask_p[8] << 14) | (mask_p[7] << 12)
2139 | (mask_p[6] << 10) | (mask_p[5] << 8)
2140 | (mask_p[4] << 6) | (mask_p[3] << 4)
2141 | (mask_p[2] << 2) | (mask_p[1] << 0);
2142 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2143 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2144
f1dc5600
S		 2145 tmp_mask = (mask_p[30] << 28)
2146 | (mask_p[29] << 26) | (mask_p[28] << 24)
2147 | (mask_p[27] << 22) | (mask_p[26] << 20)
2148 | (mask_p[25] << 18) | (mask_p[24] << 16)
2149 | (mask_p[23] << 14) | (mask_p[22] << 12)
2150 | (mask_p[21] << 10) | (mask_p[20] << 8)
2151 | (mask_p[19] << 6) | (mask_p[18] << 4)
2152 | (mask_p[17] << 2) | (mask_p[16] << 0);
2153 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2154 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2155
f1dc5600
S		 2156 tmp_mask = (mask_p[45] << 28)
2157 | (mask_p[44] << 26) | (mask_p[43] << 24)
2158 | (mask_p[42] << 22) | (mask_p[41] << 20)
2159 | (mask_p[40] << 18) | (mask_p[39] << 16)
2160 | (mask_p[38] << 14) | (mask_p[37] << 12)
2161 | (mask_p[36] << 10) | (mask_p[35] << 8)
2162 | (mask_p[34] << 6) | (mask_p[33] << 4)
2163 | (mask_p[32] << 2) | (mask_p[31] << 0);
2164 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2165 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2166
f1dc5600
S		 2167 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2168 | (mask_p[59] << 26) | (mask_p[58] << 24)
2169 | (mask_p[57] << 22) | (mask_p[56] << 20)
2170 | (mask_p[55] << 18) | (mask_p[54] << 16)
2171 | (mask_p[53] << 14) | (mask_p[52] << 12)
2172 | (mask_p[51] << 10) | (mask_p[50] << 8)
2173 | (mask_p[49] << 6) | (mask_p[48] << 4)
2174 | (mask_p[47] << 2) | (mask_p[46] << 0);
2175 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2176 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2177}
2178
f1dc5600 2179bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
f078f209
LR		 2180 enum ath9k_ht_macmode macmode,
2181 u8 txchainmask, u8 rxchainmask,
2182 enum ath9k_ht_extprotspacing extprotspacing,
f1dc5600 2183 bool bChannelChange, int *status)
f078f209 2184{
f078f209
LR		 2185 u32 saveLedState;
2186 struct ath_hal_5416 *ahp = AH5416(ah);
2187 struct ath9k_channel *curchan = ah->ah_curchan;
2188 u32 saveDefAntenna;
2189 u32 macStaId1;
2190 int ecode;
2191 int i, rx_chainmask;
2192
2193 ahp->ah_extprotspacing = extprotspacing;
2194 ahp->ah_txchainmask = txchainmask;
2195 ahp->ah_rxchainmask = rxchainmask;
2196
2197 if (AR_SREV_9280(ah)) {
2198 ahp->ah_txchainmask &= 0x3;
2199 ahp->ah_rxchainmask &= 0x3;
2200 }
2201
2202 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2203 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638
S		 2204 "invalid channel %u/0x%x; no mapping\n",
2205 chan->channel, chan->channelFlags);
1cf69cfb
LR		 2206 ecode = -EINVAL;
2207 goto bad;
f078f209
LR		 2208 }
2209
d2a3b222
LR		 2210 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2211 ecode = -EIO;
2212 goto bad;
2213 }
f078f209
LR		 2214
2215 if (curchan)
2216 ath9k_hw_getnf(ah, curchan);
2217
2218 if (bChannelChange &&
2219 (ahp->ah_chipFullSleep != true) &&
2220 (ah->ah_curchan != NULL) &&
2221 (chan->channel != ah->ah_curchan->channel) &&
2222 ((chan->channelFlags & CHANNEL_ALL) ==
2223 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2224 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
99405f93 2225 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
f078f209
LR		 2226
2227 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2228 ath9k_hw_loadnf(ah, ah->ah_curchan);
2229 ath9k_hw_start_nfcal(ah);
2230 return true;
2231 }
2232 }
2233
2234 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2235 if (saveDefAntenna == 0)
2236 saveDefAntenna = 1;
2237
2238 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2239
2240 saveLedState = REG_READ(ah, AR_CFG_LED) &
2241 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2242 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2243
2244 ath9k_hw_mark_phy_inactive(ah);
2245
2246 if (!ath9k_hw_chip_reset(ah, chan)) {
04bd4638 2247 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
1cf69cfb
LR		 2248 ecode = -EINVAL;
2249 goto bad;
f078f209
LR		 2250 }
2251
2252 if (AR_SREV_9280(ah)) {
2253 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2254 AR_GPIO_JTAG_DISABLE);
2255
86b89eed 2256 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
f078f209
LR		 2257 if (IS_CHAN_5GHZ(chan))
2258 ath9k_hw_set_gpio(ah, 9, 0);
2259 else
2260 ath9k_hw_set_gpio(ah, 9, 1);
2261 }
c83be688 2262 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
f078f209
LR		 2263 }
2264
2265 ecode = ath9k_hw_process_ini(ah, chan, macmode);
1cf69cfb
LR		 2266 if (ecode != 0) {
2267 ecode = -EINVAL;
f078f209 2268 goto bad;
1cf69cfb 2269 }
f078f209
LR		 2270
2271 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2272 ath9k_hw_set_delta_slope(ah, chan);
2273
2274 if (AR_SREV_9280_10_OR_LATER(ah))
2275 ath9k_hw_9280_spur_mitigate(ah, chan);
2276 else
2277 ath9k_hw_spur_mitigate(ah, chan);
2278
2279 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2280 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 2281 "error setting board options\n");
1cf69cfb
LR		 2282 ecode = -EIO;
2283 goto bad;
f078f209
LR		 2284 }
2285
2286 ath9k_hw_decrease_chain_power(ah, chan);
2287
2288 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2289 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2290 | macStaId1
2291 | AR_STA_ID1_RTS_USE_DEF
2292 | (ah->ah_config.
60b67f51 2293 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
f078f209 2294 | ahp->ah_staId1Defaults);
b4696c8b 2295 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 2296
2297 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2298 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2299
2300 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2301
2302 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2303 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2304 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2305
2306 REG_WRITE(ah, AR_ISR, ~0);
2307
2308 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2309
2310 if (AR_SREV_9280_10_OR_LATER(ah)) {
1cf69cfb
LR		 2311 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2312 ecode = -EIO;
2313 goto bad;
2314 }
f078f209 2315 } else {
1cf69cfb
LR		 2316 if (!(ath9k_hw_set_channel(ah, chan))) {
2317 ecode = -EIO;
2318 goto bad;
2319 }
f078f209
LR		 2320 }
2321
2322 for (i = 0; i < AR_NUM_DCU; i++)
2323 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2324
2325 ahp->ah_intrTxqs = 0;
60b67f51 2326 for (i = 0; i < ah->ah_caps.total_queues; i++)
f078f209
LR		 2327 ath9k_hw_resettxqueue(ah, i);
2328
b4696c8b 2329 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
f078f209
LR		 2330 ath9k_hw_init_qos(ah);
2331
e97275cb 2332#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2333 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2334 ath9k_enable_rfkill(ah);
2335#endif
f078f209
LR		 2336 ath9k_hw_init_user_settings(ah);
2337
f078f209
LR		 2338 REG_WRITE(ah, AR_STA_ID1,
2339 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2340
2341 ath9k_hw_set_dma(ah);
2342
2343 REG_WRITE(ah, AR_OBS, 8);
2344
2345 if (ahp->ah_intrMitigation) {
2346
2347 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2348 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2349 }
2350
2351 ath9k_hw_init_bb(ah, chan);
2352
1cf69cfb
LR		 2353 if (!ath9k_hw_init_cal(ah, chan)){
2354 ecode = -EIO;;
2355 goto bad;
2356 }
f078f209
LR		 2357
2358 rx_chainmask = ahp->ah_rxchainmask;
2359 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2360 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2361 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2362 }
2363
2364 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2365
2366 if (AR_SREV_9100(ah)) {
2367 u32 mask;
2368 mask = REG_READ(ah, AR_CFG);
2369 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2370 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2371 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2372 } else {
2373 mask =
2374 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2375 REG_WRITE(ah, AR_CFG, mask);
2376 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2377 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2378 }
2379 } else {
2380#ifdef __BIG_ENDIAN
2381 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2382#endif
2383 }
2384
2385 return true;
2386bad:
2387 if (status)
2388 *status = ecode;
2389 return false;
f078f209
LR		 2390}
2391
f1dc5600
S		 2392/************************/
2393/* Key Cache Management */
2394/************************/
f078f209 2395
f1dc5600 2396bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
f078f209 2397{
f1dc5600 2398 u32 keyType;
f078f209 2399
f1dc5600
S		 2400 if (entry >= ah->ah_caps.keycache_size) {
2401 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2402 "entry %u out of range\n", entry);
f078f209
LR		 2403 return false;
2404 }
2405
f1dc5600 2406 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2407
f1dc5600
S		 2408 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2410 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2411 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2412 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2413 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2414 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2415 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2416
f1dc5600
S		 2417 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2418 u16 micentry = entry + 64;
f078f209 2419
f1dc5600
S		 2420 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2421 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2422 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2423 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2424
f078f209
LR		 2425 }
2426
f1dc5600
S		 2427 if (ah->ah_curchan == NULL)
2428 return true;
f078f209
LR		 2429
2430 return true;
2431}
2432
f1dc5600 2433bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
f078f209 2434{
f1dc5600 2435 u32 macHi, macLo;
f078f209 2436
f1dc5600
S		 2437 if (entry >= ah->ah_caps.keycache_size) {
2438 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2439 "entry %u out of range\n", entry);
f1dc5600 2440 return false;
f078f209
LR		 2441 }
2442
f1dc5600
S		 2443 if (mac != NULL) {
2444 macHi = (mac[5] << 8) | mac[4];
2445 macLo = (mac[3] << 24) |
2446 (mac[2] << 16) |
2447 (mac[1] << 8) |
2448 mac[0];
2449 macLo >>= 1;
2450 macLo |= (macHi & 1) << 31;
2451 macHi >>= 1;
f078f209 2452 } else {
f1dc5600 2453 macLo = macHi = 0;
f078f209 2454 }
f1dc5600
S		 2455 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2456 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2457
f1dc5600 2458 return true;
f078f209
LR		 2459}
2460
f1dc5600
S		 2461bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2462 const struct ath9k_keyval *k,
2463 const u8 *mac, int xorKey)
f078f209 2464{
f1dc5600
S		 2465 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2466 u32 key0, key1, key2, key3, key4;
2467 u32 keyType;
2468 u32 xorMask = xorKey ?
2469 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2470 | ATH9K_KEY_XOR) : 0;
f078f209 2471 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 2472
f1dc5600
S		 2473 if (entry >= pCap->keycache_size) {
2474 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2475 "entry %u out of range\n", entry);
f1dc5600 2476 return false;
f078f209
LR		 2477 }
2478
f1dc5600
S		 2479 switch (k->kv_type) {
2480 case ATH9K_CIPHER_AES_OCB:
2481 keyType = AR_KEYTABLE_TYPE_AES;
2482 break;
2483 case ATH9K_CIPHER_AES_CCM:
2484 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2485 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2486 "AES-CCM not supported by mac rev 0x%x\n",
f1dc5600
S		 2487 ah->ah_macRev);
2488 return false;
2489 }
2490 keyType = AR_KEYTABLE_TYPE_CCM;
2491 break;
2492 case ATH9K_CIPHER_TKIP:
2493 keyType = AR_KEYTABLE_TYPE_TKIP;
2494 if (ATH9K_IS_MIC_ENABLED(ah)
2495 && entry + 64 >= pCap->keycache_size) {
2496 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2497 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2498 return false;
2499 }
2500 break;
2501 case ATH9K_CIPHER_WEP:
2502 if (k->kv_len < LEN_WEP40) {
2503 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2504 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2505 return false;
2506 }
2507 if (k->kv_len <= LEN_WEP40)
2508 keyType = AR_KEYTABLE_TYPE_40;
2509 else if (k->kv_len <= LEN_WEP104)
2510 keyType = AR_KEYTABLE_TYPE_104;
2511 else
2512 keyType = AR_KEYTABLE_TYPE_128;
2513 break;
2514 case ATH9K_CIPHER_CLR:
2515 keyType = AR_KEYTABLE_TYPE_CLR;
2516 break;
2517 default:
2518 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2519 "cipher %u not supported\n", k->kv_type);
f1dc5600 2520 return false;
f078f209
LR		 2521 }
2522
f1dc5600
S		 2523 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2524 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2525 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2526 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2527 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2528 if (k->kv_len <= LEN_WEP104)
2529 key4 &= 0xff;
f078f209 2530
f1dc5600
S		 2531 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2532 u16 micentry = entry + 64;
f078f209 2533
f1dc5600
S		 2534 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2535 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2536 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2537 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2538 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2539 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2540 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2541
f1dc5600
S		 2542 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2543 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2544
f1dc5600
S		 2545 mic0 = get_unaligned_le32(k->kv_mic + 0);
2546 mic2 = get_unaligned_le32(k->kv_mic + 4);
2547 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2548 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2549 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2550 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2551 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2552 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2554 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2555 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2556 AR_KEYTABLE_TYPE_CLR);
f078f209 2557
f1dc5600
S		 2558 } else {
2559 u32 mic0, mic2;
f078f209 2560
f1dc5600
S		 2561 mic0 = get_unaligned_le32(k->kv_mic + 0);
2562 mic2 = get_unaligned_le32(k->kv_mic + 4);
2563 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2564 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2565 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2566 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2567 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2568 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2569 AR_KEYTABLE_TYPE_CLR);
2570 }
2571 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2572 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2575 } else {
2576 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2577 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2578 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2579 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2581 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2582
f1dc5600
S		 2583 (void) ath9k_hw_keysetmac(ah, entry, mac);
2584 }
f078f209 2585
f1dc5600
S		 2586 if (ah->ah_curchan == NULL)
2587 return true;
f078f209
LR		 2588
2589 return true;
2590}
2591
f1dc5600 2592bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
f078f209 2593{
f1dc5600
S		 2594 if (entry < ah->ah_caps.keycache_size) {
2595 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2596 if (val & AR_KEYTABLE_VALID)
2597 return true;
2598 }
2599 return false;
f078f209
LR		 2600}
2601
f1dc5600
S		 2602/******************************/
2603/* Power Management (Chipset) */
2604/******************************/
2605
2606static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
f078f209 2607{
f1dc5600
S		 2608 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2609 if (setChip) {
2610 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2611 AR_RTC_FORCE_WAKE_EN);
2612 if (!AR_SREV_9100(ah))
2613 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2614
f1dc5600
S		 2615 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2616 AR_RTC_RESET_EN);
2617 }
f078f209
LR		 2618}
2619
f1dc5600 2620static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
f078f209 2621{
f1dc5600
S		 2622 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2623 if (setChip) {
2624 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2625
f1dc5600
S		 2626 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2627 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2628 AR_RTC_FORCE_WAKE_ON_INT);
2629 } else {
2630 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2631 AR_RTC_FORCE_WAKE_EN);
f078f209 2632 }
f078f209 2633 }
f078f209
LR		 2634}
2635
f1dc5600
S		 2636static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2637 int setChip)
f078f209 2638{
f1dc5600
S		 2639 u32 val;
2640 int i;
f078f209 2641
f1dc5600
S		 2642 if (setChip) {
2643 if ((REG_READ(ah, AR_RTC_STATUS) &
2644 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2645 if (ath9k_hw_set_reset_reg(ah,
2646 ATH9K_RESET_POWER_ON) != true) {
2647 return false;
2648 }
2649 }
2650 if (AR_SREV_9100(ah))
2651 REG_SET_BIT(ah, AR_RTC_RESET,
2652 AR_RTC_RESET_EN);
f078f209 2653
f1dc5600
S		 2654 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2655 AR_RTC_FORCE_WAKE_EN);
2656 udelay(50);
f078f209 2657
f1dc5600
S		 2658 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2659 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2660 if (val == AR_RTC_STATUS_ON)
2661 break;
2662 udelay(50);
2663 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2664 AR_RTC_FORCE_WAKE_EN);
f078f209 2665 }
f1dc5600
S		 2666 if (i == 0) {
2667 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2668 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2669 return false;
f078f209 2670 }
f078f209
LR		 2671 }
2672
f1dc5600 2673 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2674
f1dc5600 2675 return true;
f078f209
LR		 2676}
2677
f1dc5600
S		 2678bool ath9k_hw_setpower(struct ath_hal *ah,
2679 enum ath9k_power_mode mode)
f078f209
LR		 2680{
2681 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600
S		 2682 static const char *modes[] = {
2683 "AWAKE",
2684 "FULL-SLEEP",
2685 "NETWORK SLEEP",
2686 "UNDEFINED"
2687 };
2688 int status = true, setChip = true;
2689
04bd4638 2690 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
f1dc5600
S		 2691 modes[ahp->ah_powerMode], modes[mode],
2692 setChip ? "set chip " : "");
2693
2694 switch (mode) {
2695 case ATH9K_PM_AWAKE:
2696 status = ath9k_hw_set_power_awake(ah, setChip);
2697 break;
2698 case ATH9K_PM_FULL_SLEEP:
2699 ath9k_set_power_sleep(ah, setChip);
2700 ahp->ah_chipFullSleep = true;
2701 break;
2702 case ATH9K_PM_NETWORK_SLEEP:
2703 ath9k_set_power_network_sleep(ah, setChip);
2704 break;
f078f209 2705 default:
f1dc5600 2706 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2707 "Unknown power mode %u\n", mode);
f078f209
LR		 2708 return false;
2709 }
f1dc5600
S		 2710 ahp->ah_powerMode = mode;
2711
2712 return status;
f078f209
LR		 2713}
2714
f1dc5600 2715void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
f078f209
LR		 2716{
2717 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 2718 u8 i;
f078f209 2719
f1dc5600
S		 2720 if (ah->ah_isPciExpress != true)
2721 return;
f078f209 2722
f1dc5600
S		 2723 if (ah->ah_config.pcie_powersave_enable == 2)
2724 return;
2725
2726 if (restore)
2727 return;
2728
2729 if (AR_SREV_9280_20_OR_LATER(ah)) {
2730 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2731 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2732 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
f078f209 2733 }
f1dc5600
S		 2734 udelay(1000);
2735 } else if (AR_SREV_9280(ah) &&
2736 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2737 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2738 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2739
2740 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2741 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2742 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2743
2744 if (ah->ah_config.pcie_clock_req)
2745 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2746 else
2747 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2748
2749 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2750 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2751 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2752
2753 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2754
2755 udelay(1000);
2756 } else {
2757 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2758 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2759 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2760 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2761 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2762 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2763 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2764 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2766 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 2767 }
2768
f1dc5600
S		 2769 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2770
2771 if (ah->ah_config.pcie_waen) {
2772 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2773 } else {
2774 if (AR_SREV_9280(ah))
2775 REG_WRITE(ah, AR_WA, 0x0040073f);
2776 else
2777 REG_WRITE(ah, AR_WA, 0x0000073f);
2778 }
f078f209
LR		 2779}
2780
f1dc5600
S		 2781/**********************/
2782/* Interrupt Handling */
2783/**********************/
2784
f078f209
LR		 2785bool ath9k_hw_intrpend(struct ath_hal *ah)
2786{
2787 u32 host_isr;
2788
2789 if (AR_SREV_9100(ah))
2790 return true;
2791
2792 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2793 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2794 return true;
2795
2796 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2797 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2798 && (host_isr != AR_INTR_SPURIOUS))
2799 return true;
2800
2801 return false;
2802}
2803
2804bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2805{
2806 u32 isr = 0;
2807 u32 mask2 = 0;
60b67f51 2808 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 2809 u32 sync_cause = 0;
2810 bool fatal_int = false;
f1dc5600 2811 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209
LR		 2812
2813 if (!AR_SREV_9100(ah)) {
2814 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2815 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2816 == AR_RTC_STATUS_ON) {
2817 isr = REG_READ(ah, AR_ISR);
2818 }
2819 }
2820
f1dc5600
S		 2821 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2822 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2823
2824 *masked = 0;
2825
2826 if (!isr && !sync_cause)
2827 return false;
2828 } else {
2829 *masked = 0;
2830 isr = REG_READ(ah, AR_ISR);
2831 }
2832
2833 if (isr) {
f078f209
LR		 2834 if (isr & AR_ISR_BCNMISC) {
2835 u32 isr2;
2836 isr2 = REG_READ(ah, AR_ISR_S2);
2837 if (isr2 & AR_ISR_S2_TIM)
2838 mask2 |= ATH9K_INT_TIM;
2839 if (isr2 & AR_ISR_S2_DTIM)
2840 mask2 |= ATH9K_INT_DTIM;
2841 if (isr2 & AR_ISR_S2_DTIMSYNC)
2842 mask2 |= ATH9K_INT_DTIMSYNC;
2843 if (isr2 & (AR_ISR_S2_CABEND))
2844 mask2 |= ATH9K_INT_CABEND;
2845 if (isr2 & AR_ISR_S2_GTT)
2846 mask2 |= ATH9K_INT_GTT;
2847 if (isr2 & AR_ISR_S2_CST)
2848 mask2 |= ATH9K_INT_CST;
2849 }
2850
2851 isr = REG_READ(ah, AR_ISR_RAC);
2852 if (isr == 0xffffffff) {
2853 *masked = 0;
2854 return false;
2855 }
2856
2857 *masked = isr & ATH9K_INT_COMMON;
2858
2859 if (ahp->ah_intrMitigation) {
f078f209
LR		 2860 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2861 *masked |= ATH9K_INT_RX;
2862 }
2863
2864 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2865 *masked |= ATH9K_INT_RX;
2866 if (isr &
2867 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2868 AR_ISR_TXEOL)) {
2869 u32 s0_s, s1_s;
2870
2871 *masked |= ATH9K_INT_TX;
2872
2873 s0_s = REG_READ(ah, AR_ISR_S0_S);
2874 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2875 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2876
2877 s1_s = REG_READ(ah, AR_ISR_S1_S);
2878 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2879 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2880 }
2881
2882 if (isr & AR_ISR_RXORN) {
2883 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2884 "receive FIFO overrun interrupt\n");
f078f209
LR		 2885 }
2886
2887 if (!AR_SREV_9100(ah)) {
60b67f51 2888 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2889 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2890 if (isr5 & AR_ISR_S5_TIM_TIMER)
2891 *masked |= ATH9K_INT_TIM_TIMER;
2892 }
2893 }
2894
2895 *masked |= mask2;
2896 }
f1dc5600 2897
f078f209
LR		 2898 if (AR_SREV_9100(ah))
2899 return true;
f1dc5600 2900
f078f209
LR		 2901 if (sync_cause) {
2902 fatal_int =
2903 (sync_cause &
2904 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2905 ? true : false;
2906
2907 if (fatal_int) {
2908 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2909 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2910 "received PCI FATAL interrupt\n");
f078f209
LR		 2911 }
2912 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2913 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2914 "received PCI PERR interrupt\n");
f078f209
LR		 2915 }
2916 }
2917 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2918 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2919 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2920 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2921 REG_WRITE(ah, AR_RC, 0);
2922 *masked |= ATH9K_INT_FATAL;
2923 }
2924 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2925 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2926 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2927 }
2928
2929 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2930 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2931 }
f1dc5600 2932
f078f209
LR		 2933 return true;
2934}
2935
2936enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2937{
2938 return AH5416(ah)->ah_maskReg;
2939}
2940
2941enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2942{
2943 struct ath_hal_5416 *ahp = AH5416(ah);
2944 u32 omask = ahp->ah_maskReg;
2945 u32 mask, mask2;
60b67f51 2946 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 2947
04bd4638 2948 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2949
2950 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 2951 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2952 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2953 (void) REG_READ(ah, AR_IER);
2954 if (!AR_SREV_9100(ah)) {
2955 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2956 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2957
2958 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2959 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2960 }
2961 }
2962
2963 mask = ints & ATH9K_INT_COMMON;
2964 mask2 = 0;
2965
2966 if (ints & ATH9K_INT_TX) {
2967 if (ahp->ah_txOkInterruptMask)
2968 mask |= AR_IMR_TXOK;
2969 if (ahp->ah_txDescInterruptMask)
2970 mask |= AR_IMR_TXDESC;
2971 if (ahp->ah_txErrInterruptMask)
2972 mask |= AR_IMR_TXERR;
2973 if (ahp->ah_txEolInterruptMask)
2974 mask |= AR_IMR_TXEOL;
2975 }
2976 if (ints & ATH9K_INT_RX) {
2977 mask |= AR_IMR_RXERR;
2978 if (ahp->ah_intrMitigation)
2979 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2980 else
2981 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2982 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2983 mask |= AR_IMR_GENTMR;
2984 }
2985
2986 if (ints & (ATH9K_INT_BMISC)) {
2987 mask |= AR_IMR_BCNMISC;
2988 if (ints & ATH9K_INT_TIM)
2989 mask2 |= AR_IMR_S2_TIM;
2990 if (ints & ATH9K_INT_DTIM)
2991 mask2 |= AR_IMR_S2_DTIM;
2992 if (ints & ATH9K_INT_DTIMSYNC)
2993 mask2 |= AR_IMR_S2_DTIMSYNC;
2994 if (ints & ATH9K_INT_CABEND)
2995 mask2 |= (AR_IMR_S2_CABEND);
2996 }
2997
2998 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2999 mask |= AR_IMR_BCNMISC;
3000 if (ints & ATH9K_INT_GTT)
3001 mask2 |= AR_IMR_S2_GTT;
3002 if (ints & ATH9K_INT_CST)
3003 mask2 |= AR_IMR_S2_CST;
3004 }
3005
04bd4638 3006 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3007 REG_WRITE(ah, AR_IMR, mask);
3008 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3009 AR_IMR_S2_DTIM |
3010 AR_IMR_S2_DTIMSYNC |
3011 AR_IMR_S2_CABEND |
3012 AR_IMR_S2_CABTO |
3013 AR_IMR_S2_TSFOOR |
3014 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3015 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3016 ahp->ah_maskReg = ints;
3017
60b67f51 3018 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3019 if (ints & ATH9K_INT_TIM_TIMER)
3020 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3021 else
3022 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3023 }
3024
3025 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3026 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3027 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3028 if (!AR_SREV_9100(ah)) {
3029 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3030 AR_INTR_MAC_IRQ);
3031 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3032
3033
3034 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3035 AR_INTR_SYNC_DEFAULT);
3036 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3037 AR_INTR_SYNC_DEFAULT);
3038 }
3039 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3040 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3041 }
3042
3043 return omask;
3044}
3045
f1dc5600
S		 3046/*******************/
3047/* Beacon Handling */
3048/*******************/
3049
3050void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
f078f209
LR		 3051{
3052 struct ath_hal_5416 *ahp = AH5416(ah);
3053 int flags = 0;
3054
3055 ahp->ah_beaconInterval = beacon_period;
3056
3057 switch (ah->ah_opmode) {
d97809db
CM		 3058 case NL80211_IFTYPE_STATION:
3059 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3060 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3061 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3062 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3063 flags |= AR_TBTT_TIMER_EN;
3064 break;
d97809db 3065 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 3066 REG_SET_BIT(ah, AR_TXCFG,
3067 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3068 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3069 TU_TO_USEC(next_beacon +
3070 (ahp->ah_atimWindow ? ahp->
3071 ah_atimWindow : 1)));
3072 flags |= AR_NDP_TIMER_EN;
d97809db 3073 case NL80211_IFTYPE_AP:
f078f209
LR		 3074 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3075 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3076 TU_TO_USEC(next_beacon -
3077 ah->ah_config.
60b67f51 3078 dma_beacon_response_time));
f078f209
LR		 3079 REG_WRITE(ah, AR_NEXT_SWBA,
3080 TU_TO_USEC(next_beacon -
3081 ah->ah_config.
60b67f51 3082 sw_beacon_response_time));
f078f209
LR		 3083 flags |=
3084 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3085 break;
d97809db
CM		 3086 default:
3087 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3088 "%s: unsupported opmode: %d\n",
3089 __func__, ah->ah_opmode);
3090 return;
3091 break;
f078f209
LR		 3092 }
3093
3094 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3095 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3096 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3097 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3098
3099 beacon_period &= ~ATH9K_BEACON_ENA;
3100 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3101 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3102 ath9k_hw_reset_tsf(ah);
3103 }
3104
3105 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3106}
3107
f1dc5600
S		 3108void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3109 const struct ath9k_beacon_state *bs)
f078f209
LR		 3110{
3111 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
60b67f51 3112 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209
LR		 3113
3114 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3115
3116 REG_WRITE(ah, AR_BEACON_PERIOD,
3117 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3118 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3119 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3120
3121 REG_RMW_FIELD(ah, AR_RSSI_THR,
3122 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3123
3124 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3125
3126 if (bs->bs_sleepduration > beaconintval)
3127 beaconintval = bs->bs_sleepduration;
3128
3129 dtimperiod = bs->bs_dtimperiod;
3130 if (bs->bs_sleepduration > dtimperiod)
3131 dtimperiod = bs->bs_sleepduration;
3132
3133 if (beaconintval == dtimperiod)
3134 nextTbtt = bs->bs_nextdtim;
3135 else
3136 nextTbtt = bs->bs_nexttbtt;
3137
04bd4638
S		 3138 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3139 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3140 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3141 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3142
f1dc5600
S		 3143 REG_WRITE(ah, AR_NEXT_DTIM,
3144 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3145 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3146
f1dc5600
S		 3147 REG_WRITE(ah, AR_SLEEP1,
3148 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3149 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3150
f1dc5600
S		 3151 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3152 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3153 else
3154 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3155
f1dc5600
S		 3156 REG_WRITE(ah, AR_SLEEP2,
3157 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3158
f1dc5600
S		 3159 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3160 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3161
f1dc5600
S		 3162 REG_SET_BIT(ah, AR_TIMER_MODE,
3163 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3164 AR_DTIM_TIMER_EN);
f078f209 3165
f078f209
LR		 3166}
3167
f1dc5600
S		 3168/*******************/
3169/* HW Capabilities */
3170/*******************/
3171
3172bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
f078f209
LR		 3173{
3174 struct ath_hal_5416 *ahp = AH5416(ah);
60b67f51 3175 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f1dc5600 3176 u16 capField = 0, eeval;
f078f209 3177
f1dc5600 3178 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
f078f209 3179
f1dc5600 3180 ah->ah_currentRD = eeval;
f078f209 3181
f1dc5600
S		 3182 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3183 ah->ah_currentRDExt = eeval;
f078f209 3184
f1dc5600
S		 3185 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3186
d97809db 3187 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
f1dc5600
S		 3188 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3189 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3190 ah->ah_currentRD += 5;
3191 else if (ah->ah_currentRD == 0x41)
3192 ah->ah_currentRD = 0x43;
3193 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
04bd4638 3194 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
f1dc5600 3195 }
f078f209 3196
f1dc5600
S		 3197 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3198 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3199
f1dc5600
S		 3200 if (eeval & AR5416_OPFLAGS_11A) {
3201 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3202 if (ah->ah_config.ht_enable) {
3203 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3204 set_bit(ATH9K_MODE_11NA_HT20,
3205 pCap->wireless_modes);
3206 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3207 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3208 pCap->wireless_modes);
3209 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3210 pCap->wireless_modes);
3211 }
f078f209 3212 }
f078f209
LR		 3213 }
3214
f1dc5600
S		 3215 if (eeval & AR5416_OPFLAGS_11G) {
3216 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3217 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3218 if (ah->ah_config.ht_enable) {
3219 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3220 set_bit(ATH9K_MODE_11NG_HT20,
3221 pCap->wireless_modes);
3222 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3223 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3224 pCap->wireless_modes);
3225 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3226 pCap->wireless_modes);
3227 }
3228 }
f078f209 3229 }
f1dc5600
S		 3230
3231 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3232 if ((ah->ah_isPciExpress)
3233 || (eeval & AR5416_OPFLAGS_11A)) {
3234 pCap->rx_chainmask =
3235 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
f078f209 3236 } else {
f1dc5600
S		 3237 pCap->rx_chainmask =
3238 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
f078f209
LR		 3239 }
3240
f1dc5600
S		 3241 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3242 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3243
f1dc5600
S		 3244 pCap->low_2ghz_chan = 2312;
3245 pCap->high_2ghz_chan = 2732;
f078f209 3246
f1dc5600
S		 3247 pCap->low_5ghz_chan = 4920;
3248 pCap->high_5ghz_chan = 6100;
f078f209 3249
f1dc5600
S		 3250 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3251 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3252 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3253
f1dc5600
S		 3254 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3255 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3256 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3257
f1dc5600 3258 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
f078f209 3259
f1dc5600
S		 3260 if (ah->ah_config.ht_enable)
3261 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3262 else
3263 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3264
f1dc5600
S		 3265 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3266 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3267 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3268 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3269
f1dc5600
S		 3270 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3271 pCap->total_queues =
3272 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3273 else
3274 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3275
f1dc5600
S		 3276 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3277 pCap->keycache_size =
3278 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3279 else
3280 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3281
f1dc5600
S		 3282 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3283 pCap->num_mr_retries = 4;
3284 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3285
f1dc5600
S		 3286 if (AR_SREV_9280_10_OR_LATER(ah))
3287 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3288 else
3289 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3290
f1dc5600
S		 3291 if (AR_SREV_9280_10_OR_LATER(ah)) {
3292 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3293 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3294 } else {
3295 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3296 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
f078f209
LR		 3297 }
3298
f1dc5600
S		 3299 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3300 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3301 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3302 } else {
3303 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3304 }
3305
f1dc5600
S		 3306 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3307
e97275cb 3308#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600
S		 3309 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3310 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3311 ah->ah_rfkill_gpio =
3312 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3313 ah->ah_rfkill_polarity =
3314 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3315
3316 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3317 }
f1dc5600 3318#endif
f078f209 3319
f1dc5600
S		 3320 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3321 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3322 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3323 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3324 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3325 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3326 else
f1dc5600 3327 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3328
f1dc5600
S		 3329 if (AR_SREV_9280(ah))
3330 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3331 else
3332 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3333
f1dc5600
S		 3334 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3335 pCap->reg_cap =
3336 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3337 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3338 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3339 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3340 } else {
f1dc5600
S		 3341 pCap->reg_cap =
3342 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3343 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3344 }
f078f209 3345
f1dc5600
S		 3346 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3347
3348 pCap->num_antcfg_5ghz =
3349 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3350 pCap->num_antcfg_2ghz =
3351 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
f078f209 3352
f1dc5600 3353 return true;
f078f209
LR		 3354}
3355
f1dc5600
S		 3356bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3357 u32 capability, u32 *result)
f078f209 3358{
f1dc5600
S		 3359 struct ath_hal_5416 *ahp = AH5416(ah);
3360 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
f078f209 3361
f1dc5600
S		 3362 switch (type) {
3363 case ATH9K_CAP_CIPHER:
3364 switch (capability) {
3365 case ATH9K_CIPHER_AES_CCM:
3366 case ATH9K_CIPHER_AES_OCB:
3367 case ATH9K_CIPHER_TKIP:
3368 case ATH9K_CIPHER_WEP:
3369 case ATH9K_CIPHER_MIC:
3370 case ATH9K_CIPHER_CLR:
3371 return true;
3372 default:
3373 return false;
3374 }
3375 case ATH9K_CAP_TKIP_MIC:
3376 switch (capability) {
3377 case 0:
3378 return true;
3379 case 1:
3380 return (ahp->ah_staId1Defaults &
3381 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3382 false;
3383 }
3384 case ATH9K_CAP_TKIP_SPLIT:
3385 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3386 false : true;
3387 case ATH9K_CAP_WME_TKIPMIC:
3388 return 0;
3389 case ATH9K_CAP_PHYCOUNTERS:
3390 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3391 case ATH9K_CAP_DIVERSITY:
3392 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3393 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3394 true : false;
3395 case ATH9K_CAP_PHYDIAG:
3396 return true;
3397 case ATH9K_CAP_MCAST_KEYSRCH:
3398 switch (capability) {
3399 case 0:
3400 return true;
3401 case 1:
3402 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3403 return false;
3404 } else {
3405 return (ahp->ah_staId1Defaults &
3406 AR_STA_ID1_MCAST_KSRCH) ? true :
3407 false;
3408 }
3409 }
3410 return false;
3411 case ATH9K_CAP_TSF_ADJUST:
3412 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3413 true : false;
3414 case ATH9K_CAP_RFSILENT:
3415 if (capability == 3)
3416 return false;
3417 case ATH9K_CAP_ANT_CFG_2GHZ:
3418 *result = pCap->num_antcfg_2ghz;
3419 return true;
3420 case ATH9K_CAP_ANT_CFG_5GHZ:
3421 *result = pCap->num_antcfg_5ghz;
3422 return true;
3423 case ATH9K_CAP_TXPOW:
3424 switch (capability) {
3425 case 0:
3426 return 0;
3427 case 1:
3428 *result = ah->ah_powerLimit;
3429 return 0;
3430 case 2:
3431 *result = ah->ah_maxPowerLevel;
3432 return 0;
3433 case 3:
3434 *result = ah->ah_tpScale;
3435 return 0;
3436 }
3437 return false;
3438 default:
3439 return false;
f078f209 3440 }
f078f209
LR		 3441}
3442
f1dc5600
S		 3443bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3444 u32 capability, u32 setting, int *status)
f078f209 3445{
f078f209 3446 struct ath_hal_5416 *ahp = AH5416(ah);
f1dc5600 3447 u32 v;
f078f209 3448
f1dc5600
S		 3449 switch (type) {
3450 case ATH9K_CAP_TKIP_MIC:
3451 if (setting)
3452 ahp->ah_staId1Defaults |=
3453 AR_STA_ID1_CRPT_MIC_ENABLE;
3454 else
3455 ahp->ah_staId1Defaults &=
3456 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3457 return true;
3458 case ATH9K_CAP_DIVERSITY:
3459 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3460 if (setting)
3461 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3462 else
3463 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3464 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3465 return true;
3466 case ATH9K_CAP_MCAST_KEYSRCH:
3467 if (setting)
3468 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3469 else
3470 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3471 return true;
3472 case ATH9K_CAP_TSF_ADJUST:
3473 if (setting)
3474 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3475 else
3476 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3477 return true;
3478 default:
3479 return false;
f078f209
LR		 3480 }
3481}
3482
f1dc5600
S		 3483/****************************/
3484/* GPIO / RFKILL / Antennae */
3485/****************************/
f078f209 3486
f1dc5600
S		 3487static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3488 u32 gpio, u32 type)
3489{
3490 int addr;
3491 u32 gpio_shift, tmp;
f078f209 3492
f1dc5600
S		 3493 if (gpio > 11)
3494 addr = AR_GPIO_OUTPUT_MUX3;
3495 else if (gpio > 5)
3496 addr = AR_GPIO_OUTPUT_MUX2;
3497 else
3498 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3499
f1dc5600 3500 gpio_shift = (gpio % 6) * 5;
f078f209 3501
f1dc5600
S		 3502 if (AR_SREV_9280_20_OR_LATER(ah)
3503 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3504 REG_RMW(ah, addr, (type << gpio_shift),
3505 (0x1f << gpio_shift));
f078f209 3506 } else {
f1dc5600
S		 3507 tmp = REG_READ(ah, addr);
3508 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3509 tmp &= ~(0x1f << gpio_shift);
3510 tmp |= (type << gpio_shift);
3511 REG_WRITE(ah, addr, tmp);
f078f209 3512 }
f078f209
LR		 3513}
3514
f1dc5600 3515void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
f078f209 3516{
f1dc5600 3517 u32 gpio_shift;
f078f209 3518
f1dc5600 3519 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
f078f209 3520
f1dc5600 3521 gpio_shift = gpio << 1;
f078f209 3522
f1dc5600
S		 3523 REG_RMW(ah,
3524 AR_GPIO_OE_OUT,
3525 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3526 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3527}
3528
f1dc5600 3529u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
f078f209 3530{
f1dc5600
S		 3531 if (gpio >= ah->ah_caps.num_gpio_pins)
3532 return 0xffffffff;
f078f209 3533
f1dc5600
S		 3534 if (AR_SREV_9280_10_OR_LATER(ah)) {
3535 return (MS
3536 (REG_READ(ah, AR_GPIO_IN_OUT),
3537 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3538 } else {
3539 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3540 AR_GPIO_BIT(gpio)) != 0;
3541 }
f078f209
LR		 3542}
3543
f1dc5600
S		 3544void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3545 u32 ah_signal_type)
f078f209 3546{
f1dc5600 3547 u32 gpio_shift;
f078f209 3548
f1dc5600 3549 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3550
f1dc5600 3551 gpio_shift = 2 * gpio;
f078f209 3552
f1dc5600
S		 3553 REG_RMW(ah,
3554 AR_GPIO_OE_OUT,
3555 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3556 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3557}
3558
f1dc5600 3559void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
f078f209 3560{
f1dc5600
S		 3561 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3562 AR_GPIO_BIT(gpio));
f078f209
LR		 3563}
3564
e97275cb 3565#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
f1dc5600 3566void ath9k_enable_rfkill(struct ath_hal *ah)
f078f209 3567{
f1dc5600
S		 3568 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3569 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
f078f209 3570
f1dc5600
S		 3571 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3572 AR_GPIO_INPUT_MUX2_RFSILENT);
3573
3574 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3575 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
f078f209 3576}
f1dc5600 3577#endif
f078f209 3578
f1dc5600 3579int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
f078f209 3580{
f1dc5600
S		 3581 struct ath9k_channel *chan = ah->ah_curchan;
3582 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3583 u16 ant_config;
3584 u32 halNumAntConfig;
f078f209 3585
f1dc5600
S		 3586 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3587 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
f078f209 3588
f1dc5600
S		 3589 if (cfg < halNumAntConfig) {
3590 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3591 cfg, &ant_config)) {
3592 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3593 return 0;
f078f209 3594 }
f078f209
LR		 3595 }
3596
f1dc5600 3597 return -EINVAL;
f078f209
LR		 3598}
3599
f1dc5600 3600u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
f078f209 3601{
f1dc5600 3602 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3603}
3604
f1dc5600 3605void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
f078f209 3606{
f1dc5600 3607 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3608}
3609
f1dc5600
S		 3610bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3611 enum ath9k_ant_setting settings,
3612 struct ath9k_channel *chan,
3613 u8 *tx_chainmask,
3614 u8 *rx_chainmask,
3615 u8 *antenna_cfgd)
f078f209 3616{
f1dc5600
S		 3617 struct ath_hal_5416 *ahp = AH5416(ah);
3618 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3619
f1dc5600
S		 3620 if (AR_SREV_9280(ah)) {
3621 if (!tx_chainmask_cfg) {
f078f209 3622
f1dc5600
S		 3623 tx_chainmask_cfg = *tx_chainmask;
3624 rx_chainmask_cfg = *rx_chainmask;
3625 }
f078f209 3626
f1dc5600
S		 3627 switch (settings) {
3628 case ATH9K_ANT_FIXED_A:
3629 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3630 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3631 *antenna_cfgd = true;
3632 break;
3633 case ATH9K_ANT_FIXED_B:
3634 if (ah->ah_caps.tx_chainmask >
3635 ATH9K_ANTENNA1_CHAINMASK) {
3636 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3637 }
3638 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3639 *antenna_cfgd = true;
3640 break;
3641 case ATH9K_ANT_VARIABLE:
3642 *tx_chainmask = tx_chainmask_cfg;
3643 *rx_chainmask = rx_chainmask_cfg;
3644 *antenna_cfgd = true;
3645 break;
3646 default:
3647 break;
3648 }
3649 } else {
3650 ahp->ah_diversityControl = settings;
f078f209 3651 }
f078f209 3652
f1dc5600 3653 return true;
f078f209
LR		 3654}
3655
f1dc5600
S		 3656/*********************/
3657/* General Operation */
3658/*********************/
3659
3660u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
f078f209 3661{
f1dc5600
S		 3662 u32 bits = REG_READ(ah, AR_RX_FILTER);
3663 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3664
f1dc5600
S		 3665 if (phybits & AR_PHY_ERR_RADAR)
3666 bits |= ATH9K_RX_FILTER_PHYRADAR;
3667 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3668 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3669
f1dc5600 3670 return bits;
f078f209
LR		 3671}
3672
f1dc5600 3673void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
f078f209 3674{
f1dc5600 3675 u32 phybits;
f078f209 3676
f1dc5600
S		 3677 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3678 phybits = 0;
3679 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3680 phybits |= AR_PHY_ERR_RADAR;
3681 if (bits & ATH9K_RX_FILTER_PHYERR)
3682 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3683 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3684
f1dc5600
S		 3685 if (phybits)
3686 REG_WRITE(ah, AR_RXCFG,
3687 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3688 else
3689 REG_WRITE(ah, AR_RXCFG,
3690 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3691}
f078f209 3692
f1dc5600
S		 3693bool ath9k_hw_phy_disable(struct ath_hal *ah)
3694{
3695 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3696}
f078f209 3697
f1dc5600
S		 3698bool ath9k_hw_disable(struct ath_hal *ah)
3699{
3700 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3701 return false;
f078f209 3702
f1dc5600 3703 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3704}
3705
f1dc5600 3706bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
f078f209 3707{
f1dc5600 3708 struct ath9k_channel *chan = ah->ah_curchan;
f078f209 3709
f1dc5600 3710 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3711
f1dc5600
S		 3712 if (ath9k_hw_set_txpower(ah, chan,
3713 ath9k_regd_get_ctl(ah, chan),
3714 ath9k_regd_get_antenna_allowed(ah, chan),
3715 chan->maxRegTxPower * 2,
3716 min((u32) MAX_RATE_POWER,
3717 (u32) ah->ah_powerLimit)) != 0)
6f255425 3718 return false;
f1dc5600 3719
6f255425
LR		 3720 return true;
3721}
3722
f1dc5600 3723void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
f078f209 3724{
f1dc5600 3725 struct ath_hal_5416 *ahp = AH5416(ah);
6f255425 3726
f1dc5600 3727 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
f078f209
LR		 3728}
3729
f1dc5600 3730bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
f078f209
LR		 3731{
3732 struct ath_hal_5416 *ahp = AH5416(ah);
3733
f1dc5600
S		 3734 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3735
f078f209
LR		 3736 return true;
3737}
3738
f1dc5600 3739void ath9k_hw_setopmode(struct ath_hal *ah)
f078f209 3740{
f1dc5600 3741 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
f078f209
LR		 3742}
3743
f1dc5600 3744void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
f078f209 3745{
f1dc5600
S		 3746 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3747 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3748}
3749
f1dc5600 3750void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
f078f209 3751{
f1dc5600 3752 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3753
f1dc5600 3754 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
f078f209
LR		 3755}
3756
f1dc5600 3757bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
f078f209 3758{
f1dc5600
S		 3759 struct ath_hal_5416 *ahp = AH5416(ah);
3760
3761 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
f078f209 3762
f1dc5600
S		 3763 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3764 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
f078f209
LR		 3765
3766 return true;
3767}
3768
f1dc5600 3769void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
f078f209 3770{
f1dc5600 3771 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3772
f1dc5600
S		 3773 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3774 ahp->ah_assocId = assocId;
f078f209 3775
f1dc5600
S		 3776 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3777 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3778 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 3779}
3780
f1dc5600 3781u64 ath9k_hw_gettsf64(struct ath_hal *ah)
f078f209 3782{
f1dc5600 3783 u64 tsf;
f078f209 3784
f1dc5600
S		 3785 tsf = REG_READ(ah, AR_TSF_U32);
3786 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3787
f1dc5600
S		 3788 return tsf;
3789}
f078f209 3790
f1dc5600
S		 3791void ath9k_hw_reset_tsf(struct ath_hal *ah)
3792{
3793 int count;
f078f209 3794
f1dc5600
S		 3795 count = 0;
3796 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3797 count++;
3798 if (count > 10) {
3799 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 3800 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f1dc5600 3801 break;
f078f209 3802 }
f1dc5600
S		 3803 udelay(10);
3804 }
3805 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3806}
f078f209 3807
f1dc5600
S		 3808bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3809{
3810 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3811
f1dc5600
S		 3812 if (setting)
3813 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3814 else
3815 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
f078f209 3816
f1dc5600
S		 3817 return true;
3818}
f078f209 3819
f1dc5600
S		 3820bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3821{
3822 struct ath_hal_5416 *ahp = AH5416(ah);
f078f209 3823
f1dc5600 3824 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
f1dc5600
S		 3826 ahp->ah_slottime = (u32) -1;
3827 return false;
3828 } else {
3829 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3830 ahp->ah_slottime = us;
3831 return true;
f078f209 3832 }
f1dc5600
S		 3833}
3834
3835void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3836{
3837 u32 macmode;
3838
3839 if (mode == ATH9K_HT_MACMODE_2040 &&
3840 !ah->ah_config.cwm_ignore_extcca)
3841 macmode = AR_2040_JOINED_RX_CLEAR;
3842 else
3843 macmode = 0;
f078f209 3844
f1dc5600 3845 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3846}
Linux kernel - Deliverables
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