projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k: Initialize values when setting up the queue parameters
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
c0d7c7af
LR		 290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
17d7904d 300 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 301 ath9k_ps_restore(sc);
ff37e337
S		 302 return 0;
303}
304
305/*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312static void ath_ani_calibrate(unsigned long data)
313{
20977d3e
S		 314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 320 u32 cal_interval, short_cal_interval;
ff37e337 321
20977d3e
S		 322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
0c98de65 329 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 330 goto set_timer;
ff37e337
S		 331
332 /* Long calibration runs independently of short calibration. */
17d7904d 333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 334 longcal = true;
04bd4638 335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 336 sc->ani.longcal_timer = timestamp;
ff37e337
S		 337 }
338
17d7904d
S		 339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
20977d3e 341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 346 }
347 } else {
17d7904d 348 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 349 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
351 if (sc->ani.caldone)
352 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 353 }
354 }
355
356 /* Verify whether we must check ANI */
20977d3e 357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 358 aniflag = true;
17d7904d 359 sc->ani.checkani_timer = timestamp;
ff37e337
S		 360 }
361
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
365 if (aniflag)
20977d3e 366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
2660b81a 372 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 373 sc->rx_chainmask, longcal,
ff37e337
S		 374 &iscaldone)) {
375 if (longcal)
17d7904d 376 sc->ani.noise_floor =
ff37e337 377 ath9k_hw_getchan_noise(ah,
2660b81a 378 ah->curchan);
ff37e337
S		 379
380 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 381 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 382 ah->curchan->channel,
383 ah->curchan->channelFlags,
17d7904d 384 sc->ani.noise_floor);
ff37e337
S		 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 387 "calibrate chan %u/%x failed\n",
2660b81a
S		 388 ah->curchan->channel,
389 ah->curchan->channelFlags);
ff37e337 390 }
17d7904d 391 sc->ani.caldone = iscaldone;
ff37e337
S		 392 }
393 }
394
20977d3e 395set_timer:
ff37e337
S		 396 /*
397 * Set timer interval based on previous results.
398 * The interval must be the shortest necessary to satisfy ANI,
399 * short calibration and long calibration.
400 */
aac9207e 401 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 402 if (sc->sc_ah->config.enable_ani)
aac9207e 403 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 404 if (!sc->ani.caldone)
20977d3e 405 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 406
17d7904d 407 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 408}
409
410/*
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
ff37e337 415 */
0e2dedf9 416void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 417{
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
439
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337
S		 457
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
461 return;
462 } else {
463
464 if (status &
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 466 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 467 ath_rx_tasklet(sc, 0);
b77f483f 468 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 469 }
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
472 ath_tx_tasklet(sc);
473 }
474
475 /* re-enable hardware interrupt */
17d7904d 476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 477}
478
6baff7f9 479irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 480{
481 struct ath_softc *sc = dev;
cbe61d8a 482 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 483 enum ath9k_int status;
484 bool sched = false;
485
486 do {
487 if (sc->sc_flags & SC_OP_INVALID) {
488 /*
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
492 */
493 return IRQ_NONE;
494 }
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
496 return IRQ_NONE;
497 }
498
499 /*
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
504 */
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
506
17d7904d 507 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 508
509 /*
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
512 */
513 if (!status)
514 return IRQ_NONE;
515
17d7904d 516 sc->intrstatus = status;
541d8dd5 517 ath9k_ps_wakeup(sc);
ff37e337
S		 518
519 if (status & ATH9K_INT_FATAL) {
520 /* need a chip reset */
521 sched = true;
522 } else if (status & ATH9K_INT_RXORN) {
523 /* need a chip reset */
524 sched = true;
525 } else {
526 if (status & ATH9K_INT_SWBA) {
527 /* schedule a tasklet for beacon handling */
528 tasklet_schedule(&sc->bcon_tasklet);
529 }
530 if (status & ATH9K_INT_RXEOL) {
531 /*
532 * NB: the hardware should re-read the link when
533 * RXE bit is written, but it doesn't work
534 * at least on older hardware revs.
535 */
536 sched = true;
537 }
538
539 if (status & ATH9K_INT_TXURN)
540 /* bump tx trigger level */
541 ath9k_hw_updatetxtriglevel(ah, true);
542 /* XXX: optimize this */
543 if (status & ATH9K_INT_RX)
544 sched = true;
545 if (status & ATH9K_INT_TX)
546 sched = true;
547 if (status & ATH9K_INT_BMISS)
548 sched = true;
549 /* carrier sense timeout */
550 if (status & ATH9K_INT_CST)
551 sched = true;
552 if (status & ATH9K_INT_MIB) {
553 /*
554 * Disable interrupts until we service the MIB
555 * interrupt; otherwise it will continue to
556 * fire.
557 */
558 ath9k_hw_set_interrupts(ah, 0);
559 /*
560 * Let the hal handle the event. We assume
561 * it will clear whatever condition caused
562 * the interrupt.
563 */
17d7904d
S		 564 ath9k_hw_procmibevent(ah, &sc->nodestats);
565 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 566 }
567 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 568 if (!(ah->caps.hw_caps &
ff37e337
S		 569 ATH9K_HW_CAP_AUTOSLEEP)) {
570 /* Clear RxAbort bit so that we can
571 * receive frames */
3cbb5dd7 572 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 573 ath9k_hw_setrxabort(ah, 0);
574 sched = true;
3cbb5dd7 575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 576 }
577 }
4af9cf4f
S		 578 if (status & ATH9K_INT_TSFOOR) {
579 /* FIXME: Handle this interrupt for power save */
580 sched = true;
581 }
ff37e337 582 }
541d8dd5 583 ath9k_ps_restore(sc);
ff37e337
S		 584 } while (0);
585
817e11de
S		 586 ath_debug_stat_interrupt(sc, status);
587
ff37e337
S		 588 if (sched) {
589 /* turn off every interrupt except SWBA */
17d7904d 590 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595}
596
f078f209 597static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 598 struct ieee80211_channel *chan,
094d05dc 599 enum nl80211_channel_type channel_type)
f078f209
LR		 600{
601 u32 chanmode = 0;
f078f209
LR		 602
603 switch (chan->band) {
604 case IEEE80211_BAND_2GHZ:
094d05dc
S		 605 switch(channel_type) {
606 case NL80211_CHAN_NO_HT:
607 case NL80211_CHAN_HT20:
f078f209 608 chanmode = CHANNEL_G_HT20;
094d05dc
S		 609 break;
610 case NL80211_CHAN_HT40PLUS:
f078f209 611 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 612 break;
613 case NL80211_CHAN_HT40MINUS:
f078f209 614 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 615 break;
616 }
f078f209
LR		 617 break;
618 case IEEE80211_BAND_5GHZ:
094d05dc
S		 619 switch(channel_type) {
620 case NL80211_CHAN_NO_HT:
621 case NL80211_CHAN_HT20:
f078f209 622 chanmode = CHANNEL_A_HT20;
094d05dc
S		 623 break;
624 case NL80211_CHAN_HT40PLUS:
f078f209 625 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 626 break;
627 case NL80211_CHAN_HT40MINUS:
f078f209 628 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 629 break;
630 }
f078f209
LR		 631 break;
632 default:
633 break;
634 }
635
636 return chanmode;
637}
638
6ace2891 639static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 640 struct ath9k_keyval *hk, const u8 *addr,
641 bool authenticator)
f078f209 642{
6ace2891
JM		 643 const u8 *key_rxmic;
644 const u8 *key_txmic;
f078f209 645
6ace2891
JM		 646 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
647 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 648
649 if (addr == NULL) {
d216aaa6
JM		 650 /*
651 * Group key installation - only two key cache entries are used
652 * regardless of splitmic capability since group key is only
653 * used either for TX or RX.
654 */
3f53dd64
JM		 655 if (authenticator) {
656 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
657 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
658 } else {
659 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
661 }
d216aaa6 662 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 663 }
17d7904d 664 if (!sc->splitmic) {
d216aaa6 665 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 668 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 669 }
d216aaa6
JM		 670
671 /* Separate key cache entries for TX and RX */
672
673 /* TX key goes at first index, RX key at +32. */
f078f209 674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 675 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
676 /* TX MIC entry failed. No need to proceed further */
d8baa939 677 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 678 "Setting TX MIC Key Failed\n");
f078f209
LR		 679 return 0;
680 }
681
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 /* XXX delete tx key on failure? */
d216aaa6 684 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 685}
686
687static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
688{
689 int i;
690
17d7904d
S		 691 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
692 if (test_bit(i, sc->keymap) ||
693 test_bit(i + 64, sc->keymap))
6ace2891 694 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 695 if (sc->splitmic &&
696 (test_bit(i + 32, sc->keymap) ||
697 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 698 continue; /* At least one part of TKIP key allocated */
699
700 /* Found a free slot for a TKIP key */
701 return i;
702 }
703 return -1;
704}
705
706static int ath_reserve_key_cache_slot(struct ath_softc *sc)
707{
708 int i;
709
710 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 711 if (sc->splitmic) {
712 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
713 if (!test_bit(i, sc->keymap) &&
714 (test_bit(i + 32, sc->keymap) ||
715 test_bit(i + 64, sc->keymap) ||
716 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 717 return i;
17d7904d
S		 718 if (!test_bit(i + 32, sc->keymap) &&
719 (test_bit(i, sc->keymap) ||
720 test_bit(i + 64, sc->keymap) ||
721 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 722 return i + 32;
17d7904d
S		 723 if (!test_bit(i + 64, sc->keymap) &&
724 (test_bit(i , sc->keymap) ||
725 test_bit(i + 32, sc->keymap) ||
726 test_bit(i + 64 + 32, sc->keymap)))
ea612132 727 return i + 64;
17d7904d
S		 728 if (!test_bit(i + 64 + 32, sc->keymap) &&
729 (test_bit(i, sc->keymap) ||
730 test_bit(i + 32, sc->keymap) ||
731 test_bit(i + 64, sc->keymap)))
ea612132 732 return i + 64 + 32;
6ace2891
JM		 733 }
734 } else {
17d7904d
S		 735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 test_bit(i + 64, sc->keymap))
6ace2891 738 return i;
17d7904d
S		 739 if (test_bit(i, sc->keymap) &&
740 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 741 return i + 64;
742 }
743 }
744
745 /* No partially used TKIP slots, pick any available slot */
17d7904d 746 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 747 /* Do not allow slots that could be needed for TKIP group keys
748 * to be used. This limitation could be removed if we know that
749 * TKIP will not be used. */
750 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
751 continue;
17d7904d 752 if (sc->splitmic) {
be2864cf
JM		 753 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
754 continue;
755 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
756 continue;
757 }
758
17d7904d 759 if (!test_bit(i, sc->keymap))
6ace2891
JM		 760 return i; /* Found a free slot for a key */
761 }
762
763 /* No free slot found */
764 return -1;
f078f209
LR		 765}
766
767static int ath_key_config(struct ath_softc *sc,
3f53dd64 768 struct ieee80211_vif *vif,
dc822b5d 769 struct ieee80211_sta *sta,
f078f209
LR		 770 struct ieee80211_key_conf *key)
771{
f078f209
LR		 772 struct ath9k_keyval hk;
773 const u8 *mac = NULL;
774 int ret = 0;
6ace2891 775 int idx;
f078f209
LR		 776
777 memset(&hk, 0, sizeof(hk));
778
779 switch (key->alg) {
780 case ALG_WEP:
781 hk.kv_type = ATH9K_CIPHER_WEP;
782 break;
783 case ALG_TKIP:
784 hk.kv_type = ATH9K_CIPHER_TKIP;
785 break;
786 case ALG_CCMP:
787 hk.kv_type = ATH9K_CIPHER_AES_CCM;
788 break;
789 default:
ca470b29 790 return -EOPNOTSUPP;
f078f209
LR		 791 }
792
6ace2891 793 hk.kv_len = key->keylen;
f078f209
LR		 794 memcpy(hk.kv_val, key->key, key->keylen);
795
6ace2891
JM		 796 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
797 /* For now, use the default keys for broadcast keys. This may
798 * need to change with virtual interfaces. */
799 idx = key->keyidx;
800 } else if (key->keyidx) {
dc822b5d
JB		 801 if (WARN_ON(!sta))
802 return -EOPNOTSUPP;
803 mac = sta->addr;
804
6ace2891
JM		 805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
808 idx = key->keyidx;
809 } else
810 return -EIO;
f078f209 811 } else {
dc822b5d
JB		 812 if (WARN_ON(!sta))
813 return -EOPNOTSUPP;
814 mac = sta->addr;
815
6ace2891
JM		 816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
818 else
819 idx = ath_reserve_key_cache_slot(sc);
820 if (idx < 0)
ca470b29 821 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 822 }
823
824 if (key->alg == ALG_TKIP)
3f53dd64
JM		 825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
826 vif->type == NL80211_IFTYPE_AP);
f078f209 827 else
d216aaa6 828 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 829
830 if (!ret)
831 return -EIO;
832
17d7904d 833 set_bit(idx, sc->keymap);
6ace2891 834 if (key->alg == ALG_TKIP) {
17d7904d
S		 835 set_bit(idx + 64, sc->keymap);
836 if (sc->splitmic) {
837 set_bit(idx + 32, sc->keymap);
838 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 839 }
840 }
841
842 return idx;
f078f209
LR		 843}
844
845static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
846{
6ace2891
JM		 847 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
848 if (key->hw_key_idx < IEEE80211_WEP_NKID)
849 return;
850
17d7904d 851 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 852 if (key->alg != ALG_TKIP)
853 return;
f078f209 854
17d7904d
S		 855 clear_bit(key->hw_key_idx + 64, sc->keymap);
856 if (sc->splitmic) {
857 clear_bit(key->hw_key_idx + 32, sc->keymap);
858 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 859 }
f078f209
LR		 860}
861
eb2599ca
S		 862static void setup_ht_cap(struct ath_softc *sc,
863 struct ieee80211_sta_ht_cap *ht_info)
f078f209 864{
60653678
S		 865#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
866#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 867
d9fe60de
JB		 868 ht_info->ht_supported = true;
869 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
870 IEEE80211_HT_CAP_SM_PS |
871 IEEE80211_HT_CAP_SGI_40 |
872 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 873
60653678
S		 874 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
875 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 876
d9fe60de
JB		 877 /* set up supported mcs set */
878 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 879
17d7904d 880 switch(sc->rx_chainmask) {
eb2599ca
S		 881 case 1:
882 ht_info->mcs.rx_mask[0] = 0xff;
883 break;
3c457265 884 case 3:
eb2599ca
S		 885 case 5:
886 case 7:
887 default:
888 ht_info->mcs.rx_mask[0] = 0xff;
889 ht_info->mcs.rx_mask[1] = 0xff;
890 break;
891 }
892
d9fe60de 893 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 894}
895
8feceb67 896static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 897 struct ieee80211_vif *vif,
8feceb67 898 struct ieee80211_bss_conf *bss_conf)
f078f209 899{
17d7904d 900 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 901
8feceb67 902 if (bss_conf->assoc) {
094d05dc 903 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 904 bss_conf->aid, sc->curbssid);
f078f209 905
8feceb67 906 /* New association, store aid */
d97809db 907 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 908 sc->curaid = bss_conf->aid;
ba52da58 909 ath9k_hw_write_associd(sc);
8feceb67 910 }
f078f209 911
8feceb67 912 /* Configure the beacon */
2c3db3d5 913 ath_beacon_config(sc, vif);
f078f209 914
8feceb67 915 /* Reset rssi stats */
17d7904d
S		 916 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
917 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 920
6f255425 921 /* Start ANI */
17d7904d 922 mod_timer(&sc->ani.timer,
20977d3e 923 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 924 } else {
1ffb0610 925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 926 sc->curaid = 0;
f078f209 927 }
8feceb67 928}
f078f209 929
8feceb67
VT		 930/********************************/
931/* LED functions */
932/********************************/
f078f209 933
f2bffa7e
VT		 934static void ath_led_blink_work(struct work_struct *work)
935{
936 struct ath_softc *sc = container_of(work, struct ath_softc,
937 ath_led_blink_work.work);
938
939 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
940 return;
85067c06
VT		 941
942 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
943 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
944 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
945 else
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 948
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
953
85067c06
VT		 954 sc->led_on_duration = sc->led_on_cnt ?
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
956 ATH_LED_ON_DURATION_IDLE;
957 sc->led_off_duration = sc->led_off_cnt ?
958 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
959 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 960 sc->led_on_cnt = sc->led_off_cnt = 0;
961 if (sc->sc_flags & SC_OP_LED_ON)
962 sc->sc_flags &= ~SC_OP_LED_ON;
963 else
964 sc->sc_flags |= SC_OP_LED_ON;
965}
966
8feceb67
VT		 967static void ath_led_brightness(struct led_classdev *led_cdev,
968 enum led_brightness brightness)
969{
970 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
971 struct ath_softc *sc = led->sc;
f078f209 972
8feceb67
VT		 973 switch (brightness) {
974 case LED_OFF:
975 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 976 led->led_type == ATH_LED_RADIO) {
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (led->led_type == ATH_LED_RADIO));
8feceb67 979 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 980 if (led->led_type == ATH_LED_RADIO)
981 sc->sc_flags &= ~SC_OP_LED_ON;
982 } else {
983 sc->led_off_cnt++;
984 }
8feceb67
VT		 985 break;
986 case LED_FULL:
f2bffa7e 987 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 988 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 989 queue_delayed_work(sc->hw->workqueue,
990 &sc->ath_led_blink_work, 0);
991 } else if (led->led_type == ATH_LED_RADIO) {
992 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
993 sc->sc_flags |= SC_OP_LED_ON;
994 } else {
995 sc->led_on_cnt++;
996 }
8feceb67
VT		 997 break;
998 default:
999 break;
f078f209 1000 }
8feceb67 1001}
f078f209 1002
8feceb67
VT		 1003static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1004 char *trigger)
1005{
1006 int ret;
f078f209 1007
8feceb67
VT		 1008 led->sc = sc;
1009 led->led_cdev.name = led->name;
1010 led->led_cdev.default_trigger = trigger;
1011 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1012
8feceb67
VT		 1013 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1014 if (ret)
1015 DPRINTF(sc, ATH_DBG_FATAL,
1016 "Failed to register led:%s", led->name);
1017 else
1018 led->registered = 1;
1019 return ret;
1020}
f078f209 1021
8feceb67
VT		 1022static void ath_unregister_led(struct ath_led *led)
1023{
1024 if (led->registered) {
1025 led_classdev_unregister(&led->led_cdev);
1026 led->registered = 0;
f078f209 1027 }
f078f209
LR		 1028}
1029
8feceb67 1030static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1031{
f2bffa7e 1032 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1033 ath_unregister_led(&sc->assoc_led);
1034 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1035 ath_unregister_led(&sc->tx_led);
1036 ath_unregister_led(&sc->rx_led);
1037 ath_unregister_led(&sc->radio_led);
1038 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1039}
f078f209 1040
8feceb67
VT		 1041static void ath_init_leds(struct ath_softc *sc)
1042{
1043 char *trigger;
1044 int ret;
f078f209 1045
8feceb67
VT		 1046 /* Configure gpio 1 for output */
1047 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1048 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1049 /* LED off, active low */
1050 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1051
f2bffa7e
VT		 1052 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1053
8feceb67
VT		 1054 trigger = ieee80211_get_radio_led_name(sc->hw);
1055 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1056 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1057 ret = ath_register_led(sc, &sc->radio_led, trigger);
1058 sc->radio_led.led_type = ATH_LED_RADIO;
1059 if (ret)
1060 goto fail;
7dcfdcd9 1061
8feceb67
VT		 1062 trigger = ieee80211_get_assoc_led_name(sc->hw);
1063 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1064 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1065 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1066 sc->assoc_led.led_type = ATH_LED_ASSOC;
1067 if (ret)
1068 goto fail;
f078f209 1069
8feceb67
VT		 1070 trigger = ieee80211_get_tx_led_name(sc->hw);
1071 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1072 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1073 ret = ath_register_led(sc, &sc->tx_led, trigger);
1074 sc->tx_led.led_type = ATH_LED_TX;
1075 if (ret)
1076 goto fail;
f078f209 1077
8feceb67
VT		 1078 trigger = ieee80211_get_rx_led_name(sc->hw);
1079 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1080 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1081 ret = ath_register_led(sc, &sc->rx_led, trigger);
1082 sc->rx_led.led_type = ATH_LED_RX;
1083 if (ret)
1084 goto fail;
f078f209 1085
8feceb67
VT		 1086 return;
1087
1088fail:
1089 ath_deinit_leds(sc);
f078f209
LR		 1090}
1091
7ec3e514 1092void ath_radio_enable(struct ath_softc *sc)
500c064d 1093{
cbe61d8a 1094 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1095 struct ieee80211_channel *channel = sc->hw->conf.channel;
1096 int r;
500c064d 1097
3cbb5dd7 1098 ath9k_ps_wakeup(sc);
500c064d 1099 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1100
2660b81a 1101 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1102
1103 if (r) {
500c064d 1104 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1105 "Unable to reset channel %u (%uMhz) ",
1106 "reset status %u\n",
1107 channel->center_freq, r);
500c064d
VT		 1108 }
1109 spin_unlock_bh(&sc->sc_resetlock);
1110
1111 ath_update_txpow(sc);
1112 if (ath_startrecv(sc) != 0) {
1113 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1114 "Unable to restart recv logic\n");
500c064d
VT		 1115 return;
1116 }
1117
1118 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1119 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1120
1121 /* Re-Enable interrupts */
17d7904d 1122 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1123
1124 /* Enable LED */
1125 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1128
1129 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1130 ath9k_ps_restore(sc);
500c064d
VT		 1131}
1132
7ec3e514 1133void ath_radio_disable(struct ath_softc *sc)
500c064d 1134{
cbe61d8a 1135 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1136 struct ieee80211_channel *channel = sc->hw->conf.channel;
1137 int r;
500c064d 1138
3cbb5dd7 1139 ath9k_ps_wakeup(sc);
500c064d
VT		 1140 ieee80211_stop_queues(sc->hw);
1141
1142 /* Disable LED */
1143 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1144 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1145
1146 /* Disable interrupts */
1147 ath9k_hw_set_interrupts(ah, 0);
1148
043a0405 1149 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1150 ath_stoprecv(sc); /* turn off frame recv */
1151 ath_flushrecv(sc); /* flush recv queue */
1152
1153 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1154 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1155 if (r) {
500c064d 1156 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1157 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1158 "reset status %u\n",
1159 channel->center_freq, r);
500c064d
VT		 1160 }
1161 spin_unlock_bh(&sc->sc_resetlock);
1162
1163 ath9k_hw_phy_disable(ah);
1164 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1165 ath9k_ps_restore(sc);
500c064d
VT		 1166}
1167
5077fd35
GJ		 1168#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1169
1170/*******************/
1171/* Rfkill */
1172/*******************/
1173
500c064d
VT		 1174static bool ath_is_rfkill_set(struct ath_softc *sc)
1175{
cbe61d8a 1176 struct ath_hw *ah = sc->sc_ah;
500c064d 1177
2660b81a
S		 1178 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1179 ah->rfkill_polarity;
500c064d
VT		 1180}
1181
1182/* h/w rfkill poll function */
1183static void ath_rfkill_poll(struct work_struct *work)
1184{
1185 struct ath_softc *sc = container_of(work, struct ath_softc,
1186 rf_kill.rfkill_poll.work);
1187 bool radio_on;
1188
1189 if (sc->sc_flags & SC_OP_INVALID)
1190 return;
1191
1192 radio_on = !ath_is_rfkill_set(sc);
1193
1194 /*
1195 * enable/disable radio only when there is a
1196 * state change in RF switch
1197 */
1198 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1199 enum rfkill_state state;
1200
1201 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1202 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1203 : RFKILL_STATE_HARD_BLOCKED;
1204 } else if (radio_on) {
1205 ath_radio_enable(sc);
1206 state = RFKILL_STATE_UNBLOCKED;
1207 } else {
1208 ath_radio_disable(sc);
1209 state = RFKILL_STATE_HARD_BLOCKED;
1210 }
1211
1212 if (state == RFKILL_STATE_HARD_BLOCKED)
1213 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1214 else
1215 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1216
1217 rfkill_force_state(sc->rf_kill.rfkill, state);
1218 }
1219
1220 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1221 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1222}
1223
1224/* s/w rfkill handler */
1225static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1226{
1227 struct ath_softc *sc = data;
1228
1229 switch (state) {
1230 case RFKILL_STATE_SOFT_BLOCKED:
1231 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1232 SC_OP_RFKILL_SW_BLOCKED)))
1233 ath_radio_disable(sc);
1234 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1235 return 0;
1236 case RFKILL_STATE_UNBLOCKED:
1237 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1238 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1239 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1240 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1241 "radio as it is disabled by h/w\n");
500c064d
VT		 1242 return -EPERM;
1243 }
1244 ath_radio_enable(sc);
1245 }
1246 return 0;
1247 default:
1248 return -EINVAL;
1249 }
1250}
1251
1252/* Init s/w rfkill */
1253static int ath_init_sw_rfkill(struct ath_softc *sc)
1254{
1255 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1256 RFKILL_TYPE_WLAN);
1257 if (!sc->rf_kill.rfkill) {
1258 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1259 return -ENOMEM;
1260 }
1261
1262 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1263 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1264 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1265 sc->rf_kill.rfkill->data = sc;
1266 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1267 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
500c064d
VT		 1268
1269 return 0;
1270}
1271
1272/* Deinitialize rfkill */
1273static void ath_deinit_rfkill(struct ath_softc *sc)
1274{
2660b81a 1275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1276 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1277
1278 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1279 rfkill_unregister(sc->rf_kill.rfkill);
1280 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1281 sc->rf_kill.rfkill = NULL;
1282 }
1283}
9c84b797
S		 1284
1285static int ath_start_rfkill_poll(struct ath_softc *sc)
1286{
2660b81a 1287 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1288 queue_delayed_work(sc->hw->workqueue,
1289 &sc->rf_kill.rfkill_poll, 0);
1290
1291 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1292 if (rfkill_register(sc->rf_kill.rfkill)) {
1293 DPRINTF(sc, ATH_DBG_FATAL,
1294 "Unable to register rfkill\n");
1295 rfkill_free(sc->rf_kill.rfkill);
1296
1297 /* Deinitialize the device */
39c3c2f2 1298 ath_cleanup(sc);
9c84b797
S		 1299 return -EIO;
1300 } else {
1301 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1302 }
1303 }
1304
1305 return 0;
1306}
500c064d
VT		 1307#endif /* CONFIG_RFKILL */
1308
6baff7f9 1309void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1310{
1311 ath_detach(sc);
1312 free_irq(sc->irq, sc);
1313 ath_bus_cleanup(sc);
c52f33d0 1314 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1315 ieee80211_free_hw(sc->hw);
1316}
1317
6baff7f9 1318void ath_detach(struct ath_softc *sc)
f078f209 1319{
8feceb67 1320 struct ieee80211_hw *hw = sc->hw;
9c84b797 1321 int i = 0;
f078f209 1322
3cbb5dd7
VN		 1323 ath9k_ps_wakeup(sc);
1324
04bd4638 1325 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1326
e97275cb 1327#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1328 ath_deinit_rfkill(sc);
1329#endif
3fcdfb4b 1330 ath_deinit_leds(sc);
0e2dedf9 1331 cancel_work_sync(&sc->chan_work);
f98c3bd2 1332 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1333
c52f33d0
JM		 1334 for (i = 0; i < sc->num_sec_wiphy; i++) {
1335 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1336 if (aphy == NULL)
1337 continue;
1338 sc->sec_wiphy[i] = NULL;
1339 ieee80211_unregister_hw(aphy->hw);
1340 ieee80211_free_hw(aphy->hw);
1341 }
3fcdfb4b 1342 ieee80211_unregister_hw(hw);
8feceb67
VT		 1343 ath_rx_cleanup(sc);
1344 ath_tx_cleanup(sc);
f078f209 1345
9c84b797
S		 1346 tasklet_kill(&sc->intr_tq);
1347 tasklet_kill(&sc->bcon_tasklet);
f078f209 1348
9c84b797
S		 1349 if (!(sc->sc_flags & SC_OP_INVALID))
1350 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1351
9c84b797
S		 1352 /* cleanup tx queues */
1353 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1354 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1355 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1356
1357 ath9k_hw_detach(sc->sc_ah);
826d2680 1358 ath9k_exit_debug(sc);
3cbb5dd7 1359 ath9k_ps_restore(sc);
f078f209
LR		 1360}
1361
ff37e337
S		 1362static int ath_init(u16 devid, struct ath_softc *sc)
1363{
cbe61d8a 1364 struct ath_hw *ah = NULL;
ff37e337
S		 1365 int status;
1366 int error = 0, i;
1367 int csz = 0;
1368
1369 /* XXX: hardware will not be ready until ath_open() being called */
1370 sc->sc_flags |= SC_OP_INVALID;
88b126af 1371
826d2680
S		 1372 if (ath9k_init_debug(sc) < 0)
1373 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1374
c52f33d0 1375 spin_lock_init(&sc->wiphy_lock);
ff37e337 1376 spin_lock_init(&sc->sc_resetlock);
6158425b 1377 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1378 mutex_init(&sc->mutex);
ff37e337 1379 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1380 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1381 (unsigned long)sc);
1382
1383 /*
1384 * Cache line size is used to size and align various
1385 * structures used to communicate with the hardware.
1386 */
88d15707 1387 ath_read_cachesize(sc, &csz);
ff37e337 1388 /* XXX assert csz is non-zero */
17d7904d 1389 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1390
cbe61d8a 1391 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1392 if (ah == NULL) {
1393 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1394 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1395 error = -ENXIO;
1396 goto bad;
1397 }
1398 sc->sc_ah = ah;
1399
1400 /* Get the hardware key cache size. */
2660b81a 1401 sc->keymax = ah->caps.keycache_size;
17d7904d 1402 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1403 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1404 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1405 ATH_KEYMAX, sc->keymax);
1406 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1407 }
1408
1409 /*
1410 * Reset the key cache since some parts do not
1411 * reset the contents on initial power up.
1412 */
17d7904d 1413 for (i = 0; i < sc->keymax; i++)
ff37e337 1414 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1415
5f8e077c 1416 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1417 goto bad;
1418
1419 /* default to MONITOR mode */
2660b81a 1420 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1421
ff37e337
S		 1422 /* Setup rate tables */
1423
1424 ath_rate_attach(sc);
1425 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1426 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1427
1428 /*
1429 * Allocate hardware transmit queues: one queue for
1430 * beacon frames and one data queue for each QoS
1431 * priority. Note that the hal handles reseting
1432 * these queues at the needed time.
1433 */
b77f483f
S		 1434 sc->beacon.beaconq = ath_beaconq_setup(ah);
1435 if (sc->beacon.beaconq == -1) {
ff37e337 1436 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1437 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1438 error = -EIO;
1439 goto bad2;
1440 }
b77f483f
S		 1441 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1442 if (sc->beacon.cabq == NULL) {
ff37e337 1443 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1444 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1445 error = -EIO;
1446 goto bad2;
1447 }
1448
17d7904d 1449 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1450 ath_cabq_update(sc);
1451
b77f483f
S		 1452 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1453 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1454
1455 /* Setup data queues */
1456 /* NB: ensure BK queue is the lowest priority h/w queue */
1457 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1458 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1459 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1460 error = -EIO;
1461 goto bad2;
1462 }
1463
1464 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1465 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1466 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1467 error = -EIO;
1468 goto bad2;
1469 }
1470 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1471 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1472 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1473 error = -EIO;
1474 goto bad2;
1475 }
1476 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1477 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1478 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1479 error = -EIO;
1480 goto bad2;
1481 }
1482
1483 /* Initializes the noise floor to a reasonable default value.
1484 * Later on this will be updated during ANI processing. */
1485
17d7904d
S		 1486 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1487 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1488
1489 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1490 ATH9K_CIPHER_TKIP, NULL)) {
1491 /*
1492 * Whether we should enable h/w TKIP MIC.
1493 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1494 * report WMM capable, so it's always safe to turn on
1495 * TKIP MIC in this case.
1496 */
1497 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1498 0, 1, NULL);
1499 }
1500
1501 /*
1502 * Check whether the separate key cache entries
1503 * are required to handle both tx+rx MIC keys.
1504 * With split mic keys the number of stations is limited
1505 * to 27 otherwise 59.
1506 */
1507 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1508 ATH9K_CIPHER_TKIP, NULL)
1509 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1510 ATH9K_CIPHER_MIC, NULL)
1511 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1512 0, NULL))
17d7904d 1513 sc->splitmic = 1;
ff37e337
S		 1514
1515 /* turn on mcast key search if possible */
1516 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1517 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1518 1, NULL);
1519
17d7904d 1520 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1521
1522 /* 11n Capabilities */
2660b81a 1523 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1524 sc->sc_flags |= SC_OP_TXAGGR;
1525 sc->sc_flags |= SC_OP_RXAGGR;
1526 }
1527
2660b81a
S		 1528 sc->tx_chainmask = ah->caps.tx_chainmask;
1529 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1530
1531 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1532 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1533
8ca21f01 1534 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1535 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1536
b77f483f 1537 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1538
1539 /* initialize beacon slots */
c52f33d0 1540 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1541 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1542 sc->beacon.bslot_aphy[i] = NULL;
1543 }
ff37e337 1544
ff37e337
S		 1545 /* setup channels and rates */
1546
5f8e077c 1547 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1548 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1549 sc->rates[IEEE80211_BAND_2GHZ];
1550 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1551 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1552 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1553
2660b81a 1554 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1555 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1556 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1557 sc->rates[IEEE80211_BAND_5GHZ];
1558 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1559 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1560 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1561 }
1562
2660b81a 1563 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1564 ath9k_hw_btcoex_enable(sc->sc_ah);
1565
ff37e337
S		 1566 return 0;
1567bad2:
1568 /* cleanup tx queues */
1569 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1570 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1571 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1572bad:
1573 if (ah)
1574 ath9k_hw_detach(ah);
40b130a9 1575 ath9k_exit_debug(sc);
ff37e337
S		 1576
1577 return error;
1578}
1579
c52f33d0 1580void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1581{
9c84b797
S		 1582 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1583 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1584 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1585 IEEE80211_HW_AMPDU_AGGREGATION |
1586 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1587 IEEE80211_HW_PS_NULLFUNC_STACK |
1588 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1589
b3bd89ce 1590 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1591 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1592
9c84b797
S		 1593 hw->wiphy->interface_modes =
1594 BIT(NL80211_IFTYPE_AP) |
1595 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1596 BIT(NL80211_IFTYPE_ADHOC) |
1597 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1598
5f8e077c
LR		 1599 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1600 hw->wiphy->strict_regulatory = true;
1601
8feceb67 1602 hw->queues = 4;
e63835b0 1603 hw->max_rates = 4;
171387ef 1604 hw->channel_change_time = 5000;
465ca84d 1605 hw->max_listen_interval = 10;
e63835b0 1606 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1607 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1608 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1609
8feceb67 1610 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1611
c52f33d0
JM		 1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1613 &sc->sbands[IEEE80211_BAND_2GHZ];
1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1615 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616 &sc->sbands[IEEE80211_BAND_5GHZ];
1617}
1618
1619int ath_attach(u16 devid, struct ath_softc *sc)
1620{
1621 struct ieee80211_hw *hw = sc->hw;
1622 const struct ieee80211_regdomain *regd;
1623 int error = 0, i;
1624
1625 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1626
1627 error = ath_init(devid, sc);
1628 if (error != 0)
1629 return error;
1630
1631 /* get mac address from hardware and set in mac80211 */
1632
1633 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1634
1635 ath_set_hw_capab(sc, hw);
1636
2660b81a 1637 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1638 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1639 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1640 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1641 }
1642
db93e7b5
SB		 1643 /* initialize tx/rx engine */
1644 error = ath_tx_init(sc, ATH_TXBUF);
1645 if (error != 0)
40b130a9 1646 goto error_attach;
8feceb67 1647
db93e7b5
SB		 1648 error = ath_rx_init(sc, ATH_RXBUF);
1649 if (error != 0)
40b130a9 1650 goto error_attach;
8feceb67 1651
e97275cb 1652#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1653 /* Initialze h/w Rfkill */
2660b81a 1654 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1655 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1656
1657 /* Initialize s/w rfkill */
40b130a9
VT		 1658 error = ath_init_sw_rfkill(sc);
1659 if (error)
1660 goto error_attach;
500c064d
VT		 1661#endif
1662
5f8e077c 1663 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1664 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1665 * saved on the wiphy orig_* parameters */
191a99b7 1666 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1667 hw->wiphy->custom_regulatory = true;
1668 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1669 } else {
1670 /* This gets applied in the case of the absense of CRDA,
191a99b7 1671 * it's our own custom world regulatory domain, similar to
5f8e077c 1672 * cfg80211's but we enable passive scanning */
191a99b7 1673 regd = ath9k_default_world_regdomain();
5f8e077c 1674 }
191a99b7
BC		 1675 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1676 ath9k_reg_apply_radar_flags(hw->wiphy);
7db90f4a 1677 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
5f8e077c 1678
0e2dedf9 1679 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1680 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1681 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1682
db93e7b5 1683 error = ieee80211_register_hw(hw);
8feceb67 1684
fe33eb39
LR		 1685 if (!ath9k_is_world_regd(sc->sc_ah)) {
1686 error = regulatory_hint(hw->wiphy,
1687 sc->sc_ah->regulatory.alpha2);
1688 if (error)
1689 goto error_attach;
1690 }
5f8e077c 1691
db93e7b5
SB		 1692 /* Initialize LED control */
1693 ath_init_leds(sc);
8feceb67 1694
5f8e077c 1695
8feceb67 1696 return 0;
40b130a9
VT		 1697
1698error_attach:
1699 /* cleanup tx queues */
1700 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1701 if (ATH_TXQ_SETUP(sc, i))
1702 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1703
1704 ath9k_hw_detach(sc->sc_ah);
1705 ath9k_exit_debug(sc);
1706
8feceb67 1707 return error;
f078f209
LR		 1708}
1709
ff37e337
S		 1710int ath_reset(struct ath_softc *sc, bool retry_tx)
1711{
cbe61d8a 1712 struct ath_hw *ah = sc->sc_ah;
030bb495 1713 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1714 int r;
ff37e337
S		 1715
1716 ath9k_hw_set_interrupts(ah, 0);
043a0405 1717 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1718 ath_stoprecv(sc);
1719 ath_flushrecv(sc);
1720
1721 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1722 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1723 if (r)
ff37e337 1724 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1725 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1726 spin_unlock_bh(&sc->sc_resetlock);
1727
1728 if (ath_startrecv(sc) != 0)
04bd4638 1729 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1730
1731 /*
1732 * We may be doing a reset in response to a request
1733 * that changes the channel so update any state that
1734 * might change as a result.
1735 */
ce111bad 1736 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1737
1738 ath_update_txpow(sc);
1739
1740 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1741 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1742
17d7904d 1743 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1744
1745 if (retry_tx) {
1746 int i;
1747 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1748 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1749 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1750 ath_txq_schedule(sc, &sc->tx.txq[i]);
1751 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1752 }
1753 }
1754 }
1755
ae8d2858 1756 return r;
ff37e337
S		 1757}
1758
1759/*
1760 * This function will allocate both the DMA descriptor structure, and the
1761 * buffers it contains. These are used to contain the descriptors used
1762 * by the system.
1763*/
1764int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1765 struct list_head *head, const char *name,
1766 int nbuf, int ndesc)
1767{
1768#define DS2PHYS(_dd, _ds) \
1769 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1770#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1771#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1772
1773 struct ath_desc *ds;
1774 struct ath_buf *bf;
1775 int i, bsize, error;
1776
04bd4638
S		 1777 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1778 name, nbuf, ndesc);
ff37e337 1779
b03a9db9 1780 INIT_LIST_HEAD(head);
ff37e337
S		 1781 /* ath_desc must be a multiple of DWORDs */
1782 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1783 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1784 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1785 error = -ENOMEM;
1786 goto fail;
1787 }
1788
ff37e337
S		 1789 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1790
1791 /*
1792 * Need additional DMA memory because we can't use
1793 * descriptors that cross the 4K page boundary. Assume
1794 * one skipped descriptor per 4K page.
1795 */
2660b81a 1796 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1797 u32 ndesc_skipped =
1798 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1799 u32 dma_len;
1800
1801 while (ndesc_skipped) {
1802 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1803 dd->dd_desc_len += dma_len;
1804
1805 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1806 };
1807 }
1808
1809 /* allocate descriptors */
7da3c55c 1810 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1811 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1812 if (dd->dd_desc == NULL) {
1813 error = -ENOMEM;
1814 goto fail;
1815 }
1816 ds = dd->dd_desc;
04bd4638 1817 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1818 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1819 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1820
1821 /* allocate buffers */
1822 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1823 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1824 if (bf == NULL) {
1825 error = -ENOMEM;
1826 goto fail2;
1827 }
ff37e337
S		 1828 dd->dd_bufptr = bf;
1829
ff37e337
S		 1830 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1831 bf->bf_desc = ds;
1832 bf->bf_daddr = DS2PHYS(dd, ds);
1833
2660b81a 1834 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1835 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1836 /*
1837 * Skip descriptor addresses which can cause 4KB
1838 * boundary crossing (addr + length) with a 32 dword
1839 * descriptor fetch.
1840 */
1841 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1842 ASSERT((caddr_t) bf->bf_desc <
1843 ((caddr_t) dd->dd_desc +
1844 dd->dd_desc_len));
1845
1846 ds += ndesc;
1847 bf->bf_desc = ds;
1848 bf->bf_daddr = DS2PHYS(dd, ds);
1849 }
1850 }
1851 list_add_tail(&bf->list, head);
1852 }
1853 return 0;
1854fail2:
7da3c55c
GJ		 1855 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1856 dd->dd_desc_paddr);
ff37e337
S		 1857fail:
1858 memset(dd, 0, sizeof(*dd));
1859 return error;
1860#undef ATH_DESC_4KB_BOUND_CHECK
1861#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1862#undef DS2PHYS
1863}
1864
1865void ath_descdma_cleanup(struct ath_softc *sc,
1866 struct ath_descdma *dd,
1867 struct list_head *head)
1868{
7da3c55c
GJ		 1869 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1870 dd->dd_desc_paddr);
ff37e337
S		 1871
1872 INIT_LIST_HEAD(head);
1873 kfree(dd->dd_bufptr);
1874 memset(dd, 0, sizeof(*dd));
1875}
1876
1877int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1878{
1879 int qnum;
1880
1881 switch (queue) {
1882 case 0:
b77f483f 1883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1884 break;
1885 case 1:
b77f483f 1886 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1887 break;
1888 case 2:
b77f483f 1889 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1890 break;
1891 case 3:
b77f483f 1892 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1893 break;
1894 default:
b77f483f 1895 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1896 break;
1897 }
1898
1899 return qnum;
1900}
1901
1902int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1903{
1904 int qnum;
1905
1906 switch (queue) {
1907 case ATH9K_WME_AC_VO:
1908 qnum = 0;
1909 break;
1910 case ATH9K_WME_AC_VI:
1911 qnum = 1;
1912 break;
1913 case ATH9K_WME_AC_BE:
1914 qnum = 2;
1915 break;
1916 case ATH9K_WME_AC_BK:
1917 qnum = 3;
1918 break;
1919 default:
1920 qnum = -1;
1921 break;
1922 }
1923
1924 return qnum;
1925}
1926
5f8e077c
LR		 1927/* XXX: Remove me once we don't depend on ath9k_channel for all
1928 * this redundant data */
0e2dedf9
JM		 1929void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1930 struct ath9k_channel *ichan)
5f8e077c 1931{
5f8e077c
LR		 1932 struct ieee80211_channel *chan = hw->conf.channel;
1933 struct ieee80211_conf *conf = &hw->conf;
1934
1935 ichan->channel = chan->center_freq;
1936 ichan->chan = chan;
1937
1938 if (chan->band == IEEE80211_BAND_2GHZ) {
1939 ichan->chanmode = CHANNEL_G;
1940 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1941 } else {
1942 ichan->chanmode = CHANNEL_A;
1943 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1944 }
1945
1946 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1947
1948 if (conf_is_ht(conf)) {
1949 if (conf_is_ht40(conf))
1950 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1951
1952 ichan->chanmode = ath_get_extchanmode(sc, chan,
1953 conf->channel_type);
1954 }
1955}
1956
ff37e337
S		 1957/**********************/
1958/* mac80211 callbacks */
1959/**********************/
1960
8feceb67 1961static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1962{
bce048d7
JM		 1963 struct ath_wiphy *aphy = hw->priv;
1964 struct ath_softc *sc = aphy->sc;
8feceb67 1965 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1966 struct ath9k_channel *init_channel;
ae8d2858 1967 int r, pos;
f078f209 1968
04bd4638
S		 1969 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1970 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1971
141b38b6
S		 1972 mutex_lock(&sc->mutex);
1973
9580a222
JM		 1974 if (ath9k_wiphy_started(sc)) {
1975 if (sc->chan_idx == curchan->hw_value) {
1976 /*
1977 * Already on the operational channel, the new wiphy
1978 * can be marked active.
1979 */
1980 aphy->state = ATH_WIPHY_ACTIVE;
1981 ieee80211_wake_queues(hw);
1982 } else {
1983 /*
1984 * Another wiphy is on another channel, start the new
1985 * wiphy in paused state.
1986 */
1987 aphy->state = ATH_WIPHY_PAUSED;
1988 ieee80211_stop_queues(hw);
1989 }
1990 mutex_unlock(&sc->mutex);
1991 return 0;
1992 }
1993 aphy->state = ATH_WIPHY_ACTIVE;
1994
8feceb67 1995 /* setup initial channel */
f078f209 1996
5f8e077c 1997 pos = curchan->hw_value;
f078f209 1998
0e2dedf9 1999 sc->chan_idx = pos;
2660b81a 2000 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 2001 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 2002
2003 /* Reset SERDES registers */
2004 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2005
2006 /*
2007 * The basic interface to setting the hardware in a good
2008 * state is ``reset''. On return the hardware is known to
2009 * be powered up and with interrupts disabled. This must
2010 * be followed by initialization of the appropriate bits
2011 * and then setup of the interrupt mask.
2012 */
2013 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 2014 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2015 if (r) {
ff37e337 2016 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 2017 "Unable to reset hardware; reset status %u "
2018 "(freq %u MHz)\n", r,
2019 curchan->center_freq);
ff37e337 2020 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2021 goto mutex_unlock;
ff37e337
S		 2022 }
2023 spin_unlock_bh(&sc->sc_resetlock);
2024
2025 /*
2026 * This is needed only to setup initial state
2027 * but it's best done after a reset.
2028 */
2029 ath_update_txpow(sc);
8feceb67 2030
ff37e337
S		 2031 /*
2032 * Setup the hardware after reset:
2033 * The receive engine is set going.
2034 * Frame transmit is handled entirely
2035 * in the frame output path; there's nothing to do
2036 * here except setup the interrupt mask.
2037 */
2038 if (ath_startrecv(sc) != 0) {
1ffb0610 2039 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2040 r = -EIO;
2041 goto mutex_unlock;
f078f209 2042 }
8feceb67 2043
ff37e337 2044 /* Setup our intr mask. */
17d7904d 2045 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2046 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2047 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2048
2660b81a 2049 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2050 sc->imask |= ATH9K_INT_GTT;
ff37e337 2051
2660b81a 2052 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2053 sc->imask |= ATH9K_INT_CST;
ff37e337 2054
ce111bad 2055 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2056
2057 sc->sc_flags &= ~SC_OP_INVALID;
2058
2059 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2060 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2061 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2062
bce048d7 2063 ieee80211_wake_queues(hw);
ff37e337 2064
e97275cb 2065#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2066 r = ath_start_rfkill_poll(sc);
500c064d 2067#endif
141b38b6
S		 2068
2069mutex_unlock:
2070 mutex_unlock(&sc->mutex);
2071
ae8d2858 2072 return r;
f078f209
LR		 2073}
2074
8feceb67
VT		 2075static int ath9k_tx(struct ieee80211_hw *hw,
2076 struct sk_buff *skb)
f078f209 2077{
528f0c6b 2078 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2079 struct ath_wiphy *aphy = hw->priv;
2080 struct ath_softc *sc = aphy->sc;
528f0c6b 2081 struct ath_tx_control txctl;
8feceb67 2082 int hdrlen, padsize;
528f0c6b 2083
8089cc47 2084 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2085 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2086 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2087 goto exit;
2088 }
2089
528f0c6b 2090 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2091
8feceb67
VT		 2092 /*
2093 * As a temporary workaround, assign seq# here; this will likely need
2094 * to be cleaned up to work better with Beacon transmission and virtual
2095 * BSSes.
2096 */
2097 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2098 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2099 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2100 sc->tx.seq_no += 0x10;
8feceb67 2101 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2102 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2103 }
f078f209 2104
8feceb67
VT		 2105 /* Add the padding after the header if this is not already done */
2106 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2107 if (hdrlen & 3) {
2108 padsize = hdrlen % 4;
2109 if (skb_headroom(skb) < padsize)
2110 return -1;
2111 skb_push(skb, padsize);
2112 memmove(skb->data, skb->data + padsize, hdrlen);
2113 }
2114
528f0c6b
S		 2115 /* Check if a tx queue is available */
2116
2117 txctl.txq = ath_test_get_txq(sc, skb);
2118 if (!txctl.txq)
2119 goto exit;
2120
04bd4638 2121 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2122
c52f33d0 2123 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2124 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2125 goto exit;
8feceb67
VT		 2126 }
2127
528f0c6b
S		 2128 return 0;
2129exit:
2130 dev_kfree_skb_any(skb);
8feceb67 2131 return 0;
f078f209
LR		 2132}
2133
8feceb67 2134static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2135{
bce048d7
JM		 2136 struct ath_wiphy *aphy = hw->priv;
2137 struct ath_softc *sc = aphy->sc;
f078f209 2138
9580a222
JM		 2139 aphy->state = ATH_WIPHY_INACTIVE;
2140
9c84b797 2141 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2142 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2143 return;
2144 }
8feceb67 2145
141b38b6 2146 mutex_lock(&sc->mutex);
ff37e337 2147
bce048d7 2148 ieee80211_stop_queues(hw);
ff37e337 2149
9580a222
JM		 2150 if (ath9k_wiphy_started(sc)) {
2151 mutex_unlock(&sc->mutex);
2152 return; /* another wiphy still in use */
2153 }
2154
ff37e337
S		 2155 /* make sure h/w will not generate any interrupt
2156 * before setting the invalid flag. */
2157 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2158
2159 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2160 ath_drain_all_txq(sc, false);
ff37e337
S		 2161 ath_stoprecv(sc);
2162 ath9k_hw_phy_disable(sc->sc_ah);
2163 } else
b77f483f 2164 sc->rx.rxlink = NULL;
ff37e337
S		 2165
2166#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2167 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2168 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2169#endif
2170 /* disable HAL and put h/w to sleep */
2171 ath9k_hw_disable(sc->sc_ah);
2172 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2173
2174 sc->sc_flags |= SC_OP_INVALID;
500c064d 2175
141b38b6
S		 2176 mutex_unlock(&sc->mutex);
2177
04bd4638 2178 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2179}
2180
8feceb67
VT		 2181static int ath9k_add_interface(struct ieee80211_hw *hw,
2182 struct ieee80211_if_init_conf *conf)
f078f209 2183{
bce048d7
JM		 2184 struct ath_wiphy *aphy = hw->priv;
2185 struct ath_softc *sc = aphy->sc;
17d7904d 2186 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2187 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2188 int ret = 0;
8feceb67 2189
141b38b6
S		 2190 mutex_lock(&sc->mutex);
2191
8ca21f01
JM		 2192 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2193 sc->nvifs > 0) {
2194 ret = -ENOBUFS;
2195 goto out;
2196 }
2197
8feceb67 2198 switch (conf->type) {
05c914fe 2199 case NL80211_IFTYPE_STATION:
d97809db 2200 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2201 break;
05c914fe 2202 case NL80211_IFTYPE_ADHOC:
05c914fe 2203 case NL80211_IFTYPE_AP:
9cb5412b 2204 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2205 if (sc->nbcnvifs >= ATH_BCBUF) {
2206 ret = -ENOBUFS;
2207 goto out;
2208 }
9cb5412b 2209 ic_opmode = conf->type;
f078f209
LR		 2210 break;
2211 default:
2212 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2213 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2214 ret = -EOPNOTSUPP;
2215 goto out;
f078f209
LR		 2216 }
2217
17d7904d 2218 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2219
17d7904d 2220 /* Set the VIF opmode */
5640b08e
S		 2221 avp->av_opmode = ic_opmode;
2222 avp->av_bslot = -1;
2223
2c3db3d5 2224 sc->nvifs++;
8ca21f01
JM		 2225
2226 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2227 ath9k_set_bssid_mask(hw);
2228
2c3db3d5
JM		 2229 if (sc->nvifs > 1)
2230 goto out; /* skip global settings for secondary vif */
2231
b238e90e 2232 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2233 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2234 sc->sc_flags |= SC_OP_TSF_RESET;
2235 }
5640b08e 2236
5640b08e 2237 /* Set the device opmode */
2660b81a 2238 sc->sc_ah->opmode = ic_opmode;
5640b08e 2239
4e30ffa2
VN		 2240 /*
2241 * Enable MIB interrupts when there are hardware phy counters.
2242 * Note we only do this (at the moment) for station mode.
2243 */
4af9cf4f 2244 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2245 (conf->type == NL80211_IFTYPE_ADHOC) ||
2246 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2247 if (ath9k_hw_phycounters(sc->sc_ah))
2248 sc->imask |= ATH9K_INT_MIB;
2249 sc->imask |= ATH9K_INT_TSFOOR;
2250 }
2251
17d7904d 2252 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2253
6f255425
LR		 2254 if (conf->type == NL80211_IFTYPE_AP) {
2255 /* TODO: is this a suitable place to start ANI for AP mode? */
2256 /* Start ANI */
17d7904d 2257 mod_timer(&sc->ani.timer,
6f255425
LR		 2258 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2259 }
2260
2c3db3d5 2261out:
141b38b6 2262 mutex_unlock(&sc->mutex);
2c3db3d5 2263 return ret;
f078f209
LR		 2264}
2265
8feceb67
VT		 2266static void ath9k_remove_interface(struct ieee80211_hw *hw,
2267 struct ieee80211_if_init_conf *conf)
f078f209 2268{
bce048d7
JM		 2269 struct ath_wiphy *aphy = hw->priv;
2270 struct ath_softc *sc = aphy->sc;
17d7904d 2271 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2272 int i;
f078f209 2273
04bd4638 2274 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2275
141b38b6
S		 2276 mutex_lock(&sc->mutex);
2277
6f255425 2278 /* Stop ANI */
17d7904d 2279 del_timer_sync(&sc->ani.timer);
580f0b8a 2280
8feceb67 2281 /* Reclaim beacon resources */
9cb5412b
PE		 2282 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2283 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2284 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2285 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2286 ath_beacon_return(sc, avp);
580f0b8a 2287 }
f078f209 2288
8feceb67 2289 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2290
2c3db3d5
JM		 2291 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2292 if (sc->beacon.bslot[i] == conf->vif) {
2293 printk(KERN_DEBUG "%s: vif had allocated beacon "
2294 "slot\n", __func__);
2295 sc->beacon.bslot[i] = NULL;
c52f33d0 2296 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2297 }
2298 }
2299
17d7904d 2300 sc->nvifs--;
141b38b6
S		 2301
2302 mutex_unlock(&sc->mutex);
f078f209
LR		 2303}
2304
e8975581 2305static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2306{
bce048d7
JM		 2307 struct ath_wiphy *aphy = hw->priv;
2308 struct ath_softc *sc = aphy->sc;
e8975581 2309 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2310 struct ath_hw *ah = sc->sc_ah;
f078f209 2311
aa33de09 2312 mutex_lock(&sc->mutex);
141b38b6 2313
3cbb5dd7
VN		 2314 if (changed & IEEE80211_CONF_CHANGE_PS) {
2315 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2316 if (!(ah->caps.hw_caps &
2317 ATH9K_HW_CAP_AUTOSLEEP)) {
2318 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2319 sc->imask |= ATH9K_INT_TIM_TIMER;
2320 ath9k_hw_set_interrupts(sc->sc_ah,
2321 sc->imask);
2322 }
2323 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2324 }
3cbb5dd7
VN		 2325 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2326 } else {
2327 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2328 if (!(ah->caps.hw_caps &
2329 ATH9K_HW_CAP_AUTOSLEEP)) {
2330 ath9k_hw_setrxabort(sc->sc_ah, 0);
2331 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2332 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2333 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2334 ath9k_hw_set_interrupts(sc->sc_ah,
2335 sc->imask);
2336 }
3cbb5dd7
VN		 2337 }
2338 }
2339 }
2340
4797938c 2341 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2342 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2343 int pos = curchan->hw_value;
ae5eb026 2344
0e2dedf9
JM		 2345 aphy->chan_idx = pos;
2346 aphy->chan_is_ht = conf_is_ht(conf);
2347
8089cc47
JM		 2348 if (aphy->state == ATH_WIPHY_SCAN ||
2349 aphy->state == ATH_WIPHY_ACTIVE)
2350 ath9k_wiphy_pause_all_forced(sc, aphy);
2351 else {
2352 /*
2353 * Do not change operational channel based on a paused
2354 * wiphy changes.
2355 */
2356 goto skip_chan_change;
2357 }
0e2dedf9 2358
04bd4638
S		 2359 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2360 curchan->center_freq);
f078f209 2361
5f8e077c 2362 /* XXX: remove me eventualy */
0e2dedf9 2363 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2364
ecf70441 2365 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2366
0e2dedf9 2367 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2368 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2369 mutex_unlock(&sc->mutex);
e11602b7
S		 2370 return -EINVAL;
2371 }
094d05dc 2372 }
f078f209 2373
8089cc47 2374skip_chan_change:
5c020dc6 2375 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2376 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2377
b238e90e
S		 2378 /*
2379 * The HW TSF has to be reset when the beacon interval changes.
2380 * We set the flag here, and ath_beacon_config_ap() would take this
2381 * into account when it gets called through the subsequent
2382 * config_interface() call - with IFCC_BEACON in the changed field.
2383 */
2384
2385 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2386 sc->sc_flags |= SC_OP_TSF_RESET;
2387
aa33de09 2388 mutex_unlock(&sc->mutex);
141b38b6 2389
f078f209
LR		 2390 return 0;
2391}
2392
8feceb67
VT		 2393static int ath9k_config_interface(struct ieee80211_hw *hw,
2394 struct ieee80211_vif *vif,
2395 struct ieee80211_if_conf *conf)
c83be688 2396{
bce048d7
JM		 2397 struct ath_wiphy *aphy = hw->priv;
2398 struct ath_softc *sc = aphy->sc;
cbe61d8a 2399 struct ath_hw *ah = sc->sc_ah;
17d7904d 2400 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2401 u32 rfilt = 0;
2402 int error, i;
c83be688 2403
2554935b
S		 2404 mutex_lock(&sc->mutex);
2405
8feceb67
VT		 2406 /* TODO: Need to decide which hw opmode to use for multi-interface
2407 * cases */
05c914fe 2408 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2409 ah->opmode != NL80211_IFTYPE_AP) {
2410 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2411 ath9k_hw_setopmode(ah);
ba52da58
S		 2412 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2413 sc->curaid = 0;
2414 ath9k_hw_write_associd(sc);
8feceb67
VT		 2415 /* Request full reset to get hw opmode changed properly */
2416 sc->sc_flags |= SC_OP_FULL_RESET;
2417 }
c83be688 2418
8feceb67
VT		 2419 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2420 !is_zero_ether_addr(conf->bssid)) {
2421 switch (vif->type) {
05c914fe
JB		 2422 case NL80211_IFTYPE_STATION:
2423 case NL80211_IFTYPE_ADHOC:
9cb5412b 2424 case NL80211_IFTYPE_MESH_POINT:
8feceb67 2425 /* Set BSSID */
17d7904d 2426 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
f0ed85c6 2427 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
17d7904d 2428 sc->curaid = 0;
ba52da58 2429 ath9k_hw_write_associd(sc);
c83be688 2430
8feceb67 2431 /* Set aggregation protection mode parameters */
17d7904d 2432 sc->config.ath_aggr_prot = 0;
c83be688 2433
8feceb67 2434 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2435 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2436 rfilt, sc->curbssid, sc->curaid);
c83be688 2437
8feceb67
VT		 2438 /* need to reconfigure the beacon */
2439 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2440
8feceb67
VT		 2441 break;
2442 default:
2443 break;
2444 }
2445 }
c83be688 2446
1f7d6cbf 2447 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
9cb5412b
PE		 2448 (vif->type == NL80211_IFTYPE_AP) ||
2449 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1f7d6cbf
S		 2450 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2451 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2452 conf->enable_beacon)) {
2453 /*
2454 * Allocate and setup the beacon frame.
2455 *
2456 * Stop any previous beacon DMA. This may be
2457 * necessary, for example, when an ibss merge
2458 * causes reconfiguration; we may be called
2459 * with beacon transmission active.
2460 */
2461 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2462
c52f33d0 2463 error = ath_beacon_alloc(aphy, vif);
2554935b
S		 2464 if (error != 0) {
2465 mutex_unlock(&sc->mutex);
1f7d6cbf 2466 return error;
2554935b 2467 }
c83be688 2468
2c3db3d5 2469 ath_beacon_config(sc, vif);
1f7d6cbf 2470 }
8feceb67 2471 }
c83be688 2472
8feceb67 2473 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2474 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2475 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2476 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2477 ath9k_hw_keysetmac(sc->sc_ah,
2478 (u16)i,
17d7904d 2479 sc->curbssid);
8feceb67 2480 }
c83be688 2481
8feceb67 2482 /* Only legacy IBSS for now */
05c914fe 2483 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2484 ath_update_chainmask(sc, 0);
f078f209 2485
2554935b
S		 2486 mutex_unlock(&sc->mutex);
2487
8feceb67
VT		 2488 return 0;
2489}
f078f209 2490
8feceb67
VT		 2491#define SUPPORTED_FILTERS \
2492 (FIF_PROMISC_IN_BSS | \
2493 FIF_ALLMULTI | \
2494 FIF_CONTROL | \
2495 FIF_OTHER_BSS | \
2496 FIF_BCN_PRBRESP_PROMISC | \
2497 FIF_FCSFAIL)
c83be688 2498
8feceb67
VT		 2499/* FIXME: sc->sc_full_reset ? */
2500static void ath9k_configure_filter(struct ieee80211_hw *hw,
2501 unsigned int changed_flags,
2502 unsigned int *total_flags,
2503 int mc_count,
2504 struct dev_mc_list *mclist)
2505{
bce048d7
JM		 2506 struct ath_wiphy *aphy = hw->priv;
2507 struct ath_softc *sc = aphy->sc;
8feceb67 2508 u32 rfilt;
f078f209 2509
8feceb67
VT		 2510 changed_flags &= SUPPORTED_FILTERS;
2511 *total_flags &= SUPPORTED_FILTERS;
f078f209 2512
b77f483f 2513 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2514 rfilt = ath_calcrxfilter(sc);
2515 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2516
b77f483f 2517 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2518}
f078f209 2519
8feceb67
VT		 2520static void ath9k_sta_notify(struct ieee80211_hw *hw,
2521 struct ieee80211_vif *vif,
2522 enum sta_notify_cmd cmd,
17741cdc 2523 struct ieee80211_sta *sta)
8feceb67 2524{
bce048d7
JM		 2525 struct ath_wiphy *aphy = hw->priv;
2526 struct ath_softc *sc = aphy->sc;
f078f209 2527
8feceb67
VT		 2528 switch (cmd) {
2529 case STA_NOTIFY_ADD:
5640b08e 2530 ath_node_attach(sc, sta);
8feceb67
VT		 2531 break;
2532 case STA_NOTIFY_REMOVE:
b5aa9bf9 2533 ath_node_detach(sc, sta);
8feceb67
VT		 2534 break;
2535 default:
2536 break;
2537 }
f078f209
LR		 2538}
2539
141b38b6 2540static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2541 const struct ieee80211_tx_queue_params *params)
f078f209 2542{
bce048d7
JM		 2543 struct ath_wiphy *aphy = hw->priv;
2544 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2545 struct ath9k_tx_queue_info qi;
2546 int ret = 0, qnum;
f078f209 2547
8feceb67
VT		 2548 if (queue >= WME_NUM_AC)
2549 return 0;
f078f209 2550
141b38b6
S		 2551 mutex_lock(&sc->mutex);
2552
1ffb0610
S		 2553 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2554
8feceb67
VT		 2555 qi.tqi_aifs = params->aifs;
2556 qi.tqi_cwmin = params->cw_min;
2557 qi.tqi_cwmax = params->cw_max;
2558 qi.tqi_burstTime = params->txop;
2559 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2560
8feceb67 2561 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2562 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2563 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2564 queue, qnum, params->aifs, params->cw_min,
2565 params->cw_max, params->txop);
f078f209 2566
8feceb67
VT		 2567 ret = ath_txq_update(sc, qnum, &qi);
2568 if (ret)
04bd4638 2569 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2570
141b38b6
S		 2571 mutex_unlock(&sc->mutex);
2572
8feceb67
VT		 2573 return ret;
2574}
f078f209 2575
8feceb67
VT		 2576static int ath9k_set_key(struct ieee80211_hw *hw,
2577 enum set_key_cmd cmd,
dc822b5d
JB		 2578 struct ieee80211_vif *vif,
2579 struct ieee80211_sta *sta,
8feceb67
VT		 2580 struct ieee80211_key_conf *key)
2581{
bce048d7
JM		 2582 struct ath_wiphy *aphy = hw->priv;
2583 struct ath_softc *sc = aphy->sc;
8feceb67 2584 int ret = 0;
f078f209 2585
b3bd89ce
JM		 2586 if (modparam_nohwcrypt)
2587 return -ENOSPC;
2588
141b38b6 2589 mutex_lock(&sc->mutex);
3cbb5dd7 2590 ath9k_ps_wakeup(sc);
d8baa939 2591 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2592
8feceb67
VT		 2593 switch (cmd) {
2594 case SET_KEY:
3f53dd64 2595 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2596 if (ret >= 0) {
2597 key->hw_key_idx = ret;
8feceb67
VT		 2598 /* push IV and Michael MIC generation to stack */
2599 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2600 if (key->alg == ALG_TKIP)
2601 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2602 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2603 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2604 ret = 0;
8feceb67
VT		 2605 }
2606 break;
2607 case DISABLE_KEY:
2608 ath_key_delete(sc, key);
8feceb67
VT		 2609 break;
2610 default:
2611 ret = -EINVAL;
2612 }
f078f209 2613
3cbb5dd7 2614 ath9k_ps_restore(sc);
141b38b6
S		 2615 mutex_unlock(&sc->mutex);
2616
8feceb67
VT		 2617 return ret;
2618}
f078f209 2619
8feceb67
VT		 2620static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2621 struct ieee80211_vif *vif,
2622 struct ieee80211_bss_conf *bss_conf,
2623 u32 changed)
2624{
bce048d7
JM		 2625 struct ath_wiphy *aphy = hw->priv;
2626 struct ath_softc *sc = aphy->sc;
f078f209 2627
141b38b6
S		 2628 mutex_lock(&sc->mutex);
2629
8feceb67 2630 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2631 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2632 bss_conf->use_short_preamble);
2633 if (bss_conf->use_short_preamble)
2634 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2635 else
2636 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2637 }
f078f209 2638
8feceb67 2639 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2640 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2641 bss_conf->use_cts_prot);
2642 if (bss_conf->use_cts_prot &&
2643 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2644 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2645 else
2646 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2647 }
f078f209 2648
8feceb67 2649 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2650 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2651 bss_conf->assoc);
5640b08e 2652 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2653 }
141b38b6
S		 2654
2655 mutex_unlock(&sc->mutex);
8feceb67 2656}
f078f209 2657
8feceb67
VT		 2658static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2659{
2660 u64 tsf;
bce048d7
JM		 2661 struct ath_wiphy *aphy = hw->priv;
2662 struct ath_softc *sc = aphy->sc;
f078f209 2663
141b38b6
S		 2664 mutex_lock(&sc->mutex);
2665 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2666 mutex_unlock(&sc->mutex);
f078f209 2667
8feceb67
VT		 2668 return tsf;
2669}
f078f209 2670
3b5d665b
AF		 2671static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2672{
bce048d7
JM		 2673 struct ath_wiphy *aphy = hw->priv;
2674 struct ath_softc *sc = aphy->sc;
3b5d665b 2675
141b38b6
S		 2676 mutex_lock(&sc->mutex);
2677 ath9k_hw_settsf64(sc->sc_ah, tsf);
2678 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2679}
2680
8feceb67
VT		 2681static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2682{
bce048d7
JM		 2683 struct ath_wiphy *aphy = hw->priv;
2684 struct ath_softc *sc = aphy->sc;
c83be688 2685
141b38b6
S		 2686 mutex_lock(&sc->mutex);
2687 ath9k_hw_reset_tsf(sc->sc_ah);
2688 mutex_unlock(&sc->mutex);
8feceb67 2689}
f078f209 2690
8feceb67 2691static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2692 enum ieee80211_ampdu_mlme_action action,
2693 struct ieee80211_sta *sta,
2694 u16 tid, u16 *ssn)
8feceb67 2695{
bce048d7
JM		 2696 struct ath_wiphy *aphy = hw->priv;
2697 struct ath_softc *sc = aphy->sc;
8feceb67 2698 int ret = 0;
f078f209 2699
8feceb67
VT		 2700 switch (action) {
2701 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2702 if (!(sc->sc_flags & SC_OP_RXAGGR))
2703 ret = -ENOTSUPP;
8feceb67
VT		 2704 break;
2705 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2706 break;
2707 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2708 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2709 if (ret < 0)
2710 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2711 "Unable to start TX aggregation\n");
8feceb67 2712 else
17741cdc 2713 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2714 break;
2715 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2716 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2717 if (ret < 0)
2718 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2719 "Unable to stop TX aggregation\n");
f078f209 2720
17741cdc 2721 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2722 break;
b1720231 2723 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2724 ath_tx_aggr_resume(sc, sta, tid);
2725 break;
8feceb67 2726 default:
04bd4638 2727 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2728 }
2729
2730 return ret;
f078f209
LR		 2731}
2732
0c98de65
S		 2733static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2734{
bce048d7
JM		 2735 struct ath_wiphy *aphy = hw->priv;
2736 struct ath_softc *sc = aphy->sc;
0c98de65 2737
8089cc47
JM		 2738 if (ath9k_wiphy_scanning(sc)) {
2739 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2740 "same time\n");
2741 /*
2742 * Do not allow the concurrent scanning state for now. This
2743 * could be improved with scanning control moved into ath9k.
2744 */
2745 return;
2746 }
2747
2748 aphy->state = ATH_WIPHY_SCAN;
2749 ath9k_wiphy_pause_all_forced(sc, aphy);
2750
0c98de65
S		 2751 mutex_lock(&sc->mutex);
2752 sc->sc_flags |= SC_OP_SCANNING;
2753 mutex_unlock(&sc->mutex);
2754}
2755
2756static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2757{
bce048d7
JM		 2758 struct ath_wiphy *aphy = hw->priv;
2759 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2760
2761 mutex_lock(&sc->mutex);
8089cc47 2762 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65
S		 2763 sc->sc_flags &= ~SC_OP_SCANNING;
2764 mutex_unlock(&sc->mutex);
2765}
2766
6baff7f9 2767struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2768 .tx = ath9k_tx,
2769 .start = ath9k_start,
2770 .stop = ath9k_stop,
2771 .add_interface = ath9k_add_interface,
2772 .remove_interface = ath9k_remove_interface,
2773 .config = ath9k_config,
2774 .config_interface = ath9k_config_interface,
2775 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2776 .sta_notify = ath9k_sta_notify,
2777 .conf_tx = ath9k_conf_tx,
8feceb67 2778 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2779 .set_key = ath9k_set_key,
8feceb67 2780 .get_tsf = ath9k_get_tsf,
3b5d665b 2781 .set_tsf = ath9k_set_tsf,
8feceb67 2782 .reset_tsf = ath9k_reset_tsf,
4233df6b 2783 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2784 .sw_scan_start = ath9k_sw_scan_start,
2785 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2786};
2787
392dff83
BP		 2788static struct {
2789 u32 version;
2790 const char * name;
2791} ath_mac_bb_names[] = {
2792 { AR_SREV_VERSION_5416_PCI, "5416" },
2793 { AR_SREV_VERSION_5416_PCIE, "5418" },
2794 { AR_SREV_VERSION_9100, "9100" },
2795 { AR_SREV_VERSION_9160, "9160" },
2796 { AR_SREV_VERSION_9280, "9280" },
2797 { AR_SREV_VERSION_9285, "9285" }
2798};
2799
2800static struct {
2801 u16 version;
2802 const char * name;
2803} ath_rf_names[] = {
2804 { 0, "5133" },
2805 { AR_RAD5133_SREV_MAJOR, "5133" },
2806 { AR_RAD5122_SREV_MAJOR, "5122" },
2807 { AR_RAD2133_SREV_MAJOR, "2133" },
2808 { AR_RAD2122_SREV_MAJOR, "2122" }
2809};
2810
2811/*
2812 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2813 */
6baff7f9 2814const char *
392dff83
BP		 2815ath_mac_bb_name(u32 mac_bb_version)
2816{
2817 int i;
2818
2819 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2820 if (ath_mac_bb_names[i].version == mac_bb_version) {
2821 return ath_mac_bb_names[i].name;
2822 }
2823 }
2824
2825 return "????";
2826}
2827
2828/*
2829 * Return the RF name. "????" is returned if the RF is unknown.
2830 */
6baff7f9 2831const char *
392dff83
BP		 2832ath_rf_name(u16 rf_version)
2833{
2834 int i;
2835
2836 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2837 if (ath_rf_names[i].version == rf_version) {
2838 return ath_rf_names[i].name;
2839 }
2840 }
2841
2842 return "????";
2843}
2844
6baff7f9 2845static int __init ath9k_init(void)
f078f209 2846{
ca8a8560
VT		 2847 int error;
2848
ca8a8560
VT		 2849 /* Register rate control algorithm */
2850 error = ath_rate_control_register();
2851 if (error != 0) {
2852 printk(KERN_ERR
b51bb3cd
LR		 2853 "ath9k: Unable to register rate control "
2854 "algorithm: %d\n",
ca8a8560 2855 error);
6baff7f9 2856 goto err_out;
ca8a8560
VT		 2857 }
2858
19d8bc22
GJ		 2859 error = ath9k_debug_create_root();
2860 if (error) {
2861 printk(KERN_ERR
2862 "ath9k: Unable to create debugfs root: %d\n",
2863 error);
2864 goto err_rate_unregister;
2865 }
2866
6baff7f9
GJ		 2867 error = ath_pci_init();
2868 if (error < 0) {
f078f209 2869 printk(KERN_ERR
b51bb3cd 2870 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2871 error = -ENODEV;
19d8bc22 2872 goto err_remove_root;
f078f209
LR		 2873 }
2874
09329d37
GJ		 2875 error = ath_ahb_init();
2876 if (error < 0) {
2877 error = -ENODEV;
2878 goto err_pci_exit;
2879 }
2880
f078f209 2881 return 0;
6baff7f9 2882
09329d37
GJ		 2883 err_pci_exit:
2884 ath_pci_exit();
2885
19d8bc22
GJ		 2886 err_remove_root:
2887 ath9k_debug_remove_root();
6baff7f9
GJ		 2888 err_rate_unregister:
2889 ath_rate_control_unregister();
2890 err_out:
2891 return error;
f078f209 2892}
6baff7f9 2893module_init(ath9k_init);
f078f209 2894
6baff7f9 2895static void __exit ath9k_exit(void)
f078f209 2896{
09329d37 2897 ath_ahb_exit();
6baff7f9 2898 ath_pci_exit();
19d8bc22 2899 ath9k_debug_remove_root();
ca8a8560 2900 ath_rate_control_unregister();
04bd4638 2901 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2902}
6baff7f9 2903module_exit(ath9k_exit);
Linux kernel - Deliverables
This page took 0.352497 seconds and 5 git commands to generate.