ath9k: Handle chainmask for A9280
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR
17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR
21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR
24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
5f8e077c
LR
31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 30, \
37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 30, \
44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR
102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR
105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR
117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR
119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR
131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR
133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR
136 break;
137 }
ff37e337
S
138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
142 struct ath_hal *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->sc_curtxpow = txpow;
150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
190 struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
220 sband->n_bitrates++;
04bd4638
S
221 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
222 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S
223 }
224}
225
ff37e337
S
226/*
227 * Set/change channels. If the channel is really being changed, it's done
228 * by reseting the chip. To accomplish this we must first cleanup any pending
229 * DMA, then restart stuff.
230*/
231static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
232{
233 struct ath_hal *ah = sc->sc_ah;
234 bool fastcc = true, stopped;
030bb495 235 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR
236 struct ieee80211_channel *channel = hw->conf.channel;
237 int r;
ff37e337
S
238
239 if (sc->sc_flags & SC_OP_INVALID)
240 return -EIO;
241
3cbb5dd7
VN
242 ath9k_ps_wakeup(sc);
243
c0d7c7af
LR
244 /*
245 * This is only performed if the channel settings have
246 * actually changed.
247 *
248 * To switch channels clear any pending DMA operations;
249 * wait long enough for the RX fifo to drain, reset the
250 * hardware at the new frequency, and then re-enable
251 * the relevant bits of the h/w.
252 */
253 ath9k_hw_set_interrupts(ah, 0);
043a0405 254 ath_drain_all_txq(sc, false);
c0d7c7af 255 stopped = ath_stoprecv(sc);
ff37e337 256
c0d7c7af
LR
257 /* XXX: do not flush receive queue here. We don't want
258 * to flush data frames already in queue because of
259 * changing channel. */
ff37e337 260
c0d7c7af
LR
261 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
262 fastcc = false;
263
264 DPRINTF(sc, ATH_DBG_CONFIG,
265 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
266 sc->sc_ah->ah_curchan->channel,
267 channel->center_freq, sc->tx_chan_width);
ff37e337 268
c0d7c7af
LR
269 spin_lock_bh(&sc->sc_resetlock);
270
271 r = ath9k_hw_reset(ah, hchan, fastcc);
272 if (r) {
273 DPRINTF(sc, ATH_DBG_FATAL,
274 "Unable to reset channel (%u Mhz) "
275 "reset status %u\n",
276 channel->center_freq, r);
277 spin_unlock_bh(&sc->sc_resetlock);
278 return r;
ff37e337 279 }
c0d7c7af
LR
280 spin_unlock_bh(&sc->sc_resetlock);
281
282 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
283 sc->sc_flags &= ~SC_OP_FULL_RESET;
284
285 if (ath_startrecv(sc) != 0) {
286 DPRINTF(sc, ATH_DBG_FATAL,
287 "Unable to restart recv logic\n");
288 return -EIO;
289 }
290
291 ath_cache_conf_rate(sc, &hw->conf);
292 ath_update_txpow(sc);
293 ath9k_hw_set_interrupts(ah, sc->sc_imask);
3cbb5dd7 294 ath9k_ps_restore(sc);
ff37e337
S
295 return 0;
296}
297
298/*
299 * This routine performs the periodic noise floor calibration function
300 * that is used to adjust and optimize the chip performance. This
301 * takes environmental changes (location, temperature) into account.
302 * When the task is complete, it reschedules itself depending on the
303 * appropriate interval that was calculated.
304 */
305static void ath_ani_calibrate(unsigned long data)
306{
307 struct ath_softc *sc;
308 struct ath_hal *ah;
309 bool longcal = false;
310 bool shortcal = false;
311 bool aniflag = false;
312 unsigned int timestamp = jiffies_to_msecs(jiffies);
313 u32 cal_interval;
314
315 sc = (struct ath_softc *)data;
316 ah = sc->sc_ah;
317
318 /*
319 * don't calibrate when we're scanning.
320 * we are most likely not on our home channel.
321 */
b77f483f 322 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S
323 return;
324
325 /* Long calibration runs independently of short calibration. */
326 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
327 longcal = true;
04bd4638 328 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S
329 sc->sc_ani.sc_longcal_timer = timestamp;
330 }
331
332 /* Short calibration applies only while sc_caldone is false */
333 if (!sc->sc_ani.sc_caldone) {
334 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
335 ATH_SHORT_CALINTERVAL) {
336 shortcal = true;
04bd4638 337 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S
338 sc->sc_ani.sc_shortcal_timer = timestamp;
339 sc->sc_ani.sc_resetcal_timer = timestamp;
340 }
341 } else {
342 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
343 ATH_RESTART_CALINTERVAL) {
c9e27d94 344 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S
345 if (sc->sc_ani.sc_caldone)
346 sc->sc_ani.sc_resetcal_timer = timestamp;
347 }
348 }
349
350 /* Verify whether we must check ANI */
351 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
352 ATH_ANI_POLLINTERVAL) {
353 aniflag = true;
354 sc->sc_ani.sc_checkani_timer = timestamp;
355 }
356
357 /* Skip all processing if there's nothing to do. */
358 if (longcal || shortcal || aniflag) {
359 /* Call ANI routine if necessary */
360 if (aniflag)
361 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
362 ah->ah_curchan);
363
364 /* Perform calibration if necessary */
365 if (longcal || shortcal) {
366 bool iscaldone = false;
367
368 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
369 sc->sc_rx_chainmask, longcal,
370 &iscaldone)) {
371 if (longcal)
372 sc->sc_ani.sc_noise_floor =
373 ath9k_hw_getchan_noise(ah,
374 ah->ah_curchan);
375
376 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 377 "calibrate chan %u/%x nf: %d\n",
ff37e337
S
378 ah->ah_curchan->channel,
379 ah->ah_curchan->channelFlags,
380 sc->sc_ani.sc_noise_floor);
381 } else {
382 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 383 "calibrate chan %u/%x failed\n",
ff37e337
S
384 ah->ah_curchan->channel,
385 ah->ah_curchan->channelFlags);
386 }
387 sc->sc_ani.sc_caldone = iscaldone;
388 }
389 }
390
391 /*
392 * Set timer interval based on previous results.
393 * The interval must be the shortest necessary to satisfy ANI,
394 * short calibration and long calibration.
395 */
aac9207e
S
396 cal_interval = ATH_LONG_CALINTERVAL;
397 if (sc->sc_ah->ah_config.enable_ani)
398 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S
399 if (!sc->sc_ani.sc_caldone)
400 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
401
402 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
403}
404
405/*
406 * Update tx/rx chainmask. For legacy association,
407 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
408 * the chainmask configuration, for bt coexistence, use
409 * the chainmask configuration even in legacy mode.
ff37e337
S
410 */
411static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
412{
413 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT
414 if (is_ht ||
415 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S
416 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
417 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
418 } else {
419 sc->sc_tx_chainmask = 1;
420 sc->sc_rx_chainmask = 1;
421 }
422
04bd4638
S
423 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
424 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S
425}
426
427static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
428{
429 struct ath_node *an;
430
431 an = (struct ath_node *)sta->drv_priv;
432
433 if (sc->sc_flags & SC_OP_TXAGGR)
434 ath_tx_node_init(sc, an);
435
436 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
437 sta->ht_cap.ampdu_factor);
438 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
439}
440
441static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
442{
443 struct ath_node *an = (struct ath_node *)sta->drv_priv;
444
445 if (sc->sc_flags & SC_OP_TXAGGR)
446 ath_tx_node_cleanup(sc, an);
447}
448
449static void ath9k_tasklet(unsigned long data)
450{
451 struct ath_softc *sc = (struct ath_softc *)data;
452 u32 status = sc->sc_intrstatus;
453
454 if (status & ATH9K_INT_FATAL) {
455 /* need a chip reset */
456 ath_reset(sc, false);
457 return;
458 } else {
459
460 if (status &
461 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 462 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 463 ath_rx_tasklet(sc, 0);
b77f483f 464 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
465 }
466 /* XXX: optimize this */
467 if (status & ATH9K_INT_TX)
468 ath_tx_tasklet(sc);
469 }
470
471 /* re-enable hardware interrupt */
472 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
473}
474
6baff7f9 475irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S
476{
477 struct ath_softc *sc = dev;
478 struct ath_hal *ah = sc->sc_ah;
479 enum ath9k_int status;
480 bool sched = false;
481
482 do {
483 if (sc->sc_flags & SC_OP_INVALID) {
484 /*
485 * The hardware is not ready/present, don't
486 * touch anything. Note this can happen early
487 * on if the IRQ is shared.
488 */
489 return IRQ_NONE;
490 }
491 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
492 return IRQ_NONE;
493 }
494
495 /*
496 * Figure out the reason(s) for the interrupt. Note
497 * that the hal returns a pseudo-ISR that may include
498 * bits we haven't explicitly enabled so we mask the
499 * value to insure we only process bits we requested.
500 */
501 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
502
503 status &= sc->sc_imask; /* discard unasked-for bits */
504
505 /*
506 * If there are no status bits set, then this interrupt was not
507 * for me (should have been caught above).
508 */
509 if (!status)
510 return IRQ_NONE;
511
512 sc->sc_intrstatus = status;
513
514 if (status & ATH9K_INT_FATAL) {
515 /* need a chip reset */
516 sched = true;
517 } else if (status & ATH9K_INT_RXORN) {
518 /* need a chip reset */
519 sched = true;
520 } else {
521 if (status & ATH9K_INT_SWBA) {
522 /* schedule a tasklet for beacon handling */
523 tasklet_schedule(&sc->bcon_tasklet);
524 }
525 if (status & ATH9K_INT_RXEOL) {
526 /*
527 * NB: the hardware should re-read the link when
528 * RXE bit is written, but it doesn't work
529 * at least on older hardware revs.
530 */
531 sched = true;
532 }
533
534 if (status & ATH9K_INT_TXURN)
535 /* bump tx trigger level */
536 ath9k_hw_updatetxtriglevel(ah, true);
537 /* XXX: optimize this */
538 if (status & ATH9K_INT_RX)
539 sched = true;
540 if (status & ATH9K_INT_TX)
541 sched = true;
542 if (status & ATH9K_INT_BMISS)
543 sched = true;
544 /* carrier sense timeout */
545 if (status & ATH9K_INT_CST)
546 sched = true;
547 if (status & ATH9K_INT_MIB) {
548 /*
549 * Disable interrupts until we service the MIB
550 * interrupt; otherwise it will continue to
551 * fire.
552 */
553 ath9k_hw_set_interrupts(ah, 0);
554 /*
555 * Let the hal handle the event. We assume
556 * it will clear whatever condition caused
557 * the interrupt.
558 */
559 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
560 ath9k_hw_set_interrupts(ah, sc->sc_imask);
561 }
562 if (status & ATH9K_INT_TIM_TIMER) {
563 if (!(ah->ah_caps.hw_caps &
564 ATH9K_HW_CAP_AUTOSLEEP)) {
565 /* Clear RxAbort bit so that we can
566 * receive frames */
3cbb5dd7 567 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S
568 ath9k_hw_setrxabort(ah, 0);
569 sched = true;
3cbb5dd7 570 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S
571 }
572 }
573 }
574 } while (0);
575
817e11de
S
576 ath_debug_stat_interrupt(sc, status);
577
ff37e337
S
578 if (sched) {
579 /* turn off every interrupt except SWBA */
580 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
581 tasklet_schedule(&sc->intr_tq);
582 }
583
584 return IRQ_HANDLED;
585}
586
f078f209 587static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 588 struct ieee80211_channel *chan,
094d05dc 589 enum nl80211_channel_type channel_type)
f078f209
LR
590{
591 u32 chanmode = 0;
f078f209
LR
592
593 switch (chan->band) {
594 case IEEE80211_BAND_2GHZ:
094d05dc
S
595 switch(channel_type) {
596 case NL80211_CHAN_NO_HT:
597 case NL80211_CHAN_HT20:
f078f209 598 chanmode = CHANNEL_G_HT20;
094d05dc
S
599 break;
600 case NL80211_CHAN_HT40PLUS:
f078f209 601 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
602 break;
603 case NL80211_CHAN_HT40MINUS:
f078f209 604 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
605 break;
606 }
f078f209
LR
607 break;
608 case IEEE80211_BAND_5GHZ:
094d05dc
S
609 switch(channel_type) {
610 case NL80211_CHAN_NO_HT:
611 case NL80211_CHAN_HT20:
f078f209 612 chanmode = CHANNEL_A_HT20;
094d05dc
S
613 break;
614 case NL80211_CHAN_HT40PLUS:
f078f209 615 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
616 break;
617 case NL80211_CHAN_HT40MINUS:
f078f209 618 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
619 break;
620 }
f078f209
LR
621 break;
622 default:
623 break;
624 }
625
626 return chanmode;
627}
628
ff37e337
S
629static int ath_keyset(struct ath_softc *sc, u16 keyix,
630 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
631{
632 bool status;
633
634 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
635 keyix, hk, mac, false);
636
637 return status != false;
638}
f078f209 639
6ace2891 640static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR
641 struct ath9k_keyval *hk,
642 const u8 *addr)
643{
6ace2891
JM
644 const u8 *key_rxmic;
645 const u8 *key_txmic;
f078f209 646
6ace2891
JM
647 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
648 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR
649
650 if (addr == NULL) {
651 /* Group key installation */
6ace2891
JM
652 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
653 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR
654 }
655 if (!sc->sc_splitmic) {
656 /*
657 * data key goes at first index,
658 * the hal handles the MIC keys at index+64.
659 */
660 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
661 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 662 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR
663 }
664 /*
665 * TX key goes at first index, RX key at +32.
666 * The hal handles the MIC keys at index+64.
667 */
668 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 669 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR
670 /* Txmic entry failed. No need to proceed further */
671 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 672 "Setting TX MIC Key Failed\n");
f078f209
LR
673 return 0;
674 }
675
676 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
677 /* XXX delete tx key on failure? */
6ace2891
JM
678 return ath_keyset(sc, keyix + 32, hk, addr);
679}
680
681static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
682{
683 int i;
684
685 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
686 if (test_bit(i, sc->sc_keymap) ||
687 test_bit(i + 64, sc->sc_keymap))
688 continue; /* At least one part of TKIP key allocated */
689 if (sc->sc_splitmic &&
690 (test_bit(i + 32, sc->sc_keymap) ||
691 test_bit(i + 64 + 32, sc->sc_keymap)))
692 continue; /* At least one part of TKIP key allocated */
693
694 /* Found a free slot for a TKIP key */
695 return i;
696 }
697 return -1;
698}
699
700static int ath_reserve_key_cache_slot(struct ath_softc *sc)
701{
702 int i;
703
704 /* First, try to find slots that would not be available for TKIP. */
705 if (sc->sc_splitmic) {
706 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
707 if (!test_bit(i, sc->sc_keymap) &&
708 (test_bit(i + 32, sc->sc_keymap) ||
709 test_bit(i + 64, sc->sc_keymap) ||
710 test_bit(i + 64 + 32, sc->sc_keymap)))
711 return i;
712 if (!test_bit(i + 32, sc->sc_keymap) &&
713 (test_bit(i, sc->sc_keymap) ||
714 test_bit(i + 64, sc->sc_keymap) ||
715 test_bit(i + 64 + 32, sc->sc_keymap)))
716 return i + 32;
717 if (!test_bit(i + 64, sc->sc_keymap) &&
718 (test_bit(i , sc->sc_keymap) ||
719 test_bit(i + 32, sc->sc_keymap) ||
720 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 721 return i + 64;
6ace2891
JM
722 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
723 (test_bit(i, sc->sc_keymap) ||
724 test_bit(i + 32, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap)))
ea612132 726 return i + 64 + 32;
6ace2891
JM
727 }
728 } else {
729 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
730 if (!test_bit(i, sc->sc_keymap) &&
731 test_bit(i + 64, sc->sc_keymap))
732 return i;
733 if (test_bit(i, sc->sc_keymap) &&
734 !test_bit(i + 64, sc->sc_keymap))
735 return i + 64;
736 }
737 }
738
739 /* No partially used TKIP slots, pick any available slot */
740 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM
741 /* Do not allow slots that could be needed for TKIP group keys
742 * to be used. This limitation could be removed if we know that
743 * TKIP will not be used. */
744 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
745 continue;
746 if (sc->sc_splitmic) {
747 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
748 continue;
749 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
750 continue;
751 }
752
6ace2891
JM
753 if (!test_bit(i, sc->sc_keymap))
754 return i; /* Found a free slot for a key */
755 }
756
757 /* No free slot found */
758 return -1;
f078f209
LR
759}
760
761static int ath_key_config(struct ath_softc *sc,
dc822b5d 762 struct ieee80211_sta *sta,
f078f209
LR
763 struct ieee80211_key_conf *key)
764{
f078f209
LR
765 struct ath9k_keyval hk;
766 const u8 *mac = NULL;
767 int ret = 0;
6ace2891 768 int idx;
f078f209
LR
769
770 memset(&hk, 0, sizeof(hk));
771
772 switch (key->alg) {
773 case ALG_WEP:
774 hk.kv_type = ATH9K_CIPHER_WEP;
775 break;
776 case ALG_TKIP:
777 hk.kv_type = ATH9K_CIPHER_TKIP;
778 break;
779 case ALG_CCMP:
780 hk.kv_type = ATH9K_CIPHER_AES_CCM;
781 break;
782 default:
ca470b29 783 return -EOPNOTSUPP;
f078f209
LR
784 }
785
6ace2891 786 hk.kv_len = key->keylen;
f078f209
LR
787 memcpy(hk.kv_val, key->key, key->keylen);
788
6ace2891
JM
789 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
790 /* For now, use the default keys for broadcast keys. This may
791 * need to change with virtual interfaces. */
792 idx = key->keyidx;
793 } else if (key->keyidx) {
794 struct ieee80211_vif *vif;
f078f209 795
dc822b5d
JB
796 if (WARN_ON(!sta))
797 return -EOPNOTSUPP;
798 mac = sta->addr;
799
6ace2891
JM
800 vif = sc->sc_vaps[0];
801 if (vif->type != NL80211_IFTYPE_AP) {
802 /* Only keyidx 0 should be used with unicast key, but
803 * allow this for client mode for now. */
804 idx = key->keyidx;
805 } else
806 return -EIO;
f078f209 807 } else {
dc822b5d
JB
808 if (WARN_ON(!sta))
809 return -EOPNOTSUPP;
810 mac = sta->addr;
811
6ace2891
JM
812 if (key->alg == ALG_TKIP)
813 idx = ath_reserve_key_cache_slot_tkip(sc);
814 else
815 idx = ath_reserve_key_cache_slot(sc);
816 if (idx < 0)
ca470b29 817 return -ENOSPC; /* no free key cache entries */
f078f209
LR
818 }
819
820 if (key->alg == ALG_TKIP)
6ace2891 821 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 822 else
6ace2891 823 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR
824
825 if (!ret)
826 return -EIO;
827
6ace2891
JM
828 set_bit(idx, sc->sc_keymap);
829 if (key->alg == ALG_TKIP) {
830 set_bit(idx + 64, sc->sc_keymap);
831 if (sc->sc_splitmic) {
832 set_bit(idx + 32, sc->sc_keymap);
833 set_bit(idx + 64 + 32, sc->sc_keymap);
834 }
835 }
836
837 return idx;
f078f209
LR
838}
839
840static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
841{
6ace2891
JM
842 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
843 if (key->hw_key_idx < IEEE80211_WEP_NKID)
844 return;
845
846 clear_bit(key->hw_key_idx, sc->sc_keymap);
847 if (key->alg != ALG_TKIP)
848 return;
f078f209 849
6ace2891
JM
850 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
851 if (sc->sc_splitmic) {
852 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
853 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
854 }
f078f209
LR
855}
856
eb2599ca
S
857static void setup_ht_cap(struct ath_softc *sc,
858 struct ieee80211_sta_ht_cap *ht_info)
f078f209 859{
60653678
S
860#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
861#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 862
d9fe60de
JB
863 ht_info->ht_supported = true;
864 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
865 IEEE80211_HT_CAP_SM_PS |
866 IEEE80211_HT_CAP_SGI_40 |
867 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 868
60653678
S
869 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
870 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 871
d9fe60de
JB
872 /* set up supported mcs set */
873 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca
S
874
875 switch(sc->sc_rx_chainmask) {
876 case 1:
877 ht_info->mcs.rx_mask[0] = 0xff;
878 break;
3c457265 879 case 3:
eb2599ca
S
880 case 5:
881 case 7:
882 default:
883 ht_info->mcs.rx_mask[0] = 0xff;
884 ht_info->mcs.rx_mask[1] = 0xff;
885 break;
886 }
887
d9fe60de 888 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR
889}
890
8feceb67 891static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 892 struct ieee80211_vif *vif,
8feceb67 893 struct ieee80211_bss_conf *bss_conf)
f078f209 894{
5640b08e 895 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 896
8feceb67 897 if (bss_conf->assoc) {
094d05dc
S
898 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
899 bss_conf->aid, sc->sc_curbssid);
f078f209 900
8feceb67 901 /* New association, store aid */
d97809db 902 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT
903 sc->sc_curaid = bss_conf->aid;
904 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
905 sc->sc_curaid);
906 }
f078f209 907
8feceb67
VT
908 /* Configure the beacon */
909 ath_beacon_config(sc, 0);
910 sc->sc_flags |= SC_OP_BEACONS;
f078f209 911
8feceb67
VT
912 /* Reset rssi stats */
913 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
914 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
915 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
916 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 917
6f255425
LR
918 /* Start ANI */
919 mod_timer(&sc->sc_ani.timer,
920 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
921
8feceb67 922 } else {
04bd4638 923 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 924 sc->sc_curaid = 0;
f078f209 925 }
8feceb67 926}
f078f209 927
8feceb67
VT
928/********************************/
929/* LED functions */
930/********************************/
f078f209 931
8feceb67
VT
932static void ath_led_brightness(struct led_classdev *led_cdev,
933 enum led_brightness brightness)
934{
935 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
936 struct ath_softc *sc = led->sc;
f078f209 937
8feceb67
VT
938 switch (brightness) {
939 case LED_OFF:
940 if (led->led_type == ATH_LED_ASSOC ||
941 led->led_type == ATH_LED_RADIO)
942 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (led->led_type == ATH_LED_RADIO) ? 1 :
945 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
946 break;
947 case LED_FULL:
948 if (led->led_type == ATH_LED_ASSOC)
949 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
950 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
951 break;
952 default:
953 break;
f078f209 954 }
8feceb67 955}
f078f209 956
8feceb67
VT
957static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
958 char *trigger)
959{
960 int ret;
f078f209 961
8feceb67
VT
962 led->sc = sc;
963 led->led_cdev.name = led->name;
964 led->led_cdev.default_trigger = trigger;
965 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 966
8feceb67
VT
967 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
968 if (ret)
969 DPRINTF(sc, ATH_DBG_FATAL,
970 "Failed to register led:%s", led->name);
971 else
972 led->registered = 1;
973 return ret;
974}
f078f209 975
8feceb67
VT
976static void ath_unregister_led(struct ath_led *led)
977{
978 if (led->registered) {
979 led_classdev_unregister(&led->led_cdev);
980 led->registered = 0;
f078f209 981 }
f078f209
LR
982}
983
8feceb67 984static void ath_deinit_leds(struct ath_softc *sc)
f078f209 985{
8feceb67
VT
986 ath_unregister_led(&sc->assoc_led);
987 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
988 ath_unregister_led(&sc->tx_led);
989 ath_unregister_led(&sc->rx_led);
990 ath_unregister_led(&sc->radio_led);
991 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
992}
f078f209 993
8feceb67
VT
994static void ath_init_leds(struct ath_softc *sc)
995{
996 char *trigger;
997 int ret;
f078f209 998
8feceb67
VT
999 /* Configure gpio 1 for output */
1000 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1001 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1002 /* LED off, active low */
1003 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1004
8feceb67
VT
1005 trigger = ieee80211_get_radio_led_name(sc->hw);
1006 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1007 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1008 ret = ath_register_led(sc, &sc->radio_led, trigger);
1009 sc->radio_led.led_type = ATH_LED_RADIO;
1010 if (ret)
1011 goto fail;
7dcfdcd9 1012
8feceb67
VT
1013 trigger = ieee80211_get_assoc_led_name(sc->hw);
1014 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1015 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1016 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1017 sc->assoc_led.led_type = ATH_LED_ASSOC;
1018 if (ret)
1019 goto fail;
f078f209 1020
8feceb67
VT
1021 trigger = ieee80211_get_tx_led_name(sc->hw);
1022 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1023 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1024 ret = ath_register_led(sc, &sc->tx_led, trigger);
1025 sc->tx_led.led_type = ATH_LED_TX;
1026 if (ret)
1027 goto fail;
f078f209 1028
8feceb67
VT
1029 trigger = ieee80211_get_rx_led_name(sc->hw);
1030 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1031 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1032 ret = ath_register_led(sc, &sc->rx_led, trigger);
1033 sc->rx_led.led_type = ATH_LED_RX;
1034 if (ret)
1035 goto fail;
f078f209 1036
8feceb67
VT
1037 return;
1038
1039fail:
1040 ath_deinit_leds(sc);
f078f209
LR
1041}
1042
e97275cb 1043#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1044
500c064d
VT
1045/*******************/
1046/* Rfkill */
1047/*******************/
1048
1049static void ath_radio_enable(struct ath_softc *sc)
1050{
1051 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR
1052 struct ieee80211_channel *channel = sc->hw->conf.channel;
1053 int r;
500c064d 1054
3cbb5dd7 1055 ath9k_ps_wakeup(sc);
500c064d 1056 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR
1057
1058 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1059
1060 if (r) {
500c064d 1061 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR
1062 "Unable to reset channel %u (%uMhz) ",
1063 "reset status %u\n",
1064 channel->center_freq, r);
500c064d
VT
1065 }
1066 spin_unlock_bh(&sc->sc_resetlock);
1067
1068 ath_update_txpow(sc);
1069 if (ath_startrecv(sc) != 0) {
1070 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1071 "Unable to restart recv logic\n");
500c064d
VT
1072 return;
1073 }
1074
1075 if (sc->sc_flags & SC_OP_BEACONS)
1076 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1077
1078 /* Re-Enable interrupts */
1079 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1080
1081 /* Enable LED */
1082 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1083 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1084 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1085
1086 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1087 ath9k_ps_restore(sc);
500c064d
VT
1088}
1089
1090static void ath_radio_disable(struct ath_softc *sc)
1091{
1092 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR
1093 struct ieee80211_channel *channel = sc->hw->conf.channel;
1094 int r;
500c064d 1095
3cbb5dd7 1096 ath9k_ps_wakeup(sc);
500c064d
VT
1097 ieee80211_stop_queues(sc->hw);
1098
1099 /* Disable LED */
1100 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1101 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1102
1103 /* Disable interrupts */
1104 ath9k_hw_set_interrupts(ah, 0);
1105
043a0405 1106 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
1107 ath_stoprecv(sc); /* turn off frame recv */
1108 ath_flushrecv(sc); /* flush recv queue */
1109
1110 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR
1111 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1112 if (r) {
500c064d 1113 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1114 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR
1115 "reset status %u\n",
1116 channel->center_freq, r);
500c064d
VT
1117 }
1118 spin_unlock_bh(&sc->sc_resetlock);
1119
1120 ath9k_hw_phy_disable(ah);
1121 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1122 ath9k_ps_restore(sc);
500c064d
VT
1123}
1124
1125static bool ath_is_rfkill_set(struct ath_softc *sc)
1126{
1127 struct ath_hal *ah = sc->sc_ah;
1128
1129 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1130 ah->ah_rfkill_polarity;
1131}
1132
1133/* h/w rfkill poll function */
1134static void ath_rfkill_poll(struct work_struct *work)
1135{
1136 struct ath_softc *sc = container_of(work, struct ath_softc,
1137 rf_kill.rfkill_poll.work);
1138 bool radio_on;
1139
1140 if (sc->sc_flags & SC_OP_INVALID)
1141 return;
1142
1143 radio_on = !ath_is_rfkill_set(sc);
1144
1145 /*
1146 * enable/disable radio only when there is a
1147 * state change in RF switch
1148 */
1149 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1150 enum rfkill_state state;
1151
1152 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1153 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1154 : RFKILL_STATE_HARD_BLOCKED;
1155 } else if (radio_on) {
1156 ath_radio_enable(sc);
1157 state = RFKILL_STATE_UNBLOCKED;
1158 } else {
1159 ath_radio_disable(sc);
1160 state = RFKILL_STATE_HARD_BLOCKED;
1161 }
1162
1163 if (state == RFKILL_STATE_HARD_BLOCKED)
1164 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1165 else
1166 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1167
1168 rfkill_force_state(sc->rf_kill.rfkill, state);
1169 }
1170
1171 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1172 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1173}
1174
1175/* s/w rfkill handler */
1176static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1177{
1178 struct ath_softc *sc = data;
1179
1180 switch (state) {
1181 case RFKILL_STATE_SOFT_BLOCKED:
1182 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1183 SC_OP_RFKILL_SW_BLOCKED)))
1184 ath_radio_disable(sc);
1185 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1186 return 0;
1187 case RFKILL_STATE_UNBLOCKED:
1188 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1189 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1190 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1191 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1192 "radio as it is disabled by h/w\n");
500c064d
VT
1193 return -EPERM;
1194 }
1195 ath_radio_enable(sc);
1196 }
1197 return 0;
1198 default:
1199 return -EINVAL;
1200 }
1201}
1202
1203/* Init s/w rfkill */
1204static int ath_init_sw_rfkill(struct ath_softc *sc)
1205{
1206 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1207 RFKILL_TYPE_WLAN);
1208 if (!sc->rf_kill.rfkill) {
1209 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1210 return -ENOMEM;
1211 }
1212
1213 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1214 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1215 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1216 sc->rf_kill.rfkill->data = sc;
1217 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1218 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1219 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1220
1221 return 0;
1222}
1223
1224/* Deinitialize rfkill */
1225static void ath_deinit_rfkill(struct ath_softc *sc)
1226{
1227 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1228 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1229
1230 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1231 rfkill_unregister(sc->rf_kill.rfkill);
1232 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1233 sc->rf_kill.rfkill = NULL;
1234 }
1235}
9c84b797
S
1236
1237static int ath_start_rfkill_poll(struct ath_softc *sc)
1238{
1239 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1240 queue_delayed_work(sc->hw->workqueue,
1241 &sc->rf_kill.rfkill_poll, 0);
1242
1243 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1244 if (rfkill_register(sc->rf_kill.rfkill)) {
1245 DPRINTF(sc, ATH_DBG_FATAL,
1246 "Unable to register rfkill\n");
1247 rfkill_free(sc->rf_kill.rfkill);
1248
1249 /* Deinitialize the device */
39c3c2f2 1250 ath_cleanup(sc);
9c84b797
S
1251 return -EIO;
1252 } else {
1253 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1254 }
1255 }
1256
1257 return 0;
1258}
500c064d
VT
1259#endif /* CONFIG_RFKILL */
1260
6baff7f9 1261void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ
1262{
1263 ath_detach(sc);
1264 free_irq(sc->irq, sc);
1265 ath_bus_cleanup(sc);
1266 ieee80211_free_hw(sc->hw);
1267}
1268
6baff7f9 1269void ath_detach(struct ath_softc *sc)
f078f209 1270{
8feceb67 1271 struct ieee80211_hw *hw = sc->hw;
9c84b797 1272 int i = 0;
f078f209 1273
3cbb5dd7
VN
1274 ath9k_ps_wakeup(sc);
1275
04bd4638 1276 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1277
e97275cb 1278#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT
1279 ath_deinit_rfkill(sc);
1280#endif
3fcdfb4b
VT
1281 ath_deinit_leds(sc);
1282
1283 ieee80211_unregister_hw(hw);
8feceb67
VT
1284 ath_rx_cleanup(sc);
1285 ath_tx_cleanup(sc);
f078f209 1286
9c84b797
S
1287 tasklet_kill(&sc->intr_tq);
1288 tasklet_kill(&sc->bcon_tasklet);
f078f209 1289
9c84b797
S
1290 if (!(sc->sc_flags & SC_OP_INVALID))
1291 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1292
9c84b797
S
1293 /* cleanup tx queues */
1294 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1295 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1296 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S
1297
1298 ath9k_hw_detach(sc->sc_ah);
826d2680 1299 ath9k_exit_debug(sc);
3cbb5dd7 1300 ath9k_ps_restore(sc);
f078f209
LR
1301}
1302
ff37e337
S
1303static int ath_init(u16 devid, struct ath_softc *sc)
1304{
1305 struct ath_hal *ah = NULL;
1306 int status;
1307 int error = 0, i;
1308 int csz = 0;
1309
1310 /* XXX: hardware will not be ready until ath_open() being called */
1311 sc->sc_flags |= SC_OP_INVALID;
88b126af 1312
826d2680
S
1313 if (ath9k_init_debug(sc) < 0)
1314 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S
1315
1316 spin_lock_init(&sc->sc_resetlock);
aa33de09 1317 mutex_init(&sc->mutex);
ff37e337
S
1318 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1319 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1320 (unsigned long)sc);
1321
1322 /*
1323 * Cache line size is used to size and align various
1324 * structures used to communicate with the hardware.
1325 */
88d15707 1326 ath_read_cachesize(sc, &csz);
ff37e337
S
1327 /* XXX assert csz is non-zero */
1328 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1329
1330 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1331 if (ah == NULL) {
1332 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1333 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S
1334 error = -ENXIO;
1335 goto bad;
1336 }
1337 sc->sc_ah = ah;
1338
1339 /* Get the hardware key cache size. */
1340 sc->sc_keymax = ah->ah_caps.keycache_size;
1341 if (sc->sc_keymax > ATH_KEYMAX) {
1342 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S
1343 "Warning, using only %u entries in %u key cache\n",
1344 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S
1345 sc->sc_keymax = ATH_KEYMAX;
1346 }
1347
1348 /*
1349 * Reset the key cache since some parts do not
1350 * reset the contents on initial power up.
1351 */
1352 for (i = 0; i < sc->sc_keymax; i++)
1353 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1354
5f8e077c 1355 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S
1356 goto bad;
1357
1358 /* default to MONITOR mode */
d97809db
CM
1359 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1360
ff37e337
S
1361 /* Setup rate tables */
1362
1363 ath_rate_attach(sc);
1364 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1365 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1366
1367 /*
1368 * Allocate hardware transmit queues: one queue for
1369 * beacon frames and one data queue for each QoS
1370 * priority. Note that the hal handles reseting
1371 * these queues at the needed time.
1372 */
b77f483f
S
1373 sc->beacon.beaconq = ath_beaconq_setup(ah);
1374 if (sc->beacon.beaconq == -1) {
ff37e337 1375 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1376 "Unable to setup a beacon xmit queue\n");
ff37e337
S
1377 error = -EIO;
1378 goto bad2;
1379 }
b77f483f
S
1380 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1381 if (sc->beacon.cabq == NULL) {
ff37e337 1382 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1383 "Unable to setup CAB xmit queue\n");
ff37e337
S
1384 error = -EIO;
1385 goto bad2;
1386 }
1387
1388 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1389 ath_cabq_update(sc);
1390
b77f483f
S
1391 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1392 sc->tx.hwq_map[i] = -1;
ff37e337
S
1393
1394 /* Setup data queues */
1395 /* NB: ensure BK queue is the lowest priority h/w queue */
1396 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1397 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1398 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S
1399 error = -EIO;
1400 goto bad2;
1401 }
1402
1403 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1404 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1405 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S
1406 error = -EIO;
1407 goto bad2;
1408 }
1409 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1410 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1411 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S
1412 error = -EIO;
1413 goto bad2;
1414 }
1415 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1416 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1417 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S
1418 error = -EIO;
1419 goto bad2;
1420 }
1421
1422 /* Initializes the noise floor to a reasonable default value.
1423 * Later on this will be updated during ANI processing. */
1424
1425 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1426 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1427
1428 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1429 ATH9K_CIPHER_TKIP, NULL)) {
1430 /*
1431 * Whether we should enable h/w TKIP MIC.
1432 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1433 * report WMM capable, so it's always safe to turn on
1434 * TKIP MIC in this case.
1435 */
1436 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1437 0, 1, NULL);
1438 }
1439
1440 /*
1441 * Check whether the separate key cache entries
1442 * are required to handle both tx+rx MIC keys.
1443 * With split mic keys the number of stations is limited
1444 * to 27 otherwise 59.
1445 */
1446 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1447 ATH9K_CIPHER_TKIP, NULL)
1448 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1449 ATH9K_CIPHER_MIC, NULL)
1450 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1451 0, NULL))
1452 sc->sc_splitmic = 1;
1453
1454 /* turn on mcast key search if possible */
1455 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1456 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1457 1, NULL);
1458
1459 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1460 sc->sc_config.txpowlimit_override = 0;
1461
1462 /* 11n Capabilities */
1463 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1464 sc->sc_flags |= SC_OP_TXAGGR;
1465 sc->sc_flags |= SC_OP_RXAGGR;
1466 }
1467
1468 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1469 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1470
1471 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1472 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S
1473
1474 ath9k_hw_getmac(ah, sc->sc_myaddr);
1475 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1476 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1477 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1478 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1479 }
1480
b77f483f 1481 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S
1482
1483 /* initialize beacon slots */
b77f483f
S
1484 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1485 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S
1486
1487 /* save MISC configurations */
1488 sc->sc_config.swBeaconProcess = 1;
1489
ff37e337
S
1490 /* setup channels and rates */
1491
5f8e077c 1492 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S
1493 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1494 sc->rates[IEEE80211_BAND_2GHZ];
1495 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR
1496 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1497 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337
S
1498
1499 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
5f8e077c 1500 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S
1501 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1502 sc->rates[IEEE80211_BAND_5GHZ];
1503 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR
1504 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1505 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S
1506 }
1507
c97c92d9
VT
1508 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1509 ath9k_hw_btcoex_enable(sc->sc_ah);
1510
ff37e337
S
1511 return 0;
1512bad2:
1513 /* cleanup tx queues */
1514 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1515 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1516 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S
1517bad:
1518 if (ah)
1519 ath9k_hw_detach(ah);
1520
1521 return error;
1522}
1523
6baff7f9 1524int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1525{
8feceb67
VT
1526 struct ieee80211_hw *hw = sc->hw;
1527 int error = 0;
f078f209 1528
04bd4638 1529 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1530
8feceb67
VT
1531 error = ath_init(devid, sc);
1532 if (error != 0)
1533 return error;
f078f209 1534
8feceb67 1535 /* get mac address from hardware and set in mac80211 */
f078f209 1536
8feceb67 1537 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1538
9c84b797
S
1539 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1540 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1541 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN
1542 IEEE80211_HW_AMPDU_AGGREGATION |
1543 IEEE80211_HW_SUPPORTS_PS |
1544 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1545
0ced0e17
JM
1546 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1547 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1548
9c84b797
S
1549 hw->wiphy->interface_modes =
1550 BIT(NL80211_IFTYPE_AP) |
1551 BIT(NL80211_IFTYPE_STATION) |
1552 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1553
5f8e077c
LR
1554 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1555 hw->wiphy->strict_regulatory = true;
1556
8feceb67 1557 hw->queues = 4;
e63835b0
S
1558 hw->max_rates = 4;
1559 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1560 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1561 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1562
8feceb67 1563 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1564
9c84b797 1565 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1566 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
9c84b797 1567 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
eb2599ca 1568 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S
1569 }
1570
1571 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1572 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1573 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1574 &sc->sbands[IEEE80211_BAND_5GHZ];
1575
db93e7b5
SB
1576 /* initialize tx/rx engine */
1577 error = ath_tx_init(sc, ATH_TXBUF);
1578 if (error != 0)
1579 goto detach;
8feceb67 1580
db93e7b5
SB
1581 error = ath_rx_init(sc, ATH_RXBUF);
1582 if (error != 0)
1583 goto detach;
8feceb67 1584
e97275cb 1585#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT
1586 /* Initialze h/w Rfkill */
1587 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1588 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1589
1590 /* Initialize s/w rfkill */
1591 if (ath_init_sw_rfkill(sc))
1592 goto detach;
1593#endif
1594
5f8e077c
LR
1595 if (ath9k_is_world_regd(sc->sc_ah)) {
1596 /* Anything applied here (prior to wiphy registratoin) gets
1597 * saved on the wiphy orig_* parameters */
1598 const struct ieee80211_regdomain *regd =
1599 ath9k_world_regdomain(sc->sc_ah);
1600 hw->wiphy->custom_regulatory = true;
1601 hw->wiphy->strict_regulatory = false;
1602 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1603 ath9k_reg_apply_radar_flags(hw->wiphy);
1604 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1605 } else {
1606 /* This gets applied in the case of the absense of CRDA,
1607 * its our own custom world regulatory domain, similar to
1608 * cfg80211's but we enable passive scanning */
1609 const struct ieee80211_regdomain *regd =
1610 ath9k_default_world_regdomain();
1611 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1612 ath9k_reg_apply_radar_flags(hw->wiphy);
1613 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1614 }
1615
db93e7b5 1616 error = ieee80211_register_hw(hw);
8feceb67 1617
5f8e077c
LR
1618 if (!ath9k_is_world_regd(sc->sc_ah))
1619 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1620
db93e7b5
SB
1621 /* Initialize LED control */
1622 ath_init_leds(sc);
8feceb67 1623
5f8e077c 1624
8feceb67
VT
1625 return 0;
1626detach:
1627 ath_detach(sc);
8feceb67 1628 return error;
f078f209
LR
1629}
1630
ff37e337
S
1631int ath_reset(struct ath_softc *sc, bool retry_tx)
1632{
1633 struct ath_hal *ah = sc->sc_ah;
030bb495 1634 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1635 int r;
ff37e337
S
1636
1637 ath9k_hw_set_interrupts(ah, 0);
043a0405 1638 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
1639 ath_stoprecv(sc);
1640 ath_flushrecv(sc);
1641
1642 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR
1643 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1644 if (r)
ff37e337 1645 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1646 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S
1647 spin_unlock_bh(&sc->sc_resetlock);
1648
1649 if (ath_startrecv(sc) != 0)
04bd4638 1650 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S
1651
1652 /*
1653 * We may be doing a reset in response to a request
1654 * that changes the channel so update any state that
1655 * might change as a result.
1656 */
ce111bad 1657 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1658
1659 ath_update_txpow(sc);
1660
1661 if (sc->sc_flags & SC_OP_BEACONS)
1662 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1663
1664 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1665
1666 if (retry_tx) {
1667 int i;
1668 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1669 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1670 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1671 ath_txq_schedule(sc, &sc->tx.txq[i]);
1672 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1673 }
1674 }
1675 }
1676
ae8d2858 1677 return r;
ff37e337
S
1678}
1679
1680/*
1681 * This function will allocate both the DMA descriptor structure, and the
1682 * buffers it contains. These are used to contain the descriptors used
1683 * by the system.
1684*/
1685int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1686 struct list_head *head, const char *name,
1687 int nbuf, int ndesc)
1688{
1689#define DS2PHYS(_dd, _ds) \
1690 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1691#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1692#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1693
1694 struct ath_desc *ds;
1695 struct ath_buf *bf;
1696 int i, bsize, error;
1697
04bd4638
S
1698 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1699 name, nbuf, ndesc);
ff37e337
S
1700
1701 /* ath_desc must be a multiple of DWORDs */
1702 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1703 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S
1704 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708
1709 dd->dd_name = name;
1710 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1711
1712 /*
1713 * Need additional DMA memory because we can't use
1714 * descriptors that cross the 4K page boundary. Assume
1715 * one skipped descriptor per 4K page.
1716 */
1717 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1718 u32 ndesc_skipped =
1719 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1720 u32 dma_len;
1721
1722 while (ndesc_skipped) {
1723 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1724 dd->dd_desc_len += dma_len;
1725
1726 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1727 };
1728 }
1729
1730 /* allocate descriptors */
7da3c55c
GJ
1731 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1732 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S
1733 if (dd->dd_desc == NULL) {
1734 error = -ENOMEM;
1735 goto fail;
1736 }
1737 ds = dd->dd_desc;
04bd4638
S
1738 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1739 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S
1740 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1741
1742 /* allocate buffers */
1743 bsize = sizeof(struct ath_buf) * nbuf;
1744 bf = kmalloc(bsize, GFP_KERNEL);
1745 if (bf == NULL) {
1746 error = -ENOMEM;
1747 goto fail2;
1748 }
1749 memset(bf, 0, bsize);
1750 dd->dd_bufptr = bf;
1751
1752 INIT_LIST_HEAD(head);
1753 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1754 bf->bf_desc = ds;
1755 bf->bf_daddr = DS2PHYS(dd, ds);
1756
1757 if (!(sc->sc_ah->ah_caps.hw_caps &
1758 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1759 /*
1760 * Skip descriptor addresses which can cause 4KB
1761 * boundary crossing (addr + length) with a 32 dword
1762 * descriptor fetch.
1763 */
1764 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1765 ASSERT((caddr_t) bf->bf_desc <
1766 ((caddr_t) dd->dd_desc +
1767 dd->dd_desc_len));
1768
1769 ds += ndesc;
1770 bf->bf_desc = ds;
1771 bf->bf_daddr = DS2PHYS(dd, ds);
1772 }
1773 }
1774 list_add_tail(&bf->list, head);
1775 }
1776 return 0;
1777fail2:
7da3c55c
GJ
1778 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1779 dd->dd_desc_paddr);
ff37e337
S
1780fail:
1781 memset(dd, 0, sizeof(*dd));
1782 return error;
1783#undef ATH_DESC_4KB_BOUND_CHECK
1784#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1785#undef DS2PHYS
1786}
1787
1788void ath_descdma_cleanup(struct ath_softc *sc,
1789 struct ath_descdma *dd,
1790 struct list_head *head)
1791{
7da3c55c
GJ
1792 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1793 dd->dd_desc_paddr);
ff37e337
S
1794
1795 INIT_LIST_HEAD(head);
1796 kfree(dd->dd_bufptr);
1797 memset(dd, 0, sizeof(*dd));
1798}
1799
1800int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1801{
1802 int qnum;
1803
1804 switch (queue) {
1805 case 0:
b77f483f 1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S
1807 break;
1808 case 1:
b77f483f 1809 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S
1810 break;
1811 case 2:
b77f483f 1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1813 break;
1814 case 3:
b77f483f 1815 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S
1816 break;
1817 default:
b77f483f 1818 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1819 break;
1820 }
1821
1822 return qnum;
1823}
1824
1825int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1826{
1827 int qnum;
1828
1829 switch (queue) {
1830 case ATH9K_WME_AC_VO:
1831 qnum = 0;
1832 break;
1833 case ATH9K_WME_AC_VI:
1834 qnum = 1;
1835 break;
1836 case ATH9K_WME_AC_BE:
1837 qnum = 2;
1838 break;
1839 case ATH9K_WME_AC_BK:
1840 qnum = 3;
1841 break;
1842 default:
1843 qnum = -1;
1844 break;
1845 }
1846
1847 return qnum;
1848}
1849
5f8e077c
LR
1850/* XXX: Remove me once we don't depend on ath9k_channel for all
1851 * this redundant data */
1852static void ath9k_update_ichannel(struct ath_softc *sc,
1853 struct ath9k_channel *ichan)
1854{
1855 struct ieee80211_hw *hw = sc->hw;
1856 struct ieee80211_channel *chan = hw->conf.channel;
1857 struct ieee80211_conf *conf = &hw->conf;
1858
1859 ichan->channel = chan->center_freq;
1860 ichan->chan = chan;
1861
1862 if (chan->band == IEEE80211_BAND_2GHZ) {
1863 ichan->chanmode = CHANNEL_G;
1864 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1865 } else {
1866 ichan->chanmode = CHANNEL_A;
1867 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1868 }
1869
1870 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1871
1872 if (conf_is_ht(conf)) {
1873 if (conf_is_ht40(conf))
1874 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1875
1876 ichan->chanmode = ath_get_extchanmode(sc, chan,
1877 conf->channel_type);
1878 }
1879}
1880
ff37e337
S
1881/**********************/
1882/* mac80211 callbacks */
1883/**********************/
1884
8feceb67 1885static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR
1886{
1887 struct ath_softc *sc = hw->priv;
8feceb67 1888 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1889 struct ath9k_channel *init_channel;
ae8d2858 1890 int r, pos;
f078f209 1891
04bd4638
S
1892 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1893 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1894
8feceb67 1895 /* setup initial channel */
f078f209 1896
5f8e077c 1897 pos = curchan->hw_value;
f078f209 1898
ff37e337 1899 init_channel = &sc->sc_ah->ah_channels[pos];
5f8e077c 1900 ath9k_update_ichannel(sc, init_channel);
ff37e337
S
1901
1902 /* Reset SERDES registers */
1903 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1904
1905 /*
1906 * The basic interface to setting the hardware in a good
1907 * state is ``reset''. On return the hardware is known to
1908 * be powered up and with interrupts disabled. This must
1909 * be followed by initialization of the appropriate bits
1910 * and then setup of the interrupt mask.
1911 */
1912 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR
1913 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1914 if (r) {
ff37e337 1915 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR
1916 "Unable to reset hardware; reset status %u "
1917 "(freq %u MHz)\n", r,
1918 curchan->center_freq);
ff37e337 1919 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1920 return r;
ff37e337
S
1921 }
1922 spin_unlock_bh(&sc->sc_resetlock);
1923
1924 /*
1925 * This is needed only to setup initial state
1926 * but it's best done after a reset.
1927 */
1928 ath_update_txpow(sc);
8feceb67 1929
ff37e337
S
1930 /*
1931 * Setup the hardware after reset:
1932 * The receive engine is set going.
1933 * Frame transmit is handled entirely
1934 * in the frame output path; there's nothing to do
1935 * here except setup the interrupt mask.
1936 */
1937 if (ath_startrecv(sc) != 0) {
8feceb67 1938 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1939 "Unable to start recv logic\n");
ae8d2858 1940 return -EIO;
f078f209 1941 }
8feceb67 1942
ff37e337
S
1943 /* Setup our intr mask. */
1944 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1945 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1946 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1947
1948 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1949 sc->sc_imask |= ATH9K_INT_GTT;
1950
1951 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1952 sc->sc_imask |= ATH9K_INT_CST;
1953
1954 /*
1955 * Enable MIB interrupts when there are hardware phy counters.
1956 * Note we only do this (at the moment) for station mode.
1957 */
1958 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM
1959 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1960 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S
1961 sc->sc_imask |= ATH9K_INT_MIB;
1962 /*
1963 * Some hardware processes the TIM IE and fires an
1964 * interrupt when the TIM bit is set. For hardware
1965 * that does, if not overridden by configuration,
1966 * enable the TIM interrupt when operating as station.
1967 */
1968 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1969 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S
1970 !sc->sc_config.swBeaconProcess)
1971 sc->sc_imask |= ATH9K_INT_TIM;
1972
ce111bad 1973 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1974
1975 sc->sc_flags &= ~SC_OP_INVALID;
1976
1977 /* Disable BMISS interrupt when we're not associated */
1978 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1979 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1980
1981 ieee80211_wake_queues(sc->hw);
1982
e97275cb 1983#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1984 r = ath_start_rfkill_poll(sc);
500c064d 1985#endif
ae8d2858 1986 return r;
f078f209
LR
1987}
1988
8feceb67
VT
1989static int ath9k_tx(struct ieee80211_hw *hw,
1990 struct sk_buff *skb)
f078f209 1991{
528f0c6b 1992 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1993 struct ath_softc *sc = hw->priv;
528f0c6b 1994 struct ath_tx_control txctl;
8feceb67 1995 int hdrlen, padsize;
528f0c6b
S
1996
1997 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1998
8feceb67
VT
1999 /*
2000 * As a temporary workaround, assign seq# here; this will likely need
2001 * to be cleaned up to work better with Beacon transmission and virtual
2002 * BSSes.
2003 */
2004 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2005 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2006 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2007 sc->tx.seq_no += 0x10;
8feceb67 2008 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2009 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2010 }
f078f209 2011
8feceb67
VT
2012 /* Add the padding after the header if this is not already done */
2013 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2014 if (hdrlen & 3) {
2015 padsize = hdrlen % 4;
2016 if (skb_headroom(skb) < padsize)
2017 return -1;
2018 skb_push(skb, padsize);
2019 memmove(skb->data, skb->data + padsize, hdrlen);
2020 }
2021
528f0c6b
S
2022 /* Check if a tx queue is available */
2023
2024 txctl.txq = ath_test_get_txq(sc, skb);
2025 if (!txctl.txq)
2026 goto exit;
2027
04bd4638 2028 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2029
528f0c6b 2030 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2031 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2032 goto exit;
8feceb67
VT
2033 }
2034
528f0c6b
S
2035 return 0;
2036exit:
2037 dev_kfree_skb_any(skb);
8feceb67 2038 return 0;
f078f209
LR
2039}
2040
8feceb67 2041static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR
2042{
2043 struct ath_softc *sc = hw->priv;
f078f209 2044
9c84b797 2045 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2046 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S
2047 return;
2048 }
8feceb67 2049
04bd4638 2050 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S
2051
2052 ieee80211_stop_queues(sc->hw);
2053
2054 /* make sure h/w will not generate any interrupt
2055 * before setting the invalid flag. */
2056 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2057
2058 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2059 ath_drain_all_txq(sc, false);
ff37e337
S
2060 ath_stoprecv(sc);
2061 ath9k_hw_phy_disable(sc->sc_ah);
2062 } else
b77f483f 2063 sc->rx.rxlink = NULL;
ff37e337
S
2064
2065#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2066 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2067 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2068#endif
2069 /* disable HAL and put h/w to sleep */
2070 ath9k_hw_disable(sc->sc_ah);
2071 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2072
2073 sc->sc_flags |= SC_OP_INVALID;
500c064d 2074
04bd4638 2075 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
2076}
2077
8feceb67
VT
2078static int ath9k_add_interface(struct ieee80211_hw *hw,
2079 struct ieee80211_if_init_conf *conf)
f078f209
LR
2080{
2081 struct ath_softc *sc = hw->priv;
5640b08e 2082 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2083 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2084
8feceb67
VT
2085 /* Support only vap for now */
2086
2087 if (sc->sc_nvaps)
2088 return -ENOBUFS;
2089
2090 switch (conf->type) {
05c914fe 2091 case NL80211_IFTYPE_STATION:
d97809db 2092 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2093 break;
05c914fe 2094 case NL80211_IFTYPE_ADHOC:
d97809db 2095 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2096 break;
05c914fe 2097 case NL80211_IFTYPE_AP:
d97809db 2098 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR
2099 break;
2100 default:
2101 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2102 "Interface type %d not yet supported\n", conf->type);
8feceb67 2103 return -EOPNOTSUPP;
f078f209
LR
2104 }
2105
04bd4638 2106 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2107
5640b08e
S
2108 /* Set the VAP opmode */
2109 avp->av_opmode = ic_opmode;
2110 avp->av_bslot = -1;
2111
d97809db 2112 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S
2113 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2114
2115 sc->sc_vaps[0] = conf->vif;
2116 sc->sc_nvaps++;
2117
2118 /* Set the device opmode */
2119 sc->sc_ah->ah_opmode = ic_opmode;
2120
6f255425
LR
2121 if (conf->type == NL80211_IFTYPE_AP) {
2122 /* TODO: is this a suitable place to start ANI for AP mode? */
2123 /* Start ANI */
2124 mod_timer(&sc->sc_ani.timer,
2125 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2126 }
2127
8feceb67 2128 return 0;
f078f209
LR
2129}
2130
8feceb67
VT
2131static void ath9k_remove_interface(struct ieee80211_hw *hw,
2132 struct ieee80211_if_init_conf *conf)
f078f209 2133{
8feceb67 2134 struct ath_softc *sc = hw->priv;
5640b08e 2135 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2136
04bd4638 2137 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2138
6f255425
LR
2139 /* Stop ANI */
2140 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2141
8feceb67 2142 /* Reclaim beacon resources */
d97809db
CM
2143 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2144 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2145 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2146 ath_beacon_return(sc, avp);
580f0b8a 2147 }
f078f209 2148
8feceb67 2149 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2150
5640b08e
S
2151 sc->sc_vaps[0] = NULL;
2152 sc->sc_nvaps--;
f078f209
LR
2153}
2154
e8975581 2155static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2156{
8feceb67 2157 struct ath_softc *sc = hw->priv;
e8975581 2158 struct ieee80211_conf *conf = &hw->conf;
f078f209 2159
aa33de09 2160 mutex_lock(&sc->mutex);
3cbb5dd7
VN
2161 if (changed & IEEE80211_CONF_CHANGE_PS) {
2162 if (conf->flags & IEEE80211_CONF_PS) {
2163 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2164 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2165 ath9k_hw_set_interrupts(sc->sc_ah,
2166 sc->sc_imask);
2167 }
2168 ath9k_hw_setrxabort(sc->sc_ah, 1);
2169 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2170 } else {
2171 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2172 ath9k_hw_setrxabort(sc->sc_ah, 0);
2173 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2174 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2175 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2176 ath9k_hw_set_interrupts(sc->sc_ah,
2177 sc->sc_imask);
2178 }
2179 }
2180 }
2181
4797938c 2182 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2183 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2184 int pos = curchan->hw_value;
ae5eb026 2185
04bd4638
S
2186 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2187 curchan->center_freq);
f078f209 2188
5f8e077c
LR
2189 /* XXX: remove me eventualy */
2190 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
e11602b7 2191
ecf70441 2192 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2193
e11602b7 2194 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2195 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2196 mutex_unlock(&sc->mutex);
e11602b7
S
2197 return -EINVAL;
2198 }
094d05dc 2199 }
f078f209 2200
5c020dc6
LR
2201 if (changed & IEEE80211_CONF_CHANGE_POWER)
2202 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2203
aa33de09 2204 mutex_unlock(&sc->mutex);
f078f209
LR
2205 return 0;
2206}
2207
8feceb67
VT
2208static int ath9k_config_interface(struct ieee80211_hw *hw,
2209 struct ieee80211_vif *vif,
2210 struct ieee80211_if_conf *conf)
c83be688 2211{
8feceb67
VT
2212 struct ath_softc *sc = hw->priv;
2213 struct ath_hal *ah = sc->sc_ah;
5640b08e 2214 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT
2215 u32 rfilt = 0;
2216 int error, i;
c83be688 2217
8feceb67
VT
2218 /* TODO: Need to decide which hw opmode to use for multi-interface
2219 * cases */
05c914fe 2220 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM
2221 ah->ah_opmode != NL80211_IFTYPE_AP) {
2222 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT
2223 ath9k_hw_setopmode(ah);
2224 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2225 /* Request full reset to get hw opmode changed properly */
2226 sc->sc_flags |= SC_OP_FULL_RESET;
2227 }
c83be688 2228
8feceb67
VT
2229 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2230 !is_zero_ether_addr(conf->bssid)) {
2231 switch (vif->type) {
05c914fe
JB
2232 case NL80211_IFTYPE_STATION:
2233 case NL80211_IFTYPE_ADHOC:
8feceb67
VT
2234 /* Set BSSID */
2235 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2236 sc->sc_curaid = 0;
2237 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2238 sc->sc_curaid);
c83be688 2239
8feceb67
VT
2240 /* Set aggregation protection mode parameters */
2241 sc->sc_config.ath_aggr_prot = 0;
c83be688 2242
8feceb67 2243 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S
2244 "RX filter 0x%x bssid %pM aid 0x%x\n",
2245 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2246
8feceb67
VT
2247 /* need to reconfigure the beacon */
2248 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2249
8feceb67
VT
2250 break;
2251 default:
2252 break;
2253 }
2254 }
c83be688 2255
8feceb67 2256 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB
2257 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2258 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT
2259 /*
2260 * Allocate and setup the beacon frame.
2261 *
2262 * Stop any previous beacon DMA. This may be
2263 * necessary, for example, when an ibss merge
2264 * causes reconfiguration; we may be called
2265 * with beacon transmission active.
2266 */
b77f483f 2267 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2268
8feceb67
VT
2269 error = ath_beacon_alloc(sc, 0);
2270 if (error != 0)
2271 return error;
c83be688 2272
8feceb67
VT
2273 ath_beacon_sync(sc, 0);
2274 }
c83be688 2275
8feceb67 2276 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2277 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT
2278 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2279 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2280 ath9k_hw_keysetmac(sc->sc_ah,
2281 (u16)i,
2282 sc->sc_curbssid);
2283 }
c83be688 2284
8feceb67 2285 /* Only legacy IBSS for now */
05c914fe 2286 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2287 ath_update_chainmask(sc, 0);
f078f209 2288
8feceb67
VT
2289 return 0;
2290}
f078f209 2291
8feceb67
VT
2292#define SUPPORTED_FILTERS \
2293 (FIF_PROMISC_IN_BSS | \
2294 FIF_ALLMULTI | \
2295 FIF_CONTROL | \
2296 FIF_OTHER_BSS | \
2297 FIF_BCN_PRBRESP_PROMISC | \
2298 FIF_FCSFAIL)
c83be688 2299
8feceb67
VT
2300/* FIXME: sc->sc_full_reset ? */
2301static void ath9k_configure_filter(struct ieee80211_hw *hw,
2302 unsigned int changed_flags,
2303 unsigned int *total_flags,
2304 int mc_count,
2305 struct dev_mc_list *mclist)
2306{
2307 struct ath_softc *sc = hw->priv;
2308 u32 rfilt;
f078f209 2309
8feceb67
VT
2310 changed_flags &= SUPPORTED_FILTERS;
2311 *total_flags &= SUPPORTED_FILTERS;
f078f209 2312
b77f483f 2313 sc->rx.rxfilter = *total_flags;
8feceb67
VT
2314 rfilt = ath_calcrxfilter(sc);
2315 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2316
8feceb67
VT
2317 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2318 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2319 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2320 }
f078f209 2321
b77f483f 2322 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2323}
f078f209 2324
8feceb67
VT
2325static void ath9k_sta_notify(struct ieee80211_hw *hw,
2326 struct ieee80211_vif *vif,
2327 enum sta_notify_cmd cmd,
17741cdc 2328 struct ieee80211_sta *sta)
8feceb67
VT
2329{
2330 struct ath_softc *sc = hw->priv;
f078f209 2331
8feceb67
VT
2332 switch (cmd) {
2333 case STA_NOTIFY_ADD:
5640b08e 2334 ath_node_attach(sc, sta);
8feceb67
VT
2335 break;
2336 case STA_NOTIFY_REMOVE:
b5aa9bf9 2337 ath_node_detach(sc, sta);
8feceb67
VT
2338 break;
2339 default:
2340 break;
2341 }
f078f209
LR
2342}
2343
8feceb67
VT
2344static int ath9k_conf_tx(struct ieee80211_hw *hw,
2345 u16 queue,
2346 const struct ieee80211_tx_queue_params *params)
f078f209 2347{
8feceb67
VT
2348 struct ath_softc *sc = hw->priv;
2349 struct ath9k_tx_queue_info qi;
2350 int ret = 0, qnum;
f078f209 2351
8feceb67
VT
2352 if (queue >= WME_NUM_AC)
2353 return 0;
f078f209 2354
8feceb67
VT
2355 qi.tqi_aifs = params->aifs;
2356 qi.tqi_cwmin = params->cw_min;
2357 qi.tqi_cwmax = params->cw_max;
2358 qi.tqi_burstTime = params->txop;
2359 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2360
8feceb67 2361 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2362 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2363 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S
2364 queue, qnum, params->aifs, params->cw_min,
2365 params->cw_max, params->txop);
f078f209 2366
8feceb67
VT
2367 ret = ath_txq_update(sc, qnum, &qi);
2368 if (ret)
04bd4638 2369 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2370
8feceb67
VT
2371 return ret;
2372}
f078f209 2373
8feceb67
VT
2374static int ath9k_set_key(struct ieee80211_hw *hw,
2375 enum set_key_cmd cmd,
dc822b5d
JB
2376 struct ieee80211_vif *vif,
2377 struct ieee80211_sta *sta,
8feceb67
VT
2378 struct ieee80211_key_conf *key)
2379{
2380 struct ath_softc *sc = hw->priv;
2381 int ret = 0;
f078f209 2382
3cbb5dd7 2383 ath9k_ps_wakeup(sc);
04bd4638 2384 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2385
8feceb67
VT
2386 switch (cmd) {
2387 case SET_KEY:
dc822b5d 2388 ret = ath_key_config(sc, sta, key);
6ace2891
JM
2389 if (ret >= 0) {
2390 key->hw_key_idx = ret;
8feceb67
VT
2391 /* push IV and Michael MIC generation to stack */
2392 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2393 if (key->alg == ALG_TKIP)
2394 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM
2395 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2396 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2397 ret = 0;
8feceb67
VT
2398 }
2399 break;
2400 case DISABLE_KEY:
2401 ath_key_delete(sc, key);
8feceb67
VT
2402 break;
2403 default:
2404 ret = -EINVAL;
2405 }
f078f209 2406
3cbb5dd7 2407 ath9k_ps_restore(sc);
8feceb67
VT
2408 return ret;
2409}
f078f209 2410
8feceb67
VT
2411static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2412 struct ieee80211_vif *vif,
2413 struct ieee80211_bss_conf *bss_conf,
2414 u32 changed)
2415{
2416 struct ath_softc *sc = hw->priv;
f078f209 2417
8feceb67 2418 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2419 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT
2420 bss_conf->use_short_preamble);
2421 if (bss_conf->use_short_preamble)
2422 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2423 else
2424 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2425 }
f078f209 2426
8feceb67 2427 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2428 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT
2429 bss_conf->use_cts_prot);
2430 if (bss_conf->use_cts_prot &&
2431 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2432 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2433 else
2434 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2435 }
f078f209 2436
8feceb67 2437 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2438 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2439 bss_conf->assoc);
5640b08e 2440 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT
2441 }
2442}
f078f209 2443
8feceb67
VT
2444static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2445{
2446 u64 tsf;
2447 struct ath_softc *sc = hw->priv;
2448 struct ath_hal *ah = sc->sc_ah;
f078f209 2449
8feceb67 2450 tsf = ath9k_hw_gettsf64(ah);
f078f209 2451
8feceb67
VT
2452 return tsf;
2453}
f078f209 2454
3b5d665b
AF
2455static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2456{
2457 struct ath_softc *sc = hw->priv;
2458 struct ath_hal *ah = sc->sc_ah;
2459
2460 ath9k_hw_settsf64(ah, tsf);
2461}
2462
8feceb67
VT
2463static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2464{
2465 struct ath_softc *sc = hw->priv;
2466 struct ath_hal *ah = sc->sc_ah;
c83be688 2467
8feceb67
VT
2468 ath9k_hw_reset_tsf(ah);
2469}
f078f209 2470
8feceb67
VT
2471static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2472 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB
2473 struct ieee80211_sta *sta,
2474 u16 tid, u16 *ssn)
8feceb67
VT
2475{
2476 struct ath_softc *sc = hw->priv;
2477 int ret = 0;
f078f209 2478
8feceb67
VT
2479 switch (action) {
2480 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2481 if (!(sc->sc_flags & SC_OP_RXAGGR))
2482 ret = -ENOTSUPP;
8feceb67
VT
2483 break;
2484 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2485 break;
2486 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2487 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT
2488 if (ret < 0)
2489 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2490 "Unable to start TX aggregation\n");
8feceb67 2491 else
17741cdc 2492 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT
2493 break;
2494 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2495 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT
2496 if (ret < 0)
2497 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2498 "Unable to stop TX aggregation\n");
f078f209 2499
17741cdc 2500 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2501 break;
8469cdef
S
2502 case IEEE80211_AMPDU_TX_RESUME:
2503 ath_tx_aggr_resume(sc, sta, tid);
2504 break;
8feceb67 2505 default:
04bd4638 2506 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT
2507 }
2508
2509 return ret;
f078f209
LR
2510}
2511
6baff7f9 2512struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2513 .tx = ath9k_tx,
2514 .start = ath9k_start,
2515 .stop = ath9k_stop,
2516 .add_interface = ath9k_add_interface,
2517 .remove_interface = ath9k_remove_interface,
2518 .config = ath9k_config,
2519 .config_interface = ath9k_config_interface,
2520 .configure_filter = ath9k_configure_filter,
8feceb67
VT
2521 .sta_notify = ath9k_sta_notify,
2522 .conf_tx = ath9k_conf_tx,
8feceb67 2523 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2524 .set_key = ath9k_set_key,
8feceb67 2525 .get_tsf = ath9k_get_tsf,
3b5d665b 2526 .set_tsf = ath9k_set_tsf,
8feceb67 2527 .reset_tsf = ath9k_reset_tsf,
4233df6b 2528 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT
2529};
2530
392dff83
BP
2531static struct {
2532 u32 version;
2533 const char * name;
2534} ath_mac_bb_names[] = {
2535 { AR_SREV_VERSION_5416_PCI, "5416" },
2536 { AR_SREV_VERSION_5416_PCIE, "5418" },
2537 { AR_SREV_VERSION_9100, "9100" },
2538 { AR_SREV_VERSION_9160, "9160" },
2539 { AR_SREV_VERSION_9280, "9280" },
2540 { AR_SREV_VERSION_9285, "9285" }
2541};
2542
2543static struct {
2544 u16 version;
2545 const char * name;
2546} ath_rf_names[] = {
2547 { 0, "5133" },
2548 { AR_RAD5133_SREV_MAJOR, "5133" },
2549 { AR_RAD5122_SREV_MAJOR, "5122" },
2550 { AR_RAD2133_SREV_MAJOR, "2133" },
2551 { AR_RAD2122_SREV_MAJOR, "2122" }
2552};
2553
2554/*
2555 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2556 */
6baff7f9 2557const char *
392dff83
BP
2558ath_mac_bb_name(u32 mac_bb_version)
2559{
2560 int i;
2561
2562 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2563 if (ath_mac_bb_names[i].version == mac_bb_version) {
2564 return ath_mac_bb_names[i].name;
2565 }
2566 }
2567
2568 return "????";
2569}
2570
2571/*
2572 * Return the RF name. "????" is returned if the RF is unknown.
2573 */
6baff7f9 2574const char *
392dff83
BP
2575ath_rf_name(u16 rf_version)
2576{
2577 int i;
2578
2579 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2580 if (ath_rf_names[i].version == rf_version) {
2581 return ath_rf_names[i].name;
2582 }
2583 }
2584
2585 return "????";
2586}
2587
6baff7f9 2588static int __init ath9k_init(void)
f078f209 2589{
ca8a8560
VT
2590 int error;
2591
ca8a8560
VT
2592 /* Register rate control algorithm */
2593 error = ath_rate_control_register();
2594 if (error != 0) {
2595 printk(KERN_ERR
b51bb3cd
LR
2596 "ath9k: Unable to register rate control "
2597 "algorithm: %d\n",
ca8a8560 2598 error);
6baff7f9 2599 goto err_out;
ca8a8560
VT
2600 }
2601
6baff7f9
GJ
2602 error = ath_pci_init();
2603 if (error < 0) {
f078f209 2604 printk(KERN_ERR
b51bb3cd 2605 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ
2606 error = -ENODEV;
2607 goto err_rate_unregister;
f078f209
LR
2608 }
2609
09329d37
GJ
2610 error = ath_ahb_init();
2611 if (error < 0) {
2612 error = -ENODEV;
2613 goto err_pci_exit;
2614 }
2615
f078f209 2616 return 0;
6baff7f9 2617
09329d37
GJ
2618 err_pci_exit:
2619 ath_pci_exit();
2620
6baff7f9
GJ
2621 err_rate_unregister:
2622 ath_rate_control_unregister();
2623 err_out:
2624 return error;
f078f209 2625}
6baff7f9 2626module_init(ath9k_init);
f078f209 2627
6baff7f9 2628static void __exit ath9k_exit(void)
f078f209 2629{
09329d37 2630 ath_ahb_exit();
6baff7f9 2631 ath_pci_exit();
ca8a8560 2632 ath_rate_control_unregister();
04bd4638 2633 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2634}
6baff7f9 2635module_exit(ath9k_exit);
This page took 0.262147 seconds and 5 git commands to generate.