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ath9k: Fill in rate_update mac80211 callback
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
239static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
240{
cbe61d8a 241 struct ath_hw *ah = sc->sc_ah;
ff37e337 242 bool fastcc = true, stopped;
030bb495 243 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
17d7904d 301 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 302 ath9k_ps_restore(sc);
ff37e337
S		 303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
20977d3e
S		 315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 321 u32 cal_interval, short_cal_interval;
ff37e337 322
20977d3e
S		 323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
b77f483f 330 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
20977d3e 331 goto set_timer;
ff37e337
S		 332
333 /* Long calibration runs independently of short calibration. */
17d7904d 334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 335 longcal = true;
04bd4638 336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 337 sc->ani.longcal_timer = timestamp;
ff37e337
S		 338 }
339
17d7904d
S		 340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
20977d3e 342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 343 shortcal = true;
04bd4638 344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 347 }
348 } else {
17d7904d 349 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 350 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 354 }
355 }
356
357 /* Verify whether we must check ANI */
20977d3e 358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 359 aniflag = true;
17d7904d 360 sc->ani.checkani_timer = timestamp;
ff37e337
S		 361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
20977d3e 367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
2660b81a 373 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 374 sc->rx_chainmask, longcal,
ff37e337
S		 375 &iscaldone)) {
376 if (longcal)
17d7904d 377 sc->ani.noise_floor =
ff37e337 378 ath9k_hw_getchan_noise(ah,
2660b81a 379 ah->curchan);
ff37e337
S		 380
381 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 382 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 383 ah->curchan->channel,
384 ah->curchan->channelFlags,
17d7904d 385 sc->ani.noise_floor);
ff37e337
S		 386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 388 "calibrate chan %u/%x failed\n",
2660b81a
S		 389 ah->curchan->channel,
390 ah->curchan->channelFlags);
ff37e337 391 }
17d7904d 392 sc->ani.caldone = iscaldone;
ff37e337
S		 393 }
394 }
395
20977d3e 396set_timer:
ff37e337
S		 397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e 402 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 403 if (sc->sc_ah->config.enable_ani)
aac9207e 404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 405 if (!sc->ani.caldone)
20977d3e 406 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 407
17d7904d 408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337
S		 416 */
417static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 420 if (is_ht ||
2660b81a
S		 421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 424 } else {
17d7904d
S		 425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
ff37e337
S		 427 }
428
04bd4638 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 430 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 458 u32 status = sc->intrstatus;
ff37e337
S		 459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
17d7904d 478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
cbe61d8a 484 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
17d7904d 509 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
17d7904d 518 sc->intrstatus = status;
ff37e337
S		 519
520 if (status & ATH9K_INT_FATAL) {
521 /* need a chip reset */
522 sched = true;
523 } else if (status & ATH9K_INT_RXORN) {
524 /* need a chip reset */
525 sched = true;
526 } else {
527 if (status & ATH9K_INT_SWBA) {
528 /* schedule a tasklet for beacon handling */
529 tasklet_schedule(&sc->bcon_tasklet);
530 }
531 if (status & ATH9K_INT_RXEOL) {
532 /*
533 * NB: the hardware should re-read the link when
534 * RXE bit is written, but it doesn't work
535 * at least on older hardware revs.
536 */
537 sched = true;
538 }
539
540 if (status & ATH9K_INT_TXURN)
541 /* bump tx trigger level */
542 ath9k_hw_updatetxtriglevel(ah, true);
543 /* XXX: optimize this */
544 if (status & ATH9K_INT_RX)
545 sched = true;
546 if (status & ATH9K_INT_TX)
547 sched = true;
548 if (status & ATH9K_INT_BMISS)
549 sched = true;
550 /* carrier sense timeout */
551 if (status & ATH9K_INT_CST)
552 sched = true;
553 if (status & ATH9K_INT_MIB) {
554 /*
555 * Disable interrupts until we service the MIB
556 * interrupt; otherwise it will continue to
557 * fire.
558 */
559 ath9k_hw_set_interrupts(ah, 0);
560 /*
561 * Let the hal handle the event. We assume
562 * it will clear whatever condition caused
563 * the interrupt.
564 */
17d7904d
S		 565 ath9k_hw_procmibevent(ah, &sc->nodestats);
566 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 567 }
568 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 569 if (!(ah->caps.hw_caps &
ff37e337
S		 570 ATH9K_HW_CAP_AUTOSLEEP)) {
571 /* Clear RxAbort bit so that we can
572 * receive frames */
3cbb5dd7 573 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 574 ath9k_hw_setrxabort(ah, 0);
575 sched = true;
3cbb5dd7 576 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 577 }
578 }
4af9cf4f
S		 579 if (status & ATH9K_INT_TSFOOR) {
580 /* FIXME: Handle this interrupt for power save */
581 sched = true;
582 }
ff37e337
S		 583 }
584 } while (0);
585
817e11de
S		 586 ath_debug_stat_interrupt(sc, status);
587
ff37e337
S		 588 if (sched) {
589 /* turn off every interrupt except SWBA */
17d7904d 590 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595}
596
f078f209 597static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 598 struct ieee80211_channel *chan,
094d05dc 599 enum nl80211_channel_type channel_type)
f078f209
LR		 600{
601 u32 chanmode = 0;
f078f209
LR		 602
603 switch (chan->band) {
604 case IEEE80211_BAND_2GHZ:
094d05dc
S		 605 switch(channel_type) {
606 case NL80211_CHAN_NO_HT:
607 case NL80211_CHAN_HT20:
f078f209 608 chanmode = CHANNEL_G_HT20;
094d05dc
S		 609 break;
610 case NL80211_CHAN_HT40PLUS:
f078f209 611 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 612 break;
613 case NL80211_CHAN_HT40MINUS:
f078f209 614 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 615 break;
616 }
f078f209
LR		 617 break;
618 case IEEE80211_BAND_5GHZ:
094d05dc
S		 619 switch(channel_type) {
620 case NL80211_CHAN_NO_HT:
621 case NL80211_CHAN_HT20:
f078f209 622 chanmode = CHANNEL_A_HT20;
094d05dc
S		 623 break;
624 case NL80211_CHAN_HT40PLUS:
f078f209 625 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 626 break;
627 case NL80211_CHAN_HT40MINUS:
f078f209 628 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 629 break;
630 }
f078f209
LR		 631 break;
632 default:
633 break;
634 }
635
636 return chanmode;
637}
638
ff37e337
S		 639static int ath_keyset(struct ath_softc *sc, u16 keyix,
640 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
641{
642 bool status;
643
644 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
e0caf9ea 645 keyix, hk, mac);
ff37e337
S		 646
647 return status != false;
648}
f078f209 649
6ace2891 650static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 651 struct ath9k_keyval *hk, const u8 *addr,
652 bool authenticator)
f078f209 653{
6ace2891
JM		 654 const u8 *key_rxmic;
655 const u8 *key_txmic;
f078f209 656
6ace2891
JM		 657 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
658 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 659
660 if (addr == NULL) {
661 /* Group key installation */
3f53dd64
JM		 662 if (authenticator) {
663 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
664 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
665 } else {
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
668 }
6ace2891 669 return ath_keyset(sc, keyix, hk, addr);
f078f209 670 }
17d7904d 671 if (!sc->splitmic) {
f078f209
LR		 672 /*
673 * data key goes at first index,
674 * the hal handles the MIC keys at index+64.
675 */
676 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
677 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 678 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 679 }
680 /*
681 * TX key goes at first index, RX key at +32.
682 * The hal handles the MIC keys at index+64.
683 */
684 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 685 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 686 /* Txmic entry failed. No need to proceed further */
687 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 688 "Setting TX MIC Key Failed\n");
f078f209
LR		 689 return 0;
690 }
691
692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 /* XXX delete tx key on failure? */
6ace2891
JM		 694 return ath_keyset(sc, keyix + 32, hk, addr);
695}
696
697static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
698{
699 int i;
700
17d7904d
S		 701 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
702 if (test_bit(i, sc->keymap) ||
703 test_bit(i + 64, sc->keymap))
6ace2891 704 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 705 if (sc->splitmic &&
706 (test_bit(i + 32, sc->keymap) ||
707 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 708 continue; /* At least one part of TKIP key allocated */
709
710 /* Found a free slot for a TKIP key */
711 return i;
712 }
713 return -1;
714}
715
716static int ath_reserve_key_cache_slot(struct ath_softc *sc)
717{
718 int i;
719
720 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 721 if (sc->splitmic) {
722 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
723 if (!test_bit(i, sc->keymap) &&
724 (test_bit(i + 32, sc->keymap) ||
725 test_bit(i + 64, sc->keymap) ||
726 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 727 return i;
17d7904d
S		 728 if (!test_bit(i + 32, sc->keymap) &&
729 (test_bit(i, sc->keymap) ||
730 test_bit(i + 64, sc->keymap) ||
731 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 732 return i + 32;
17d7904d
S		 733 if (!test_bit(i + 64, sc->keymap) &&
734 (test_bit(i , sc->keymap) ||
735 test_bit(i + 32, sc->keymap) ||
736 test_bit(i + 64 + 32, sc->keymap)))
ea612132 737 return i + 64;
17d7904d
S		 738 if (!test_bit(i + 64 + 32, sc->keymap) &&
739 (test_bit(i, sc->keymap) ||
740 test_bit(i + 32, sc->keymap) ||
741 test_bit(i + 64, sc->keymap)))
ea612132 742 return i + 64 + 32;
6ace2891
JM		 743 }
744 } else {
17d7904d
S		 745 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
746 if (!test_bit(i, sc->keymap) &&
747 test_bit(i + 64, sc->keymap))
6ace2891 748 return i;
17d7904d
S		 749 if (test_bit(i, sc->keymap) &&
750 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 751 return i + 64;
752 }
753 }
754
755 /* No partially used TKIP slots, pick any available slot */
17d7904d 756 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 757 /* Do not allow slots that could be needed for TKIP group keys
758 * to be used. This limitation could be removed if we know that
759 * TKIP will not be used. */
760 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
761 continue;
17d7904d 762 if (sc->splitmic) {
be2864cf
JM		 763 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
764 continue;
765 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
766 continue;
767 }
768
17d7904d 769 if (!test_bit(i, sc->keymap))
6ace2891
JM		 770 return i; /* Found a free slot for a key */
771 }
772
773 /* No free slot found */
774 return -1;
f078f209
LR		 775}
776
777static int ath_key_config(struct ath_softc *sc,
3f53dd64 778 struct ieee80211_vif *vif,
dc822b5d 779 struct ieee80211_sta *sta,
f078f209
LR		 780 struct ieee80211_key_conf *key)
781{
f078f209
LR		 782 struct ath9k_keyval hk;
783 const u8 *mac = NULL;
784 int ret = 0;
6ace2891 785 int idx;
f078f209
LR		 786
787 memset(&hk, 0, sizeof(hk));
788
789 switch (key->alg) {
790 case ALG_WEP:
791 hk.kv_type = ATH9K_CIPHER_WEP;
792 break;
793 case ALG_TKIP:
794 hk.kv_type = ATH9K_CIPHER_TKIP;
795 break;
796 case ALG_CCMP:
797 hk.kv_type = ATH9K_CIPHER_AES_CCM;
798 break;
799 default:
ca470b29 800 return -EOPNOTSUPP;
f078f209
LR		 801 }
802
6ace2891 803 hk.kv_len = key->keylen;
f078f209
LR		 804 memcpy(hk.kv_val, key->key, key->keylen);
805
6ace2891
JM		 806 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
807 /* For now, use the default keys for broadcast keys. This may
808 * need to change with virtual interfaces. */
809 idx = key->keyidx;
810 } else if (key->keyidx) {
811 struct ieee80211_vif *vif;
f078f209 812
dc822b5d
JB		 813 if (WARN_ON(!sta))
814 return -EOPNOTSUPP;
815 mac = sta->addr;
816
17d7904d 817 vif = sc->vifs[0];
6ace2891
JM		 818 if (vif->type != NL80211_IFTYPE_AP) {
819 /* Only keyidx 0 should be used with unicast key, but
820 * allow this for client mode for now. */
821 idx = key->keyidx;
822 } else
823 return -EIO;
f078f209 824 } else {
dc822b5d
JB		 825 if (WARN_ON(!sta))
826 return -EOPNOTSUPP;
827 mac = sta->addr;
828
6ace2891
JM		 829 if (key->alg == ALG_TKIP)
830 idx = ath_reserve_key_cache_slot_tkip(sc);
831 else
832 idx = ath_reserve_key_cache_slot(sc);
833 if (idx < 0)
ca470b29 834 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 835 }
836
837 if (key->alg == ALG_TKIP)
3f53dd64
JM		 838 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
839 vif->type == NL80211_IFTYPE_AP);
f078f209 840 else
6ace2891 841 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 842
843 if (!ret)
844 return -EIO;
845
17d7904d 846 set_bit(idx, sc->keymap);
6ace2891 847 if (key->alg == ALG_TKIP) {
17d7904d
S		 848 set_bit(idx + 64, sc->keymap);
849 if (sc->splitmic) {
850 set_bit(idx + 32, sc->keymap);
851 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 852 }
853 }
854
855 return idx;
f078f209
LR		 856}
857
858static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
859{
6ace2891
JM		 860 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
861 if (key->hw_key_idx < IEEE80211_WEP_NKID)
862 return;
863
17d7904d 864 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 865 if (key->alg != ALG_TKIP)
866 return;
f078f209 867
17d7904d
S		 868 clear_bit(key->hw_key_idx + 64, sc->keymap);
869 if (sc->splitmic) {
870 clear_bit(key->hw_key_idx + 32, sc->keymap);
871 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 872 }
f078f209
LR		 873}
874
eb2599ca
S		 875static void setup_ht_cap(struct ath_softc *sc,
876 struct ieee80211_sta_ht_cap *ht_info)
f078f209 877{
60653678
S		 878#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
879#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 880
d9fe60de
JB		 881 ht_info->ht_supported = true;
882 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
883 IEEE80211_HT_CAP_SM_PS |
884 IEEE80211_HT_CAP_SGI_40 |
885 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 886
60653678
S		 887 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
888 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 889
d9fe60de
JB		 890 /* set up supported mcs set */
891 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 892
17d7904d 893 switch(sc->rx_chainmask) {
eb2599ca
S		 894 case 1:
895 ht_info->mcs.rx_mask[0] = 0xff;
896 break;
3c457265 897 case 3:
eb2599ca
S		 898 case 5:
899 case 7:
900 default:
901 ht_info->mcs.rx_mask[0] = 0xff;
902 ht_info->mcs.rx_mask[1] = 0xff;
903 break;
904 }
905
d9fe60de 906 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 907}
908
8feceb67 909static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 910 struct ieee80211_vif *vif,
8feceb67 911 struct ieee80211_bss_conf *bss_conf)
f078f209 912{
17d7904d 913 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 914
8feceb67 915 if (bss_conf->assoc) {
094d05dc 916 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 917 bss_conf->aid, sc->curbssid);
f078f209 918
8feceb67 919 /* New association, store aid */
d97809db 920 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 921 sc->curaid = bss_conf->aid;
ba52da58 922 ath9k_hw_write_associd(sc);
8feceb67 923 }
f078f209 924
8feceb67
VT		 925 /* Configure the beacon */
926 ath_beacon_config(sc, 0);
927 sc->sc_flags |= SC_OP_BEACONS;
f078f209 928
8feceb67 929 /* Reset rssi stats */
17d7904d
S		 930 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
931 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
932 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
933 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 934
6f255425 935 /* Start ANI */
17d7904d 936 mod_timer(&sc->ani.timer,
20977d3e 937 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 938 } else {
04bd4638 939 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 940 sc->curaid = 0;
f078f209 941 }
8feceb67 942}
f078f209 943
8feceb67
VT		 944/********************************/
945/* LED functions */
946/********************************/
f078f209 947
f2bffa7e
VT		 948static void ath_led_blink_work(struct work_struct *work)
949{
950 struct ath_softc *sc = container_of(work, struct ath_softc,
951 ath_led_blink_work.work);
952
953 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
954 return;
955 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
956 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
957
958 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
959 (sc->sc_flags & SC_OP_LED_ON) ?
960 msecs_to_jiffies(sc->led_off_duration) :
961 msecs_to_jiffies(sc->led_on_duration));
962
963 sc->led_on_duration =
964 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
965 sc->led_off_duration =
966 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
967 sc->led_on_cnt = sc->led_off_cnt = 0;
968 if (sc->sc_flags & SC_OP_LED_ON)
969 sc->sc_flags &= ~SC_OP_LED_ON;
970 else
971 sc->sc_flags |= SC_OP_LED_ON;
972}
973
8feceb67
VT		 974static void ath_led_brightness(struct led_classdev *led_cdev,
975 enum led_brightness brightness)
976{
977 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
978 struct ath_softc *sc = led->sc;
f078f209 979
8feceb67
VT		 980 switch (brightness) {
981 case LED_OFF:
982 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 983 led->led_type == ATH_LED_RADIO) {
984 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
985 (led->led_type == ATH_LED_RADIO));
8feceb67 986 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 987 if (led->led_type == ATH_LED_RADIO)
988 sc->sc_flags &= ~SC_OP_LED_ON;
989 } else {
990 sc->led_off_cnt++;
991 }
8feceb67
VT		 992 break;
993 case LED_FULL:
f2bffa7e 994 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 995 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 996 queue_delayed_work(sc->hw->workqueue,
997 &sc->ath_led_blink_work, 0);
998 } else if (led->led_type == ATH_LED_RADIO) {
999 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1000 sc->sc_flags |= SC_OP_LED_ON;
1001 } else {
1002 sc->led_on_cnt++;
1003 }
8feceb67
VT		 1004 break;
1005 default:
1006 break;
f078f209 1007 }
8feceb67 1008}
f078f209 1009
8feceb67
VT		 1010static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1011 char *trigger)
1012{
1013 int ret;
f078f209 1014
8feceb67
VT		 1015 led->sc = sc;
1016 led->led_cdev.name = led->name;
1017 led->led_cdev.default_trigger = trigger;
1018 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1019
8feceb67
VT		 1020 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1021 if (ret)
1022 DPRINTF(sc, ATH_DBG_FATAL,
1023 "Failed to register led:%s", led->name);
1024 else
1025 led->registered = 1;
1026 return ret;
1027}
f078f209 1028
8feceb67
VT		 1029static void ath_unregister_led(struct ath_led *led)
1030{
1031 if (led->registered) {
1032 led_classdev_unregister(&led->led_cdev);
1033 led->registered = 0;
f078f209 1034 }
f078f209
LR		 1035}
1036
8feceb67 1037static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1038{
f2bffa7e 1039 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1040 ath_unregister_led(&sc->assoc_led);
1041 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1042 ath_unregister_led(&sc->tx_led);
1043 ath_unregister_led(&sc->rx_led);
1044 ath_unregister_led(&sc->radio_led);
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046}
f078f209 1047
8feceb67
VT		 1048static void ath_init_leds(struct ath_softc *sc)
1049{
1050 char *trigger;
1051 int ret;
f078f209 1052
8feceb67
VT		 1053 /* Configure gpio 1 for output */
1054 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1055 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1056 /* LED off, active low */
1057 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1058
f2bffa7e
VT		 1059 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1060
8feceb67
VT		 1061 trigger = ieee80211_get_radio_led_name(sc->hw);
1062 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1063 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1064 ret = ath_register_led(sc, &sc->radio_led, trigger);
1065 sc->radio_led.led_type = ATH_LED_RADIO;
1066 if (ret)
1067 goto fail;
7dcfdcd9 1068
8feceb67
VT		 1069 trigger = ieee80211_get_assoc_led_name(sc->hw);
1070 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1071 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1072 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1073 sc->assoc_led.led_type = ATH_LED_ASSOC;
1074 if (ret)
1075 goto fail;
f078f209 1076
8feceb67
VT		 1077 trigger = ieee80211_get_tx_led_name(sc->hw);
1078 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1079 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1080 ret = ath_register_led(sc, &sc->tx_led, trigger);
1081 sc->tx_led.led_type = ATH_LED_TX;
1082 if (ret)
1083 goto fail;
f078f209 1084
8feceb67
VT		 1085 trigger = ieee80211_get_rx_led_name(sc->hw);
1086 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1087 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1088 ret = ath_register_led(sc, &sc->rx_led, trigger);
1089 sc->rx_led.led_type = ATH_LED_RX;
1090 if (ret)
1091 goto fail;
f078f209 1092
8feceb67
VT		 1093 return;
1094
1095fail:
1096 ath_deinit_leds(sc);
f078f209
LR		 1097}
1098
e97275cb 1099#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1100
500c064d
VT		 1101/*******************/
1102/* Rfkill */
1103/*******************/
1104
1105static void ath_radio_enable(struct ath_softc *sc)
1106{
cbe61d8a 1107 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1108 struct ieee80211_channel *channel = sc->hw->conf.channel;
1109 int r;
500c064d 1110
3cbb5dd7 1111 ath9k_ps_wakeup(sc);
500c064d 1112 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1113
2660b81a 1114 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1115
1116 if (r) {
500c064d 1117 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1118 "Unable to reset channel %u (%uMhz) ",
1119 "reset status %u\n",
1120 channel->center_freq, r);
500c064d
VT		 1121 }
1122 spin_unlock_bh(&sc->sc_resetlock);
1123
1124 ath_update_txpow(sc);
1125 if (ath_startrecv(sc) != 0) {
1126 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1127 "Unable to restart recv logic\n");
500c064d
VT		 1128 return;
1129 }
1130
1131 if (sc->sc_flags & SC_OP_BEACONS)
1132 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1133
1134 /* Re-Enable interrupts */
17d7904d 1135 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1136
1137 /* Enable LED */
1138 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1139 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1140 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1141
1142 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1143 ath9k_ps_restore(sc);
500c064d
VT		 1144}
1145
1146static void ath_radio_disable(struct ath_softc *sc)
1147{
cbe61d8a 1148 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1149 struct ieee80211_channel *channel = sc->hw->conf.channel;
1150 int r;
500c064d 1151
3cbb5dd7 1152 ath9k_ps_wakeup(sc);
500c064d
VT		 1153 ieee80211_stop_queues(sc->hw);
1154
1155 /* Disable LED */
1156 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1157 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1158
1159 /* Disable interrupts */
1160 ath9k_hw_set_interrupts(ah, 0);
1161
043a0405 1162 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1163 ath_stoprecv(sc); /* turn off frame recv */
1164 ath_flushrecv(sc); /* flush recv queue */
1165
1166 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1167 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1168 if (r) {
500c064d 1169 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1170 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1171 "reset status %u\n",
1172 channel->center_freq, r);
500c064d
VT		 1173 }
1174 spin_unlock_bh(&sc->sc_resetlock);
1175
1176 ath9k_hw_phy_disable(ah);
1177 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1178 ath9k_ps_restore(sc);
500c064d
VT		 1179}
1180
1181static bool ath_is_rfkill_set(struct ath_softc *sc)
1182{
cbe61d8a 1183 struct ath_hw *ah = sc->sc_ah;
500c064d 1184
2660b81a
S		 1185 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1186 ah->rfkill_polarity;
500c064d
VT		 1187}
1188
1189/* h/w rfkill poll function */
1190static void ath_rfkill_poll(struct work_struct *work)
1191{
1192 struct ath_softc *sc = container_of(work, struct ath_softc,
1193 rf_kill.rfkill_poll.work);
1194 bool radio_on;
1195
1196 if (sc->sc_flags & SC_OP_INVALID)
1197 return;
1198
1199 radio_on = !ath_is_rfkill_set(sc);
1200
1201 /*
1202 * enable/disable radio only when there is a
1203 * state change in RF switch
1204 */
1205 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1206 enum rfkill_state state;
1207
1208 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1209 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1210 : RFKILL_STATE_HARD_BLOCKED;
1211 } else if (radio_on) {
1212 ath_radio_enable(sc);
1213 state = RFKILL_STATE_UNBLOCKED;
1214 } else {
1215 ath_radio_disable(sc);
1216 state = RFKILL_STATE_HARD_BLOCKED;
1217 }
1218
1219 if (state == RFKILL_STATE_HARD_BLOCKED)
1220 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1221 else
1222 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1223
1224 rfkill_force_state(sc->rf_kill.rfkill, state);
1225 }
1226
1227 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1228 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1229}
1230
1231/* s/w rfkill handler */
1232static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1233{
1234 struct ath_softc *sc = data;
1235
1236 switch (state) {
1237 case RFKILL_STATE_SOFT_BLOCKED:
1238 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1239 SC_OP_RFKILL_SW_BLOCKED)))
1240 ath_radio_disable(sc);
1241 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1242 return 0;
1243 case RFKILL_STATE_UNBLOCKED:
1244 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1245 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1246 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1247 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1248 "radio as it is disabled by h/w\n");
500c064d
VT		 1249 return -EPERM;
1250 }
1251 ath_radio_enable(sc);
1252 }
1253 return 0;
1254 default:
1255 return -EINVAL;
1256 }
1257}
1258
1259/* Init s/w rfkill */
1260static int ath_init_sw_rfkill(struct ath_softc *sc)
1261{
1262 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1263 RFKILL_TYPE_WLAN);
1264 if (!sc->rf_kill.rfkill) {
1265 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1266 return -ENOMEM;
1267 }
1268
1269 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1270 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1271 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1272 sc->rf_kill.rfkill->data = sc;
1273 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1274 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1275 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1276
1277 return 0;
1278}
1279
1280/* Deinitialize rfkill */
1281static void ath_deinit_rfkill(struct ath_softc *sc)
1282{
2660b81a 1283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1284 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1285
1286 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1287 rfkill_unregister(sc->rf_kill.rfkill);
1288 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1289 sc->rf_kill.rfkill = NULL;
1290 }
1291}
9c84b797
S		 1292
1293static int ath_start_rfkill_poll(struct ath_softc *sc)
1294{
2660b81a 1295 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1296 queue_delayed_work(sc->hw->workqueue,
1297 &sc->rf_kill.rfkill_poll, 0);
1298
1299 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1300 if (rfkill_register(sc->rf_kill.rfkill)) {
1301 DPRINTF(sc, ATH_DBG_FATAL,
1302 "Unable to register rfkill\n");
1303 rfkill_free(sc->rf_kill.rfkill);
1304
1305 /* Deinitialize the device */
39c3c2f2 1306 ath_cleanup(sc);
9c84b797
S		 1307 return -EIO;
1308 } else {
1309 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1310 }
1311 }
1312
1313 return 0;
1314}
500c064d
VT		 1315#endif /* CONFIG_RFKILL */
1316
6baff7f9 1317void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1318{
1319 ath_detach(sc);
1320 free_irq(sc->irq, sc);
1321 ath_bus_cleanup(sc);
1322 ieee80211_free_hw(sc->hw);
1323}
1324
6baff7f9 1325void ath_detach(struct ath_softc *sc)
f078f209 1326{
8feceb67 1327 struct ieee80211_hw *hw = sc->hw;
9c84b797 1328 int i = 0;
f078f209 1329
3cbb5dd7
VN		 1330 ath9k_ps_wakeup(sc);
1331
04bd4638 1332 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1333
e97275cb 1334#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1335 ath_deinit_rfkill(sc);
1336#endif
3fcdfb4b
VT		 1337 ath_deinit_leds(sc);
1338
1339 ieee80211_unregister_hw(hw);
8feceb67
VT		 1340 ath_rx_cleanup(sc);
1341 ath_tx_cleanup(sc);
f078f209 1342
9c84b797
S		 1343 tasklet_kill(&sc->intr_tq);
1344 tasklet_kill(&sc->bcon_tasklet);
f078f209 1345
9c84b797
S		 1346 if (!(sc->sc_flags & SC_OP_INVALID))
1347 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1348
9c84b797
S		 1349 /* cleanup tx queues */
1350 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1351 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1352 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1353
1354 ath9k_hw_detach(sc->sc_ah);
826d2680 1355 ath9k_exit_debug(sc);
3cbb5dd7 1356 ath9k_ps_restore(sc);
f078f209
LR		 1357}
1358
ff37e337
S		 1359static int ath_init(u16 devid, struct ath_softc *sc)
1360{
cbe61d8a 1361 struct ath_hw *ah = NULL;
ff37e337
S		 1362 int status;
1363 int error = 0, i;
1364 int csz = 0;
1365
1366 /* XXX: hardware will not be ready until ath_open() being called */
1367 sc->sc_flags |= SC_OP_INVALID;
88b126af 1368
826d2680
S		 1369 if (ath9k_init_debug(sc) < 0)
1370 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1371
1372 spin_lock_init(&sc->sc_resetlock);
aa33de09 1373 mutex_init(&sc->mutex);
ff37e337
S		 1374 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1375 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1376 (unsigned long)sc);
1377
1378 /*
1379 * Cache line size is used to size and align various
1380 * structures used to communicate with the hardware.
1381 */
88d15707 1382 ath_read_cachesize(sc, &csz);
ff37e337 1383 /* XXX assert csz is non-zero */
17d7904d 1384 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1385
cbe61d8a 1386 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1387 if (ah == NULL) {
1388 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1389 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1390 error = -ENXIO;
1391 goto bad;
1392 }
1393 sc->sc_ah = ah;
1394
1395 /* Get the hardware key cache size. */
2660b81a 1396 sc->keymax = ah->caps.keycache_size;
17d7904d 1397 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1398 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1399 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1400 ATH_KEYMAX, sc->keymax);
1401 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1402 }
1403
1404 /*
1405 * Reset the key cache since some parts do not
1406 * reset the contents on initial power up.
1407 */
17d7904d 1408 for (i = 0; i < sc->keymax; i++)
ff37e337 1409 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1410
5f8e077c 1411 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1412 goto bad;
1413
1414 /* default to MONITOR mode */
2660b81a 1415 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1416
ff37e337
S		 1417 /* Setup rate tables */
1418
1419 ath_rate_attach(sc);
1420 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1421 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1422
1423 /*
1424 * Allocate hardware transmit queues: one queue for
1425 * beacon frames and one data queue for each QoS
1426 * priority. Note that the hal handles reseting
1427 * these queues at the needed time.
1428 */
b77f483f
S		 1429 sc->beacon.beaconq = ath_beaconq_setup(ah);
1430 if (sc->beacon.beaconq == -1) {
ff37e337 1431 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1432 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1433 error = -EIO;
1434 goto bad2;
1435 }
b77f483f
S		 1436 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1437 if (sc->beacon.cabq == NULL) {
ff37e337 1438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1439 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1440 error = -EIO;
1441 goto bad2;
1442 }
1443
17d7904d 1444 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1445 ath_cabq_update(sc);
1446
b77f483f
S		 1447 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1448 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1449
1450 /* Setup data queues */
1451 /* NB: ensure BK queue is the lowest priority h/w queue */
1452 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1453 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1454 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1455 error = -EIO;
1456 goto bad2;
1457 }
1458
1459 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1460 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1461 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1462 error = -EIO;
1463 goto bad2;
1464 }
1465 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1466 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1467 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1468 error = -EIO;
1469 goto bad2;
1470 }
1471 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1472 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1473 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1474 error = -EIO;
1475 goto bad2;
1476 }
1477
1478 /* Initializes the noise floor to a reasonable default value.
1479 * Later on this will be updated during ANI processing. */
1480
17d7904d
S		 1481 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1482 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1483
1484 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1485 ATH9K_CIPHER_TKIP, NULL)) {
1486 /*
1487 * Whether we should enable h/w TKIP MIC.
1488 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1489 * report WMM capable, so it's always safe to turn on
1490 * TKIP MIC in this case.
1491 */
1492 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1493 0, 1, NULL);
1494 }
1495
1496 /*
1497 * Check whether the separate key cache entries
1498 * are required to handle both tx+rx MIC keys.
1499 * With split mic keys the number of stations is limited
1500 * to 27 otherwise 59.
1501 */
1502 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1503 ATH9K_CIPHER_TKIP, NULL)
1504 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1505 ATH9K_CIPHER_MIC, NULL)
1506 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1507 0, NULL))
17d7904d 1508 sc->splitmic = 1;
ff37e337
S		 1509
1510 /* turn on mcast key search if possible */
1511 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1512 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1513 1, NULL);
1514
17d7904d 1515 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1516
1517 /* 11n Capabilities */
2660b81a 1518 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1519 sc->sc_flags |= SC_OP_TXAGGR;
1520 sc->sc_flags |= SC_OP_RXAGGR;
1521 }
1522
2660b81a
S		 1523 sc->tx_chainmask = ah->caps.tx_chainmask;
1524 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1525
1526 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1527 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1528
2660b81a 1529 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
ba52da58 1530 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
17d7904d 1531 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
ba52da58 1532 ath9k_hw_setbssidmask(sc);
ff37e337
S		 1533 }
1534
b77f483f 1535 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1536
1537 /* initialize beacon slots */
b77f483f
S		 1538 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1539 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1540
1541 /* save MISC configurations */
17d7904d 1542 sc->config.swBeaconProcess = 1;
ff37e337 1543
ff37e337
S		 1544 /* setup channels and rates */
1545
5f8e077c 1546 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1547 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1548 sc->rates[IEEE80211_BAND_2GHZ];
1549 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1550 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1551 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1552
2660b81a 1553 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1554 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1555 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1556 sc->rates[IEEE80211_BAND_5GHZ];
1557 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1558 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1559 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1560 }
1561
2660b81a 1562 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1563 ath9k_hw_btcoex_enable(sc->sc_ah);
1564
ff37e337
S		 1565 return 0;
1566bad2:
1567 /* cleanup tx queues */
1568 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1569 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1570 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1571bad:
1572 if (ah)
1573 ath9k_hw_detach(ah);
40b130a9 1574 ath9k_exit_debug(sc);
ff37e337
S		 1575
1576 return error;
1577}
1578
6baff7f9 1579int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1580{
8feceb67 1581 struct ieee80211_hw *hw = sc->hw;
191a99b7 1582 const struct ieee80211_regdomain *regd;
40b130a9 1583 int error = 0, i;
f078f209 1584
04bd4638 1585 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1586
8feceb67
VT		 1587 error = ath_init(devid, sc);
1588 if (error != 0)
1589 return error;
f078f209 1590
8feceb67 1591 /* get mac address from hardware and set in mac80211 */
f078f209 1592
ba52da58 1593 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
f078f209 1594
9c84b797
S		 1595 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1596 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1597 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1598 IEEE80211_HW_AMPDU_AGGREGATION |
1599 IEEE80211_HW_SUPPORTS_PS |
1600 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1601
b3bd89ce 1602 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1603 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1604
9c84b797
S		 1605 hw->wiphy->interface_modes =
1606 BIT(NL80211_IFTYPE_AP) |
1607 BIT(NL80211_IFTYPE_STATION) |
1608 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1609
5f8e077c
LR		 1610 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1611 hw->wiphy->strict_regulatory = true;
1612
8feceb67 1613 hw->queues = 4;
e63835b0 1614 hw->max_rates = 4;
171387ef 1615 hw->channel_change_time = 5000;
e63835b0 1616 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1617 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1618 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1619
8feceb67 1620 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1621
2660b81a 1622 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1623 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1624 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1625 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1626 }
1627
1628 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
2660b81a 1629 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
9c84b797
S		 1630 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1631 &sc->sbands[IEEE80211_BAND_5GHZ];
1632
db93e7b5
SB		 1633 /* initialize tx/rx engine */
1634 error = ath_tx_init(sc, ATH_TXBUF);
1635 if (error != 0)
40b130a9 1636 goto error_attach;
8feceb67 1637
db93e7b5
SB		 1638 error = ath_rx_init(sc, ATH_RXBUF);
1639 if (error != 0)
40b130a9 1640 goto error_attach;
8feceb67 1641
e97275cb 1642#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1643 /* Initialze h/w Rfkill */
2660b81a 1644 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1645 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1646
1647 /* Initialize s/w rfkill */
40b130a9
VT		 1648 error = ath_init_sw_rfkill(sc);
1649 if (error)
1650 goto error_attach;
500c064d
VT		 1651#endif
1652
5f8e077c 1653 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1654 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1655 * saved on the wiphy orig_* parameters */
191a99b7 1656 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1657 hw->wiphy->custom_regulatory = true;
1658 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1659 } else {
1660 /* This gets applied in the case of the absense of CRDA,
191a99b7 1661 * it's our own custom world regulatory domain, similar to
5f8e077c 1662 * cfg80211's but we enable passive scanning */
191a99b7 1663 regd = ath9k_default_world_regdomain();
5f8e077c 1664 }
191a99b7
BC		 1665 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1666 ath9k_reg_apply_radar_flags(hw->wiphy);
1667 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
5f8e077c 1668
db93e7b5 1669 error = ieee80211_register_hw(hw);
8feceb67 1670
fe33eb39
LR		 1671 if (!ath9k_is_world_regd(sc->sc_ah)) {
1672 error = regulatory_hint(hw->wiphy,
1673 sc->sc_ah->regulatory.alpha2);
1674 if (error)
1675 goto error_attach;
1676 }
5f8e077c 1677
db93e7b5
SB		 1678 /* Initialize LED control */
1679 ath_init_leds(sc);
8feceb67 1680
5f8e077c 1681
8feceb67 1682 return 0;
40b130a9
VT		 1683
1684error_attach:
1685 /* cleanup tx queues */
1686 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1687 if (ATH_TXQ_SETUP(sc, i))
1688 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1689
1690 ath9k_hw_detach(sc->sc_ah);
1691 ath9k_exit_debug(sc);
1692
8feceb67 1693 return error;
f078f209
LR		 1694}
1695
ff37e337
S		 1696int ath_reset(struct ath_softc *sc, bool retry_tx)
1697{
cbe61d8a 1698 struct ath_hw *ah = sc->sc_ah;
030bb495 1699 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1700 int r;
ff37e337
S		 1701
1702 ath9k_hw_set_interrupts(ah, 0);
043a0405 1703 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1704 ath_stoprecv(sc);
1705 ath_flushrecv(sc);
1706
1707 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1708 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1709 if (r)
ff37e337 1710 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1711 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1712 spin_unlock_bh(&sc->sc_resetlock);
1713
1714 if (ath_startrecv(sc) != 0)
04bd4638 1715 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1716
1717 /*
1718 * We may be doing a reset in response to a request
1719 * that changes the channel so update any state that
1720 * might change as a result.
1721 */
ce111bad 1722 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1723
1724 ath_update_txpow(sc);
1725
1726 if (sc->sc_flags & SC_OP_BEACONS)
1727 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1728
17d7904d 1729 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1730
1731 if (retry_tx) {
1732 int i;
1733 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1734 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1735 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1736 ath_txq_schedule(sc, &sc->tx.txq[i]);
1737 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1738 }
1739 }
1740 }
1741
ae8d2858 1742 return r;
ff37e337
S		 1743}
1744
1745/*
1746 * This function will allocate both the DMA descriptor structure, and the
1747 * buffers it contains. These are used to contain the descriptors used
1748 * by the system.
1749*/
1750int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1751 struct list_head *head, const char *name,
1752 int nbuf, int ndesc)
1753{
1754#define DS2PHYS(_dd, _ds) \
1755 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1756#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1757#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1758
1759 struct ath_desc *ds;
1760 struct ath_buf *bf;
1761 int i, bsize, error;
1762
04bd4638
S		 1763 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1764 name, nbuf, ndesc);
ff37e337
S		 1765
1766 /* ath_desc must be a multiple of DWORDs */
1767 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1768 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1769 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1770 error = -ENOMEM;
1771 goto fail;
1772 }
1773
1774 dd->dd_name = name;
1775 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1776
1777 /*
1778 * Need additional DMA memory because we can't use
1779 * descriptors that cross the 4K page boundary. Assume
1780 * one skipped descriptor per 4K page.
1781 */
2660b81a 1782 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1783 u32 ndesc_skipped =
1784 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1785 u32 dma_len;
1786
1787 while (ndesc_skipped) {
1788 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1789 dd->dd_desc_len += dma_len;
1790
1791 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1792 };
1793 }
1794
1795 /* allocate descriptors */
7da3c55c
GJ		 1796 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1797 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1798 if (dd->dd_desc == NULL) {
1799 error = -ENOMEM;
1800 goto fail;
1801 }
1802 ds = dd->dd_desc;
04bd4638
S		 1803 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1804 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1805 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1806
1807 /* allocate buffers */
1808 bsize = sizeof(struct ath_buf) * nbuf;
1809 bf = kmalloc(bsize, GFP_KERNEL);
1810 if (bf == NULL) {
1811 error = -ENOMEM;
1812 goto fail2;
1813 }
1814 memset(bf, 0, bsize);
1815 dd->dd_bufptr = bf;
1816
1817 INIT_LIST_HEAD(head);
1818 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1819 bf->bf_desc = ds;
1820 bf->bf_daddr = DS2PHYS(dd, ds);
1821
2660b81a 1822 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1823 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1824 /*
1825 * Skip descriptor addresses which can cause 4KB
1826 * boundary crossing (addr + length) with a 32 dword
1827 * descriptor fetch.
1828 */
1829 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1830 ASSERT((caddr_t) bf->bf_desc <
1831 ((caddr_t) dd->dd_desc +
1832 dd->dd_desc_len));
1833
1834 ds += ndesc;
1835 bf->bf_desc = ds;
1836 bf->bf_daddr = DS2PHYS(dd, ds);
1837 }
1838 }
1839 list_add_tail(&bf->list, head);
1840 }
1841 return 0;
1842fail2:
7da3c55c
GJ		 1843 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1844 dd->dd_desc_paddr);
ff37e337
S		 1845fail:
1846 memset(dd, 0, sizeof(*dd));
1847 return error;
1848#undef ATH_DESC_4KB_BOUND_CHECK
1849#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1850#undef DS2PHYS
1851}
1852
1853void ath_descdma_cleanup(struct ath_softc *sc,
1854 struct ath_descdma *dd,
1855 struct list_head *head)
1856{
7da3c55c
GJ		 1857 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1858 dd->dd_desc_paddr);
ff37e337
S		 1859
1860 INIT_LIST_HEAD(head);
1861 kfree(dd->dd_bufptr);
1862 memset(dd, 0, sizeof(*dd));
1863}
1864
1865int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1866{
1867 int qnum;
1868
1869 switch (queue) {
1870 case 0:
b77f483f 1871 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1872 break;
1873 case 1:
b77f483f 1874 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1875 break;
1876 case 2:
b77f483f 1877 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1878 break;
1879 case 3:
b77f483f 1880 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1881 break;
1882 default:
b77f483f 1883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1884 break;
1885 }
1886
1887 return qnum;
1888}
1889
1890int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1891{
1892 int qnum;
1893
1894 switch (queue) {
1895 case ATH9K_WME_AC_VO:
1896 qnum = 0;
1897 break;
1898 case ATH9K_WME_AC_VI:
1899 qnum = 1;
1900 break;
1901 case ATH9K_WME_AC_BE:
1902 qnum = 2;
1903 break;
1904 case ATH9K_WME_AC_BK:
1905 qnum = 3;
1906 break;
1907 default:
1908 qnum = -1;
1909 break;
1910 }
1911
1912 return qnum;
1913}
1914
5f8e077c
LR		 1915/* XXX: Remove me once we don't depend on ath9k_channel for all
1916 * this redundant data */
1917static void ath9k_update_ichannel(struct ath_softc *sc,
1918 struct ath9k_channel *ichan)
1919{
1920 struct ieee80211_hw *hw = sc->hw;
1921 struct ieee80211_channel *chan = hw->conf.channel;
1922 struct ieee80211_conf *conf = &hw->conf;
1923
1924 ichan->channel = chan->center_freq;
1925 ichan->chan = chan;
1926
1927 if (chan->band == IEEE80211_BAND_2GHZ) {
1928 ichan->chanmode = CHANNEL_G;
1929 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1930 } else {
1931 ichan->chanmode = CHANNEL_A;
1932 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1933 }
1934
1935 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1936
1937 if (conf_is_ht(conf)) {
1938 if (conf_is_ht40(conf))
1939 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1940
1941 ichan->chanmode = ath_get_extchanmode(sc, chan,
1942 conf->channel_type);
1943 }
1944}
1945
ff37e337
S		 1946/**********************/
1947/* mac80211 callbacks */
1948/**********************/
1949
8feceb67 1950static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1951{
1952 struct ath_softc *sc = hw->priv;
8feceb67 1953 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1954 struct ath9k_channel *init_channel;
ae8d2858 1955 int r, pos;
f078f209 1956
04bd4638
S		 1957 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1958 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1959
141b38b6
S		 1960 mutex_lock(&sc->mutex);
1961
8feceb67 1962 /* setup initial channel */
f078f209 1963
5f8e077c 1964 pos = curchan->hw_value;
f078f209 1965
2660b81a 1966 init_channel = &sc->sc_ah->channels[pos];
5f8e077c 1967 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1968
1969 /* Reset SERDES registers */
1970 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1971
1972 /*
1973 * The basic interface to setting the hardware in a good
1974 * state is ``reset''. On return the hardware is known to
1975 * be powered up and with interrupts disabled. This must
1976 * be followed by initialization of the appropriate bits
1977 * and then setup of the interrupt mask.
1978 */
1979 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1980 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1981 if (r) {
ff37e337 1982 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1983 "Unable to reset hardware; reset status %u "
1984 "(freq %u MHz)\n", r,
1985 curchan->center_freq);
ff37e337 1986 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1987 goto mutex_unlock;
ff37e337
S		 1988 }
1989 spin_unlock_bh(&sc->sc_resetlock);
1990
1991 /*
1992 * This is needed only to setup initial state
1993 * but it's best done after a reset.
1994 */
1995 ath_update_txpow(sc);
8feceb67 1996
ff37e337
S		 1997 /*
1998 * Setup the hardware after reset:
1999 * The receive engine is set going.
2000 * Frame transmit is handled entirely
2001 * in the frame output path; there's nothing to do
2002 * here except setup the interrupt mask.
2003 */
2004 if (ath_startrecv(sc) != 0) {
8feceb67 2005 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2006 "Unable to start recv logic\n");
141b38b6
S		 2007 r = -EIO;
2008 goto mutex_unlock;
f078f209 2009 }
8feceb67 2010
ff37e337 2011 /* Setup our intr mask. */
17d7904d 2012 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2013 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2014 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2015
2660b81a 2016 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2017 sc->imask |= ATH9K_INT_GTT;
ff37e337 2018
2660b81a 2019 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2020 sc->imask |= ATH9K_INT_CST;
ff37e337 2021
ce111bad 2022 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2023
2024 sc->sc_flags &= ~SC_OP_INVALID;
2025
2026 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2027 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2028 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 2029
2030 ieee80211_wake_queues(sc->hw);
2031
e97275cb 2032#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2033 r = ath_start_rfkill_poll(sc);
500c064d 2034#endif
141b38b6
S		 2035
2036mutex_unlock:
2037 mutex_unlock(&sc->mutex);
2038
ae8d2858 2039 return r;
f078f209
LR		 2040}
2041
8feceb67
VT		 2042static int ath9k_tx(struct ieee80211_hw *hw,
2043 struct sk_buff *skb)
f078f209 2044{
528f0c6b 2045 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2046 struct ath_softc *sc = hw->priv;
528f0c6b 2047 struct ath_tx_control txctl;
8feceb67 2048 int hdrlen, padsize;
528f0c6b
S		 2049
2050 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2051
8feceb67
VT		 2052 /*
2053 * As a temporary workaround, assign seq# here; this will likely need
2054 * to be cleaned up to work better with Beacon transmission and virtual
2055 * BSSes.
2056 */
2057 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2058 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2059 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2060 sc->tx.seq_no += 0x10;
8feceb67 2061 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2062 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2063 }
f078f209 2064
8feceb67
VT		 2065 /* Add the padding after the header if this is not already done */
2066 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2067 if (hdrlen & 3) {
2068 padsize = hdrlen % 4;
2069 if (skb_headroom(skb) < padsize)
2070 return -1;
2071 skb_push(skb, padsize);
2072 memmove(skb->data, skb->data + padsize, hdrlen);
2073 }
2074
528f0c6b
S		 2075 /* Check if a tx queue is available */
2076
2077 txctl.txq = ath_test_get_txq(sc, skb);
2078 if (!txctl.txq)
2079 goto exit;
2080
04bd4638 2081 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2082
528f0c6b 2083 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2084 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2085 goto exit;
8feceb67
VT		 2086 }
2087
528f0c6b
S		 2088 return 0;
2089exit:
2090 dev_kfree_skb_any(skb);
8feceb67 2091 return 0;
f078f209
LR		 2092}
2093
8feceb67 2094static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2095{
2096 struct ath_softc *sc = hw->priv;
f078f209 2097
9c84b797 2098 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2099 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2100 return;
2101 }
8feceb67 2102
141b38b6 2103 mutex_lock(&sc->mutex);
ff37e337
S		 2104
2105 ieee80211_stop_queues(sc->hw);
2106
2107 /* make sure h/w will not generate any interrupt
2108 * before setting the invalid flag. */
2109 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2110
2111 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2112 ath_drain_all_txq(sc, false);
ff37e337
S		 2113 ath_stoprecv(sc);
2114 ath9k_hw_phy_disable(sc->sc_ah);
2115 } else
b77f483f 2116 sc->rx.rxlink = NULL;
ff37e337
S		 2117
2118#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2119 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2120 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2121#endif
2122 /* disable HAL and put h/w to sleep */
2123 ath9k_hw_disable(sc->sc_ah);
2124 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2125
2126 sc->sc_flags |= SC_OP_INVALID;
500c064d 2127
141b38b6
S		 2128 mutex_unlock(&sc->mutex);
2129
04bd4638 2130 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2131}
2132
8feceb67
VT		 2133static int ath9k_add_interface(struct ieee80211_hw *hw,
2134 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2135{
2136 struct ath_softc *sc = hw->priv;
17d7904d 2137 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2138 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2139
17d7904d 2140 /* Support only vif for now */
8feceb67 2141
17d7904d 2142 if (sc->nvifs)
8feceb67
VT		 2143 return -ENOBUFS;
2144
141b38b6
S		 2145 mutex_lock(&sc->mutex);
2146
8feceb67 2147 switch (conf->type) {
05c914fe 2148 case NL80211_IFTYPE_STATION:
d97809db 2149 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2150 break;
05c914fe 2151 case NL80211_IFTYPE_ADHOC:
d97809db 2152 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2153 break;
05c914fe 2154 case NL80211_IFTYPE_AP:
d97809db 2155 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2156 break;
2157 default:
2158 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2159 "Interface type %d not yet supported\n", conf->type);
222d0b33 2160 mutex_unlock(&sc->mutex);
8feceb67 2161 return -EOPNOTSUPP;
f078f209
LR		 2162 }
2163
17d7904d 2164 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2165
17d7904d 2166 /* Set the VIF opmode */
5640b08e
S		 2167 avp->av_opmode = ic_opmode;
2168 avp->av_bslot = -1;
2169
d97809db 2170 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2171 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2172
17d7904d
S		 2173 sc->vifs[0] = conf->vif;
2174 sc->nvifs++;
5640b08e
S		 2175
2176 /* Set the device opmode */
2660b81a 2177 sc->sc_ah->opmode = ic_opmode;
5640b08e 2178
4e30ffa2
VN		 2179 /*
2180 * Enable MIB interrupts when there are hardware phy counters.
2181 * Note we only do this (at the moment) for station mode.
2182 */
4af9cf4f
S		 2183 if ((conf->type == NL80211_IFTYPE_STATION) ||
2184 (conf->type == NL80211_IFTYPE_ADHOC)) {
2185 if (ath9k_hw_phycounters(sc->sc_ah))
2186 sc->imask |= ATH9K_INT_MIB;
2187 sc->imask |= ATH9K_INT_TSFOOR;
2188 }
2189
4e30ffa2
VN		 2190 /*
2191 * Some hardware processes the TIM IE and fires an
2192 * interrupt when the TIM bit is set. For hardware
2193 * that does, if not overridden by configuration,
2194 * enable the TIM interrupt when operating as station.
2195 */
2660b81a 2196 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2197 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2198 !sc->config.swBeaconProcess)
2199 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2200
17d7904d 2201 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2202
6f255425
LR		 2203 if (conf->type == NL80211_IFTYPE_AP) {
2204 /* TODO: is this a suitable place to start ANI for AP mode? */
2205 /* Start ANI */
17d7904d 2206 mod_timer(&sc->ani.timer,
6f255425
LR		 2207 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2208 }
2209
141b38b6
S		 2210 mutex_unlock(&sc->mutex);
2211
8feceb67 2212 return 0;
f078f209
LR		 2213}
2214
8feceb67
VT		 2215static void ath9k_remove_interface(struct ieee80211_hw *hw,
2216 struct ieee80211_if_init_conf *conf)
f078f209 2217{
8feceb67 2218 struct ath_softc *sc = hw->priv;
17d7904d 2219 struct ath_vif *avp = (void *)conf->vif->drv_priv;
f078f209 2220
04bd4638 2221 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2222
141b38b6
S		 2223 mutex_lock(&sc->mutex);
2224
6f255425 2225 /* Stop ANI */
17d7904d 2226 del_timer_sync(&sc->ani.timer);
580f0b8a 2227
8feceb67 2228 /* Reclaim beacon resources */
2660b81a
S		 2229 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2230 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2231 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2232 ath_beacon_return(sc, avp);
580f0b8a 2233 }
f078f209 2234
8feceb67 2235 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2236
17d7904d
S		 2237 sc->vifs[0] = NULL;
2238 sc->nvifs--;
141b38b6
S		 2239
2240 mutex_unlock(&sc->mutex);
f078f209
LR		 2241}
2242
e8975581 2243static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2244{
8feceb67 2245 struct ath_softc *sc = hw->priv;
e8975581 2246 struct ieee80211_conf *conf = &hw->conf;
f078f209 2247
aa33de09 2248 mutex_lock(&sc->mutex);
141b38b6 2249
3cbb5dd7
VN		 2250 if (changed & IEEE80211_CONF_CHANGE_PS) {
2251 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2252 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2253 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2254 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2255 sc->imask);
3cbb5dd7
VN		 2256 }
2257 ath9k_hw_setrxabort(sc->sc_ah, 1);
2258 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2259 } else {
2260 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2261 ath9k_hw_setrxabort(sc->sc_ah, 0);
2262 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2263 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2264 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2265 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2266 sc->imask);
3cbb5dd7
VN		 2267 }
2268 }
2269 }
2270
4797938c 2271 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2272 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2273 int pos = curchan->hw_value;
ae5eb026 2274
04bd4638
S		 2275 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2276 curchan->center_freq);
f078f209 2277
5f8e077c 2278 /* XXX: remove me eventualy */
2660b81a 2279 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
e11602b7 2280
ecf70441 2281 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2282
2660b81a 2283 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2284 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2285 mutex_unlock(&sc->mutex);
e11602b7
S		 2286 return -EINVAL;
2287 }
094d05dc 2288 }
f078f209 2289
5c020dc6 2290 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2291 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2292
aa33de09 2293 mutex_unlock(&sc->mutex);
141b38b6 2294
f078f209
LR		 2295 return 0;
2296}
2297
8feceb67
VT		 2298static int ath9k_config_interface(struct ieee80211_hw *hw,
2299 struct ieee80211_vif *vif,
2300 struct ieee80211_if_conf *conf)
c83be688 2301{
8feceb67 2302 struct ath_softc *sc = hw->priv;
cbe61d8a 2303 struct ath_hw *ah = sc->sc_ah;
17d7904d 2304 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2305 u32 rfilt = 0;
2306 int error, i;
c83be688 2307
8feceb67
VT		 2308 /* TODO: Need to decide which hw opmode to use for multi-interface
2309 * cases */
05c914fe 2310 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2311 ah->opmode != NL80211_IFTYPE_AP) {
2312 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2313 ath9k_hw_setopmode(ah);
ba52da58
S		 2314 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2315 sc->curaid = 0;
2316 ath9k_hw_write_associd(sc);
8feceb67
VT		 2317 /* Request full reset to get hw opmode changed properly */
2318 sc->sc_flags |= SC_OP_FULL_RESET;
2319 }
c83be688 2320
8feceb67
VT		 2321 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2322 !is_zero_ether_addr(conf->bssid)) {
2323 switch (vif->type) {
05c914fe
JB		 2324 case NL80211_IFTYPE_STATION:
2325 case NL80211_IFTYPE_ADHOC:
8feceb67 2326 /* Set BSSID */
17d7904d
S		 2327 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2328 sc->curaid = 0;
ba52da58 2329 ath9k_hw_write_associd(sc);
c83be688 2330
8feceb67 2331 /* Set aggregation protection mode parameters */
17d7904d 2332 sc->config.ath_aggr_prot = 0;
c83be688 2333
8feceb67 2334 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2335 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2336 rfilt, sc->curbssid, sc->curaid);
c83be688 2337
8feceb67
VT		 2338 /* need to reconfigure the beacon */
2339 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2340
8feceb67
VT		 2341 break;
2342 default:
2343 break;
2344 }
2345 }
c83be688 2346
1f7d6cbf
S		 2347 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2348 (vif->type == NL80211_IFTYPE_AP)) {
2349 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2350 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2351 conf->enable_beacon)) {
2352 /*
2353 * Allocate and setup the beacon frame.
2354 *
2355 * Stop any previous beacon DMA. This may be
2356 * necessary, for example, when an ibss merge
2357 * causes reconfiguration; we may be called
2358 * with beacon transmission active.
2359 */
2360 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2361
1f7d6cbf
S		 2362 error = ath_beacon_alloc(sc, 0);
2363 if (error != 0)
2364 return error;
c83be688 2365
1f7d6cbf
S		 2366 ath_beacon_sync(sc, 0);
2367 }
8feceb67 2368 }
c83be688 2369
8feceb67 2370 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2371 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2372 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2373 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2374 ath9k_hw_keysetmac(sc->sc_ah,
2375 (u16)i,
17d7904d 2376 sc->curbssid);
8feceb67 2377 }
c83be688 2378
8feceb67 2379 /* Only legacy IBSS for now */
05c914fe 2380 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2381 ath_update_chainmask(sc, 0);
f078f209 2382
8feceb67
VT		 2383 return 0;
2384}
f078f209 2385
8feceb67
VT		 2386#define SUPPORTED_FILTERS \
2387 (FIF_PROMISC_IN_BSS | \
2388 FIF_ALLMULTI | \
2389 FIF_CONTROL | \
2390 FIF_OTHER_BSS | \
2391 FIF_BCN_PRBRESP_PROMISC | \
2392 FIF_FCSFAIL)
c83be688 2393
8feceb67
VT		 2394/* FIXME: sc->sc_full_reset ? */
2395static void ath9k_configure_filter(struct ieee80211_hw *hw,
2396 unsigned int changed_flags,
2397 unsigned int *total_flags,
2398 int mc_count,
2399 struct dev_mc_list *mclist)
2400{
2401 struct ath_softc *sc = hw->priv;
2402 u32 rfilt;
f078f209 2403
8feceb67
VT		 2404 changed_flags &= SUPPORTED_FILTERS;
2405 *total_flags &= SUPPORTED_FILTERS;
f078f209 2406
b77f483f 2407 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2408 rfilt = ath_calcrxfilter(sc);
2409 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2410
8feceb67 2411 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
ba52da58
S		 2412 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2413 memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2414 sc->curaid = 0;
2415 ath9k_hw_write_associd(sc);
2416 }
8feceb67 2417 }
f078f209 2418
b77f483f 2419 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2420}
f078f209 2421
8feceb67
VT		 2422static void ath9k_sta_notify(struct ieee80211_hw *hw,
2423 struct ieee80211_vif *vif,
2424 enum sta_notify_cmd cmd,
17741cdc 2425 struct ieee80211_sta *sta)
8feceb67
VT		 2426{
2427 struct ath_softc *sc = hw->priv;
f078f209 2428
8feceb67
VT		 2429 switch (cmd) {
2430 case STA_NOTIFY_ADD:
5640b08e 2431 ath_node_attach(sc, sta);
8feceb67
VT		 2432 break;
2433 case STA_NOTIFY_REMOVE:
b5aa9bf9 2434 ath_node_detach(sc, sta);
8feceb67
VT		 2435 break;
2436 default:
2437 break;
2438 }
f078f209
LR		 2439}
2440
141b38b6 2441static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2442 const struct ieee80211_tx_queue_params *params)
f078f209 2443{
8feceb67
VT		 2444 struct ath_softc *sc = hw->priv;
2445 struct ath9k_tx_queue_info qi;
2446 int ret = 0, qnum;
f078f209 2447
8feceb67
VT		 2448 if (queue >= WME_NUM_AC)
2449 return 0;
f078f209 2450
141b38b6
S		 2451 mutex_lock(&sc->mutex);
2452
8feceb67
VT		 2453 qi.tqi_aifs = params->aifs;
2454 qi.tqi_cwmin = params->cw_min;
2455 qi.tqi_cwmax = params->cw_max;
2456 qi.tqi_burstTime = params->txop;
2457 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2458
8feceb67 2459 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2460 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2461 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2462 queue, qnum, params->aifs, params->cw_min,
2463 params->cw_max, params->txop);
f078f209 2464
8feceb67
VT		 2465 ret = ath_txq_update(sc, qnum, &qi);
2466 if (ret)
04bd4638 2467 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2468
141b38b6
S		 2469 mutex_unlock(&sc->mutex);
2470
8feceb67
VT		 2471 return ret;
2472}
f078f209 2473
8feceb67
VT		 2474static int ath9k_set_key(struct ieee80211_hw *hw,
2475 enum set_key_cmd cmd,
dc822b5d
JB		 2476 struct ieee80211_vif *vif,
2477 struct ieee80211_sta *sta,
8feceb67
VT		 2478 struct ieee80211_key_conf *key)
2479{
2480 struct ath_softc *sc = hw->priv;
2481 int ret = 0;
f078f209 2482
b3bd89ce
JM		 2483 if (modparam_nohwcrypt)
2484 return -ENOSPC;
2485
141b38b6 2486 mutex_lock(&sc->mutex);
3cbb5dd7 2487 ath9k_ps_wakeup(sc);
04bd4638 2488 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2489
8feceb67
VT		 2490 switch (cmd) {
2491 case SET_KEY:
3f53dd64 2492 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2493 if (ret >= 0) {
2494 key->hw_key_idx = ret;
8feceb67
VT		 2495 /* push IV and Michael MIC generation to stack */
2496 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2497 if (key->alg == ALG_TKIP)
2498 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2499 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2500 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2501 ret = 0;
8feceb67
VT		 2502 }
2503 break;
2504 case DISABLE_KEY:
2505 ath_key_delete(sc, key);
8feceb67
VT		 2506 break;
2507 default:
2508 ret = -EINVAL;
2509 }
f078f209 2510
3cbb5dd7 2511 ath9k_ps_restore(sc);
141b38b6
S		 2512 mutex_unlock(&sc->mutex);
2513
8feceb67
VT		 2514 return ret;
2515}
f078f209 2516
8feceb67
VT		 2517static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2518 struct ieee80211_vif *vif,
2519 struct ieee80211_bss_conf *bss_conf,
2520 u32 changed)
2521{
2522 struct ath_softc *sc = hw->priv;
f078f209 2523
141b38b6
S		 2524 mutex_lock(&sc->mutex);
2525
8feceb67 2526 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2527 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2528 bss_conf->use_short_preamble);
2529 if (bss_conf->use_short_preamble)
2530 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2531 else
2532 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2533 }
f078f209 2534
8feceb67 2535 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2536 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2537 bss_conf->use_cts_prot);
2538 if (bss_conf->use_cts_prot &&
2539 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2540 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2541 else
2542 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2543 }
f078f209 2544
8feceb67 2545 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2546 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2547 bss_conf->assoc);
5640b08e 2548 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2549 }
141b38b6
S		 2550
2551 mutex_unlock(&sc->mutex);
8feceb67 2552}
f078f209 2553
8feceb67
VT		 2554static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2555{
2556 u64 tsf;
2557 struct ath_softc *sc = hw->priv;
f078f209 2558
141b38b6
S		 2559 mutex_lock(&sc->mutex);
2560 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2561 mutex_unlock(&sc->mutex);
f078f209 2562
8feceb67
VT		 2563 return tsf;
2564}
f078f209 2565
3b5d665b
AF		 2566static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2567{
2568 struct ath_softc *sc = hw->priv;
3b5d665b 2569
141b38b6
S		 2570 mutex_lock(&sc->mutex);
2571 ath9k_hw_settsf64(sc->sc_ah, tsf);
2572 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2573}
2574
8feceb67
VT		 2575static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2576{
2577 struct ath_softc *sc = hw->priv;
c83be688 2578
141b38b6
S		 2579 mutex_lock(&sc->mutex);
2580 ath9k_hw_reset_tsf(sc->sc_ah);
2581 mutex_unlock(&sc->mutex);
8feceb67 2582}
f078f209 2583
8feceb67 2584static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2585 enum ieee80211_ampdu_mlme_action action,
2586 struct ieee80211_sta *sta,
2587 u16 tid, u16 *ssn)
8feceb67
VT		 2588{
2589 struct ath_softc *sc = hw->priv;
2590 int ret = 0;
f078f209 2591
8feceb67
VT		 2592 switch (action) {
2593 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2594 if (!(sc->sc_flags & SC_OP_RXAGGR))
2595 ret = -ENOTSUPP;
8feceb67
VT		 2596 break;
2597 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2598 break;
2599 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2600 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2601 if (ret < 0)
2602 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2603 "Unable to start TX aggregation\n");
8feceb67 2604 else
17741cdc 2605 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2606 break;
2607 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2608 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2609 if (ret < 0)
2610 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2611 "Unable to stop TX aggregation\n");
f078f209 2612
17741cdc 2613 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2614 break;
8469cdef
S		 2615 case IEEE80211_AMPDU_TX_RESUME:
2616 ath_tx_aggr_resume(sc, sta, tid);
2617 break;
8feceb67 2618 default:
04bd4638 2619 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2620 }
2621
2622 return ret;
f078f209
LR		 2623}
2624
6baff7f9 2625struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2626 .tx = ath9k_tx,
2627 .start = ath9k_start,
2628 .stop = ath9k_stop,
2629 .add_interface = ath9k_add_interface,
2630 .remove_interface = ath9k_remove_interface,
2631 .config = ath9k_config,
2632 .config_interface = ath9k_config_interface,
2633 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2634 .sta_notify = ath9k_sta_notify,
2635 .conf_tx = ath9k_conf_tx,
8feceb67 2636 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2637 .set_key = ath9k_set_key,
8feceb67 2638 .get_tsf = ath9k_get_tsf,
3b5d665b 2639 .set_tsf = ath9k_set_tsf,
8feceb67 2640 .reset_tsf = ath9k_reset_tsf,
4233df6b 2641 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2642};
2643
392dff83
BP		 2644static struct {
2645 u32 version;
2646 const char * name;
2647} ath_mac_bb_names[] = {
2648 { AR_SREV_VERSION_5416_PCI, "5416" },
2649 { AR_SREV_VERSION_5416_PCIE, "5418" },
2650 { AR_SREV_VERSION_9100, "9100" },
2651 { AR_SREV_VERSION_9160, "9160" },
2652 { AR_SREV_VERSION_9280, "9280" },
2653 { AR_SREV_VERSION_9285, "9285" }
2654};
2655
2656static struct {
2657 u16 version;
2658 const char * name;
2659} ath_rf_names[] = {
2660 { 0, "5133" },
2661 { AR_RAD5133_SREV_MAJOR, "5133" },
2662 { AR_RAD5122_SREV_MAJOR, "5122" },
2663 { AR_RAD2133_SREV_MAJOR, "2133" },
2664 { AR_RAD2122_SREV_MAJOR, "2122" }
2665};
2666
2667/*
2668 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2669 */
6baff7f9 2670const char *
392dff83
BP		 2671ath_mac_bb_name(u32 mac_bb_version)
2672{
2673 int i;
2674
2675 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2676 if (ath_mac_bb_names[i].version == mac_bb_version) {
2677 return ath_mac_bb_names[i].name;
2678 }
2679 }
2680
2681 return "????";
2682}
2683
2684/*
2685 * Return the RF name. "????" is returned if the RF is unknown.
2686 */
6baff7f9 2687const char *
392dff83
BP		 2688ath_rf_name(u16 rf_version)
2689{
2690 int i;
2691
2692 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2693 if (ath_rf_names[i].version == rf_version) {
2694 return ath_rf_names[i].name;
2695 }
2696 }
2697
2698 return "????";
2699}
2700
6baff7f9 2701static int __init ath9k_init(void)
f078f209 2702{
ca8a8560
VT		 2703 int error;
2704
ca8a8560
VT		 2705 /* Register rate control algorithm */
2706 error = ath_rate_control_register();
2707 if (error != 0) {
2708 printk(KERN_ERR
b51bb3cd
LR		 2709 "ath9k: Unable to register rate control "
2710 "algorithm: %d\n",
ca8a8560 2711 error);
6baff7f9 2712 goto err_out;
ca8a8560
VT		 2713 }
2714
6baff7f9
GJ		 2715 error = ath_pci_init();
2716 if (error < 0) {
f078f209 2717 printk(KERN_ERR
b51bb3cd 2718 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2719 error = -ENODEV;
2720 goto err_rate_unregister;
f078f209
LR		 2721 }
2722
09329d37
GJ		 2723 error = ath_ahb_init();
2724 if (error < 0) {
2725 error = -ENODEV;
2726 goto err_pci_exit;
2727 }
2728
f078f209 2729 return 0;
6baff7f9 2730
09329d37
GJ		 2731 err_pci_exit:
2732 ath_pci_exit();
2733
6baff7f9
GJ		 2734 err_rate_unregister:
2735 ath_rate_control_unregister();
2736 err_out:
2737 return error;
f078f209 2738}
6baff7f9 2739module_init(ath9k_init);
f078f209 2740
6baff7f9 2741static void __exit ath9k_exit(void)
f078f209 2742{
09329d37 2743 ath_ahb_exit();
6baff7f9 2744 ath_pci_exit();
ca8a8560 2745 ath_rate_control_unregister();
04bd4638 2746 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2747}
6baff7f9 2748module_exit(ath9k_exit);
Linux kernel - Deliverables
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