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mac80211: make wake/stop_queue_by_reason() functions static
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
e7594072 37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
f078f209
LR		 38 { 0 }
39};
40
9757d556
S		 41static void ath_detach(struct ath_softc *sc);
42
ff37e337
S		 43/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60}
61
ce111bad
LR		 62static void ath_cache_conf_rate(struct ath_softc *sc,
63 struct ieee80211_conf *conf)
ff37e337 64{
030bb495
LR		 65 switch (conf->channel->band) {
66 case IEEE80211_BAND_2GHZ:
67 if (conf_is_ht20(conf))
68 sc->cur_rate_table =
69 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
70 else if (conf_is_ht40_minus(conf))
71 sc->cur_rate_table =
72 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
73 else if (conf_is_ht40_plus(conf))
74 sc->cur_rate_table =
75 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 76 else
030bb495
LR		 77 sc->cur_rate_table =
78 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 79 break;
80 case IEEE80211_BAND_5GHZ:
81 if (conf_is_ht20(conf))
82 sc->cur_rate_table =
83 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
84 else if (conf_is_ht40_minus(conf))
85 sc->cur_rate_table =
86 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
87 else if (conf_is_ht40_plus(conf))
88 sc->cur_rate_table =
89 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
90 else
96742256
LR		 91 sc->cur_rate_table =
92 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 93 break;
94 default:
ce111bad 95 BUG_ON(1);
030bb495
LR		 96 break;
97 }
ff37e337
S		 98}
99
100static void ath_update_txpow(struct ath_softc *sc)
101{
102 struct ath_hal *ah = sc->sc_ah;
103 u32 txpow;
104
105 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
106 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
107 /* read back in case value is clamped */
108 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
109 sc->sc_curtxpow = txpow;
110 }
111}
112
113static u8 parse_mpdudensity(u8 mpdudensity)
114{
115 /*
116 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
117 * 0 for no restriction
118 * 1 for 1/4 us
119 * 2 for 1/2 us
120 * 3 for 1 us
121 * 4 for 2 us
122 * 5 for 4 us
123 * 6 for 8 us
124 * 7 for 16 us
125 */
126 switch (mpdudensity) {
127 case 0:
128 return 0;
129 case 1:
130 case 2:
131 case 3:
132 /* Our lower layer calculations limit our precision to
133 1 microsecond */
134 return 1;
135 case 4:
136 return 2;
137 case 5:
138 return 4;
139 case 6:
140 return 8;
141 case 7:
142 return 16;
143 default:
144 return 0;
145 }
146}
147
148static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
149{
150 struct ath_rate_table *rate_table = NULL;
151 struct ieee80211_supported_band *sband;
152 struct ieee80211_rate *rate;
153 int i, maxrates;
154
155 switch (band) {
156 case IEEE80211_BAND_2GHZ:
157 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
158 break;
159 case IEEE80211_BAND_5GHZ:
160 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
161 break;
162 default:
163 break;
164 }
165
166 if (rate_table == NULL)
167 return;
168
169 sband = &sc->sbands[band];
170 rate = sc->rates[band];
171
172 if (rate_table->rate_cnt > ATH_RATE_MAX)
173 maxrates = ATH_RATE_MAX;
174 else
175 maxrates = rate_table->rate_cnt;
176
177 for (i = 0; i < maxrates; i++) {
178 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
179 rate[i].hw_value = rate_table->info[i].ratecode;
180 sband->n_bitrates++;
04bd4638
S		 181 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
182 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 183 }
184}
185
186static int ath_setup_channels(struct ath_softc *sc)
187{
188 struct ath_hal *ah = sc->sc_ah;
189 int nchan, i, a = 0, b = 0;
190 u8 regclassids[ATH_REGCLASSIDS_MAX];
191 u32 nregclass = 0;
192 struct ieee80211_supported_band *band_2ghz;
193 struct ieee80211_supported_band *band_5ghz;
194 struct ieee80211_channel *chan_2ghz;
195 struct ieee80211_channel *chan_5ghz;
196 struct ath9k_channel *c;
197
198 /* Fill in ah->ah_channels */
199 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
200 regclassids, ATH_REGCLASSIDS_MAX,
201 &nregclass, CTRY_DEFAULT, false, 1)) {
202 u32 rd = ah->ah_currentRD;
203 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 204 "Unable to collect channel list; "
ff37e337 205 "regdomain likely %u country code %u\n",
04bd4638 206 rd, CTRY_DEFAULT);
ff37e337
S		 207 return -EINVAL;
208 }
209
210 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
211 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
212 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
213 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
214
215 for (i = 0; i < nchan; i++) {
216 c = &ah->ah_channels[i];
217 if (IS_CHAN_2GHZ(c)) {
218 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
219 chan_2ghz[a].center_freq = c->channel;
220 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 221 c->chan = &chan_2ghz[a];
ff37e337
S		 222
223 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
225 if (c->channelFlags & CHANNEL_PASSIVE)
226 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
227
228 band_2ghz->n_channels = ++a;
229
04bd4638 230 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 231 "channelFlags: 0x%x\n",
04bd4638 232 c->channel, c->channelFlags);
ff37e337
S		 233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 237 c->chan = &chan_5ghz[a];
ff37e337
S		 238
239 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
240 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
243
244 band_5ghz->n_channels = ++b;
245
04bd4638 246 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 247 "channelFlags: 0x%x\n",
04bd4638 248 c->channel, c->channelFlags);
ff37e337
S		 249 }
250 }
251
252 return 0;
253}
254
255/*
256 * Set/change channels. If the channel is really being changed, it's done
257 * by reseting the chip. To accomplish this we must first cleanup any pending
258 * DMA, then restart stuff.
259*/
260static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
261{
262 struct ath_hal *ah = sc->sc_ah;
263 bool fastcc = true, stopped;
030bb495 264 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 265 struct ieee80211_channel *channel = hw->conf.channel;
266 int r;
ff37e337
S		 267
268 if (sc->sc_flags & SC_OP_INVALID)
269 return -EIO;
270
c0d7c7af
LR		 271 /*
272 * This is only performed if the channel settings have
273 * actually changed.
274 *
275 * To switch channels clear any pending DMA operations;
276 * wait long enough for the RX fifo to drain, reset the
277 * hardware at the new frequency, and then re-enable
278 * the relevant bits of the h/w.
279 */
280 ath9k_hw_set_interrupts(ah, 0);
281 ath_draintxq(sc, false);
282 stopped = ath_stoprecv(sc);
ff37e337 283
c0d7c7af
LR		 284 /* XXX: do not flush receive queue here. We don't want
285 * to flush data frames already in queue because of
286 * changing channel. */
ff37e337 287
c0d7c7af
LR		 288 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
289 fastcc = false;
290
291 DPRINTF(sc, ATH_DBG_CONFIG,
292 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
293 sc->sc_ah->ah_curchan->channel,
294 channel->center_freq, sc->tx_chan_width);
ff37e337 295
c0d7c7af
LR		 296 spin_lock_bh(&sc->sc_resetlock);
297
298 r = ath9k_hw_reset(ah, hchan, fastcc);
299 if (r) {
300 DPRINTF(sc, ATH_DBG_FATAL,
301 "Unable to reset channel (%u Mhz) "
302 "reset status %u\n",
303 channel->center_freq, r);
304 spin_unlock_bh(&sc->sc_resetlock);
305 return r;
ff37e337 306 }
c0d7c7af
LR		 307 spin_unlock_bh(&sc->sc_resetlock);
308
309 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
310 sc->sc_flags &= ~SC_OP_FULL_RESET;
311
312 if (ath_startrecv(sc) != 0) {
313 DPRINTF(sc, ATH_DBG_FATAL,
314 "Unable to restart recv logic\n");
315 return -EIO;
316 }
317
318 ath_cache_conf_rate(sc, &hw->conf);
319 ath_update_txpow(sc);
320 ath9k_hw_set_interrupts(ah, sc->sc_imask);
ff37e337
S		 321 return 0;
322}
323
324/*
325 * This routine performs the periodic noise floor calibration function
326 * that is used to adjust and optimize the chip performance. This
327 * takes environmental changes (location, temperature) into account.
328 * When the task is complete, it reschedules itself depending on the
329 * appropriate interval that was calculated.
330 */
331static void ath_ani_calibrate(unsigned long data)
332{
333 struct ath_softc *sc;
334 struct ath_hal *ah;
335 bool longcal = false;
336 bool shortcal = false;
337 bool aniflag = false;
338 unsigned int timestamp = jiffies_to_msecs(jiffies);
339 u32 cal_interval;
340
341 sc = (struct ath_softc *)data;
342 ah = sc->sc_ah;
343
344 /*
345 * don't calibrate when we're scanning.
346 * we are most likely not on our home channel.
347 */
b77f483f 348 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 349 return;
350
351 /* Long calibration runs independently of short calibration. */
352 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
353 longcal = true;
04bd4638 354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 355 sc->sc_ani.sc_longcal_timer = timestamp;
356 }
357
358 /* Short calibration applies only while sc_caldone is false */
359 if (!sc->sc_ani.sc_caldone) {
360 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
361 ATH_SHORT_CALINTERVAL) {
362 shortcal = true;
04bd4638 363 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 364 sc->sc_ani.sc_shortcal_timer = timestamp;
365 sc->sc_ani.sc_resetcal_timer = timestamp;
366 }
367 } else {
368 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
369 ATH_RESTART_CALINTERVAL) {
c9e27d94 370 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 371 if (sc->sc_ani.sc_caldone)
372 sc->sc_ani.sc_resetcal_timer = timestamp;
373 }
374 }
375
376 /* Verify whether we must check ANI */
377 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
378 ATH_ANI_POLLINTERVAL) {
379 aniflag = true;
380 sc->sc_ani.sc_checkani_timer = timestamp;
381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
387 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
388 ah->ah_curchan);
389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
392 bool iscaldone = false;
393
394 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
395 sc->sc_rx_chainmask, longcal,
396 &iscaldone)) {
397 if (longcal)
398 sc->sc_ani.sc_noise_floor =
399 ath9k_hw_getchan_noise(ah,
400 ah->ah_curchan);
401
402 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 403 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 404 ah->ah_curchan->channel,
405 ah->ah_curchan->channelFlags,
406 sc->sc_ani.sc_noise_floor);
407 } else {
408 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 409 "calibrate chan %u/%x failed\n",
ff37e337
S		 410 ah->ah_curchan->channel,
411 ah->ah_curchan->channelFlags);
412 }
413 sc->sc_ani.sc_caldone = iscaldone;
414 }
415 }
416
417 /*
418 * Set timer interval based on previous results.
419 * The interval must be the shortest necessary to satisfy ANI,
420 * short calibration and long calibration.
421 */
aac9207e
S		 422 cal_interval = ATH_LONG_CALINTERVAL;
423 if (sc->sc_ah->ah_config.enable_ani)
424 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 425 if (!sc->sc_ani.sc_caldone)
426 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
427
428 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
429}
430
431/*
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
434 * the chainmask configuration.
435 */
436static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
437{
438 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
439 if (is_ht) {
440 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
441 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
442 } else {
443 sc->sc_tx_chainmask = 1;
444 sc->sc_rx_chainmask = 1;
445 }
446
04bd4638
S		 447 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
448 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 449}
450
451static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
452{
453 struct ath_node *an;
454
455 an = (struct ath_node *)sta->drv_priv;
456
457 if (sc->sc_flags & SC_OP_TXAGGR)
458 ath_tx_node_init(sc, an);
459
460 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
461 sta->ht_cap.ampdu_factor);
462 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
463}
464
465static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
466{
467 struct ath_node *an = (struct ath_node *)sta->drv_priv;
468
469 if (sc->sc_flags & SC_OP_TXAGGR)
470 ath_tx_node_cleanup(sc, an);
471}
472
473static void ath9k_tasklet(unsigned long data)
474{
475 struct ath_softc *sc = (struct ath_softc *)data;
476 u32 status = sc->sc_intrstatus;
477
478 if (status & ATH9K_INT_FATAL) {
479 /* need a chip reset */
480 ath_reset(sc, false);
481 return;
482 } else {
483
484 if (status &
485 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 486 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 487 ath_rx_tasklet(sc, 0);
b77f483f 488 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 489 }
490 /* XXX: optimize this */
491 if (status & ATH9K_INT_TX)
492 ath_tx_tasklet(sc);
493 }
494
495 /* re-enable hardware interrupt */
496 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
497}
498
499static irqreturn_t ath_isr(int irq, void *dev)
500{
501 struct ath_softc *sc = dev;
502 struct ath_hal *ah = sc->sc_ah;
503 enum ath9k_int status;
504 bool sched = false;
505
506 do {
507 if (sc->sc_flags & SC_OP_INVALID) {
508 /*
509 * The hardware is not ready/present, don't
510 * touch anything. Note this can happen early
511 * on if the IRQ is shared.
512 */
513 return IRQ_NONE;
514 }
515 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
516 return IRQ_NONE;
517 }
518
519 /*
520 * Figure out the reason(s) for the interrupt. Note
521 * that the hal returns a pseudo-ISR that may include
522 * bits we haven't explicitly enabled so we mask the
523 * value to insure we only process bits we requested.
524 */
525 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
526
527 status &= sc->sc_imask; /* discard unasked-for bits */
528
529 /*
530 * If there are no status bits set, then this interrupt was not
531 * for me (should have been caught above).
532 */
533 if (!status)
534 return IRQ_NONE;
535
536 sc->sc_intrstatus = status;
537
538 if (status & ATH9K_INT_FATAL) {
539 /* need a chip reset */
540 sched = true;
541 } else if (status & ATH9K_INT_RXORN) {
542 /* need a chip reset */
543 sched = true;
544 } else {
545 if (status & ATH9K_INT_SWBA) {
546 /* schedule a tasklet for beacon handling */
547 tasklet_schedule(&sc->bcon_tasklet);
548 }
549 if (status & ATH9K_INT_RXEOL) {
550 /*
551 * NB: the hardware should re-read the link when
552 * RXE bit is written, but it doesn't work
553 * at least on older hardware revs.
554 */
555 sched = true;
556 }
557
558 if (status & ATH9K_INT_TXURN)
559 /* bump tx trigger level */
560 ath9k_hw_updatetxtriglevel(ah, true);
561 /* XXX: optimize this */
562 if (status & ATH9K_INT_RX)
563 sched = true;
564 if (status & ATH9K_INT_TX)
565 sched = true;
566 if (status & ATH9K_INT_BMISS)
567 sched = true;
568 /* carrier sense timeout */
569 if (status & ATH9K_INT_CST)
570 sched = true;
571 if (status & ATH9K_INT_MIB) {
572 /*
573 * Disable interrupts until we service the MIB
574 * interrupt; otherwise it will continue to
575 * fire.
576 */
577 ath9k_hw_set_interrupts(ah, 0);
578 /*
579 * Let the hal handle the event. We assume
580 * it will clear whatever condition caused
581 * the interrupt.
582 */
583 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
584 ath9k_hw_set_interrupts(ah, sc->sc_imask);
585 }
586 if (status & ATH9K_INT_TIM_TIMER) {
587 if (!(ah->ah_caps.hw_caps &
588 ATH9K_HW_CAP_AUTOSLEEP)) {
589 /* Clear RxAbort bit so that we can
590 * receive frames */
591 ath9k_hw_setrxabort(ah, 0);
592 sched = true;
593 }
594 }
595 }
596 } while (0);
597
817e11de
S		 598 ath_debug_stat_interrupt(sc, status);
599
ff37e337
S		 600 if (sched) {
601 /* turn off every interrupt except SWBA */
602 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
603 tasklet_schedule(&sc->intr_tq);
604 }
605
606 return IRQ_HANDLED;
607}
608
f078f209
LR		 609static int ath_get_channel(struct ath_softc *sc,
610 struct ieee80211_channel *chan)
611{
612 int i;
613
614 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
615 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
616 return i;
617 }
618
619 return -1;
620}
621
622static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 623 struct ieee80211_channel *chan,
094d05dc 624 enum nl80211_channel_type channel_type)
f078f209
LR		 625{
626 u32 chanmode = 0;
f078f209
LR		 627
628 switch (chan->band) {
629 case IEEE80211_BAND_2GHZ:
094d05dc
S		 630 switch(channel_type) {
631 case NL80211_CHAN_NO_HT:
632 case NL80211_CHAN_HT20:
f078f209 633 chanmode = CHANNEL_G_HT20;
094d05dc
S		 634 break;
635 case NL80211_CHAN_HT40PLUS:
f078f209 636 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 637 break;
638 case NL80211_CHAN_HT40MINUS:
f078f209 639 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 640 break;
641 }
f078f209
LR		 642 break;
643 case IEEE80211_BAND_5GHZ:
094d05dc
S		 644 switch(channel_type) {
645 case NL80211_CHAN_NO_HT:
646 case NL80211_CHAN_HT20:
f078f209 647 chanmode = CHANNEL_A_HT20;
094d05dc
S		 648 break;
649 case NL80211_CHAN_HT40PLUS:
f078f209 650 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 651 break;
652 case NL80211_CHAN_HT40MINUS:
f078f209 653 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 654 break;
655 }
f078f209
LR		 656 break;
657 default:
658 break;
659 }
660
661 return chanmode;
662}
663
ff37e337
S		 664static int ath_keyset(struct ath_softc *sc, u16 keyix,
665 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
666{
667 bool status;
668
669 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
670 keyix, hk, mac, false);
671
672 return status != false;
673}
f078f209 674
6ace2891 675static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 676 struct ath9k_keyval *hk,
677 const u8 *addr)
678{
6ace2891
JM		 679 const u8 *key_rxmic;
680 const u8 *key_txmic;
f078f209 681
6ace2891
JM		 682 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
683 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 684
685 if (addr == NULL) {
686 /* Group key installation */
6ace2891
JM		 687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 689 }
690 if (!sc->sc_splitmic) {
691 /*
692 * data key goes at first index,
693 * the hal handles the MIC keys at index+64.
694 */
695 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
696 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 697 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 698 }
699 /*
700 * TX key goes at first index, RX key at +32.
701 * The hal handles the MIC keys at index+64.
702 */
703 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 704 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 705 /* Txmic entry failed. No need to proceed further */
706 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 707 "Setting TX MIC Key Failed\n");
f078f209
LR		 708 return 0;
709 }
710
711 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
712 /* XXX delete tx key on failure? */
6ace2891
JM		 713 return ath_keyset(sc, keyix + 32, hk, addr);
714}
715
716static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
717{
718 int i;
719
720 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
721 if (test_bit(i, sc->sc_keymap) ||
722 test_bit(i + 64, sc->sc_keymap))
723 continue; /* At least one part of TKIP key allocated */
724 if (sc->sc_splitmic &&
725 (test_bit(i + 32, sc->sc_keymap) ||
726 test_bit(i + 64 + 32, sc->sc_keymap)))
727 continue; /* At least one part of TKIP key allocated */
728
729 /* Found a free slot for a TKIP key */
730 return i;
731 }
732 return -1;
733}
734
735static int ath_reserve_key_cache_slot(struct ath_softc *sc)
736{
737 int i;
738
739 /* First, try to find slots that would not be available for TKIP. */
740 if (sc->sc_splitmic) {
741 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
742 if (!test_bit(i, sc->sc_keymap) &&
743 (test_bit(i + 32, sc->sc_keymap) ||
744 test_bit(i + 64, sc->sc_keymap) ||
745 test_bit(i + 64 + 32, sc->sc_keymap)))
746 return i;
747 if (!test_bit(i + 32, sc->sc_keymap) &&
748 (test_bit(i, sc->sc_keymap) ||
749 test_bit(i + 64, sc->sc_keymap) ||
750 test_bit(i + 64 + 32, sc->sc_keymap)))
751 return i + 32;
752 if (!test_bit(i + 64, sc->sc_keymap) &&
753 (test_bit(i , sc->sc_keymap) ||
754 test_bit(i + 32, sc->sc_keymap) ||
755 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 756 return i + 64;
6ace2891
JM		 757 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
758 (test_bit(i, sc->sc_keymap) ||
759 test_bit(i + 32, sc->sc_keymap) ||
760 test_bit(i + 64, sc->sc_keymap)))
ea612132 761 return i + 64 + 32;
6ace2891
JM		 762 }
763 } else {
764 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
765 if (!test_bit(i, sc->sc_keymap) &&
766 test_bit(i + 64, sc->sc_keymap))
767 return i;
768 if (test_bit(i, sc->sc_keymap) &&
769 !test_bit(i + 64, sc->sc_keymap))
770 return i + 64;
771 }
772 }
773
774 /* No partially used TKIP slots, pick any available slot */
775 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 776 /* Do not allow slots that could be needed for TKIP group keys
777 * to be used. This limitation could be removed if we know that
778 * TKIP will not be used. */
779 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
780 continue;
781 if (sc->sc_splitmic) {
782 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
783 continue;
784 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
785 continue;
786 }
787
6ace2891
JM		 788 if (!test_bit(i, sc->sc_keymap))
789 return i; /* Found a free slot for a key */
790 }
791
792 /* No free slot found */
793 return -1;
f078f209
LR		 794}
795
796static int ath_key_config(struct ath_softc *sc,
797 const u8 *addr,
798 struct ieee80211_key_conf *key)
799{
f078f209
LR		 800 struct ath9k_keyval hk;
801 const u8 *mac = NULL;
802 int ret = 0;
6ace2891 803 int idx;
f078f209
LR		 804
805 memset(&hk, 0, sizeof(hk));
806
807 switch (key->alg) {
808 case ALG_WEP:
809 hk.kv_type = ATH9K_CIPHER_WEP;
810 break;
811 case ALG_TKIP:
812 hk.kv_type = ATH9K_CIPHER_TKIP;
813 break;
814 case ALG_CCMP:
815 hk.kv_type = ATH9K_CIPHER_AES_CCM;
816 break;
817 default:
818 return -EINVAL;
819 }
820
6ace2891 821 hk.kv_len = key->keylen;
f078f209
LR		 822 memcpy(hk.kv_val, key->key, key->keylen);
823
6ace2891
JM		 824 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
825 /* For now, use the default keys for broadcast keys. This may
826 * need to change with virtual interfaces. */
827 idx = key->keyidx;
828 } else if (key->keyidx) {
829 struct ieee80211_vif *vif;
f078f209 830
6ace2891
JM		 831 mac = addr;
832 vif = sc->sc_vaps[0];
833 if (vif->type != NL80211_IFTYPE_AP) {
834 /* Only keyidx 0 should be used with unicast key, but
835 * allow this for client mode for now. */
836 idx = key->keyidx;
837 } else
838 return -EIO;
f078f209
LR		 839 } else {
840 mac = addr;
6ace2891
JM		 841 if (key->alg == ALG_TKIP)
842 idx = ath_reserve_key_cache_slot_tkip(sc);
843 else
844 idx = ath_reserve_key_cache_slot(sc);
845 if (idx < 0)
846 return -EIO; /* no free key cache entries */
f078f209
LR		 847 }
848
849 if (key->alg == ALG_TKIP)
6ace2891 850 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 851 else
6ace2891 852 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 853
854 if (!ret)
855 return -EIO;
856
6ace2891
JM		 857 set_bit(idx, sc->sc_keymap);
858 if (key->alg == ALG_TKIP) {
859 set_bit(idx + 64, sc->sc_keymap);
860 if (sc->sc_splitmic) {
861 set_bit(idx + 32, sc->sc_keymap);
862 set_bit(idx + 64 + 32, sc->sc_keymap);
863 }
864 }
865
866 return idx;
f078f209
LR		 867}
868
869static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
870{
6ace2891
JM		 871 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
872 if (key->hw_key_idx < IEEE80211_WEP_NKID)
873 return;
874
875 clear_bit(key->hw_key_idx, sc->sc_keymap);
876 if (key->alg != ALG_TKIP)
877 return;
f078f209 878
6ace2891
JM		 879 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
880 if (sc->sc_splitmic) {
881 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
882 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
883 }
f078f209
LR		 884}
885
d9fe60de 886static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 887{
60653678
S		 888#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
889#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 890
d9fe60de
JB		 891 ht_info->ht_supported = true;
892 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
893 IEEE80211_HT_CAP_SM_PS |
894 IEEE80211_HT_CAP_SGI_40 |
895 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 896
60653678
S		 897 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
898 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 899 /* set up supported mcs set */
900 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
901 ht_info->mcs.rx_mask[0] = 0xff;
902 ht_info->mcs.rx_mask[1] = 0xff;
903 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 904}
905
8feceb67 906static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 907 struct ieee80211_vif *vif,
8feceb67 908 struct ieee80211_bss_conf *bss_conf)
f078f209 909{
5640b08e 910 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 911
8feceb67 912 if (bss_conf->assoc) {
094d05dc
S		 913 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
914 bss_conf->aid, sc->sc_curbssid);
f078f209 915
8feceb67 916 /* New association, store aid */
d97809db 917 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 918 sc->sc_curaid = bss_conf->aid;
919 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
920 sc->sc_curaid);
921 }
f078f209 922
8feceb67
VT		 923 /* Configure the beacon */
924 ath_beacon_config(sc, 0);
925 sc->sc_flags |= SC_OP_BEACONS;
f078f209 926
8feceb67
VT		 927 /* Reset rssi stats */
928 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
929 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
930 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
931 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 932
6f255425
LR		 933 /* Start ANI */
934 mod_timer(&sc->sc_ani.timer,
935 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
936
8feceb67 937 } else {
04bd4638 938 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 939 sc->sc_curaid = 0;
f078f209 940 }
8feceb67 941}
f078f209 942
8feceb67
VT		 943/********************************/
944/* LED functions */
945/********************************/
f078f209 946
8feceb67
VT		 947static void ath_led_brightness(struct led_classdev *led_cdev,
948 enum led_brightness brightness)
949{
950 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
951 struct ath_softc *sc = led->sc;
f078f209 952
8feceb67
VT		 953 switch (brightness) {
954 case LED_OFF:
955 if (led->led_type == ATH_LED_ASSOC ||
956 led->led_type == ATH_LED_RADIO)
957 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
958 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
959 (led->led_type == ATH_LED_RADIO) ? 1 :
960 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
961 break;
962 case LED_FULL:
963 if (led->led_type == ATH_LED_ASSOC)
964 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
965 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
966 break;
967 default:
968 break;
f078f209 969 }
8feceb67 970}
f078f209 971
8feceb67
VT		 972static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
973 char *trigger)
974{
975 int ret;
f078f209 976
8feceb67
VT		 977 led->sc = sc;
978 led->led_cdev.name = led->name;
979 led->led_cdev.default_trigger = trigger;
980 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 981
8feceb67
VT		 982 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
983 if (ret)
984 DPRINTF(sc, ATH_DBG_FATAL,
985 "Failed to register led:%s", led->name);
986 else
987 led->registered = 1;
988 return ret;
989}
f078f209 990
8feceb67
VT		 991static void ath_unregister_led(struct ath_led *led)
992{
993 if (led->registered) {
994 led_classdev_unregister(&led->led_cdev);
995 led->registered = 0;
f078f209 996 }
f078f209
LR		 997}
998
8feceb67 999static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1000{
8feceb67
VT		 1001 ath_unregister_led(&sc->assoc_led);
1002 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1003 ath_unregister_led(&sc->tx_led);
1004 ath_unregister_led(&sc->rx_led);
1005 ath_unregister_led(&sc->radio_led);
1006 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1007}
f078f209 1008
8feceb67
VT		 1009static void ath_init_leds(struct ath_softc *sc)
1010{
1011 char *trigger;
1012 int ret;
f078f209 1013
8feceb67
VT		 1014 /* Configure gpio 1 for output */
1015 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1016 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1017 /* LED off, active low */
1018 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1019
8feceb67
VT		 1020 trigger = ieee80211_get_radio_led_name(sc->hw);
1021 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1022 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1023 ret = ath_register_led(sc, &sc->radio_led, trigger);
1024 sc->radio_led.led_type = ATH_LED_RADIO;
1025 if (ret)
1026 goto fail;
7dcfdcd9 1027
8feceb67
VT		 1028 trigger = ieee80211_get_assoc_led_name(sc->hw);
1029 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1030 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1031 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1032 sc->assoc_led.led_type = ATH_LED_ASSOC;
1033 if (ret)
1034 goto fail;
f078f209 1035
8feceb67
VT		 1036 trigger = ieee80211_get_tx_led_name(sc->hw);
1037 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1038 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1039 ret = ath_register_led(sc, &sc->tx_led, trigger);
1040 sc->tx_led.led_type = ATH_LED_TX;
1041 if (ret)
1042 goto fail;
f078f209 1043
8feceb67
VT		 1044 trigger = ieee80211_get_rx_led_name(sc->hw);
1045 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1046 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1047 ret = ath_register_led(sc, &sc->rx_led, trigger);
1048 sc->rx_led.led_type = ATH_LED_RX;
1049 if (ret)
1050 goto fail;
f078f209 1051
8feceb67
VT		 1052 return;
1053
1054fail:
1055 ath_deinit_leds(sc);
f078f209
LR		 1056}
1057
e97275cb 1058#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1059
500c064d
VT		 1060/*******************/
1061/* Rfkill */
1062/*******************/
1063
1064static void ath_radio_enable(struct ath_softc *sc)
1065{
1066 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1067 struct ieee80211_channel *channel = sc->hw->conf.channel;
1068 int r;
500c064d
VT		 1069
1070 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1071
1072 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1073
1074 if (r) {
500c064d 1075 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1076 "Unable to reset channel %u (%uMhz) ",
1077 "reset status %u\n",
1078 channel->center_freq, r);
500c064d
VT		 1079 }
1080 spin_unlock_bh(&sc->sc_resetlock);
1081
1082 ath_update_txpow(sc);
1083 if (ath_startrecv(sc) != 0) {
1084 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1085 "Unable to restart recv logic\n");
500c064d
VT		 1086 return;
1087 }
1088
1089 if (sc->sc_flags & SC_OP_BEACONS)
1090 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1091
1092 /* Re-Enable interrupts */
1093 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1094
1095 /* Enable LED */
1096 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1097 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1098 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1099
1100 ieee80211_wake_queues(sc->hw);
1101}
1102
1103static void ath_radio_disable(struct ath_softc *sc)
1104{
1105 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1106 struct ieee80211_channel *channel = sc->hw->conf.channel;
1107 int r;
500c064d
VT		 1108
1109 ieee80211_stop_queues(sc->hw);
1110
1111 /* Disable LED */
1112 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1113 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1114
1115 /* Disable interrupts */
1116 ath9k_hw_set_interrupts(ah, 0);
1117
1118 ath_draintxq(sc, false); /* clear pending tx frames */
1119 ath_stoprecv(sc); /* turn off frame recv */
1120 ath_flushrecv(sc); /* flush recv queue */
1121
1122 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1123 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1124 if (r) {
500c064d 1125 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1126 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1127 "reset status %u\n",
1128 channel->center_freq, r);
500c064d
VT		 1129 }
1130 spin_unlock_bh(&sc->sc_resetlock);
1131
1132 ath9k_hw_phy_disable(ah);
1133 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1134}
1135
1136static bool ath_is_rfkill_set(struct ath_softc *sc)
1137{
1138 struct ath_hal *ah = sc->sc_ah;
1139
1140 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1141 ah->ah_rfkill_polarity;
1142}
1143
1144/* h/w rfkill poll function */
1145static void ath_rfkill_poll(struct work_struct *work)
1146{
1147 struct ath_softc *sc = container_of(work, struct ath_softc,
1148 rf_kill.rfkill_poll.work);
1149 bool radio_on;
1150
1151 if (sc->sc_flags & SC_OP_INVALID)
1152 return;
1153
1154 radio_on = !ath_is_rfkill_set(sc);
1155
1156 /*
1157 * enable/disable radio only when there is a
1158 * state change in RF switch
1159 */
1160 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1161 enum rfkill_state state;
1162
1163 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1164 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1165 : RFKILL_STATE_HARD_BLOCKED;
1166 } else if (radio_on) {
1167 ath_radio_enable(sc);
1168 state = RFKILL_STATE_UNBLOCKED;
1169 } else {
1170 ath_radio_disable(sc);
1171 state = RFKILL_STATE_HARD_BLOCKED;
1172 }
1173
1174 if (state == RFKILL_STATE_HARD_BLOCKED)
1175 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1176 else
1177 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1178
1179 rfkill_force_state(sc->rf_kill.rfkill, state);
1180 }
1181
1182 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1183 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1184}
1185
1186/* s/w rfkill handler */
1187static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1188{
1189 struct ath_softc *sc = data;
1190
1191 switch (state) {
1192 case RFKILL_STATE_SOFT_BLOCKED:
1193 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1194 SC_OP_RFKILL_SW_BLOCKED)))
1195 ath_radio_disable(sc);
1196 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1197 return 0;
1198 case RFKILL_STATE_UNBLOCKED:
1199 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1200 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1201 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1202 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1203 "radio as it is disabled by h/w\n");
500c064d
VT		 1204 return -EPERM;
1205 }
1206 ath_radio_enable(sc);
1207 }
1208 return 0;
1209 default:
1210 return -EINVAL;
1211 }
1212}
1213
1214/* Init s/w rfkill */
1215static int ath_init_sw_rfkill(struct ath_softc *sc)
1216{
1217 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1218 RFKILL_TYPE_WLAN);
1219 if (!sc->rf_kill.rfkill) {
1220 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1221 return -ENOMEM;
1222 }
1223
1224 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1225 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1226 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1227 sc->rf_kill.rfkill->data = sc;
1228 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1229 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1230 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1231
1232 return 0;
1233}
1234
1235/* Deinitialize rfkill */
1236static void ath_deinit_rfkill(struct ath_softc *sc)
1237{
1238 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1239 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1240
1241 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1242 rfkill_unregister(sc->rf_kill.rfkill);
1243 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1244 sc->rf_kill.rfkill = NULL;
1245 }
1246}
9c84b797
S		 1247
1248static int ath_start_rfkill_poll(struct ath_softc *sc)
1249{
1250 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1251 queue_delayed_work(sc->hw->workqueue,
1252 &sc->rf_kill.rfkill_poll, 0);
1253
1254 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1255 if (rfkill_register(sc->rf_kill.rfkill)) {
1256 DPRINTF(sc, ATH_DBG_FATAL,
1257 "Unable to register rfkill\n");
1258 rfkill_free(sc->rf_kill.rfkill);
1259
1260 /* Deinitialize the device */
306efdd1 1261 ath_detach(sc);
9c84b797
S		 1262 if (sc->pdev->irq)
1263 free_irq(sc->pdev->irq, sc);
9c84b797
S		 1264 pci_iounmap(sc->pdev, sc->mem);
1265 pci_release_region(sc->pdev, 0);
1266 pci_disable_device(sc->pdev);
9757d556 1267 ieee80211_free_hw(sc->hw);
9c84b797
S		 1268 return -EIO;
1269 } else {
1270 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1271 }
1272 }
1273
1274 return 0;
1275}
500c064d
VT		 1276#endif /* CONFIG_RFKILL */
1277
9c84b797 1278static void ath_detach(struct ath_softc *sc)
f078f209 1279{
8feceb67 1280 struct ieee80211_hw *hw = sc->hw;
9c84b797 1281 int i = 0;
f078f209 1282
04bd4638 1283 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1284
e97275cb 1285#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1286 ath_deinit_rfkill(sc);
1287#endif
3fcdfb4b
VT		 1288 ath_deinit_leds(sc);
1289
1290 ieee80211_unregister_hw(hw);
8feceb67
VT		 1291 ath_rx_cleanup(sc);
1292 ath_tx_cleanup(sc);
f078f209 1293
9c84b797
S		 1294 tasklet_kill(&sc->intr_tq);
1295 tasklet_kill(&sc->bcon_tasklet);
f078f209 1296
9c84b797
S		 1297 if (!(sc->sc_flags & SC_OP_INVALID))
1298 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1299
9c84b797
S		 1300 /* cleanup tx queues */
1301 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1302 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1303 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1304
1305 ath9k_hw_detach(sc->sc_ah);
826d2680 1306 ath9k_exit_debug(sc);
f078f209
LR		 1307}
1308
ff37e337
S		 1309static int ath_init(u16 devid, struct ath_softc *sc)
1310{
1311 struct ath_hal *ah = NULL;
1312 int status;
1313 int error = 0, i;
1314 int csz = 0;
1315
1316 /* XXX: hardware will not be ready until ath_open() being called */
1317 sc->sc_flags |= SC_OP_INVALID;
88b126af 1318
826d2680
S		 1319 if (ath9k_init_debug(sc) < 0)
1320 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1321
1322 spin_lock_init(&sc->sc_resetlock);
aa33de09 1323 mutex_init(&sc->mutex);
ff37e337
S		 1324 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1325 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1326 (unsigned long)sc);
1327
1328 /*
1329 * Cache line size is used to size and align various
1330 * structures used to communicate with the hardware.
1331 */
1332 bus_read_cachesize(sc, &csz);
1333 /* XXX assert csz is non-zero */
1334 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1335
1336 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1337 if (ah == NULL) {
1338 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1339 "Unable to attach hardware; HAL status %u\n", status);
ff37e337
S		 1340 error = -ENXIO;
1341 goto bad;
1342 }
1343 sc->sc_ah = ah;
1344
1345 /* Get the hardware key cache size. */
1346 sc->sc_keymax = ah->ah_caps.keycache_size;
1347 if (sc->sc_keymax > ATH_KEYMAX) {
1348 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1349 "Warning, using only %u entries in %u key cache\n",
1350 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1351 sc->sc_keymax = ATH_KEYMAX;
1352 }
1353
1354 /*
1355 * Reset the key cache since some parts do not
1356 * reset the contents on initial power up.
1357 */
1358 for (i = 0; i < sc->sc_keymax; i++)
1359 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1360
1361 /* Collect the channel list using the default country code */
1362
1363 error = ath_setup_channels(sc);
1364 if (error)
1365 goto bad;
1366
1367 /* default to MONITOR mode */
d97809db
CM		 1368 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1369
ff37e337
S		 1370
1371 /* Setup rate tables */
1372
1373 ath_rate_attach(sc);
1374 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1375 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1376
1377 /*
1378 * Allocate hardware transmit queues: one queue for
1379 * beacon frames and one data queue for each QoS
1380 * priority. Note that the hal handles reseting
1381 * these queues at the needed time.
1382 */
b77f483f
S		 1383 sc->beacon.beaconq = ath_beaconq_setup(ah);
1384 if (sc->beacon.beaconq == -1) {
ff37e337 1385 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1386 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1387 error = -EIO;
1388 goto bad2;
1389 }
b77f483f
S		 1390 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1391 if (sc->beacon.cabq == NULL) {
ff37e337 1392 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1393 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1394 error = -EIO;
1395 goto bad2;
1396 }
1397
1398 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1399 ath_cabq_update(sc);
1400
b77f483f
S		 1401 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1402 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1403
1404 /* Setup data queues */
1405 /* NB: ensure BK queue is the lowest priority h/w queue */
1406 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1407 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1408 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1409 error = -EIO;
1410 goto bad2;
1411 }
1412
1413 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1414 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1415 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1416 error = -EIO;
1417 goto bad2;
1418 }
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1421 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1422 error = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1428 error = -EIO;
1429 goto bad2;
1430 }
1431
1432 /* Initializes the noise floor to a reasonable default value.
1433 * Later on this will be updated during ANI processing. */
1434
1435 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1436 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1437
1438 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1439 ATH9K_CIPHER_TKIP, NULL)) {
1440 /*
1441 * Whether we should enable h/w TKIP MIC.
1442 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1443 * report WMM capable, so it's always safe to turn on
1444 * TKIP MIC in this case.
1445 */
1446 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1447 0, 1, NULL);
1448 }
1449
1450 /*
1451 * Check whether the separate key cache entries
1452 * are required to handle both tx+rx MIC keys.
1453 * With split mic keys the number of stations is limited
1454 * to 27 otherwise 59.
1455 */
1456 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457 ATH9K_CIPHER_TKIP, NULL)
1458 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1459 ATH9K_CIPHER_MIC, NULL)
1460 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1461 0, NULL))
1462 sc->sc_splitmic = 1;
1463
1464 /* turn on mcast key search if possible */
1465 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1466 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1467 1, NULL);
1468
1469 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1470 sc->sc_config.txpowlimit_override = 0;
1471
1472 /* 11n Capabilities */
1473 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1474 sc->sc_flags |= SC_OP_TXAGGR;
1475 sc->sc_flags |= SC_OP_RXAGGR;
1476 }
1477
1478 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1479 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1480
1481 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1482 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1483
1484 ath9k_hw_getmac(ah, sc->sc_myaddr);
1485 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1486 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1487 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1488 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1489 }
1490
b77f483f 1491 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1492
1493 /* initialize beacon slots */
b77f483f
S		 1494 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1495 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1496
1497 /* save MISC configurations */
1498 sc->sc_config.swBeaconProcess = 1;
1499
ff37e337
S		 1500 /* setup channels and rates */
1501
1502 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1503 sc->channels[IEEE80211_BAND_2GHZ];
1504 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1505 sc->rates[IEEE80211_BAND_2GHZ];
1506 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1507
1508 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1509 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1510 sc->channels[IEEE80211_BAND_5GHZ];
1511 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1512 sc->rates[IEEE80211_BAND_5GHZ];
1513 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1514 }
1515
1516 return 0;
1517bad2:
1518 /* cleanup tx queues */
1519 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1520 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1521 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1522bad:
1523 if (ah)
1524 ath9k_hw_detach(ah);
1525
1526 return error;
1527}
1528
9c84b797 1529static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1530{
8feceb67
VT		 1531 struct ieee80211_hw *hw = sc->hw;
1532 int error = 0;
f078f209 1533
04bd4638 1534 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1535
8feceb67
VT		 1536 error = ath_init(devid, sc);
1537 if (error != 0)
1538 return error;
f078f209 1539
8feceb67 1540 /* get mac address from hardware and set in mac80211 */
f078f209 1541
8feceb67 1542 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1543
9c84b797
S		 1544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1546 IEEE80211_HW_SIGNAL_DBM |
1547 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1548
9c84b797
S		 1549 hw->wiphy->interface_modes =
1550 BIT(NL80211_IFTYPE_AP) |
1551 BIT(NL80211_IFTYPE_STATION) |
1552 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1553
8feceb67 1554 hw->queues = 4;
e63835b0
S		 1555 hw->max_rates = 4;
1556 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1557 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1558 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1559
8feceb67 1560 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1561
9c84b797
S		 1562 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1563 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1564 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1565 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1566 }
1567
1568 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1569 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1570 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1571 &sc->sbands[IEEE80211_BAND_5GHZ];
1572
db93e7b5
SB		 1573 /* initialize tx/rx engine */
1574 error = ath_tx_init(sc, ATH_TXBUF);
1575 if (error != 0)
1576 goto detach;
8feceb67 1577
db93e7b5
SB		 1578 error = ath_rx_init(sc, ATH_RXBUF);
1579 if (error != 0)
1580 goto detach;
8feceb67 1581
e97275cb 1582#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1583 /* Initialze h/w Rfkill */
1584 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1585 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1586
1587 /* Initialize s/w rfkill */
1588 if (ath_init_sw_rfkill(sc))
1589 goto detach;
1590#endif
1591
db93e7b5 1592 error = ieee80211_register_hw(hw);
8feceb67 1593
db93e7b5
SB		 1594 /* Initialize LED control */
1595 ath_init_leds(sc);
8feceb67
VT		 1596
1597 return 0;
1598detach:
1599 ath_detach(sc);
8feceb67 1600 return error;
f078f209
LR		 1601}
1602
ff37e337
S		 1603int ath_reset(struct ath_softc *sc, bool retry_tx)
1604{
1605 struct ath_hal *ah = sc->sc_ah;
030bb495 1606 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1607 int r;
ff37e337
S		 1608
1609 ath9k_hw_set_interrupts(ah, 0);
1610 ath_draintxq(sc, retry_tx);
1611 ath_stoprecv(sc);
1612 ath_flushrecv(sc);
1613
1614 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1615 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1616 if (r)
ff37e337 1617 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1618 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1619 spin_unlock_bh(&sc->sc_resetlock);
1620
1621 if (ath_startrecv(sc) != 0)
04bd4638 1622 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1623
1624 /*
1625 * We may be doing a reset in response to a request
1626 * that changes the channel so update any state that
1627 * might change as a result.
1628 */
ce111bad 1629 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1630
1631 ath_update_txpow(sc);
1632
1633 if (sc->sc_flags & SC_OP_BEACONS)
1634 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1635
1636 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1637
1638 if (retry_tx) {
1639 int i;
1640 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1641 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1642 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1643 ath_txq_schedule(sc, &sc->tx.txq[i]);
1644 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1645 }
1646 }
1647 }
1648
ae8d2858 1649 return r;
ff37e337
S		 1650}
1651
1652/*
1653 * This function will allocate both the DMA descriptor structure, and the
1654 * buffers it contains. These are used to contain the descriptors used
1655 * by the system.
1656*/
1657int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1658 struct list_head *head, const char *name,
1659 int nbuf, int ndesc)
1660{
1661#define DS2PHYS(_dd, _ds) \
1662 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1663#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1664#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1665
1666 struct ath_desc *ds;
1667 struct ath_buf *bf;
1668 int i, bsize, error;
1669
04bd4638
S		 1670 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1671 name, nbuf, ndesc);
ff37e337
S		 1672
1673 /* ath_desc must be a multiple of DWORDs */
1674 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1675 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1676 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1677 error = -ENOMEM;
1678 goto fail;
1679 }
1680
1681 dd->dd_name = name;
1682 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1683
1684 /*
1685 * Need additional DMA memory because we can't use
1686 * descriptors that cross the 4K page boundary. Assume
1687 * one skipped descriptor per 4K page.
1688 */
1689 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1690 u32 ndesc_skipped =
1691 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1692 u32 dma_len;
1693
1694 while (ndesc_skipped) {
1695 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1696 dd->dd_desc_len += dma_len;
1697
1698 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1699 };
1700 }
1701
1702 /* allocate descriptors */
1703 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1704 dd->dd_desc_len,
1705 &dd->dd_desc_paddr);
1706 if (dd->dd_desc == NULL) {
1707 error = -ENOMEM;
1708 goto fail;
1709 }
1710 ds = dd->dd_desc;
04bd4638
S		 1711 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1712 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1713 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1714
1715 /* allocate buffers */
1716 bsize = sizeof(struct ath_buf) * nbuf;
1717 bf = kmalloc(bsize, GFP_KERNEL);
1718 if (bf == NULL) {
1719 error = -ENOMEM;
1720 goto fail2;
1721 }
1722 memset(bf, 0, bsize);
1723 dd->dd_bufptr = bf;
1724
1725 INIT_LIST_HEAD(head);
1726 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1727 bf->bf_desc = ds;
1728 bf->bf_daddr = DS2PHYS(dd, ds);
1729
1730 if (!(sc->sc_ah->ah_caps.hw_caps &
1731 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1732 /*
1733 * Skip descriptor addresses which can cause 4KB
1734 * boundary crossing (addr + length) with a 32 dword
1735 * descriptor fetch.
1736 */
1737 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1738 ASSERT((caddr_t) bf->bf_desc <
1739 ((caddr_t) dd->dd_desc +
1740 dd->dd_desc_len));
1741
1742 ds += ndesc;
1743 bf->bf_desc = ds;
1744 bf->bf_daddr = DS2PHYS(dd, ds);
1745 }
1746 }
1747 list_add_tail(&bf->list, head);
1748 }
1749 return 0;
1750fail2:
1751 pci_free_consistent(sc->pdev,
1752 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1753fail:
1754 memset(dd, 0, sizeof(*dd));
1755 return error;
1756#undef ATH_DESC_4KB_BOUND_CHECK
1757#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1758#undef DS2PHYS
1759}
1760
1761void ath_descdma_cleanup(struct ath_softc *sc,
1762 struct ath_descdma *dd,
1763 struct list_head *head)
1764{
1765 pci_free_consistent(sc->pdev,
1766 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1767
1768 INIT_LIST_HEAD(head);
1769 kfree(dd->dd_bufptr);
1770 memset(dd, 0, sizeof(*dd));
1771}
1772
1773int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1774{
1775 int qnum;
1776
1777 switch (queue) {
1778 case 0:
b77f483f 1779 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1780 break;
1781 case 1:
b77f483f 1782 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1783 break;
1784 case 2:
b77f483f 1785 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1786 break;
1787 case 3:
b77f483f 1788 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1789 break;
1790 default:
b77f483f 1791 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1792 break;
1793 }
1794
1795 return qnum;
1796}
1797
1798int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1799{
1800 int qnum;
1801
1802 switch (queue) {
1803 case ATH9K_WME_AC_VO:
1804 qnum = 0;
1805 break;
1806 case ATH9K_WME_AC_VI:
1807 qnum = 1;
1808 break;
1809 case ATH9K_WME_AC_BE:
1810 qnum = 2;
1811 break;
1812 case ATH9K_WME_AC_BK:
1813 qnum = 3;
1814 break;
1815 default:
1816 qnum = -1;
1817 break;
1818 }
1819
1820 return qnum;
1821}
1822
1823/**********************/
1824/* mac80211 callbacks */
1825/**********************/
1826
8feceb67 1827static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1828{
1829 struct ath_softc *sc = hw->priv;
8feceb67 1830 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1831 struct ath9k_channel *init_channel;
ae8d2858 1832 int r, pos;
f078f209 1833
04bd4638
S		 1834 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1835 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1836
8feceb67 1837 /* setup initial channel */
f078f209 1838
8feceb67
VT		 1839 pos = ath_get_channel(sc, curchan);
1840 if (pos == -1) {
04bd4638 1841 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1842 return -EINVAL;
f078f209
LR		 1843 }
1844
99405f93 1845 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1846 sc->sc_ah->ah_channels[pos].chanmode =
1847 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1848 init_channel = &sc->sc_ah->ah_channels[pos];
1849
1850 /* Reset SERDES registers */
1851 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1852
1853 /*
1854 * The basic interface to setting the hardware in a good
1855 * state is ``reset''. On return the hardware is known to
1856 * be powered up and with interrupts disabled. This must
1857 * be followed by initialization of the appropriate bits
1858 * and then setup of the interrupt mask.
1859 */
1860 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1861 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1862 if (r) {
ff37e337 1863 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1864 "Unable to reset hardware; reset status %u "
1865 "(freq %u MHz)\n", r,
1866 curchan->center_freq);
ff37e337 1867 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1868 return r;
ff37e337
S		 1869 }
1870 spin_unlock_bh(&sc->sc_resetlock);
1871
1872 /*
1873 * This is needed only to setup initial state
1874 * but it's best done after a reset.
1875 */
1876 ath_update_txpow(sc);
8feceb67 1877
ff37e337
S		 1878 /*
1879 * Setup the hardware after reset:
1880 * The receive engine is set going.
1881 * Frame transmit is handled entirely
1882 * in the frame output path; there's nothing to do
1883 * here except setup the interrupt mask.
1884 */
1885 if (ath_startrecv(sc) != 0) {
8feceb67 1886 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1887 "Unable to start recv logic\n");
ae8d2858 1888 return -EIO;
f078f209 1889 }
8feceb67 1890
ff37e337
S		 1891 /* Setup our intr mask. */
1892 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1893 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1894 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1895
1896 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1897 sc->sc_imask |= ATH9K_INT_GTT;
1898
1899 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1900 sc->sc_imask |= ATH9K_INT_CST;
1901
1902 /*
1903 * Enable MIB interrupts when there are hardware phy counters.
1904 * Note we only do this (at the moment) for station mode.
1905 */
1906 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1907 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1908 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1909 sc->sc_imask |= ATH9K_INT_MIB;
1910 /*
1911 * Some hardware processes the TIM IE and fires an
1912 * interrupt when the TIM bit is set. For hardware
1913 * that does, if not overridden by configuration,
1914 * enable the TIM interrupt when operating as station.
1915 */
1916 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1917 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1918 !sc->sc_config.swBeaconProcess)
1919 sc->sc_imask |= ATH9K_INT_TIM;
1920
ce111bad 1921 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1922
1923 sc->sc_flags &= ~SC_OP_INVALID;
1924
1925 /* Disable BMISS interrupt when we're not associated */
1926 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1927 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1928
1929 ieee80211_wake_queues(sc->hw);
1930
e97275cb 1931#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1932 r = ath_start_rfkill_poll(sc);
500c064d 1933#endif
ae8d2858 1934 return r;
f078f209
LR		 1935}
1936
8feceb67
VT		 1937static int ath9k_tx(struct ieee80211_hw *hw,
1938 struct sk_buff *skb)
f078f209 1939{
528f0c6b 1940 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1941 struct ath_softc *sc = hw->priv;
528f0c6b 1942 struct ath_tx_control txctl;
8feceb67 1943 int hdrlen, padsize;
528f0c6b
S		 1944
1945 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1946
8feceb67
VT		 1947 /*
1948 * As a temporary workaround, assign seq# here; this will likely need
1949 * to be cleaned up to work better with Beacon transmission and virtual
1950 * BSSes.
1951 */
1952 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1953 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1954 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1955 sc->tx.seq_no += 0x10;
8feceb67 1956 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1957 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1958 }
f078f209 1959
8feceb67
VT		 1960 /* Add the padding after the header if this is not already done */
1961 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1962 if (hdrlen & 3) {
1963 padsize = hdrlen % 4;
1964 if (skb_headroom(skb) < padsize)
1965 return -1;
1966 skb_push(skb, padsize);
1967 memmove(skb->data, skb->data + padsize, hdrlen);
1968 }
1969
528f0c6b
S		 1970 /* Check if a tx queue is available */
1971
1972 txctl.txq = ath_test_get_txq(sc, skb);
1973 if (!txctl.txq)
1974 goto exit;
1975
04bd4638 1976 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1977
528f0c6b 1978 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1979 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1980 goto exit;
8feceb67
VT		 1981 }
1982
528f0c6b
S		 1983 return 0;
1984exit:
1985 dev_kfree_skb_any(skb);
8feceb67 1986 return 0;
f078f209
LR		 1987}
1988
8feceb67 1989static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 1990{
1991 struct ath_softc *sc = hw->priv;
f078f209 1992
9c84b797 1993 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 1994 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 1995 return;
1996 }
8feceb67 1997
04bd4638 1998 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 1999
2000 ieee80211_stop_queues(sc->hw);
2001
2002 /* make sure h/w will not generate any interrupt
2003 * before setting the invalid flag. */
2004 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2005
2006 if (!(sc->sc_flags & SC_OP_INVALID)) {
2007 ath_draintxq(sc, false);
2008 ath_stoprecv(sc);
2009 ath9k_hw_phy_disable(sc->sc_ah);
2010 } else
b77f483f 2011 sc->rx.rxlink = NULL;
ff37e337
S		 2012
2013#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2014 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2015 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2016#endif
2017 /* disable HAL and put h/w to sleep */
2018 ath9k_hw_disable(sc->sc_ah);
2019 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2020
2021 sc->sc_flags |= SC_OP_INVALID;
500c064d 2022
04bd4638 2023 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2024}
2025
8feceb67
VT		 2026static int ath9k_add_interface(struct ieee80211_hw *hw,
2027 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2028{
2029 struct ath_softc *sc = hw->priv;
5640b08e 2030 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2031 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2032
8feceb67
VT		 2033 /* Support only vap for now */
2034
2035 if (sc->sc_nvaps)
2036 return -ENOBUFS;
2037
2038 switch (conf->type) {
05c914fe 2039 case NL80211_IFTYPE_STATION:
d97809db 2040 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2041 break;
05c914fe 2042 case NL80211_IFTYPE_ADHOC:
d97809db 2043 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2044 break;
05c914fe 2045 case NL80211_IFTYPE_AP:
d97809db 2046 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2047 break;
2048 default:
2049 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2050 "Interface type %d not yet supported\n", conf->type);
8feceb67 2051 return -EOPNOTSUPP;
f078f209
LR		 2052 }
2053
04bd4638 2054 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2055
5640b08e
S		 2056 /* Set the VAP opmode */
2057 avp->av_opmode = ic_opmode;
2058 avp->av_bslot = -1;
2059
d97809db 2060 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2061 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2062
2063 sc->sc_vaps[0] = conf->vif;
2064 sc->sc_nvaps++;
2065
2066 /* Set the device opmode */
2067 sc->sc_ah->ah_opmode = ic_opmode;
2068
6f255425
LR		 2069 if (conf->type == NL80211_IFTYPE_AP) {
2070 /* TODO: is this a suitable place to start ANI for AP mode? */
2071 /* Start ANI */
2072 mod_timer(&sc->sc_ani.timer,
2073 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2074 }
2075
8feceb67 2076 return 0;
f078f209
LR		 2077}
2078
8feceb67
VT		 2079static void ath9k_remove_interface(struct ieee80211_hw *hw,
2080 struct ieee80211_if_init_conf *conf)
f078f209 2081{
8feceb67 2082 struct ath_softc *sc = hw->priv;
5640b08e 2083 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2084
04bd4638 2085 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2086
6f255425
LR		 2087 /* Stop ANI */
2088 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2089
8feceb67 2090 /* Reclaim beacon resources */
d97809db
CM		 2091 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2092 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2093 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2094 ath_beacon_return(sc, avp);
580f0b8a 2095 }
f078f209 2096
8feceb67 2097 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2098
5640b08e
S		 2099 sc->sc_vaps[0] = NULL;
2100 sc->sc_nvaps--;
f078f209
LR		 2101}
2102
e8975581 2103static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2104{
8feceb67 2105 struct ath_softc *sc = hw->priv;
e8975581 2106 struct ieee80211_conf *conf = &hw->conf;
f078f209 2107
aa33de09 2108 mutex_lock(&sc->mutex);
094d05dc
S		 2109 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2110 IEEE80211_CONF_CHANGE_HT)) {
99405f93
S		 2111 struct ieee80211_channel *curchan = hw->conf.channel;
2112 int pos;
ae5eb026 2113
04bd4638
S		 2114 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2115 curchan->center_freq);
f078f209 2116
99405f93
S		 2117 pos = ath_get_channel(sc, curchan);
2118 if (pos == -1) {
04bd4638
S		 2119 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2120 curchan->center_freq);
aa33de09 2121 mutex_unlock(&sc->mutex);
99405f93
S		 2122 return -EINVAL;
2123 }
f078f209 2124
99405f93 2125 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2126 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2127 (curchan->band == IEEE80211_BAND_2GHZ) ?
2128 CHANNEL_G : CHANNEL_A;
2129
ecf70441
LR		 2130 if (conf_is_ht(conf)) {
2131 if (conf_is_ht40(conf))
094d05dc 2132 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2133
2134 sc->sc_ah->ah_channels[pos].chanmode =
2135 ath_get_extchanmode(sc, curchan,
094d05dc 2136 conf->ht.channel_type);
e11602b7
S		 2137 }
2138
ecf70441 2139 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2140
e11602b7 2141 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2142 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2143 mutex_unlock(&sc->mutex);
e11602b7
S		 2144 return -EINVAL;
2145 }
094d05dc 2146 }
f078f209 2147
5c020dc6
LR		 2148 if (changed & IEEE80211_CONF_CHANGE_POWER)
2149 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2150
aa33de09 2151 mutex_unlock(&sc->mutex);
f078f209
LR		 2152 return 0;
2153}
2154
8feceb67
VT		 2155static int ath9k_config_interface(struct ieee80211_hw *hw,
2156 struct ieee80211_vif *vif,
2157 struct ieee80211_if_conf *conf)
c83be688 2158{
8feceb67
VT		 2159 struct ath_softc *sc = hw->priv;
2160 struct ath_hal *ah = sc->sc_ah;
5640b08e 2161 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2162 u32 rfilt = 0;
2163 int error, i;
c83be688 2164
8feceb67
VT		 2165 /* TODO: Need to decide which hw opmode to use for multi-interface
2166 * cases */
05c914fe 2167 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2168 ah->ah_opmode != NL80211_IFTYPE_AP) {
2169 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2170 ath9k_hw_setopmode(ah);
2171 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2172 /* Request full reset to get hw opmode changed properly */
2173 sc->sc_flags |= SC_OP_FULL_RESET;
2174 }
c83be688 2175
8feceb67
VT		 2176 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2177 !is_zero_ether_addr(conf->bssid)) {
2178 switch (vif->type) {
05c914fe
JB		 2179 case NL80211_IFTYPE_STATION:
2180 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2181 /* Set BSSID */
2182 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2183 sc->sc_curaid = 0;
2184 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2185 sc->sc_curaid);
c83be688 2186
8feceb67
VT		 2187 /* Set aggregation protection mode parameters */
2188 sc->sc_config.ath_aggr_prot = 0;
c83be688 2189
8feceb67 2190 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2191 "RX filter 0x%x bssid %pM aid 0x%x\n",
2192 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2193
8feceb67
VT		 2194 /* need to reconfigure the beacon */
2195 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2196
8feceb67
VT		 2197 break;
2198 default:
2199 break;
2200 }
2201 }
c83be688 2202
8feceb67 2203 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2204 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2205 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2206 /*
2207 * Allocate and setup the beacon frame.
2208 *
2209 * Stop any previous beacon DMA. This may be
2210 * necessary, for example, when an ibss merge
2211 * causes reconfiguration; we may be called
2212 * with beacon transmission active.
2213 */
b77f483f 2214 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2215
8feceb67
VT		 2216 error = ath_beacon_alloc(sc, 0);
2217 if (error != 0)
2218 return error;
c83be688 2219
8feceb67
VT		 2220 ath_beacon_sync(sc, 0);
2221 }
c83be688 2222
8feceb67 2223 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2224 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2225 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2226 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2227 ath9k_hw_keysetmac(sc->sc_ah,
2228 (u16)i,
2229 sc->sc_curbssid);
2230 }
c83be688 2231
8feceb67 2232 /* Only legacy IBSS for now */
05c914fe 2233 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2234 ath_update_chainmask(sc, 0);
f078f209 2235
8feceb67
VT		 2236 return 0;
2237}
f078f209 2238
8feceb67
VT		 2239#define SUPPORTED_FILTERS \
2240 (FIF_PROMISC_IN_BSS | \
2241 FIF_ALLMULTI | \
2242 FIF_CONTROL | \
2243 FIF_OTHER_BSS | \
2244 FIF_BCN_PRBRESP_PROMISC | \
2245 FIF_FCSFAIL)
c83be688 2246
8feceb67
VT		 2247/* FIXME: sc->sc_full_reset ? */
2248static void ath9k_configure_filter(struct ieee80211_hw *hw,
2249 unsigned int changed_flags,
2250 unsigned int *total_flags,
2251 int mc_count,
2252 struct dev_mc_list *mclist)
2253{
2254 struct ath_softc *sc = hw->priv;
2255 u32 rfilt;
f078f209 2256
8feceb67
VT		 2257 changed_flags &= SUPPORTED_FILTERS;
2258 *total_flags &= SUPPORTED_FILTERS;
f078f209 2259
b77f483f 2260 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2261 rfilt = ath_calcrxfilter(sc);
2262 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2263
8feceb67
VT		 2264 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2265 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2266 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2267 }
f078f209 2268
b77f483f 2269 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2270}
f078f209 2271
8feceb67
VT		 2272static void ath9k_sta_notify(struct ieee80211_hw *hw,
2273 struct ieee80211_vif *vif,
2274 enum sta_notify_cmd cmd,
17741cdc 2275 struct ieee80211_sta *sta)
8feceb67
VT		 2276{
2277 struct ath_softc *sc = hw->priv;
f078f209 2278
8feceb67
VT		 2279 switch (cmd) {
2280 case STA_NOTIFY_ADD:
5640b08e 2281 ath_node_attach(sc, sta);
8feceb67
VT		 2282 break;
2283 case STA_NOTIFY_REMOVE:
b5aa9bf9 2284 ath_node_detach(sc, sta);
8feceb67
VT		 2285 break;
2286 default:
2287 break;
2288 }
f078f209
LR		 2289}
2290
8feceb67
VT		 2291static int ath9k_conf_tx(struct ieee80211_hw *hw,
2292 u16 queue,
2293 const struct ieee80211_tx_queue_params *params)
f078f209 2294{
8feceb67
VT		 2295 struct ath_softc *sc = hw->priv;
2296 struct ath9k_tx_queue_info qi;
2297 int ret = 0, qnum;
f078f209 2298
8feceb67
VT		 2299 if (queue >= WME_NUM_AC)
2300 return 0;
f078f209 2301
8feceb67
VT		 2302 qi.tqi_aifs = params->aifs;
2303 qi.tqi_cwmin = params->cw_min;
2304 qi.tqi_cwmax = params->cw_max;
2305 qi.tqi_burstTime = params->txop;
2306 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2307
8feceb67 2308 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2309 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2310 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2311 queue, qnum, params->aifs, params->cw_min,
2312 params->cw_max, params->txop);
f078f209 2313
8feceb67
VT		 2314 ret = ath_txq_update(sc, qnum, &qi);
2315 if (ret)
04bd4638 2316 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2317
8feceb67
VT		 2318 return ret;
2319}
f078f209 2320
8feceb67
VT		 2321static int ath9k_set_key(struct ieee80211_hw *hw,
2322 enum set_key_cmd cmd,
2323 const u8 *local_addr,
2324 const u8 *addr,
2325 struct ieee80211_key_conf *key)
2326{
2327 struct ath_softc *sc = hw->priv;
2328 int ret = 0;
f078f209 2329
04bd4638 2330 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2331
8feceb67
VT		 2332 switch (cmd) {
2333 case SET_KEY:
2334 ret = ath_key_config(sc, addr, key);
6ace2891
JM		 2335 if (ret >= 0) {
2336 key->hw_key_idx = ret;
8feceb67
VT		 2337 /* push IV and Michael MIC generation to stack */
2338 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2339 if (key->alg == ALG_TKIP)
2340 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6ace2891 2341 ret = 0;
8feceb67
VT		 2342 }
2343 break;
2344 case DISABLE_KEY:
2345 ath_key_delete(sc, key);
8feceb67
VT		 2346 break;
2347 default:
2348 ret = -EINVAL;
2349 }
f078f209 2350
8feceb67
VT		 2351 return ret;
2352}
f078f209 2353
8feceb67
VT		 2354static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2355 struct ieee80211_vif *vif,
2356 struct ieee80211_bss_conf *bss_conf,
2357 u32 changed)
2358{
2359 struct ath_softc *sc = hw->priv;
f078f209 2360
8feceb67 2361 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2362 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2363 bss_conf->use_short_preamble);
2364 if (bss_conf->use_short_preamble)
2365 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2366 else
2367 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2368 }
f078f209 2369
8feceb67 2370 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2371 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2372 bss_conf->use_cts_prot);
2373 if (bss_conf->use_cts_prot &&
2374 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2375 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2376 else
2377 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2378 }
f078f209 2379
8feceb67 2380 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2381 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2382 bss_conf->assoc);
5640b08e 2383 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2384 }
2385}
f078f209 2386
8feceb67
VT		 2387static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2388{
2389 u64 tsf;
2390 struct ath_softc *sc = hw->priv;
2391 struct ath_hal *ah = sc->sc_ah;
f078f209 2392
8feceb67 2393 tsf = ath9k_hw_gettsf64(ah);
f078f209 2394
8feceb67
VT		 2395 return tsf;
2396}
f078f209 2397
8feceb67
VT		 2398static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2399{
2400 struct ath_softc *sc = hw->priv;
2401 struct ath_hal *ah = sc->sc_ah;
c83be688 2402
8feceb67
VT		 2403 ath9k_hw_reset_tsf(ah);
2404}
f078f209 2405
8feceb67
VT		 2406static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2407 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2408 struct ieee80211_sta *sta,
2409 u16 tid, u16 *ssn)
8feceb67
VT		 2410{
2411 struct ath_softc *sc = hw->priv;
2412 int ret = 0;
f078f209 2413
8feceb67
VT		 2414 switch (action) {
2415 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2416 if (!(sc->sc_flags & SC_OP_RXAGGR))
2417 ret = -ENOTSUPP;
8feceb67
VT		 2418 break;
2419 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2420 break;
2421 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2422 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2423 if (ret < 0)
2424 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2425 "Unable to start TX aggregation\n");
8feceb67 2426 else
17741cdc 2427 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2428 break;
2429 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2430 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2431 if (ret < 0)
2432 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2433 "Unable to stop TX aggregation\n");
f078f209 2434
17741cdc 2435 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2436 break;
8469cdef
S		 2437 case IEEE80211_AMPDU_TX_RESUME:
2438 ath_tx_aggr_resume(sc, sta, tid);
2439 break;
8feceb67 2440 default:
04bd4638 2441 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2442 }
2443
2444 return ret;
f078f209
LR		 2445}
2446
8feceb67
VT		 2447static struct ieee80211_ops ath9k_ops = {
2448 .tx = ath9k_tx,
2449 .start = ath9k_start,
2450 .stop = ath9k_stop,
2451 .add_interface = ath9k_add_interface,
2452 .remove_interface = ath9k_remove_interface,
2453 .config = ath9k_config,
2454 .config_interface = ath9k_config_interface,
2455 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2456 .sta_notify = ath9k_sta_notify,
2457 .conf_tx = ath9k_conf_tx,
8feceb67 2458 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2459 .set_key = ath9k_set_key,
8feceb67
VT		 2460 .get_tsf = ath9k_get_tsf,
2461 .reset_tsf = ath9k_reset_tsf,
4233df6b 2462 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2463};
2464
392dff83
BP		 2465static struct {
2466 u32 version;
2467 const char * name;
2468} ath_mac_bb_names[] = {
2469 { AR_SREV_VERSION_5416_PCI, "5416" },
2470 { AR_SREV_VERSION_5416_PCIE, "5418" },
2471 { AR_SREV_VERSION_9100, "9100" },
2472 { AR_SREV_VERSION_9160, "9160" },
2473 { AR_SREV_VERSION_9280, "9280" },
2474 { AR_SREV_VERSION_9285, "9285" }
2475};
2476
2477static struct {
2478 u16 version;
2479 const char * name;
2480} ath_rf_names[] = {
2481 { 0, "5133" },
2482 { AR_RAD5133_SREV_MAJOR, "5133" },
2483 { AR_RAD5122_SREV_MAJOR, "5122" },
2484 { AR_RAD2133_SREV_MAJOR, "2133" },
2485 { AR_RAD2122_SREV_MAJOR, "2122" }
2486};
2487
2488/*
2489 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2490 */
392dff83
BP		 2491static const char *
2492ath_mac_bb_name(u32 mac_bb_version)
2493{
2494 int i;
2495
2496 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2497 if (ath_mac_bb_names[i].version == mac_bb_version) {
2498 return ath_mac_bb_names[i].name;
2499 }
2500 }
2501
2502 return "????";
2503}
2504
2505/*
2506 * Return the RF name. "????" is returned if the RF is unknown.
2507 */
392dff83
BP		 2508static const char *
2509ath_rf_name(u16 rf_version)
2510{
2511 int i;
2512
2513 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2514 if (ath_rf_names[i].version == rf_version) {
2515 return ath_rf_names[i].name;
2516 }
2517 }
2518
2519 return "????";
2520}
2521
f078f209
LR		 2522static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2523{
2524 void __iomem *mem;
2525 struct ath_softc *sc;
2526 struct ieee80211_hw *hw;
f078f209
LR		 2527 u8 csz;
2528 u32 val;
2529 int ret = 0;
392dff83 2530 struct ath_hal *ah;
f078f209
LR		 2531
2532 if (pci_enable_device(pdev))
2533 return -EIO;
2534
97b777db
LR		 2535 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2536
2537 if (ret) {
1d450cfc 2538 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2539 goto bad;
2540 }
2541
2542 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2543
2544 if (ret) {
2545 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2546 "DMA enable failed\n");
f078f209
LR		 2547 goto bad;
2548 }
2549
2550 /*
2551 * Cache line size is used to size and align various
2552 * structures used to communicate with the hardware.
2553 */
2554 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2555 if (csz == 0) {
2556 /*
2557 * Linux 2.4.18 (at least) writes the cache line size
2558 * register as a 16-bit wide register which is wrong.
2559 * We must have this setup properly for rx buffer
2560 * DMA to work so force a reasonable value here if it
2561 * comes up zero.
2562 */
2563 csz = L1_CACHE_BYTES / sizeof(u32);
2564 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2565 }
2566 /*
2567 * The default setting of latency timer yields poor results,
2568 * set it to the value used by other systems. It may be worth
2569 * tweaking this setting more.
2570 */
2571 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2572
2573 pci_set_master(pdev);
2574
2575 /*
2576 * Disable the RETRY_TIMEOUT register (0x41) to keep
2577 * PCI Tx retries from interfering with C3 CPU state.
2578 */
2579 pci_read_config_dword(pdev, 0x40, &val);
2580 if ((val & 0x0000ff00) != 0)
2581 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2582
2583 ret = pci_request_region(pdev, 0, "ath9k");
2584 if (ret) {
2585 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2586 ret = -ENODEV;
2587 goto bad;
2588 }
2589
2590 mem = pci_iomap(pdev, 0, 0);
2591 if (!mem) {
2592 printk(KERN_ERR "PCI memory map error\n") ;
2593 ret = -EIO;
2594 goto bad1;
2595 }
2596
2597 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2598 if (hw == NULL) {
2599 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2600 goto bad2;
2601 }
2602
f078f209
LR		 2603 SET_IEEE80211_DEV(hw, &pdev->dev);
2604 pci_set_drvdata(pdev, hw);
2605
2606 sc = hw->priv;
2607 sc->hw = hw;
2608 sc->pdev = pdev;
2609 sc->mem = mem;
2610
2611 if (ath_attach(id->device, sc) != 0) {
2612 ret = -ENODEV;
2613 goto bad3;
2614 }
2615
2616 /* setup interrupt service routine */
2617
2618 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2619 printk(KERN_ERR "%s: request_irq failed\n",
2620 wiphy_name(hw->wiphy));
2621 ret = -EIO;
2622 goto bad4;
2623 }
2624
392dff83
BP		 2625 ah = sc->sc_ah;
2626 printk(KERN_INFO
2627 "%s: Atheros AR%s MAC/BB Rev:%x "
2628 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2629 wiphy_name(hw->wiphy),
392dff83
BP		 2630 ath_mac_bb_name(ah->ah_macVersion),
2631 ah->ah_macRev,
2632 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2633 ah->ah_phyRev,
f078f209
LR		 2634 (unsigned long)mem, pdev->irq);
2635
2636 return 0;
2637bad4:
2638 ath_detach(sc);
2639bad3:
2640 ieee80211_free_hw(hw);
2641bad2:
2642 pci_iounmap(pdev, mem);
2643bad1:
2644 pci_release_region(pdev, 0);
2645bad:
2646 pci_disable_device(pdev);
2647 return ret;
2648}
2649
2650static void ath_pci_remove(struct pci_dev *pdev)
2651{
2652 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2653 struct ath_softc *sc = hw->priv;
2654
f078f209 2655 ath_detach(sc);
9c84b797
S		 2656 if (pdev->irq)
2657 free_irq(pdev->irq, sc);
f078f209
LR		 2658 pci_iounmap(pdev, sc->mem);
2659 pci_release_region(pdev, 0);
2660 pci_disable_device(pdev);
2661 ieee80211_free_hw(hw);
2662}
2663
2664#ifdef CONFIG_PM
2665
2666static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2667{
c83be688
VT		 2668 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2669 struct ath_softc *sc = hw->priv;
2670
2671 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2672
e97275cb 2673#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2674 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2675 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2676#endif
2677
f078f209
LR		 2678 pci_save_state(pdev);
2679 pci_disable_device(pdev);
2680 pci_set_power_state(pdev, 3);
2681
2682 return 0;
2683}
2684
2685static int ath_pci_resume(struct pci_dev *pdev)
2686{
c83be688
VT		 2687 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2688 struct ath_softc *sc = hw->priv;
f078f209
LR		 2689 u32 val;
2690 int err;
2691
2692 err = pci_enable_device(pdev);
2693 if (err)
2694 return err;
2695 pci_restore_state(pdev);
2696 /*
2697 * Suspend/Resume resets the PCI configuration space, so we have to
2698 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2699 * PCI Tx retries from interfering with C3 CPU state
2700 */
2701 pci_read_config_dword(pdev, 0x40, &val);
2702 if ((val & 0x0000ff00) != 0)
2703 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2704
c83be688
VT		 2705 /* Enable LED */
2706 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2707 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2708 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2709
e97275cb 2710#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2711 /*
2712 * check the h/w rfkill state on resume
2713 * and start the rfkill poll timer
2714 */
2715 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2716 queue_delayed_work(sc->hw->workqueue,
2717 &sc->rf_kill.rfkill_poll, 0);
2718#endif
2719
f078f209
LR		 2720 return 0;
2721}
2722
2723#endif /* CONFIG_PM */
2724
2725MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2726
2727static struct pci_driver ath_pci_driver = {
2728 .name = "ath9k",
2729 .id_table = ath_pci_id_table,
2730 .probe = ath_pci_probe,
2731 .remove = ath_pci_remove,
2732#ifdef CONFIG_PM
2733 .suspend = ath_pci_suspend,
2734 .resume = ath_pci_resume,
2735#endif /* CONFIG_PM */
2736};
2737
2738static int __init init_ath_pci(void)
2739{
ca8a8560
VT		 2740 int error;
2741
f078f209
LR		 2742 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2743
ca8a8560
VT		 2744 /* Register rate control algorithm */
2745 error = ath_rate_control_register();
2746 if (error != 0) {
2747 printk(KERN_ERR
2748 "Unable to register rate control algorithm: %d\n",
2749 error);
2750 ath_rate_control_unregister();
2751 return error;
2752 }
2753
f078f209
LR		 2754 if (pci_register_driver(&ath_pci_driver) < 0) {
2755 printk(KERN_ERR
2756 "ath_pci: No devices found, driver not installed.\n");
ca8a8560 2757 ath_rate_control_unregister();
f078f209
LR		 2758 pci_unregister_driver(&ath_pci_driver);
2759 return -ENODEV;
2760 }
2761
2762 return 0;
2763}
2764module_init(init_ath_pci);
2765
2766static void __exit exit_ath_pci(void)
2767{
ca8a8560 2768 ath_rate_control_unregister();
f078f209 2769 pci_unregister_driver(&ath_pci_driver);
04bd4638 2770 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2771}
2772module_exit(exit_ath_pci);
Linux kernel - Deliverables
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