mac80211/drivers: rewrite the rate control API
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
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1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/* mac80211 and PCI callbacks */
18
19#include <linux/nl80211.h>
20#include "core.h"
21
22#define ATH_PCI_VERSION "0.1"
23
24#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
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25
26static char *dev_info = "ath9k";
27
28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static struct pci_device_id ath_pci_id_table[] __devinitdata = {
34 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
36 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
37 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
38 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
39 { 0 }
40};
41
42static int ath_get_channel(struct ath_softc *sc,
43 struct ieee80211_channel *chan)
44{
45 int i;
46
47 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
48 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
49 return i;
50 }
51
52 return -1;
53}
54
55static u32 ath_get_extchanmode(struct ath_softc *sc,
56 struct ieee80211_channel *chan)
57{
58 u32 chanmode = 0;
59 u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
60 enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
61
62 switch (chan->band) {
63 case IEEE80211_BAND_2GHZ:
d9fe60de 64 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
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LR
65 (tx_chan_width == ATH9K_HT_MACMODE_20))
66 chanmode = CHANNEL_G_HT20;
d9fe60de 67 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
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68 (tx_chan_width == ATH9K_HT_MACMODE_2040))
69 chanmode = CHANNEL_G_HT40PLUS;
d9fe60de 70 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
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71 (tx_chan_width == ATH9K_HT_MACMODE_2040))
72 chanmode = CHANNEL_G_HT40MINUS;
73 break;
74 case IEEE80211_BAND_5GHZ:
d9fe60de 75 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
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76 (tx_chan_width == ATH9K_HT_MACMODE_20))
77 chanmode = CHANNEL_A_HT20;
d9fe60de 78 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
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79 (tx_chan_width == ATH9K_HT_MACMODE_2040))
80 chanmode = CHANNEL_A_HT40PLUS;
d9fe60de 81 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
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82 (tx_chan_width == ATH9K_HT_MACMODE_2040))
83 chanmode = CHANNEL_A_HT40MINUS;
84 break;
85 default:
86 break;
87 }
88
89 return chanmode;
90}
91
92
93static int ath_setkey_tkip(struct ath_softc *sc,
94 struct ieee80211_key_conf *key,
95 struct ath9k_keyval *hk,
96 const u8 *addr)
97{
98 u8 *key_rxmic = NULL;
99 u8 *key_txmic = NULL;
100
101 key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
102 key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
103
104 if (addr == NULL) {
105 /* Group key installation */
106 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
107 return ath_keyset(sc, key->keyidx, hk, addr);
108 }
109 if (!sc->sc_splitmic) {
110 /*
111 * data key goes at first index,
112 * the hal handles the MIC keys at index+64.
113 */
114 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
115 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
116 return ath_keyset(sc, key->keyidx, hk, addr);
117 }
118 /*
119 * TX key goes at first index, RX key at +32.
120 * The hal handles the MIC keys at index+64.
121 */
122 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
123 if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
124 /* Txmic entry failed. No need to proceed further */
125 DPRINTF(sc, ATH_DBG_KEYCACHE,
126 "%s Setting TX MIC Key Failed\n", __func__);
127 return 0;
128 }
129
130 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
131 /* XXX delete tx key on failure? */
132 return ath_keyset(sc, key->keyidx+32, hk, addr);
133}
134
135static int ath_key_config(struct ath_softc *sc,
136 const u8 *addr,
137 struct ieee80211_key_conf *key)
138{
139 struct ieee80211_vif *vif;
140 struct ath9k_keyval hk;
141 const u8 *mac = NULL;
142 int ret = 0;
05c914fe 143 enum nl80211_iftype opmode;
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144
145 memset(&hk, 0, sizeof(hk));
146
147 switch (key->alg) {
148 case ALG_WEP:
149 hk.kv_type = ATH9K_CIPHER_WEP;
150 break;
151 case ALG_TKIP:
152 hk.kv_type = ATH9K_CIPHER_TKIP;
153 break;
154 case ALG_CCMP:
155 hk.kv_type = ATH9K_CIPHER_AES_CCM;
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 hk.kv_len = key->keylen;
162 memcpy(hk.kv_val, key->key, key->keylen);
163
164 if (!sc->sc_vaps[0])
165 return -EIO;
166
167 vif = sc->sc_vaps[0]->av_if_data;
168 opmode = vif->type;
169
170 /*
171 * Strategy:
172 * For _M_STA mc tx, we will not setup a key at all since we never
173 * tx mc.
174 * _M_STA mc rx, we will use the keyID.
175 * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
176 * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
177 * peer node. BUT we will plumb a cleartext key so that we can do
178 * perSta default key table lookup in software.
179 */
180 if (is_broadcast_ether_addr(addr)) {
181 switch (opmode) {
05c914fe 182 case NL80211_IFTYPE_STATION:
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183 /* default key: could be group WPA key
184 * or could be static WEP key */
185 mac = NULL;
186 break;
05c914fe 187 case NL80211_IFTYPE_ADHOC:
f078f209 188 break;
05c914fe 189 case NL80211_IFTYPE_AP:
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190 break;
191 default:
192 ASSERT(0);
193 break;
194 }
195 } else {
196 mac = addr;
197 }
198
199 if (key->alg == ALG_TKIP)
200 ret = ath_setkey_tkip(sc, key, &hk, mac);
201 else
202 ret = ath_keyset(sc, key->keyidx, &hk, mac);
203
204 if (!ret)
205 return -EIO;
206
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207 return 0;
208}
209
210static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
211{
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212 int freeslot;
213
ff9b662d 214 freeslot = (key->keyidx >= 4) ? 1 : 0;
f078f209 215 ath_key_reset(sc, key->keyidx, freeslot);
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216}
217
d9fe60de 218static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 219{
60653678
S
220#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
221#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 222
d9fe60de
JB
223 ht_info->ht_supported = true;
224 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
225 IEEE80211_HT_CAP_SM_PS |
226 IEEE80211_HT_CAP_SGI_40 |
227 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 228
60653678
S
229 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
230 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB
231 /* set up supported mcs set */
232 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
233 ht_info->mcs.rx_mask[0] = 0xff;
234 ht_info->mcs.rx_mask[1] = 0xff;
235 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
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LR
236}
237
238static int ath_rate2idx(struct ath_softc *sc, int rate)
239{
240 int i = 0, cur_band, n_rates;
241 struct ieee80211_hw *hw = sc->hw;
242
243 cur_band = hw->conf.channel->band;
244 n_rates = sc->sbands[cur_band].n_bitrates;
245
246 for (i = 0; i < n_rates; i++) {
247 if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
248 break;
249 }
250
251 /*
252 * NB:mac80211 validates rx rate index against the supported legacy rate
253 * index only (should be done against ht rates also), return the highest
254 * legacy rate index for rx rate which does not match any one of the
255 * supported basic and extended rates to make mac80211 happy.
256 * The following hack will be cleaned up once the issue with
257 * the rx rate index validation in mac80211 is fixed.
258 */
259 if (i == n_rates)
260 return n_rates - 1;
261 return i;
262}
263
264static void ath9k_rx_prepare(struct ath_softc *sc,
265 struct sk_buff *skb,
266 struct ath_recv_status *status,
267 struct ieee80211_rx_status *rx_status)
268{
269 struct ieee80211_hw *hw = sc->hw;
270 struct ieee80211_channel *curchan = hw->conf.channel;
271
272 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
273
274 rx_status->mactime = status->tsf;
275 rx_status->band = curchan->band;
276 rx_status->freq = curchan->center_freq;
6f255425 277 rx_status->noise = sc->sc_ani.sc_noise_floor;
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LR
278 rx_status->signal = rx_status->noise + status->rssi;
279 rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
280 rx_status->antenna = status->antenna;
6f255425 281
c49d154a
LR
282 /* at 45 you will be able to use MCS 15 reliably. A more elaborate
283 * scheme can be used here but it requires tables of SNR/throughput for
284 * each possible mode used. */
285 rx_status->qual = status->rssi * 100 / 45;
286
287 /* rssi can be more than 45 though, anything above that
288 * should be considered at 100% */
289 if (rx_status->qual > 100)
290 rx_status->qual = 100;
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291
292 if (status->flags & ATH_RX_MIC_ERROR)
293 rx_status->flag |= RX_FLAG_MMIC_ERROR;
294 if (status->flags & ATH_RX_FCS_ERROR)
295 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
296
297 rx_status->flag |= RX_FLAG_TSFT;
298}
299
300static u8 parse_mpdudensity(u8 mpdudensity)
301{
302 /*
303 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
304 * 0 for no restriction
305 * 1 for 1/4 us
306 * 2 for 1/2 us
307 * 3 for 1 us
308 * 4 for 2 us
309 * 5 for 4 us
310 * 6 for 8 us
311 * 7 for 16 us
312 */
313 switch (mpdudensity) {
314 case 0:
315 return 0;
316 case 1:
317 case 2:
318 case 3:
319 /* Our lower layer calculations limit our precision to
320 1 microsecond */
321 return 1;
322 case 4:
323 return 2;
324 case 5:
325 return 4;
326 case 6:
327 return 8;
328 case 7:
329 return 16;
330 default:
331 return 0;
332 }
333}
334
8feceb67
VT
335static void ath9k_ht_conf(struct ath_softc *sc,
336 struct ieee80211_bss_conf *bss_conf)
f078f209 337{
8feceb67 338 struct ath_ht_info *ht_info = &sc->sc_ht_info;
f078f209 339
ae5eb026
JB
340 if (sc->hw->conf.ht.enabled) {
341 ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
342
343 if (bss_conf->ht.width_40_ok)
8feceb67
VT
344 ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
345 else
346 ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
f078f209 347
8feceb67 348 ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
f078f209 349 }
f078f209
LR
350}
351
8feceb67
VT
352static void ath9k_bss_assoc_info(struct ath_softc *sc,
353 struct ieee80211_bss_conf *bss_conf)
f078f209 354{
8feceb67
VT
355 struct ieee80211_hw *hw = sc->hw;
356 struct ieee80211_channel *curchan = hw->conf.channel;
357 struct ath_vap *avp;
358 int pos;
f078f209 359
8feceb67
VT
360 if (bss_conf->assoc) {
361 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
362 __func__,
363 bss_conf->aid);
f078f209 364
8feceb67
VT
365 avp = sc->sc_vaps[0];
366 if (avp == NULL) {
367 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
368 __func__);
369 return;
370 }
f078f209 371
8feceb67
VT
372 /* New association, store aid */
373 if (avp->av_opmode == ATH9K_M_STA) {
374 sc->sc_curaid = bss_conf->aid;
375 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
376 sc->sc_curaid);
377 }
f078f209 378
8feceb67
VT
379 /* Configure the beacon */
380 ath_beacon_config(sc, 0);
381 sc->sc_flags |= SC_OP_BEACONS;
f078f209 382
8feceb67
VT
383 /* Reset rssi stats */
384 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
385 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
386 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
387 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 388
8feceb67 389 /* Update chainmask */
ae5eb026 390 ath_update_chainmask(sc, hw->conf.ht.enabled);
f078f209 391
f078f209 392 DPRINTF(sc, ATH_DBG_CONFIG,
e174961c 393 "%s: bssid %pM aid 0x%x\n",
8feceb67 394 __func__,
e174961c 395 sc->sc_curbssid, sc->sc_curaid);
f078f209 396
8feceb67
VT
397 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
398 __func__,
399 curchan->center_freq);
f078f209 400
8feceb67
VT
401 pos = ath_get_channel(sc, curchan);
402 if (pos == -1) {
403 DPRINTF(sc, ATH_DBG_FATAL,
404 "%s: Invalid channel\n", __func__);
405 return;
406 }
f078f209 407
ae5eb026 408 if (hw->conf.ht.enabled)
8feceb67
VT
409 sc->sc_ah->ah_channels[pos].chanmode =
410 ath_get_extchanmode(sc, curchan);
411 else
412 sc->sc_ah->ah_channels[pos].chanmode =
413 (curchan->band == IEEE80211_BAND_2GHZ) ?
414 CHANNEL_G : CHANNEL_A;
f078f209 415
8feceb67
VT
416 /* set h/w channel */
417 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
418 DPRINTF(sc, ATH_DBG_FATAL,
419 "%s: Unable to set channel\n",
420 __func__);
f078f209 421
8feceb67
VT
422 ath_rate_newstate(sc, avp);
423 /* Update ratectrl about the new state */
424 ath_rc_node_update(hw, avp->rc_node);
6f255425
LR
425
426 /* Start ANI */
427 mod_timer(&sc->sc_ani.timer,
428 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
429
8feceb67
VT
430 } else {
431 DPRINTF(sc, ATH_DBG_CONFIG,
432 "%s: Bss Info DISSOC\n", __func__);
433 sc->sc_curaid = 0;
f078f209 434 }
8feceb67 435}
f078f209 436
8feceb67
VT
437void ath_get_beaconconfig(struct ath_softc *sc,
438 int if_id,
439 struct ath_beacon_config *conf)
440{
441 struct ieee80211_hw *hw = sc->hw;
f078f209 442
8feceb67 443 /* fill in beacon config data */
f078f209 444
8feceb67
VT
445 conf->beacon_interval = hw->conf.beacon_int;
446 conf->listen_interval = 100;
447 conf->dtim_count = 1;
448 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
f078f209
LR
449}
450
8feceb67
VT
451void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
452 struct ath_xmit_status *tx_status, struct ath_node *an)
f078f209 453{
8feceb67
VT
454 struct ieee80211_hw *hw = sc->hw;
455 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
f078f209 456
8feceb67
VT
457 DPRINTF(sc, ATH_DBG_XMIT,
458 "%s: TX complete: skb: %p\n", __func__, skb);
f078f209 459
e6a9854b 460 ieee80211_tx_info_clear_status(tx_info);
8feceb67
VT
461 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
462 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
e6a9854b
JB
463 /* free driver's private data area of tx_info, XXX: HACK! */
464 if (tx_info->control.vif != NULL)
465 kfree(tx_info->control.vif);
466 tx_info->control.vif = NULL;
f078f209
LR
467 }
468
8feceb67
VT
469 if (tx_status->flags & ATH_TX_BAR) {
470 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
471 tx_status->flags &= ~ATH_TX_BAR;
472 }
f078f209 473
e6a9854b 474 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
8feceb67
VT
475 /* Frame was ACKed */
476 tx_info->flags |= IEEE80211_TX_STAT_ACK;
f078f209
LR
477 }
478
e6a9854b 479 tx_info->status.rates[0].count = tx_status->retries + 1;
f078f209 480
8feceb67
VT
481 ieee80211_tx_status(hw, skb);
482 if (an)
483 ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
f078f209
LR
484}
485
8feceb67
VT
486int _ath_rx_indicate(struct ath_softc *sc,
487 struct sk_buff *skb,
488 struct ath_recv_status *status,
489 u16 keyix)
f078f209 490{
8feceb67
VT
491 struct ieee80211_hw *hw = sc->hw;
492 struct ath_node *an = NULL;
493 struct ieee80211_rx_status rx_status;
494 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
495 int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
496 int padsize;
497 enum ATH_RX_TYPE st;
f078f209 498
8feceb67
VT
499 /* see if any padding is done by the hw and remove it */
500 if (hdrlen & 3) {
501 padsize = hdrlen % 4;
502 memmove(skb->data + padsize, skb->data, hdrlen);
503 skb_pull(skb, padsize);
f078f209
LR
504 }
505
8feceb67
VT
506 /* Prepare rx status */
507 ath9k_rx_prepare(sc, skb, status, &rx_status);
86b89eed 508
8feceb67
VT
509 if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
510 !(status->flags & ATH_RX_DECRYPT_ERROR)) {
511 rx_status.flag |= RX_FLAG_DECRYPTED;
512 } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
513 && !(status->flags & ATH_RX_DECRYPT_ERROR)
514 && skb->len >= hdrlen + 4) {
515 keyix = skb->data[hdrlen + 3] >> 6;
86b89eed 516
8feceb67
VT
517 if (test_bit(keyix, sc->sc_keymap))
518 rx_status.flag |= RX_FLAG_DECRYPTED;
519 }
f078f209 520
8feceb67
VT
521 spin_lock_bh(&sc->node_lock);
522 an = ath_node_find(sc, hdr->addr2);
523 spin_unlock_bh(&sc->node_lock);
524
525 if (an) {
526 ath_rx_input(sc, an,
8feceb67
VT
527 skb, status, &st);
528 }
529 if (!an || (st != ATH_RX_CONSUMED))
530 __ieee80211_rx(hw, skb, &rx_status);
f078f209
LR
531
532 return 0;
533}
534
8feceb67
VT
535int ath_rx_subframe(struct ath_node *an,
536 struct sk_buff *skb,
537 struct ath_recv_status *status)
f078f209 538{
8feceb67
VT
539 struct ath_softc *sc = an->an_sc;
540 struct ieee80211_hw *hw = sc->hw;
541 struct ieee80211_rx_status rx_status;
f078f209 542
8feceb67
VT
543 /* Prepare rx status */
544 ath9k_rx_prepare(sc, skb, status, &rx_status);
545 if (!(status->flags & ATH_RX_DECRYPT_ERROR))
546 rx_status.flag |= RX_FLAG_DECRYPTED;
f078f209 547
8feceb67 548 __ieee80211_rx(hw, skb, &rx_status);
f078f209 549
8feceb67
VT
550 return 0;
551}
f078f209 552
8feceb67
VT
553/********************************/
554/* LED functions */
555/********************************/
f078f209 556
8feceb67
VT
557static void ath_led_brightness(struct led_classdev *led_cdev,
558 enum led_brightness brightness)
559{
560 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
561 struct ath_softc *sc = led->sc;
f078f209 562
8feceb67
VT
563 switch (brightness) {
564 case LED_OFF:
565 if (led->led_type == ATH_LED_ASSOC ||
566 led->led_type == ATH_LED_RADIO)
567 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
568 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
569 (led->led_type == ATH_LED_RADIO) ? 1 :
570 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
571 break;
572 case LED_FULL:
573 if (led->led_type == ATH_LED_ASSOC)
574 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
575 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
576 break;
577 default:
578 break;
f078f209 579 }
8feceb67 580}
f078f209 581
8feceb67
VT
582static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
583 char *trigger)
584{
585 int ret;
f078f209 586
8feceb67
VT
587 led->sc = sc;
588 led->led_cdev.name = led->name;
589 led->led_cdev.default_trigger = trigger;
590 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 591
8feceb67
VT
592 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
593 if (ret)
594 DPRINTF(sc, ATH_DBG_FATAL,
595 "Failed to register led:%s", led->name);
596 else
597 led->registered = 1;
598 return ret;
599}
f078f209 600
8feceb67
VT
601static void ath_unregister_led(struct ath_led *led)
602{
603 if (led->registered) {
604 led_classdev_unregister(&led->led_cdev);
605 led->registered = 0;
f078f209 606 }
f078f209
LR
607}
608
8feceb67 609static void ath_deinit_leds(struct ath_softc *sc)
f078f209 610{
8feceb67
VT
611 ath_unregister_led(&sc->assoc_led);
612 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
613 ath_unregister_led(&sc->tx_led);
614 ath_unregister_led(&sc->rx_led);
615 ath_unregister_led(&sc->radio_led);
616 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
617}
f078f209 618
8feceb67
VT
619static void ath_init_leds(struct ath_softc *sc)
620{
621 char *trigger;
622 int ret;
f078f209 623
8feceb67
VT
624 /* Configure gpio 1 for output */
625 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
626 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
627 /* LED off, active low */
628 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 629
8feceb67
VT
630 trigger = ieee80211_get_radio_led_name(sc->hw);
631 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
632 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
633 ret = ath_register_led(sc, &sc->radio_led, trigger);
634 sc->radio_led.led_type = ATH_LED_RADIO;
635 if (ret)
636 goto fail;
7dcfdcd9 637
8feceb67
VT
638 trigger = ieee80211_get_assoc_led_name(sc->hw);
639 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
640 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
641 ret = ath_register_led(sc, &sc->assoc_led, trigger);
642 sc->assoc_led.led_type = ATH_LED_ASSOC;
643 if (ret)
644 goto fail;
f078f209 645
8feceb67
VT
646 trigger = ieee80211_get_tx_led_name(sc->hw);
647 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
648 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
649 ret = ath_register_led(sc, &sc->tx_led, trigger);
650 sc->tx_led.led_type = ATH_LED_TX;
651 if (ret)
652 goto fail;
f078f209 653
8feceb67
VT
654 trigger = ieee80211_get_rx_led_name(sc->hw);
655 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
656 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
657 ret = ath_register_led(sc, &sc->rx_led, trigger);
658 sc->rx_led.led_type = ATH_LED_RX;
659 if (ret)
660 goto fail;
f078f209 661
8feceb67
VT
662 return;
663
664fail:
665 ath_deinit_leds(sc);
f078f209
LR
666}
667
500c064d
VT
668#ifdef CONFIG_RFKILL
669/*******************/
670/* Rfkill */
671/*******************/
672
673static void ath_radio_enable(struct ath_softc *sc)
674{
675 struct ath_hal *ah = sc->sc_ah;
676 int status;
677
678 spin_lock_bh(&sc->sc_resetlock);
679 if (!ath9k_hw_reset(ah, ah->ah_curchan,
680 sc->sc_ht_info.tx_chan_width,
681 sc->sc_tx_chainmask,
682 sc->sc_rx_chainmask,
683 sc->sc_ht_extprotspacing,
684 false, &status)) {
685 DPRINTF(sc, ATH_DBG_FATAL,
686 "%s: unable to reset channel %u (%uMhz) "
687 "flags 0x%x hal status %u\n", __func__,
688 ath9k_hw_mhz2ieee(ah,
689 ah->ah_curchan->channel,
690 ah->ah_curchan->channelFlags),
691 ah->ah_curchan->channel,
692 ah->ah_curchan->channelFlags, status);
693 }
694 spin_unlock_bh(&sc->sc_resetlock);
695
696 ath_update_txpow(sc);
697 if (ath_startrecv(sc) != 0) {
698 DPRINTF(sc, ATH_DBG_FATAL,
699 "%s: unable to restart recv logic\n", __func__);
700 return;
701 }
702
703 if (sc->sc_flags & SC_OP_BEACONS)
704 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
705
706 /* Re-Enable interrupts */
707 ath9k_hw_set_interrupts(ah, sc->sc_imask);
708
709 /* Enable LED */
710 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
711 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
712 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
713
714 ieee80211_wake_queues(sc->hw);
715}
716
717static void ath_radio_disable(struct ath_softc *sc)
718{
719 struct ath_hal *ah = sc->sc_ah;
720 int status;
721
722
723 ieee80211_stop_queues(sc->hw);
724
725 /* Disable LED */
726 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
727 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
728
729 /* Disable interrupts */
730 ath9k_hw_set_interrupts(ah, 0);
731
732 ath_draintxq(sc, false); /* clear pending tx frames */
733 ath_stoprecv(sc); /* turn off frame recv */
734 ath_flushrecv(sc); /* flush recv queue */
735
736 spin_lock_bh(&sc->sc_resetlock);
737 if (!ath9k_hw_reset(ah, ah->ah_curchan,
738 sc->sc_ht_info.tx_chan_width,
739 sc->sc_tx_chainmask,
740 sc->sc_rx_chainmask,
741 sc->sc_ht_extprotspacing,
742 false, &status)) {
743 DPRINTF(sc, ATH_DBG_FATAL,
744 "%s: unable to reset channel %u (%uMhz) "
745 "flags 0x%x hal status %u\n", __func__,
746 ath9k_hw_mhz2ieee(ah,
747 ah->ah_curchan->channel,
748 ah->ah_curchan->channelFlags),
749 ah->ah_curchan->channel,
750 ah->ah_curchan->channelFlags, status);
751 }
752 spin_unlock_bh(&sc->sc_resetlock);
753
754 ath9k_hw_phy_disable(ah);
755 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
756}
757
758static bool ath_is_rfkill_set(struct ath_softc *sc)
759{
760 struct ath_hal *ah = sc->sc_ah;
761
762 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
763 ah->ah_rfkill_polarity;
764}
765
766/* h/w rfkill poll function */
767static void ath_rfkill_poll(struct work_struct *work)
768{
769 struct ath_softc *sc = container_of(work, struct ath_softc,
770 rf_kill.rfkill_poll.work);
771 bool radio_on;
772
773 if (sc->sc_flags & SC_OP_INVALID)
774 return;
775
776 radio_on = !ath_is_rfkill_set(sc);
777
778 /*
779 * enable/disable radio only when there is a
780 * state change in RF switch
781 */
782 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
783 enum rfkill_state state;
784
785 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
786 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
787 : RFKILL_STATE_HARD_BLOCKED;
788 } else if (radio_on) {
789 ath_radio_enable(sc);
790 state = RFKILL_STATE_UNBLOCKED;
791 } else {
792 ath_radio_disable(sc);
793 state = RFKILL_STATE_HARD_BLOCKED;
794 }
795
796 if (state == RFKILL_STATE_HARD_BLOCKED)
797 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
798 else
799 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
800
801 rfkill_force_state(sc->rf_kill.rfkill, state);
802 }
803
804 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
805 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
806}
807
808/* s/w rfkill handler */
809static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
810{
811 struct ath_softc *sc = data;
812
813 switch (state) {
814 case RFKILL_STATE_SOFT_BLOCKED:
815 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
816 SC_OP_RFKILL_SW_BLOCKED)))
817 ath_radio_disable(sc);
818 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
819 return 0;
820 case RFKILL_STATE_UNBLOCKED:
821 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
822 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
823 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
824 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
825 "radio as it is disabled by h/w \n");
826 return -EPERM;
827 }
828 ath_radio_enable(sc);
829 }
830 return 0;
831 default:
832 return -EINVAL;
833 }
834}
835
836/* Init s/w rfkill */
837static int ath_init_sw_rfkill(struct ath_softc *sc)
838{
839 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
840 RFKILL_TYPE_WLAN);
841 if (!sc->rf_kill.rfkill) {
842 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
843 return -ENOMEM;
844 }
845
846 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
847 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
848 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
849 sc->rf_kill.rfkill->data = sc;
850 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
851 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
852 sc->rf_kill.rfkill->user_claim_unsupported = 1;
853
854 return 0;
855}
856
857/* Deinitialize rfkill */
858static void ath_deinit_rfkill(struct ath_softc *sc)
859{
860 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
861 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
862
863 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
864 rfkill_unregister(sc->rf_kill.rfkill);
865 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
866 sc->rf_kill.rfkill = NULL;
867 }
868}
869#endif /* CONFIG_RFKILL */
870
8feceb67 871static int ath_detach(struct ath_softc *sc)
f078f209 872{
8feceb67 873 struct ieee80211_hw *hw = sc->hw;
f078f209 874
8feceb67 875 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
f078f209 876
8feceb67
VT
877 /* Deinit LED control */
878 ath_deinit_leds(sc);
f078f209 879
500c064d
VT
880#ifdef CONFIG_RFKILL
881 /* deinit rfkill */
882 ath_deinit_rfkill(sc);
883#endif
884
8feceb67 885 /* Unregister hw */
f078f209 886
8feceb67 887 ieee80211_unregister_hw(hw);
f078f209 888
8feceb67
VT
889 /* unregister Rate control */
890 ath_rate_control_unregister();
f078f209 891
8feceb67 892 /* tx/rx cleanup */
f078f209 893
8feceb67
VT
894 ath_rx_cleanup(sc);
895 ath_tx_cleanup(sc);
f078f209 896
8feceb67 897 /* Deinit */
f078f209 898
8feceb67
VT
899 ath_deinit(sc);
900
901 return 0;
f078f209
LR
902}
903
8feceb67
VT
904static int ath_attach(u16 devid,
905 struct ath_softc *sc)
f078f209 906{
8feceb67
VT
907 struct ieee80211_hw *hw = sc->hw;
908 int error = 0;
f078f209 909
8feceb67 910 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
f078f209 911
8feceb67
VT
912 error = ath_init(devid, sc);
913 if (error != 0)
914 return error;
f078f209 915
8feceb67 916 /* Init nodes */
f078f209 917
8feceb67
VT
918 INIT_LIST_HEAD(&sc->node_list);
919 spin_lock_init(&sc->node_lock);
f078f209 920
8feceb67 921 /* get mac address from hardware and set in mac80211 */
f078f209 922
8feceb67 923 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 924
8feceb67 925 /* setup channels and rates */
f078f209 926
8feceb67
VT
927 sc->sbands[IEEE80211_BAND_2GHZ].channels =
928 sc->channels[IEEE80211_BAND_2GHZ];
929 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
930 sc->rates[IEEE80211_BAND_2GHZ];
931 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
f078f209 932
8feceb67
VT
933 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
934 /* Setup HT capabilities for 2.4Ghz*/
d9fe60de 935 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
f078f209 936
8feceb67
VT
937 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
938 &sc->sbands[IEEE80211_BAND_2GHZ];
f078f209 939
8feceb67
VT
940 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
941 sc->sbands[IEEE80211_BAND_5GHZ].channels =
942 sc->channels[IEEE80211_BAND_5GHZ];
943 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
944 sc->rates[IEEE80211_BAND_5GHZ];
945 sc->sbands[IEEE80211_BAND_5GHZ].band =
946 IEEE80211_BAND_5GHZ;
f078f209 947
8feceb67
VT
948 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
949 /* Setup HT capabilities for 5Ghz*/
d9fe60de 950 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
f078f209 951
8feceb67
VT
952 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
953 &sc->sbands[IEEE80211_BAND_5GHZ];
954 }
f078f209 955
8feceb67 956 /* FIXME: Have to figure out proper hw init values later */
f078f209 957
8feceb67
VT
958 hw->queues = 4;
959 hw->ampdu_queues = 1;
f078f209 960
8feceb67
VT
961 /* Register rate control */
962 hw->rate_control_algorithm = "ath9k_rate_control";
963 error = ath_rate_control_register();
964 if (error != 0) {
965 DPRINTF(sc, ATH_DBG_FATAL,
966 "%s: Unable to register rate control "
967 "algorithm:%d\n", __func__, error);
968 ath_rate_control_unregister();
969 goto bad;
970 }
f078f209 971
8feceb67
VT
972 error = ieee80211_register_hw(hw);
973 if (error != 0) {
974 ath_rate_control_unregister();
975 goto bad;
f078f209 976 }
8feceb67
VT
977
978 /* Initialize LED control */
979 ath_init_leds(sc);
980
500c064d
VT
981#ifdef CONFIG_RFKILL
982 /* Initialze h/w Rfkill */
983 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
984 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
985
986 /* Initialize s/w rfkill */
987 if (ath_init_sw_rfkill(sc))
988 goto detach;
989#endif
990
8feceb67
VT
991 /* initialize tx/rx engine */
992
993 error = ath_tx_init(sc, ATH_TXBUF);
994 if (error != 0)
995 goto detach;
996
997 error = ath_rx_init(sc, ATH_RXBUF);
998 if (error != 0)
999 goto detach;
1000
1001 return 0;
1002detach:
1003 ath_detach(sc);
1004bad:
1005 return error;
f078f209
LR
1006}
1007
8feceb67 1008static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR
1009{
1010 struct ath_softc *sc = hw->priv;
8feceb67
VT
1011 struct ieee80211_channel *curchan = hw->conf.channel;
1012 int error = 0, pos;
f078f209 1013
8feceb67
VT
1014 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
1015 "initial channel: %d MHz\n", __func__, curchan->center_freq);
f078f209 1016
8feceb67 1017 /* setup initial channel */
f078f209 1018
8feceb67
VT
1019 pos = ath_get_channel(sc, curchan);
1020 if (pos == -1) {
1021 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1022 return -EINVAL;
f078f209
LR
1023 }
1024
8feceb67
VT
1025 sc->sc_ah->ah_channels[pos].chanmode =
1026 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1027
1028 /* open ath_dev */
1029 error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
1030 if (error) {
1031 DPRINTF(sc, ATH_DBG_FATAL,
1032 "%s: Unable to complete ath_open\n", __func__);
1033 return error;
f078f209 1034 }
8feceb67 1035
500c064d
VT
1036#ifdef CONFIG_RFKILL
1037 /* Start rfkill polling */
1038 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1039 queue_delayed_work(sc->hw->workqueue,
1040 &sc->rf_kill.rfkill_poll, 0);
1041
1042 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1043 if (rfkill_register(sc->rf_kill.rfkill)) {
1044 DPRINTF(sc, ATH_DBG_FATAL,
1045 "Unable to register rfkill\n");
1046 rfkill_free(sc->rf_kill.rfkill);
1047
1048 /* Deinitialize the device */
1049 if (sc->pdev->irq)
1050 free_irq(sc->pdev->irq, sc);
1051 ath_detach(sc);
1052 pci_iounmap(sc->pdev, sc->mem);
1053 pci_release_region(sc->pdev, 0);
1054 pci_disable_device(sc->pdev);
1055 ieee80211_free_hw(hw);
1056 return -EIO;
1057 } else {
1058 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1059 }
1060 }
1061#endif
1062
8feceb67
VT
1063 ieee80211_wake_queues(hw);
1064 return 0;
f078f209
LR
1065}
1066
8feceb67
VT
1067static int ath9k_tx(struct ieee80211_hw *hw,
1068 struct sk_buff *skb)
f078f209 1069{
f078f209 1070 struct ath_softc *sc = hw->priv;
8feceb67
VT
1071 int hdrlen, padsize;
1072 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1073
8feceb67
VT
1074 /*
1075 * As a temporary workaround, assign seq# here; this will likely need
1076 * to be cleaned up to work better with Beacon transmission and virtual
1077 * BSSes.
1078 */
1079 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1080 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1081 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1082 sc->seq_no += 0x10;
1083 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1084 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1085 }
f078f209 1086
8feceb67
VT
1087 /* Add the padding after the header if this is not already done */
1088 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1089 if (hdrlen & 3) {
1090 padsize = hdrlen % 4;
1091 if (skb_headroom(skb) < padsize)
1092 return -1;
1093 skb_push(skb, padsize);
1094 memmove(skb->data, skb->data + padsize, hdrlen);
1095 }
1096
1097 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
1098 __func__,
1099 skb);
1100
1101 if (ath_tx_start(sc, skb) != 0) {
1102 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
1103 dev_kfree_skb_any(skb);
1104 /* FIXME: Check for proper return value from ATH_DEV */
1105 return 0;
1106 }
1107
1108 return 0;
f078f209
LR
1109}
1110
8feceb67 1111static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR
1112{
1113 struct ath_softc *sc = hw->priv;
8feceb67 1114 int error;
f078f209 1115
8feceb67
VT
1116 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
1117
1118 error = ath_suspend(sc);
1119 if (error)
1120 DPRINTF(sc, ATH_DBG_CONFIG,
1121 "%s: Device is no longer present\n", __func__);
1122
1123 ieee80211_stop_queues(hw);
500c064d
VT
1124
1125#ifdef CONFIG_RFKILL
1126 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1127 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1128#endif
f078f209
LR
1129}
1130
8feceb67
VT
1131static int ath9k_add_interface(struct ieee80211_hw *hw,
1132 struct ieee80211_if_init_conf *conf)
f078f209
LR
1133{
1134 struct ath_softc *sc = hw->priv;
8feceb67 1135 int error, ic_opmode = 0;
f078f209 1136
8feceb67
VT
1137 /* Support only vap for now */
1138
1139 if (sc->sc_nvaps)
1140 return -ENOBUFS;
1141
1142 switch (conf->type) {
05c914fe 1143 case NL80211_IFTYPE_STATION:
8feceb67 1144 ic_opmode = ATH9K_M_STA;
f078f209 1145 break;
05c914fe 1146 case NL80211_IFTYPE_ADHOC:
8feceb67 1147 ic_opmode = ATH9K_M_IBSS;
f078f209 1148 break;
05c914fe 1149 case NL80211_IFTYPE_AP:
8feceb67 1150 ic_opmode = ATH9K_M_HOSTAP;
f078f209
LR
1151 break;
1152 default:
1153 DPRINTF(sc, ATH_DBG_FATAL,
8feceb67
VT
1154 "%s: Interface type %d not yet supported\n",
1155 __func__, conf->type);
1156 return -EOPNOTSUPP;
f078f209
LR
1157 }
1158
8feceb67
VT
1159 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
1160 __func__,
1161 ic_opmode);
1162
1163 error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
1164 if (error) {
1165 DPRINTF(sc, ATH_DBG_FATAL,
1166 "%s: Unable to attach vap, error: %d\n",
1167 __func__, error);
1168 return error;
1169 }
1170
6f255425
LR
1171 if (conf->type == NL80211_IFTYPE_AP) {
1172 /* TODO: is this a suitable place to start ANI for AP mode? */
1173 /* Start ANI */
1174 mod_timer(&sc->sc_ani.timer,
1175 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
1176 }
1177
8feceb67 1178 return 0;
f078f209
LR
1179}
1180
8feceb67
VT
1181static void ath9k_remove_interface(struct ieee80211_hw *hw,
1182 struct ieee80211_if_init_conf *conf)
f078f209 1183{
8feceb67
VT
1184 struct ath_softc *sc = hw->priv;
1185 struct ath_vap *avp;
1186 int error;
f078f209 1187
8feceb67 1188 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
f078f209 1189
8feceb67
VT
1190 avp = sc->sc_vaps[0];
1191 if (avp == NULL) {
1192 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
1193 __func__);
1194 return;
f078f209
LR
1195 }
1196
8feceb67
VT
1197#ifdef CONFIG_SLOW_ANT_DIV
1198 ath_slow_ant_div_stop(&sc->sc_antdiv);
1199#endif
6f255425
LR
1200 /* Stop ANI */
1201 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 1202
8feceb67
VT
1203 /* Update ratectrl */
1204 ath_rate_newstate(sc, avp);
1205
1206 /* Reclaim beacon resources */
1207 if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
1208 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
1209 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
1210 ath_beacon_return(sc, avp);
580f0b8a 1211 }
f078f209 1212
8feceb67
VT
1213 /* Set interrupt mask */
1214 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1215 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
1216 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1217
8feceb67
VT
1218 error = ath_vap_detach(sc, 0);
1219 if (error)
1220 DPRINTF(sc, ATH_DBG_FATAL,
1221 "%s: Unable to detach vap, error: %d\n",
1222 __func__, error);
f078f209
LR
1223}
1224
e8975581 1225static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1226{
8feceb67
VT
1227 struct ath_softc *sc = hw->priv;
1228 struct ieee80211_channel *curchan = hw->conf.channel;
e8975581 1229 struct ieee80211_conf *conf = &hw->conf;
8feceb67 1230 int pos;
f078f209 1231
8feceb67
VT
1232 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
1233 __func__,
1234 curchan->center_freq);
f078f209 1235
ae5eb026
JB
1236 /* Update chainmask */
1237 ath_update_chainmask(sc, conf->ht.enabled);
1238
8feceb67
VT
1239 pos = ath_get_channel(sc, curchan);
1240 if (pos == -1) {
1241 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1242 return -EINVAL;
f078f209 1243 }
f078f209 1244
8feceb67
VT
1245 sc->sc_ah->ah_channels[pos].chanmode =
1246 (curchan->band == IEEE80211_BAND_2GHZ) ?
1247 CHANNEL_G : CHANNEL_A;
f078f209 1248
ae5eb026 1249 if (sc->sc_curaid && hw->conf.ht.enabled)
8feceb67
VT
1250 sc->sc_ah->ah_channels[pos].chanmode =
1251 ath_get_extchanmode(sc, curchan);
f078f209 1252
8feceb67 1253 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 1254
8feceb67
VT
1255 /* set h/w channel */
1256 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
1257 DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
1258 __func__);
f078f209
LR
1259
1260 return 0;
1261}
1262
8feceb67
VT
1263static int ath9k_config_interface(struct ieee80211_hw *hw,
1264 struct ieee80211_vif *vif,
1265 struct ieee80211_if_conf *conf)
c83be688 1266{
8feceb67
VT
1267 struct ath_softc *sc = hw->priv;
1268 struct ath_hal *ah = sc->sc_ah;
1269 struct ath_vap *avp;
1270 u32 rfilt = 0;
1271 int error, i;
c83be688 1272
8feceb67
VT
1273 avp = sc->sc_vaps[0];
1274 if (avp == NULL) {
1275 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
1276 __func__);
1277 return -EINVAL;
c83be688 1278 }
c83be688 1279
8feceb67
VT
1280 /* TODO: Need to decide which hw opmode to use for multi-interface
1281 * cases */
05c914fe 1282 if (vif->type == NL80211_IFTYPE_AP &&
8feceb67
VT
1283 ah->ah_opmode != ATH9K_M_HOSTAP) {
1284 ah->ah_opmode = ATH9K_M_HOSTAP;
1285 ath9k_hw_setopmode(ah);
1286 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
1287 /* Request full reset to get hw opmode changed properly */
1288 sc->sc_flags |= SC_OP_FULL_RESET;
1289 }
c83be688 1290
8feceb67
VT
1291 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
1292 !is_zero_ether_addr(conf->bssid)) {
1293 switch (vif->type) {
05c914fe
JB
1294 case NL80211_IFTYPE_STATION:
1295 case NL80211_IFTYPE_ADHOC:
8feceb67
VT
1296 /* Update ratectrl about the new state */
1297 ath_rate_newstate(sc, avp);
c83be688 1298
8feceb67
VT
1299 /* Set BSSID */
1300 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
1301 sc->sc_curaid = 0;
1302 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
1303 sc->sc_curaid);
c83be688 1304
8feceb67
VT
1305 /* Set aggregation protection mode parameters */
1306 sc->sc_config.ath_aggr_prot = 0;
c83be688 1307
8feceb67
VT
1308 /*
1309 * Reset our TSF so that its value is lower than the
1310 * beacon that we are trying to catch.
1311 * Only then hw will update its TSF register with the
1312 * new beacon. Reset the TSF before setting the BSSID
1313 * to avoid allowing in any frames that would update
1314 * our TSF only to have us clear it
1315 * immediately thereafter.
1316 */
1317 ath9k_hw_reset_tsf(sc->sc_ah);
c83be688 1318
8feceb67
VT
1319 /* Disable BMISS interrupt when we're not associated */
1320 ath9k_hw_set_interrupts(sc->sc_ah,
1321 sc->sc_imask &
1322 ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
1323 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
c83be688 1324
8feceb67 1325 DPRINTF(sc, ATH_DBG_CONFIG,
e174961c 1326 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
8feceb67 1327 __func__, rfilt,
e174961c 1328 sc->sc_curbssid, sc->sc_curaid);
c83be688 1329
8feceb67
VT
1330 /* need to reconfigure the beacon */
1331 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 1332
8feceb67
VT
1333 break;
1334 default:
1335 break;
1336 }
1337 }
c83be688 1338
8feceb67 1339 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB
1340 ((vif->type == NL80211_IFTYPE_ADHOC) ||
1341 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT
1342 /*
1343 * Allocate and setup the beacon frame.
1344 *
1345 * Stop any previous beacon DMA. This may be
1346 * necessary, for example, when an ibss merge
1347 * causes reconfiguration; we may be called
1348 * with beacon transmission active.
1349 */
1350 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
c83be688 1351
8feceb67
VT
1352 error = ath_beacon_alloc(sc, 0);
1353 if (error != 0)
1354 return error;
c83be688 1355
8feceb67
VT
1356 ath_beacon_sync(sc, 0);
1357 }
c83be688 1358
8feceb67 1359 /* Check for WLAN_CAPABILITY_PRIVACY ? */
05c914fe 1360 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT
1361 for (i = 0; i < IEEE80211_WEP_NKID; i++)
1362 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
1363 ath9k_hw_keysetmac(sc->sc_ah,
1364 (u16)i,
1365 sc->sc_curbssid);
1366 }
c83be688 1367
8feceb67 1368 /* Only legacy IBSS for now */
05c914fe 1369 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 1370 ath_update_chainmask(sc, 0);
f078f209 1371
8feceb67
VT
1372 return 0;
1373}
f078f209 1374
8feceb67
VT
1375#define SUPPORTED_FILTERS \
1376 (FIF_PROMISC_IN_BSS | \
1377 FIF_ALLMULTI | \
1378 FIF_CONTROL | \
1379 FIF_OTHER_BSS | \
1380 FIF_BCN_PRBRESP_PROMISC | \
1381 FIF_FCSFAIL)
c83be688 1382
8feceb67
VT
1383/* FIXME: sc->sc_full_reset ? */
1384static void ath9k_configure_filter(struct ieee80211_hw *hw,
1385 unsigned int changed_flags,
1386 unsigned int *total_flags,
1387 int mc_count,
1388 struct dev_mc_list *mclist)
1389{
1390 struct ath_softc *sc = hw->priv;
1391 u32 rfilt;
f078f209 1392
8feceb67
VT
1393 changed_flags &= SUPPORTED_FILTERS;
1394 *total_flags &= SUPPORTED_FILTERS;
f078f209 1395
8feceb67
VT
1396 sc->rx_filter = *total_flags;
1397 rfilt = ath_calcrxfilter(sc);
1398 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 1399
8feceb67
VT
1400 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1401 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1402 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
1403 }
f078f209 1404
8feceb67
VT
1405 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
1406 __func__, sc->rx_filter);
1407}
f078f209 1408
8feceb67
VT
1409static void ath9k_sta_notify(struct ieee80211_hw *hw,
1410 struct ieee80211_vif *vif,
1411 enum sta_notify_cmd cmd,
17741cdc 1412 struct ieee80211_sta *sta)
8feceb67
VT
1413{
1414 struct ath_softc *sc = hw->priv;
1415 struct ath_node *an;
1416 unsigned long flags;
f078f209 1417
8feceb67 1418 spin_lock_irqsave(&sc->node_lock, flags);
17741cdc 1419 an = ath_node_find(sc, sta->addr);
8feceb67 1420 spin_unlock_irqrestore(&sc->node_lock, flags);
f078f209 1421
8feceb67
VT
1422 switch (cmd) {
1423 case STA_NOTIFY_ADD:
1424 spin_lock_irqsave(&sc->node_lock, flags);
1425 if (!an) {
17741cdc 1426 ath_node_attach(sc, sta->addr, 0);
e174961c
JB
1427 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %pM\n",
1428 __func__, sta->addr);
8feceb67 1429 } else {
17741cdc 1430 ath_node_get(sc, sta->addr);
8feceb67 1431 }
ae5eb026
JB
1432
1433 /* XXX: Is this right? Can the capabilities change? */
1434 an = ath_node_find(sc, sta->addr);
1435 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
1436 sta->ht_cap.ampdu_factor);
1437 an->mpdudensity =
1438 parse_mpdudensity(sta->ht_cap.ampdu_density);
1439
8feceb67
VT
1440 spin_unlock_irqrestore(&sc->node_lock, flags);
1441 break;
1442 case STA_NOTIFY_REMOVE:
1443 if (!an)
1444 DPRINTF(sc, ATH_DBG_FATAL,
1445 "%s: Removal of a non-existent node\n",
1446 __func__);
1447 else {
1448 ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
e174961c 1449 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %pM\n",
8feceb67 1450 __func__,
e174961c 1451 sta->addr);
8feceb67
VT
1452 }
1453 break;
1454 default:
1455 break;
1456 }
f078f209
LR
1457}
1458
8feceb67
VT
1459static int ath9k_conf_tx(struct ieee80211_hw *hw,
1460 u16 queue,
1461 const struct ieee80211_tx_queue_params *params)
f078f209 1462{
8feceb67
VT
1463 struct ath_softc *sc = hw->priv;
1464 struct ath9k_tx_queue_info qi;
1465 int ret = 0, qnum;
f078f209 1466
8feceb67
VT
1467 if (queue >= WME_NUM_AC)
1468 return 0;
f078f209 1469
8feceb67
VT
1470 qi.tqi_aifs = params->aifs;
1471 qi.tqi_cwmin = params->cw_min;
1472 qi.tqi_cwmax = params->cw_max;
1473 qi.tqi_burstTime = params->txop;
1474 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1475
8feceb67
VT
1476 DPRINTF(sc, ATH_DBG_CONFIG,
1477 "%s: Configure tx [queue/halq] [%d/%d], "
1478 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1479 __func__,
1480 queue,
1481 qnum,
1482 params->aifs,
1483 params->cw_min,
1484 params->cw_max,
1485 params->txop);
f078f209 1486
8feceb67
VT
1487 ret = ath_txq_update(sc, qnum, &qi);
1488 if (ret)
1489 DPRINTF(sc, ATH_DBG_FATAL,
1490 "%s: TXQ Update failed\n", __func__);
f078f209 1491
8feceb67
VT
1492 return ret;
1493}
f078f209 1494
8feceb67
VT
1495static int ath9k_set_key(struct ieee80211_hw *hw,
1496 enum set_key_cmd cmd,
1497 const u8 *local_addr,
1498 const u8 *addr,
1499 struct ieee80211_key_conf *key)
1500{
1501 struct ath_softc *sc = hw->priv;
1502 int ret = 0;
f078f209 1503
8feceb67 1504 DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
f078f209 1505
8feceb67
VT
1506 switch (cmd) {
1507 case SET_KEY:
1508 ret = ath_key_config(sc, addr, key);
1509 if (!ret) {
1510 set_bit(key->keyidx, sc->sc_keymap);
1511 key->hw_key_idx = key->keyidx;
1512 /* push IV and Michael MIC generation to stack */
1513 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1514 if (key->alg == ALG_TKIP)
1515 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1516 }
1517 break;
1518 case DISABLE_KEY:
1519 ath_key_delete(sc, key);
1520 clear_bit(key->keyidx, sc->sc_keymap);
8feceb67
VT
1521 break;
1522 default:
1523 ret = -EINVAL;
1524 }
f078f209 1525
8feceb67
VT
1526 return ret;
1527}
f078f209 1528
8feceb67
VT
1529static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1530 struct ieee80211_vif *vif,
1531 struct ieee80211_bss_conf *bss_conf,
1532 u32 changed)
1533{
1534 struct ath_softc *sc = hw->priv;
f078f209 1535
8feceb67
VT
1536 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1537 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
1538 __func__,
1539 bss_conf->use_short_preamble);
1540 if (bss_conf->use_short_preamble)
1541 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1542 else
1543 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1544 }
f078f209 1545
8feceb67
VT
1546 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1547 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
1548 __func__,
1549 bss_conf->use_cts_prot);
1550 if (bss_conf->use_cts_prot &&
1551 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1552 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1553 else
1554 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1555 }
f078f209 1556
8feceb67 1557 if (changed & BSS_CHANGED_HT) {
ae5eb026
JB
1558 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
1559 __func__);
8feceb67 1560 ath9k_ht_conf(sc, bss_conf);
f078f209
LR
1561 }
1562
8feceb67
VT
1563 if (changed & BSS_CHANGED_ASSOC) {
1564 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
1565 __func__,
1566 bss_conf->assoc);
1567 ath9k_bss_assoc_info(sc, bss_conf);
1568 }
1569}
f078f209 1570
8feceb67
VT
1571static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1572{
1573 u64 tsf;
1574 struct ath_softc *sc = hw->priv;
1575 struct ath_hal *ah = sc->sc_ah;
f078f209 1576
8feceb67 1577 tsf = ath9k_hw_gettsf64(ah);
f078f209 1578
8feceb67
VT
1579 return tsf;
1580}
f078f209 1581
8feceb67
VT
1582static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1583{
1584 struct ath_softc *sc = hw->priv;
1585 struct ath_hal *ah = sc->sc_ah;
c83be688 1586
8feceb67
VT
1587 ath9k_hw_reset_tsf(ah);
1588}
f078f209 1589
8feceb67
VT
1590static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1591 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB
1592 struct ieee80211_sta *sta,
1593 u16 tid, u16 *ssn)
8feceb67
VT
1594{
1595 struct ath_softc *sc = hw->priv;
1596 int ret = 0;
f078f209 1597
8feceb67
VT
1598 switch (action) {
1599 case IEEE80211_AMPDU_RX_START:
17741cdc 1600 ret = ath_rx_aggr_start(sc, sta->addr, tid, ssn);
8feceb67
VT
1601 if (ret < 0)
1602 DPRINTF(sc, ATH_DBG_FATAL,
1603 "%s: Unable to start RX aggregation\n",
1604 __func__);
1605 break;
1606 case IEEE80211_AMPDU_RX_STOP:
17741cdc 1607 ret = ath_rx_aggr_stop(sc, sta->addr, tid);
8feceb67
VT
1608 if (ret < 0)
1609 DPRINTF(sc, ATH_DBG_FATAL,
1610 "%s: Unable to stop RX aggregation\n",
1611 __func__);
1612 break;
1613 case IEEE80211_AMPDU_TX_START:
17741cdc 1614 ret = ath_tx_aggr_start(sc, sta->addr, tid, ssn);
8feceb67
VT
1615 if (ret < 0)
1616 DPRINTF(sc, ATH_DBG_FATAL,
1617 "%s: Unable to start TX aggregation\n",
1618 __func__);
1619 else
17741cdc 1620 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT
1621 break;
1622 case IEEE80211_AMPDU_TX_STOP:
17741cdc 1623 ret = ath_tx_aggr_stop(sc, sta->addr, tid);
8feceb67
VT
1624 if (ret < 0)
1625 DPRINTF(sc, ATH_DBG_FATAL,
1626 "%s: Unable to stop TX aggregation\n",
1627 __func__);
f078f209 1628
17741cdc 1629 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT
1630 break;
1631 default:
1632 DPRINTF(sc, ATH_DBG_FATAL,
1633 "%s: Unknown AMPDU action\n", __func__);
1634 }
1635
1636 return ret;
f078f209
LR
1637}
1638
4233df6b
JB
1639static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
1640{
1641 return -EOPNOTSUPP;
1642}
1643
8feceb67
VT
1644static struct ieee80211_ops ath9k_ops = {
1645 .tx = ath9k_tx,
1646 .start = ath9k_start,
1647 .stop = ath9k_stop,
1648 .add_interface = ath9k_add_interface,
1649 .remove_interface = ath9k_remove_interface,
1650 .config = ath9k_config,
1651 .config_interface = ath9k_config_interface,
1652 .configure_filter = ath9k_configure_filter,
1653 .get_stats = NULL,
1654 .sta_notify = ath9k_sta_notify,
1655 .conf_tx = ath9k_conf_tx,
1656 .get_tx_stats = NULL,
1657 .bss_info_changed = ath9k_bss_info_changed,
1658 .set_tim = NULL,
1659 .set_key = ath9k_set_key,
1660 .hw_scan = NULL,
1661 .get_tkip_seq = NULL,
1662 .set_rts_threshold = NULL,
1663 .set_frag_threshold = NULL,
8feceb67
VT
1664 .get_tsf = ath9k_get_tsf,
1665 .reset_tsf = ath9k_reset_tsf,
1666 .tx_last_beacon = NULL,
4233df6b
JB
1667 .ampdu_action = ath9k_ampdu_action,
1668 .set_frag_threshold = ath9k_no_fragmentation,
8feceb67
VT
1669};
1670
f078f209
LR
1671static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1672{
1673 void __iomem *mem;
1674 struct ath_softc *sc;
1675 struct ieee80211_hw *hw;
1676 const char *athname;
1677 u8 csz;
1678 u32 val;
1679 int ret = 0;
1680
1681 if (pci_enable_device(pdev))
1682 return -EIO;
1683
1684 /* XXX 32-bit addressing only */
1685 if (pci_set_dma_mask(pdev, 0xffffffff)) {
1686 printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
1687 ret = -ENODEV;
1688 goto bad;
1689 }
1690
1691 /*
1692 * Cache line size is used to size and align various
1693 * structures used to communicate with the hardware.
1694 */
1695 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
1696 if (csz == 0) {
1697 /*
1698 * Linux 2.4.18 (at least) writes the cache line size
1699 * register as a 16-bit wide register which is wrong.
1700 * We must have this setup properly for rx buffer
1701 * DMA to work so force a reasonable value here if it
1702 * comes up zero.
1703 */
1704 csz = L1_CACHE_BYTES / sizeof(u32);
1705 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
1706 }
1707 /*
1708 * The default setting of latency timer yields poor results,
1709 * set it to the value used by other systems. It may be worth
1710 * tweaking this setting more.
1711 */
1712 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
1713
1714 pci_set_master(pdev);
1715
1716 /*
1717 * Disable the RETRY_TIMEOUT register (0x41) to keep
1718 * PCI Tx retries from interfering with C3 CPU state.
1719 */
1720 pci_read_config_dword(pdev, 0x40, &val);
1721 if ((val & 0x0000ff00) != 0)
1722 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1723
1724 ret = pci_request_region(pdev, 0, "ath9k");
1725 if (ret) {
1726 dev_err(&pdev->dev, "PCI memory region reserve error\n");
1727 ret = -ENODEV;
1728 goto bad;
1729 }
1730
1731 mem = pci_iomap(pdev, 0, 0);
1732 if (!mem) {
1733 printk(KERN_ERR "PCI memory map error\n") ;
1734 ret = -EIO;
1735 goto bad1;
1736 }
1737
1738 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
1739 if (hw == NULL) {
1740 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
1741 goto bad2;
1742 }
1743
19b73c7f 1744 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
e022edbd 1745 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
19b73c7f 1746 IEEE80211_HW_SIGNAL_DBM |
f078f209
LR
1747 IEEE80211_HW_NOISE_DBM;
1748
f59ac048
LR
1749 hw->wiphy->interface_modes =
1750 BIT(NL80211_IFTYPE_AP) |
1751 BIT(NL80211_IFTYPE_STATION) |
1752 BIT(NL80211_IFTYPE_ADHOC);
1753
f078f209
LR
1754 SET_IEEE80211_DEV(hw, &pdev->dev);
1755 pci_set_drvdata(pdev, hw);
1756
1757 sc = hw->priv;
1758 sc->hw = hw;
1759 sc->pdev = pdev;
1760 sc->mem = mem;
1761
1762 if (ath_attach(id->device, sc) != 0) {
1763 ret = -ENODEV;
1764 goto bad3;
1765 }
1766
1767 /* setup interrupt service routine */
1768
1769 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
1770 printk(KERN_ERR "%s: request_irq failed\n",
1771 wiphy_name(hw->wiphy));
1772 ret = -EIO;
1773 goto bad4;
1774 }
1775
1776 athname = ath9k_hw_probe(id->vendor, id->device);
1777
1778 printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
1779 wiphy_name(hw->wiphy),
1780 athname ? athname : "Atheros ???",
1781 (unsigned long)mem, pdev->irq);
1782
1783 return 0;
1784bad4:
1785 ath_detach(sc);
1786bad3:
1787 ieee80211_free_hw(hw);
1788bad2:
1789 pci_iounmap(pdev, mem);
1790bad1:
1791 pci_release_region(pdev, 0);
1792bad:
1793 pci_disable_device(pdev);
1794 return ret;
1795}
1796
1797static void ath_pci_remove(struct pci_dev *pdev)
1798{
1799 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1800 struct ath_softc *sc = hw->priv;
6115e855 1801 enum ath9k_int status;
f078f209 1802
6115e855
SB
1803 if (pdev->irq) {
1804 ath9k_hw_set_interrupts(sc->sc_ah, 0);
1805 /* clear the ISR */
1806 ath9k_hw_getisr(sc->sc_ah, &status);
b262e603 1807 sc->sc_flags |= SC_OP_INVALID;
f078f209 1808 free_irq(pdev->irq, sc);
6115e855 1809 }
f078f209 1810 ath_detach(sc);
6115e855 1811
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LR
1812 pci_iounmap(pdev, sc->mem);
1813 pci_release_region(pdev, 0);
1814 pci_disable_device(pdev);
1815 ieee80211_free_hw(hw);
1816}
1817
1818#ifdef CONFIG_PM
1819
1820static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1821{
c83be688
VT
1822 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1823 struct ath_softc *sc = hw->priv;
1824
1825 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d
VT
1826
1827#ifdef CONFIG_RFKILL
1828 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1829 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1830#endif
1831
f078f209
LR
1832 pci_save_state(pdev);
1833 pci_disable_device(pdev);
1834 pci_set_power_state(pdev, 3);
1835
1836 return 0;
1837}
1838
1839static int ath_pci_resume(struct pci_dev *pdev)
1840{
c83be688
VT
1841 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1842 struct ath_softc *sc = hw->priv;
f078f209
LR
1843 u32 val;
1844 int err;
1845
1846 err = pci_enable_device(pdev);
1847 if (err)
1848 return err;
1849 pci_restore_state(pdev);
1850 /*
1851 * Suspend/Resume resets the PCI configuration space, so we have to
1852 * re-disable the RETRY_TIMEOUT register (0x41) to keep
1853 * PCI Tx retries from interfering with C3 CPU state
1854 */
1855 pci_read_config_dword(pdev, 0x40, &val);
1856 if ((val & 0x0000ff00) != 0)
1857 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1858
c83be688
VT
1859 /* Enable LED */
1860 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1861 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1862 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1863
500c064d
VT
1864#ifdef CONFIG_RFKILL
1865 /*
1866 * check the h/w rfkill state on resume
1867 * and start the rfkill poll timer
1868 */
1869 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1870 queue_delayed_work(sc->hw->workqueue,
1871 &sc->rf_kill.rfkill_poll, 0);
1872#endif
1873
f078f209
LR
1874 return 0;
1875}
1876
1877#endif /* CONFIG_PM */
1878
1879MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
1880
1881static struct pci_driver ath_pci_driver = {
1882 .name = "ath9k",
1883 .id_table = ath_pci_id_table,
1884 .probe = ath_pci_probe,
1885 .remove = ath_pci_remove,
1886#ifdef CONFIG_PM
1887 .suspend = ath_pci_suspend,
1888 .resume = ath_pci_resume,
1889#endif /* CONFIG_PM */
1890};
1891
1892static int __init init_ath_pci(void)
1893{
1894 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
1895
1896 if (pci_register_driver(&ath_pci_driver) < 0) {
1897 printk(KERN_ERR
1898 "ath_pci: No devices found, driver not installed.\n");
1899 pci_unregister_driver(&ath_pci_driver);
1900 return -ENODEV;
1901 }
1902
1903 return 0;
1904}
1905module_init(init_ath_pci);
1906
1907static void __exit exit_ath_pci(void)
1908{
1909 pci_unregister_driver(&ath_pci_driver);
1910 printk(KERN_INFO "%s: driver unloaded\n", dev_info);
1911}
1912module_exit(exit_ath_pci);
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