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ath9k: Convert ANI channel to a pointer
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
5f8e077c
LR		 29/* We use the hw_value as an index into our private channel structure */
30
31#define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 30, \
35}
36
37#define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 30, \
42}
43
44/* Some 2 GHz radios are actually tunable on 2312-2732
45 * on 5 MHz steps, we support the channels which we know
46 * we have calibration data for all cards though to make
47 * this static */
48static struct ieee80211_channel ath9k_2ghz_chantable[] = {
49 CHAN2G(2412, 0), /* Channel 1 */
50 CHAN2G(2417, 1), /* Channel 2 */
51 CHAN2G(2422, 2), /* Channel 3 */
52 CHAN2G(2427, 3), /* Channel 4 */
53 CHAN2G(2432, 4), /* Channel 5 */
54 CHAN2G(2437, 5), /* Channel 6 */
55 CHAN2G(2442, 6), /* Channel 7 */
56 CHAN2G(2447, 7), /* Channel 8 */
57 CHAN2G(2452, 8), /* Channel 9 */
58 CHAN2G(2457, 9), /* Channel 10 */
59 CHAN2G(2462, 10), /* Channel 11 */
60 CHAN2G(2467, 11), /* Channel 12 */
61 CHAN2G(2472, 12), /* Channel 13 */
62 CHAN2G(2484, 13), /* Channel 14 */
63};
64
65/* Some 5 GHz radios are actually tunable on XXXX-YYYY
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
68 * this static */
69static struct ieee80211_channel ath9k_5ghz_chantable[] = {
70 /* _We_ call this UNII 1 */
71 CHAN5G(5180, 14), /* Channel 36 */
72 CHAN5G(5200, 15), /* Channel 40 */
73 CHAN5G(5220, 16), /* Channel 44 */
74 CHAN5G(5240, 17), /* Channel 48 */
75 /* _We_ call this UNII 2 */
76 CHAN5G(5260, 18), /* Channel 52 */
77 CHAN5G(5280, 19), /* Channel 56 */
78 CHAN5G(5300, 20), /* Channel 60 */
79 CHAN5G(5320, 21), /* Channel 64 */
80 /* _We_ call this "Middle band" */
81 CHAN5G(5500, 22), /* Channel 100 */
82 CHAN5G(5520, 23), /* Channel 104 */
83 CHAN5G(5540, 24), /* Channel 108 */
84 CHAN5G(5560, 25), /* Channel 112 */
85 CHAN5G(5580, 26), /* Channel 116 */
86 CHAN5G(5600, 27), /* Channel 120 */
87 CHAN5G(5620, 28), /* Channel 124 */
88 CHAN5G(5640, 29), /* Channel 128 */
89 CHAN5G(5660, 30), /* Channel 132 */
90 CHAN5G(5680, 31), /* Channel 136 */
91 CHAN5G(5700, 32), /* Channel 140 */
92 /* _We_ call this UNII 3 */
93 CHAN5G(5745, 33), /* Channel 149 */
94 CHAN5G(5765, 34), /* Channel 153 */
95 CHAN5G(5785, 35), /* Channel 157 */
96 CHAN5G(5805, 36), /* Channel 161 */
97 CHAN5G(5825, 37), /* Channel 165 */
98};
99
ce111bad
LR		 100static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
ff37e337 102{
030bb495
LR		 103 switch (conf->channel->band) {
104 case IEEE80211_BAND_2GHZ:
105 if (conf_is_ht20(conf))
106 sc->cur_rate_table =
107 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
108 else if (conf_is_ht40_minus(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
111 else if (conf_is_ht40_plus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 114 else
030bb495
LR		 115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 117 break;
118 case IEEE80211_BAND_5GHZ:
119 if (conf_is_ht20(conf))
120 sc->cur_rate_table =
121 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
122 else if (conf_is_ht40_minus(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
125 else if (conf_is_ht40_plus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
128 else
96742256
LR		 129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 131 break;
132 default:
ce111bad 133 BUG_ON(1);
030bb495
LR		 134 break;
135 }
ff37e337
S		 136}
137
138static void ath_update_txpow(struct ath_softc *sc)
139{
140 struct ath_hal *ah = sc->sc_ah;
141 u32 txpow;
142
143 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
144 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
145 /* read back in case value is clamped */
146 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
147 sc->sc_curtxpow = txpow;
148 }
149}
150
151static u8 parse_mpdudensity(u8 mpdudensity)
152{
153 /*
154 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
155 * 0 for no restriction
156 * 1 for 1/4 us
157 * 2 for 1/2 us
158 * 3 for 1 us
159 * 4 for 2 us
160 * 5 for 4 us
161 * 6 for 8 us
162 * 7 for 16 us
163 */
164 switch (mpdudensity) {
165 case 0:
166 return 0;
167 case 1:
168 case 2:
169 case 3:
170 /* Our lower layer calculations limit our precision to
171 1 microsecond */
172 return 1;
173 case 4:
174 return 2;
175 case 5:
176 return 4;
177 case 6:
178 return 8;
179 case 7:
180 return 16;
181 default:
182 return 0;
183 }
184}
185
186static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
187{
188 struct ath_rate_table *rate_table = NULL;
189 struct ieee80211_supported_band *sband;
190 struct ieee80211_rate *rate;
191 int i, maxrates;
192
193 switch (band) {
194 case IEEE80211_BAND_2GHZ:
195 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
196 break;
197 case IEEE80211_BAND_5GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
199 break;
200 default:
201 break;
202 }
203
204 if (rate_table == NULL)
205 return;
206
207 sband = &sc->sbands[band];
208 rate = sc->rates[band];
209
210 if (rate_table->rate_cnt > ATH_RATE_MAX)
211 maxrates = ATH_RATE_MAX;
212 else
213 maxrates = rate_table->rate_cnt;
214
215 for (i = 0; i < maxrates; i++) {
216 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
217 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 218 if (rate_table->info[i].short_preamble) {
219 rate[i].hw_value_short = rate_table->info[i].ratecode |
220 rate_table->info[i].short_preamble;
221 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
222 }
ff37e337 223 sband->n_bitrates++;
f46730d1 224
04bd4638
S		 225 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
226 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 227 }
228}
229
ff37e337
S		 230/*
231 * Set/change channels. If the channel is really being changed, it's done
232 * by reseting the chip. To accomplish this we must first cleanup any pending
233 * DMA, then restart stuff.
234*/
235static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
236{
237 struct ath_hal *ah = sc->sc_ah;
238 bool fastcc = true, stopped;
030bb495 239 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 240 struct ieee80211_channel *channel = hw->conf.channel;
241 int r;
ff37e337
S		 242
243 if (sc->sc_flags & SC_OP_INVALID)
244 return -EIO;
245
3cbb5dd7
VN		 246 ath9k_ps_wakeup(sc);
247
c0d7c7af
LR		 248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
257 ath9k_hw_set_interrupts(ah, 0);
043a0405 258 ath_drain_all_txq(sc, false);
c0d7c7af 259 stopped = ath_stoprecv(sc);
ff37e337 260
c0d7c7af
LR		 261 /* XXX: do not flush receive queue here. We don't want
262 * to flush data frames already in queue because of
263 * changing channel. */
ff37e337 264
c0d7c7af
LR		 265 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
266 fastcc = false;
267
268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
270 sc->sc_ah->ah_curchan->channel,
271 channel->center_freq, sc->tx_chan_width);
ff37e337 272
c0d7c7af
LR		 273 spin_lock_bh(&sc->sc_resetlock);
274
275 r = ath9k_hw_reset(ah, hchan, fastcc);
276 if (r) {
277 DPRINTF(sc, ATH_DBG_FATAL,
278 "Unable to reset channel (%u Mhz) "
279 "reset status %u\n",
280 channel->center_freq, r);
281 spin_unlock_bh(&sc->sc_resetlock);
282 return r;
ff37e337 283 }
c0d7c7af
LR		 284 spin_unlock_bh(&sc->sc_resetlock);
285
286 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
287 sc->sc_flags &= ~SC_OP_FULL_RESET;
288
289 if (ath_startrecv(sc) != 0) {
290 DPRINTF(sc, ATH_DBG_FATAL,
291 "Unable to restart recv logic\n");
292 return -EIO;
293 }
294
295 ath_cache_conf_rate(sc, &hw->conf);
296 ath_update_txpow(sc);
297 ath9k_hw_set_interrupts(ah, sc->sc_imask);
3cbb5dd7 298 ath9k_ps_restore(sc);
ff37e337
S		 299 return 0;
300}
301
302/*
303 * This routine performs the periodic noise floor calibration function
304 * that is used to adjust and optimize the chip performance. This
305 * takes environmental changes (location, temperature) into account.
306 * When the task is complete, it reschedules itself depending on the
307 * appropriate interval that was calculated.
308 */
309static void ath_ani_calibrate(unsigned long data)
310{
311 struct ath_softc *sc;
312 struct ath_hal *ah;
313 bool longcal = false;
314 bool shortcal = false;
315 bool aniflag = false;
316 unsigned int timestamp = jiffies_to_msecs(jiffies);
317 u32 cal_interval;
318
319 sc = (struct ath_softc *)data;
320 ah = sc->sc_ah;
321
322 /*
323 * don't calibrate when we're scanning.
324 * we are most likely not on our home channel.
325 */
b77f483f 326 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 327 return;
328
329 /* Long calibration runs independently of short calibration. */
330 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
331 longcal = true;
04bd4638 332 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 333 sc->sc_ani.sc_longcal_timer = timestamp;
334 }
335
336 /* Short calibration applies only while sc_caldone is false */
337 if (!sc->sc_ani.sc_caldone) {
338 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
339 ATH_SHORT_CALINTERVAL) {
340 shortcal = true;
04bd4638 341 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 342 sc->sc_ani.sc_shortcal_timer = timestamp;
343 sc->sc_ani.sc_resetcal_timer = timestamp;
344 }
345 } else {
346 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
347 ATH_RESTART_CALINTERVAL) {
c9e27d94 348 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 349 if (sc->sc_ani.sc_caldone)
350 sc->sc_ani.sc_resetcal_timer = timestamp;
351 }
352 }
353
354 /* Verify whether we must check ANI */
355 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
356 ATH_ANI_POLLINTERVAL) {
357 aniflag = true;
358 sc->sc_ani.sc_checkani_timer = timestamp;
359 }
360
361 /* Skip all processing if there's nothing to do. */
362 if (longcal || shortcal || aniflag) {
363 /* Call ANI routine if necessary */
364 if (aniflag)
365 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
366 ah->ah_curchan);
367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
372 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
373 sc->sc_rx_chainmask, longcal,
374 &iscaldone)) {
375 if (longcal)
376 sc->sc_ani.sc_noise_floor =
377 ath9k_hw_getchan_noise(ah,
378 ah->ah_curchan);
379
380 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 381 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 382 ah->ah_curchan->channel,
383 ah->ah_curchan->channelFlags,
384 sc->sc_ani.sc_noise_floor);
385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 387 "calibrate chan %u/%x failed\n",
ff37e337
S		 388 ah->ah_curchan->channel,
389 ah->ah_curchan->channelFlags);
390 }
391 sc->sc_ani.sc_caldone = iscaldone;
392 }
393 }
394
395 /*
396 * Set timer interval based on previous results.
397 * The interval must be the shortest necessary to satisfy ANI,
398 * short calibration and long calibration.
399 */
aac9207e
S		 400 cal_interval = ATH_LONG_CALINTERVAL;
401 if (sc->sc_ah->ah_config.enable_ani)
402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 403 if (!sc->sc_ani.sc_caldone)
404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
405
406 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
407}
408
409/*
410 * Update tx/rx chainmask. For legacy association,
411 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 412 * the chainmask configuration, for bt coexistence, use
413 * the chainmask configuration even in legacy mode.
ff37e337
S		 414 */
415static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416{
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 418 if (is_ht ||
419 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 420 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
421 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
422 } else {
423 sc->sc_tx_chainmask = 1;
424 sc->sc_rx_chainmask = 1;
425 }
426
04bd4638
S		 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
439
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
456 u32 status = sc->sc_intrstatus;
457
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
461 return;
462 } else {
463
464 if (status &
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 466 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 467 ath_rx_tasklet(sc, 0);
b77f483f 468 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 469 }
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
472 ath_tx_tasklet(sc);
473 }
474
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
477}
478
6baff7f9 479irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 480{
481 struct ath_softc *sc = dev;
482 struct ath_hal *ah = sc->sc_ah;
483 enum ath9k_int status;
484 bool sched = false;
485
486 do {
487 if (sc->sc_flags & SC_OP_INVALID) {
488 /*
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
492 */
493 return IRQ_NONE;
494 }
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
496 return IRQ_NONE;
497 }
498
499 /*
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
504 */
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
506
507 status &= sc->sc_imask; /* discard unasked-for bits */
508
509 /*
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
512 */
513 if (!status)
514 return IRQ_NONE;
515
516 sc->sc_intrstatus = status;
517
518 if (status & ATH9K_INT_FATAL) {
519 /* need a chip reset */
520 sched = true;
521 } else if (status & ATH9K_INT_RXORN) {
522 /* need a chip reset */
523 sched = true;
524 } else {
525 if (status & ATH9K_INT_SWBA) {
526 /* schedule a tasklet for beacon handling */
527 tasklet_schedule(&sc->bcon_tasklet);
528 }
529 if (status & ATH9K_INT_RXEOL) {
530 /*
531 * NB: the hardware should re-read the link when
532 * RXE bit is written, but it doesn't work
533 * at least on older hardware revs.
534 */
535 sched = true;
536 }
537
538 if (status & ATH9K_INT_TXURN)
539 /* bump tx trigger level */
540 ath9k_hw_updatetxtriglevel(ah, true);
541 /* XXX: optimize this */
542 if (status & ATH9K_INT_RX)
543 sched = true;
544 if (status & ATH9K_INT_TX)
545 sched = true;
546 if (status & ATH9K_INT_BMISS)
547 sched = true;
548 /* carrier sense timeout */
549 if (status & ATH9K_INT_CST)
550 sched = true;
551 if (status & ATH9K_INT_MIB) {
552 /*
553 * Disable interrupts until we service the MIB
554 * interrupt; otherwise it will continue to
555 * fire.
556 */
557 ath9k_hw_set_interrupts(ah, 0);
558 /*
559 * Let the hal handle the event. We assume
560 * it will clear whatever condition caused
561 * the interrupt.
562 */
563 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
564 ath9k_hw_set_interrupts(ah, sc->sc_imask);
565 }
566 if (status & ATH9K_INT_TIM_TIMER) {
567 if (!(ah->ah_caps.hw_caps &
568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can
570 * receive frames */
3cbb5dd7 571 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 572 ath9k_hw_setrxabort(ah, 0);
573 sched = true;
3cbb5dd7 574 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 575 }
576 }
577 }
578 } while (0);
579
817e11de
S		 580 ath_debug_stat_interrupt(sc, status);
581
ff37e337
S		 582 if (sched) {
583 /* turn off every interrupt except SWBA */
584 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
585 tasklet_schedule(&sc->intr_tq);
586 }
587
588 return IRQ_HANDLED;
589}
590
f078f209 591static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 592 struct ieee80211_channel *chan,
094d05dc 593 enum nl80211_channel_type channel_type)
f078f209
LR		 594{
595 u32 chanmode = 0;
f078f209
LR		 596
597 switch (chan->band) {
598 case IEEE80211_BAND_2GHZ:
094d05dc
S		 599 switch(channel_type) {
600 case NL80211_CHAN_NO_HT:
601 case NL80211_CHAN_HT20:
f078f209 602 chanmode = CHANNEL_G_HT20;
094d05dc
S		 603 break;
604 case NL80211_CHAN_HT40PLUS:
f078f209 605 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 606 break;
607 case NL80211_CHAN_HT40MINUS:
f078f209 608 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 609 break;
610 }
f078f209
LR		 611 break;
612 case IEEE80211_BAND_5GHZ:
094d05dc
S		 613 switch(channel_type) {
614 case NL80211_CHAN_NO_HT:
615 case NL80211_CHAN_HT20:
f078f209 616 chanmode = CHANNEL_A_HT20;
094d05dc
S		 617 break;
618 case NL80211_CHAN_HT40PLUS:
f078f209 619 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 620 break;
621 case NL80211_CHAN_HT40MINUS:
f078f209 622 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 623 break;
624 }
f078f209
LR		 625 break;
626 default:
627 break;
628 }
629
630 return chanmode;
631}
632
ff37e337
S		 633static int ath_keyset(struct ath_softc *sc, u16 keyix,
634 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
635{
636 bool status;
637
638 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
639 keyix, hk, mac, false);
640
641 return status != false;
642}
f078f209 643
6ace2891 644static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 645 struct ath9k_keyval *hk,
646 const u8 *addr)
647{
6ace2891
JM		 648 const u8 *key_rxmic;
649 const u8 *key_txmic;
f078f209 650
6ace2891
JM		 651 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
652 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 653
654 if (addr == NULL) {
655 /* Group key installation */
6ace2891
JM		 656 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
657 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 658 }
659 if (!sc->sc_splitmic) {
660 /*
661 * data key goes at first index,
662 * the hal handles the MIC keys at index+64.
663 */
664 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
665 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 666 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 667 }
668 /*
669 * TX key goes at first index, RX key at +32.
670 * The hal handles the MIC keys at index+64.
671 */
672 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 673 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 674 /* Txmic entry failed. No need to proceed further */
675 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 676 "Setting TX MIC Key Failed\n");
f078f209
LR		 677 return 0;
678 }
679
680 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
681 /* XXX delete tx key on failure? */
6ace2891
JM		 682 return ath_keyset(sc, keyix + 32, hk, addr);
683}
684
685static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
686{
687 int i;
688
689 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
690 if (test_bit(i, sc->sc_keymap) ||
691 test_bit(i + 64, sc->sc_keymap))
692 continue; /* At least one part of TKIP key allocated */
693 if (sc->sc_splitmic &&
694 (test_bit(i + 32, sc->sc_keymap) ||
695 test_bit(i + 64 + 32, sc->sc_keymap)))
696 continue; /* At least one part of TKIP key allocated */
697
698 /* Found a free slot for a TKIP key */
699 return i;
700 }
701 return -1;
702}
703
704static int ath_reserve_key_cache_slot(struct ath_softc *sc)
705{
706 int i;
707
708 /* First, try to find slots that would not be available for TKIP. */
709 if (sc->sc_splitmic) {
710 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
711 if (!test_bit(i, sc->sc_keymap) &&
712 (test_bit(i + 32, sc->sc_keymap) ||
713 test_bit(i + 64, sc->sc_keymap) ||
714 test_bit(i + 64 + 32, sc->sc_keymap)))
715 return i;
716 if (!test_bit(i + 32, sc->sc_keymap) &&
717 (test_bit(i, sc->sc_keymap) ||
718 test_bit(i + 64, sc->sc_keymap) ||
719 test_bit(i + 64 + 32, sc->sc_keymap)))
720 return i + 32;
721 if (!test_bit(i + 64, sc->sc_keymap) &&
722 (test_bit(i , sc->sc_keymap) ||
723 test_bit(i + 32, sc->sc_keymap) ||
724 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 725 return i + 64;
6ace2891
JM		 726 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
727 (test_bit(i, sc->sc_keymap) ||
728 test_bit(i + 32, sc->sc_keymap) ||
729 test_bit(i + 64, sc->sc_keymap)))
ea612132 730 return i + 64 + 32;
6ace2891
JM		 731 }
732 } else {
733 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
734 if (!test_bit(i, sc->sc_keymap) &&
735 test_bit(i + 64, sc->sc_keymap))
736 return i;
737 if (test_bit(i, sc->sc_keymap) &&
738 !test_bit(i + 64, sc->sc_keymap))
739 return i + 64;
740 }
741 }
742
743 /* No partially used TKIP slots, pick any available slot */
744 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 745 /* Do not allow slots that could be needed for TKIP group keys
746 * to be used. This limitation could be removed if we know that
747 * TKIP will not be used. */
748 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
749 continue;
750 if (sc->sc_splitmic) {
751 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
752 continue;
753 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
754 continue;
755 }
756
6ace2891
JM		 757 if (!test_bit(i, sc->sc_keymap))
758 return i; /* Found a free slot for a key */
759 }
760
761 /* No free slot found */
762 return -1;
f078f209
LR		 763}
764
765static int ath_key_config(struct ath_softc *sc,
dc822b5d 766 struct ieee80211_sta *sta,
f078f209
LR		 767 struct ieee80211_key_conf *key)
768{
f078f209
LR		 769 struct ath9k_keyval hk;
770 const u8 *mac = NULL;
771 int ret = 0;
6ace2891 772 int idx;
f078f209
LR		 773
774 memset(&hk, 0, sizeof(hk));
775
776 switch (key->alg) {
777 case ALG_WEP:
778 hk.kv_type = ATH9K_CIPHER_WEP;
779 break;
780 case ALG_TKIP:
781 hk.kv_type = ATH9K_CIPHER_TKIP;
782 break;
783 case ALG_CCMP:
784 hk.kv_type = ATH9K_CIPHER_AES_CCM;
785 break;
786 default:
ca470b29 787 return -EOPNOTSUPP;
f078f209
LR		 788 }
789
6ace2891 790 hk.kv_len = key->keylen;
f078f209
LR		 791 memcpy(hk.kv_val, key->key, key->keylen);
792
6ace2891
JM		 793 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
794 /* For now, use the default keys for broadcast keys. This may
795 * need to change with virtual interfaces. */
796 idx = key->keyidx;
797 } else if (key->keyidx) {
798 struct ieee80211_vif *vif;
f078f209 799
dc822b5d
JB		 800 if (WARN_ON(!sta))
801 return -EOPNOTSUPP;
802 mac = sta->addr;
803
6ace2891
JM		 804 vif = sc->sc_vaps[0];
805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
808 idx = key->keyidx;
809 } else
810 return -EIO;
f078f209 811 } else {
dc822b5d
JB		 812 if (WARN_ON(!sta))
813 return -EOPNOTSUPP;
814 mac = sta->addr;
815
6ace2891
JM		 816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
818 else
819 idx = ath_reserve_key_cache_slot(sc);
820 if (idx < 0)
ca470b29 821 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 822 }
823
824 if (key->alg == ALG_TKIP)
6ace2891 825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 826 else
6ace2891 827 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 828
829 if (!ret)
830 return -EIO;
831
6ace2891
JM		 832 set_bit(idx, sc->sc_keymap);
833 if (key->alg == ALG_TKIP) {
834 set_bit(idx + 64, sc->sc_keymap);
835 if (sc->sc_splitmic) {
836 set_bit(idx + 32, sc->sc_keymap);
837 set_bit(idx + 64 + 32, sc->sc_keymap);
838 }
839 }
840
841 return idx;
f078f209
LR		 842}
843
844static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
845{
6ace2891
JM		 846 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
847 if (key->hw_key_idx < IEEE80211_WEP_NKID)
848 return;
849
850 clear_bit(key->hw_key_idx, sc->sc_keymap);
851 if (key->alg != ALG_TKIP)
852 return;
f078f209 853
6ace2891
JM		 854 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
855 if (sc->sc_splitmic) {
856 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
857 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
858 }
f078f209
LR		 859}
860
eb2599ca
S		 861static void setup_ht_cap(struct ath_softc *sc,
862 struct ieee80211_sta_ht_cap *ht_info)
f078f209 863{
60653678
S		 864#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
865#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 866
d9fe60de
JB		 867 ht_info->ht_supported = true;
868 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
869 IEEE80211_HT_CAP_SM_PS |
870 IEEE80211_HT_CAP_SGI_40 |
871 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 872
60653678
S		 873 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
874 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 875
d9fe60de
JB		 876 /* set up supported mcs set */
877 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca
S		 878
879 switch(sc->sc_rx_chainmask) {
880 case 1:
881 ht_info->mcs.rx_mask[0] = 0xff;
882 break;
3c457265 883 case 3:
eb2599ca
S		 884 case 5:
885 case 7:
886 default:
887 ht_info->mcs.rx_mask[0] = 0xff;
888 ht_info->mcs.rx_mask[1] = 0xff;
889 break;
890 }
891
d9fe60de 892 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 893}
894
8feceb67 895static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 896 struct ieee80211_vif *vif,
8feceb67 897 struct ieee80211_bss_conf *bss_conf)
f078f209 898{
5640b08e 899 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 900
8feceb67 901 if (bss_conf->assoc) {
094d05dc
S		 902 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
903 bss_conf->aid, sc->sc_curbssid);
f078f209 904
8feceb67 905 /* New association, store aid */
d97809db 906 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 907 sc->sc_curaid = bss_conf->aid;
908 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
909 sc->sc_curaid);
910 }
f078f209 911
8feceb67
VT		 912 /* Configure the beacon */
913 ath_beacon_config(sc, 0);
914 sc->sc_flags |= SC_OP_BEACONS;
f078f209 915
8feceb67
VT		 916 /* Reset rssi stats */
917 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 921
6f255425
LR		 922 /* Start ANI */
923 mod_timer(&sc->sc_ani.timer,
924 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
925
8feceb67 926 } else {
04bd4638 927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 928 sc->sc_curaid = 0;
f078f209 929 }
8feceb67 930}
f078f209 931
8feceb67
VT		 932/********************************/
933/* LED functions */
934/********************************/
f078f209 935
f2bffa7e
VT		 936static void ath_led_blink_work(struct work_struct *work)
937{
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
945
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
950
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960}
961
8feceb67
VT		 962static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964{
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
f078f209 967
8feceb67
VT		 968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
8feceb67 974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
8feceb67
VT		 980 break;
981 case LED_FULL:
f2bffa7e 982 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
8feceb67
VT		 992 break;
993 default:
994 break;
f078f209 995 }
8feceb67 996}
f078f209 997
8feceb67
VT		 998static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000{
1001 int ret;
f078f209 1002
8feceb67
VT		 1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1007
8feceb67
VT		 1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015}
f078f209 1016
8feceb67
VT		 1017static void ath_unregister_led(struct ath_led *led)
1018{
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
f078f209 1022 }
f078f209
LR		 1023}
1024
8feceb67 1025static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1026{
f2bffa7e 1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034}
f078f209 1035
8feceb67
VT		 1036static void ath_init_leds(struct ath_softc *sc)
1037{
1038 char *trigger;
1039 int ret;
f078f209 1040
8feceb67
VT		 1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1046
f2bffa7e
VT		 1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
8feceb67
VT		 1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
7dcfdcd9 1056
8feceb67
VT		 1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
f078f209 1064
8feceb67
VT		 1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
f078f209 1072
8feceb67
VT		 1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
f078f209 1080
8feceb67
VT		 1081 return;
1082
1083fail:
1084 ath_deinit_leds(sc);
f078f209
LR		 1085}
1086
e97275cb 1087#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1088
500c064d
VT		 1089/*******************/
1090/* Rfkill */
1091/*******************/
1092
1093static void ath_radio_enable(struct ath_softc *sc)
1094{
1095 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1096 struct ieee80211_channel *channel = sc->hw->conf.channel;
1097 int r;
500c064d 1098
3cbb5dd7 1099 ath9k_ps_wakeup(sc);
500c064d 1100 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1101
1102 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1103
1104 if (r) {
500c064d 1105 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1106 "Unable to reset channel %u (%uMhz) ",
1107 "reset status %u\n",
1108 channel->center_freq, r);
500c064d
VT		 1109 }
1110 spin_unlock_bh(&sc->sc_resetlock);
1111
1112 ath_update_txpow(sc);
1113 if (ath_startrecv(sc) != 0) {
1114 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1115 "Unable to restart recv logic\n");
500c064d
VT		 1116 return;
1117 }
1118
1119 if (sc->sc_flags & SC_OP_BEACONS)
1120 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1121
1122 /* Re-Enable interrupts */
1123 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1124
1125 /* Enable LED */
1126 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129
1130 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1131 ath9k_ps_restore(sc);
500c064d
VT		 1132}
1133
1134static void ath_radio_disable(struct ath_softc *sc)
1135{
1136 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1137 struct ieee80211_channel *channel = sc->hw->conf.channel;
1138 int r;
500c064d 1139
3cbb5dd7 1140 ath9k_ps_wakeup(sc);
500c064d
VT		 1141 ieee80211_stop_queues(sc->hw);
1142
1143 /* Disable LED */
1144 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146
1147 /* Disable interrupts */
1148 ath9k_hw_set_interrupts(ah, 0);
1149
043a0405 1150 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1151 ath_stoprecv(sc); /* turn off frame recv */
1152 ath_flushrecv(sc); /* flush recv queue */
1153
1154 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1155 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1156 if (r) {
500c064d 1157 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1158 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1159 "reset status %u\n",
1160 channel->center_freq, r);
500c064d
VT		 1161 }
1162 spin_unlock_bh(&sc->sc_resetlock);
1163
1164 ath9k_hw_phy_disable(ah);
1165 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1166 ath9k_ps_restore(sc);
500c064d
VT		 1167}
1168
1169static bool ath_is_rfkill_set(struct ath_softc *sc)
1170{
1171 struct ath_hal *ah = sc->sc_ah;
1172
1173 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1174 ah->ah_rfkill_polarity;
1175}
1176
1177/* h/w rfkill poll function */
1178static void ath_rfkill_poll(struct work_struct *work)
1179{
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1182 bool radio_on;
1183
1184 if (sc->sc_flags & SC_OP_INVALID)
1185 return;
1186
1187 radio_on = !ath_is_rfkill_set(sc);
1188
1189 /*
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1192 */
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1195
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1202 } else {
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1205 }
1206
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209 else
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1213 }
1214
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217}
1218
1219/* s/w rfkill handler */
1220static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221{
1222 struct ath_softc *sc = data;
1223
1224 switch (state) {
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230 return 0;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1236 "radio as it is disabled by h/w\n");
500c064d
VT		 1237 return -EPERM;
1238 }
1239 ath_radio_enable(sc);
1240 }
1241 return 0;
1242 default:
1243 return -EINVAL;
1244 }
1245}
1246
1247/* Init s/w rfkill */
1248static int ath_init_sw_rfkill(struct ath_softc *sc)
1249{
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251 RFKILL_TYPE_WLAN);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254 return -ENOMEM;
1255 }
1256
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265 return 0;
1266}
1267
1268/* Deinitialize rfkill */
1269static void ath_deinit_rfkill(struct ath_softc *sc)
1270{
1271 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279}
9c84b797
S		 1280
1281static int ath_start_rfkill_poll(struct ath_softc *sc)
1282{
1283 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
39c3c2f2 1294 ath_cleanup(sc);
9c84b797
S		 1295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302}
500c064d
VT		 1303#endif /* CONFIG_RFKILL */
1304
6baff7f9 1305void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1306{
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
1310 ieee80211_free_hw(sc->hw);
1311}
1312
6baff7f9 1313void ath_detach(struct ath_softc *sc)
f078f209 1314{
8feceb67 1315 struct ieee80211_hw *hw = sc->hw;
9c84b797 1316 int i = 0;
f078f209 1317
3cbb5dd7
VN		 1318 ath9k_ps_wakeup(sc);
1319
04bd4638 1320 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1321
e97275cb 1322#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1323 ath_deinit_rfkill(sc);
1324#endif
3fcdfb4b
VT		 1325 ath_deinit_leds(sc);
1326
1327 ieee80211_unregister_hw(hw);
8feceb67
VT		 1328 ath_rx_cleanup(sc);
1329 ath_tx_cleanup(sc);
f078f209 1330
9c84b797
S		 1331 tasklet_kill(&sc->intr_tq);
1332 tasklet_kill(&sc->bcon_tasklet);
f078f209 1333
9c84b797
S		 1334 if (!(sc->sc_flags & SC_OP_INVALID))
1335 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1336
9c84b797
S		 1337 /* cleanup tx queues */
1338 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1339 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1340 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1341
1342 ath9k_hw_detach(sc->sc_ah);
826d2680 1343 ath9k_exit_debug(sc);
3cbb5dd7 1344 ath9k_ps_restore(sc);
f078f209
LR		 1345}
1346
ff37e337
S		 1347static int ath_init(u16 devid, struct ath_softc *sc)
1348{
1349 struct ath_hal *ah = NULL;
1350 int status;
1351 int error = 0, i;
1352 int csz = 0;
1353
1354 /* XXX: hardware will not be ready until ath_open() being called */
1355 sc->sc_flags |= SC_OP_INVALID;
88b126af 1356
826d2680
S		 1357 if (ath9k_init_debug(sc) < 0)
1358 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1359
1360 spin_lock_init(&sc->sc_resetlock);
aa33de09 1361 mutex_init(&sc->mutex);
ff37e337
S		 1362 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1363 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1364 (unsigned long)sc);
1365
1366 /*
1367 * Cache line size is used to size and align various
1368 * structures used to communicate with the hardware.
1369 */
88d15707 1370 ath_read_cachesize(sc, &csz);
ff37e337
S		 1371 /* XXX assert csz is non-zero */
1372 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1373
1374 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1375 if (ah == NULL) {
1376 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1377 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1378 error = -ENXIO;
1379 goto bad;
1380 }
1381 sc->sc_ah = ah;
1382
1383 /* Get the hardware key cache size. */
1384 sc->sc_keymax = ah->ah_caps.keycache_size;
1385 if (sc->sc_keymax > ATH_KEYMAX) {
1386 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1387 "Warning, using only %u entries in %u key cache\n",
1388 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1389 sc->sc_keymax = ATH_KEYMAX;
1390 }
1391
1392 /*
1393 * Reset the key cache since some parts do not
1394 * reset the contents on initial power up.
1395 */
1396 for (i = 0; i < sc->sc_keymax; i++)
1397 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1398
5f8e077c 1399 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1400 goto bad;
1401
1402 /* default to MONITOR mode */
d97809db
CM		 1403 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1404
ff37e337
S		 1405 /* Setup rate tables */
1406
1407 ath_rate_attach(sc);
1408 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1409 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1410
1411 /*
1412 * Allocate hardware transmit queues: one queue for
1413 * beacon frames and one data queue for each QoS
1414 * priority. Note that the hal handles reseting
1415 * these queues at the needed time.
1416 */
b77f483f
S		 1417 sc->beacon.beaconq = ath_beaconq_setup(ah);
1418 if (sc->beacon.beaconq == -1) {
ff37e337 1419 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1420 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1421 error = -EIO;
1422 goto bad2;
1423 }
b77f483f
S		 1424 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1425 if (sc->beacon.cabq == NULL) {
ff37e337 1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1428 error = -EIO;
1429 goto bad2;
1430 }
1431
1432 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1433 ath_cabq_update(sc);
1434
b77f483f
S		 1435 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1436 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1437
1438 /* Setup data queues */
1439 /* NB: ensure BK queue is the lowest priority h/w queue */
1440 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1441 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1442 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1443 error = -EIO;
1444 goto bad2;
1445 }
1446
1447 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1448 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1449 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1450 error = -EIO;
1451 goto bad2;
1452 }
1453 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1454 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1455 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1456 error = -EIO;
1457 goto bad2;
1458 }
1459 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1460 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1461 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1462 error = -EIO;
1463 goto bad2;
1464 }
1465
1466 /* Initializes the noise floor to a reasonable default value.
1467 * Later on this will be updated during ANI processing. */
1468
1469 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1470 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1471
1472 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473 ATH9K_CIPHER_TKIP, NULL)) {
1474 /*
1475 * Whether we should enable h/w TKIP MIC.
1476 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1477 * report WMM capable, so it's always safe to turn on
1478 * TKIP MIC in this case.
1479 */
1480 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1481 0, 1, NULL);
1482 }
1483
1484 /*
1485 * Check whether the separate key cache entries
1486 * are required to handle both tx+rx MIC keys.
1487 * With split mic keys the number of stations is limited
1488 * to 27 otherwise 59.
1489 */
1490 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491 ATH9K_CIPHER_TKIP, NULL)
1492 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493 ATH9K_CIPHER_MIC, NULL)
1494 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1495 0, NULL))
1496 sc->sc_splitmic = 1;
1497
1498 /* turn on mcast key search if possible */
1499 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1500 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1501 1, NULL);
1502
1503 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1504
1505 /* 11n Capabilities */
1506 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1507 sc->sc_flags |= SC_OP_TXAGGR;
1508 sc->sc_flags |= SC_OP_RXAGGR;
1509 }
1510
1511 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1512 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1513
1514 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1515 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1516
1517 ath9k_hw_getmac(ah, sc->sc_myaddr);
1518 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1519 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1520 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1521 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1522 }
1523
b77f483f 1524 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1525
1526 /* initialize beacon slots */
b77f483f
S		 1527 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1528 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1529
1530 /* save MISC configurations */
1531 sc->sc_config.swBeaconProcess = 1;
1532
ff37e337
S		 1533 /* setup channels and rates */
1534
5f8e077c 1535 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1536 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1537 sc->rates[IEEE80211_BAND_2GHZ];
1538 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1539 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1540 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337
S		 1541
1542 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
5f8e077c 1543 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1544 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1545 sc->rates[IEEE80211_BAND_5GHZ];
1546 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1547 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1548 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1549 }
1550
c97c92d9
VT		 1551 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1552 ath9k_hw_btcoex_enable(sc->sc_ah);
1553
ff37e337
S		 1554 return 0;
1555bad2:
1556 /* cleanup tx queues */
1557 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1558 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1559 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1560bad:
1561 if (ah)
1562 ath9k_hw_detach(ah);
1563
1564 return error;
1565}
1566
6baff7f9 1567int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1568{
8feceb67
VT		 1569 struct ieee80211_hw *hw = sc->hw;
1570 int error = 0;
f078f209 1571
04bd4638 1572 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1573
8feceb67
VT		 1574 error = ath_init(devid, sc);
1575 if (error != 0)
1576 return error;
f078f209 1577
8feceb67 1578 /* get mac address from hardware and set in mac80211 */
f078f209 1579
8feceb67 1580 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1581
9c84b797
S		 1582 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1583 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1584 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1585 IEEE80211_HW_AMPDU_AGGREGATION |
1586 IEEE80211_HW_SUPPORTS_PS |
1587 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1588
0ced0e17
JM		 1589 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1590 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1591
9c84b797
S		 1592 hw->wiphy->interface_modes =
1593 BIT(NL80211_IFTYPE_AP) |
1594 BIT(NL80211_IFTYPE_STATION) |
1595 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1596
5f8e077c
LR		 1597 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1598 hw->wiphy->strict_regulatory = true;
1599
8feceb67 1600 hw->queues = 4;
e63835b0
S		 1601 hw->max_rates = 4;
1602 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1603 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1604 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1605
8feceb67 1606 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1607
9c84b797 1608 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
9c84b797 1610 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
eb2599ca 1611 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1612 }
1613
1614 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1615 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1616 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1617 &sc->sbands[IEEE80211_BAND_5GHZ];
1618
db93e7b5
SB		 1619 /* initialize tx/rx engine */
1620 error = ath_tx_init(sc, ATH_TXBUF);
1621 if (error != 0)
1622 goto detach;
8feceb67 1623
db93e7b5
SB		 1624 error = ath_rx_init(sc, ATH_RXBUF);
1625 if (error != 0)
1626 goto detach;
8feceb67 1627
e97275cb 1628#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1629 /* Initialze h/w Rfkill */
1630 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1631 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1632
1633 /* Initialize s/w rfkill */
1634 if (ath_init_sw_rfkill(sc))
1635 goto detach;
1636#endif
1637
5f8e077c
LR		 1638 if (ath9k_is_world_regd(sc->sc_ah)) {
1639 /* Anything applied here (prior to wiphy registratoin) gets
1640 * saved on the wiphy orig_* parameters */
1641 const struct ieee80211_regdomain *regd =
1642 ath9k_world_regdomain(sc->sc_ah);
1643 hw->wiphy->custom_regulatory = true;
1644 hw->wiphy->strict_regulatory = false;
1645 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1646 ath9k_reg_apply_radar_flags(hw->wiphy);
1647 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1648 } else {
1649 /* This gets applied in the case of the absense of CRDA,
1650 * its our own custom world regulatory domain, similar to
1651 * cfg80211's but we enable passive scanning */
1652 const struct ieee80211_regdomain *regd =
1653 ath9k_default_world_regdomain();
1654 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1655 ath9k_reg_apply_radar_flags(hw->wiphy);
1656 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1657 }
1658
db93e7b5 1659 error = ieee80211_register_hw(hw);
8feceb67 1660
5f8e077c
LR		 1661 if (!ath9k_is_world_regd(sc->sc_ah))
1662 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1663
db93e7b5
SB		 1664 /* Initialize LED control */
1665 ath_init_leds(sc);
8feceb67 1666
5f8e077c 1667
8feceb67
VT		 1668 return 0;
1669detach:
1670 ath_detach(sc);
8feceb67 1671 return error;
f078f209
LR		 1672}
1673
ff37e337
S		 1674int ath_reset(struct ath_softc *sc, bool retry_tx)
1675{
1676 struct ath_hal *ah = sc->sc_ah;
030bb495 1677 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1678 int r;
ff37e337
S		 1679
1680 ath9k_hw_set_interrupts(ah, 0);
043a0405 1681 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1682 ath_stoprecv(sc);
1683 ath_flushrecv(sc);
1684
1685 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1686 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1687 if (r)
ff37e337 1688 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1689 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1690 spin_unlock_bh(&sc->sc_resetlock);
1691
1692 if (ath_startrecv(sc) != 0)
04bd4638 1693 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1694
1695 /*
1696 * We may be doing a reset in response to a request
1697 * that changes the channel so update any state that
1698 * might change as a result.
1699 */
ce111bad 1700 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1701
1702 ath_update_txpow(sc);
1703
1704 if (sc->sc_flags & SC_OP_BEACONS)
1705 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1706
1707 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1708
1709 if (retry_tx) {
1710 int i;
1711 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1712 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1713 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1714 ath_txq_schedule(sc, &sc->tx.txq[i]);
1715 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1716 }
1717 }
1718 }
1719
ae8d2858 1720 return r;
ff37e337
S		 1721}
1722
1723/*
1724 * This function will allocate both the DMA descriptor structure, and the
1725 * buffers it contains. These are used to contain the descriptors used
1726 * by the system.
1727*/
1728int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1729 struct list_head *head, const char *name,
1730 int nbuf, int ndesc)
1731{
1732#define DS2PHYS(_dd, _ds) \
1733 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1734#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1735#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1736
1737 struct ath_desc *ds;
1738 struct ath_buf *bf;
1739 int i, bsize, error;
1740
04bd4638
S		 1741 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1742 name, nbuf, ndesc);
ff37e337
S		 1743
1744 /* ath_desc must be a multiple of DWORDs */
1745 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1746 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1747 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1748 error = -ENOMEM;
1749 goto fail;
1750 }
1751
1752 dd->dd_name = name;
1753 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1754
1755 /*
1756 * Need additional DMA memory because we can't use
1757 * descriptors that cross the 4K page boundary. Assume
1758 * one skipped descriptor per 4K page.
1759 */
1760 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1761 u32 ndesc_skipped =
1762 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1763 u32 dma_len;
1764
1765 while (ndesc_skipped) {
1766 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1767 dd->dd_desc_len += dma_len;
1768
1769 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1770 };
1771 }
1772
1773 /* allocate descriptors */
7da3c55c
GJ		 1774 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1775 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1776 if (dd->dd_desc == NULL) {
1777 error = -ENOMEM;
1778 goto fail;
1779 }
1780 ds = dd->dd_desc;
04bd4638
S		 1781 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1782 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1783 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1784
1785 /* allocate buffers */
1786 bsize = sizeof(struct ath_buf) * nbuf;
1787 bf = kmalloc(bsize, GFP_KERNEL);
1788 if (bf == NULL) {
1789 error = -ENOMEM;
1790 goto fail2;
1791 }
1792 memset(bf, 0, bsize);
1793 dd->dd_bufptr = bf;
1794
1795 INIT_LIST_HEAD(head);
1796 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1797 bf->bf_desc = ds;
1798 bf->bf_daddr = DS2PHYS(dd, ds);
1799
1800 if (!(sc->sc_ah->ah_caps.hw_caps &
1801 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1802 /*
1803 * Skip descriptor addresses which can cause 4KB
1804 * boundary crossing (addr + length) with a 32 dword
1805 * descriptor fetch.
1806 */
1807 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1808 ASSERT((caddr_t) bf->bf_desc <
1809 ((caddr_t) dd->dd_desc +
1810 dd->dd_desc_len));
1811
1812 ds += ndesc;
1813 bf->bf_desc = ds;
1814 bf->bf_daddr = DS2PHYS(dd, ds);
1815 }
1816 }
1817 list_add_tail(&bf->list, head);
1818 }
1819 return 0;
1820fail2:
7da3c55c
GJ		 1821 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1822 dd->dd_desc_paddr);
ff37e337
S		 1823fail:
1824 memset(dd, 0, sizeof(*dd));
1825 return error;
1826#undef ATH_DESC_4KB_BOUND_CHECK
1827#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1828#undef DS2PHYS
1829}
1830
1831void ath_descdma_cleanup(struct ath_softc *sc,
1832 struct ath_descdma *dd,
1833 struct list_head *head)
1834{
7da3c55c
GJ		 1835 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1836 dd->dd_desc_paddr);
ff37e337
S		 1837
1838 INIT_LIST_HEAD(head);
1839 kfree(dd->dd_bufptr);
1840 memset(dd, 0, sizeof(*dd));
1841}
1842
1843int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1844{
1845 int qnum;
1846
1847 switch (queue) {
1848 case 0:
b77f483f 1849 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1850 break;
1851 case 1:
b77f483f 1852 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1853 break;
1854 case 2:
b77f483f 1855 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1856 break;
1857 case 3:
b77f483f 1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1859 break;
1860 default:
b77f483f 1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1862 break;
1863 }
1864
1865 return qnum;
1866}
1867
1868int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1869{
1870 int qnum;
1871
1872 switch (queue) {
1873 case ATH9K_WME_AC_VO:
1874 qnum = 0;
1875 break;
1876 case ATH9K_WME_AC_VI:
1877 qnum = 1;
1878 break;
1879 case ATH9K_WME_AC_BE:
1880 qnum = 2;
1881 break;
1882 case ATH9K_WME_AC_BK:
1883 qnum = 3;
1884 break;
1885 default:
1886 qnum = -1;
1887 break;
1888 }
1889
1890 return qnum;
1891}
1892
5f8e077c
LR		 1893/* XXX: Remove me once we don't depend on ath9k_channel for all
1894 * this redundant data */
1895static void ath9k_update_ichannel(struct ath_softc *sc,
1896 struct ath9k_channel *ichan)
1897{
1898 struct ieee80211_hw *hw = sc->hw;
1899 struct ieee80211_channel *chan = hw->conf.channel;
1900 struct ieee80211_conf *conf = &hw->conf;
1901
1902 ichan->channel = chan->center_freq;
1903 ichan->chan = chan;
1904
1905 if (chan->band == IEEE80211_BAND_2GHZ) {
1906 ichan->chanmode = CHANNEL_G;
1907 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1908 } else {
1909 ichan->chanmode = CHANNEL_A;
1910 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1911 }
1912
1913 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1914
1915 if (conf_is_ht(conf)) {
1916 if (conf_is_ht40(conf))
1917 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1918
1919 ichan->chanmode = ath_get_extchanmode(sc, chan,
1920 conf->channel_type);
1921 }
1922}
1923
ff37e337
S		 1924/**********************/
1925/* mac80211 callbacks */
1926/**********************/
1927
8feceb67 1928static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1929{
1930 struct ath_softc *sc = hw->priv;
8feceb67 1931 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1932 struct ath9k_channel *init_channel;
ae8d2858 1933 int r, pos;
f078f209 1934
04bd4638
S		 1935 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1936 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1937
141b38b6
S		 1938 mutex_lock(&sc->mutex);
1939
8feceb67 1940 /* setup initial channel */
f078f209 1941
5f8e077c 1942 pos = curchan->hw_value;
f078f209 1943
ff37e337 1944 init_channel = &sc->sc_ah->ah_channels[pos];
5f8e077c 1945 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1946
1947 /* Reset SERDES registers */
1948 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1949
1950 /*
1951 * The basic interface to setting the hardware in a good
1952 * state is ``reset''. On return the hardware is known to
1953 * be powered up and with interrupts disabled. This must
1954 * be followed by initialization of the appropriate bits
1955 * and then setup of the interrupt mask.
1956 */
1957 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1958 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1959 if (r) {
ff37e337 1960 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1961 "Unable to reset hardware; reset status %u "
1962 "(freq %u MHz)\n", r,
1963 curchan->center_freq);
ff37e337 1964 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1965 goto mutex_unlock;
ff37e337
S		 1966 }
1967 spin_unlock_bh(&sc->sc_resetlock);
1968
1969 /*
1970 * This is needed only to setup initial state
1971 * but it's best done after a reset.
1972 */
1973 ath_update_txpow(sc);
8feceb67 1974
ff37e337
S		 1975 /*
1976 * Setup the hardware after reset:
1977 * The receive engine is set going.
1978 * Frame transmit is handled entirely
1979 * in the frame output path; there's nothing to do
1980 * here except setup the interrupt mask.
1981 */
1982 if (ath_startrecv(sc) != 0) {
8feceb67 1983 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1984 "Unable to start recv logic\n");
141b38b6
S		 1985 r = -EIO;
1986 goto mutex_unlock;
f078f209 1987 }
8feceb67 1988
ff37e337
S		 1989 /* Setup our intr mask. */
1990 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1991 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1992 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1993
1994 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1995 sc->sc_imask |= ATH9K_INT_GTT;
1996
1997 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1998 sc->sc_imask |= ATH9K_INT_CST;
1999
ce111bad 2000 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2001
2002 sc->sc_flags &= ~SC_OP_INVALID;
2003
2004 /* Disable BMISS interrupt when we're not associated */
2005 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2006 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2007
2008 ieee80211_wake_queues(sc->hw);
2009
e97275cb 2010#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2011 r = ath_start_rfkill_poll(sc);
500c064d 2012#endif
141b38b6
S		 2013
2014mutex_unlock:
2015 mutex_unlock(&sc->mutex);
2016
ae8d2858 2017 return r;
f078f209
LR		 2018}
2019
8feceb67
VT		 2020static int ath9k_tx(struct ieee80211_hw *hw,
2021 struct sk_buff *skb)
f078f209 2022{
528f0c6b 2023 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2024 struct ath_softc *sc = hw->priv;
528f0c6b 2025 struct ath_tx_control txctl;
8feceb67 2026 int hdrlen, padsize;
528f0c6b
S		 2027
2028 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2029
8feceb67
VT		 2030 /*
2031 * As a temporary workaround, assign seq# here; this will likely need
2032 * to be cleaned up to work better with Beacon transmission and virtual
2033 * BSSes.
2034 */
2035 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2036 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2037 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2038 sc->tx.seq_no += 0x10;
8feceb67 2039 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2040 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2041 }
f078f209 2042
8feceb67
VT		 2043 /* Add the padding after the header if this is not already done */
2044 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2045 if (hdrlen & 3) {
2046 padsize = hdrlen % 4;
2047 if (skb_headroom(skb) < padsize)
2048 return -1;
2049 skb_push(skb, padsize);
2050 memmove(skb->data, skb->data + padsize, hdrlen);
2051 }
2052
528f0c6b
S		 2053 /* Check if a tx queue is available */
2054
2055 txctl.txq = ath_test_get_txq(sc, skb);
2056 if (!txctl.txq)
2057 goto exit;
2058
04bd4638 2059 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2060
528f0c6b 2061 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2062 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2063 goto exit;
8feceb67
VT		 2064 }
2065
528f0c6b
S		 2066 return 0;
2067exit:
2068 dev_kfree_skb_any(skb);
8feceb67 2069 return 0;
f078f209
LR		 2070}
2071
8feceb67 2072static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2073{
2074 struct ath_softc *sc = hw->priv;
f078f209 2075
9c84b797 2076 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2077 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2078 return;
2079 }
8feceb67 2080
141b38b6 2081 mutex_lock(&sc->mutex);
ff37e337
S		 2082
2083 ieee80211_stop_queues(sc->hw);
2084
2085 /* make sure h/w will not generate any interrupt
2086 * before setting the invalid flag. */
2087 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2088
2089 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2090 ath_drain_all_txq(sc, false);
ff37e337
S		 2091 ath_stoprecv(sc);
2092 ath9k_hw_phy_disable(sc->sc_ah);
2093 } else
b77f483f 2094 sc->rx.rxlink = NULL;
ff37e337
S		 2095
2096#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2097 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2098 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2099#endif
2100 /* disable HAL and put h/w to sleep */
2101 ath9k_hw_disable(sc->sc_ah);
2102 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2103
2104 sc->sc_flags |= SC_OP_INVALID;
500c064d 2105
141b38b6
S		 2106 mutex_unlock(&sc->mutex);
2107
04bd4638 2108 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2109}
2110
8feceb67
VT		 2111static int ath9k_add_interface(struct ieee80211_hw *hw,
2112 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2113{
2114 struct ath_softc *sc = hw->priv;
5640b08e 2115 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2116 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2117
8feceb67
VT		 2118 /* Support only vap for now */
2119
2120 if (sc->sc_nvaps)
2121 return -ENOBUFS;
2122
141b38b6
S		 2123 mutex_lock(&sc->mutex);
2124
8feceb67 2125 switch (conf->type) {
05c914fe 2126 case NL80211_IFTYPE_STATION:
d97809db 2127 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2128 break;
05c914fe 2129 case NL80211_IFTYPE_ADHOC:
d97809db 2130 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2131 break;
05c914fe 2132 case NL80211_IFTYPE_AP:
d97809db 2133 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2134 break;
2135 default:
2136 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2137 "Interface type %d not yet supported\n", conf->type);
8feceb67 2138 return -EOPNOTSUPP;
f078f209
LR		 2139 }
2140
04bd4638 2141 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2142
5640b08e
S		 2143 /* Set the VAP opmode */
2144 avp->av_opmode = ic_opmode;
2145 avp->av_bslot = -1;
2146
d97809db 2147 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2148 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2149
2150 sc->sc_vaps[0] = conf->vif;
2151 sc->sc_nvaps++;
2152
2153 /* Set the device opmode */
2154 sc->sc_ah->ah_opmode = ic_opmode;
2155
4e30ffa2
VN		 2156 /*
2157 * Enable MIB interrupts when there are hardware phy counters.
2158 * Note we only do this (at the moment) for station mode.
2159 */
2160 if (ath9k_hw_phycounters(sc->sc_ah) &&
2161 ((conf->type == NL80211_IFTYPE_STATION) ||
2162 (conf->type == NL80211_IFTYPE_ADHOC)))
2163 sc->sc_imask |= ATH9K_INT_MIB;
2164 /*
2165 * Some hardware processes the TIM IE and fires an
2166 * interrupt when the TIM bit is set. For hardware
2167 * that does, if not overridden by configuration,
2168 * enable the TIM interrupt when operating as station.
2169 */
2170 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2171 (conf->type == NL80211_IFTYPE_STATION) &&
2172 !sc->sc_config.swBeaconProcess)
2173 sc->sc_imask |= ATH9K_INT_TIM;
2174
2175 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2176
6f255425
LR		 2177 if (conf->type == NL80211_IFTYPE_AP) {
2178 /* TODO: is this a suitable place to start ANI for AP mode? */
2179 /* Start ANI */
2180 mod_timer(&sc->sc_ani.timer,
2181 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2182 }
2183
141b38b6
S		 2184 mutex_unlock(&sc->mutex);
2185
8feceb67 2186 return 0;
f078f209
LR		 2187}
2188
8feceb67
VT		 2189static void ath9k_remove_interface(struct ieee80211_hw *hw,
2190 struct ieee80211_if_init_conf *conf)
f078f209 2191{
8feceb67 2192 struct ath_softc *sc = hw->priv;
5640b08e 2193 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2194
04bd4638 2195 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2196
141b38b6
S		 2197 mutex_lock(&sc->mutex);
2198
6f255425
LR		 2199 /* Stop ANI */
2200 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2201
8feceb67 2202 /* Reclaim beacon resources */
d97809db
CM		 2203 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2204 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2205 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2206 ath_beacon_return(sc, avp);
580f0b8a 2207 }
f078f209 2208
8feceb67 2209 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2210
5640b08e
S		 2211 sc->sc_vaps[0] = NULL;
2212 sc->sc_nvaps--;
141b38b6
S		 2213
2214 mutex_unlock(&sc->mutex);
f078f209
LR		 2215}
2216
e8975581 2217static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2218{
8feceb67 2219 struct ath_softc *sc = hw->priv;
e8975581 2220 struct ieee80211_conf *conf = &hw->conf;
f078f209 2221
aa33de09 2222 mutex_lock(&sc->mutex);
141b38b6 2223
3cbb5dd7
VN		 2224 if (changed & IEEE80211_CONF_CHANGE_PS) {
2225 if (conf->flags & IEEE80211_CONF_PS) {
2226 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2227 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2228 ath9k_hw_set_interrupts(sc->sc_ah,
2229 sc->sc_imask);
2230 }
2231 ath9k_hw_setrxabort(sc->sc_ah, 1);
2232 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2233 } else {
2234 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2235 ath9k_hw_setrxabort(sc->sc_ah, 0);
2236 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2237 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2238 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2239 ath9k_hw_set_interrupts(sc->sc_ah,
2240 sc->sc_imask);
2241 }
2242 }
2243 }
2244
4797938c 2245 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2246 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2247 int pos = curchan->hw_value;
ae5eb026 2248
04bd4638
S		 2249 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2250 curchan->center_freq);
f078f209 2251
5f8e077c
LR		 2252 /* XXX: remove me eventualy */
2253 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
e11602b7 2254
ecf70441 2255 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2256
e11602b7 2257 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2258 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2259 mutex_unlock(&sc->mutex);
e11602b7
S		 2260 return -EINVAL;
2261 }
094d05dc 2262 }
f078f209 2263
5c020dc6
LR		 2264 if (changed & IEEE80211_CONF_CHANGE_POWER)
2265 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2266
aa33de09 2267 mutex_unlock(&sc->mutex);
141b38b6 2268
f078f209
LR		 2269 return 0;
2270}
2271
8feceb67
VT		 2272static int ath9k_config_interface(struct ieee80211_hw *hw,
2273 struct ieee80211_vif *vif,
2274 struct ieee80211_if_conf *conf)
c83be688 2275{
8feceb67
VT		 2276 struct ath_softc *sc = hw->priv;
2277 struct ath_hal *ah = sc->sc_ah;
5640b08e 2278 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2279 u32 rfilt = 0;
2280 int error, i;
c83be688 2281
8feceb67
VT		 2282 /* TODO: Need to decide which hw opmode to use for multi-interface
2283 * cases */
05c914fe 2284 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2285 ah->ah_opmode != NL80211_IFTYPE_AP) {
2286 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2287 ath9k_hw_setopmode(ah);
2288 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2289 /* Request full reset to get hw opmode changed properly */
2290 sc->sc_flags |= SC_OP_FULL_RESET;
2291 }
c83be688 2292
8feceb67
VT		 2293 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2294 !is_zero_ether_addr(conf->bssid)) {
2295 switch (vif->type) {
05c914fe
JB		 2296 case NL80211_IFTYPE_STATION:
2297 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2298 /* Set BSSID */
2299 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2300 sc->sc_curaid = 0;
2301 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2302 sc->sc_curaid);
c83be688 2303
8feceb67
VT		 2304 /* Set aggregation protection mode parameters */
2305 sc->sc_config.ath_aggr_prot = 0;
c83be688 2306
8feceb67 2307 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2308 "RX filter 0x%x bssid %pM aid 0x%x\n",
2309 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2310
8feceb67
VT		 2311 /* need to reconfigure the beacon */
2312 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2313
8feceb67
VT		 2314 break;
2315 default:
2316 break;
2317 }
2318 }
c83be688 2319
1f7d6cbf
S		 2320 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2321 (vif->type == NL80211_IFTYPE_AP)) {
2322 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2323 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2324 conf->enable_beacon)) {
2325 /*
2326 * Allocate and setup the beacon frame.
2327 *
2328 * Stop any previous beacon DMA. This may be
2329 * necessary, for example, when an ibss merge
2330 * causes reconfiguration; we may be called
2331 * with beacon transmission active.
2332 */
2333 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2334
1f7d6cbf
S		 2335 error = ath_beacon_alloc(sc, 0);
2336 if (error != 0)
2337 return error;
c83be688 2338
1f7d6cbf
S		 2339 ath_beacon_sync(sc, 0);
2340 }
8feceb67 2341 }
c83be688 2342
8feceb67 2343 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2344 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2345 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2346 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2347 ath9k_hw_keysetmac(sc->sc_ah,
2348 (u16)i,
2349 sc->sc_curbssid);
2350 }
c83be688 2351
8feceb67 2352 /* Only legacy IBSS for now */
05c914fe 2353 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2354 ath_update_chainmask(sc, 0);
f078f209 2355
8feceb67
VT		 2356 return 0;
2357}
f078f209 2358
8feceb67
VT		 2359#define SUPPORTED_FILTERS \
2360 (FIF_PROMISC_IN_BSS | \
2361 FIF_ALLMULTI | \
2362 FIF_CONTROL | \
2363 FIF_OTHER_BSS | \
2364 FIF_BCN_PRBRESP_PROMISC | \
2365 FIF_FCSFAIL)
c83be688 2366
8feceb67
VT		 2367/* FIXME: sc->sc_full_reset ? */
2368static void ath9k_configure_filter(struct ieee80211_hw *hw,
2369 unsigned int changed_flags,
2370 unsigned int *total_flags,
2371 int mc_count,
2372 struct dev_mc_list *mclist)
2373{
2374 struct ath_softc *sc = hw->priv;
2375 u32 rfilt;
f078f209 2376
8feceb67
VT		 2377 changed_flags &= SUPPORTED_FILTERS;
2378 *total_flags &= SUPPORTED_FILTERS;
f078f209 2379
b77f483f 2380 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2381 rfilt = ath_calcrxfilter(sc);
2382 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2383
8feceb67
VT		 2384 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2385 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2386 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2387 }
f078f209 2388
b77f483f 2389 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2390}
f078f209 2391
8feceb67
VT		 2392static void ath9k_sta_notify(struct ieee80211_hw *hw,
2393 struct ieee80211_vif *vif,
2394 enum sta_notify_cmd cmd,
17741cdc 2395 struct ieee80211_sta *sta)
8feceb67
VT		 2396{
2397 struct ath_softc *sc = hw->priv;
f078f209 2398
8feceb67
VT		 2399 switch (cmd) {
2400 case STA_NOTIFY_ADD:
5640b08e 2401 ath_node_attach(sc, sta);
8feceb67
VT		 2402 break;
2403 case STA_NOTIFY_REMOVE:
b5aa9bf9 2404 ath_node_detach(sc, sta);
8feceb67
VT		 2405 break;
2406 default:
2407 break;
2408 }
f078f209
LR		 2409}
2410
141b38b6 2411static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2412 const struct ieee80211_tx_queue_params *params)
f078f209 2413{
8feceb67
VT		 2414 struct ath_softc *sc = hw->priv;
2415 struct ath9k_tx_queue_info qi;
2416 int ret = 0, qnum;
f078f209 2417
8feceb67
VT		 2418 if (queue >= WME_NUM_AC)
2419 return 0;
f078f209 2420
141b38b6
S		 2421 mutex_lock(&sc->mutex);
2422
8feceb67
VT		 2423 qi.tqi_aifs = params->aifs;
2424 qi.tqi_cwmin = params->cw_min;
2425 qi.tqi_cwmax = params->cw_max;
2426 qi.tqi_burstTime = params->txop;
2427 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2428
8feceb67 2429 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2430 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2431 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2432 queue, qnum, params->aifs, params->cw_min,
2433 params->cw_max, params->txop);
f078f209 2434
8feceb67
VT		 2435 ret = ath_txq_update(sc, qnum, &qi);
2436 if (ret)
04bd4638 2437 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2438
141b38b6
S		 2439 mutex_unlock(&sc->mutex);
2440
8feceb67
VT		 2441 return ret;
2442}
f078f209 2443
8feceb67
VT		 2444static int ath9k_set_key(struct ieee80211_hw *hw,
2445 enum set_key_cmd cmd,
dc822b5d
JB		 2446 struct ieee80211_vif *vif,
2447 struct ieee80211_sta *sta,
8feceb67
VT		 2448 struct ieee80211_key_conf *key)
2449{
2450 struct ath_softc *sc = hw->priv;
2451 int ret = 0;
f078f209 2452
141b38b6 2453 mutex_lock(&sc->mutex);
3cbb5dd7 2454 ath9k_ps_wakeup(sc);
04bd4638 2455 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2456
8feceb67
VT		 2457 switch (cmd) {
2458 case SET_KEY:
dc822b5d 2459 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2460 if (ret >= 0) {
2461 key->hw_key_idx = ret;
8feceb67
VT		 2462 /* push IV and Michael MIC generation to stack */
2463 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2464 if (key->alg == ALG_TKIP)
2465 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2466 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2467 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2468 ret = 0;
8feceb67
VT		 2469 }
2470 break;
2471 case DISABLE_KEY:
2472 ath_key_delete(sc, key);
8feceb67
VT		 2473 break;
2474 default:
2475 ret = -EINVAL;
2476 }
f078f209 2477
3cbb5dd7 2478 ath9k_ps_restore(sc);
141b38b6
S		 2479 mutex_unlock(&sc->mutex);
2480
8feceb67
VT		 2481 return ret;
2482}
f078f209 2483
8feceb67
VT		 2484static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2485 struct ieee80211_vif *vif,
2486 struct ieee80211_bss_conf *bss_conf,
2487 u32 changed)
2488{
2489 struct ath_softc *sc = hw->priv;
f078f209 2490
141b38b6
S		 2491 mutex_lock(&sc->mutex);
2492
8feceb67 2493 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2494 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2495 bss_conf->use_short_preamble);
2496 if (bss_conf->use_short_preamble)
2497 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2498 else
2499 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2500 }
f078f209 2501
8feceb67 2502 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2503 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2504 bss_conf->use_cts_prot);
2505 if (bss_conf->use_cts_prot &&
2506 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2507 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2508 else
2509 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2510 }
f078f209 2511
8feceb67 2512 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2513 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2514 bss_conf->assoc);
5640b08e 2515 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2516 }
141b38b6
S		 2517
2518 mutex_unlock(&sc->mutex);
8feceb67 2519}
f078f209 2520
8feceb67
VT		 2521static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2522{
2523 u64 tsf;
2524 struct ath_softc *sc = hw->priv;
f078f209 2525
141b38b6
S		 2526 mutex_lock(&sc->mutex);
2527 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2528 mutex_unlock(&sc->mutex);
f078f209 2529
8feceb67
VT		 2530 return tsf;
2531}
f078f209 2532
3b5d665b
AF		 2533static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2534{
2535 struct ath_softc *sc = hw->priv;
3b5d665b 2536
141b38b6
S		 2537 mutex_lock(&sc->mutex);
2538 ath9k_hw_settsf64(sc->sc_ah, tsf);
2539 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2540}
2541
8feceb67
VT		 2542static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2543{
2544 struct ath_softc *sc = hw->priv;
c83be688 2545
141b38b6
S		 2546 mutex_lock(&sc->mutex);
2547 ath9k_hw_reset_tsf(sc->sc_ah);
2548 mutex_unlock(&sc->mutex);
8feceb67 2549}
f078f209 2550
8feceb67 2551static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2552 enum ieee80211_ampdu_mlme_action action,
2553 struct ieee80211_sta *sta,
2554 u16 tid, u16 *ssn)
8feceb67
VT		 2555{
2556 struct ath_softc *sc = hw->priv;
2557 int ret = 0;
f078f209 2558
8feceb67
VT		 2559 switch (action) {
2560 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2561 if (!(sc->sc_flags & SC_OP_RXAGGR))
2562 ret = -ENOTSUPP;
8feceb67
VT		 2563 break;
2564 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2565 break;
2566 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2567 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2568 if (ret < 0)
2569 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2570 "Unable to start TX aggregation\n");
8feceb67 2571 else
17741cdc 2572 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2573 break;
2574 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2575 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2576 if (ret < 0)
2577 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2578 "Unable to stop TX aggregation\n");
f078f209 2579
17741cdc 2580 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2581 break;
8469cdef
S		 2582 case IEEE80211_AMPDU_TX_RESUME:
2583 ath_tx_aggr_resume(sc, sta, tid);
2584 break;
8feceb67 2585 default:
04bd4638 2586 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2587 }
2588
2589 return ret;
f078f209
LR		 2590}
2591
6baff7f9 2592struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2593 .tx = ath9k_tx,
2594 .start = ath9k_start,
2595 .stop = ath9k_stop,
2596 .add_interface = ath9k_add_interface,
2597 .remove_interface = ath9k_remove_interface,
2598 .config = ath9k_config,
2599 .config_interface = ath9k_config_interface,
2600 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2601 .sta_notify = ath9k_sta_notify,
2602 .conf_tx = ath9k_conf_tx,
8feceb67 2603 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2604 .set_key = ath9k_set_key,
8feceb67 2605 .get_tsf = ath9k_get_tsf,
3b5d665b 2606 .set_tsf = ath9k_set_tsf,
8feceb67 2607 .reset_tsf = ath9k_reset_tsf,
4233df6b 2608 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2609};
2610
392dff83
BP		 2611static struct {
2612 u32 version;
2613 const char * name;
2614} ath_mac_bb_names[] = {
2615 { AR_SREV_VERSION_5416_PCI, "5416" },
2616 { AR_SREV_VERSION_5416_PCIE, "5418" },
2617 { AR_SREV_VERSION_9100, "9100" },
2618 { AR_SREV_VERSION_9160, "9160" },
2619 { AR_SREV_VERSION_9280, "9280" },
2620 { AR_SREV_VERSION_9285, "9285" }
2621};
2622
2623static struct {
2624 u16 version;
2625 const char * name;
2626} ath_rf_names[] = {
2627 { 0, "5133" },
2628 { AR_RAD5133_SREV_MAJOR, "5133" },
2629 { AR_RAD5122_SREV_MAJOR, "5122" },
2630 { AR_RAD2133_SREV_MAJOR, "2133" },
2631 { AR_RAD2122_SREV_MAJOR, "2122" }
2632};
2633
2634/*
2635 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2636 */
6baff7f9 2637const char *
392dff83
BP		 2638ath_mac_bb_name(u32 mac_bb_version)
2639{
2640 int i;
2641
2642 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2643 if (ath_mac_bb_names[i].version == mac_bb_version) {
2644 return ath_mac_bb_names[i].name;
2645 }
2646 }
2647
2648 return "????";
2649}
2650
2651/*
2652 * Return the RF name. "????" is returned if the RF is unknown.
2653 */
6baff7f9 2654const char *
392dff83
BP		 2655ath_rf_name(u16 rf_version)
2656{
2657 int i;
2658
2659 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2660 if (ath_rf_names[i].version == rf_version) {
2661 return ath_rf_names[i].name;
2662 }
2663 }
2664
2665 return "????";
2666}
2667
6baff7f9 2668static int __init ath9k_init(void)
f078f209 2669{
ca8a8560
VT		 2670 int error;
2671
ca8a8560
VT		 2672 /* Register rate control algorithm */
2673 error = ath_rate_control_register();
2674 if (error != 0) {
2675 printk(KERN_ERR
b51bb3cd
LR		 2676 "ath9k: Unable to register rate control "
2677 "algorithm: %d\n",
ca8a8560 2678 error);
6baff7f9 2679 goto err_out;
ca8a8560
VT		 2680 }
2681
6baff7f9
GJ		 2682 error = ath_pci_init();
2683 if (error < 0) {
f078f209 2684 printk(KERN_ERR
b51bb3cd 2685 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2686 error = -ENODEV;
2687 goto err_rate_unregister;
f078f209
LR		 2688 }
2689
09329d37
GJ		 2690 error = ath_ahb_init();
2691 if (error < 0) {
2692 error = -ENODEV;
2693 goto err_pci_exit;
2694 }
2695
f078f209 2696 return 0;
6baff7f9 2697
09329d37
GJ		 2698 err_pci_exit:
2699 ath_pci_exit();
2700
6baff7f9
GJ		 2701 err_rate_unregister:
2702 ath_rate_control_unregister();
2703 err_out:
2704 return error;
f078f209 2705}
6baff7f9 2706module_init(ath9k_init);
f078f209 2707
6baff7f9 2708static void __exit ath9k_exit(void)
f078f209 2709{
09329d37 2710 ath_ahb_exit();
6baff7f9 2711 ath_pci_exit();
ca8a8560 2712 ath_rate_control_unregister();
04bd4638 2713 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2714}
6baff7f9 2715module_exit(ath9k_exit);
Linux kernel - Deliverables
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