Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 S |
61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
62 | struct list_head *bf_q, | |
63 | int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 VT |
67 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
68 | int txok); | |
69 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, | |
8a92e2ee | 70 | int nbad, int txok, bool update_rc); |
c4288390 | 71 | |
e8324357 S |
72 | /*********************/ |
73 | /* Aggregation logic */ | |
74 | /*********************/ | |
f078f209 | 75 | |
a37c2c79 | 76 | static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
f078f209 LR |
77 | { |
78 | struct ath_atx_tid *tid; | |
79 | tid = ATH_AN_2_TID(an, tidno); | |
80 | ||
a37c2c79 S |
81 | if (tid->state & AGGR_ADDBA_COMPLETE || |
82 | tid->state & AGGR_ADDBA_PROGRESS) | |
f078f209 LR |
83 | return 1; |
84 | else | |
85 | return 0; | |
86 | } | |
87 | ||
e8324357 | 88 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 89 | { |
e8324357 | 90 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 91 | |
e8324357 S |
92 | if (tid->paused) |
93 | return; | |
ff37e337 | 94 | |
e8324357 S |
95 | if (tid->sched) |
96 | return; | |
ff37e337 | 97 | |
e8324357 S |
98 | tid->sched = true; |
99 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 100 | |
e8324357 S |
101 | if (ac->sched) |
102 | return; | |
f078f209 | 103 | |
e8324357 S |
104 | ac->sched = true; |
105 | list_add_tail(&ac->list, &txq->axq_acq); | |
106 | } | |
f078f209 | 107 | |
e8324357 S |
108 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
109 | { | |
110 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 111 | |
e8324357 S |
112 | spin_lock_bh(&txq->axq_lock); |
113 | tid->paused++; | |
114 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
115 | } |
116 | ||
e8324357 | 117 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 118 | { |
e8324357 | 119 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 120 | |
e8324357 S |
121 | ASSERT(tid->paused > 0); |
122 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 123 | |
e8324357 | 124 | tid->paused--; |
f078f209 | 125 | |
e8324357 S |
126 | if (tid->paused > 0) |
127 | goto unlock; | |
f078f209 | 128 | |
e8324357 S |
129 | if (list_empty(&tid->buf_q)) |
130 | goto unlock; | |
f078f209 | 131 | |
e8324357 S |
132 | ath_tx_queue_tid(txq, tid); |
133 | ath_txq_schedule(sc, txq); | |
134 | unlock: | |
135 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 136 | } |
f078f209 | 137 | |
e8324357 | 138 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 139 | { |
e8324357 S |
140 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
141 | struct ath_buf *bf; | |
142 | struct list_head bf_head; | |
143 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 144 | |
e8324357 S |
145 | ASSERT(tid->paused > 0); |
146 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 147 | |
e8324357 | 148 | tid->paused--; |
f078f209 | 149 | |
e8324357 S |
150 | if (tid->paused > 0) { |
151 | spin_unlock_bh(&txq->axq_lock); | |
152 | return; | |
153 | } | |
f078f209 | 154 | |
e8324357 S |
155 | while (!list_empty(&tid->buf_q)) { |
156 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
157 | ASSERT(!bf_isretried(bf)); | |
d43f3015 | 158 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 159 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 160 | } |
f078f209 | 161 | |
e8324357 | 162 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 163 | } |
f078f209 | 164 | |
e8324357 S |
165 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
166 | int seqno) | |
528f0c6b | 167 | { |
e8324357 | 168 | int index, cindex; |
f078f209 | 169 | |
e8324357 S |
170 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
171 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 172 | |
e8324357 | 173 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 174 | |
e8324357 S |
175 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
176 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
177 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
178 | } | |
528f0c6b | 179 | } |
f078f209 | 180 | |
e8324357 S |
181 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
182 | struct ath_buf *bf) | |
528f0c6b | 183 | { |
e8324357 | 184 | int index, cindex; |
528f0c6b | 185 | |
e8324357 S |
186 | if (bf_isretried(bf)) |
187 | return; | |
528f0c6b | 188 | |
e8324357 S |
189 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
190 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 191 | |
e8324357 S |
192 | ASSERT(tid->tx_buf[cindex] == NULL); |
193 | tid->tx_buf[cindex] = bf; | |
f078f209 | 194 | |
e8324357 S |
195 | if (index >= ((tid->baw_tail - tid->baw_head) & |
196 | (ATH_TID_MAX_BUFS - 1))) { | |
197 | tid->baw_tail = cindex; | |
198 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 199 | } |
f078f209 LR |
200 | } |
201 | ||
202 | /* | |
e8324357 S |
203 | * TODO: For frame(s) that are in the retry state, we will reuse the |
204 | * sequence number(s) without setting the retry bit. The | |
205 | * alternative is to give up on these and BAR the receiver's window | |
206 | * forward. | |
f078f209 | 207 | */ |
e8324357 S |
208 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
209 | struct ath_atx_tid *tid) | |
f078f209 | 210 | |
f078f209 | 211 | { |
e8324357 S |
212 | struct ath_buf *bf; |
213 | struct list_head bf_head; | |
214 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 215 | |
e8324357 S |
216 | for (;;) { |
217 | if (list_empty(&tid->buf_q)) | |
218 | break; | |
f078f209 | 219 | |
d43f3015 S |
220 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
221 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 222 | |
e8324357 S |
223 | if (bf_isretried(bf)) |
224 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 225 | |
e8324357 S |
226 | spin_unlock(&txq->axq_lock); |
227 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
228 | spin_lock(&txq->axq_lock); | |
229 | } | |
f078f209 | 230 | |
e8324357 S |
231 | tid->seq_next = tid->seq_start; |
232 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
233 | } |
234 | ||
e8324357 | 235 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) |
f078f209 | 236 | { |
e8324357 S |
237 | struct sk_buff *skb; |
238 | struct ieee80211_hdr *hdr; | |
f078f209 | 239 | |
e8324357 S |
240 | bf->bf_state.bf_type |= BUF_RETRY; |
241 | bf->bf_retries++; | |
f078f209 | 242 | |
e8324357 S |
243 | skb = bf->bf_mpdu; |
244 | hdr = (struct ieee80211_hdr *)skb->data; | |
245 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
246 | } |
247 | ||
d43f3015 S |
248 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
249 | { | |
250 | struct ath_buf *tbf; | |
251 | ||
252 | spin_lock_bh(&sc->tx.txbuflock); | |
253 | ASSERT(!list_empty((&sc->tx.txbuf))); | |
254 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
255 | list_del(&tbf->list); | |
256 | spin_unlock_bh(&sc->tx.txbuflock); | |
257 | ||
258 | ATH_TXBUF_RESET(tbf); | |
259 | ||
260 | tbf->bf_mpdu = bf->bf_mpdu; | |
261 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
262 | *(tbf->bf_desc) = *(bf->bf_desc); | |
263 | tbf->bf_state = bf->bf_state; | |
264 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
265 | ||
266 | return tbf; | |
267 | } | |
268 | ||
269 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
270 | struct ath_buf *bf, struct list_head *bf_q, | |
271 | int txok) | |
f078f209 | 272 | { |
e8324357 S |
273 | struct ath_node *an = NULL; |
274 | struct sk_buff *skb; | |
1286ec6d S |
275 | struct ieee80211_sta *sta; |
276 | struct ieee80211_hdr *hdr; | |
e8324357 | 277 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 278 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 279 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 280 | struct list_head bf_head, bf_pending; |
0934af23 | 281 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 282 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
283 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
284 | bool rc_update = true; | |
f078f209 | 285 | |
e8324357 | 286 | skb = (struct sk_buff *)bf->bf_mpdu; |
1286ec6d S |
287 | hdr = (struct ieee80211_hdr *)skb->data; |
288 | ||
289 | rcu_read_lock(); | |
f078f209 | 290 | |
1286ec6d S |
291 | sta = ieee80211_find_sta(sc->hw, hdr->addr1); |
292 | if (!sta) { | |
293 | rcu_read_unlock(); | |
294 | return; | |
f078f209 LR |
295 | } |
296 | ||
1286ec6d S |
297 | an = (struct ath_node *)sta->drv_priv; |
298 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
299 | ||
e8324357 | 300 | isaggr = bf_isaggr(bf); |
d43f3015 | 301 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 302 | |
d43f3015 S |
303 | if (isaggr && txok) { |
304 | if (ATH_DS_TX_BA(ds)) { | |
305 | seq_st = ATH_DS_BA_SEQ(ds); | |
306 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
307 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 308 | } else { |
d43f3015 S |
309 | /* |
310 | * AR5416 can become deaf/mute when BA | |
311 | * issue happens. Chip needs to be reset. | |
312 | * But AP code may have sychronization issues | |
313 | * when perform internal reset in this routine. | |
314 | * Only enable reset in STA mode for now. | |
315 | */ | |
2660b81a | 316 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 317 | needreset = 1; |
e8324357 | 318 | } |
f078f209 LR |
319 | } |
320 | ||
e8324357 S |
321 | INIT_LIST_HEAD(&bf_pending); |
322 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 323 | |
0934af23 | 324 | nbad = ath_tx_num_badfrms(sc, bf, txok); |
e8324357 S |
325 | while (bf) { |
326 | txfail = txpending = 0; | |
327 | bf_next = bf->bf_next; | |
f078f209 | 328 | |
e8324357 S |
329 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
330 | /* transmit completion, subframe is | |
331 | * acked by block ack */ | |
0934af23 | 332 | acked_cnt++; |
e8324357 S |
333 | } else if (!isaggr && txok) { |
334 | /* transmit completion */ | |
0934af23 | 335 | acked_cnt++; |
e8324357 | 336 | } else { |
e8324357 S |
337 | if (!(tid->state & AGGR_CLEANUP) && |
338 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
339 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
340 | ath_tx_set_retry(sc, bf); | |
341 | txpending = 1; | |
342 | } else { | |
343 | bf->bf_state.bf_type |= BUF_XRETRY; | |
344 | txfail = 1; | |
345 | sendbar = 1; | |
0934af23 | 346 | txfail_cnt++; |
e8324357 S |
347 | } |
348 | } else { | |
349 | /* | |
350 | * cleanup in progress, just fail | |
351 | * the un-acked sub-frames | |
352 | */ | |
353 | txfail = 1; | |
354 | } | |
355 | } | |
f078f209 | 356 | |
e8324357 | 357 | if (bf_next == NULL) { |
d43f3015 | 358 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
359 | } else { |
360 | ASSERT(!list_empty(bf_q)); | |
d43f3015 | 361 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 362 | } |
f078f209 | 363 | |
e8324357 S |
364 | if (!txpending) { |
365 | /* | |
366 | * complete the acked-ones/xretried ones; update | |
367 | * block-ack window | |
368 | */ | |
369 | spin_lock_bh(&txq->axq_lock); | |
370 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
371 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 372 | |
8a92e2ee VT |
373 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
374 | ath_tx_rc_status(bf, ds, nbad, txok, true); | |
375 | rc_update = false; | |
376 | } else { | |
377 | ath_tx_rc_status(bf, ds, nbad, txok, false); | |
378 | } | |
379 | ||
e8324357 S |
380 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); |
381 | } else { | |
d43f3015 | 382 | /* retry the un-acked ones */ |
e8324357 S |
383 | if (bf->bf_next == NULL && |
384 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | |
385 | struct ath_buf *tbf; | |
f078f209 | 386 | |
d43f3015 S |
387 | tbf = ath_clone_txbuf(sc, bf_last); |
388 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); | |
e8324357 S |
389 | list_add_tail(&tbf->list, &bf_head); |
390 | } else { | |
391 | /* | |
392 | * Clear descriptor status words for | |
393 | * software retry | |
394 | */ | |
d43f3015 | 395 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
396 | } |
397 | ||
398 | /* | |
399 | * Put this buffer to the temporary pending | |
400 | * queue to retain ordering | |
401 | */ | |
402 | list_splice_tail_init(&bf_head, &bf_pending); | |
403 | } | |
404 | ||
405 | bf = bf_next; | |
f078f209 | 406 | } |
f078f209 | 407 | |
e8324357 | 408 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
409 | if (tid->baw_head == tid->baw_tail) { |
410 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
411 | tid->addba_exchangeattempts = 0; | |
e8324357 | 412 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 413 | |
e8324357 S |
414 | /* send buffered frames as singles */ |
415 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 416 | } |
1286ec6d | 417 | rcu_read_unlock(); |
e8324357 S |
418 | return; |
419 | } | |
f078f209 | 420 | |
d43f3015 | 421 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
422 | if (!list_empty(&bf_pending)) { |
423 | spin_lock_bh(&txq->axq_lock); | |
424 | list_splice(&bf_pending, &tid->buf_q); | |
425 | ath_tx_queue_tid(txq, tid); | |
426 | spin_unlock_bh(&txq->axq_lock); | |
427 | } | |
102e0572 | 428 | |
1286ec6d S |
429 | rcu_read_unlock(); |
430 | ||
e8324357 S |
431 | if (needreset) |
432 | ath_reset(sc, false); | |
e8324357 | 433 | } |
f078f209 | 434 | |
e8324357 S |
435 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
436 | struct ath_atx_tid *tid) | |
f078f209 | 437 | { |
e8324357 | 438 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
439 | struct sk_buff *skb; |
440 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 441 | struct ieee80211_tx_rate *rates; |
e8324357 | 442 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 443 | u32 max_4ms_framelen, frmlen; |
e8324357 S |
444 | u16 aggr_limit, legacy = 0, maxampdu; |
445 | int i; | |
528f0c6b S |
446 | |
447 | skb = (struct sk_buff *)bf->bf_mpdu; | |
448 | tx_info = IEEE80211_SKB_CB(skb); | |
e63835b0 | 449 | rates = tx_info->control.rates; |
d43f3015 | 450 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 451 | |
e8324357 S |
452 | /* |
453 | * Find the lowest frame length among the rate series that will have a | |
454 | * 4ms transmit duration. | |
455 | * TODO - TXOP limit needs to be considered. | |
456 | */ | |
457 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 458 | |
e8324357 S |
459 | for (i = 0; i < 4; i++) { |
460 | if (rates[i].count) { | |
461 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
462 | legacy = 1; | |
463 | break; | |
464 | } | |
465 | ||
d43f3015 S |
466 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
467 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
468 | } |
469 | } | |
e63835b0 | 470 | |
f078f209 | 471 | /* |
e8324357 S |
472 | * limit aggregate size by the minimum rate if rate selected is |
473 | * not a probe rate, if rate selected is a probe rate then | |
474 | * avoid aggregation of this packet. | |
f078f209 | 475 | */ |
e8324357 S |
476 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
477 | return 0; | |
f078f209 | 478 | |
d43f3015 | 479 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT); |
f078f209 | 480 | |
e8324357 S |
481 | /* |
482 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
483 | * The IE, however can hold upto 65536, which shows up here | |
484 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 485 | */ |
e8324357 S |
486 | maxampdu = tid->an->maxampdu; |
487 | if (maxampdu) | |
488 | aggr_limit = min(aggr_limit, maxampdu); | |
f078f209 | 489 | |
e8324357 S |
490 | return aggr_limit; |
491 | } | |
f078f209 | 492 | |
e8324357 | 493 | /* |
d43f3015 | 494 | * Returns the number of delimiters to be added to |
e8324357 | 495 | * meet the minimum required mpdudensity. |
d43f3015 | 496 | * caller should make sure that the rate is HT rate . |
e8324357 S |
497 | */ |
498 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
499 | struct ath_buf *bf, u16 frmlen) | |
500 | { | |
501 | struct ath_rate_table *rt = sc->cur_rate_table; | |
502 | struct sk_buff *skb = bf->bf_mpdu; | |
503 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
504 | u32 nsymbits, nsymbols, mpdudensity; | |
505 | u16 minlen; | |
506 | u8 rc, flags, rix; | |
507 | int width, half_gi, ndelim, mindelim; | |
508 | ||
509 | /* Select standard number of delimiters based on frame length alone */ | |
510 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
511 | |
512 | /* | |
e8324357 S |
513 | * If encryption enabled, hardware requires some more padding between |
514 | * subframes. | |
515 | * TODO - this could be improved to be dependent on the rate. | |
516 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 517 | */ |
e8324357 S |
518 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
519 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 520 | |
e8324357 S |
521 | /* |
522 | * Convert desired mpdu density from microeconds to bytes based | |
523 | * on highest rate in rate series (i.e. first rate) to determine | |
524 | * required minimum length for subframe. Take into account | |
525 | * whether high rate is 20 or 40Mhz and half or full GI. | |
526 | */ | |
527 | mpdudensity = tid->an->mpdudensity; | |
f078f209 | 528 | |
e8324357 S |
529 | /* |
530 | * If there is no mpdu density restriction, no further calculation | |
531 | * is needed. | |
532 | */ | |
533 | if (mpdudensity == 0) | |
534 | return ndelim; | |
f078f209 | 535 | |
e8324357 S |
536 | rix = tx_info->control.rates[0].idx; |
537 | flags = tx_info->control.rates[0].flags; | |
538 | rc = rt->info[rix].ratecode; | |
539 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
540 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 541 | |
e8324357 S |
542 | if (half_gi) |
543 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
544 | else | |
545 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
f078f209 | 546 | |
e8324357 S |
547 | if (nsymbols == 0) |
548 | nsymbols = 1; | |
f078f209 | 549 | |
e8324357 S |
550 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
551 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 552 | |
e8324357 | 553 | if (frmlen < minlen) { |
e8324357 S |
554 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
555 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
556 | } |
557 | ||
e8324357 | 558 | return ndelim; |
f078f209 LR |
559 | } |
560 | ||
e8324357 | 561 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
d43f3015 S |
562 | struct ath_atx_tid *tid, |
563 | struct list_head *bf_q) | |
f078f209 | 564 | { |
e8324357 | 565 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
566 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
567 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
568 | u16 aggr_limit = 0, al = 0, bpad = 0, |
569 | al_delta, h_baw = tid->baw_size / 2; | |
570 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 571 | |
e8324357 | 572 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 573 | |
e8324357 S |
574 | do { |
575 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 576 | |
d43f3015 | 577 | /* do not step over block-ack window */ |
e8324357 S |
578 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
579 | status = ATH_AGGR_BAW_CLOSED; | |
580 | break; | |
581 | } | |
f078f209 | 582 | |
e8324357 S |
583 | if (!rl) { |
584 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
585 | rl = 1; | |
586 | } | |
f078f209 | 587 | |
d43f3015 | 588 | /* do not exceed aggregation limit */ |
e8324357 | 589 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 590 | |
d43f3015 S |
591 | if (nframes && |
592 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
593 | status = ATH_AGGR_LIMITED; |
594 | break; | |
595 | } | |
f078f209 | 596 | |
d43f3015 S |
597 | /* do not exceed subframe limit */ |
598 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
599 | status = ATH_AGGR_LIMITED; |
600 | break; | |
601 | } | |
d43f3015 | 602 | nframes++; |
f078f209 | 603 | |
d43f3015 | 604 | /* add padding for previous frame to aggregation length */ |
e8324357 | 605 | al += bpad + al_delta; |
f078f209 | 606 | |
e8324357 S |
607 | /* |
608 | * Get the delimiters needed to meet the MPDU | |
609 | * density for this node. | |
610 | */ | |
611 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 612 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 613 | |
e8324357 | 614 | bf->bf_next = NULL; |
d43f3015 | 615 | bf->bf_desc->ds_link = 0; |
f078f209 | 616 | |
d43f3015 | 617 | /* link buffers of this frame to the aggregate */ |
e8324357 | 618 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
619 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
620 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
621 | if (bf_prev) { |
622 | bf_prev->bf_next = bf; | |
d43f3015 | 623 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
624 | } |
625 | bf_prev = bf; | |
e8324357 | 626 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 627 | |
e8324357 S |
628 | bf_first->bf_al = al; |
629 | bf_first->bf_nframes = nframes; | |
d43f3015 | 630 | |
e8324357 S |
631 | return status; |
632 | #undef PADBYTES | |
633 | } | |
f078f209 | 634 | |
e8324357 S |
635 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
636 | struct ath_atx_tid *tid) | |
637 | { | |
d43f3015 | 638 | struct ath_buf *bf; |
e8324357 S |
639 | enum ATH_AGGR_STATUS status; |
640 | struct list_head bf_q; | |
f078f209 | 641 | |
e8324357 S |
642 | do { |
643 | if (list_empty(&tid->buf_q)) | |
644 | return; | |
f078f209 | 645 | |
e8324357 S |
646 | INIT_LIST_HEAD(&bf_q); |
647 | ||
d43f3015 | 648 | status = ath_tx_form_aggr(sc, tid, &bf_q); |
f078f209 | 649 | |
f078f209 | 650 | /* |
d43f3015 S |
651 | * no frames picked up to be aggregated; |
652 | * block-ack window is not open. | |
f078f209 | 653 | */ |
e8324357 S |
654 | if (list_empty(&bf_q)) |
655 | break; | |
f078f209 | 656 | |
e8324357 | 657 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 658 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 659 | |
d43f3015 | 660 | /* if only one frame, send as non-aggregate */ |
e8324357 | 661 | if (bf->bf_nframes == 1) { |
e8324357 | 662 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 663 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
664 | ath_buf_set_rate(sc, bf); |
665 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
666 | continue; | |
667 | } | |
f078f209 | 668 | |
d43f3015 | 669 | /* setup first desc of aggregate */ |
e8324357 S |
670 | bf->bf_state.bf_type |= BUF_AGGR; |
671 | ath_buf_set_rate(sc, bf); | |
672 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 673 | |
d43f3015 S |
674 | /* anchor last desc of aggregate */ |
675 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 676 | |
e8324357 | 677 | txq->axq_aggr_depth++; |
e8324357 | 678 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
f078f209 | 679 | |
e8324357 S |
680 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
681 | status != ATH_AGGR_BAW_CLOSED); | |
682 | } | |
683 | ||
684 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
685 | u16 tid, u16 *ssn) | |
686 | { | |
687 | struct ath_atx_tid *txtid; | |
688 | struct ath_node *an; | |
689 | ||
690 | an = (struct ath_node *)sta->drv_priv; | |
691 | ||
692 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
693 | txtid = ATH_AN_2_TID(an, tid); | |
694 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
695 | ath_tx_pause_tid(sc, txtid); | |
d22b0022 | 696 | *ssn = txtid->seq_start; |
f078f209 LR |
697 | } |
698 | ||
e8324357 S |
699 | return 0; |
700 | } | |
f078f209 | 701 | |
e8324357 S |
702 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
703 | { | |
704 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
705 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
706 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
707 | struct ath_buf *bf; | |
708 | struct list_head bf_head; | |
709 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 710 | |
e8324357 S |
711 | if (txtid->state & AGGR_CLEANUP) |
712 | return 0; | |
f078f209 | 713 | |
e8324357 S |
714 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
715 | txtid->addba_exchangeattempts = 0; | |
716 | return 0; | |
717 | } | |
f078f209 | 718 | |
e8324357 S |
719 | ath_tx_pause_tid(sc, txtid); |
720 | ||
721 | /* drop all software retried frames and mark this TID */ | |
722 | spin_lock_bh(&txq->axq_lock); | |
723 | while (!list_empty(&txtid->buf_q)) { | |
724 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
725 | if (!bf_isretried(bf)) { | |
726 | /* | |
727 | * NB: it's based on the assumption that | |
728 | * software retried frame will always stay | |
729 | * at the head of software queue. | |
730 | */ | |
731 | break; | |
732 | } | |
d43f3015 | 733 | list_move_tail(&bf->list, &bf_head); |
e8324357 S |
734 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
735 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 | 736 | } |
d43f3015 | 737 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 738 | |
e8324357 | 739 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
740 | txtid->state |= AGGR_CLEANUP; |
741 | } else { | |
742 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
743 | txtid->addba_exchangeattempts = 0; | |
e8324357 | 744 | ath_tx_flush_tid(sc, txtid); |
f078f209 LR |
745 | } |
746 | ||
e8324357 S |
747 | return 0; |
748 | } | |
f078f209 | 749 | |
e8324357 S |
750 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
751 | { | |
752 | struct ath_atx_tid *txtid; | |
753 | struct ath_node *an; | |
754 | ||
755 | an = (struct ath_node *)sta->drv_priv; | |
756 | ||
757 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
758 | txtid = ATH_AN_2_TID(an, tid); | |
759 | txtid->baw_size = | |
760 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
761 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
762 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
763 | ath_tx_resume_tid(sc, txtid); | |
764 | } | |
f078f209 LR |
765 | } |
766 | ||
e8324357 | 767 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 768 | { |
e8324357 | 769 | struct ath_atx_tid *txtid; |
c4288390 | 770 | |
e8324357 S |
771 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
772 | return false; | |
c4288390 | 773 | |
e8324357 S |
774 | txtid = ATH_AN_2_TID(an, tidno); |
775 | ||
776 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { | |
777 | if (!(txtid->state & AGGR_ADDBA_PROGRESS) && | |
778 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
779 | txtid->addba_exchangeattempts++; | |
780 | return true; | |
c4288390 S |
781 | } |
782 | } | |
e8324357 S |
783 | |
784 | return false; | |
c4288390 S |
785 | } |
786 | ||
e8324357 S |
787 | /********************/ |
788 | /* Queue Management */ | |
789 | /********************/ | |
f078f209 | 790 | |
e8324357 S |
791 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
792 | struct ath_txq *txq) | |
f078f209 | 793 | { |
e8324357 S |
794 | struct ath_atx_ac *ac, *ac_tmp; |
795 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 796 | |
e8324357 S |
797 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
798 | list_del(&ac->list); | |
799 | ac->sched = false; | |
800 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
801 | list_del(&tid->list); | |
802 | tid->sched = false; | |
803 | ath_tid_drain(sc, txq, tid); | |
804 | } | |
f078f209 LR |
805 | } |
806 | } | |
807 | ||
e8324357 | 808 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 809 | { |
cbe61d8a | 810 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
811 | struct ath9k_tx_queue_info qi; |
812 | int qnum; | |
f078f209 | 813 | |
e8324357 S |
814 | memset(&qi, 0, sizeof(qi)); |
815 | qi.tqi_subtype = subtype; | |
816 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
817 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
818 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
819 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
820 | |
821 | /* | |
e8324357 S |
822 | * Enable interrupts only for EOL and DESC conditions. |
823 | * We mark tx descriptors to receive a DESC interrupt | |
824 | * when a tx queue gets deep; otherwise waiting for the | |
825 | * EOL to reap descriptors. Note that this is done to | |
826 | * reduce interrupt load and this only defers reaping | |
827 | * descriptors, never transmitting frames. Aside from | |
828 | * reducing interrupts this also permits more concurrency. | |
829 | * The only potential downside is if the tx queue backs | |
830 | * up in which case the top half of the kernel may backup | |
831 | * due to a lack of tx descriptors. | |
832 | * | |
833 | * The UAPSD queue is an exception, since we take a desc- | |
834 | * based intr on the EOSP frames. | |
f078f209 | 835 | */ |
e8324357 S |
836 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
837 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
838 | else | |
839 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
840 | TXQ_FLAG_TXDESCINT_ENABLE; | |
841 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
842 | if (qnum == -1) { | |
f078f209 | 843 | /* |
e8324357 S |
844 | * NB: don't print a message, this happens |
845 | * normally on parts with too few tx queues | |
f078f209 | 846 | */ |
e8324357 | 847 | return NULL; |
f078f209 | 848 | } |
e8324357 S |
849 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
850 | DPRINTF(sc, ATH_DBG_FATAL, | |
851 | "qnum %u out of range, max %u!\n", | |
852 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
853 | ath9k_hw_releasetxqueue(ah, qnum); | |
854 | return NULL; | |
855 | } | |
856 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
857 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 858 | |
e8324357 S |
859 | txq->axq_qnum = qnum; |
860 | txq->axq_link = NULL; | |
861 | INIT_LIST_HEAD(&txq->axq_q); | |
862 | INIT_LIST_HEAD(&txq->axq_acq); | |
863 | spin_lock_init(&txq->axq_lock); | |
864 | txq->axq_depth = 0; | |
865 | txq->axq_aggr_depth = 0; | |
866 | txq->axq_totalqueued = 0; | |
867 | txq->axq_linkbuf = NULL; | |
868 | sc->tx.txqsetup |= 1<<qnum; | |
869 | } | |
870 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
871 | } |
872 | ||
e8324357 | 873 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 874 | { |
e8324357 | 875 | int qnum; |
f078f209 | 876 | |
e8324357 S |
877 | switch (qtype) { |
878 | case ATH9K_TX_QUEUE_DATA: | |
879 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
880 | DPRINTF(sc, ATH_DBG_FATAL, | |
881 | "HAL AC %u out of range, max %zu!\n", | |
882 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
883 | return -1; | |
884 | } | |
885 | qnum = sc->tx.hwq_map[haltype]; | |
886 | break; | |
887 | case ATH9K_TX_QUEUE_BEACON: | |
888 | qnum = sc->beacon.beaconq; | |
889 | break; | |
890 | case ATH9K_TX_QUEUE_CAB: | |
891 | qnum = sc->beacon.cabq->axq_qnum; | |
892 | break; | |
893 | default: | |
894 | qnum = -1; | |
895 | } | |
896 | return qnum; | |
897 | } | |
f078f209 | 898 | |
e8324357 S |
899 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
900 | { | |
901 | struct ath_txq *txq = NULL; | |
902 | int qnum; | |
f078f209 | 903 | |
e8324357 S |
904 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
905 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 906 | |
e8324357 S |
907 | spin_lock_bh(&txq->axq_lock); |
908 | ||
909 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c117fa0b | 910 | DPRINTF(sc, ATH_DBG_XMIT, |
e8324357 S |
911 | "TX queue: %d is full, depth: %d\n", |
912 | qnum, txq->axq_depth); | |
913 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
914 | txq->stopped = 1; | |
915 | spin_unlock_bh(&txq->axq_lock); | |
916 | return NULL; | |
f078f209 LR |
917 | } |
918 | ||
e8324357 S |
919 | spin_unlock_bh(&txq->axq_lock); |
920 | ||
921 | return txq; | |
922 | } | |
923 | ||
924 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
925 | struct ath9k_tx_queue_info *qinfo) | |
926 | { | |
cbe61d8a | 927 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
928 | int error = 0; |
929 | struct ath9k_tx_queue_info qi; | |
930 | ||
931 | if (qnum == sc->beacon.beaconq) { | |
932 | /* | |
933 | * XXX: for beacon queue, we just save the parameter. | |
934 | * It will be picked up by ath_beaconq_config when | |
935 | * it's necessary. | |
936 | */ | |
937 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 938 | return 0; |
e8324357 | 939 | } |
f078f209 | 940 | |
e8324357 S |
941 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
942 | ||
943 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
944 | qi.tqi_aifs = qinfo->tqi_aifs; | |
945 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
946 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
947 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
948 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
949 | ||
950 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
951 | DPRINTF(sc, ATH_DBG_FATAL, | |
952 | "Unable to update hardware queue %u!\n", qnum); | |
953 | error = -EIO; | |
954 | } else { | |
955 | ath9k_hw_resettxqueue(ah, qnum); | |
956 | } | |
957 | ||
958 | return error; | |
959 | } | |
960 | ||
961 | int ath_cabq_update(struct ath_softc *sc) | |
962 | { | |
963 | struct ath9k_tx_queue_info qi; | |
964 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 965 | |
e8324357 | 966 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 967 | /* |
e8324357 | 968 | * Ensure the readytime % is within the bounds. |
f078f209 | 969 | */ |
17d7904d S |
970 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
971 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
972 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
973 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 974 | |
fdbf7335 S |
975 | qi.tqi_readyTime = (sc->hw->conf.beacon_int * |
976 | sc->config.cabqReadytime) / 100; | |
e8324357 S |
977 | ath_txq_update(sc, qnum, &qi); |
978 | ||
979 | return 0; | |
f078f209 LR |
980 | } |
981 | ||
043a0405 S |
982 | /* |
983 | * Drain a given TX queue (could be Beacon or Data) | |
984 | * | |
985 | * This assumes output has been stopped and | |
986 | * we do not need to block ath_tx_tasklet. | |
987 | */ | |
988 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 989 | { |
e8324357 S |
990 | struct ath_buf *bf, *lastbf; |
991 | struct list_head bf_head; | |
f078f209 | 992 | |
e8324357 | 993 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 994 | |
e8324357 S |
995 | for (;;) { |
996 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 997 | |
e8324357 S |
998 | if (list_empty(&txq->axq_q)) { |
999 | txq->axq_link = NULL; | |
1000 | txq->axq_linkbuf = NULL; | |
1001 | spin_unlock_bh(&txq->axq_lock); | |
1002 | break; | |
1003 | } | |
f078f209 | 1004 | |
e8324357 | 1005 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1006 | |
e8324357 S |
1007 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
1008 | list_del(&bf->list); | |
1009 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1010 | |
e8324357 S |
1011 | spin_lock_bh(&sc->tx.txbuflock); |
1012 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1013 | spin_unlock_bh(&sc->tx.txbuflock); | |
1014 | continue; | |
1015 | } | |
f078f209 | 1016 | |
e8324357 S |
1017 | lastbf = bf->bf_lastbf; |
1018 | if (!retry_tx) | |
1019 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1020 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1021 | |
e8324357 S |
1022 | /* remove ath_buf's of the same mpdu from txq */ |
1023 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1024 | txq->axq_depth--; | |
f078f209 | 1025 | |
e8324357 S |
1026 | spin_unlock_bh(&txq->axq_lock); |
1027 | ||
1028 | if (bf_isampdu(bf)) | |
d43f3015 | 1029 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 S |
1030 | else |
1031 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
1032 | } |
1033 | ||
e8324357 S |
1034 | /* flush any pending frames if aggregation is enabled */ |
1035 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1036 | if (!retry_tx) { | |
1037 | spin_lock_bh(&txq->axq_lock); | |
1038 | ath_txq_drain_pending_buffers(sc, txq); | |
1039 | spin_unlock_bh(&txq->axq_lock); | |
1040 | } | |
1041 | } | |
f078f209 LR |
1042 | } |
1043 | ||
043a0405 | 1044 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1045 | { |
cbe61d8a | 1046 | struct ath_hw *ah = sc->sc_ah; |
043a0405 S |
1047 | struct ath_txq *txq; |
1048 | int i, npend = 0; | |
1049 | ||
1050 | if (sc->sc_flags & SC_OP_INVALID) | |
1051 | return; | |
1052 | ||
1053 | /* Stop beacon queue */ | |
1054 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1055 | ||
1056 | /* Stop data queues */ | |
1057 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1058 | if (ATH_TXQ_SETUP(sc, i)) { | |
1059 | txq = &sc->tx.txq[i]; | |
1060 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1061 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | if (npend) { | |
1066 | int r; | |
1067 | ||
1068 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); | |
1069 | ||
1070 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1071 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); |
043a0405 S |
1072 | if (r) |
1073 | DPRINTF(sc, ATH_DBG_FATAL, | |
1074 | "Unable to reset hardware; reset status %u\n", | |
1075 | r); | |
1076 | spin_unlock_bh(&sc->sc_resetlock); | |
1077 | } | |
1078 | ||
1079 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1080 | if (ATH_TXQ_SETUP(sc, i)) | |
1081 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1082 | } | |
e8324357 | 1083 | } |
f078f209 | 1084 | |
043a0405 | 1085 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1086 | { |
043a0405 S |
1087 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1088 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1089 | } |
f078f209 | 1090 | |
e8324357 S |
1091 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1092 | { | |
1093 | struct ath_atx_ac *ac; | |
1094 | struct ath_atx_tid *tid; | |
f078f209 | 1095 | |
e8324357 S |
1096 | if (list_empty(&txq->axq_acq)) |
1097 | return; | |
f078f209 | 1098 | |
e8324357 S |
1099 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1100 | list_del(&ac->list); | |
1101 | ac->sched = false; | |
f078f209 | 1102 | |
e8324357 S |
1103 | do { |
1104 | if (list_empty(&ac->tid_q)) | |
1105 | return; | |
f078f209 | 1106 | |
e8324357 S |
1107 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1108 | list_del(&tid->list); | |
1109 | tid->sched = false; | |
f078f209 | 1110 | |
e8324357 S |
1111 | if (tid->paused) |
1112 | continue; | |
f078f209 | 1113 | |
e8324357 S |
1114 | if ((txq->axq_depth % 2) == 0) |
1115 | ath_tx_sched_aggr(sc, txq, tid); | |
f078f209 LR |
1116 | |
1117 | /* | |
e8324357 S |
1118 | * add tid to round-robin queue if more frames |
1119 | * are pending for the tid | |
f078f209 | 1120 | */ |
e8324357 S |
1121 | if (!list_empty(&tid->buf_q)) |
1122 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1123 | |
e8324357 S |
1124 | break; |
1125 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1126 | |
e8324357 S |
1127 | if (!list_empty(&ac->tid_q)) { |
1128 | if (!ac->sched) { | |
1129 | ac->sched = true; | |
1130 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1131 | } |
e8324357 S |
1132 | } |
1133 | } | |
f078f209 | 1134 | |
e8324357 S |
1135 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1136 | { | |
1137 | struct ath_txq *txq; | |
f078f209 | 1138 | |
e8324357 S |
1139 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1140 | DPRINTF(sc, ATH_DBG_FATAL, | |
1141 | "HAL AC %u out of range, max %zu!\n", | |
1142 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1143 | return 0; | |
1144 | } | |
1145 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1146 | if (txq != NULL) { | |
1147 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1148 | return 1; | |
1149 | } else | |
1150 | return 0; | |
f078f209 LR |
1151 | } |
1152 | ||
e8324357 S |
1153 | /***********/ |
1154 | /* TX, DMA */ | |
1155 | /***********/ | |
1156 | ||
f078f209 | 1157 | /* |
e8324357 S |
1158 | * Insert a chain of ath_buf (descriptors) on a txq and |
1159 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1160 | */ |
e8324357 S |
1161 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1162 | struct list_head *head) | |
f078f209 | 1163 | { |
cbe61d8a | 1164 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1165 | struct ath_buf *bf; |
f078f209 | 1166 | |
e8324357 S |
1167 | /* |
1168 | * Insert the frame on the outbound list and | |
1169 | * pass it on to the hardware. | |
1170 | */ | |
f078f209 | 1171 | |
e8324357 S |
1172 | if (list_empty(head)) |
1173 | return; | |
f078f209 | 1174 | |
e8324357 | 1175 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1176 | |
e8324357 S |
1177 | list_splice_tail_init(head, &txq->axq_q); |
1178 | txq->axq_depth++; | |
1179 | txq->axq_totalqueued++; | |
1180 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
f078f209 | 1181 | |
e8324357 S |
1182 | DPRINTF(sc, ATH_DBG_QUEUE, |
1183 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1184 | |
e8324357 S |
1185 | if (txq->axq_link == NULL) { |
1186 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1187 | DPRINTF(sc, ATH_DBG_XMIT, | |
1188 | "TXDP[%u] = %llx (%p)\n", | |
1189 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1190 | } else { | |
1191 | *txq->axq_link = bf->bf_daddr; | |
1192 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1193 | txq->axq_qnum, txq->axq_link, | |
1194 | ito64(bf->bf_daddr), bf->bf_desc); | |
1195 | } | |
1196 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1197 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1198 | } | |
f078f209 | 1199 | |
e8324357 S |
1200 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1201 | { | |
1202 | struct ath_buf *bf = NULL; | |
f078f209 | 1203 | |
e8324357 | 1204 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1205 | |
e8324357 S |
1206 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1207 | spin_unlock_bh(&sc->tx.txbuflock); | |
1208 | return NULL; | |
1209 | } | |
f078f209 | 1210 | |
e8324357 S |
1211 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1212 | list_del(&bf->list); | |
f078f209 | 1213 | |
e8324357 | 1214 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1215 | |
e8324357 | 1216 | return bf; |
f078f209 LR |
1217 | } |
1218 | ||
e8324357 S |
1219 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1220 | struct list_head *bf_head, | |
1221 | struct ath_tx_control *txctl) | |
f078f209 LR |
1222 | { |
1223 | struct ath_buf *bf; | |
f078f209 | 1224 | |
e8324357 S |
1225 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1226 | bf->bf_state.bf_type |= BUF_AMPDU; | |
f078f209 | 1227 | |
e8324357 S |
1228 | /* |
1229 | * Do not queue to h/w when any of the following conditions is true: | |
1230 | * - there are pending frames in software queue | |
1231 | * - the TID is currently paused for ADDBA/BAR request | |
1232 | * - seqno is not within block-ack window | |
1233 | * - h/w queue depth exceeds low water mark | |
1234 | */ | |
1235 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1236 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1237 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1238 | /* |
e8324357 S |
1239 | * Add this frame to software queue for scheduling later |
1240 | * for aggregation. | |
f078f209 | 1241 | */ |
d43f3015 | 1242 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1243 | ath_tx_queue_tid(txctl->txq, tid); |
1244 | return; | |
1245 | } | |
1246 | ||
1247 | /* Add sub-frame to BAW */ | |
1248 | ath_tx_addto_baw(sc, tid, bf); | |
1249 | ||
1250 | /* Queue to h/w without aggregation */ | |
1251 | bf->bf_nframes = 1; | |
d43f3015 | 1252 | bf->bf_lastbf = bf; |
e8324357 S |
1253 | ath_buf_set_rate(sc, bf); |
1254 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1255 | } |
1256 | ||
c37452b0 S |
1257 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1258 | struct ath_atx_tid *tid, | |
1259 | struct list_head *bf_head) | |
e8324357 S |
1260 | { |
1261 | struct ath_buf *bf; | |
1262 | ||
e8324357 S |
1263 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1264 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1265 | ||
1266 | /* update starting sequence number for subsequent ADDBA request */ | |
1267 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1268 | ||
1269 | bf->bf_nframes = 1; | |
d43f3015 | 1270 | bf->bf_lastbf = bf; |
e8324357 S |
1271 | ath_buf_set_rate(sc, bf); |
1272 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1273 | } | |
1274 | ||
c37452b0 S |
1275 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1276 | struct list_head *bf_head) | |
1277 | { | |
1278 | struct ath_buf *bf; | |
1279 | ||
1280 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1281 | ||
1282 | bf->bf_lastbf = bf; | |
1283 | bf->bf_nframes = 1; | |
1284 | ath_buf_set_rate(sc, bf); | |
1285 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1286 | } | |
1287 | ||
e8324357 S |
1288 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1289 | { | |
1290 | struct ieee80211_hdr *hdr; | |
1291 | enum ath9k_pkt_type htype; | |
1292 | __le16 fc; | |
1293 | ||
1294 | hdr = (struct ieee80211_hdr *)skb->data; | |
1295 | fc = hdr->frame_control; | |
1296 | ||
1297 | if (ieee80211_is_beacon(fc)) | |
1298 | htype = ATH9K_PKT_TYPE_BEACON; | |
1299 | else if (ieee80211_is_probe_resp(fc)) | |
1300 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1301 | else if (ieee80211_is_atim(fc)) | |
1302 | htype = ATH9K_PKT_TYPE_ATIM; | |
1303 | else if (ieee80211_is_pspoll(fc)) | |
1304 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1305 | else | |
1306 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1307 | ||
1308 | return htype; | |
1309 | } | |
1310 | ||
1311 | static bool is_pae(struct sk_buff *skb) | |
1312 | { | |
1313 | struct ieee80211_hdr *hdr; | |
1314 | __le16 fc; | |
1315 | ||
1316 | hdr = (struct ieee80211_hdr *)skb->data; | |
1317 | fc = hdr->frame_control; | |
1318 | ||
1319 | if (ieee80211_is_data(fc)) { | |
1320 | if (ieee80211_is_nullfunc(fc) || | |
1321 | /* Port Access Entity (IEEE 802.1X) */ | |
1322 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1323 | return true; | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | return false; | |
1328 | } | |
1329 | ||
1330 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1331 | { | |
1332 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1333 | ||
1334 | if (tx_info->control.hw_key) { | |
1335 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1336 | return ATH9K_KEY_TYPE_WEP; | |
1337 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1338 | return ATH9K_KEY_TYPE_TKIP; | |
1339 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1340 | return ATH9K_KEY_TYPE_AES; | |
1341 | } | |
1342 | ||
1343 | return ATH9K_KEY_TYPE_CLEAR; | |
1344 | } | |
1345 | ||
1346 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1347 | struct ath_buf *bf) | |
1348 | { | |
1349 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1350 | struct ieee80211_hdr *hdr; | |
1351 | struct ath_node *an; | |
1352 | struct ath_atx_tid *tid; | |
1353 | __le16 fc; | |
1354 | u8 *qc; | |
1355 | ||
1356 | if (!tx_info->control.sta) | |
1357 | return; | |
1358 | ||
1359 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1360 | hdr = (struct ieee80211_hdr *)skb->data; | |
1361 | fc = hdr->frame_control; | |
1362 | ||
1363 | if (ieee80211_is_data_qos(fc)) { | |
1364 | qc = ieee80211_get_qos_ctl(hdr); | |
1365 | bf->bf_tidno = qc[0] & 0xf; | |
1366 | } | |
1367 | ||
1368 | /* | |
1369 | * For HT capable stations, we save tidno for later use. | |
1370 | * We also override seqno set by upper layer with the one | |
1371 | * in tx aggregation state. | |
1372 | * | |
1373 | * If fragmentation is on, the sequence number is | |
1374 | * not overridden, since it has been | |
1375 | * incremented by the fragmentation routine. | |
1376 | * | |
1377 | * FIXME: check if the fragmentation threshold exceeds | |
1378 | * IEEE80211 max. | |
1379 | */ | |
1380 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1381 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1382 | IEEE80211_SEQ_SEQ_SHIFT); | |
1383 | bf->bf_seqno = tid->seq_next; | |
1384 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1385 | } | |
1386 | ||
1387 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1388 | struct ath_txq *txq) | |
1389 | { | |
1390 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1391 | int flags = 0; | |
1392 | ||
1393 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1394 | flags |= ATH9K_TXDESC_INTREQ; | |
1395 | ||
1396 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1397 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1398 | |
1399 | return flags; | |
1400 | } | |
1401 | ||
1402 | /* | |
1403 | * rix - rate index | |
1404 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1405 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1406 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1407 | */ | |
1408 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1409 | int width, int half_gi, bool shortPreamble) | |
1410 | { | |
1411 | struct ath_rate_table *rate_table = sc->cur_rate_table; | |
1412 | u32 nbits, nsymbits, duration, nsymbols; | |
1413 | u8 rc; | |
1414 | int streams, pktlen; | |
1415 | ||
1416 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1417 | rc = rate_table->info[rix].ratecode; | |
1418 | ||
1419 | /* for legacy rates, use old function to compute packet duration */ | |
1420 | if (!IS_HT_RATE(rc)) | |
1421 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1422 | rix, shortPreamble); | |
1423 | ||
1424 | /* find number of symbols: PLCP + data */ | |
1425 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1426 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1427 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1428 | ||
1429 | if (!half_gi) | |
1430 | duration = SYMBOL_TIME(nsymbols); | |
1431 | else | |
1432 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1433 | ||
1434 | /* addup duration for legacy/ht training and signal fields */ | |
1435 | streams = HT_RC_2_STREAMS(rc); | |
1436 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1437 | ||
1438 | return duration; | |
1439 | } | |
1440 | ||
1441 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1442 | { | |
c89424df | 1443 | struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
1444 | struct ath9k_11n_rate_series series[4]; |
1445 | struct sk_buff *skb; | |
1446 | struct ieee80211_tx_info *tx_info; | |
1447 | struct ieee80211_tx_rate *rates; | |
254ad0ff | 1448 | struct ieee80211_hdr *hdr; |
c89424df S |
1449 | int i, flags = 0; |
1450 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1451 | bool is_pspoll; |
e8324357 S |
1452 | |
1453 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1454 | ||
1455 | skb = (struct sk_buff *)bf->bf_mpdu; | |
e8324357 S |
1456 | tx_info = IEEE80211_SKB_CB(skb); |
1457 | rates = tx_info->control.rates; | |
254ad0ff S |
1458 | hdr = (struct ieee80211_hdr *)skb->data; |
1459 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1460 | |
e8324357 | 1461 | /* |
c89424df S |
1462 | * We check if Short Preamble is needed for the CTS rate by |
1463 | * checking the BSS's global flag. | |
1464 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1465 | */ |
c89424df S |
1466 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
1467 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | | |
1468 | rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; | |
1469 | else | |
1470 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; | |
e8324357 | 1471 | |
c89424df S |
1472 | /* |
1473 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1474 | * Check the first rate in the series to decide whether RTS/CTS | |
1475 | * or CTS-to-self has to be used. | |
e8324357 | 1476 | */ |
c89424df S |
1477 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1478 | flags = ATH9K_TXDESC_CTSENA; | |
1479 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1480 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1481 | |
c89424df | 1482 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1483 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1484 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1485 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1486 | } |
1487 | ||
1488 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1489 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1490 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1491 | ||
e8324357 S |
1492 | for (i = 0; i < 4; i++) { |
1493 | if (!rates[i].count || (rates[i].idx < 0)) | |
1494 | continue; | |
1495 | ||
1496 | rix = rates[i].idx; | |
e8324357 | 1497 | series[i].Tries = rates[i].count; |
17d7904d | 1498 | series[i].ChSel = sc->tx_chainmask; |
e8324357 | 1499 | |
c89424df S |
1500 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
1501 | series[i].Rate = rt->info[rix].ratecode | | |
1502 | rt->info[rix].short_preamble; | |
1503 | else | |
1504 | series[i].Rate = rt->info[rix].ratecode; | |
1505 | ||
1506 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1507 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1508 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1509 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1510 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1511 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 S |
1512 | |
1513 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1514 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1515 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
c89424df | 1516 | (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); |
f078f209 LR |
1517 | } |
1518 | ||
e8324357 | 1519 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1520 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1521 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1522 | !is_pspoll, ctsrate, |
c89424df | 1523 | 0, series, 4, flags); |
f078f209 | 1524 | |
17d7904d | 1525 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1526 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1527 | } |
1528 | ||
c52f33d0 | 1529 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1530 | struct sk_buff *skb, |
528f0c6b | 1531 | struct ath_tx_control *txctl) |
f078f209 | 1532 | { |
c52f33d0 JM |
1533 | struct ath_wiphy *aphy = hw->priv; |
1534 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1535 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1536 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1537 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1538 | int hdrlen; |
1539 | __le16 fc; | |
e022edbd | 1540 | |
c112d0c5 LR |
1541 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1542 | if (unlikely(!tx_info_priv)) | |
1543 | return -ENOMEM; | |
a8efee4f | 1544 | tx_info->rate_driver_data[0] = tx_info_priv; |
c52f33d0 | 1545 | tx_info_priv->aphy = aphy; |
f0ed85c6 | 1546 | tx_info_priv->frame_type = txctl->frame_type; |
528f0c6b S |
1547 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1548 | fc = hdr->frame_control; | |
f078f209 | 1549 | |
528f0c6b | 1550 | ATH_TXBUF_RESET(bf); |
f078f209 | 1551 | |
528f0c6b | 1552 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 | 1553 | |
c37452b0 | 1554 | if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) |
c656bbb5 | 1555 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1556 | |
1557 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1558 | ||
528f0c6b | 1559 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1560 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1561 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1562 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1563 | } else { | |
1564 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1565 | } | |
1566 | ||
d3a1db1c | 1567 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1568 | assign_aggr_tid_seqno(skb, bf); |
1569 | ||
f078f209 | 1570 | bf->bf_mpdu = skb; |
f8316df1 | 1571 | |
7da3c55c GJ |
1572 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1573 | skb->len, DMA_TO_DEVICE); | |
1574 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 LR |
1575 | bf->bf_mpdu = NULL; |
1576 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 1577 | "dma_mapping_error() on TX\n"); |
f8316df1 LR |
1578 | return -ENOMEM; |
1579 | } | |
1580 | ||
528f0c6b | 1581 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1582 | return 0; |
528f0c6b S |
1583 | } |
1584 | ||
1585 | /* FIXME: tx power */ | |
1586 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1587 | struct ath_tx_control *txctl) |
1588 | { | |
1589 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
1590 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
c37452b0 | 1591 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1592 | struct ath_node *an = NULL; |
1593 | struct list_head bf_head; | |
1594 | struct ath_desc *ds; | |
1595 | struct ath_atx_tid *tid; | |
cbe61d8a | 1596 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1597 | int frm_type; |
c37452b0 | 1598 | __le16 fc; |
528f0c6b | 1599 | |
528f0c6b | 1600 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1601 | fc = hdr->frame_control; |
528f0c6b S |
1602 | |
1603 | INIT_LIST_HEAD(&bf_head); | |
1604 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1605 | |
f078f209 LR |
1606 | ds = bf->bf_desc; |
1607 | ds->ds_link = 0; | |
1608 | ds->ds_data = bf->bf_buf_addr; | |
1609 | ||
528f0c6b S |
1610 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1611 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1612 | ||
1613 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1614 | skb->len, /* segment length */ |
1615 | true, /* first segment */ | |
1616 | true, /* last segment */ | |
1617 | ds); /* first descriptor */ | |
f078f209 | 1618 | |
528f0c6b | 1619 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1620 | |
f1617967 JL |
1621 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1622 | tx_info->control.sta) { | |
1623 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1624 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1625 | ||
c37452b0 S |
1626 | if (!ieee80211_is_data_qos(fc)) { |
1627 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1628 | goto tx_done; | |
1629 | } | |
1630 | ||
528f0c6b | 1631 | if (ath_aggr_query(sc, an, bf->bf_tidno)) { |
f078f209 LR |
1632 | /* |
1633 | * Try aggregation if it's a unicast data frame | |
1634 | * and the destination is HT capable. | |
1635 | */ | |
528f0c6b | 1636 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1637 | } else { |
1638 | /* | |
528f0c6b S |
1639 | * Send this frame as regular when ADDBA |
1640 | * exchange is neither complete nor pending. | |
f078f209 | 1641 | */ |
c37452b0 S |
1642 | ath_tx_send_ht_normal(sc, txctl->txq, |
1643 | tid, &bf_head); | |
f078f209 LR |
1644 | } |
1645 | } else { | |
c37452b0 | 1646 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1647 | } |
528f0c6b | 1648 | |
c37452b0 | 1649 | tx_done: |
528f0c6b | 1650 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1651 | } |
1652 | ||
f8316df1 | 1653 | /* Upon failure caller should free skb */ |
c52f33d0 | 1654 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1655 | struct ath_tx_control *txctl) |
f078f209 | 1656 | { |
c52f33d0 JM |
1657 | struct ath_wiphy *aphy = hw->priv; |
1658 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 1659 | struct ath_buf *bf; |
f8316df1 | 1660 | int r; |
f078f209 | 1661 | |
528f0c6b S |
1662 | bf = ath_tx_get_buffer(sc); |
1663 | if (!bf) { | |
04bd4638 | 1664 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1665 | return -1; |
1666 | } | |
1667 | ||
c52f33d0 | 1668 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1669 | if (unlikely(r)) { |
c112d0c5 LR |
1670 | struct ath_txq *txq = txctl->txq; |
1671 | ||
f8316df1 | 1672 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1673 | |
1674 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1675 | * guarantee this will happen by knowing beforehand that | |
1676 | * we will at least have to run TX completionon one buffer | |
1677 | * on the queue */ | |
1678 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1679 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
c112d0c5 LR |
1680 | ieee80211_stop_queue(sc->hw, |
1681 | skb_get_queue_mapping(skb)); | |
1682 | txq->stopped = 1; | |
1683 | } | |
1684 | spin_unlock_bh(&txq->axq_lock); | |
1685 | ||
b77f483f S |
1686 | spin_lock_bh(&sc->tx.txbuflock); |
1687 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1688 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1689 | |
f8316df1 LR |
1690 | return r; |
1691 | } | |
1692 | ||
8f93b8b3 | 1693 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1694 | |
528f0c6b | 1695 | return 0; |
f078f209 LR |
1696 | } |
1697 | ||
c52f33d0 | 1698 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1699 | { |
c52f33d0 JM |
1700 | struct ath_wiphy *aphy = hw->priv; |
1701 | struct ath_softc *sc = aphy->sc; | |
e8324357 S |
1702 | int hdrlen, padsize; |
1703 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1704 | struct ath_tx_control txctl; | |
f078f209 | 1705 | |
e8324357 | 1706 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1707 | |
1708 | /* | |
e8324357 S |
1709 | * As a temporary workaround, assign seq# here; this will likely need |
1710 | * to be cleaned up to work better with Beacon transmission and virtual | |
1711 | * BSSes. | |
f078f209 | 1712 | */ |
e8324357 S |
1713 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1714 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1715 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1716 | sc->tx.seq_no += 0x10; | |
1717 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1718 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1719 | } |
f078f209 | 1720 | |
e8324357 S |
1721 | /* Add the padding after the header if this is not already done */ |
1722 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1723 | if (hdrlen & 3) { | |
1724 | padsize = hdrlen % 4; | |
1725 | if (skb_headroom(skb) < padsize) { | |
1726 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1727 | dev_kfree_skb_any(skb); | |
1728 | return; | |
1729 | } | |
1730 | skb_push(skb, padsize); | |
1731 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1732 | } |
f078f209 | 1733 | |
e8324357 | 1734 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1735 | |
e8324357 | 1736 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1737 | |
c52f33d0 | 1738 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
e8324357 S |
1739 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); |
1740 | goto exit; | |
f078f209 | 1741 | } |
f078f209 | 1742 | |
e8324357 S |
1743 | return; |
1744 | exit: | |
1745 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1746 | } |
1747 | ||
e8324357 S |
1748 | /*****************/ |
1749 | /* TX Completion */ | |
1750 | /*****************/ | |
528f0c6b | 1751 | |
e8324357 | 1752 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
6b2c4032 | 1753 | int tx_flags) |
528f0c6b | 1754 | { |
e8324357 S |
1755 | struct ieee80211_hw *hw = sc->hw; |
1756 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1757 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1758 | int hdrlen, padsize; | |
f0ed85c6 | 1759 | int frame_type = ATH9K_NOT_INTERNAL; |
528f0c6b | 1760 | |
e8324357 | 1761 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1762 | |
f0ed85c6 | 1763 | if (tx_info_priv) { |
c52f33d0 | 1764 | hw = tx_info_priv->aphy->hw; |
f0ed85c6 JM |
1765 | frame_type = tx_info_priv->frame_type; |
1766 | } | |
c52f33d0 | 1767 | |
e8324357 S |
1768 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1769 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1770 | kfree(tx_info_priv); | |
1771 | tx_info->rate_driver_data[0] = NULL; | |
1772 | } | |
528f0c6b | 1773 | |
6b2c4032 | 1774 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1775 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1776 | |
6b2c4032 | 1777 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1778 | /* Frame was ACKed */ |
1779 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1780 | } |
1781 | ||
e8324357 S |
1782 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1783 | padsize = hdrlen & 3; | |
1784 | if (padsize && hdrlen >= 24) { | |
1785 | /* | |
1786 | * Remove MAC header padding before giving the frame back to | |
1787 | * mac80211. | |
1788 | */ | |
1789 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1790 | skb_pull(skb, padsize); | |
1791 | } | |
528f0c6b | 1792 | |
f0ed85c6 JM |
1793 | if (frame_type == ATH9K_NOT_INTERNAL) |
1794 | ieee80211_tx_status(hw, skb); | |
1795 | else | |
1796 | ath9k_tx_status(hw, skb); | |
e8324357 | 1797 | } |
f078f209 | 1798 | |
e8324357 S |
1799 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
1800 | struct list_head *bf_q, | |
1801 | int txok, int sendbar) | |
f078f209 | 1802 | { |
e8324357 | 1803 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1804 | unsigned long flags; |
6b2c4032 | 1805 | int tx_flags = 0; |
f078f209 | 1806 | |
f078f209 | 1807 | |
e8324357 | 1808 | if (sendbar) |
6b2c4032 | 1809 | tx_flags = ATH_TX_BAR; |
f078f209 | 1810 | |
e8324357 | 1811 | if (!txok) { |
6b2c4032 | 1812 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1813 | |
e8324357 | 1814 | if (bf_isxretried(bf)) |
6b2c4032 | 1815 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1816 | } |
1817 | ||
e8324357 | 1818 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
6b2c4032 | 1819 | ath_tx_complete(sc, skb, tx_flags); |
e8324357 S |
1820 | |
1821 | /* | |
1822 | * Return the list of ath_buf of this mpdu to free queue | |
1823 | */ | |
1824 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1825 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1826 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1827 | } |
1828 | ||
e8324357 S |
1829 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1830 | int txok) | |
f078f209 | 1831 | { |
e8324357 S |
1832 | struct ath_buf *bf_last = bf->bf_lastbf; |
1833 | struct ath_desc *ds = bf_last->bf_desc; | |
1834 | u16 seq_st = 0; | |
1835 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1836 | int ba_index; | |
1837 | int nbad = 0; | |
1838 | int isaggr = 0; | |
f078f209 | 1839 | |
e8324357 S |
1840 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1841 | return 0; | |
f078f209 | 1842 | |
e8324357 S |
1843 | isaggr = bf_isaggr(bf); |
1844 | if (isaggr) { | |
1845 | seq_st = ATH_DS_BA_SEQ(ds); | |
1846 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1847 | } | |
f078f209 | 1848 | |
e8324357 S |
1849 | while (bf) { |
1850 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1851 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1852 | nbad++; | |
1853 | ||
1854 | bf = bf->bf_next; | |
1855 | } | |
f078f209 | 1856 | |
e8324357 S |
1857 | return nbad; |
1858 | } | |
f078f209 | 1859 | |
95e4acb7 | 1860 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, |
8a92e2ee | 1861 | int nbad, int txok, bool update_rc) |
f078f209 | 1862 | { |
e8324357 | 1863 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; |
254ad0ff | 1864 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 S |
1865 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1866 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
8a92e2ee VT |
1867 | struct ieee80211_hw *hw = tx_info_priv->aphy->hw; |
1868 | u8 i, tx_rateindex; | |
f078f209 | 1869 | |
95e4acb7 S |
1870 | if (txok) |
1871 | tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; | |
1872 | ||
8a92e2ee VT |
1873 | tx_rateindex = ds->ds_txstat.ts_rateindex; |
1874 | WARN_ON(tx_rateindex >= hw->max_rates); | |
1875 | ||
1876 | tx_info_priv->update_rc = update_rc; | |
e8324357 S |
1877 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1878 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1879 | |
e8324357 | 1880 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1881 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1882 | if (ieee80211_is_data(hdr->frame_control)) { |
e8324357 S |
1883 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, |
1884 | sizeof(tx_info_priv->tx)); | |
1885 | tx_info_priv->n_frames = bf->bf_nframes; | |
1886 | tx_info_priv->n_bad_frames = nbad; | |
e8324357 | 1887 | } |
f078f209 | 1888 | } |
8a92e2ee VT |
1889 | |
1890 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) | |
1891 | tx_info->status.rates[i].count = 0; | |
1892 | ||
1893 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1894 | } |
1895 | ||
059d806c S |
1896 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1897 | { | |
1898 | int qnum; | |
1899 | ||
1900 | spin_lock_bh(&txq->axq_lock); | |
1901 | if (txq->stopped && | |
f7a99e46 | 1902 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1903 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1904 | if (qnum != -1) { | |
1905 | ieee80211_wake_queue(sc->hw, qnum); | |
1906 | txq->stopped = 0; | |
1907 | } | |
1908 | } | |
1909 | spin_unlock_bh(&txq->axq_lock); | |
1910 | } | |
1911 | ||
e8324357 | 1912 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1913 | { |
cbe61d8a | 1914 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1915 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1916 | struct list_head bf_head; |
e8324357 | 1917 | struct ath_desc *ds; |
0934af23 | 1918 | int txok; |
e8324357 | 1919 | int status; |
f078f209 | 1920 | |
e8324357 S |
1921 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1922 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1923 | txq->axq_link); | |
f078f209 | 1924 | |
f078f209 LR |
1925 | for (;;) { |
1926 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1927 | if (list_empty(&txq->axq_q)) { |
1928 | txq->axq_link = NULL; | |
1929 | txq->axq_linkbuf = NULL; | |
1930 | spin_unlock_bh(&txq->axq_lock); | |
1931 | break; | |
1932 | } | |
f078f209 LR |
1933 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1934 | ||
e8324357 S |
1935 | /* |
1936 | * There is a race condition that a BH gets scheduled | |
1937 | * after sw writes TxE and before hw re-load the last | |
1938 | * descriptor to get the newly chained one. | |
1939 | * Software must keep the last DONE descriptor as a | |
1940 | * holding descriptor - software does so by marking | |
1941 | * it with the STALE flag. | |
1942 | */ | |
1943 | bf_held = NULL; | |
f078f209 | 1944 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
e8324357 S |
1945 | bf_held = bf; |
1946 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d S |
1947 | txq->axq_link = NULL; |
1948 | txq->axq_linkbuf = NULL; | |
1949 | spin_unlock_bh(&txq->axq_lock); | |
1950 | ||
1951 | /* | |
e8324357 S |
1952 | * The holding descriptor is the last |
1953 | * descriptor in queue. It's safe to remove | |
1954 | * the last holding descriptor in BH context. | |
1955 | */ | |
6ef9b13d S |
1956 | spin_lock_bh(&sc->tx.txbuflock); |
1957 | list_move_tail(&bf_held->list, &sc->tx.txbuf); | |
1958 | spin_unlock_bh(&sc->tx.txbuflock); | |
1959 | ||
e8324357 S |
1960 | break; |
1961 | } else { | |
1962 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1963 | struct ath_buf, list); |
e8324357 | 1964 | } |
f078f209 LR |
1965 | } |
1966 | ||
1967 | lastbf = bf->bf_lastbf; | |
e8324357 | 1968 | ds = lastbf->bf_desc; |
f078f209 | 1969 | |
e8324357 S |
1970 | status = ath9k_hw_txprocdesc(ah, ds); |
1971 | if (status == -EINPROGRESS) { | |
f078f209 | 1972 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 1973 | break; |
f078f209 | 1974 | } |
e8324357 S |
1975 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
1976 | txq->axq_lastdsWithCTS = NULL; | |
1977 | if (ds == txq->axq_gatingds) | |
1978 | txq->axq_gatingds = NULL; | |
f078f209 | 1979 | |
e8324357 S |
1980 | /* |
1981 | * Remove ath_buf's of the same transmit unit from txq, | |
1982 | * however leave the last descriptor back as the holding | |
1983 | * descriptor for hw. | |
1984 | */ | |
1985 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | |
1986 | INIT_LIST_HEAD(&bf_head); | |
e8324357 S |
1987 | if (!list_is_singular(&lastbf->list)) |
1988 | list_cut_position(&bf_head, | |
1989 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 1990 | |
e8324357 | 1991 | txq->axq_depth--; |
e8324357 S |
1992 | if (bf_isaggr(bf)) |
1993 | txq->axq_aggr_depth--; | |
f078f209 | 1994 | |
e8324357 | 1995 | txok = (ds->ds_txstat.ts_status == 0); |
e8324357 | 1996 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 1997 | |
e8324357 | 1998 | if (bf_held) { |
e8324357 | 1999 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2000 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2001 | spin_unlock_bh(&sc->tx.txbuflock); |
2002 | } | |
f078f209 | 2003 | |
e8324357 S |
2004 | if (!bf_isampdu(bf)) { |
2005 | /* | |
2006 | * This frame is sent out as a single frame. | |
2007 | * Use hardware retry status for this frame. | |
2008 | */ | |
2009 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2010 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2011 | bf->bf_state.bf_type |= BUF_XRETRY; | |
8a92e2ee | 2012 | ath_tx_rc_status(bf, ds, 0, txok, true); |
e8324357 | 2013 | } |
f078f209 | 2014 | |
e8324357 | 2015 | if (bf_isampdu(bf)) |
d43f3015 | 2016 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 S |
2017 | else |
2018 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
8469cdef | 2019 | |
059d806c | 2020 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2021 | |
059d806c | 2022 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2023 | if (sc->sc_flags & SC_OP_TXAGGR) |
2024 | ath_txq_schedule(sc, txq); | |
2025 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2026 | } |
2027 | } | |
2028 | ||
f078f209 | 2029 | |
e8324357 | 2030 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2031 | { |
e8324357 S |
2032 | int i; |
2033 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2034 | |
e8324357 | 2035 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2036 | |
e8324357 S |
2037 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2038 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2039 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2040 | } |
2041 | } | |
2042 | ||
e8324357 S |
2043 | /*****************/ |
2044 | /* Init, Cleanup */ | |
2045 | /*****************/ | |
f078f209 | 2046 | |
e8324357 | 2047 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2048 | { |
e8324357 | 2049 | int error = 0; |
f078f209 | 2050 | |
f078f209 | 2051 | do { |
e8324357 | 2052 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2053 | |
e8324357 S |
2054 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2055 | "tx", nbufs, 1); | |
2056 | if (error != 0) { | |
2057 | DPRINTF(sc, ATH_DBG_FATAL, | |
2058 | "Failed to allocate tx descriptors: %d\n", | |
2059 | error); | |
2060 | break; | |
2061 | } | |
f078f209 | 2062 | |
e8324357 S |
2063 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2064 | "beacon", ATH_BCBUF, 1); | |
2065 | if (error != 0) { | |
2066 | DPRINTF(sc, ATH_DBG_FATAL, | |
2067 | "Failed to allocate beacon descriptors: %d\n", | |
2068 | error); | |
2069 | break; | |
2070 | } | |
f078f209 | 2071 | |
e8324357 | 2072 | } while (0); |
f078f209 | 2073 | |
e8324357 S |
2074 | if (error != 0) |
2075 | ath_tx_cleanup(sc); | |
f078f209 | 2076 | |
e8324357 | 2077 | return error; |
f078f209 LR |
2078 | } |
2079 | ||
e8324357 S |
2080 | int ath_tx_cleanup(struct ath_softc *sc) |
2081 | { | |
2082 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2083 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2084 | ||
2085 | if (sc->tx.txdma.dd_desc_len != 0) | |
2086 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
2087 | ||
2088 | return 0; | |
2089 | } | |
f078f209 LR |
2090 | |
2091 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2092 | { | |
c5170163 S |
2093 | struct ath_atx_tid *tid; |
2094 | struct ath_atx_ac *ac; | |
2095 | int tidno, acno; | |
f078f209 | 2096 | |
8ee5afbc | 2097 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2098 | tidno < WME_NUM_TID; |
2099 | tidno++, tid++) { | |
2100 | tid->an = an; | |
2101 | tid->tidno = tidno; | |
2102 | tid->seq_start = tid->seq_next = 0; | |
2103 | tid->baw_size = WME_MAX_BA; | |
2104 | tid->baw_head = tid->baw_tail = 0; | |
2105 | tid->sched = false; | |
e8324357 | 2106 | tid->paused = false; |
a37c2c79 | 2107 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2108 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2109 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2110 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2111 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2112 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
2113 | tid->addba_exchangeattempts = 0; | |
c5170163 | 2114 | } |
f078f209 | 2115 | |
8ee5afbc | 2116 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2117 | acno < WME_NUM_AC; acno++, ac++) { |
2118 | ac->sched = false; | |
2119 | INIT_LIST_HEAD(&ac->tid_q); | |
2120 | ||
2121 | switch (acno) { | |
2122 | case WME_AC_BE: | |
2123 | ac->qnum = ath_tx_get_qnum(sc, | |
2124 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2125 | break; | |
2126 | case WME_AC_BK: | |
2127 | ac->qnum = ath_tx_get_qnum(sc, | |
2128 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2129 | break; | |
2130 | case WME_AC_VI: | |
2131 | ac->qnum = ath_tx_get_qnum(sc, | |
2132 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2133 | break; | |
2134 | case WME_AC_VO: | |
2135 | ac->qnum = ath_tx_get_qnum(sc, | |
2136 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2137 | break; | |
f078f209 LR |
2138 | } |
2139 | } | |
2140 | } | |
2141 | ||
b5aa9bf9 | 2142 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2143 | { |
2144 | int i; | |
2145 | struct ath_atx_ac *ac, *ac_tmp; | |
2146 | struct ath_atx_tid *tid, *tid_tmp; | |
2147 | struct ath_txq *txq; | |
e8324357 | 2148 | |
f078f209 LR |
2149 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2150 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2151 | txq = &sc->tx.txq[i]; |
f078f209 | 2152 | |
b5aa9bf9 | 2153 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2154 | |
2155 | list_for_each_entry_safe(ac, | |
2156 | ac_tmp, &txq->axq_acq, list) { | |
2157 | tid = list_first_entry(&ac->tid_q, | |
2158 | struct ath_atx_tid, list); | |
2159 | if (tid && tid->an != an) | |
2160 | continue; | |
2161 | list_del(&ac->list); | |
2162 | ac->sched = false; | |
2163 | ||
2164 | list_for_each_entry_safe(tid, | |
2165 | tid_tmp, &ac->tid_q, list) { | |
2166 | list_del(&tid->list); | |
2167 | tid->sched = false; | |
b5aa9bf9 | 2168 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2169 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
f078f209 | 2170 | tid->addba_exchangeattempts = 0; |
a37c2c79 | 2171 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2172 | } |
2173 | } | |
2174 | ||
b5aa9bf9 | 2175 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2176 | } |
2177 | } | |
2178 | } |