Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
e8324357 S |
58 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |
62 | struct list_head *bf_q, | |
63 | int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
c4288390 | 67 | |
e8324357 S |
68 | /*********************/ |
69 | /* Aggregation logic */ | |
70 | /*********************/ | |
f078f209 | 71 | |
a37c2c79 | 72 | static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
f078f209 LR |
73 | { |
74 | struct ath_atx_tid *tid; | |
75 | tid = ATH_AN_2_TID(an, tidno); | |
76 | ||
a37c2c79 S |
77 | if (tid->state & AGGR_ADDBA_COMPLETE || |
78 | tid->state & AGGR_ADDBA_PROGRESS) | |
f078f209 LR |
79 | return 1; |
80 | else | |
81 | return 0; | |
82 | } | |
83 | ||
e8324357 | 84 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 85 | { |
e8324357 | 86 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 87 | |
e8324357 S |
88 | if (tid->paused) |
89 | return; | |
ff37e337 | 90 | |
e8324357 S |
91 | if (tid->sched) |
92 | return; | |
ff37e337 | 93 | |
e8324357 S |
94 | tid->sched = true; |
95 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 96 | |
e8324357 S |
97 | if (ac->sched) |
98 | return; | |
f078f209 | 99 | |
e8324357 S |
100 | ac->sched = true; |
101 | list_add_tail(&ac->list, &txq->axq_acq); | |
102 | } | |
f078f209 | 103 | |
e8324357 S |
104 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
105 | { | |
106 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 107 | |
e8324357 S |
108 | spin_lock_bh(&txq->axq_lock); |
109 | tid->paused++; | |
110 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
111 | } |
112 | ||
e8324357 | 113 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 114 | { |
e8324357 | 115 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 116 | |
e8324357 S |
117 | ASSERT(tid->paused > 0); |
118 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 119 | |
e8324357 | 120 | tid->paused--; |
f078f209 | 121 | |
e8324357 S |
122 | if (tid->paused > 0) |
123 | goto unlock; | |
f078f209 | 124 | |
e8324357 S |
125 | if (list_empty(&tid->buf_q)) |
126 | goto unlock; | |
f078f209 | 127 | |
e8324357 S |
128 | ath_tx_queue_tid(txq, tid); |
129 | ath_txq_schedule(sc, txq); | |
130 | unlock: | |
131 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 132 | } |
f078f209 | 133 | |
e8324357 | 134 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 135 | { |
e8324357 S |
136 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
137 | struct ath_buf *bf; | |
138 | struct list_head bf_head; | |
139 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 140 | |
e8324357 S |
141 | ASSERT(tid->paused > 0); |
142 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 143 | |
e8324357 | 144 | tid->paused--; |
f078f209 | 145 | |
e8324357 S |
146 | if (tid->paused > 0) { |
147 | spin_unlock_bh(&txq->axq_lock); | |
148 | return; | |
149 | } | |
f078f209 | 150 | |
e8324357 S |
151 | while (!list_empty(&tid->buf_q)) { |
152 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
153 | ASSERT(!bf_isretried(bf)); | |
d43f3015 | 154 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 155 | ath_tx_send_normal(sc, txq, tid, &bf_head); |
528f0c6b | 156 | } |
f078f209 | 157 | |
e8324357 | 158 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 159 | } |
f078f209 | 160 | |
e8324357 S |
161 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
162 | int seqno) | |
528f0c6b | 163 | { |
e8324357 | 164 | int index, cindex; |
f078f209 | 165 | |
e8324357 S |
166 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
167 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 168 | |
e8324357 | 169 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 170 | |
e8324357 S |
171 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
172 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
173 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
174 | } | |
528f0c6b | 175 | } |
f078f209 | 176 | |
e8324357 S |
177 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
178 | struct ath_buf *bf) | |
528f0c6b | 179 | { |
e8324357 | 180 | int index, cindex; |
528f0c6b | 181 | |
e8324357 S |
182 | if (bf_isretried(bf)) |
183 | return; | |
528f0c6b | 184 | |
e8324357 S |
185 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
186 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 187 | |
e8324357 S |
188 | ASSERT(tid->tx_buf[cindex] == NULL); |
189 | tid->tx_buf[cindex] = bf; | |
f078f209 | 190 | |
e8324357 S |
191 | if (index >= ((tid->baw_tail - tid->baw_head) & |
192 | (ATH_TID_MAX_BUFS - 1))) { | |
193 | tid->baw_tail = cindex; | |
194 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 195 | } |
f078f209 LR |
196 | } |
197 | ||
198 | /* | |
e8324357 S |
199 | * TODO: For frame(s) that are in the retry state, we will reuse the |
200 | * sequence number(s) without setting the retry bit. The | |
201 | * alternative is to give up on these and BAR the receiver's window | |
202 | * forward. | |
f078f209 | 203 | */ |
e8324357 S |
204 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
205 | struct ath_atx_tid *tid) | |
f078f209 | 206 | |
f078f209 | 207 | { |
e8324357 S |
208 | struct ath_buf *bf; |
209 | struct list_head bf_head; | |
210 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 211 | |
e8324357 S |
212 | for (;;) { |
213 | if (list_empty(&tid->buf_q)) | |
214 | break; | |
f078f209 | 215 | |
d43f3015 S |
216 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
217 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 218 | |
e8324357 S |
219 | if (bf_isretried(bf)) |
220 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 221 | |
e8324357 S |
222 | spin_unlock(&txq->axq_lock); |
223 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
224 | spin_lock(&txq->axq_lock); | |
225 | } | |
f078f209 | 226 | |
e8324357 S |
227 | tid->seq_next = tid->seq_start; |
228 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
229 | } |
230 | ||
e8324357 | 231 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) |
f078f209 | 232 | { |
e8324357 S |
233 | struct sk_buff *skb; |
234 | struct ieee80211_hdr *hdr; | |
f078f209 | 235 | |
e8324357 S |
236 | bf->bf_state.bf_type |= BUF_RETRY; |
237 | bf->bf_retries++; | |
f078f209 | 238 | |
e8324357 S |
239 | skb = bf->bf_mpdu; |
240 | hdr = (struct ieee80211_hdr *)skb->data; | |
241 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
242 | } |
243 | ||
d43f3015 S |
244 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
245 | { | |
246 | struct ath_buf *tbf; | |
247 | ||
248 | spin_lock_bh(&sc->tx.txbuflock); | |
249 | ASSERT(!list_empty((&sc->tx.txbuf))); | |
250 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
251 | list_del(&tbf->list); | |
252 | spin_unlock_bh(&sc->tx.txbuflock); | |
253 | ||
254 | ATH_TXBUF_RESET(tbf); | |
255 | ||
256 | tbf->bf_mpdu = bf->bf_mpdu; | |
257 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
258 | *(tbf->bf_desc) = *(bf->bf_desc); | |
259 | tbf->bf_state = bf->bf_state; | |
260 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
261 | ||
262 | return tbf; | |
263 | } | |
264 | ||
265 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
266 | struct ath_buf *bf, struct list_head *bf_q, | |
267 | int txok) | |
f078f209 | 268 | { |
e8324357 S |
269 | struct ath_node *an = NULL; |
270 | struct sk_buff *skb; | |
1286ec6d S |
271 | struct ieee80211_sta *sta; |
272 | struct ieee80211_hdr *hdr; | |
e8324357 | 273 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 274 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 275 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 276 | struct list_head bf_head, bf_pending; |
f078f209 LR |
277 | u16 seq_st = 0; |
278 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
e8324357 | 279 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0; |
f078f209 | 280 | |
e8324357 | 281 | skb = (struct sk_buff *)bf->bf_mpdu; |
1286ec6d S |
282 | hdr = (struct ieee80211_hdr *)skb->data; |
283 | ||
284 | rcu_read_lock(); | |
f078f209 | 285 | |
1286ec6d S |
286 | sta = ieee80211_find_sta(sc->hw, hdr->addr1); |
287 | if (!sta) { | |
288 | rcu_read_unlock(); | |
289 | return; | |
f078f209 LR |
290 | } |
291 | ||
1286ec6d S |
292 | an = (struct ath_node *)sta->drv_priv; |
293 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
294 | ||
e8324357 | 295 | isaggr = bf_isaggr(bf); |
d43f3015 | 296 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 297 | |
d43f3015 S |
298 | if (isaggr && txok) { |
299 | if (ATH_DS_TX_BA(ds)) { | |
300 | seq_st = ATH_DS_BA_SEQ(ds); | |
301 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
302 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 303 | } else { |
d43f3015 S |
304 | /* |
305 | * AR5416 can become deaf/mute when BA | |
306 | * issue happens. Chip needs to be reset. | |
307 | * But AP code may have sychronization issues | |
308 | * when perform internal reset in this routine. | |
309 | * Only enable reset in STA mode for now. | |
310 | */ | |
2660b81a | 311 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 312 | needreset = 1; |
e8324357 | 313 | } |
f078f209 LR |
314 | } |
315 | ||
e8324357 S |
316 | INIT_LIST_HEAD(&bf_pending); |
317 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 318 | |
e8324357 S |
319 | while (bf) { |
320 | txfail = txpending = 0; | |
321 | bf_next = bf->bf_next; | |
f078f209 | 322 | |
e8324357 S |
323 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
324 | /* transmit completion, subframe is | |
325 | * acked by block ack */ | |
326 | } else if (!isaggr && txok) { | |
327 | /* transmit completion */ | |
328 | } else { | |
e8324357 S |
329 | if (!(tid->state & AGGR_CLEANUP) && |
330 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
331 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
332 | ath_tx_set_retry(sc, bf); | |
333 | txpending = 1; | |
334 | } else { | |
335 | bf->bf_state.bf_type |= BUF_XRETRY; | |
336 | txfail = 1; | |
337 | sendbar = 1; | |
338 | } | |
339 | } else { | |
340 | /* | |
341 | * cleanup in progress, just fail | |
342 | * the un-acked sub-frames | |
343 | */ | |
344 | txfail = 1; | |
345 | } | |
346 | } | |
f078f209 | 347 | |
e8324357 | 348 | if (bf_next == NULL) { |
d43f3015 | 349 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
350 | } else { |
351 | ASSERT(!list_empty(bf_q)); | |
d43f3015 | 352 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 353 | } |
f078f209 | 354 | |
e8324357 S |
355 | if (!txpending) { |
356 | /* | |
357 | * complete the acked-ones/xretried ones; update | |
358 | * block-ack window | |
359 | */ | |
360 | spin_lock_bh(&txq->axq_lock); | |
361 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
362 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 363 | |
e8324357 S |
364 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); |
365 | } else { | |
d43f3015 | 366 | /* retry the un-acked ones */ |
e8324357 S |
367 | if (bf->bf_next == NULL && |
368 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | |
369 | struct ath_buf *tbf; | |
f078f209 | 370 | |
d43f3015 S |
371 | tbf = ath_clone_txbuf(sc, bf_last); |
372 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); | |
e8324357 S |
373 | list_add_tail(&tbf->list, &bf_head); |
374 | } else { | |
375 | /* | |
376 | * Clear descriptor status words for | |
377 | * software retry | |
378 | */ | |
d43f3015 | 379 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
380 | } |
381 | ||
382 | /* | |
383 | * Put this buffer to the temporary pending | |
384 | * queue to retain ordering | |
385 | */ | |
386 | list_splice_tail_init(&bf_head, &bf_pending); | |
387 | } | |
388 | ||
389 | bf = bf_next; | |
f078f209 | 390 | } |
f078f209 | 391 | |
e8324357 | 392 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
393 | if (tid->baw_head == tid->baw_tail) { |
394 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
395 | tid->addba_exchangeattempts = 0; | |
e8324357 | 396 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 397 | |
e8324357 S |
398 | /* send buffered frames as singles */ |
399 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 400 | } |
1286ec6d | 401 | rcu_read_unlock(); |
e8324357 S |
402 | return; |
403 | } | |
f078f209 | 404 | |
d43f3015 | 405 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
406 | if (!list_empty(&bf_pending)) { |
407 | spin_lock_bh(&txq->axq_lock); | |
408 | list_splice(&bf_pending, &tid->buf_q); | |
409 | ath_tx_queue_tid(txq, tid); | |
410 | spin_unlock_bh(&txq->axq_lock); | |
411 | } | |
102e0572 | 412 | |
1286ec6d S |
413 | rcu_read_unlock(); |
414 | ||
e8324357 S |
415 | if (needreset) |
416 | ath_reset(sc, false); | |
e8324357 | 417 | } |
f078f209 | 418 | |
e8324357 S |
419 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
420 | struct ath_atx_tid *tid) | |
f078f209 | 421 | { |
e8324357 | 422 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
423 | struct sk_buff *skb; |
424 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 425 | struct ieee80211_tx_rate *rates; |
e8324357 | 426 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 427 | u32 max_4ms_framelen, frmlen; |
e8324357 S |
428 | u16 aggr_limit, legacy = 0, maxampdu; |
429 | int i; | |
528f0c6b S |
430 | |
431 | skb = (struct sk_buff *)bf->bf_mpdu; | |
432 | tx_info = IEEE80211_SKB_CB(skb); | |
e63835b0 | 433 | rates = tx_info->control.rates; |
d43f3015 | 434 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 435 | |
e8324357 S |
436 | /* |
437 | * Find the lowest frame length among the rate series that will have a | |
438 | * 4ms transmit duration. | |
439 | * TODO - TXOP limit needs to be considered. | |
440 | */ | |
441 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 442 | |
e8324357 S |
443 | for (i = 0; i < 4; i++) { |
444 | if (rates[i].count) { | |
445 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
446 | legacy = 1; | |
447 | break; | |
448 | } | |
449 | ||
d43f3015 S |
450 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
451 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
452 | } |
453 | } | |
e63835b0 | 454 | |
f078f209 | 455 | /* |
e8324357 S |
456 | * limit aggregate size by the minimum rate if rate selected is |
457 | * not a probe rate, if rate selected is a probe rate then | |
458 | * avoid aggregation of this packet. | |
f078f209 | 459 | */ |
e8324357 S |
460 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
461 | return 0; | |
f078f209 | 462 | |
d43f3015 | 463 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT); |
f078f209 | 464 | |
e8324357 S |
465 | /* |
466 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
467 | * The IE, however can hold upto 65536, which shows up here | |
468 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 469 | */ |
e8324357 S |
470 | maxampdu = tid->an->maxampdu; |
471 | if (maxampdu) | |
472 | aggr_limit = min(aggr_limit, maxampdu); | |
f078f209 | 473 | |
e8324357 S |
474 | return aggr_limit; |
475 | } | |
f078f209 | 476 | |
e8324357 | 477 | /* |
d43f3015 | 478 | * Returns the number of delimiters to be added to |
e8324357 | 479 | * meet the minimum required mpdudensity. |
d43f3015 | 480 | * caller should make sure that the rate is HT rate . |
e8324357 S |
481 | */ |
482 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
483 | struct ath_buf *bf, u16 frmlen) | |
484 | { | |
485 | struct ath_rate_table *rt = sc->cur_rate_table; | |
486 | struct sk_buff *skb = bf->bf_mpdu; | |
487 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
488 | u32 nsymbits, nsymbols, mpdudensity; | |
489 | u16 minlen; | |
490 | u8 rc, flags, rix; | |
491 | int width, half_gi, ndelim, mindelim; | |
492 | ||
493 | /* Select standard number of delimiters based on frame length alone */ | |
494 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
495 | |
496 | /* | |
e8324357 S |
497 | * If encryption enabled, hardware requires some more padding between |
498 | * subframes. | |
499 | * TODO - this could be improved to be dependent on the rate. | |
500 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 501 | */ |
e8324357 S |
502 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
503 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 504 | |
e8324357 S |
505 | /* |
506 | * Convert desired mpdu density from microeconds to bytes based | |
507 | * on highest rate in rate series (i.e. first rate) to determine | |
508 | * required minimum length for subframe. Take into account | |
509 | * whether high rate is 20 or 40Mhz and half or full GI. | |
510 | */ | |
511 | mpdudensity = tid->an->mpdudensity; | |
f078f209 | 512 | |
e8324357 S |
513 | /* |
514 | * If there is no mpdu density restriction, no further calculation | |
515 | * is needed. | |
516 | */ | |
517 | if (mpdudensity == 0) | |
518 | return ndelim; | |
f078f209 | 519 | |
e8324357 S |
520 | rix = tx_info->control.rates[0].idx; |
521 | flags = tx_info->control.rates[0].flags; | |
522 | rc = rt->info[rix].ratecode; | |
523 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
524 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 525 | |
e8324357 S |
526 | if (half_gi) |
527 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
528 | else | |
529 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
f078f209 | 530 | |
e8324357 S |
531 | if (nsymbols == 0) |
532 | nsymbols = 1; | |
f078f209 | 533 | |
e8324357 S |
534 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
535 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 536 | |
e8324357 | 537 | if (frmlen < minlen) { |
e8324357 S |
538 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
539 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
540 | } |
541 | ||
e8324357 | 542 | return ndelim; |
f078f209 LR |
543 | } |
544 | ||
e8324357 | 545 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
d43f3015 S |
546 | struct ath_atx_tid *tid, |
547 | struct list_head *bf_q) | |
f078f209 | 548 | { |
e8324357 | 549 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
550 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
551 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
552 | u16 aggr_limit = 0, al = 0, bpad = 0, |
553 | al_delta, h_baw = tid->baw_size / 2; | |
554 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 555 | |
e8324357 | 556 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 557 | |
e8324357 S |
558 | do { |
559 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 560 | |
d43f3015 | 561 | /* do not step over block-ack window */ |
e8324357 S |
562 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
563 | status = ATH_AGGR_BAW_CLOSED; | |
564 | break; | |
565 | } | |
f078f209 | 566 | |
e8324357 S |
567 | if (!rl) { |
568 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
569 | rl = 1; | |
570 | } | |
f078f209 | 571 | |
d43f3015 | 572 | /* do not exceed aggregation limit */ |
e8324357 | 573 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 574 | |
d43f3015 S |
575 | if (nframes && |
576 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
577 | status = ATH_AGGR_LIMITED; |
578 | break; | |
579 | } | |
f078f209 | 580 | |
d43f3015 S |
581 | /* do not exceed subframe limit */ |
582 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
583 | status = ATH_AGGR_LIMITED; |
584 | break; | |
585 | } | |
d43f3015 | 586 | nframes++; |
f078f209 | 587 | |
d43f3015 | 588 | /* add padding for previous frame to aggregation length */ |
e8324357 | 589 | al += bpad + al_delta; |
f078f209 | 590 | |
e8324357 S |
591 | /* |
592 | * Get the delimiters needed to meet the MPDU | |
593 | * density for this node. | |
594 | */ | |
595 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 596 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 597 | |
e8324357 | 598 | bf->bf_next = NULL; |
d43f3015 | 599 | bf->bf_desc->ds_link = 0; |
f078f209 | 600 | |
d43f3015 | 601 | /* link buffers of this frame to the aggregate */ |
e8324357 | 602 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
603 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
604 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
605 | if (bf_prev) { |
606 | bf_prev->bf_next = bf; | |
d43f3015 | 607 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
608 | } |
609 | bf_prev = bf; | |
e8324357 | 610 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 611 | |
e8324357 S |
612 | bf_first->bf_al = al; |
613 | bf_first->bf_nframes = nframes; | |
d43f3015 | 614 | |
e8324357 S |
615 | return status; |
616 | #undef PADBYTES | |
617 | } | |
f078f209 | 618 | |
e8324357 S |
619 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
620 | struct ath_atx_tid *tid) | |
621 | { | |
d43f3015 | 622 | struct ath_buf *bf; |
e8324357 S |
623 | enum ATH_AGGR_STATUS status; |
624 | struct list_head bf_q; | |
f078f209 | 625 | |
e8324357 S |
626 | do { |
627 | if (list_empty(&tid->buf_q)) | |
628 | return; | |
f078f209 | 629 | |
e8324357 S |
630 | INIT_LIST_HEAD(&bf_q); |
631 | ||
d43f3015 | 632 | status = ath_tx_form_aggr(sc, tid, &bf_q); |
f078f209 | 633 | |
f078f209 | 634 | /* |
d43f3015 S |
635 | * no frames picked up to be aggregated; |
636 | * block-ack window is not open. | |
f078f209 | 637 | */ |
e8324357 S |
638 | if (list_empty(&bf_q)) |
639 | break; | |
f078f209 | 640 | |
e8324357 | 641 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 642 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 643 | |
d43f3015 | 644 | /* if only one frame, send as non-aggregate */ |
e8324357 | 645 | if (bf->bf_nframes == 1) { |
e8324357 | 646 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 647 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
648 | ath_buf_set_rate(sc, bf); |
649 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
650 | continue; | |
651 | } | |
f078f209 | 652 | |
d43f3015 | 653 | /* setup first desc of aggregate */ |
e8324357 S |
654 | bf->bf_state.bf_type |= BUF_AGGR; |
655 | ath_buf_set_rate(sc, bf); | |
656 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 657 | |
d43f3015 S |
658 | /* anchor last desc of aggregate */ |
659 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 660 | |
e8324357 | 661 | txq->axq_aggr_depth++; |
e8324357 | 662 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
f078f209 | 663 | |
e8324357 S |
664 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
665 | status != ATH_AGGR_BAW_CLOSED); | |
666 | } | |
667 | ||
668 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
669 | u16 tid, u16 *ssn) | |
670 | { | |
671 | struct ath_atx_tid *txtid; | |
672 | struct ath_node *an; | |
673 | ||
674 | an = (struct ath_node *)sta->drv_priv; | |
675 | ||
676 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
677 | txtid = ATH_AN_2_TID(an, tid); | |
678 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
679 | ath_tx_pause_tid(sc, txtid); | |
d22b0022 | 680 | *ssn = txtid->seq_start; |
f078f209 LR |
681 | } |
682 | ||
e8324357 S |
683 | return 0; |
684 | } | |
f078f209 | 685 | |
e8324357 S |
686 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
687 | { | |
688 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
689 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
690 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
691 | struct ath_buf *bf; | |
692 | struct list_head bf_head; | |
693 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 694 | |
e8324357 S |
695 | if (txtid->state & AGGR_CLEANUP) |
696 | return 0; | |
f078f209 | 697 | |
e8324357 S |
698 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
699 | txtid->addba_exchangeattempts = 0; | |
700 | return 0; | |
701 | } | |
f078f209 | 702 | |
e8324357 S |
703 | ath_tx_pause_tid(sc, txtid); |
704 | ||
705 | /* drop all software retried frames and mark this TID */ | |
706 | spin_lock_bh(&txq->axq_lock); | |
707 | while (!list_empty(&txtid->buf_q)) { | |
708 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
709 | if (!bf_isretried(bf)) { | |
710 | /* | |
711 | * NB: it's based on the assumption that | |
712 | * software retried frame will always stay | |
713 | * at the head of software queue. | |
714 | */ | |
715 | break; | |
716 | } | |
d43f3015 | 717 | list_move_tail(&bf->list, &bf_head); |
e8324357 S |
718 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
719 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 | 720 | } |
d43f3015 | 721 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 722 | |
e8324357 | 723 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
724 | txtid->state |= AGGR_CLEANUP; |
725 | } else { | |
726 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
727 | txtid->addba_exchangeattempts = 0; | |
e8324357 | 728 | ath_tx_flush_tid(sc, txtid); |
f078f209 LR |
729 | } |
730 | ||
e8324357 S |
731 | return 0; |
732 | } | |
f078f209 | 733 | |
e8324357 S |
734 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
735 | { | |
736 | struct ath_atx_tid *txtid; | |
737 | struct ath_node *an; | |
738 | ||
739 | an = (struct ath_node *)sta->drv_priv; | |
740 | ||
741 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
742 | txtid = ATH_AN_2_TID(an, tid); | |
743 | txtid->baw_size = | |
744 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
745 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
746 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
747 | ath_tx_resume_tid(sc, txtid); | |
748 | } | |
f078f209 LR |
749 | } |
750 | ||
e8324357 | 751 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 752 | { |
e8324357 | 753 | struct ath_atx_tid *txtid; |
c4288390 | 754 | |
e8324357 S |
755 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
756 | return false; | |
c4288390 | 757 | |
e8324357 S |
758 | txtid = ATH_AN_2_TID(an, tidno); |
759 | ||
760 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { | |
761 | if (!(txtid->state & AGGR_ADDBA_PROGRESS) && | |
762 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
763 | txtid->addba_exchangeattempts++; | |
764 | return true; | |
c4288390 S |
765 | } |
766 | } | |
e8324357 S |
767 | |
768 | return false; | |
c4288390 S |
769 | } |
770 | ||
e8324357 S |
771 | /********************/ |
772 | /* Queue Management */ | |
773 | /********************/ | |
f078f209 | 774 | |
e8324357 S |
775 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
776 | struct ath_txq *txq) | |
f078f209 | 777 | { |
e8324357 S |
778 | struct ath_atx_ac *ac, *ac_tmp; |
779 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 780 | |
e8324357 S |
781 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
782 | list_del(&ac->list); | |
783 | ac->sched = false; | |
784 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
785 | list_del(&tid->list); | |
786 | tid->sched = false; | |
787 | ath_tid_drain(sc, txq, tid); | |
788 | } | |
f078f209 LR |
789 | } |
790 | } | |
791 | ||
e8324357 | 792 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 793 | { |
cbe61d8a | 794 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
795 | struct ath9k_tx_queue_info qi; |
796 | int qnum; | |
f078f209 | 797 | |
e8324357 S |
798 | memset(&qi, 0, sizeof(qi)); |
799 | qi.tqi_subtype = subtype; | |
800 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
801 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
802 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
803 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
804 | |
805 | /* | |
e8324357 S |
806 | * Enable interrupts only for EOL and DESC conditions. |
807 | * We mark tx descriptors to receive a DESC interrupt | |
808 | * when a tx queue gets deep; otherwise waiting for the | |
809 | * EOL to reap descriptors. Note that this is done to | |
810 | * reduce interrupt load and this only defers reaping | |
811 | * descriptors, never transmitting frames. Aside from | |
812 | * reducing interrupts this also permits more concurrency. | |
813 | * The only potential downside is if the tx queue backs | |
814 | * up in which case the top half of the kernel may backup | |
815 | * due to a lack of tx descriptors. | |
816 | * | |
817 | * The UAPSD queue is an exception, since we take a desc- | |
818 | * based intr on the EOSP frames. | |
f078f209 | 819 | */ |
e8324357 S |
820 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
821 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
822 | else | |
823 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
824 | TXQ_FLAG_TXDESCINT_ENABLE; | |
825 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
826 | if (qnum == -1) { | |
f078f209 | 827 | /* |
e8324357 S |
828 | * NB: don't print a message, this happens |
829 | * normally on parts with too few tx queues | |
f078f209 | 830 | */ |
e8324357 | 831 | return NULL; |
f078f209 | 832 | } |
e8324357 S |
833 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
834 | DPRINTF(sc, ATH_DBG_FATAL, | |
835 | "qnum %u out of range, max %u!\n", | |
836 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
837 | ath9k_hw_releasetxqueue(ah, qnum); | |
838 | return NULL; | |
839 | } | |
840 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
841 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 842 | |
e8324357 S |
843 | txq->axq_qnum = qnum; |
844 | txq->axq_link = NULL; | |
845 | INIT_LIST_HEAD(&txq->axq_q); | |
846 | INIT_LIST_HEAD(&txq->axq_acq); | |
847 | spin_lock_init(&txq->axq_lock); | |
848 | txq->axq_depth = 0; | |
849 | txq->axq_aggr_depth = 0; | |
850 | txq->axq_totalqueued = 0; | |
851 | txq->axq_linkbuf = NULL; | |
852 | sc->tx.txqsetup |= 1<<qnum; | |
853 | } | |
854 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
855 | } |
856 | ||
e8324357 | 857 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 858 | { |
e8324357 | 859 | int qnum; |
f078f209 | 860 | |
e8324357 S |
861 | switch (qtype) { |
862 | case ATH9K_TX_QUEUE_DATA: | |
863 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
864 | DPRINTF(sc, ATH_DBG_FATAL, | |
865 | "HAL AC %u out of range, max %zu!\n", | |
866 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
867 | return -1; | |
868 | } | |
869 | qnum = sc->tx.hwq_map[haltype]; | |
870 | break; | |
871 | case ATH9K_TX_QUEUE_BEACON: | |
872 | qnum = sc->beacon.beaconq; | |
873 | break; | |
874 | case ATH9K_TX_QUEUE_CAB: | |
875 | qnum = sc->beacon.cabq->axq_qnum; | |
876 | break; | |
877 | default: | |
878 | qnum = -1; | |
879 | } | |
880 | return qnum; | |
881 | } | |
f078f209 | 882 | |
e8324357 S |
883 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
884 | { | |
885 | struct ath_txq *txq = NULL; | |
886 | int qnum; | |
f078f209 | 887 | |
e8324357 S |
888 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
889 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 890 | |
e8324357 S |
891 | spin_lock_bh(&txq->axq_lock); |
892 | ||
893 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
894 | DPRINTF(sc, ATH_DBG_FATAL, | |
895 | "TX queue: %d is full, depth: %d\n", | |
896 | qnum, txq->axq_depth); | |
897 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
898 | txq->stopped = 1; | |
899 | spin_unlock_bh(&txq->axq_lock); | |
900 | return NULL; | |
f078f209 LR |
901 | } |
902 | ||
e8324357 S |
903 | spin_unlock_bh(&txq->axq_lock); |
904 | ||
905 | return txq; | |
906 | } | |
907 | ||
908 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
909 | struct ath9k_tx_queue_info *qinfo) | |
910 | { | |
cbe61d8a | 911 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
912 | int error = 0; |
913 | struct ath9k_tx_queue_info qi; | |
914 | ||
915 | if (qnum == sc->beacon.beaconq) { | |
916 | /* | |
917 | * XXX: for beacon queue, we just save the parameter. | |
918 | * It will be picked up by ath_beaconq_config when | |
919 | * it's necessary. | |
920 | */ | |
921 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 922 | return 0; |
e8324357 | 923 | } |
f078f209 | 924 | |
e8324357 S |
925 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
926 | ||
927 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
928 | qi.tqi_aifs = qinfo->tqi_aifs; | |
929 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
930 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
931 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
932 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
933 | ||
934 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
935 | DPRINTF(sc, ATH_DBG_FATAL, | |
936 | "Unable to update hardware queue %u!\n", qnum); | |
937 | error = -EIO; | |
938 | } else { | |
939 | ath9k_hw_resettxqueue(ah, qnum); | |
940 | } | |
941 | ||
942 | return error; | |
943 | } | |
944 | ||
945 | int ath_cabq_update(struct ath_softc *sc) | |
946 | { | |
947 | struct ath9k_tx_queue_info qi; | |
948 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 949 | |
e8324357 | 950 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 951 | /* |
e8324357 | 952 | * Ensure the readytime % is within the bounds. |
f078f209 | 953 | */ |
17d7904d S |
954 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
955 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
956 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
957 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 958 | |
fdbf7335 S |
959 | qi.tqi_readyTime = (sc->hw->conf.beacon_int * |
960 | sc->config.cabqReadytime) / 100; | |
e8324357 S |
961 | ath_txq_update(sc, qnum, &qi); |
962 | ||
963 | return 0; | |
f078f209 LR |
964 | } |
965 | ||
043a0405 S |
966 | /* |
967 | * Drain a given TX queue (could be Beacon or Data) | |
968 | * | |
969 | * This assumes output has been stopped and | |
970 | * we do not need to block ath_tx_tasklet. | |
971 | */ | |
972 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 973 | { |
e8324357 S |
974 | struct ath_buf *bf, *lastbf; |
975 | struct list_head bf_head; | |
f078f209 | 976 | |
e8324357 | 977 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 978 | |
e8324357 S |
979 | for (;;) { |
980 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 981 | |
e8324357 S |
982 | if (list_empty(&txq->axq_q)) { |
983 | txq->axq_link = NULL; | |
984 | txq->axq_linkbuf = NULL; | |
985 | spin_unlock_bh(&txq->axq_lock); | |
986 | break; | |
987 | } | |
f078f209 | 988 | |
e8324357 | 989 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 990 | |
e8324357 S |
991 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
992 | list_del(&bf->list); | |
993 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 994 | |
e8324357 S |
995 | spin_lock_bh(&sc->tx.txbuflock); |
996 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
997 | spin_unlock_bh(&sc->tx.txbuflock); | |
998 | continue; | |
999 | } | |
f078f209 | 1000 | |
e8324357 S |
1001 | lastbf = bf->bf_lastbf; |
1002 | if (!retry_tx) | |
1003 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1004 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1005 | |
e8324357 S |
1006 | /* remove ath_buf's of the same mpdu from txq */ |
1007 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1008 | txq->axq_depth--; | |
f078f209 | 1009 | |
e8324357 S |
1010 | spin_unlock_bh(&txq->axq_lock); |
1011 | ||
1012 | if (bf_isampdu(bf)) | |
d43f3015 | 1013 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 S |
1014 | else |
1015 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
1016 | } |
1017 | ||
e8324357 S |
1018 | /* flush any pending frames if aggregation is enabled */ |
1019 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1020 | if (!retry_tx) { | |
1021 | spin_lock_bh(&txq->axq_lock); | |
1022 | ath_txq_drain_pending_buffers(sc, txq); | |
1023 | spin_unlock_bh(&txq->axq_lock); | |
1024 | } | |
1025 | } | |
f078f209 LR |
1026 | } |
1027 | ||
043a0405 | 1028 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1029 | { |
cbe61d8a | 1030 | struct ath_hw *ah = sc->sc_ah; |
043a0405 S |
1031 | struct ath_txq *txq; |
1032 | int i, npend = 0; | |
1033 | ||
1034 | if (sc->sc_flags & SC_OP_INVALID) | |
1035 | return; | |
1036 | ||
1037 | /* Stop beacon queue */ | |
1038 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1039 | ||
1040 | /* Stop data queues */ | |
1041 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1042 | if (ATH_TXQ_SETUP(sc, i)) { | |
1043 | txq = &sc->tx.txq[i]; | |
1044 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1045 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | if (npend) { | |
1050 | int r; | |
1051 | ||
1052 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); | |
1053 | ||
1054 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1055 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); |
043a0405 S |
1056 | if (r) |
1057 | DPRINTF(sc, ATH_DBG_FATAL, | |
1058 | "Unable to reset hardware; reset status %u\n", | |
1059 | r); | |
1060 | spin_unlock_bh(&sc->sc_resetlock); | |
1061 | } | |
1062 | ||
1063 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1064 | if (ATH_TXQ_SETUP(sc, i)) | |
1065 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1066 | } | |
e8324357 | 1067 | } |
f078f209 | 1068 | |
043a0405 | 1069 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1070 | { |
043a0405 S |
1071 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1072 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1073 | } |
f078f209 | 1074 | |
e8324357 S |
1075 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1076 | { | |
1077 | struct ath_atx_ac *ac; | |
1078 | struct ath_atx_tid *tid; | |
f078f209 | 1079 | |
e8324357 S |
1080 | if (list_empty(&txq->axq_acq)) |
1081 | return; | |
f078f209 | 1082 | |
e8324357 S |
1083 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1084 | list_del(&ac->list); | |
1085 | ac->sched = false; | |
f078f209 | 1086 | |
e8324357 S |
1087 | do { |
1088 | if (list_empty(&ac->tid_q)) | |
1089 | return; | |
f078f209 | 1090 | |
e8324357 S |
1091 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1092 | list_del(&tid->list); | |
1093 | tid->sched = false; | |
f078f209 | 1094 | |
e8324357 S |
1095 | if (tid->paused) |
1096 | continue; | |
f078f209 | 1097 | |
e8324357 S |
1098 | if ((txq->axq_depth % 2) == 0) |
1099 | ath_tx_sched_aggr(sc, txq, tid); | |
f078f209 LR |
1100 | |
1101 | /* | |
e8324357 S |
1102 | * add tid to round-robin queue if more frames |
1103 | * are pending for the tid | |
f078f209 | 1104 | */ |
e8324357 S |
1105 | if (!list_empty(&tid->buf_q)) |
1106 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1107 | |
e8324357 S |
1108 | break; |
1109 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1110 | |
e8324357 S |
1111 | if (!list_empty(&ac->tid_q)) { |
1112 | if (!ac->sched) { | |
1113 | ac->sched = true; | |
1114 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1115 | } |
e8324357 S |
1116 | } |
1117 | } | |
f078f209 | 1118 | |
e8324357 S |
1119 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1120 | { | |
1121 | struct ath_txq *txq; | |
f078f209 | 1122 | |
e8324357 S |
1123 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1124 | DPRINTF(sc, ATH_DBG_FATAL, | |
1125 | "HAL AC %u out of range, max %zu!\n", | |
1126 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1127 | return 0; | |
1128 | } | |
1129 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1130 | if (txq != NULL) { | |
1131 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1132 | return 1; | |
1133 | } else | |
1134 | return 0; | |
f078f209 LR |
1135 | } |
1136 | ||
e8324357 S |
1137 | /***********/ |
1138 | /* TX, DMA */ | |
1139 | /***********/ | |
1140 | ||
f078f209 | 1141 | /* |
e8324357 S |
1142 | * Insert a chain of ath_buf (descriptors) on a txq and |
1143 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1144 | */ |
e8324357 S |
1145 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1146 | struct list_head *head) | |
f078f209 | 1147 | { |
cbe61d8a | 1148 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1149 | struct ath_buf *bf; |
f078f209 | 1150 | |
e8324357 S |
1151 | /* |
1152 | * Insert the frame on the outbound list and | |
1153 | * pass it on to the hardware. | |
1154 | */ | |
f078f209 | 1155 | |
e8324357 S |
1156 | if (list_empty(head)) |
1157 | return; | |
f078f209 | 1158 | |
e8324357 | 1159 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1160 | |
e8324357 S |
1161 | list_splice_tail_init(head, &txq->axq_q); |
1162 | txq->axq_depth++; | |
1163 | txq->axq_totalqueued++; | |
1164 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
f078f209 | 1165 | |
e8324357 S |
1166 | DPRINTF(sc, ATH_DBG_QUEUE, |
1167 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1168 | |
e8324357 S |
1169 | if (txq->axq_link == NULL) { |
1170 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1171 | DPRINTF(sc, ATH_DBG_XMIT, | |
1172 | "TXDP[%u] = %llx (%p)\n", | |
1173 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1174 | } else { | |
1175 | *txq->axq_link = bf->bf_daddr; | |
1176 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1177 | txq->axq_qnum, txq->axq_link, | |
1178 | ito64(bf->bf_daddr), bf->bf_desc); | |
1179 | } | |
1180 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1181 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1182 | } | |
f078f209 | 1183 | |
e8324357 S |
1184 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1185 | { | |
1186 | struct ath_buf *bf = NULL; | |
f078f209 | 1187 | |
e8324357 | 1188 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1189 | |
e8324357 S |
1190 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1191 | spin_unlock_bh(&sc->tx.txbuflock); | |
1192 | return NULL; | |
1193 | } | |
f078f209 | 1194 | |
e8324357 S |
1195 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1196 | list_del(&bf->list); | |
f078f209 | 1197 | |
e8324357 | 1198 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1199 | |
e8324357 | 1200 | return bf; |
f078f209 LR |
1201 | } |
1202 | ||
e8324357 S |
1203 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1204 | struct list_head *bf_head, | |
1205 | struct ath_tx_control *txctl) | |
f078f209 LR |
1206 | { |
1207 | struct ath_buf *bf; | |
f078f209 | 1208 | |
e8324357 S |
1209 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1210 | bf->bf_state.bf_type |= BUF_AMPDU; | |
f078f209 | 1211 | |
e8324357 S |
1212 | /* |
1213 | * Do not queue to h/w when any of the following conditions is true: | |
1214 | * - there are pending frames in software queue | |
1215 | * - the TID is currently paused for ADDBA/BAR request | |
1216 | * - seqno is not within block-ack window | |
1217 | * - h/w queue depth exceeds low water mark | |
1218 | */ | |
1219 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1220 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1221 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1222 | /* |
e8324357 S |
1223 | * Add this frame to software queue for scheduling later |
1224 | * for aggregation. | |
f078f209 | 1225 | */ |
d43f3015 | 1226 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1227 | ath_tx_queue_tid(txctl->txq, tid); |
1228 | return; | |
1229 | } | |
1230 | ||
1231 | /* Add sub-frame to BAW */ | |
1232 | ath_tx_addto_baw(sc, tid, bf); | |
1233 | ||
1234 | /* Queue to h/w without aggregation */ | |
1235 | bf->bf_nframes = 1; | |
d43f3015 | 1236 | bf->bf_lastbf = bf; |
e8324357 S |
1237 | ath_buf_set_rate(sc, bf); |
1238 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1239 | } |
1240 | ||
1241 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, | |
1242 | struct ath_atx_tid *tid, | |
1243 | struct list_head *bf_head) | |
1244 | { | |
1245 | struct ath_buf *bf; | |
1246 | ||
e8324357 S |
1247 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1248 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1249 | ||
1250 | /* update starting sequence number for subsequent ADDBA request */ | |
1251 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1252 | ||
1253 | bf->bf_nframes = 1; | |
d43f3015 | 1254 | bf->bf_lastbf = bf; |
e8324357 S |
1255 | ath_buf_set_rate(sc, bf); |
1256 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1257 | } | |
1258 | ||
1259 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) | |
1260 | { | |
1261 | struct ieee80211_hdr *hdr; | |
1262 | enum ath9k_pkt_type htype; | |
1263 | __le16 fc; | |
1264 | ||
1265 | hdr = (struct ieee80211_hdr *)skb->data; | |
1266 | fc = hdr->frame_control; | |
1267 | ||
1268 | if (ieee80211_is_beacon(fc)) | |
1269 | htype = ATH9K_PKT_TYPE_BEACON; | |
1270 | else if (ieee80211_is_probe_resp(fc)) | |
1271 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1272 | else if (ieee80211_is_atim(fc)) | |
1273 | htype = ATH9K_PKT_TYPE_ATIM; | |
1274 | else if (ieee80211_is_pspoll(fc)) | |
1275 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1276 | else | |
1277 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1278 | ||
1279 | return htype; | |
1280 | } | |
1281 | ||
1282 | static bool is_pae(struct sk_buff *skb) | |
1283 | { | |
1284 | struct ieee80211_hdr *hdr; | |
1285 | __le16 fc; | |
1286 | ||
1287 | hdr = (struct ieee80211_hdr *)skb->data; | |
1288 | fc = hdr->frame_control; | |
1289 | ||
1290 | if (ieee80211_is_data(fc)) { | |
1291 | if (ieee80211_is_nullfunc(fc) || | |
1292 | /* Port Access Entity (IEEE 802.1X) */ | |
1293 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1294 | return true; | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | return false; | |
1299 | } | |
1300 | ||
1301 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1302 | { | |
1303 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1304 | ||
1305 | if (tx_info->control.hw_key) { | |
1306 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1307 | return ATH9K_KEY_TYPE_WEP; | |
1308 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1309 | return ATH9K_KEY_TYPE_TKIP; | |
1310 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1311 | return ATH9K_KEY_TYPE_AES; | |
1312 | } | |
1313 | ||
1314 | return ATH9K_KEY_TYPE_CLEAR; | |
1315 | } | |
1316 | ||
1317 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1318 | struct ath_buf *bf) | |
1319 | { | |
1320 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1321 | struct ieee80211_hdr *hdr; | |
1322 | struct ath_node *an; | |
1323 | struct ath_atx_tid *tid; | |
1324 | __le16 fc; | |
1325 | u8 *qc; | |
1326 | ||
1327 | if (!tx_info->control.sta) | |
1328 | return; | |
1329 | ||
1330 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1331 | hdr = (struct ieee80211_hdr *)skb->data; | |
1332 | fc = hdr->frame_control; | |
1333 | ||
1334 | if (ieee80211_is_data_qos(fc)) { | |
1335 | qc = ieee80211_get_qos_ctl(hdr); | |
1336 | bf->bf_tidno = qc[0] & 0xf; | |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * For HT capable stations, we save tidno for later use. | |
1341 | * We also override seqno set by upper layer with the one | |
1342 | * in tx aggregation state. | |
1343 | * | |
1344 | * If fragmentation is on, the sequence number is | |
1345 | * not overridden, since it has been | |
1346 | * incremented by the fragmentation routine. | |
1347 | * | |
1348 | * FIXME: check if the fragmentation threshold exceeds | |
1349 | * IEEE80211 max. | |
1350 | */ | |
1351 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1352 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1353 | IEEE80211_SEQ_SEQ_SHIFT); | |
1354 | bf->bf_seqno = tid->seq_next; | |
1355 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1356 | } | |
1357 | ||
1358 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1359 | struct ath_txq *txq) | |
1360 | { | |
1361 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1362 | int flags = 0; | |
1363 | ||
1364 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1365 | flags |= ATH9K_TXDESC_INTREQ; | |
1366 | ||
1367 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1368 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1369 | |
1370 | return flags; | |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * rix - rate index | |
1375 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1376 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1377 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1378 | */ | |
1379 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1380 | int width, int half_gi, bool shortPreamble) | |
1381 | { | |
1382 | struct ath_rate_table *rate_table = sc->cur_rate_table; | |
1383 | u32 nbits, nsymbits, duration, nsymbols; | |
1384 | u8 rc; | |
1385 | int streams, pktlen; | |
1386 | ||
1387 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1388 | rc = rate_table->info[rix].ratecode; | |
1389 | ||
1390 | /* for legacy rates, use old function to compute packet duration */ | |
1391 | if (!IS_HT_RATE(rc)) | |
1392 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1393 | rix, shortPreamble); | |
1394 | ||
1395 | /* find number of symbols: PLCP + data */ | |
1396 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1397 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1398 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1399 | ||
1400 | if (!half_gi) | |
1401 | duration = SYMBOL_TIME(nsymbols); | |
1402 | else | |
1403 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1404 | ||
1405 | /* addup duration for legacy/ht training and signal fields */ | |
1406 | streams = HT_RC_2_STREAMS(rc); | |
1407 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1408 | ||
1409 | return duration; | |
1410 | } | |
1411 | ||
1412 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1413 | { | |
c89424df | 1414 | struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
1415 | struct ath9k_11n_rate_series series[4]; |
1416 | struct sk_buff *skb; | |
1417 | struct ieee80211_tx_info *tx_info; | |
1418 | struct ieee80211_tx_rate *rates; | |
254ad0ff | 1419 | struct ieee80211_hdr *hdr; |
c89424df S |
1420 | int i, flags = 0; |
1421 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1422 | bool is_pspoll; |
e8324357 S |
1423 | |
1424 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1425 | ||
1426 | skb = (struct sk_buff *)bf->bf_mpdu; | |
e8324357 S |
1427 | tx_info = IEEE80211_SKB_CB(skb); |
1428 | rates = tx_info->control.rates; | |
254ad0ff S |
1429 | hdr = (struct ieee80211_hdr *)skb->data; |
1430 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1431 | |
e8324357 | 1432 | /* |
c89424df S |
1433 | * We check if Short Preamble is needed for the CTS rate by |
1434 | * checking the BSS's global flag. | |
1435 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1436 | */ |
c89424df S |
1437 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
1438 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | | |
1439 | rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; | |
1440 | else | |
1441 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; | |
e8324357 | 1442 | |
c89424df S |
1443 | /* |
1444 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1445 | * Check the first rate in the series to decide whether RTS/CTS | |
1446 | * or CTS-to-self has to be used. | |
e8324357 | 1447 | */ |
c89424df S |
1448 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1449 | flags = ATH9K_TXDESC_CTSENA; | |
1450 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1451 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1452 | |
c89424df | 1453 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1454 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1455 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1456 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1457 | } |
1458 | ||
1459 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1460 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1461 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1462 | ||
e8324357 S |
1463 | for (i = 0; i < 4; i++) { |
1464 | if (!rates[i].count || (rates[i].idx < 0)) | |
1465 | continue; | |
1466 | ||
1467 | rix = rates[i].idx; | |
e8324357 | 1468 | series[i].Tries = rates[i].count; |
17d7904d | 1469 | series[i].ChSel = sc->tx_chainmask; |
e8324357 | 1470 | |
c89424df S |
1471 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
1472 | series[i].Rate = rt->info[rix].ratecode | | |
1473 | rt->info[rix].short_preamble; | |
1474 | else | |
1475 | series[i].Rate = rt->info[rix].ratecode; | |
1476 | ||
1477 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1478 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1479 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1480 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1481 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1482 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 S |
1483 | |
1484 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1485 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1486 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
c89424df | 1487 | (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); |
f078f209 LR |
1488 | } |
1489 | ||
e8324357 | 1490 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1491 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1492 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1493 | !is_pspoll, ctsrate, |
c89424df | 1494 | 0, series, 4, flags); |
f078f209 | 1495 | |
17d7904d | 1496 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1497 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1498 | } |
1499 | ||
c52f33d0 | 1500 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1501 | struct sk_buff *skb, |
528f0c6b | 1502 | struct ath_tx_control *txctl) |
f078f209 | 1503 | { |
c52f33d0 JM |
1504 | struct ath_wiphy *aphy = hw->priv; |
1505 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1506 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1507 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1508 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1509 | int hdrlen; |
1510 | __le16 fc; | |
e022edbd | 1511 | |
c112d0c5 LR |
1512 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1513 | if (unlikely(!tx_info_priv)) | |
1514 | return -ENOMEM; | |
a8efee4f | 1515 | tx_info->rate_driver_data[0] = tx_info_priv; |
c52f33d0 | 1516 | tx_info_priv->aphy = aphy; |
f0ed85c6 | 1517 | tx_info_priv->frame_type = txctl->frame_type; |
528f0c6b S |
1518 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1519 | fc = hdr->frame_control; | |
f078f209 | 1520 | |
528f0c6b | 1521 | ATH_TXBUF_RESET(bf); |
f078f209 | 1522 | |
528f0c6b | 1523 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 | 1524 | |
c656bbb5 S |
1525 | if ((conf_is_ht(&sc->hw->conf) && !is_pae(skb) && |
1526 | (tx_info->flags & IEEE80211_TX_CTL_AMPDU))) | |
1527 | bf->bf_state.bf_type |= BUF_HT; | |
528f0c6b S |
1528 | |
1529 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1530 | ||
528f0c6b | 1531 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1532 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1533 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1534 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1535 | } else { | |
1536 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1537 | } | |
1538 | ||
d3a1db1c | 1539 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1540 | assign_aggr_tid_seqno(skb, bf); |
1541 | ||
f078f209 | 1542 | bf->bf_mpdu = skb; |
f8316df1 | 1543 | |
7da3c55c GJ |
1544 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1545 | skb->len, DMA_TO_DEVICE); | |
1546 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 LR |
1547 | bf->bf_mpdu = NULL; |
1548 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 1549 | "dma_mapping_error() on TX\n"); |
f8316df1 LR |
1550 | return -ENOMEM; |
1551 | } | |
1552 | ||
528f0c6b | 1553 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1554 | return 0; |
528f0c6b S |
1555 | } |
1556 | ||
1557 | /* FIXME: tx power */ | |
1558 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1559 | struct ath_tx_control *txctl) |
1560 | { | |
1561 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
1562 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1563 | struct ath_node *an = NULL; | |
1564 | struct list_head bf_head; | |
1565 | struct ath_desc *ds; | |
1566 | struct ath_atx_tid *tid; | |
cbe61d8a | 1567 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b S |
1568 | int frm_type; |
1569 | ||
528f0c6b S |
1570 | frm_type = get_hw_packet_type(skb); |
1571 | ||
1572 | INIT_LIST_HEAD(&bf_head); | |
1573 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1574 | |
f078f209 LR |
1575 | ds = bf->bf_desc; |
1576 | ds->ds_link = 0; | |
1577 | ds->ds_data = bf->bf_buf_addr; | |
1578 | ||
528f0c6b S |
1579 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1580 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1581 | ||
1582 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1583 | skb->len, /* segment length */ |
1584 | true, /* first segment */ | |
1585 | true, /* last segment */ | |
1586 | ds); /* first descriptor */ | |
f078f209 | 1587 | |
528f0c6b | 1588 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1589 | |
f1617967 JL |
1590 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1591 | tx_info->control.sta) { | |
1592 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1593 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1594 | ||
528f0c6b | 1595 | if (ath_aggr_query(sc, an, bf->bf_tidno)) { |
f078f209 LR |
1596 | /* |
1597 | * Try aggregation if it's a unicast data frame | |
1598 | * and the destination is HT capable. | |
1599 | */ | |
528f0c6b | 1600 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1601 | } else { |
1602 | /* | |
528f0c6b S |
1603 | * Send this frame as regular when ADDBA |
1604 | * exchange is neither complete nor pending. | |
f078f209 | 1605 | */ |
528f0c6b S |
1606 | ath_tx_send_normal(sc, txctl->txq, |
1607 | tid, &bf_head); | |
f078f209 LR |
1608 | } |
1609 | } else { | |
1610 | bf->bf_lastbf = bf; | |
1611 | bf->bf_nframes = 1; | |
f078f209 | 1612 | |
528f0c6b S |
1613 | ath_buf_set_rate(sc, bf); |
1614 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head); | |
f078f209 | 1615 | } |
528f0c6b S |
1616 | |
1617 | spin_unlock_bh(&txctl->txq->axq_lock); | |
f078f209 LR |
1618 | } |
1619 | ||
f8316df1 | 1620 | /* Upon failure caller should free skb */ |
c52f33d0 | 1621 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1622 | struct ath_tx_control *txctl) |
f078f209 | 1623 | { |
c52f33d0 JM |
1624 | struct ath_wiphy *aphy = hw->priv; |
1625 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 1626 | struct ath_buf *bf; |
f8316df1 | 1627 | int r; |
f078f209 | 1628 | |
528f0c6b S |
1629 | bf = ath_tx_get_buffer(sc); |
1630 | if (!bf) { | |
04bd4638 | 1631 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1632 | return -1; |
1633 | } | |
1634 | ||
c52f33d0 | 1635 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1636 | if (unlikely(r)) { |
c112d0c5 LR |
1637 | struct ath_txq *txq = txctl->txq; |
1638 | ||
f8316df1 | 1639 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1640 | |
1641 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1642 | * guarantee this will happen by knowing beforehand that | |
1643 | * we will at least have to run TX completionon one buffer | |
1644 | * on the queue */ | |
1645 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1646 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
c112d0c5 LR |
1647 | ieee80211_stop_queue(sc->hw, |
1648 | skb_get_queue_mapping(skb)); | |
1649 | txq->stopped = 1; | |
1650 | } | |
1651 | spin_unlock_bh(&txq->axq_lock); | |
1652 | ||
b77f483f S |
1653 | spin_lock_bh(&sc->tx.txbuflock); |
1654 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1655 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1656 | |
f8316df1 LR |
1657 | return r; |
1658 | } | |
1659 | ||
8f93b8b3 | 1660 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1661 | |
528f0c6b | 1662 | return 0; |
f078f209 LR |
1663 | } |
1664 | ||
c52f33d0 | 1665 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1666 | { |
c52f33d0 JM |
1667 | struct ath_wiphy *aphy = hw->priv; |
1668 | struct ath_softc *sc = aphy->sc; | |
e8324357 S |
1669 | int hdrlen, padsize; |
1670 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1671 | struct ath_tx_control txctl; | |
f078f209 | 1672 | |
e8324357 | 1673 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1674 | |
1675 | /* | |
e8324357 S |
1676 | * As a temporary workaround, assign seq# here; this will likely need |
1677 | * to be cleaned up to work better with Beacon transmission and virtual | |
1678 | * BSSes. | |
f078f209 | 1679 | */ |
e8324357 S |
1680 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1681 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1682 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1683 | sc->tx.seq_no += 0x10; | |
1684 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1685 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1686 | } |
f078f209 | 1687 | |
e8324357 S |
1688 | /* Add the padding after the header if this is not already done */ |
1689 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1690 | if (hdrlen & 3) { | |
1691 | padsize = hdrlen % 4; | |
1692 | if (skb_headroom(skb) < padsize) { | |
1693 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1694 | dev_kfree_skb_any(skb); | |
1695 | return; | |
1696 | } | |
1697 | skb_push(skb, padsize); | |
1698 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1699 | } |
f078f209 | 1700 | |
e8324357 | 1701 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1702 | |
e8324357 | 1703 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1704 | |
c52f33d0 | 1705 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
e8324357 S |
1706 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); |
1707 | goto exit; | |
f078f209 | 1708 | } |
f078f209 | 1709 | |
e8324357 S |
1710 | return; |
1711 | exit: | |
1712 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1713 | } |
1714 | ||
e8324357 S |
1715 | /*****************/ |
1716 | /* TX Completion */ | |
1717 | /*****************/ | |
528f0c6b | 1718 | |
e8324357 S |
1719 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
1720 | struct ath_xmit_status *tx_status) | |
528f0c6b | 1721 | { |
e8324357 S |
1722 | struct ieee80211_hw *hw = sc->hw; |
1723 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1724 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1725 | int hdrlen, padsize; | |
f0ed85c6 | 1726 | int frame_type = ATH9K_NOT_INTERNAL; |
528f0c6b | 1727 | |
e8324357 | 1728 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1729 | |
f0ed85c6 | 1730 | if (tx_info_priv) { |
c52f33d0 | 1731 | hw = tx_info_priv->aphy->hw; |
f0ed85c6 JM |
1732 | frame_type = tx_info_priv->frame_type; |
1733 | } | |
c52f33d0 | 1734 | |
e8324357 S |
1735 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1736 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1737 | kfree(tx_info_priv); | |
1738 | tx_info->rate_driver_data[0] = NULL; | |
1739 | } | |
528f0c6b | 1740 | |
e8324357 S |
1741 | if (tx_status->flags & ATH_TX_BAR) { |
1742 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
1743 | tx_status->flags &= ~ATH_TX_BAR; | |
1744 | } | |
1745 | ||
1746 | if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { | |
1747 | /* Frame was ACKed */ | |
1748 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1749 | } |
1750 | ||
e8324357 | 1751 | tx_info->status.rates[0].count = tx_status->retries + 1; |
528f0c6b | 1752 | |
e8324357 S |
1753 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1754 | padsize = hdrlen & 3; | |
1755 | if (padsize && hdrlen >= 24) { | |
1756 | /* | |
1757 | * Remove MAC header padding before giving the frame back to | |
1758 | * mac80211. | |
1759 | */ | |
1760 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1761 | skb_pull(skb, padsize); | |
1762 | } | |
528f0c6b | 1763 | |
f0ed85c6 JM |
1764 | if (frame_type == ATH9K_NOT_INTERNAL) |
1765 | ieee80211_tx_status(hw, skb); | |
1766 | else | |
1767 | ath9k_tx_status(hw, skb); | |
e8324357 | 1768 | } |
f078f209 | 1769 | |
e8324357 S |
1770 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
1771 | struct list_head *bf_q, | |
1772 | int txok, int sendbar) | |
f078f209 | 1773 | { |
e8324357 S |
1774 | struct sk_buff *skb = bf->bf_mpdu; |
1775 | struct ath_xmit_status tx_status; | |
1776 | unsigned long flags; | |
f078f209 | 1777 | |
e8324357 S |
1778 | /* |
1779 | * Set retry information. | |
1780 | * NB: Don't use the information in the descriptor, because the frame | |
1781 | * could be software retried. | |
1782 | */ | |
1783 | tx_status.retries = bf->bf_retries; | |
1784 | tx_status.flags = 0; | |
f078f209 | 1785 | |
e8324357 S |
1786 | if (sendbar) |
1787 | tx_status.flags = ATH_TX_BAR; | |
f078f209 | 1788 | |
e8324357 S |
1789 | if (!txok) { |
1790 | tx_status.flags |= ATH_TX_ERROR; | |
f078f209 | 1791 | |
e8324357 S |
1792 | if (bf_isxretried(bf)) |
1793 | tx_status.flags |= ATH_TX_XRETRY; | |
f078f209 LR |
1794 | } |
1795 | ||
e8324357 S |
1796 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
1797 | ath_tx_complete(sc, skb, &tx_status); | |
1798 | ||
1799 | /* | |
1800 | * Return the list of ath_buf of this mpdu to free queue | |
1801 | */ | |
1802 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1803 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1804 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1805 | } |
1806 | ||
e8324357 S |
1807 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1808 | int txok) | |
f078f209 | 1809 | { |
e8324357 S |
1810 | struct ath_buf *bf_last = bf->bf_lastbf; |
1811 | struct ath_desc *ds = bf_last->bf_desc; | |
1812 | u16 seq_st = 0; | |
1813 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1814 | int ba_index; | |
1815 | int nbad = 0; | |
1816 | int isaggr = 0; | |
f078f209 | 1817 | |
e8324357 S |
1818 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1819 | return 0; | |
f078f209 | 1820 | |
e8324357 S |
1821 | isaggr = bf_isaggr(bf); |
1822 | if (isaggr) { | |
1823 | seq_st = ATH_DS_BA_SEQ(ds); | |
1824 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1825 | } | |
f078f209 | 1826 | |
e8324357 S |
1827 | while (bf) { |
1828 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1829 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1830 | nbad++; | |
1831 | ||
1832 | bf = bf->bf_next; | |
1833 | } | |
f078f209 | 1834 | |
e8324357 S |
1835 | return nbad; |
1836 | } | |
f078f209 | 1837 | |
e8324357 | 1838 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad) |
f078f209 | 1839 | { |
e8324357 | 1840 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; |
254ad0ff | 1841 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 S |
1842 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1843 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
f078f209 | 1844 | |
e8324357 S |
1845 | tx_info_priv->update_rc = false; |
1846 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) | |
1847 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1848 | |
e8324357 S |
1849 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
1850 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | |
254ad0ff | 1851 | if (ieee80211_is_data(hdr->frame_control)) { |
e8324357 S |
1852 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, |
1853 | sizeof(tx_info_priv->tx)); | |
1854 | tx_info_priv->n_frames = bf->bf_nframes; | |
1855 | tx_info_priv->n_bad_frames = nbad; | |
1856 | tx_info_priv->update_rc = true; | |
1857 | } | |
f078f209 | 1858 | } |
f078f209 LR |
1859 | } |
1860 | ||
059d806c S |
1861 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1862 | { | |
1863 | int qnum; | |
1864 | ||
1865 | spin_lock_bh(&txq->axq_lock); | |
1866 | if (txq->stopped && | |
f7a99e46 | 1867 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1868 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1869 | if (qnum != -1) { | |
1870 | ieee80211_wake_queue(sc->hw, qnum); | |
1871 | txq->stopped = 0; | |
1872 | } | |
1873 | } | |
1874 | spin_unlock_bh(&txq->axq_lock); | |
1875 | } | |
1876 | ||
e8324357 | 1877 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1878 | { |
cbe61d8a | 1879 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1880 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1881 | struct list_head bf_head; |
e8324357 S |
1882 | struct ath_desc *ds; |
1883 | int txok, nbad = 0; | |
1884 | int status; | |
f078f209 | 1885 | |
e8324357 S |
1886 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1887 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1888 | txq->axq_link); | |
f078f209 | 1889 | |
f078f209 LR |
1890 | for (;;) { |
1891 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1892 | if (list_empty(&txq->axq_q)) { |
1893 | txq->axq_link = NULL; | |
1894 | txq->axq_linkbuf = NULL; | |
1895 | spin_unlock_bh(&txq->axq_lock); | |
1896 | break; | |
1897 | } | |
f078f209 LR |
1898 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1899 | ||
e8324357 S |
1900 | /* |
1901 | * There is a race condition that a BH gets scheduled | |
1902 | * after sw writes TxE and before hw re-load the last | |
1903 | * descriptor to get the newly chained one. | |
1904 | * Software must keep the last DONE descriptor as a | |
1905 | * holding descriptor - software does so by marking | |
1906 | * it with the STALE flag. | |
1907 | */ | |
1908 | bf_held = NULL; | |
f078f209 | 1909 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
e8324357 S |
1910 | bf_held = bf; |
1911 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d S |
1912 | txq->axq_link = NULL; |
1913 | txq->axq_linkbuf = NULL; | |
1914 | spin_unlock_bh(&txq->axq_lock); | |
1915 | ||
1916 | /* | |
e8324357 S |
1917 | * The holding descriptor is the last |
1918 | * descriptor in queue. It's safe to remove | |
1919 | * the last holding descriptor in BH context. | |
1920 | */ | |
6ef9b13d S |
1921 | spin_lock_bh(&sc->tx.txbuflock); |
1922 | list_move_tail(&bf_held->list, &sc->tx.txbuf); | |
1923 | spin_unlock_bh(&sc->tx.txbuflock); | |
1924 | ||
e8324357 S |
1925 | break; |
1926 | } else { | |
1927 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1928 | struct ath_buf, list); |
e8324357 | 1929 | } |
f078f209 LR |
1930 | } |
1931 | ||
1932 | lastbf = bf->bf_lastbf; | |
e8324357 | 1933 | ds = lastbf->bf_desc; |
f078f209 | 1934 | |
e8324357 S |
1935 | status = ath9k_hw_txprocdesc(ah, ds); |
1936 | if (status == -EINPROGRESS) { | |
f078f209 | 1937 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 1938 | break; |
f078f209 | 1939 | } |
e8324357 S |
1940 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
1941 | txq->axq_lastdsWithCTS = NULL; | |
1942 | if (ds == txq->axq_gatingds) | |
1943 | txq->axq_gatingds = NULL; | |
f078f209 | 1944 | |
e8324357 S |
1945 | /* |
1946 | * Remove ath_buf's of the same transmit unit from txq, | |
1947 | * however leave the last descriptor back as the holding | |
1948 | * descriptor for hw. | |
1949 | */ | |
1950 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | |
1951 | INIT_LIST_HEAD(&bf_head); | |
e8324357 S |
1952 | if (!list_is_singular(&lastbf->list)) |
1953 | list_cut_position(&bf_head, | |
1954 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 1955 | |
e8324357 | 1956 | txq->axq_depth--; |
e8324357 S |
1957 | if (bf_isaggr(bf)) |
1958 | txq->axq_aggr_depth--; | |
f078f209 | 1959 | |
e8324357 | 1960 | txok = (ds->ds_txstat.ts_status == 0); |
e8324357 | 1961 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 1962 | |
e8324357 | 1963 | if (bf_held) { |
e8324357 | 1964 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 1965 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
1966 | spin_unlock_bh(&sc->tx.txbuflock); |
1967 | } | |
f078f209 | 1968 | |
e8324357 S |
1969 | if (!bf_isampdu(bf)) { |
1970 | /* | |
1971 | * This frame is sent out as a single frame. | |
1972 | * Use hardware retry status for this frame. | |
1973 | */ | |
1974 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
1975 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
1976 | bf->bf_state.bf_type |= BUF_XRETRY; | |
1977 | nbad = 0; | |
1978 | } else { | |
1979 | nbad = ath_tx_num_badfrms(sc, bf, txok); | |
1980 | } | |
f078f209 | 1981 | |
e8324357 | 1982 | ath_tx_rc_status(bf, ds, nbad); |
f078f209 | 1983 | |
e8324357 | 1984 | if (bf_isampdu(bf)) |
d43f3015 | 1985 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 S |
1986 | else |
1987 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
8469cdef | 1988 | |
059d806c | 1989 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 1990 | |
059d806c | 1991 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
1992 | if (sc->sc_flags & SC_OP_TXAGGR) |
1993 | ath_txq_schedule(sc, txq); | |
1994 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
1995 | } |
1996 | } | |
1997 | ||
f078f209 | 1998 | |
e8324357 | 1999 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2000 | { |
e8324357 S |
2001 | int i; |
2002 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2003 | |
e8324357 | 2004 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2005 | |
e8324357 S |
2006 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2007 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2008 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2009 | } |
2010 | } | |
2011 | ||
e8324357 S |
2012 | /*****************/ |
2013 | /* Init, Cleanup */ | |
2014 | /*****************/ | |
f078f209 | 2015 | |
e8324357 | 2016 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2017 | { |
e8324357 | 2018 | int error = 0; |
f078f209 | 2019 | |
f078f209 | 2020 | do { |
e8324357 | 2021 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2022 | |
e8324357 S |
2023 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2024 | "tx", nbufs, 1); | |
2025 | if (error != 0) { | |
2026 | DPRINTF(sc, ATH_DBG_FATAL, | |
2027 | "Failed to allocate tx descriptors: %d\n", | |
2028 | error); | |
2029 | break; | |
2030 | } | |
f078f209 | 2031 | |
e8324357 S |
2032 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2033 | "beacon", ATH_BCBUF, 1); | |
2034 | if (error != 0) { | |
2035 | DPRINTF(sc, ATH_DBG_FATAL, | |
2036 | "Failed to allocate beacon descriptors: %d\n", | |
2037 | error); | |
2038 | break; | |
2039 | } | |
f078f209 | 2040 | |
e8324357 | 2041 | } while (0); |
f078f209 | 2042 | |
e8324357 S |
2043 | if (error != 0) |
2044 | ath_tx_cleanup(sc); | |
f078f209 | 2045 | |
e8324357 | 2046 | return error; |
f078f209 LR |
2047 | } |
2048 | ||
e8324357 S |
2049 | int ath_tx_cleanup(struct ath_softc *sc) |
2050 | { | |
2051 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2052 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2053 | ||
2054 | if (sc->tx.txdma.dd_desc_len != 0) | |
2055 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
2056 | ||
2057 | return 0; | |
2058 | } | |
f078f209 LR |
2059 | |
2060 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2061 | { | |
c5170163 S |
2062 | struct ath_atx_tid *tid; |
2063 | struct ath_atx_ac *ac; | |
2064 | int tidno, acno; | |
f078f209 | 2065 | |
8ee5afbc | 2066 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2067 | tidno < WME_NUM_TID; |
2068 | tidno++, tid++) { | |
2069 | tid->an = an; | |
2070 | tid->tidno = tidno; | |
2071 | tid->seq_start = tid->seq_next = 0; | |
2072 | tid->baw_size = WME_MAX_BA; | |
2073 | tid->baw_head = tid->baw_tail = 0; | |
2074 | tid->sched = false; | |
e8324357 | 2075 | tid->paused = false; |
a37c2c79 | 2076 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2077 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2078 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2079 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2080 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2081 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
2082 | tid->addba_exchangeattempts = 0; | |
c5170163 | 2083 | } |
f078f209 | 2084 | |
8ee5afbc | 2085 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2086 | acno < WME_NUM_AC; acno++, ac++) { |
2087 | ac->sched = false; | |
2088 | INIT_LIST_HEAD(&ac->tid_q); | |
2089 | ||
2090 | switch (acno) { | |
2091 | case WME_AC_BE: | |
2092 | ac->qnum = ath_tx_get_qnum(sc, | |
2093 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2094 | break; | |
2095 | case WME_AC_BK: | |
2096 | ac->qnum = ath_tx_get_qnum(sc, | |
2097 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2098 | break; | |
2099 | case WME_AC_VI: | |
2100 | ac->qnum = ath_tx_get_qnum(sc, | |
2101 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2102 | break; | |
2103 | case WME_AC_VO: | |
2104 | ac->qnum = ath_tx_get_qnum(sc, | |
2105 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2106 | break; | |
f078f209 LR |
2107 | } |
2108 | } | |
2109 | } | |
2110 | ||
b5aa9bf9 | 2111 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2112 | { |
2113 | int i; | |
2114 | struct ath_atx_ac *ac, *ac_tmp; | |
2115 | struct ath_atx_tid *tid, *tid_tmp; | |
2116 | struct ath_txq *txq; | |
e8324357 | 2117 | |
f078f209 LR |
2118 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2119 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2120 | txq = &sc->tx.txq[i]; |
f078f209 | 2121 | |
b5aa9bf9 | 2122 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2123 | |
2124 | list_for_each_entry_safe(ac, | |
2125 | ac_tmp, &txq->axq_acq, list) { | |
2126 | tid = list_first_entry(&ac->tid_q, | |
2127 | struct ath_atx_tid, list); | |
2128 | if (tid && tid->an != an) | |
2129 | continue; | |
2130 | list_del(&ac->list); | |
2131 | ac->sched = false; | |
2132 | ||
2133 | list_for_each_entry_safe(tid, | |
2134 | tid_tmp, &ac->tid_q, list) { | |
2135 | list_del(&tid->list); | |
2136 | tid->sched = false; | |
b5aa9bf9 | 2137 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2138 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
f078f209 | 2139 | tid->addba_exchangeattempts = 0; |
a37c2c79 | 2140 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2141 | } |
2142 | } | |
2143 | ||
b5aa9bf9 | 2144 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2145 | } |
2146 | } | |
2147 | } |