Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include "core.h" |
18 | ||
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
e8324357 S |
58 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |
62 | struct list_head *bf_q, | |
63 | int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
c4288390 | 67 | |
e8324357 S |
68 | /*********************/ |
69 | /* Aggregation logic */ | |
70 | /*********************/ | |
f078f209 | 71 | |
a37c2c79 | 72 | static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
f078f209 LR |
73 | { |
74 | struct ath_atx_tid *tid; | |
75 | tid = ATH_AN_2_TID(an, tidno); | |
76 | ||
a37c2c79 S |
77 | if (tid->state & AGGR_ADDBA_COMPLETE || |
78 | tid->state & AGGR_ADDBA_PROGRESS) | |
f078f209 LR |
79 | return 1; |
80 | else | |
81 | return 0; | |
82 | } | |
83 | ||
e8324357 | 84 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 85 | { |
e8324357 | 86 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 87 | |
e8324357 S |
88 | if (tid->paused) |
89 | return; | |
ff37e337 | 90 | |
e8324357 S |
91 | if (tid->sched) |
92 | return; | |
ff37e337 | 93 | |
e8324357 S |
94 | tid->sched = true; |
95 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 96 | |
e8324357 S |
97 | if (ac->sched) |
98 | return; | |
f078f209 | 99 | |
e8324357 S |
100 | ac->sched = true; |
101 | list_add_tail(&ac->list, &txq->axq_acq); | |
102 | } | |
f078f209 | 103 | |
e8324357 S |
104 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
105 | { | |
106 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 107 | |
e8324357 S |
108 | spin_lock_bh(&txq->axq_lock); |
109 | tid->paused++; | |
110 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
111 | } |
112 | ||
e8324357 | 113 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 114 | { |
e8324357 | 115 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 116 | |
e8324357 S |
117 | ASSERT(tid->paused > 0); |
118 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 119 | |
e8324357 | 120 | tid->paused--; |
f078f209 | 121 | |
e8324357 S |
122 | if (tid->paused > 0) |
123 | goto unlock; | |
f078f209 | 124 | |
e8324357 S |
125 | if (list_empty(&tid->buf_q)) |
126 | goto unlock; | |
f078f209 | 127 | |
e8324357 S |
128 | ath_tx_queue_tid(txq, tid); |
129 | ath_txq_schedule(sc, txq); | |
130 | unlock: | |
131 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 132 | } |
f078f209 | 133 | |
e8324357 | 134 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 135 | { |
e8324357 S |
136 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
137 | struct ath_buf *bf; | |
138 | struct list_head bf_head; | |
139 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 140 | |
e8324357 S |
141 | ASSERT(tid->paused > 0); |
142 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 143 | |
e8324357 | 144 | tid->paused--; |
f078f209 | 145 | |
e8324357 S |
146 | if (tid->paused > 0) { |
147 | spin_unlock_bh(&txq->axq_lock); | |
148 | return; | |
149 | } | |
f078f209 | 150 | |
e8324357 S |
151 | while (!list_empty(&tid->buf_q)) { |
152 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
153 | ASSERT(!bf_isretried(bf)); | |
d43f3015 | 154 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 155 | ath_tx_send_normal(sc, txq, tid, &bf_head); |
528f0c6b | 156 | } |
f078f209 | 157 | |
e8324357 | 158 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 159 | } |
f078f209 | 160 | |
e8324357 S |
161 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
162 | int seqno) | |
528f0c6b | 163 | { |
e8324357 | 164 | int index, cindex; |
f078f209 | 165 | |
e8324357 S |
166 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
167 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 168 | |
e8324357 | 169 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 170 | |
e8324357 S |
171 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
172 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
173 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
174 | } | |
528f0c6b | 175 | } |
f078f209 | 176 | |
e8324357 S |
177 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
178 | struct ath_buf *bf) | |
528f0c6b | 179 | { |
e8324357 | 180 | int index, cindex; |
528f0c6b | 181 | |
e8324357 S |
182 | if (bf_isretried(bf)) |
183 | return; | |
528f0c6b | 184 | |
e8324357 S |
185 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
186 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 187 | |
e8324357 S |
188 | ASSERT(tid->tx_buf[cindex] == NULL); |
189 | tid->tx_buf[cindex] = bf; | |
f078f209 | 190 | |
e8324357 S |
191 | if (index >= ((tid->baw_tail - tid->baw_head) & |
192 | (ATH_TID_MAX_BUFS - 1))) { | |
193 | tid->baw_tail = cindex; | |
194 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 195 | } |
f078f209 LR |
196 | } |
197 | ||
198 | /* | |
e8324357 S |
199 | * TODO: For frame(s) that are in the retry state, we will reuse the |
200 | * sequence number(s) without setting the retry bit. The | |
201 | * alternative is to give up on these and BAR the receiver's window | |
202 | * forward. | |
f078f209 | 203 | */ |
e8324357 S |
204 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
205 | struct ath_atx_tid *tid) | |
f078f209 | 206 | |
f078f209 | 207 | { |
e8324357 S |
208 | struct ath_buf *bf; |
209 | struct list_head bf_head; | |
210 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 211 | |
e8324357 S |
212 | for (;;) { |
213 | if (list_empty(&tid->buf_q)) | |
214 | break; | |
f078f209 | 215 | |
d43f3015 S |
216 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
217 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 218 | |
e8324357 S |
219 | if (bf_isretried(bf)) |
220 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 221 | |
e8324357 S |
222 | spin_unlock(&txq->axq_lock); |
223 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
224 | spin_lock(&txq->axq_lock); | |
225 | } | |
f078f209 | 226 | |
e8324357 S |
227 | tid->seq_next = tid->seq_start; |
228 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
229 | } |
230 | ||
e8324357 | 231 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) |
f078f209 | 232 | { |
e8324357 S |
233 | struct sk_buff *skb; |
234 | struct ieee80211_hdr *hdr; | |
f078f209 | 235 | |
e8324357 S |
236 | bf->bf_state.bf_type |= BUF_RETRY; |
237 | bf->bf_retries++; | |
f078f209 | 238 | |
e8324357 S |
239 | skb = bf->bf_mpdu; |
240 | hdr = (struct ieee80211_hdr *)skb->data; | |
241 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
242 | } |
243 | ||
d43f3015 S |
244 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
245 | { | |
246 | struct ath_buf *tbf; | |
247 | ||
248 | spin_lock_bh(&sc->tx.txbuflock); | |
249 | ASSERT(!list_empty((&sc->tx.txbuf))); | |
250 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
251 | list_del(&tbf->list); | |
252 | spin_unlock_bh(&sc->tx.txbuflock); | |
253 | ||
254 | ATH_TXBUF_RESET(tbf); | |
255 | ||
256 | tbf->bf_mpdu = bf->bf_mpdu; | |
257 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
258 | *(tbf->bf_desc) = *(bf->bf_desc); | |
259 | tbf->bf_state = bf->bf_state; | |
260 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
261 | ||
262 | return tbf; | |
263 | } | |
264 | ||
265 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
266 | struct ath_buf *bf, struct list_head *bf_q, | |
267 | int txok) | |
f078f209 | 268 | { |
e8324357 S |
269 | struct ath_node *an = NULL; |
270 | struct sk_buff *skb; | |
271 | struct ieee80211_tx_info *tx_info; | |
272 | struct ath_atx_tid *tid = NULL; | |
d43f3015 | 273 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 274 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 275 | struct list_head bf_head, bf_pending; |
f078f209 LR |
276 | u16 seq_st = 0; |
277 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
e8324357 | 278 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0; |
f078f209 | 279 | |
e8324357 S |
280 | skb = (struct sk_buff *)bf->bf_mpdu; |
281 | tx_info = IEEE80211_SKB_CB(skb); | |
f078f209 | 282 | |
e8324357 S |
283 | if (tx_info->control.sta) { |
284 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
285 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
f078f209 LR |
286 | } |
287 | ||
e8324357 | 288 | isaggr = bf_isaggr(bf); |
d43f3015 | 289 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 290 | |
d43f3015 S |
291 | if (isaggr && txok) { |
292 | if (ATH_DS_TX_BA(ds)) { | |
293 | seq_st = ATH_DS_BA_SEQ(ds); | |
294 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
295 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 296 | } else { |
d43f3015 S |
297 | /* |
298 | * AR5416 can become deaf/mute when BA | |
299 | * issue happens. Chip needs to be reset. | |
300 | * But AP code may have sychronization issues | |
301 | * when perform internal reset in this routine. | |
302 | * Only enable reset in STA mode for now. | |
303 | */ | |
304 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) | |
305 | needreset = 1; | |
e8324357 | 306 | } |
f078f209 LR |
307 | } |
308 | ||
e8324357 S |
309 | INIT_LIST_HEAD(&bf_pending); |
310 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 311 | |
e8324357 S |
312 | while (bf) { |
313 | txfail = txpending = 0; | |
314 | bf_next = bf->bf_next; | |
f078f209 | 315 | |
e8324357 S |
316 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
317 | /* transmit completion, subframe is | |
318 | * acked by block ack */ | |
319 | } else if (!isaggr && txok) { | |
320 | /* transmit completion */ | |
321 | } else { | |
e8324357 S |
322 | if (!(tid->state & AGGR_CLEANUP) && |
323 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
324 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
325 | ath_tx_set_retry(sc, bf); | |
326 | txpending = 1; | |
327 | } else { | |
328 | bf->bf_state.bf_type |= BUF_XRETRY; | |
329 | txfail = 1; | |
330 | sendbar = 1; | |
331 | } | |
332 | } else { | |
333 | /* | |
334 | * cleanup in progress, just fail | |
335 | * the un-acked sub-frames | |
336 | */ | |
337 | txfail = 1; | |
338 | } | |
339 | } | |
f078f209 | 340 | |
e8324357 | 341 | if (bf_next == NULL) { |
d43f3015 | 342 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
343 | } else { |
344 | ASSERT(!list_empty(bf_q)); | |
d43f3015 | 345 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 346 | } |
f078f209 | 347 | |
e8324357 S |
348 | if (!txpending) { |
349 | /* | |
350 | * complete the acked-ones/xretried ones; update | |
351 | * block-ack window | |
352 | */ | |
353 | spin_lock_bh(&txq->axq_lock); | |
354 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
355 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 356 | |
e8324357 S |
357 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); |
358 | } else { | |
d43f3015 | 359 | /* retry the un-acked ones */ |
e8324357 S |
360 | if (bf->bf_next == NULL && |
361 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | |
362 | struct ath_buf *tbf; | |
f078f209 | 363 | |
d43f3015 S |
364 | tbf = ath_clone_txbuf(sc, bf_last); |
365 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); | |
e8324357 S |
366 | list_add_tail(&tbf->list, &bf_head); |
367 | } else { | |
368 | /* | |
369 | * Clear descriptor status words for | |
370 | * software retry | |
371 | */ | |
d43f3015 | 372 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
373 | } |
374 | ||
375 | /* | |
376 | * Put this buffer to the temporary pending | |
377 | * queue to retain ordering | |
378 | */ | |
379 | list_splice_tail_init(&bf_head, &bf_pending); | |
380 | } | |
381 | ||
382 | bf = bf_next; | |
f078f209 | 383 | } |
f078f209 | 384 | |
e8324357 | 385 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
386 | if (tid->baw_head == tid->baw_tail) { |
387 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
388 | tid->addba_exchangeattempts = 0; | |
e8324357 | 389 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 390 | |
e8324357 S |
391 | /* send buffered frames as singles */ |
392 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 393 | } |
e8324357 S |
394 | return; |
395 | } | |
f078f209 | 396 | |
d43f3015 | 397 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
398 | if (!list_empty(&bf_pending)) { |
399 | spin_lock_bh(&txq->axq_lock); | |
400 | list_splice(&bf_pending, &tid->buf_q); | |
401 | ath_tx_queue_tid(txq, tid); | |
402 | spin_unlock_bh(&txq->axq_lock); | |
403 | } | |
102e0572 | 404 | |
e8324357 S |
405 | if (needreset) |
406 | ath_reset(sc, false); | |
e8324357 | 407 | } |
f078f209 | 408 | |
e8324357 S |
409 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
410 | struct ath_atx_tid *tid) | |
f078f209 | 411 | { |
e8324357 | 412 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
413 | struct sk_buff *skb; |
414 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 415 | struct ieee80211_tx_rate *rates; |
e8324357 | 416 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 417 | u32 max_4ms_framelen, frmlen; |
e8324357 S |
418 | u16 aggr_limit, legacy = 0, maxampdu; |
419 | int i; | |
528f0c6b S |
420 | |
421 | skb = (struct sk_buff *)bf->bf_mpdu; | |
422 | tx_info = IEEE80211_SKB_CB(skb); | |
e63835b0 | 423 | rates = tx_info->control.rates; |
d43f3015 | 424 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 425 | |
e8324357 S |
426 | /* |
427 | * Find the lowest frame length among the rate series that will have a | |
428 | * 4ms transmit duration. | |
429 | * TODO - TXOP limit needs to be considered. | |
430 | */ | |
431 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 432 | |
e8324357 S |
433 | for (i = 0; i < 4; i++) { |
434 | if (rates[i].count) { | |
435 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
436 | legacy = 1; | |
437 | break; | |
438 | } | |
439 | ||
d43f3015 S |
440 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
441 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
442 | } |
443 | } | |
e63835b0 | 444 | |
f078f209 | 445 | /* |
e8324357 S |
446 | * limit aggregate size by the minimum rate if rate selected is |
447 | * not a probe rate, if rate selected is a probe rate then | |
448 | * avoid aggregation of this packet. | |
f078f209 | 449 | */ |
e8324357 S |
450 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
451 | return 0; | |
f078f209 | 452 | |
d43f3015 | 453 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT); |
f078f209 | 454 | |
e8324357 S |
455 | /* |
456 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
457 | * The IE, however can hold upto 65536, which shows up here | |
458 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 459 | */ |
e8324357 S |
460 | maxampdu = tid->an->maxampdu; |
461 | if (maxampdu) | |
462 | aggr_limit = min(aggr_limit, maxampdu); | |
f078f209 | 463 | |
e8324357 S |
464 | return aggr_limit; |
465 | } | |
f078f209 | 466 | |
e8324357 | 467 | /* |
d43f3015 | 468 | * Returns the number of delimiters to be added to |
e8324357 | 469 | * meet the minimum required mpdudensity. |
d43f3015 | 470 | * caller should make sure that the rate is HT rate . |
e8324357 S |
471 | */ |
472 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
473 | struct ath_buf *bf, u16 frmlen) | |
474 | { | |
475 | struct ath_rate_table *rt = sc->cur_rate_table; | |
476 | struct sk_buff *skb = bf->bf_mpdu; | |
477 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
478 | u32 nsymbits, nsymbols, mpdudensity; | |
479 | u16 minlen; | |
480 | u8 rc, flags, rix; | |
481 | int width, half_gi, ndelim, mindelim; | |
482 | ||
483 | /* Select standard number of delimiters based on frame length alone */ | |
484 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
485 | |
486 | /* | |
e8324357 S |
487 | * If encryption enabled, hardware requires some more padding between |
488 | * subframes. | |
489 | * TODO - this could be improved to be dependent on the rate. | |
490 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 491 | */ |
e8324357 S |
492 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
493 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 494 | |
e8324357 S |
495 | /* |
496 | * Convert desired mpdu density from microeconds to bytes based | |
497 | * on highest rate in rate series (i.e. first rate) to determine | |
498 | * required minimum length for subframe. Take into account | |
499 | * whether high rate is 20 or 40Mhz and half or full GI. | |
500 | */ | |
501 | mpdudensity = tid->an->mpdudensity; | |
f078f209 | 502 | |
e8324357 S |
503 | /* |
504 | * If there is no mpdu density restriction, no further calculation | |
505 | * is needed. | |
506 | */ | |
507 | if (mpdudensity == 0) | |
508 | return ndelim; | |
f078f209 | 509 | |
e8324357 S |
510 | rix = tx_info->control.rates[0].idx; |
511 | flags = tx_info->control.rates[0].flags; | |
512 | rc = rt->info[rix].ratecode; | |
513 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
514 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 515 | |
e8324357 S |
516 | if (half_gi) |
517 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
518 | else | |
519 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
f078f209 | 520 | |
e8324357 S |
521 | if (nsymbols == 0) |
522 | nsymbols = 1; | |
f078f209 | 523 | |
e8324357 S |
524 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
525 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 526 | |
e8324357 | 527 | if (frmlen < minlen) { |
e8324357 S |
528 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
529 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
530 | } |
531 | ||
e8324357 | 532 | return ndelim; |
f078f209 LR |
533 | } |
534 | ||
e8324357 | 535 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
d43f3015 S |
536 | struct ath_atx_tid *tid, |
537 | struct list_head *bf_q) | |
f078f209 | 538 | { |
e8324357 | 539 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
540 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
541 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
542 | u16 aggr_limit = 0, al = 0, bpad = 0, |
543 | al_delta, h_baw = tid->baw_size / 2; | |
544 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 545 | |
e8324357 | 546 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 547 | |
e8324357 S |
548 | do { |
549 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 550 | |
d43f3015 | 551 | /* do not step over block-ack window */ |
e8324357 S |
552 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
553 | status = ATH_AGGR_BAW_CLOSED; | |
554 | break; | |
555 | } | |
f078f209 | 556 | |
e8324357 S |
557 | if (!rl) { |
558 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
559 | rl = 1; | |
560 | } | |
f078f209 | 561 | |
d43f3015 | 562 | /* do not exceed aggregation limit */ |
e8324357 | 563 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 564 | |
d43f3015 S |
565 | if (nframes && |
566 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
567 | status = ATH_AGGR_LIMITED; |
568 | break; | |
569 | } | |
f078f209 | 570 | |
d43f3015 S |
571 | /* do not exceed subframe limit */ |
572 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
573 | status = ATH_AGGR_LIMITED; |
574 | break; | |
575 | } | |
d43f3015 | 576 | nframes++; |
f078f209 | 577 | |
d43f3015 | 578 | /* add padding for previous frame to aggregation length */ |
e8324357 | 579 | al += bpad + al_delta; |
f078f209 | 580 | |
e8324357 S |
581 | /* |
582 | * Get the delimiters needed to meet the MPDU | |
583 | * density for this node. | |
584 | */ | |
585 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 586 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 587 | |
e8324357 | 588 | bf->bf_next = NULL; |
d43f3015 | 589 | bf->bf_desc->ds_link = 0; |
f078f209 | 590 | |
d43f3015 | 591 | /* link buffers of this frame to the aggregate */ |
e8324357 | 592 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
593 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
594 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
595 | if (bf_prev) { |
596 | bf_prev->bf_next = bf; | |
d43f3015 | 597 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
598 | } |
599 | bf_prev = bf; | |
e8324357 | 600 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 601 | |
e8324357 S |
602 | bf_first->bf_al = al; |
603 | bf_first->bf_nframes = nframes; | |
d43f3015 | 604 | |
e8324357 S |
605 | return status; |
606 | #undef PADBYTES | |
607 | } | |
f078f209 | 608 | |
e8324357 S |
609 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
610 | struct ath_atx_tid *tid) | |
611 | { | |
d43f3015 | 612 | struct ath_buf *bf; |
e8324357 S |
613 | enum ATH_AGGR_STATUS status; |
614 | struct list_head bf_q; | |
f078f209 | 615 | |
e8324357 S |
616 | do { |
617 | if (list_empty(&tid->buf_q)) | |
618 | return; | |
f078f209 | 619 | |
e8324357 S |
620 | INIT_LIST_HEAD(&bf_q); |
621 | ||
d43f3015 | 622 | status = ath_tx_form_aggr(sc, tid, &bf_q); |
f078f209 | 623 | |
f078f209 | 624 | /* |
d43f3015 S |
625 | * no frames picked up to be aggregated; |
626 | * block-ack window is not open. | |
f078f209 | 627 | */ |
e8324357 S |
628 | if (list_empty(&bf_q)) |
629 | break; | |
f078f209 | 630 | |
e8324357 | 631 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 632 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 633 | |
d43f3015 | 634 | /* if only one frame, send as non-aggregate */ |
e8324357 | 635 | if (bf->bf_nframes == 1) { |
e8324357 | 636 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 637 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
638 | ath_buf_set_rate(sc, bf); |
639 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
640 | continue; | |
641 | } | |
f078f209 | 642 | |
d43f3015 | 643 | /* setup first desc of aggregate */ |
e8324357 S |
644 | bf->bf_state.bf_type |= BUF_AGGR; |
645 | ath_buf_set_rate(sc, bf); | |
646 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 647 | |
d43f3015 S |
648 | /* anchor last desc of aggregate */ |
649 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 650 | |
e8324357 | 651 | txq->axq_aggr_depth++; |
e8324357 | 652 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
f078f209 | 653 | |
e8324357 S |
654 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
655 | status != ATH_AGGR_BAW_CLOSED); | |
656 | } | |
657 | ||
658 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
659 | u16 tid, u16 *ssn) | |
660 | { | |
661 | struct ath_atx_tid *txtid; | |
662 | struct ath_node *an; | |
663 | ||
664 | an = (struct ath_node *)sta->drv_priv; | |
665 | ||
666 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
667 | txtid = ATH_AN_2_TID(an, tid); | |
668 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
669 | ath_tx_pause_tid(sc, txtid); | |
f078f209 LR |
670 | } |
671 | ||
e8324357 S |
672 | return 0; |
673 | } | |
f078f209 | 674 | |
e8324357 S |
675 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
676 | { | |
677 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
678 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
679 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
680 | struct ath_buf *bf; | |
681 | struct list_head bf_head; | |
682 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 683 | |
e8324357 S |
684 | if (txtid->state & AGGR_CLEANUP) |
685 | return 0; | |
f078f209 | 686 | |
e8324357 S |
687 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
688 | txtid->addba_exchangeattempts = 0; | |
689 | return 0; | |
690 | } | |
f078f209 | 691 | |
e8324357 S |
692 | ath_tx_pause_tid(sc, txtid); |
693 | ||
694 | /* drop all software retried frames and mark this TID */ | |
695 | spin_lock_bh(&txq->axq_lock); | |
696 | while (!list_empty(&txtid->buf_q)) { | |
697 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
698 | if (!bf_isretried(bf)) { | |
699 | /* | |
700 | * NB: it's based on the assumption that | |
701 | * software retried frame will always stay | |
702 | * at the head of software queue. | |
703 | */ | |
704 | break; | |
705 | } | |
d43f3015 | 706 | list_move_tail(&bf->list, &bf_head); |
e8324357 S |
707 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
708 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 | 709 | } |
d43f3015 | 710 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 711 | |
e8324357 | 712 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
713 | txtid->state |= AGGR_CLEANUP; |
714 | } else { | |
715 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
716 | txtid->addba_exchangeattempts = 0; | |
e8324357 | 717 | ath_tx_flush_tid(sc, txtid); |
f078f209 LR |
718 | } |
719 | ||
e8324357 S |
720 | return 0; |
721 | } | |
f078f209 | 722 | |
e8324357 S |
723 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
724 | { | |
725 | struct ath_atx_tid *txtid; | |
726 | struct ath_node *an; | |
727 | ||
728 | an = (struct ath_node *)sta->drv_priv; | |
729 | ||
730 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
731 | txtid = ATH_AN_2_TID(an, tid); | |
732 | txtid->baw_size = | |
733 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
734 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
735 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
736 | ath_tx_resume_tid(sc, txtid); | |
737 | } | |
f078f209 LR |
738 | } |
739 | ||
e8324357 | 740 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 741 | { |
e8324357 | 742 | struct ath_atx_tid *txtid; |
c4288390 | 743 | |
e8324357 S |
744 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
745 | return false; | |
c4288390 | 746 | |
e8324357 S |
747 | txtid = ATH_AN_2_TID(an, tidno); |
748 | ||
749 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { | |
750 | if (!(txtid->state & AGGR_ADDBA_PROGRESS) && | |
751 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
752 | txtid->addba_exchangeattempts++; | |
753 | return true; | |
c4288390 S |
754 | } |
755 | } | |
e8324357 S |
756 | |
757 | return false; | |
c4288390 S |
758 | } |
759 | ||
e8324357 S |
760 | /********************/ |
761 | /* Queue Management */ | |
762 | /********************/ | |
f078f209 | 763 | |
e8324357 S |
764 | static u32 ath_txq_depth(struct ath_softc *sc, int qnum) |
765 | { | |
766 | return sc->tx.txq[qnum].axq_depth; | |
767 | } | |
768 | ||
e8324357 S |
769 | static void ath_get_beaconconfig(struct ath_softc *sc, int if_id, |
770 | struct ath_beacon_config *conf) | |
f078f209 | 771 | { |
e8324357 | 772 | struct ieee80211_hw *hw = sc->hw; |
f078f209 | 773 | |
e8324357 | 774 | /* fill in beacon config data */ |
f078f209 | 775 | |
e8324357 S |
776 | conf->beacon_interval = hw->conf.beacon_int; |
777 | conf->listen_interval = 100; | |
778 | conf->dtim_count = 1; | |
779 | conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval; | |
780 | } | |
f078f209 | 781 | |
e8324357 S |
782 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
783 | struct ath_txq *txq) | |
f078f209 | 784 | { |
e8324357 S |
785 | struct ath_atx_ac *ac, *ac_tmp; |
786 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 787 | |
e8324357 S |
788 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
789 | list_del(&ac->list); | |
790 | ac->sched = false; | |
791 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
792 | list_del(&tid->list); | |
793 | tid->sched = false; | |
794 | ath_tid_drain(sc, txq, tid); | |
795 | } | |
f078f209 LR |
796 | } |
797 | } | |
798 | ||
e8324357 | 799 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 800 | { |
e8324357 S |
801 | struct ath_hal *ah = sc->sc_ah; |
802 | struct ath9k_tx_queue_info qi; | |
803 | int qnum; | |
f078f209 | 804 | |
e8324357 S |
805 | memset(&qi, 0, sizeof(qi)); |
806 | qi.tqi_subtype = subtype; | |
807 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
808 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
809 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
810 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
811 | |
812 | /* | |
e8324357 S |
813 | * Enable interrupts only for EOL and DESC conditions. |
814 | * We mark tx descriptors to receive a DESC interrupt | |
815 | * when a tx queue gets deep; otherwise waiting for the | |
816 | * EOL to reap descriptors. Note that this is done to | |
817 | * reduce interrupt load and this only defers reaping | |
818 | * descriptors, never transmitting frames. Aside from | |
819 | * reducing interrupts this also permits more concurrency. | |
820 | * The only potential downside is if the tx queue backs | |
821 | * up in which case the top half of the kernel may backup | |
822 | * due to a lack of tx descriptors. | |
823 | * | |
824 | * The UAPSD queue is an exception, since we take a desc- | |
825 | * based intr on the EOSP frames. | |
f078f209 | 826 | */ |
e8324357 S |
827 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
828 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
829 | else | |
830 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
831 | TXQ_FLAG_TXDESCINT_ENABLE; | |
832 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
833 | if (qnum == -1) { | |
f078f209 | 834 | /* |
e8324357 S |
835 | * NB: don't print a message, this happens |
836 | * normally on parts with too few tx queues | |
f078f209 | 837 | */ |
e8324357 | 838 | return NULL; |
f078f209 | 839 | } |
e8324357 S |
840 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
841 | DPRINTF(sc, ATH_DBG_FATAL, | |
842 | "qnum %u out of range, max %u!\n", | |
843 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
844 | ath9k_hw_releasetxqueue(ah, qnum); | |
845 | return NULL; | |
846 | } | |
847 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
848 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 849 | |
e8324357 S |
850 | txq->axq_qnum = qnum; |
851 | txq->axq_link = NULL; | |
852 | INIT_LIST_HEAD(&txq->axq_q); | |
853 | INIT_LIST_HEAD(&txq->axq_acq); | |
854 | spin_lock_init(&txq->axq_lock); | |
855 | txq->axq_depth = 0; | |
856 | txq->axq_aggr_depth = 0; | |
857 | txq->axq_totalqueued = 0; | |
858 | txq->axq_linkbuf = NULL; | |
859 | sc->tx.txqsetup |= 1<<qnum; | |
860 | } | |
861 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
862 | } |
863 | ||
e8324357 | 864 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 865 | { |
e8324357 | 866 | int qnum; |
f078f209 | 867 | |
e8324357 S |
868 | switch (qtype) { |
869 | case ATH9K_TX_QUEUE_DATA: | |
870 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
871 | DPRINTF(sc, ATH_DBG_FATAL, | |
872 | "HAL AC %u out of range, max %zu!\n", | |
873 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
874 | return -1; | |
875 | } | |
876 | qnum = sc->tx.hwq_map[haltype]; | |
877 | break; | |
878 | case ATH9K_TX_QUEUE_BEACON: | |
879 | qnum = sc->beacon.beaconq; | |
880 | break; | |
881 | case ATH9K_TX_QUEUE_CAB: | |
882 | qnum = sc->beacon.cabq->axq_qnum; | |
883 | break; | |
884 | default: | |
885 | qnum = -1; | |
886 | } | |
887 | return qnum; | |
888 | } | |
f078f209 | 889 | |
e8324357 S |
890 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
891 | { | |
892 | struct ath_txq *txq = NULL; | |
893 | int qnum; | |
f078f209 | 894 | |
e8324357 S |
895 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
896 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 897 | |
e8324357 S |
898 | spin_lock_bh(&txq->axq_lock); |
899 | ||
900 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
901 | DPRINTF(sc, ATH_DBG_FATAL, | |
902 | "TX queue: %d is full, depth: %d\n", | |
903 | qnum, txq->axq_depth); | |
904 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
905 | txq->stopped = 1; | |
906 | spin_unlock_bh(&txq->axq_lock); | |
907 | return NULL; | |
f078f209 LR |
908 | } |
909 | ||
e8324357 S |
910 | spin_unlock_bh(&txq->axq_lock); |
911 | ||
912 | return txq; | |
913 | } | |
914 | ||
915 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
916 | struct ath9k_tx_queue_info *qinfo) | |
917 | { | |
918 | struct ath_hal *ah = sc->sc_ah; | |
919 | int error = 0; | |
920 | struct ath9k_tx_queue_info qi; | |
921 | ||
922 | if (qnum == sc->beacon.beaconq) { | |
923 | /* | |
924 | * XXX: for beacon queue, we just save the parameter. | |
925 | * It will be picked up by ath_beaconq_config when | |
926 | * it's necessary. | |
927 | */ | |
928 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 929 | return 0; |
e8324357 | 930 | } |
f078f209 | 931 | |
e8324357 S |
932 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
933 | ||
934 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
935 | qi.tqi_aifs = qinfo->tqi_aifs; | |
936 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
937 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
938 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
939 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
940 | ||
941 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
942 | DPRINTF(sc, ATH_DBG_FATAL, | |
943 | "Unable to update hardware queue %u!\n", qnum); | |
944 | error = -EIO; | |
945 | } else { | |
946 | ath9k_hw_resettxqueue(ah, qnum); | |
947 | } | |
948 | ||
949 | return error; | |
950 | } | |
951 | ||
952 | int ath_cabq_update(struct ath_softc *sc) | |
953 | { | |
954 | struct ath9k_tx_queue_info qi; | |
955 | int qnum = sc->beacon.cabq->axq_qnum; | |
956 | struct ath_beacon_config conf; | |
f078f209 | 957 | |
e8324357 | 958 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 959 | /* |
e8324357 | 960 | * Ensure the readytime % is within the bounds. |
f078f209 | 961 | */ |
e8324357 S |
962 | if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
963 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
964 | else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
965 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 966 | |
e8324357 S |
967 | ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf); |
968 | qi.tqi_readyTime = | |
969 | (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100; | |
970 | ath_txq_update(sc, qnum, &qi); | |
971 | ||
972 | return 0; | |
f078f209 LR |
973 | } |
974 | ||
043a0405 S |
975 | /* |
976 | * Drain a given TX queue (could be Beacon or Data) | |
977 | * | |
978 | * This assumes output has been stopped and | |
979 | * we do not need to block ath_tx_tasklet. | |
980 | */ | |
981 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 982 | { |
e8324357 S |
983 | struct ath_buf *bf, *lastbf; |
984 | struct list_head bf_head; | |
f078f209 | 985 | |
e8324357 | 986 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 987 | |
e8324357 S |
988 | for (;;) { |
989 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 990 | |
e8324357 S |
991 | if (list_empty(&txq->axq_q)) { |
992 | txq->axq_link = NULL; | |
993 | txq->axq_linkbuf = NULL; | |
994 | spin_unlock_bh(&txq->axq_lock); | |
995 | break; | |
996 | } | |
f078f209 | 997 | |
e8324357 | 998 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 999 | |
e8324357 S |
1000 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
1001 | list_del(&bf->list); | |
1002 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1003 | |
e8324357 S |
1004 | spin_lock_bh(&sc->tx.txbuflock); |
1005 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1006 | spin_unlock_bh(&sc->tx.txbuflock); | |
1007 | continue; | |
1008 | } | |
f078f209 | 1009 | |
e8324357 S |
1010 | lastbf = bf->bf_lastbf; |
1011 | if (!retry_tx) | |
1012 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1013 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1014 | |
e8324357 S |
1015 | /* remove ath_buf's of the same mpdu from txq */ |
1016 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1017 | txq->axq_depth--; | |
f078f209 | 1018 | |
e8324357 S |
1019 | spin_unlock_bh(&txq->axq_lock); |
1020 | ||
1021 | if (bf_isampdu(bf)) | |
d43f3015 | 1022 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 S |
1023 | else |
1024 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
1025 | } |
1026 | ||
e8324357 S |
1027 | /* flush any pending frames if aggregation is enabled */ |
1028 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1029 | if (!retry_tx) { | |
1030 | spin_lock_bh(&txq->axq_lock); | |
1031 | ath_txq_drain_pending_buffers(sc, txq); | |
1032 | spin_unlock_bh(&txq->axq_lock); | |
1033 | } | |
1034 | } | |
f078f209 LR |
1035 | } |
1036 | ||
043a0405 | 1037 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1038 | { |
043a0405 S |
1039 | struct ath_hal *ah = sc->sc_ah; |
1040 | struct ath_txq *txq; | |
1041 | int i, npend = 0; | |
1042 | ||
1043 | if (sc->sc_flags & SC_OP_INVALID) | |
1044 | return; | |
1045 | ||
1046 | /* Stop beacon queue */ | |
1047 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1048 | ||
1049 | /* Stop data queues */ | |
1050 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1051 | if (ATH_TXQ_SETUP(sc, i)) { | |
1052 | txq = &sc->tx.txq[i]; | |
1053 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1054 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | if (npend) { | |
1059 | int r; | |
1060 | ||
1061 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); | |
1062 | ||
1063 | spin_lock_bh(&sc->sc_resetlock); | |
1064 | r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); | |
1065 | if (r) | |
1066 | DPRINTF(sc, ATH_DBG_FATAL, | |
1067 | "Unable to reset hardware; reset status %u\n", | |
1068 | r); | |
1069 | spin_unlock_bh(&sc->sc_resetlock); | |
1070 | } | |
1071 | ||
1072 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1073 | if (ATH_TXQ_SETUP(sc, i)) | |
1074 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1075 | } | |
e8324357 | 1076 | } |
f078f209 | 1077 | |
043a0405 | 1078 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1079 | { |
043a0405 S |
1080 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1081 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1082 | } |
f078f209 | 1083 | |
e8324357 S |
1084 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1085 | { | |
1086 | struct ath_atx_ac *ac; | |
1087 | struct ath_atx_tid *tid; | |
f078f209 | 1088 | |
e8324357 S |
1089 | if (list_empty(&txq->axq_acq)) |
1090 | return; | |
f078f209 | 1091 | |
e8324357 S |
1092 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1093 | list_del(&ac->list); | |
1094 | ac->sched = false; | |
f078f209 | 1095 | |
e8324357 S |
1096 | do { |
1097 | if (list_empty(&ac->tid_q)) | |
1098 | return; | |
f078f209 | 1099 | |
e8324357 S |
1100 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1101 | list_del(&tid->list); | |
1102 | tid->sched = false; | |
f078f209 | 1103 | |
e8324357 S |
1104 | if (tid->paused) |
1105 | continue; | |
f078f209 | 1106 | |
e8324357 S |
1107 | if ((txq->axq_depth % 2) == 0) |
1108 | ath_tx_sched_aggr(sc, txq, tid); | |
f078f209 LR |
1109 | |
1110 | /* | |
e8324357 S |
1111 | * add tid to round-robin queue if more frames |
1112 | * are pending for the tid | |
f078f209 | 1113 | */ |
e8324357 S |
1114 | if (!list_empty(&tid->buf_q)) |
1115 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1116 | |
e8324357 S |
1117 | break; |
1118 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1119 | |
e8324357 S |
1120 | if (!list_empty(&ac->tid_q)) { |
1121 | if (!ac->sched) { | |
1122 | ac->sched = true; | |
1123 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1124 | } |
e8324357 S |
1125 | } |
1126 | } | |
f078f209 | 1127 | |
e8324357 S |
1128 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1129 | { | |
1130 | struct ath_txq *txq; | |
f078f209 | 1131 | |
e8324357 S |
1132 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1133 | DPRINTF(sc, ATH_DBG_FATAL, | |
1134 | "HAL AC %u out of range, max %zu!\n", | |
1135 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1136 | return 0; | |
1137 | } | |
1138 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1139 | if (txq != NULL) { | |
1140 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1141 | return 1; | |
1142 | } else | |
1143 | return 0; | |
f078f209 LR |
1144 | } |
1145 | ||
e8324357 S |
1146 | /***********/ |
1147 | /* TX, DMA */ | |
1148 | /***********/ | |
1149 | ||
f078f209 | 1150 | /* |
e8324357 S |
1151 | * Insert a chain of ath_buf (descriptors) on a txq and |
1152 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1153 | */ |
e8324357 S |
1154 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1155 | struct list_head *head) | |
f078f209 | 1156 | { |
e8324357 S |
1157 | struct ath_hal *ah = sc->sc_ah; |
1158 | struct ath_buf *bf; | |
f078f209 | 1159 | |
e8324357 S |
1160 | /* |
1161 | * Insert the frame on the outbound list and | |
1162 | * pass it on to the hardware. | |
1163 | */ | |
f078f209 | 1164 | |
e8324357 S |
1165 | if (list_empty(head)) |
1166 | return; | |
f078f209 | 1167 | |
e8324357 | 1168 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1169 | |
e8324357 S |
1170 | list_splice_tail_init(head, &txq->axq_q); |
1171 | txq->axq_depth++; | |
1172 | txq->axq_totalqueued++; | |
1173 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
f078f209 | 1174 | |
e8324357 S |
1175 | DPRINTF(sc, ATH_DBG_QUEUE, |
1176 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1177 | |
e8324357 S |
1178 | if (txq->axq_link == NULL) { |
1179 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1180 | DPRINTF(sc, ATH_DBG_XMIT, | |
1181 | "TXDP[%u] = %llx (%p)\n", | |
1182 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1183 | } else { | |
1184 | *txq->axq_link = bf->bf_daddr; | |
1185 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1186 | txq->axq_qnum, txq->axq_link, | |
1187 | ito64(bf->bf_daddr), bf->bf_desc); | |
1188 | } | |
1189 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1190 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1191 | } | |
f078f209 | 1192 | |
e8324357 S |
1193 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1194 | { | |
1195 | struct ath_buf *bf = NULL; | |
f078f209 | 1196 | |
e8324357 | 1197 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1198 | |
e8324357 S |
1199 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1200 | spin_unlock_bh(&sc->tx.txbuflock); | |
1201 | return NULL; | |
1202 | } | |
f078f209 | 1203 | |
e8324357 S |
1204 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1205 | list_del(&bf->list); | |
f078f209 | 1206 | |
e8324357 | 1207 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1208 | |
e8324357 | 1209 | return bf; |
f078f209 LR |
1210 | } |
1211 | ||
e8324357 S |
1212 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1213 | struct list_head *bf_head, | |
1214 | struct ath_tx_control *txctl) | |
f078f209 LR |
1215 | { |
1216 | struct ath_buf *bf; | |
f078f209 | 1217 | |
e8324357 S |
1218 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1219 | bf->bf_state.bf_type |= BUF_AMPDU; | |
f078f209 | 1220 | |
e8324357 S |
1221 | /* |
1222 | * Do not queue to h/w when any of the following conditions is true: | |
1223 | * - there are pending frames in software queue | |
1224 | * - the TID is currently paused for ADDBA/BAR request | |
1225 | * - seqno is not within block-ack window | |
1226 | * - h/w queue depth exceeds low water mark | |
1227 | */ | |
1228 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1229 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1230 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1231 | /* |
e8324357 S |
1232 | * Add this frame to software queue for scheduling later |
1233 | * for aggregation. | |
f078f209 | 1234 | */ |
d43f3015 | 1235 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1236 | ath_tx_queue_tid(txctl->txq, tid); |
1237 | return; | |
1238 | } | |
1239 | ||
1240 | /* Add sub-frame to BAW */ | |
1241 | ath_tx_addto_baw(sc, tid, bf); | |
1242 | ||
1243 | /* Queue to h/w without aggregation */ | |
1244 | bf->bf_nframes = 1; | |
d43f3015 | 1245 | bf->bf_lastbf = bf; |
e8324357 S |
1246 | ath_buf_set_rate(sc, bf); |
1247 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1248 | } |
1249 | ||
1250 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, | |
1251 | struct ath_atx_tid *tid, | |
1252 | struct list_head *bf_head) | |
1253 | { | |
1254 | struct ath_buf *bf; | |
1255 | ||
e8324357 S |
1256 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1257 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1258 | ||
1259 | /* update starting sequence number for subsequent ADDBA request */ | |
1260 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1261 | ||
1262 | bf->bf_nframes = 1; | |
d43f3015 | 1263 | bf->bf_lastbf = bf; |
e8324357 S |
1264 | ath_buf_set_rate(sc, bf); |
1265 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1266 | } | |
1267 | ||
1268 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) | |
1269 | { | |
1270 | struct ieee80211_hdr *hdr; | |
1271 | enum ath9k_pkt_type htype; | |
1272 | __le16 fc; | |
1273 | ||
1274 | hdr = (struct ieee80211_hdr *)skb->data; | |
1275 | fc = hdr->frame_control; | |
1276 | ||
1277 | if (ieee80211_is_beacon(fc)) | |
1278 | htype = ATH9K_PKT_TYPE_BEACON; | |
1279 | else if (ieee80211_is_probe_resp(fc)) | |
1280 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1281 | else if (ieee80211_is_atim(fc)) | |
1282 | htype = ATH9K_PKT_TYPE_ATIM; | |
1283 | else if (ieee80211_is_pspoll(fc)) | |
1284 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1285 | else | |
1286 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1287 | ||
1288 | return htype; | |
1289 | } | |
1290 | ||
1291 | static bool is_pae(struct sk_buff *skb) | |
1292 | { | |
1293 | struct ieee80211_hdr *hdr; | |
1294 | __le16 fc; | |
1295 | ||
1296 | hdr = (struct ieee80211_hdr *)skb->data; | |
1297 | fc = hdr->frame_control; | |
1298 | ||
1299 | if (ieee80211_is_data(fc)) { | |
1300 | if (ieee80211_is_nullfunc(fc) || | |
1301 | /* Port Access Entity (IEEE 802.1X) */ | |
1302 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1303 | return true; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | return false; | |
1308 | } | |
1309 | ||
1310 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1311 | { | |
1312 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1313 | ||
1314 | if (tx_info->control.hw_key) { | |
1315 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1316 | return ATH9K_KEY_TYPE_WEP; | |
1317 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1318 | return ATH9K_KEY_TYPE_TKIP; | |
1319 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1320 | return ATH9K_KEY_TYPE_AES; | |
1321 | } | |
1322 | ||
1323 | return ATH9K_KEY_TYPE_CLEAR; | |
1324 | } | |
1325 | ||
1326 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1327 | struct ath_buf *bf) | |
1328 | { | |
1329 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1330 | struct ieee80211_hdr *hdr; | |
1331 | struct ath_node *an; | |
1332 | struct ath_atx_tid *tid; | |
1333 | __le16 fc; | |
1334 | u8 *qc; | |
1335 | ||
1336 | if (!tx_info->control.sta) | |
1337 | return; | |
1338 | ||
1339 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1340 | hdr = (struct ieee80211_hdr *)skb->data; | |
1341 | fc = hdr->frame_control; | |
1342 | ||
1343 | if (ieee80211_is_data_qos(fc)) { | |
1344 | qc = ieee80211_get_qos_ctl(hdr); | |
1345 | bf->bf_tidno = qc[0] & 0xf; | |
1346 | } | |
1347 | ||
1348 | /* | |
1349 | * For HT capable stations, we save tidno for later use. | |
1350 | * We also override seqno set by upper layer with the one | |
1351 | * in tx aggregation state. | |
1352 | * | |
1353 | * If fragmentation is on, the sequence number is | |
1354 | * not overridden, since it has been | |
1355 | * incremented by the fragmentation routine. | |
1356 | * | |
1357 | * FIXME: check if the fragmentation threshold exceeds | |
1358 | * IEEE80211 max. | |
1359 | */ | |
1360 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1361 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1362 | IEEE80211_SEQ_SEQ_SHIFT); | |
1363 | bf->bf_seqno = tid->seq_next; | |
1364 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1365 | } | |
1366 | ||
1367 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1368 | struct ath_txq *txq) | |
1369 | { | |
1370 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1371 | int flags = 0; | |
1372 | ||
1373 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1374 | flags |= ATH9K_TXDESC_INTREQ; | |
1375 | ||
1376 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1377 | flags |= ATH9K_TXDESC_NOACK; | |
1378 | if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1379 | flags |= ATH9K_TXDESC_RTSENA; | |
1380 | ||
1381 | return flags; | |
1382 | } | |
1383 | ||
1384 | /* | |
1385 | * rix - rate index | |
1386 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1387 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1388 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1389 | */ | |
1390 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1391 | int width, int half_gi, bool shortPreamble) | |
1392 | { | |
1393 | struct ath_rate_table *rate_table = sc->cur_rate_table; | |
1394 | u32 nbits, nsymbits, duration, nsymbols; | |
1395 | u8 rc; | |
1396 | int streams, pktlen; | |
1397 | ||
1398 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1399 | rc = rate_table->info[rix].ratecode; | |
1400 | ||
1401 | /* for legacy rates, use old function to compute packet duration */ | |
1402 | if (!IS_HT_RATE(rc)) | |
1403 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1404 | rix, shortPreamble); | |
1405 | ||
1406 | /* find number of symbols: PLCP + data */ | |
1407 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1408 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1409 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1410 | ||
1411 | if (!half_gi) | |
1412 | duration = SYMBOL_TIME(nsymbols); | |
1413 | else | |
1414 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1415 | ||
1416 | /* addup duration for legacy/ht training and signal fields */ | |
1417 | streams = HT_RC_2_STREAMS(rc); | |
1418 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1419 | ||
1420 | return duration; | |
1421 | } | |
1422 | ||
1423 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1424 | { | |
1425 | struct ath_hal *ah = sc->sc_ah; | |
1426 | struct ath_rate_table *rt; | |
1427 | struct ath_desc *ds = bf->bf_desc; | |
1428 | struct ath_desc *lastds = bf->bf_lastbf->bf_desc; | |
1429 | struct ath9k_11n_rate_series series[4]; | |
1430 | struct sk_buff *skb; | |
1431 | struct ieee80211_tx_info *tx_info; | |
1432 | struct ieee80211_tx_rate *rates; | |
1433 | struct ieee80211_hdr *hdr; | |
1434 | struct ieee80211_hw *hw = sc->hw; | |
1435 | int i, flags, rtsctsena = 0, enable_g_protection = 0; | |
1436 | u32 ctsduration = 0; | |
1437 | u8 rix = 0, cix, ctsrate = 0; | |
1438 | __le16 fc; | |
1439 | ||
1440 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1441 | ||
1442 | skb = (struct sk_buff *)bf->bf_mpdu; | |
1443 | hdr = (struct ieee80211_hdr *)skb->data; | |
1444 | fc = hdr->frame_control; | |
1445 | tx_info = IEEE80211_SKB_CB(skb); | |
1446 | rates = tx_info->control.rates; | |
1447 | ||
1448 | if (ieee80211_has_morefrags(fc) || | |
1449 | (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) { | |
1450 | rates[1].count = rates[2].count = rates[3].count = 0; | |
1451 | rates[1].idx = rates[2].idx = rates[3].idx = 0; | |
1452 | rates[0].count = ATH_TXMAXTRY; | |
1453 | } | |
1454 | ||
1455 | /* get the cix for the lowest valid rix */ | |
1456 | rt = sc->cur_rate_table; | |
1457 | for (i = 3; i >= 0; i--) { | |
1458 | if (rates[i].count && (rates[i].idx >= 0)) { | |
1459 | rix = rates[i].idx; | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)); | |
1465 | cix = rt->info[rix].ctrl_rate; | |
1466 | ||
1467 | /* All protection frames are transmited at 2Mb/s for 802.11g, | |
1468 | * otherwise we transmit them at 1Mb/s */ | |
1469 | if (hw->conf.channel->band == IEEE80211_BAND_2GHZ && | |
1470 | !conf_is_ht(&hw->conf)) | |
1471 | enable_g_protection = 1; | |
1472 | ||
1473 | /* | |
1474 | * If 802.11g protection is enabled, determine whether to use RTS/CTS or | |
1475 | * just CTS. Note that this is only done for OFDM/HT unicast frames. | |
1476 | */ | |
1477 | if (sc->sc_protmode != PROT_M_NONE && !(bf->bf_flags & ATH9K_TXDESC_NOACK) | |
1478 | && (rt->info[rix].phy == WLAN_RC_PHY_OFDM || | |
1479 | WLAN_RC_PHY_HT(rt->info[rix].phy))) { | |
1480 | if (sc->sc_protmode == PROT_M_RTSCTS) | |
1481 | flags = ATH9K_TXDESC_RTSENA; | |
1482 | else if (sc->sc_protmode == PROT_M_CTSONLY) | |
1483 | flags = ATH9K_TXDESC_CTSENA; | |
1484 | ||
1485 | cix = rt->info[enable_g_protection].ctrl_rate; | |
1486 | rtsctsena = 1; | |
1487 | } | |
1488 | ||
1489 | /* For 11n, the default behavior is to enable RTS for hw retried frames. | |
1490 | * We enable the global flag here and let rate series flags determine | |
1491 | * which rates will actually use RTS. | |
1492 | */ | |
1493 | if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) { | |
1494 | /* 802.11g protection not needed, use our default behavior */ | |
1495 | if (!rtsctsena) | |
1496 | flags = ATH9K_TXDESC_RTSENA; | |
1497 | } | |
1498 | ||
1499 | /* Set protection if aggregate protection on */ | |
1500 | if (sc->sc_config.ath_aggr_prot && | |
1501 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { | |
1502 | flags = ATH9K_TXDESC_RTSENA; | |
1503 | cix = rt->info[enable_g_protection].ctrl_rate; | |
1504 | rtsctsena = 1; | |
1505 | } | |
1506 | ||
1507 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1508 | if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit)) | |
1509 | flags &= ~(ATH9K_TXDESC_RTSENA); | |
1510 | ||
1511 | /* | |
1512 | * CTS transmit rate is derived from the transmit rate by looking in the | |
1513 | * h/w rate table. We must also factor in whether or not a short | |
1514 | * preamble is to be used. NB: cix is set above where RTS/CTS is enabled | |
1515 | */ | |
1516 | ctsrate = rt->info[cix].ratecode | | |
1517 | (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0); | |
1518 | ||
1519 | for (i = 0; i < 4; i++) { | |
1520 | if (!rates[i].count || (rates[i].idx < 0)) | |
1521 | continue; | |
1522 | ||
1523 | rix = rates[i].idx; | |
1524 | ||
1525 | series[i].Rate = rt->info[rix].ratecode | | |
1526 | (bf_isshpreamble(bf) ? rt->info[rix].short_preamble : 0); | |
1527 | ||
1528 | series[i].Tries = rates[i].count; | |
1529 | ||
1530 | series[i].RateFlags = ( | |
1531 | (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) ? | |
1532 | ATH9K_RATESERIES_RTS_CTS : 0) | | |
1533 | ((rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? | |
1534 | ATH9K_RATESERIES_2040 : 0) | | |
1535 | ((rates[i].flags & IEEE80211_TX_RC_SHORT_GI) ? | |
1536 | ATH9K_RATESERIES_HALFGI : 0); | |
1537 | ||
1538 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1539 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1540 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
1541 | bf_isshpreamble(bf)); | |
f078f209 | 1542 | |
e8324357 | 1543 | series[i].ChSel = sc->sc_tx_chainmask; |
f078f209 | 1544 | |
e8324357 S |
1545 | if (rtsctsena) |
1546 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
f078f209 LR |
1547 | } |
1548 | ||
e8324357 S |
1549 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
1550 | ath9k_hw_set11n_ratescenario(ah, ds, lastds, !bf_ispspoll(bf), | |
1551 | ctsrate, ctsduration, | |
1552 | series, 4, flags); | |
f078f209 | 1553 | |
e8324357 S |
1554 | if (sc->sc_config.ath_aggr_prot && flags) |
1555 | ath9k_hw_set11n_burstduration(ah, ds, 8192); | |
f078f209 LR |
1556 | } |
1557 | ||
f8316df1 | 1558 | static int ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf, |
8f93b8b3 | 1559 | struct sk_buff *skb, |
528f0c6b | 1560 | struct ath_tx_control *txctl) |
f078f209 | 1561 | { |
528f0c6b S |
1562 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1563 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1564 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1565 | int hdrlen; |
1566 | __le16 fc; | |
e022edbd | 1567 | |
c112d0c5 LR |
1568 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1569 | if (unlikely(!tx_info_priv)) | |
1570 | return -ENOMEM; | |
a8efee4f | 1571 | tx_info->rate_driver_data[0] = tx_info_priv; |
528f0c6b S |
1572 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1573 | fc = hdr->frame_control; | |
f078f209 | 1574 | |
528f0c6b | 1575 | ATH_TXBUF_RESET(bf); |
f078f209 | 1576 | |
528f0c6b | 1577 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 S |
1578 | |
1579 | ieee80211_is_data(fc) ? | |
1580 | (bf->bf_state.bf_type |= BUF_DATA) : | |
1581 | (bf->bf_state.bf_type &= ~BUF_DATA); | |
1582 | ieee80211_is_back_req(fc) ? | |
1583 | (bf->bf_state.bf_type |= BUF_BAR) : | |
1584 | (bf->bf_state.bf_type &= ~BUF_BAR); | |
1585 | ieee80211_is_pspoll(fc) ? | |
1586 | (bf->bf_state.bf_type |= BUF_PSPOLL) : | |
1587 | (bf->bf_state.bf_type &= ~BUF_PSPOLL); | |
672840ac | 1588 | (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ? |
cd3d39a6 S |
1589 | (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) : |
1590 | (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE); | |
ecf70441 | 1591 | (conf_is_ht(&sc->hw->conf) && !is_pae(skb) && |
528f0c6b S |
1592 | (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ? |
1593 | (bf->bf_state.bf_type |= BUF_HT) : | |
1594 | (bf->bf_state.bf_type &= ~BUF_HT); | |
1595 | ||
1596 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1597 | ||
528f0c6b S |
1598 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
1599 | ||
1600 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { | |
1601 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1602 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1603 | } else { | |
1604 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1605 | } | |
1606 | ||
d3a1db1c | 1607 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1608 | assign_aggr_tid_seqno(skb, bf); |
1609 | ||
f078f209 | 1610 | bf->bf_mpdu = skb; |
f8316df1 | 1611 | |
7da3c55c GJ |
1612 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1613 | skb->len, DMA_TO_DEVICE); | |
1614 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 LR |
1615 | bf->bf_mpdu = NULL; |
1616 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 1617 | "dma_mapping_error() on TX\n"); |
f8316df1 LR |
1618 | return -ENOMEM; |
1619 | } | |
1620 | ||
528f0c6b | 1621 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1622 | return 0; |
528f0c6b S |
1623 | } |
1624 | ||
1625 | /* FIXME: tx power */ | |
1626 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1627 | struct ath_tx_control *txctl) |
1628 | { | |
1629 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
1630 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1631 | struct ath_node *an = NULL; | |
1632 | struct list_head bf_head; | |
1633 | struct ath_desc *ds; | |
1634 | struct ath_atx_tid *tid; | |
1635 | struct ath_hal *ah = sc->sc_ah; | |
1636 | int frm_type; | |
1637 | ||
528f0c6b S |
1638 | frm_type = get_hw_packet_type(skb); |
1639 | ||
1640 | INIT_LIST_HEAD(&bf_head); | |
1641 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1642 | |
f078f209 LR |
1643 | ds = bf->bf_desc; |
1644 | ds->ds_link = 0; | |
1645 | ds->ds_data = bf->bf_buf_addr; | |
1646 | ||
528f0c6b S |
1647 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1648 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1649 | ||
1650 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1651 | skb->len, /* segment length */ |
1652 | true, /* first segment */ | |
1653 | true, /* last segment */ | |
1654 | ds); /* first descriptor */ | |
f078f209 | 1655 | |
528f0c6b | 1656 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1657 | |
f1617967 JL |
1658 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1659 | tx_info->control.sta) { | |
1660 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1661 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1662 | ||
528f0c6b | 1663 | if (ath_aggr_query(sc, an, bf->bf_tidno)) { |
f078f209 LR |
1664 | /* |
1665 | * Try aggregation if it's a unicast data frame | |
1666 | * and the destination is HT capable. | |
1667 | */ | |
528f0c6b | 1668 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1669 | } else { |
1670 | /* | |
528f0c6b S |
1671 | * Send this frame as regular when ADDBA |
1672 | * exchange is neither complete nor pending. | |
f078f209 | 1673 | */ |
528f0c6b S |
1674 | ath_tx_send_normal(sc, txctl->txq, |
1675 | tid, &bf_head); | |
f078f209 LR |
1676 | } |
1677 | } else { | |
1678 | bf->bf_lastbf = bf; | |
1679 | bf->bf_nframes = 1; | |
f078f209 | 1680 | |
528f0c6b S |
1681 | ath_buf_set_rate(sc, bf); |
1682 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head); | |
f078f209 | 1683 | } |
528f0c6b S |
1684 | |
1685 | spin_unlock_bh(&txctl->txq->axq_lock); | |
f078f209 LR |
1686 | } |
1687 | ||
f8316df1 | 1688 | /* Upon failure caller should free skb */ |
528f0c6b S |
1689 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, |
1690 | struct ath_tx_control *txctl) | |
f078f209 | 1691 | { |
528f0c6b | 1692 | struct ath_buf *bf; |
f8316df1 | 1693 | int r; |
f078f209 | 1694 | |
528f0c6b S |
1695 | bf = ath_tx_get_buffer(sc); |
1696 | if (!bf) { | |
04bd4638 | 1697 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1698 | return -1; |
1699 | } | |
1700 | ||
f8316df1 LR |
1701 | r = ath_tx_setup_buffer(sc, bf, skb, txctl); |
1702 | if (unlikely(r)) { | |
c112d0c5 LR |
1703 | struct ath_txq *txq = txctl->txq; |
1704 | ||
f8316df1 | 1705 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1706 | |
1707 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1708 | * guarantee this will happen by knowing beforehand that | |
1709 | * we will at least have to run TX completionon one buffer | |
1710 | * on the queue */ | |
1711 | spin_lock_bh(&txq->axq_lock); | |
1712 | if (ath_txq_depth(sc, txq->axq_qnum) > 1) { | |
1713 | ieee80211_stop_queue(sc->hw, | |
1714 | skb_get_queue_mapping(skb)); | |
1715 | txq->stopped = 1; | |
1716 | } | |
1717 | spin_unlock_bh(&txq->axq_lock); | |
1718 | ||
b77f483f S |
1719 | spin_lock_bh(&sc->tx.txbuflock); |
1720 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1721 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1722 | |
f8316df1 LR |
1723 | return r; |
1724 | } | |
1725 | ||
8f93b8b3 | 1726 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1727 | |
528f0c6b | 1728 | return 0; |
f078f209 LR |
1729 | } |
1730 | ||
e8324357 | 1731 | void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb) |
f078f209 | 1732 | { |
e8324357 S |
1733 | int hdrlen, padsize; |
1734 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1735 | struct ath_tx_control txctl; | |
f078f209 | 1736 | |
e8324357 | 1737 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1738 | |
1739 | /* | |
e8324357 S |
1740 | * As a temporary workaround, assign seq# here; this will likely need |
1741 | * to be cleaned up to work better with Beacon transmission and virtual | |
1742 | * BSSes. | |
f078f209 | 1743 | */ |
e8324357 S |
1744 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1745 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1746 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1747 | sc->tx.seq_no += 0x10; | |
1748 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1749 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1750 | } |
f078f209 | 1751 | |
e8324357 S |
1752 | /* Add the padding after the header if this is not already done */ |
1753 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1754 | if (hdrlen & 3) { | |
1755 | padsize = hdrlen % 4; | |
1756 | if (skb_headroom(skb) < padsize) { | |
1757 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1758 | dev_kfree_skb_any(skb); | |
1759 | return; | |
1760 | } | |
1761 | skb_push(skb, padsize); | |
1762 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1763 | } |
f078f209 | 1764 | |
e8324357 | 1765 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1766 | |
e8324357 | 1767 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1768 | |
e8324357 S |
1769 | if (ath_tx_start(sc, skb, &txctl) != 0) { |
1770 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); | |
1771 | goto exit; | |
f078f209 | 1772 | } |
f078f209 | 1773 | |
e8324357 S |
1774 | return; |
1775 | exit: | |
1776 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1777 | } |
1778 | ||
e8324357 S |
1779 | /*****************/ |
1780 | /* TX Completion */ | |
1781 | /*****************/ | |
528f0c6b | 1782 | |
e8324357 S |
1783 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
1784 | struct ath_xmit_status *tx_status) | |
528f0c6b | 1785 | { |
e8324357 S |
1786 | struct ieee80211_hw *hw = sc->hw; |
1787 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1788 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1789 | int hdrlen, padsize; | |
528f0c6b | 1790 | |
e8324357 | 1791 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1792 | |
e8324357 S |
1793 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1794 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1795 | kfree(tx_info_priv); | |
1796 | tx_info->rate_driver_data[0] = NULL; | |
1797 | } | |
528f0c6b | 1798 | |
e8324357 S |
1799 | if (tx_status->flags & ATH_TX_BAR) { |
1800 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
1801 | tx_status->flags &= ~ATH_TX_BAR; | |
1802 | } | |
1803 | ||
1804 | if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { | |
1805 | /* Frame was ACKed */ | |
1806 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1807 | } |
1808 | ||
e8324357 | 1809 | tx_info->status.rates[0].count = tx_status->retries + 1; |
528f0c6b | 1810 | |
e8324357 S |
1811 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1812 | padsize = hdrlen & 3; | |
1813 | if (padsize && hdrlen >= 24) { | |
1814 | /* | |
1815 | * Remove MAC header padding before giving the frame back to | |
1816 | * mac80211. | |
1817 | */ | |
1818 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1819 | skb_pull(skb, padsize); | |
1820 | } | |
528f0c6b | 1821 | |
e8324357 S |
1822 | ieee80211_tx_status(hw, skb); |
1823 | } | |
f078f209 | 1824 | |
e8324357 S |
1825 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
1826 | struct list_head *bf_q, | |
1827 | int txok, int sendbar) | |
f078f209 | 1828 | { |
e8324357 S |
1829 | struct sk_buff *skb = bf->bf_mpdu; |
1830 | struct ath_xmit_status tx_status; | |
1831 | unsigned long flags; | |
f078f209 | 1832 | |
e8324357 S |
1833 | /* |
1834 | * Set retry information. | |
1835 | * NB: Don't use the information in the descriptor, because the frame | |
1836 | * could be software retried. | |
1837 | */ | |
1838 | tx_status.retries = bf->bf_retries; | |
1839 | tx_status.flags = 0; | |
f078f209 | 1840 | |
e8324357 S |
1841 | if (sendbar) |
1842 | tx_status.flags = ATH_TX_BAR; | |
f078f209 | 1843 | |
e8324357 S |
1844 | if (!txok) { |
1845 | tx_status.flags |= ATH_TX_ERROR; | |
f078f209 | 1846 | |
e8324357 S |
1847 | if (bf_isxretried(bf)) |
1848 | tx_status.flags |= ATH_TX_XRETRY; | |
f078f209 LR |
1849 | } |
1850 | ||
e8324357 S |
1851 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
1852 | ath_tx_complete(sc, skb, &tx_status); | |
1853 | ||
1854 | /* | |
1855 | * Return the list of ath_buf of this mpdu to free queue | |
1856 | */ | |
1857 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1858 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1859 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1860 | } |
1861 | ||
e8324357 S |
1862 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1863 | int txok) | |
f078f209 | 1864 | { |
e8324357 S |
1865 | struct ath_buf *bf_last = bf->bf_lastbf; |
1866 | struct ath_desc *ds = bf_last->bf_desc; | |
1867 | u16 seq_st = 0; | |
1868 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1869 | int ba_index; | |
1870 | int nbad = 0; | |
1871 | int isaggr = 0; | |
f078f209 | 1872 | |
e8324357 S |
1873 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1874 | return 0; | |
f078f209 | 1875 | |
e8324357 S |
1876 | isaggr = bf_isaggr(bf); |
1877 | if (isaggr) { | |
1878 | seq_st = ATH_DS_BA_SEQ(ds); | |
1879 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1880 | } | |
f078f209 | 1881 | |
e8324357 S |
1882 | while (bf) { |
1883 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1884 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1885 | nbad++; | |
1886 | ||
1887 | bf = bf->bf_next; | |
1888 | } | |
f078f209 | 1889 | |
e8324357 S |
1890 | return nbad; |
1891 | } | |
f078f209 | 1892 | |
e8324357 | 1893 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad) |
f078f209 | 1894 | { |
e8324357 S |
1895 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; |
1896 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1897 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
f078f209 | 1898 | |
e8324357 S |
1899 | tx_info_priv->update_rc = false; |
1900 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) | |
1901 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1902 | |
e8324357 S |
1903 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
1904 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | |
1905 | if (bf_isdata(bf)) { | |
1906 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, | |
1907 | sizeof(tx_info_priv->tx)); | |
1908 | tx_info_priv->n_frames = bf->bf_nframes; | |
1909 | tx_info_priv->n_bad_frames = nbad; | |
1910 | tx_info_priv->update_rc = true; | |
1911 | } | |
f078f209 | 1912 | } |
f078f209 LR |
1913 | } |
1914 | ||
059d806c S |
1915 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1916 | { | |
1917 | int qnum; | |
1918 | ||
1919 | spin_lock_bh(&txq->axq_lock); | |
1920 | if (txq->stopped && | |
1921 | ath_txq_depth(sc, txq->axq_qnum) <= (ATH_TXBUF - 20)) { | |
1922 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); | |
1923 | if (qnum != -1) { | |
1924 | ieee80211_wake_queue(sc->hw, qnum); | |
1925 | txq->stopped = 0; | |
1926 | } | |
1927 | } | |
1928 | spin_unlock_bh(&txq->axq_lock); | |
1929 | } | |
1930 | ||
e8324357 | 1931 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1932 | { |
e8324357 S |
1933 | struct ath_hal *ah = sc->sc_ah; |
1934 | struct ath_buf *bf, *lastbf, *bf_held = NULL; | |
f078f209 | 1935 | struct list_head bf_head; |
e8324357 S |
1936 | struct ath_desc *ds; |
1937 | int txok, nbad = 0; | |
1938 | int status; | |
f078f209 | 1939 | |
e8324357 S |
1940 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1941 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1942 | txq->axq_link); | |
f078f209 | 1943 | |
f078f209 LR |
1944 | for (;;) { |
1945 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1946 | if (list_empty(&txq->axq_q)) { |
1947 | txq->axq_link = NULL; | |
1948 | txq->axq_linkbuf = NULL; | |
1949 | spin_unlock_bh(&txq->axq_lock); | |
1950 | break; | |
1951 | } | |
f078f209 LR |
1952 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1953 | ||
e8324357 S |
1954 | /* |
1955 | * There is a race condition that a BH gets scheduled | |
1956 | * after sw writes TxE and before hw re-load the last | |
1957 | * descriptor to get the newly chained one. | |
1958 | * Software must keep the last DONE descriptor as a | |
1959 | * holding descriptor - software does so by marking | |
1960 | * it with the STALE flag. | |
1961 | */ | |
1962 | bf_held = NULL; | |
f078f209 | 1963 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
e8324357 S |
1964 | bf_held = bf; |
1965 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d S |
1966 | txq->axq_link = NULL; |
1967 | txq->axq_linkbuf = NULL; | |
1968 | spin_unlock_bh(&txq->axq_lock); | |
1969 | ||
1970 | /* | |
e8324357 S |
1971 | * The holding descriptor is the last |
1972 | * descriptor in queue. It's safe to remove | |
1973 | * the last holding descriptor in BH context. | |
1974 | */ | |
6ef9b13d S |
1975 | spin_lock_bh(&sc->tx.txbuflock); |
1976 | list_move_tail(&bf_held->list, &sc->tx.txbuf); | |
1977 | spin_unlock_bh(&sc->tx.txbuflock); | |
1978 | ||
e8324357 S |
1979 | break; |
1980 | } else { | |
1981 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1982 | struct ath_buf, list); |
e8324357 | 1983 | } |
f078f209 LR |
1984 | } |
1985 | ||
1986 | lastbf = bf->bf_lastbf; | |
e8324357 | 1987 | ds = lastbf->bf_desc; |
f078f209 | 1988 | |
e8324357 S |
1989 | status = ath9k_hw_txprocdesc(ah, ds); |
1990 | if (status == -EINPROGRESS) { | |
f078f209 | 1991 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 1992 | break; |
f078f209 | 1993 | } |
e8324357 S |
1994 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
1995 | txq->axq_lastdsWithCTS = NULL; | |
1996 | if (ds == txq->axq_gatingds) | |
1997 | txq->axq_gatingds = NULL; | |
f078f209 | 1998 | |
e8324357 S |
1999 | /* |
2000 | * Remove ath_buf's of the same transmit unit from txq, | |
2001 | * however leave the last descriptor back as the holding | |
2002 | * descriptor for hw. | |
2003 | */ | |
2004 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | |
2005 | INIT_LIST_HEAD(&bf_head); | |
e8324357 S |
2006 | if (!list_is_singular(&lastbf->list)) |
2007 | list_cut_position(&bf_head, | |
2008 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2009 | |
e8324357 | 2010 | txq->axq_depth--; |
e8324357 S |
2011 | if (bf_isaggr(bf)) |
2012 | txq->axq_aggr_depth--; | |
f078f209 | 2013 | |
e8324357 | 2014 | txok = (ds->ds_txstat.ts_status == 0); |
e8324357 | 2015 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2016 | |
e8324357 | 2017 | if (bf_held) { |
e8324357 | 2018 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2019 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2020 | spin_unlock_bh(&sc->tx.txbuflock); |
2021 | } | |
f078f209 | 2022 | |
e8324357 S |
2023 | if (!bf_isampdu(bf)) { |
2024 | /* | |
2025 | * This frame is sent out as a single frame. | |
2026 | * Use hardware retry status for this frame. | |
2027 | */ | |
2028 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2029 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2030 | bf->bf_state.bf_type |= BUF_XRETRY; | |
2031 | nbad = 0; | |
2032 | } else { | |
2033 | nbad = ath_tx_num_badfrms(sc, bf, txok); | |
2034 | } | |
f078f209 | 2035 | |
e8324357 | 2036 | ath_tx_rc_status(bf, ds, nbad); |
f078f209 | 2037 | |
e8324357 | 2038 | if (bf_isampdu(bf)) |
d43f3015 | 2039 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 S |
2040 | else |
2041 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
8469cdef | 2042 | |
059d806c | 2043 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2044 | |
059d806c | 2045 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2046 | if (sc->sc_flags & SC_OP_TXAGGR) |
2047 | ath_txq_schedule(sc, txq); | |
2048 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2049 | } |
2050 | } | |
2051 | ||
f078f209 | 2052 | |
e8324357 | 2053 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2054 | { |
e8324357 S |
2055 | int i; |
2056 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2057 | |
e8324357 | 2058 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2059 | |
e8324357 S |
2060 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2061 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2062 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2063 | } |
2064 | } | |
2065 | ||
e8324357 S |
2066 | /*****************/ |
2067 | /* Init, Cleanup */ | |
2068 | /*****************/ | |
f078f209 | 2069 | |
e8324357 | 2070 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2071 | { |
e8324357 | 2072 | int error = 0; |
f078f209 | 2073 | |
f078f209 | 2074 | do { |
e8324357 | 2075 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2076 | |
e8324357 S |
2077 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2078 | "tx", nbufs, 1); | |
2079 | if (error != 0) { | |
2080 | DPRINTF(sc, ATH_DBG_FATAL, | |
2081 | "Failed to allocate tx descriptors: %d\n", | |
2082 | error); | |
2083 | break; | |
2084 | } | |
f078f209 | 2085 | |
e8324357 S |
2086 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2087 | "beacon", ATH_BCBUF, 1); | |
2088 | if (error != 0) { | |
2089 | DPRINTF(sc, ATH_DBG_FATAL, | |
2090 | "Failed to allocate beacon descriptors: %d\n", | |
2091 | error); | |
2092 | break; | |
2093 | } | |
f078f209 | 2094 | |
e8324357 | 2095 | } while (0); |
f078f209 | 2096 | |
e8324357 S |
2097 | if (error != 0) |
2098 | ath_tx_cleanup(sc); | |
f078f209 | 2099 | |
e8324357 | 2100 | return error; |
f078f209 LR |
2101 | } |
2102 | ||
e8324357 S |
2103 | int ath_tx_cleanup(struct ath_softc *sc) |
2104 | { | |
2105 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2106 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2107 | ||
2108 | if (sc->tx.txdma.dd_desc_len != 0) | |
2109 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
2110 | ||
2111 | return 0; | |
2112 | } | |
f078f209 LR |
2113 | |
2114 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2115 | { | |
c5170163 S |
2116 | struct ath_atx_tid *tid; |
2117 | struct ath_atx_ac *ac; | |
2118 | int tidno, acno; | |
f078f209 | 2119 | |
8ee5afbc | 2120 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2121 | tidno < WME_NUM_TID; |
2122 | tidno++, tid++) { | |
2123 | tid->an = an; | |
2124 | tid->tidno = tidno; | |
2125 | tid->seq_start = tid->seq_next = 0; | |
2126 | tid->baw_size = WME_MAX_BA; | |
2127 | tid->baw_head = tid->baw_tail = 0; | |
2128 | tid->sched = false; | |
e8324357 | 2129 | tid->paused = false; |
a37c2c79 | 2130 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2131 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2132 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2133 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2134 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2135 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
2136 | tid->addba_exchangeattempts = 0; | |
c5170163 | 2137 | } |
f078f209 | 2138 | |
8ee5afbc | 2139 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2140 | acno < WME_NUM_AC; acno++, ac++) { |
2141 | ac->sched = false; | |
2142 | INIT_LIST_HEAD(&ac->tid_q); | |
2143 | ||
2144 | switch (acno) { | |
2145 | case WME_AC_BE: | |
2146 | ac->qnum = ath_tx_get_qnum(sc, | |
2147 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2148 | break; | |
2149 | case WME_AC_BK: | |
2150 | ac->qnum = ath_tx_get_qnum(sc, | |
2151 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2152 | break; | |
2153 | case WME_AC_VI: | |
2154 | ac->qnum = ath_tx_get_qnum(sc, | |
2155 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2156 | break; | |
2157 | case WME_AC_VO: | |
2158 | ac->qnum = ath_tx_get_qnum(sc, | |
2159 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2160 | break; | |
f078f209 LR |
2161 | } |
2162 | } | |
2163 | } | |
2164 | ||
b5aa9bf9 | 2165 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2166 | { |
2167 | int i; | |
2168 | struct ath_atx_ac *ac, *ac_tmp; | |
2169 | struct ath_atx_tid *tid, *tid_tmp; | |
2170 | struct ath_txq *txq; | |
e8324357 | 2171 | |
f078f209 LR |
2172 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2173 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2174 | txq = &sc->tx.txq[i]; |
f078f209 | 2175 | |
b5aa9bf9 | 2176 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2177 | |
2178 | list_for_each_entry_safe(ac, | |
2179 | ac_tmp, &txq->axq_acq, list) { | |
2180 | tid = list_first_entry(&ac->tid_q, | |
2181 | struct ath_atx_tid, list); | |
2182 | if (tid && tid->an != an) | |
2183 | continue; | |
2184 | list_del(&ac->list); | |
2185 | ac->sched = false; | |
2186 | ||
2187 | list_for_each_entry_safe(tid, | |
2188 | tid_tmp, &ac->tid_q, list) { | |
2189 | list_del(&tid->list); | |
2190 | tid->sched = false; | |
b5aa9bf9 | 2191 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2192 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
f078f209 | 2193 | tid->addba_exchangeattempts = 0; |
a37c2c79 | 2194 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2195 | } |
2196 | } | |
2197 | ||
b5aa9bf9 | 2198 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2199 | } |
2200 | } | |
2201 | } |