Commit | Line | Data |
---|---|---|
e4d6b795 MB |
1 | #ifndef B43_H_ |
2 | #define B43_H_ | |
3 | ||
4 | #include <linux/kernel.h> | |
5 | #include <linux/spinlock.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/hw_random.h> | |
3c65ab62 | 8 | #include <linux/bcma/bcma.h> |
e4d6b795 MB |
9 | #include <linux/ssb/ssb.h> |
10 | #include <net/mac80211.h> | |
11 | ||
12 | #include "debugfs.h" | |
13 | #include "leds.h" | |
8e9f7529 | 14 | #include "rfkill.h" |
482f0538 | 15 | #include "bus.h" |
e4d6b795 | 16 | #include "lo.h" |
ef1a628d | 17 | #include "phy_common.h" |
e4d6b795 | 18 | |
26bc783f | 19 | |
e4d6b795 MB |
20 | #ifdef CONFIG_B43_DEBUG |
21 | # define B43_DEBUG 1 | |
22 | #else | |
23 | # define B43_DEBUG 0 | |
24 | #endif | |
25 | ||
e4d6b795 MB |
26 | /* MMIO offsets */ |
27 | #define B43_MMIO_DMA0_REASON 0x20 | |
28 | #define B43_MMIO_DMA0_IRQ_MASK 0x24 | |
29 | #define B43_MMIO_DMA1_REASON 0x28 | |
30 | #define B43_MMIO_DMA1_IRQ_MASK 0x2C | |
31 | #define B43_MMIO_DMA2_REASON 0x30 | |
32 | #define B43_MMIO_DMA2_IRQ_MASK 0x34 | |
33 | #define B43_MMIO_DMA3_REASON 0x38 | |
34 | #define B43_MMIO_DMA3_IRQ_MASK 0x3C | |
35 | #define B43_MMIO_DMA4_REASON 0x40 | |
36 | #define B43_MMIO_DMA4_IRQ_MASK 0x44 | |
37 | #define B43_MMIO_DMA5_REASON 0x48 | |
38 | #define B43_MMIO_DMA5_IRQ_MASK 0x4C | |
aa6c7ae2 MB |
39 | #define B43_MMIO_MACCTL 0x120 /* MAC control */ |
40 | #define B43_MMIO_MACCMD 0x124 /* MAC command */ | |
e4d6b795 MB |
41 | #define B43_MMIO_GEN_IRQ_REASON 0x128 |
42 | #define B43_MMIO_GEN_IRQ_MASK 0x12C | |
43 | #define B43_MMIO_RAM_CONTROL 0x130 | |
44 | #define B43_MMIO_RAM_DATA 0x134 | |
45 | #define B43_MMIO_PS_STATUS 0x140 | |
46 | #define B43_MMIO_RADIO_HWENABLED_HI 0x158 | |
47 | #define B43_MMIO_SHM_CONTROL 0x160 | |
48 | #define B43_MMIO_SHM_DATA 0x164 | |
49 | #define B43_MMIO_SHM_DATA_UNALIGNED 0x166 | |
50 | #define B43_MMIO_XMITSTAT_0 0x170 | |
51 | #define B43_MMIO_XMITSTAT_1 0x174 | |
52 | #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ | |
53 | #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ | |
f3dd3fcc MB |
54 | #define B43_MMIO_TSF_CFP_REP 0x188 |
55 | #define B43_MMIO_TSF_CFP_START 0x18C | |
56 | #define B43_MMIO_TSF_CFP_MAXDUR 0x190 | |
e4d6b795 MB |
57 | |
58 | /* 32-bit DMA */ | |
59 | #define B43_MMIO_DMA32_BASE0 0x200 | |
60 | #define B43_MMIO_DMA32_BASE1 0x220 | |
61 | #define B43_MMIO_DMA32_BASE2 0x240 | |
62 | #define B43_MMIO_DMA32_BASE3 0x260 | |
63 | #define B43_MMIO_DMA32_BASE4 0x280 | |
64 | #define B43_MMIO_DMA32_BASE5 0x2A0 | |
65 | /* 64-bit DMA */ | |
66 | #define B43_MMIO_DMA64_BASE0 0x200 | |
67 | #define B43_MMIO_DMA64_BASE1 0x240 | |
68 | #define B43_MMIO_DMA64_BASE2 0x280 | |
69 | #define B43_MMIO_DMA64_BASE3 0x2C0 | |
70 | #define B43_MMIO_DMA64_BASE4 0x300 | |
71 | #define B43_MMIO_DMA64_BASE5 0x340 | |
e4d6b795 | 72 | |
5100d5ac MB |
73 | /* PIO on core rev < 11 */ |
74 | #define B43_MMIO_PIO_BASE0 0x300 | |
75 | #define B43_MMIO_PIO_BASE1 0x310 | |
76 | #define B43_MMIO_PIO_BASE2 0x320 | |
77 | #define B43_MMIO_PIO_BASE3 0x330 | |
78 | #define B43_MMIO_PIO_BASE4 0x340 | |
79 | #define B43_MMIO_PIO_BASE5 0x350 | |
80 | #define B43_MMIO_PIO_BASE6 0x360 | |
81 | #define B43_MMIO_PIO_BASE7 0x370 | |
82 | /* PIO on core rev >= 11 */ | |
83 | #define B43_MMIO_PIO11_BASE0 0x200 | |
84 | #define B43_MMIO_PIO11_BASE1 0x240 | |
85 | #define B43_MMIO_PIO11_BASE2 0x280 | |
86 | #define B43_MMIO_PIO11_BASE3 0x2C0 | |
87 | #define B43_MMIO_PIO11_BASE4 0x300 | |
88 | #define B43_MMIO_PIO11_BASE5 0x340 | |
89 | ||
443c1a24 RM |
90 | #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */ |
91 | #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */ | |
e4d6b795 MB |
92 | #define B43_MMIO_PHY_VER 0x3E0 |
93 | #define B43_MMIO_PHY_RADIO 0x3E2 | |
94 | #define B43_MMIO_PHY0 0x3E6 | |
95 | #define B43_MMIO_ANTENNA 0x3E8 | |
96 | #define B43_MMIO_CHANNEL 0x3F0 | |
97 | #define B43_MMIO_CHANNEL_EXT 0x3F4 | |
98 | #define B43_MMIO_RADIO_CONTROL 0x3F6 | |
99 | #define B43_MMIO_RADIO_DATA_HIGH 0x3F8 | |
100 | #define B43_MMIO_RADIO_DATA_LOW 0x3FA | |
101 | #define B43_MMIO_PHY_CONTROL 0x3FC | |
102 | #define B43_MMIO_PHY_DATA 0x3FE | |
103 | #define B43_MMIO_MACFILTER_CONTROL 0x420 | |
104 | #define B43_MMIO_MACFILTER_DATA 0x422 | |
105 | #define B43_MMIO_RCMTA_COUNT 0x43C | |
9734485c | 106 | #define B43_MMIO_PSM_PHY_HDR 0x492 |
e4d6b795 MB |
107 | #define B43_MMIO_RADIO_HWENABLED_LO 0x49A |
108 | #define B43_MMIO_GPIO_CONTROL 0x49C | |
109 | #define B43_MMIO_GPIO_MASK 0x49E | |
7955d87f RM |
110 | #define B43_MMIO_TXE0_CTL 0x500 |
111 | #define B43_MMIO_TXE0_AUX 0x502 | |
112 | #define B43_MMIO_TXE0_TS_LOC 0x504 | |
113 | #define B43_MMIO_TXE0_TIME_OUT 0x506 | |
114 | #define B43_MMIO_TXE0_WM_0 0x508 | |
115 | #define B43_MMIO_TXE0_WM_1 0x50A | |
116 | #define B43_MMIO_TXE0_PHYCTL 0x50C | |
117 | #define B43_MMIO_TXE0_STATUS 0x50E | |
118 | #define B43_MMIO_TXE0_MMPLCP0 0x510 | |
119 | #define B43_MMIO_TXE0_MMPLCP1 0x512 | |
120 | #define B43_MMIO_TXE0_PHYCTL1 0x514 | |
121 | #define B43_MMIO_XMTFIFODEF 0x520 | |
122 | #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */ | |
123 | #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */ | |
124 | #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */ | |
125 | #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */ | |
126 | #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */ | |
127 | #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */ | |
128 | #define B43_MMIO_XMTFIFOCMD 0x540 | |
129 | #define B43_MMIO_XMTFIFOFLUSH 0x542 | |
130 | #define B43_MMIO_XMTFIFOTHRESH 0x544 | |
131 | #define B43_MMIO_XMTFIFORDY 0x546 | |
132 | #define B43_MMIO_XMTFIFOPRIRDY 0x548 | |
133 | #define B43_MMIO_XMTFIFORQPRI 0x54A | |
134 | #define B43_MMIO_XMTTPLATETXPTR 0x54C | |
135 | #define B43_MMIO_XMTTPLATEPTR 0x550 | |
136 | #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */ | |
137 | #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */ | |
138 | #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */ | |
139 | #define B43_MMIO_XMTTPLATEDATALO 0x560 | |
140 | #define B43_MMIO_XMTTPLATEDATAHI 0x562 | |
141 | #define B43_MMIO_XMTSEL 0x568 | |
142 | #define B43_MMIO_XMTTXCNT 0x56A | |
143 | #define B43_MMIO_XMTTXSHMADDR 0x56C | |
f3dd3fcc MB |
144 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 |
145 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 | |
d59f720d | 146 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 |
0b4ff45d RM |
147 | #define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E |
148 | #define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630 | |
e4d6b795 MB |
149 | #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
150 | #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ | |
151 | #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ | |
152 | #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ | |
153 | #define B43_MMIO_RNG 0x65A | |
b6c3f5be | 154 | #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ |
7955d87f RM |
155 | #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ |
156 | #define B43_MMIO_IFSSTAT 0x690 | |
157 | #define B43_MMIO_IFSMEDBUSYCTL 0x692 | |
158 | #define B43_MMIO_IFTXDUR 0x694 | |
e6f5b934 | 159 | #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 |
e4d6b795 | 160 | #define B43_MMIO_POWERUP_DELAY 0x6A8 |
ce1a9ee3 MB |
161 | #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ |
162 | #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ | |
163 | #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ | |
7955d87f | 164 | #define B43_MMIO_WEPCTL 0x7C0 |
e4d6b795 MB |
165 | |
166 | /* SPROM boardflags_lo values */ | |
167 | #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ | |
168 | #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ | |
169 | #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ | |
170 | #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ | |
171 | #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ | |
172 | #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ | |
173 | #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ | |
174 | #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */ | |
175 | #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */ | |
176 | #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ | |
177 | #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */ | |
178 | #define B43_BFL_FEM 0x0800 /* supports the Front End Module */ | |
179 | #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */ | |
180 | #define B43_BFL_HGPA 0x2000 /* had high gain PA */ | |
181 | #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ | |
182 | #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ | |
183 | ||
738f0f43 GS |
184 | /* SPROM boardflags_hi values */ |
185 | #define B43_BFH_NOPA 0x0001 /* has no PA */ | |
186 | #define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ | |
187 | #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */ | |
188 | #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared | |
189 | * with bluetooth */ | |
190 | #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ | |
191 | #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */ | |
192 | #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna | |
193 | * with bluetooth */ | |
cc96addd RM |
194 | #define B43_BFH_NOCBUCK 0x0080 |
195 | #define B43_BFH_PALDO 0x0200 | |
196 | #define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */ | |
738f0f43 | 197 | |
7e6da2bf RM |
198 | /* SPROM boardflags2_lo values */ |
199 | #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ | |
200 | #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ | |
201 | #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ | |
202 | #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ | |
203 | #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ | |
204 | #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ | |
205 | #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ | |
206 | #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ | |
207 | #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ | |
208 | #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ | |
209 | #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ | |
cc96addd RM |
210 | #define B43_BFL2_SINGLEANT_CCK 0x1000 |
211 | #define B43_BFL2_2G_SPUR_WAR 0x2000 | |
212 | ||
213 | /* SPROM boardflags2_hi values */ | |
214 | #define B43_BFH2_GPLL_WAR2 0x0001 | |
215 | #define B43_BFH2_IPALVLSHIFT_3P3 0x0002 | |
216 | #define B43_BFH2_INTERNDET_TXIQCAL 0x0004 | |
217 | #define B43_BFH2_XTALBUFOUTEN 0x0008 | |
7e6da2bf | 218 | |
e4d6b795 MB |
219 | /* GPIO register offset, in both ChipCommon and PCI core. */ |
220 | #define B43_GPIO_CONTROL 0x6c | |
221 | ||
222 | /* SHM Routing */ | |
223 | enum { | |
224 | B43_SHM_UCODE, /* Microcode memory */ | |
225 | B43_SHM_SHARED, /* Shared memory */ | |
226 | B43_SHM_SCRATCH, /* Scratch memory */ | |
227 | B43_SHM_HW, /* Internal hardware register */ | |
228 | B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */ | |
229 | }; | |
230 | /* SHM Routing modifiers */ | |
231 | #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */ | |
232 | #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */ | |
233 | #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \ | |
234 | B43_SHM_AUTOINC_W) | |
235 | ||
236 | /* Misc SHM_SHARED offsets */ | |
237 | #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ | |
238 | #define B43_SHM_SH_PCTLWDPOS 0x0008 | |
239 | #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */ | |
403a3a13 | 240 | #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */ |
e4d6b795 MB |
241 | #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */ |
242 | #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */ | |
243 | #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */ | |
244 | #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */ | |
35f0d354 MB |
245 | #define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */ |
246 | #define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */ | |
e4d6b795 MB |
247 | #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */ |
248 | #define B43_SHM_SH_RADAR 0x0066 /* Radar register */ | |
249 | #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ | |
250 | #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ | |
251 | #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ | |
106cb09a RM |
252 | #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */ |
253 | #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */ | |
e4d6b795 | 254 | #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ |
18c8adeb MB |
255 | /* TSSI information */ |
256 | #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ | |
257 | #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */ | |
258 | #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */ | |
259 | #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */ | |
e4d6b795 MB |
260 | /* SHM_SHARED TX FIFO variables */ |
261 | #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */ | |
262 | #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */ | |
263 | #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */ | |
264 | #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */ | |
265 | /* SHM_SHARED background noise */ | |
266 | #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */ | |
267 | #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */ | |
268 | #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */ | |
269 | /* SHM_SHARED crypto engine */ | |
270 | #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */ | |
271 | #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */ | |
272 | #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */ | |
273 | #define B43_SHM_SH_TKIPTSCTTAK 0x0318 | |
274 | #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */ | |
275 | #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */ | |
276 | /* SHM_SHARED WME variables */ | |
277 | #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */ | |
278 | #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */ | |
279 | #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */ | |
280 | /* SHM_SHARED powersave mode related */ | |
281 | #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */ | |
282 | #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */ | |
283 | #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */ | |
280d0e16 | 284 | /* SHM_SHARED beacon/AP variables */ |
e4d6b795 MB |
285 | #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ |
286 | #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ | |
287 | #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ | |
288 | #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */ | |
280d0e16 MB |
289 | #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */ |
290 | #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */ | |
e4d6b795 MB |
291 | #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */ |
292 | #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */ | |
293 | #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */ | |
280d0e16 | 294 | #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */ |
e4d6b795 MB |
295 | /* SHM_SHARED ACK/CTS control */ |
296 | #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */ | |
297 | /* SHM_SHARED probe response variables */ | |
298 | #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */ | |
299 | #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */ | |
300 | #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ | |
301 | #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ | |
302 | #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */ | |
303 | /* SHM_SHARED rate tables */ | |
304 | #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */ | |
305 | #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */ | |
306 | #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */ | |
307 | #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */ | |
308 | /* SHM_SHARED microcode soft registers */ | |
309 | #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ | |
310 | #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ | |
311 | #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ | |
312 | #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */ | |
313 | #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */ | |
314 | #define B43_SHM_SH_UCODESTAT_INVALID 0 | |
315 | #define B43_SHM_SH_UCODESTAT_INIT 1 | |
316 | #define B43_SHM_SH_UCODESTAT_ACTIVE 2 | |
317 | #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */ | |
318 | #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */ | |
319 | #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */ | |
320 | #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ | |
321 | #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ | |
76a4db30 RM |
322 | /* SHM_SHARED tx iq workarounds */ |
323 | #define B43_SHM_SH_NPHY_TXIQW0 0x0700 | |
324 | #define B43_SHM_SH_NPHY_TXIQW1 0x0702 | |
325 | #define B43_SHM_SH_NPHY_TXIQW2 0x0704 | |
326 | #define B43_SHM_SH_NPHY_TXIQW3 0x0706 | |
327 | /* SHM_SHARED tx pwr ctrl */ | |
328 | #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708 | |
329 | #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E | |
e4d6b795 MB |
330 | |
331 | /* SHM_SCRATCH offsets */ | |
332 | #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */ | |
333 | #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */ | |
334 | #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */ | |
335 | #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */ | |
336 | #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */ | |
337 | #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */ | |
338 | #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */ | |
339 | #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */ | |
340 | #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */ | |
341 | #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */ | |
342 | ||
343 | /* Hardware Radio Enable masks */ | |
344 | #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) | |
345 | #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) | |
346 | ||
347 | /* HostFlags. See b43_hf_read/write() */ | |
35f0d354 MB |
348 | #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */ |
349 | #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */ | |
350 | #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */ | |
351 | #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */ | |
352 | #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */ | |
353 | #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */ | |
354 | #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */ | |
355 | #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */ | |
356 | #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */ | |
357 | #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */ | |
358 | #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */ | |
359 | #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */ | |
360 | #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */ | |
361 | #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */ | |
362 | #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */ | |
363 | #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */ | |
364 | #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */ | |
365 | #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */ | |
366 | #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */ | |
367 | #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */ | |
368 | #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */ | |
369 | #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */ | |
370 | #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */ | |
371 | #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */ | |
372 | #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */ | |
373 | #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */ | |
374 | #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */ | |
375 | #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */ | |
376 | #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */ | |
377 | #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */ | |
378 | #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */ | |
379 | #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */ | |
380 | #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */ | |
381 | #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */ | |
382 | #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */ | |
e4d6b795 | 383 | |
403a3a13 MB |
384 | /* Firmware capabilities field in SHM (Opensource firmware only) */ |
385 | #define B43_FWCAPA_HWCRYPTO 0x0001 | |
386 | #define B43_FWCAPA_QOS 0x0002 | |
387 | ||
e4d6b795 MB |
388 | /* MacFilter offsets. */ |
389 | #define B43_MACFILTER_SELF 0x0000 | |
390 | #define B43_MACFILTER_BSSID 0x0003 | |
391 | ||
392 | /* PowerControl */ | |
393 | #define B43_PCTL_IN 0xB0 | |
394 | #define B43_PCTL_OUT 0xB4 | |
395 | #define B43_PCTL_OUTENABLE 0xB8 | |
396 | #define B43_PCTL_XTAL_POWERUP 0x40 | |
397 | #define B43_PCTL_PLL_POWERDOWN 0x80 | |
398 | ||
399 | /* PowerControl Clock Modes */ | |
400 | #define B43_PCTL_CLK_FAST 0x00 | |
401 | #define B43_PCTL_CLK_SLOW 0x01 | |
402 | #define B43_PCTL_CLK_DYNAMIC 0x02 | |
403 | ||
404 | #define B43_PCTL_FORCE_SLOW 0x0800 | |
405 | #define B43_PCTL_FORCE_PLL 0x1000 | |
406 | #define B43_PCTL_DYN_XTAL 0x2000 | |
407 | ||
408 | /* PHYVersioning */ | |
409 | #define B43_PHYTYPE_A 0x00 | |
410 | #define B43_PHYTYPE_B 0x01 | |
411 | #define B43_PHYTYPE_G 0x02 | |
d987160b MB |
412 | #define B43_PHYTYPE_N 0x04 |
413 | #define B43_PHYTYPE_LP 0x05 | |
443c1a24 RM |
414 | #define B43_PHYTYPE_SSLPN 0x06 |
415 | #define B43_PHYTYPE_HT 0x07 | |
416 | #define B43_PHYTYPE_LCN 0x08 | |
417 | #define B43_PHYTYPE_LCNXN 0x09 | |
e4d6b795 MB |
418 | |
419 | /* PHYRegisters */ | |
420 | #define B43_PHY_ILT_A_CTRL 0x0072 | |
421 | #define B43_PHY_ILT_A_DATA1 0x0073 | |
422 | #define B43_PHY_ILT_A_DATA2 0x0074 | |
423 | #define B43_PHY_G_LO_CONTROL 0x0810 | |
424 | #define B43_PHY_ILT_G_CTRL 0x0472 | |
425 | #define B43_PHY_ILT_G_DATA1 0x0473 | |
426 | #define B43_PHY_ILT_G_DATA2 0x0474 | |
427 | #define B43_PHY_A_PCTL 0x007B | |
428 | #define B43_PHY_G_PCTL 0x0029 | |
429 | #define B43_PHY_A_CRS 0x0029 | |
430 | #define B43_PHY_RADIO_BITFIELD 0x0401 | |
431 | #define B43_PHY_G_CRS 0x0429 | |
432 | #define B43_PHY_NRSSILT_CTRL 0x0803 | |
433 | #define B43_PHY_NRSSILT_DATA 0x0804 | |
434 | ||
435 | /* RadioRegisters */ | |
436 | #define B43_RADIOCTL_ID 0x01 | |
437 | ||
438 | /* MAC Control bitfield */ | |
439 | #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ | |
440 | #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ | |
441 | #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ | |
442 | #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ | |
443 | #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */ | |
444 | #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ | |
445 | #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */ | |
446 | #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */ | |
447 | #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */ | |
448 | #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ | |
449 | #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */ | |
450 | #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ | |
451 | #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ | |
452 | #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */ | |
453 | #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ | |
454 | #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ | |
455 | #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ | |
456 | #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ | |
457 | #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */ | |
458 | #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */ | |
459 | #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ | |
460 | #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */ | |
461 | #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */ | |
462 | #define B43_MACCTL_GMODE 0x80000000 /* G Mode */ | |
463 | ||
aa6c7ae2 MB |
464 | /* MAC Command bitfield */ |
465 | #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ | |
466 | #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ | |
467 | #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ | |
468 | #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ | |
469 | #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ | |
470 | ||
aa4e0141 RM |
471 | /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ |
472 | #define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */ | |
473 | #define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */ | |
474 | #define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */ | |
475 | #define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */ | |
476 | #define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */ | |
477 | #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ | |
478 | #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */ | |
479 | #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */ | |
480 | #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */ | |
481 | ||
124cc111 RM |
482 | /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ |
483 | #define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */ | |
484 | #define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */ | |
485 | #define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */ | |
486 | #define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */ | |
487 | ||
96c755a3 | 488 | /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ |
e4d6b795 | 489 | #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ |
42ab135f RM |
490 | #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ |
491 | #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ | |
492 | #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */ | |
493 | #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */ | |
96c755a3 | 494 | #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ |
e4d6b795 MB |
495 | #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ |
496 | #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ | |
497 | #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ | |
498 | ||
96c755a3 MB |
499 | /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */ |
500 | #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */ | |
e4d6b795 | 501 | #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */ |
96c755a3 MB |
502 | #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */ |
503 | #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */ | |
e4d6b795 MB |
504 | |
505 | /* Generic-Interrupt reasons. */ | |
506 | #define B43_IRQ_MAC_SUSPENDED 0x00000001 | |
507 | #define B43_IRQ_BEACON 0x00000002 | |
508 | #define B43_IRQ_TBTT_INDI 0x00000004 | |
509 | #define B43_IRQ_BEACON_TX_OK 0x00000008 | |
510 | #define B43_IRQ_BEACON_CANCEL 0x00000010 | |
511 | #define B43_IRQ_ATIM_END 0x00000020 | |
512 | #define B43_IRQ_PMQ 0x00000040 | |
513 | #define B43_IRQ_PIO_WORKAROUND 0x00000100 | |
514 | #define B43_IRQ_MAC_TXERR 0x00000200 | |
515 | #define B43_IRQ_PHY_TXERR 0x00000800 | |
516 | #define B43_IRQ_PMEVENT 0x00001000 | |
517 | #define B43_IRQ_TIMER0 0x00002000 | |
518 | #define B43_IRQ_TIMER1 0x00004000 | |
519 | #define B43_IRQ_DMA 0x00008000 | |
520 | #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000 | |
521 | #define B43_IRQ_CCA_MEASURE_OK 0x00020000 | |
522 | #define B43_IRQ_NOISESAMPLE_OK 0x00040000 | |
523 | #define B43_IRQ_UCODE_DEBUG 0x08000000 | |
524 | #define B43_IRQ_RFKILL 0x10000000 | |
525 | #define B43_IRQ_TX_OK 0x20000000 | |
526 | #define B43_IRQ_PHY_G_CHANGED 0x40000000 | |
527 | #define B43_IRQ_TIMEOUT 0x80000000 | |
528 | ||
529 | #define B43_IRQ_ALL 0xFFFFFFFF | |
e40ac414 | 530 | #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \ |
e4d6b795 MB |
531 | B43_IRQ_ATIM_END | \ |
532 | B43_IRQ_PMQ | \ | |
533 | B43_IRQ_MAC_TXERR | \ | |
534 | B43_IRQ_PHY_TXERR | \ | |
535 | B43_IRQ_DMA | \ | |
536 | B43_IRQ_TXFIFO_FLUSH_OK | \ | |
537 | B43_IRQ_NOISESAMPLE_OK | \ | |
538 | B43_IRQ_UCODE_DEBUG | \ | |
539 | B43_IRQ_RFKILL | \ | |
540 | B43_IRQ_TX_OK) | |
541 | ||
afa83e23 MB |
542 | /* The firmware register to fetch the debug-IRQ reason from. */ |
543 | #define B43_DEBUGIRQ_REASON_REG 63 | |
e48b0eeb MB |
544 | /* Debug-IRQ reasons. */ |
545 | #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */ | |
546 | #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */ | |
547 | #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */ | |
53c06856 | 548 | #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */ |
e48b0eeb MB |
549 | #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */ |
550 | ||
53c06856 MB |
551 | /* The firmware register that contains the "marker" line. */ |
552 | #define B43_MARKER_ID_REG 2 | |
553 | #define B43_MARKER_LINE_REG 3 | |
554 | ||
afa83e23 MB |
555 | /* The firmware register to fetch the panic reason from. */ |
556 | #define B43_FWPANIC_REASON_REG 3 | |
557 | /* Firmware panic reason codes */ | |
558 | #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */ | |
559 | #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */ | |
560 | ||
9b839a74 MB |
561 | /* The firmware register that contains the watchdog counter. */ |
562 | #define B43_WATCHDOG_REG 1 | |
afa83e23 | 563 | |
e4d6b795 MB |
564 | /* Device specific rate values. |
565 | * The actual values defined here are (rate_in_mbps * 2). | |
566 | * Some code depends on this. Don't change it. */ | |
567 | #define B43_CCK_RATE_1MB 0x02 | |
568 | #define B43_CCK_RATE_2MB 0x04 | |
569 | #define B43_CCK_RATE_5MB 0x0B | |
570 | #define B43_CCK_RATE_11MB 0x16 | |
571 | #define B43_OFDM_RATE_6MB 0x0C | |
572 | #define B43_OFDM_RATE_9MB 0x12 | |
573 | #define B43_OFDM_RATE_12MB 0x18 | |
574 | #define B43_OFDM_RATE_18MB 0x24 | |
575 | #define B43_OFDM_RATE_24MB 0x30 | |
576 | #define B43_OFDM_RATE_36MB 0x48 | |
577 | #define B43_OFDM_RATE_48MB 0x60 | |
578 | #define B43_OFDM_RATE_54MB 0x6C | |
579 | /* Convert a b43 rate value to a rate in 100kbps */ | |
580 | #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2) | |
581 | ||
582 | #define B43_DEFAULT_SHORT_RETRY_LIMIT 7 | |
583 | #define B43_DEFAULT_LONG_RETRY_LIMIT 4 | |
584 | ||
00e0b8cb SB |
585 | #define B43_PHY_TX_BADNESS_LIMIT 1000 |
586 | ||
e4d6b795 MB |
587 | /* Max size of a security key */ |
588 | #define B43_SEC_KEYSIZE 16 | |
66d2d089 MB |
589 | /* Max number of group keys */ |
590 | #define B43_NR_GROUP_KEYS 4 | |
591 | /* Max number of pairwise keys */ | |
592 | #define B43_NR_PAIRWISE_KEYS 50 | |
e4d6b795 MB |
593 | /* Security algorithms. */ |
594 | enum { | |
595 | B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ | |
596 | B43_SEC_ALGO_WEP40, | |
597 | B43_SEC_ALGO_TKIP, | |
598 | B43_SEC_ALGO_AES, | |
599 | B43_SEC_ALGO_WEP104, | |
600 | B43_SEC_ALGO_AES_LEGACY, | |
601 | }; | |
602 | ||
603 | struct b43_dmaring; | |
e4d6b795 MB |
604 | |
605 | /* The firmware file header */ | |
606 | #define B43_FW_TYPE_UCODE 'u' | |
607 | #define B43_FW_TYPE_PCM 'p' | |
608 | #define B43_FW_TYPE_IV 'i' | |
609 | struct b43_fw_header { | |
610 | /* File type */ | |
611 | u8 type; | |
612 | /* File format version */ | |
613 | u8 ver; | |
614 | u8 __padding[2]; | |
615 | /* Size of the data. For ucode and PCM this is in bytes. | |
616 | * For IV this is number-of-ivs. */ | |
617 | __be32 size; | |
ba2d3587 | 618 | } __packed; |
e4d6b795 MB |
619 | |
620 | /* Initial Value file format */ | |
621 | #define B43_IV_OFFSET_MASK 0x7FFF | |
622 | #define B43_IV_32BIT 0x8000 | |
623 | struct b43_iv { | |
624 | __be16 offset_size; | |
625 | union { | |
626 | __be16 d16; | |
627 | __be32 d32; | |
ba2d3587 ED |
628 | } data __packed; |
629 | } __packed; | |
e4d6b795 MB |
630 | |
631 | ||
e4d6b795 MB |
632 | /* Data structures for DMA transmission, per 80211 core. */ |
633 | struct b43_dma { | |
b27faf8e MB |
634 | struct b43_dmaring *tx_ring_AC_BK; /* Background */ |
635 | struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */ | |
636 | struct b43_dmaring *tx_ring_AC_VI; /* Video */ | |
637 | struct b43_dmaring *tx_ring_AC_VO; /* Voice */ | |
638 | struct b43_dmaring *tx_ring_mcast; /* Multicast */ | |
639 | ||
640 | struct b43_dmaring *rx_ring; | |
05100a29 RM |
641 | |
642 | u32 translation; /* Routing bits */ | |
0cc9772a | 643 | bool translation_in_low; /* Should translation bit go into low addr? */ |
78c1ee7e | 644 | bool parity; /* Check for parity */ |
e4d6b795 MB |
645 | }; |
646 | ||
5100d5ac MB |
647 | struct b43_pio_txqueue; |
648 | struct b43_pio_rxqueue; | |
649 | ||
650 | /* Data structures for PIO transmission, per 80211 core. */ | |
651 | struct b43_pio { | |
652 | struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */ | |
653 | struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */ | |
654 | struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */ | |
655 | struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */ | |
656 | struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */ | |
657 | ||
658 | struct b43_pio_rxqueue *rx_queue; | |
659 | }; | |
660 | ||
e4d6b795 MB |
661 | /* Context information for a noise calculation (Link Quality). */ |
662 | struct b43_noise_calculation { | |
e4d6b795 MB |
663 | bool calculation_running; |
664 | u8 nr_samples; | |
665 | s8 samples[8][4]; | |
666 | }; | |
667 | ||
668 | struct b43_stats { | |
669 | u8 link_noise; | |
e4d6b795 MB |
670 | }; |
671 | ||
672 | struct b43_key { | |
673 | /* If keyconf is NULL, this key is disabled. | |
674 | * keyconf is a cookie. Don't derefenrence it outside of the set_key | |
675 | * path, because b43 doesn't own it. */ | |
676 | struct ieee80211_key_conf *keyconf; | |
677 | u8 algorithm; | |
678 | }; | |
679 | ||
e6f5b934 | 680 | /* SHM offsets to the QOS data structures for the 4 different queues. */ |
bad69194 | 681 | #define B43_QOS_QUEUE_NUM 4 |
e6f5b934 MB |
682 | #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \ |
683 | (B43_NR_QOSPARAMS * sizeof(u16) * (queue))) | |
684 | #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0) | |
685 | #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1) | |
686 | #define B43_QOS_VIDEO B43_QOS_PARAMS(2) | |
687 | #define B43_QOS_VOICE B43_QOS_PARAMS(3) | |
688 | ||
689 | /* QOS parameter hardware data structure offsets. */ | |
e35cc4dd | 690 | #define B43_NR_QOSPARAMS 16 |
e6f5b934 MB |
691 | enum { |
692 | B43_QOSPARAM_TXOP = 0, | |
693 | B43_QOSPARAM_CWMIN, | |
694 | B43_QOSPARAM_CWMAX, | |
695 | B43_QOSPARAM_CWCUR, | |
696 | B43_QOSPARAM_AIFS, | |
697 | B43_QOSPARAM_BSLOTS, | |
698 | B43_QOSPARAM_REGGAP, | |
699 | B43_QOSPARAM_STATUS, | |
700 | }; | |
701 | ||
702 | /* QOS parameters for a queue. */ | |
703 | struct b43_qos_params { | |
704 | /* The QOS parameters */ | |
705 | struct ieee80211_tx_queue_params p; | |
e6f5b934 MB |
706 | }; |
707 | ||
7e937c63 | 708 | struct b43_wl; |
e4d6b795 | 709 | |
1a9f5093 MB |
710 | /* The type of the firmware file. */ |
711 | enum b43_firmware_file_type { | |
712 | B43_FWTYPE_PROPRIETARY, | |
713 | B43_FWTYPE_OPENSOURCE, | |
714 | B43_NR_FWTYPES, | |
715 | }; | |
716 | ||
717 | /* Context data for fetching firmware. */ | |
718 | struct b43_request_fw_context { | |
719 | /* The device we are requesting the fw for. */ | |
720 | struct b43_wldev *dev; | |
721 | /* The type of firmware to request. */ | |
722 | enum b43_firmware_file_type req_type; | |
723 | /* Error messages for each firmware type. */ | |
724 | char errors[B43_NR_FWTYPES][128]; | |
725 | /* Temporary buffer for storing the firmware name. */ | |
726 | char fwname[64]; | |
e64851f5 JC |
727 | /* A fatal error occurred while requesting. Firmware request |
728 | * can not continue, as any other request will also fail. */ | |
1a9f5093 MB |
729 | int fatal_failure; |
730 | }; | |
731 | ||
61cb5dd6 MB |
732 | /* In-memory representation of a cached microcode file. */ |
733 | struct b43_firmware_file { | |
734 | const char *filename; | |
735 | const struct firmware *data; | |
1a9f5093 MB |
736 | /* Type of the firmware file name. Note that this does only indicate |
737 | * the type by the firmware name. NOT the file contents. | |
738 | * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource | |
739 | * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware | |
740 | * binary code, not just the filename. | |
741 | */ | |
742 | enum b43_firmware_file_type type; | |
61cb5dd6 MB |
743 | }; |
744 | ||
efe0249b | 745 | enum b43_firmware_hdr_format { |
5d852905 | 746 | B43_FW_HDR_598, |
efe0249b RM |
747 | B43_FW_HDR_410, |
748 | B43_FW_HDR_351, | |
749 | }; | |
750 | ||
e4d6b795 MB |
751 | /* Pointers to the firmware data and meta information about it. */ |
752 | struct b43_firmware { | |
753 | /* Microcode */ | |
61cb5dd6 | 754 | struct b43_firmware_file ucode; |
e4d6b795 | 755 | /* PCM code */ |
61cb5dd6 | 756 | struct b43_firmware_file pcm; |
e4d6b795 | 757 | /* Initial MMIO values for the firmware */ |
61cb5dd6 | 758 | struct b43_firmware_file initvals; |
e4d6b795 | 759 | /* Initial MMIO values for the firmware, band-specific */ |
61cb5dd6 MB |
760 | struct b43_firmware_file initvals_band; |
761 | ||
e4d6b795 MB |
762 | /* Firmware revision */ |
763 | u16 rev; | |
764 | /* Firmware patchlevel */ | |
765 | u16 patch; | |
e48b0eeb | 766 | |
efe0249b RM |
767 | /* Format of header used by firmware */ |
768 | enum b43_firmware_hdr_format hdr_format; | |
769 | ||
1a9f5093 MB |
770 | /* Set to true, if we are using an opensource firmware. |
771 | * Use this to check for proprietary vs opensource. */ | |
e48b0eeb | 772 | bool opensource; |
68217832 MB |
773 | /* Set to true, if the core needs a PCM firmware, but |
774 | * we failed to load one. This is always false for | |
775 | * core rev > 10, as these don't need PCM firmware. */ | |
776 | bool pcm_request_failed; | |
e4d6b795 MB |
777 | }; |
778 | ||
779 | /* Device (802.11 core) initialization status. */ | |
780 | enum { | |
781 | B43_STAT_UNINIT = 0, /* Uninitialized. */ | |
782 | B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */ | |
783 | B43_STAT_STARTED = 2, /* Up and running. */ | |
784 | }; | |
785 | #define b43_status(wldev) atomic_read(&(wldev)->__init_status) | |
786 | #define b43_set_status(wldev, stat) do { \ | |
787 | atomic_set(&(wldev)->__init_status, (stat)); \ | |
788 | smp_wmb(); \ | |
789 | } while (0) | |
790 | ||
e4d6b795 MB |
791 | /* Data structure for one wireless device (802.11 core) */ |
792 | struct b43_wldev { | |
482f0538 | 793 | struct b43_bus_dev *dev; |
e4d6b795 MB |
794 | struct b43_wl *wl; |
795 | ||
796 | /* The device initialization status. | |
797 | * Use b43_status() to query. */ | |
798 | atomic_t __init_status; | |
e4d6b795 | 799 | |
e4d6b795 | 800 | bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */ |
aa6c7ae2 | 801 | bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */ |
e4d6b795 | 802 | bool radio_hw_enable; /* saved state of radio hardware enabled state */ |
403a3a13 MB |
803 | bool qos_enabled; /* TRUE, if QoS is used. */ |
804 | bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */ | |
9e3bd919 | 805 | bool use_pio; /* TRUE if next init should use PIO */ |
e4d6b795 MB |
806 | |
807 | /* PHY/Radio device. */ | |
808 | struct b43_phy phy; | |
03b29773 | 809 | |
5100d5ac MB |
810 | union { |
811 | /* DMA engines. */ | |
812 | struct b43_dma dma; | |
813 | /* PIO engines. */ | |
814 | struct b43_pio pio; | |
815 | }; | |
816 | /* Use b43_using_pio_transfers() to check whether we are using | |
817 | * DMA or PIO data transfers. */ | |
818 | bool __using_pio_transfers; | |
e4d6b795 MB |
819 | |
820 | /* Various statistics about the physical device. */ | |
821 | struct b43_stats stats; | |
822 | ||
e4d6b795 MB |
823 | /* Reason code of the last interrupt. */ |
824 | u32 irq_reason; | |
825 | u32 dma_reason[6]; | |
13790728 MB |
826 | /* The currently active generic-interrupt mask. */ |
827 | u32 irq_mask; | |
36dbd954 | 828 | |
e4d6b795 MB |
829 | /* Link Quality calculation context. */ |
830 | struct b43_noise_calculation noisecalc; | |
831 | /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ | |
832 | int mac_suspended; | |
833 | ||
e4d6b795 MB |
834 | /* Periodic tasks */ |
835 | struct delayed_work periodic_work; | |
836 | unsigned int periodic_state; | |
837 | ||
838 | struct work_struct restart_work; | |
839 | ||
840 | /* encryption/decryption */ | |
841 | u16 ktp; /* Key table pointer */ | |
66d2d089 | 842 | struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS]; |
e4d6b795 | 843 | |
e4d6b795 MB |
844 | /* Firmware data */ |
845 | struct b43_firmware fw; | |
846 | ||
847 | /* Devicelist in struct b43_wl (all 802.11 cores) */ | |
848 | struct list_head list; | |
849 | ||
850 | /* Debugging stuff follows. */ | |
851 | #ifdef CONFIG_B43_DEBUG | |
852 | struct b43_dfsentry *dfsentry; | |
990b86f4 MB |
853 | unsigned int irq_count; |
854 | unsigned int irq_bit_count[32]; | |
855 | unsigned int tx_count; | |
856 | unsigned int rx_count; | |
e4d6b795 MB |
857 | #endif |
858 | }; | |
859 | ||
7e937c63 AH |
860 | /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */ |
861 | struct b43_wl { | |
862 | /* Pointer to the active wireless device on this chip */ | |
863 | struct b43_wldev *current_dev; | |
864 | /* Pointer to the ieee80211 hardware data structure */ | |
865 | struct ieee80211_hw *hw; | |
866 | ||
867 | /* Global driver mutex. Every operation must run with this mutex locked. */ | |
868 | struct mutex mutex; | |
869 | /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ | |
870 | * handler, only. This basically is just the IRQ mask register. */ | |
871 | spinlock_t hardirq_lock; | |
872 | ||
873 | /* The number of queues that were registered with the mac80211 subsystem | |
874 | * initially. This is a backup copy of hw->queues in case hw->queues has | |
875 | * to be dynamically lowered at runtime (Firmware does not support QoS). | |
876 | * hw->queues has to be restored to the original value before unregistering | |
877 | * from the mac80211 subsystem. */ | |
878 | u16 mac80211_initially_registered_queues; | |
879 | ||
e64add27 OR |
880 | /* Set this if we call ieee80211_register_hw() and check if we call |
881 | * ieee80211_unregister_hw(). */ | |
882 | bool hw_registred; | |
883 | ||
7e937c63 AH |
884 | /* We can only have one operating interface (802.11 core) |
885 | * at a time. General information about this interface follows. | |
886 | */ | |
887 | ||
888 | struct ieee80211_vif *vif; | |
889 | /* The MAC address of the operating interface. */ | |
890 | u8 mac_addr[ETH_ALEN]; | |
891 | /* Current BSSID */ | |
892 | u8 bssid[ETH_ALEN]; | |
893 | /* Interface type. (NL80211_IFTYPE_XXX) */ | |
894 | int if_type; | |
895 | /* Is the card operating in AP, STA or IBSS mode? */ | |
896 | bool operating; | |
897 | /* filter flags */ | |
898 | unsigned int filter_flags; | |
899 | /* Stats about the wireless interface */ | |
900 | struct ieee80211_low_level_stats ieee_stats; | |
901 | ||
902 | #ifdef CONFIG_B43_HWRNG | |
903 | struct hwrng rng; | |
904 | bool rng_initialized; | |
905 | char rng_name[30 + 1]; | |
906 | #endif /* CONFIG_B43_HWRNG */ | |
907 | ||
908 | /* List of all wireless devices on this chip */ | |
909 | struct list_head devlist; | |
910 | u8 nr_devs; | |
911 | ||
912 | bool radiotap_enabled; | |
913 | bool radio_enabled; | |
914 | ||
915 | /* The beacon we are currently using (AP or IBSS mode). */ | |
916 | struct sk_buff *current_beacon; | |
917 | bool beacon0_uploaded; | |
918 | bool beacon1_uploaded; | |
919 | bool beacon_templates_virgin; /* Never wrote the templates? */ | |
920 | struct work_struct beacon_update_trigger; | |
921 | ||
922 | /* The current QOS parameters for the 4 queues. */ | |
bad69194 | 923 | struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM]; |
7e937c63 AH |
924 | |
925 | /* Work for adjustment of the transmission power. | |
926 | * This is scheduled when we determine that the actual TX output | |
927 | * power doesn't match what we want. */ | |
928 | struct work_struct txpower_adjust_work; | |
929 | ||
930 | /* Packet transmit work */ | |
931 | struct work_struct tx_work; | |
bad69194 | 932 | |
7e937c63 | 933 | /* Queue of packets to be transmitted. */ |
bad69194 | 934 | struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM]; |
935 | ||
936 | /* Flag that implement the queues stopping. */ | |
937 | bool tx_queue_stopped[B43_QOS_QUEUE_NUM]; | |
7e937c63 | 938 | |
6b6fa586 LF |
939 | /* firmware loading work */ |
940 | struct work_struct firmware_load; | |
941 | ||
7e937c63 AH |
942 | /* The device LEDs. */ |
943 | struct b43_leds leds; | |
944 | ||
88499ab3 | 945 | /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */ |
5d852905 | 946 | u8 pio_scratchspace[118] __attribute__((__aligned__(8))); |
88499ab3 | 947 | u8 pio_tailspace[4] __attribute__((__aligned__(8))); |
7e937c63 AH |
948 | }; |
949 | ||
e4d6b795 MB |
950 | static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw) |
951 | { | |
952 | return hw->priv; | |
953 | } | |
954 | ||
e4d6b795 MB |
955 | static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev) |
956 | { | |
957 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
958 | return ssb_get_drvdata(ssb_dev); | |
959 | } | |
960 | ||
bedaf808 | 961 | /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */ |
e4d6b795 MB |
962 | static inline int b43_is_mode(struct b43_wl *wl, int type) |
963 | { | |
e4d6b795 MB |
964 | return (wl->operating && wl->if_type == type); |
965 | } | |
966 | ||
ef1a628d MB |
967 | /** |
968 | * b43_current_band - Returns the currently used band. | |
969 | * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ. | |
970 | */ | |
971 | static inline enum ieee80211_band b43_current_band(struct b43_wl *wl) | |
972 | { | |
973 | return wl->hw->conf.channel->band; | |
974 | } | |
975 | ||
24ca39d6 RM |
976 | static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) |
977 | { | |
978 | return wldev->dev->bus_may_powerdown(wldev->dev); | |
979 | } | |
980 | static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl) | |
981 | { | |
982 | return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl); | |
983 | } | |
984 | static inline int b43_device_is_enabled(struct b43_wldev *wldev) | |
985 | { | |
986 | return wldev->dev->device_is_enabled(wldev->dev); | |
987 | } | |
988 | static inline void b43_device_enable(struct b43_wldev *wldev, | |
989 | u32 core_specific_flags) | |
990 | { | |
991 | wldev->dev->device_enable(wldev->dev, core_specific_flags); | |
992 | } | |
993 | static inline void b43_device_disable(struct b43_wldev *wldev, | |
994 | u32 core_specific_flags) | |
995 | { | |
996 | wldev->dev->device_disable(wldev->dev, core_specific_flags); | |
997 | } | |
998 | ||
e4d6b795 MB |
999 | static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) |
1000 | { | |
c0b4c009 | 1001 | return dev->dev->read16(dev->dev, offset); |
e4d6b795 MB |
1002 | } |
1003 | ||
1004 | static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) | |
1005 | { | |
c0b4c009 | 1006 | dev->dev->write16(dev->dev, offset, value); |
e4d6b795 MB |
1007 | } |
1008 | ||
5056635c RM |
1009 | static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask, |
1010 | u16 set) | |
1011 | { | |
1012 | b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set); | |
1013 | } | |
1014 | ||
e4d6b795 MB |
1015 | static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) |
1016 | { | |
c0b4c009 | 1017 | return dev->dev->read32(dev->dev, offset); |
e4d6b795 MB |
1018 | } |
1019 | ||
1020 | static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) | |
1021 | { | |
c0b4c009 | 1022 | dev->dev->write32(dev->dev, offset, value); |
e4d6b795 MB |
1023 | } |
1024 | ||
5056635c RM |
1025 | static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask, |
1026 | u32 set) | |
1027 | { | |
1028 | b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set); | |
1029 | } | |
1030 | ||
620d785b RM |
1031 | static inline void b43_block_read(struct b43_wldev *dev, void *buffer, |
1032 | size_t count, u16 offset, u8 reg_width) | |
1033 | { | |
c0b4c009 | 1034 | dev->dev->block_read(dev->dev, buffer, count, offset, reg_width); |
620d785b RM |
1035 | } |
1036 | ||
1037 | static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, | |
1038 | size_t count, u16 offset, u8 reg_width) | |
1039 | { | |
c0b4c009 | 1040 | dev->dev->block_write(dev->dev, buffer, count, offset, reg_width); |
e4d6b795 MB |
1041 | } |
1042 | ||
5100d5ac MB |
1043 | static inline bool b43_using_pio_transfers(struct b43_wldev *dev) |
1044 | { | |
5100d5ac | 1045 | return dev->__using_pio_transfers; |
5100d5ac MB |
1046 | } |
1047 | ||
e4d6b795 | 1048 | /* Message printing */ |
b9075fa9 JP |
1049 | __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...); |
1050 | __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...); | |
1051 | __printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...); | |
1052 | __printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...); | |
060210f9 | 1053 | |
e4d6b795 MB |
1054 | |
1055 | /* A WARN_ON variant that vanishes when b43 debugging is disabled. | |
1056 | * This _also_ evaluates the arg with debugging disabled. */ | |
1057 | #if B43_DEBUG | |
1058 | # define B43_WARN_ON(x) WARN_ON(x) | |
1059 | #else | |
1060 | static inline bool __b43_warn_on_dummy(bool x) { return x; } | |
1061 | # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x))) | |
1062 | #endif | |
1063 | ||
e4d6b795 MB |
1064 | /* Convert an integer to a Q5.2 value */ |
1065 | #define INT_TO_Q52(i) ((i) << 2) | |
1066 | /* Convert a Q5.2 value to an integer (precision loss!) */ | |
1067 | #define Q52_TO_INT(q52) ((q52) >> 2) | |
1068 | /* Macros for printing a value in Q5.2 format */ | |
1069 | #define Q52_FMT "%u.%u" | |
1070 | #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4) | |
1071 | ||
1072 | #endif /* B43_H_ */ |