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iwlwifi: Eliminate association from beacon
[deliverable/linux.git] / drivers / net / wireless / b43 / dma.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
280d0e16 40#include <linux/etherdevice.h>
57df40d2 41#include <asm/div64.h>
280d0e16 42
e4d6b795
MB		 43
44/* 32bit DMA ops. */
45static
46struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
47 int slot,
48 struct b43_dmadesc_meta **meta)
49{
50 struct b43_dmadesc32 *desc;
51
52 *meta = &(ring->meta[slot]);
53 desc = ring->descbase;
54 desc = &(desc[slot]);
55
56 return (struct b43_dmadesc_generic *)desc;
57}
58
59static void op32_fill_descriptor(struct b43_dmaring *ring,
60 struct b43_dmadesc_generic *desc,
61 dma_addr_t dmaaddr, u16 bufsize,
62 int start, int end, int irq)
63{
64 struct b43_dmadesc32 *descbase = ring->descbase;
65 int slot;
66 u32 ctl;
67 u32 addr;
68 u32 addrext;
69
70 slot = (int)(&(desc->dma32) - descbase);
71 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
72
73 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
74 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
75 >> SSB_DMA_TRANSLATION_SHIFT;
76 addr |= ssb_dma_translation(ring->dev->dev);
77 ctl = (bufsize - ring->frameoffset)
78 & B43_DMA32_DCTL_BYTECNT;
79 if (slot == ring->nr_slots - 1)
80 ctl |= B43_DMA32_DCTL_DTABLEEND;
81 if (start)
82 ctl |= B43_DMA32_DCTL_FRAMESTART;
83 if (end)
84 ctl |= B43_DMA32_DCTL_FRAMEEND;
85 if (irq)
86 ctl |= B43_DMA32_DCTL_IRQ;
87 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
88 & B43_DMA32_DCTL_ADDREXT_MASK;
89
90 desc->dma32.control = cpu_to_le32(ctl);
91 desc->dma32.address = cpu_to_le32(addr);
92}
93
94static void op32_poke_tx(struct b43_dmaring *ring, int slot)
95{
96 b43_dma_write(ring, B43_DMA32_TXINDEX,
97 (u32) (slot * sizeof(struct b43_dmadesc32)));
98}
99
100static void op32_tx_suspend(struct b43_dmaring *ring)
101{
102 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
103 | B43_DMA32_TXSUSPEND);
104}
105
106static void op32_tx_resume(struct b43_dmaring *ring)
107{
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 & ~B43_DMA32_TXSUSPEND);
110}
111
112static int op32_get_current_rxslot(struct b43_dmaring *ring)
113{
114 u32 val;
115
116 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
117 val &= B43_DMA32_RXDPTR;
118
119 return (val / sizeof(struct b43_dmadesc32));
120}
121
122static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
123{
124 b43_dma_write(ring, B43_DMA32_RXINDEX,
125 (u32) (slot * sizeof(struct b43_dmadesc32)));
126}
127
128static const struct b43_dma_ops dma32_ops = {
129 .idx2desc = op32_idx2desc,
130 .fill_descriptor = op32_fill_descriptor,
131 .poke_tx = op32_poke_tx,
132 .tx_suspend = op32_tx_suspend,
133 .tx_resume = op32_tx_resume,
134 .get_current_rxslot = op32_get_current_rxslot,
135 .set_current_rxslot = op32_set_current_rxslot,
136};
137
138/* 64bit DMA ops. */
139static
140struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
141 int slot,
142 struct b43_dmadesc_meta **meta)
143{
144 struct b43_dmadesc64 *desc;
145
146 *meta = &(ring->meta[slot]);
147 desc = ring->descbase;
148 desc = &(desc[slot]);
149
150 return (struct b43_dmadesc_generic *)desc;
151}
152
153static void op64_fill_descriptor(struct b43_dmaring *ring,
154 struct b43_dmadesc_generic *desc,
155 dma_addr_t dmaaddr, u16 bufsize,
156 int start, int end, int irq)
157{
158 struct b43_dmadesc64 *descbase = ring->descbase;
159 int slot;
160 u32 ctl0 = 0, ctl1 = 0;
161 u32 addrlo, addrhi;
162 u32 addrext;
163
164 slot = (int)(&(desc->dma64) - descbase);
165 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
166
167 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
168 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
169 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
170 >> SSB_DMA_TRANSLATION_SHIFT;
013978b6 171 addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
e4d6b795
MB		 172 if (slot == ring->nr_slots - 1)
173 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
174 if (start)
175 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
176 if (end)
177 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
178 if (irq)
179 ctl0 |= B43_DMA64_DCTL0_IRQ;
180 ctl1 |= (bufsize - ring->frameoffset)
181 & B43_DMA64_DCTL1_BYTECNT;
182 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
183 & B43_DMA64_DCTL1_ADDREXT_MASK;
184
185 desc->dma64.control0 = cpu_to_le32(ctl0);
186 desc->dma64.control1 = cpu_to_le32(ctl1);
187 desc->dma64.address_low = cpu_to_le32(addrlo);
188 desc->dma64.address_high = cpu_to_le32(addrhi);
189}
190
191static void op64_poke_tx(struct b43_dmaring *ring, int slot)
192{
193 b43_dma_write(ring, B43_DMA64_TXINDEX,
194 (u32) (slot * sizeof(struct b43_dmadesc64)));
195}
196
197static void op64_tx_suspend(struct b43_dmaring *ring)
198{
199 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
200 | B43_DMA64_TXSUSPEND);
201}
202
203static void op64_tx_resume(struct b43_dmaring *ring)
204{
205 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
206 & ~B43_DMA64_TXSUSPEND);
207}
208
209static int op64_get_current_rxslot(struct b43_dmaring *ring)
210{
211 u32 val;
212
213 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
214 val &= B43_DMA64_RXSTATDPTR;
215
216 return (val / sizeof(struct b43_dmadesc64));
217}
218
219static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
220{
221 b43_dma_write(ring, B43_DMA64_RXINDEX,
222 (u32) (slot * sizeof(struct b43_dmadesc64)));
223}
224
225static const struct b43_dma_ops dma64_ops = {
226 .idx2desc = op64_idx2desc,
227 .fill_descriptor = op64_fill_descriptor,
228 .poke_tx = op64_poke_tx,
229 .tx_suspend = op64_tx_suspend,
230 .tx_resume = op64_tx_resume,
231 .get_current_rxslot = op64_get_current_rxslot,
232 .set_current_rxslot = op64_set_current_rxslot,
233};
234
235static inline int free_slots(struct b43_dmaring *ring)
236{
237 return (ring->nr_slots - ring->used_slots);
238}
239
240static inline int next_slot(struct b43_dmaring *ring, int slot)
241{
242 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
243 if (slot == ring->nr_slots - 1)
244 return 0;
245 return slot + 1;
246}
247
248static inline int prev_slot(struct b43_dmaring *ring, int slot)
249{
250 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
251 if (slot == 0)
252 return ring->nr_slots - 1;
253 return slot - 1;
254}
255
256#ifdef CONFIG_B43_DEBUG
257static void update_max_used_slots(struct b43_dmaring *ring,
258 int current_used_slots)
259{
260 if (current_used_slots <= ring->max_used_slots)
261 return;
262 ring->max_used_slots = current_used_slots;
263 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
264 b43dbg(ring->dev->wl,
265 "max_used_slots increased to %d on %s ring %d\n",
266 ring->max_used_slots,
267 ring->tx ? "TX" : "RX", ring->index);
268 }
269}
270#else
271static inline
272 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
273{
274}
275#endif /* DEBUG */
276
277/* Request a slot for usage. */
278static inline int request_slot(struct b43_dmaring *ring)
279{
280 int slot;
281
282 B43_WARN_ON(!ring->tx);
283 B43_WARN_ON(ring->stopped);
284 B43_WARN_ON(free_slots(ring) == 0);
285
286 slot = next_slot(ring, ring->current_slot);
287 ring->current_slot = slot;
288 ring->used_slots++;
289
290 update_max_used_slots(ring, ring->used_slots);
291
292 return slot;
293}
294
b79caa68 295static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
e4d6b795
MB		 296{
297 static const u16 map64[] = {
298 B43_MMIO_DMA64_BASE0,
299 B43_MMIO_DMA64_BASE1,
300 B43_MMIO_DMA64_BASE2,
301 B43_MMIO_DMA64_BASE3,
302 B43_MMIO_DMA64_BASE4,
303 B43_MMIO_DMA64_BASE5,
304 };
305 static const u16 map32[] = {
306 B43_MMIO_DMA32_BASE0,
307 B43_MMIO_DMA32_BASE1,
308 B43_MMIO_DMA32_BASE2,
309 B43_MMIO_DMA32_BASE3,
310 B43_MMIO_DMA32_BASE4,
311 B43_MMIO_DMA32_BASE5,
312 };
313
b79caa68 314 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 315 B43_WARN_ON(!(controller_idx >= 0 &&
316 controller_idx < ARRAY_SIZE(map64)));
317 return map64[controller_idx];
318 }
319 B43_WARN_ON(!(controller_idx >= 0 &&
320 controller_idx < ARRAY_SIZE(map32)));
321 return map32[controller_idx];
322}
323
324static inline
325 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
326 unsigned char *buf, size_t len, int tx)
327{
328 dma_addr_t dmaaddr;
329
330 if (tx) {
331 dmaaddr = dma_map_single(ring->dev->dev->dev,
332 buf, len, DMA_TO_DEVICE);
333 } else {
334 dmaaddr = dma_map_single(ring->dev->dev->dev,
335 buf, len, DMA_FROM_DEVICE);
336 }
337
338 return dmaaddr;
339}
340
341static inline
342 void unmap_descbuffer(struct b43_dmaring *ring,
343 dma_addr_t addr, size_t len, int tx)
344{
345 if (tx) {
346 dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
347 } else {
348 dma_unmap_single(ring->dev->dev->dev,
349 addr, len, DMA_FROM_DEVICE);
350 }
351}
352
353static inline
354 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
355 dma_addr_t addr, size_t len)
356{
357 B43_WARN_ON(ring->tx);
358 dma_sync_single_for_cpu(ring->dev->dev->dev,
359 addr, len, DMA_FROM_DEVICE);
360}
361
362static inline
363 void sync_descbuffer_for_device(struct b43_dmaring *ring,
364 dma_addr_t addr, size_t len)
365{
366 B43_WARN_ON(ring->tx);
367 dma_sync_single_for_device(ring->dev->dev->dev,
368 addr, len, DMA_FROM_DEVICE);
369}
370
371static inline
372 void free_descriptor_buffer(struct b43_dmaring *ring,
373 struct b43_dmadesc_meta *meta)
374{
375 if (meta->skb) {
376 dev_kfree_skb_any(meta->skb);
377 meta->skb = NULL;
378 }
379}
380
381static int alloc_ringmemory(struct b43_dmaring *ring)
382{
383 struct device *dev = ring->dev->dev->dev;
013978b6
LF		 384 gfp_t flags = GFP_KERNEL;
385
386 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
387 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
388 * has shown that 4K is sufficient for the latter as long as the buffer
389 * does not cross an 8K boundary.
390 *
391 * For unknown reasons - possibly a hardware error - the BCM4311 rev
392 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
393 * which accounts for the GFP_DMA flag below.
394 */
b79caa68 395 if (ring->type == B43_DMA_64BIT)
013978b6 396 flags |= GFP_DMA;
e4d6b795 397 ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
013978b6 398 &(ring->dmabase), flags);
e4d6b795
MB		 399 if (!ring->descbase) {
400 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
401 return -ENOMEM;
402 }
403 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
404
405 return 0;
406}
407
408static void free_ringmemory(struct b43_dmaring *ring)
409{
410 struct device *dev = ring->dev->dev->dev;
411
412 dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
413 ring->descbase, ring->dmabase);
414}
415
416/* Reset the RX DMA channel */
b79caa68
MB		 417static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
418 enum b43_dmatype type)
e4d6b795
MB		 419{
420 int i;
421 u32 value;
422 u16 offset;
423
424 might_sleep();
425
b79caa68 426 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
e4d6b795
MB		 427 b43_write32(dev, mmio_base + offset, 0);
428 for (i = 0; i < 10; i++) {
b79caa68
MB		 429 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
430 B43_DMA32_RXSTATUS;
e4d6b795 431 value = b43_read32(dev, mmio_base + offset);
b79caa68 432 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 433 value &= B43_DMA64_RXSTAT;
434 if (value == B43_DMA64_RXSTAT_DISABLED) {
435 i = -1;
436 break;
437 }
438 } else {
439 value &= B43_DMA32_RXSTATE;
440 if (value == B43_DMA32_RXSTAT_DISABLED) {
441 i = -1;
442 break;
443 }
444 }
445 msleep(1);
446 }
447 if (i != -1) {
448 b43err(dev->wl, "DMA RX reset timed out\n");
449 return -ENODEV;
450 }
451
452 return 0;
453}
454
013978b6 455/* Reset the TX DMA channel */
b79caa68
MB		 456static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
457 enum b43_dmatype type)
e4d6b795
MB		 458{
459 int i;
460 u32 value;
461 u16 offset;
462
463 might_sleep();
464
465 for (i = 0; i < 10; i++) {
b79caa68
MB		 466 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
467 B43_DMA32_TXSTATUS;
e4d6b795 468 value = b43_read32(dev, mmio_base + offset);
b79caa68 469 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 470 value &= B43_DMA64_TXSTAT;
471 if (value == B43_DMA64_TXSTAT_DISABLED ||
472 value == B43_DMA64_TXSTAT_IDLEWAIT ||
473 value == B43_DMA64_TXSTAT_STOPPED)
474 break;
475 } else {
476 value &= B43_DMA32_TXSTATE;
477 if (value == B43_DMA32_TXSTAT_DISABLED ||
478 value == B43_DMA32_TXSTAT_IDLEWAIT ||
479 value == B43_DMA32_TXSTAT_STOPPED)
480 break;
481 }
482 msleep(1);
483 }
b79caa68 484 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
e4d6b795
MB		 485 b43_write32(dev, mmio_base + offset, 0);
486 for (i = 0; i < 10; i++) {
b79caa68
MB		 487 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
488 B43_DMA32_TXSTATUS;
e4d6b795 489 value = b43_read32(dev, mmio_base + offset);
b79caa68 490 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 491 value &= B43_DMA64_TXSTAT;
492 if (value == B43_DMA64_TXSTAT_DISABLED) {
493 i = -1;
494 break;
495 }
496 } else {
497 value &= B43_DMA32_TXSTATE;
498 if (value == B43_DMA32_TXSTAT_DISABLED) {
499 i = -1;
500 break;
501 }
502 }
503 msleep(1);
504 }
505 if (i != -1) {
506 b43err(dev->wl, "DMA TX reset timed out\n");
507 return -ENODEV;
508 }
509 /* ensure the reset is completed. */
510 msleep(1);
511
512 return 0;
513}
514
b79caa68
MB		 515/* Check if a DMA mapping address is invalid. */
516static bool b43_dma_mapping_error(struct b43_dmaring *ring,
517 dma_addr_t addr,
ffa9256a 518 size_t buffersize, bool dma_to_device)
b79caa68
MB		 519{
520 if (unlikely(dma_mapping_error(addr)))
521 return 1;
522
523 switch (ring->type) {
524 case B43_DMA_30BIT:
525 if ((u64)addr + buffersize > (1ULL << 30))
ffa9256a 526 goto address_error;
b79caa68
MB		 527 break;
528 case B43_DMA_32BIT:
529 if ((u64)addr + buffersize > (1ULL << 32))
ffa9256a 530 goto address_error;
b79caa68
MB		 531 break;
532 case B43_DMA_64BIT:
533 /* Currently we can't have addresses beyond
534 * 64bit in the kernel. */
535 break;
536 }
537
538 /* The address is OK. */
539 return 0;
ffa9256a
MB		 540
541address_error:
542 /* We can't support this address. Unmap it again. */
543 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
544
545 return 1;
b79caa68
MB		 546}
547
e4d6b795
MB		 548static int setup_rx_descbuffer(struct b43_dmaring *ring,
549 struct b43_dmadesc_generic *desc,
550 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
551{
552 struct b43_rxhdr_fw4 *rxhdr;
553 struct b43_hwtxstatus *txstat;
554 dma_addr_t dmaaddr;
555 struct sk_buff *skb;
556
557 B43_WARN_ON(ring->tx);
558
559 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
560 if (unlikely(!skb))
561 return -ENOMEM;
562 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
ffa9256a 563 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
e4d6b795
MB		 564 /* ugh. try to realloc in zone_dma */
565 gfp_flags |= GFP_DMA;
566
567 dev_kfree_skb_any(skb);
568
569 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
570 if (unlikely(!skb))
571 return -ENOMEM;
572 dmaaddr = map_descbuffer(ring, skb->data,
573 ring->rx_buffersize, 0);
574 }
575
ffa9256a 576 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
539e6f8c 577 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
e4d6b795
MB		 578 dev_kfree_skb_any(skb);
579 return -EIO;
580 }
581
582 meta->skb = skb;
583 meta->dmaaddr = dmaaddr;
584 ring->ops->fill_descriptor(ring, desc, dmaaddr,
585 ring->rx_buffersize, 0, 0, 0);
586
587 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
588 rxhdr->frame_len = 0;
589 txstat = (struct b43_hwtxstatus *)(skb->data);
590 txstat->cookie = 0;
591
592 return 0;
593}
594
595/* Allocate the initial descbuffers.
596 * This is used for an RX ring only.
597 */
598static int alloc_initial_descbuffers(struct b43_dmaring *ring)
599{
600 int i, err = -ENOMEM;
601 struct b43_dmadesc_generic *desc;
602 struct b43_dmadesc_meta *meta;
603
604 for (i = 0; i < ring->nr_slots; i++) {
605 desc = ring->ops->idx2desc(ring, i, &meta);
606
607 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
608 if (err) {
609 b43err(ring->dev->wl,
610 "Failed to allocate initial descbuffers\n");
611 goto err_unwind;
612 }
613 }
614 mb();
615 ring->used_slots = ring->nr_slots;
616 err = 0;
617 out:
618 return err;
619
620 err_unwind:
621 for (i--; i >= 0; i--) {
622 desc = ring->ops->idx2desc(ring, i, &meta);
623
624 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
625 dev_kfree_skb(meta->skb);
626 }
627 goto out;
628}
629
630/* Do initial setup of the DMA controller.
631 * Reset the controller, write the ring busaddress
632 * and switch the "enable" bit on.
633 */
634static int dmacontroller_setup(struct b43_dmaring *ring)
635{
636 int err = 0;
637 u32 value;
638 u32 addrext;
639 u32 trans = ssb_dma_translation(ring->dev->dev);
640
641 if (ring->tx) {
b79caa68 642 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 643 u64 ringbase = (u64) (ring->dmabase);
644
645 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
646 >> SSB_DMA_TRANSLATION_SHIFT;
647 value = B43_DMA64_TXENABLE;
648 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
649 & B43_DMA64_TXADDREXT_MASK;
650 b43_dma_write(ring, B43_DMA64_TXCTL, value);
651 b43_dma_write(ring, B43_DMA64_TXRINGLO,
652 (ringbase & 0xFFFFFFFF));
653 b43_dma_write(ring, B43_DMA64_TXRINGHI,
654 ((ringbase >> 32) &
655 ~SSB_DMA_TRANSLATION_MASK)
013978b6 656 | (trans << 1));
e4d6b795
MB		 657 } else {
658 u32 ringbase = (u32) (ring->dmabase);
659
660 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
661 >> SSB_DMA_TRANSLATION_SHIFT;
662 value = B43_DMA32_TXENABLE;
663 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
664 & B43_DMA32_TXADDREXT_MASK;
665 b43_dma_write(ring, B43_DMA32_TXCTL, value);
666 b43_dma_write(ring, B43_DMA32_TXRING,
667 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
668 | trans);
669 }
670 } else {
671 err = alloc_initial_descbuffers(ring);
672 if (err)
673 goto out;
b79caa68 674 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 675 u64 ringbase = (u64) (ring->dmabase);
676
677 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
678 >> SSB_DMA_TRANSLATION_SHIFT;
679 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
680 value |= B43_DMA64_RXENABLE;
681 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
682 & B43_DMA64_RXADDREXT_MASK;
683 b43_dma_write(ring, B43_DMA64_RXCTL, value);
684 b43_dma_write(ring, B43_DMA64_RXRINGLO,
685 (ringbase & 0xFFFFFFFF));
686 b43_dma_write(ring, B43_DMA64_RXRINGHI,
687 ((ringbase >> 32) &
688 ~SSB_DMA_TRANSLATION_MASK)
013978b6
LF		 689 | (trans << 1));
690 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
691 sizeof(struct b43_dmadesc64));
e4d6b795
MB		 692 } else {
693 u32 ringbase = (u32) (ring->dmabase);
694
695 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
696 >> SSB_DMA_TRANSLATION_SHIFT;
697 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
698 value |= B43_DMA32_RXENABLE;
699 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
700 & B43_DMA32_RXADDREXT_MASK;
701 b43_dma_write(ring, B43_DMA32_RXCTL, value);
702 b43_dma_write(ring, B43_DMA32_RXRING,
703 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
704 | trans);
013978b6
LF		 705 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
706 sizeof(struct b43_dmadesc32));
e4d6b795
MB		 707 }
708 }
709
013978b6 710out:
e4d6b795
MB		 711 return err;
712}
713
714/* Shutdown the DMA controller. */
715static void dmacontroller_cleanup(struct b43_dmaring *ring)
716{
717 if (ring->tx) {
718 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 719 ring->type);
720 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 721 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
722 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
723 } else
724 b43_dma_write(ring, B43_DMA32_TXRING, 0);
725 } else {
726 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 727 ring->type);
728 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 729 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
730 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
731 } else
732 b43_dma_write(ring, B43_DMA32_RXRING, 0);
733 }
734}
735
736static void free_all_descbuffers(struct b43_dmaring *ring)
737{
738 struct b43_dmadesc_generic *desc;
739 struct b43_dmadesc_meta *meta;
740 int i;
741
742 if (!ring->used_slots)
743 return;
744 for (i = 0; i < ring->nr_slots; i++) {
745 desc = ring->ops->idx2desc(ring, i, &meta);
746
747 if (!meta->skb) {
748 B43_WARN_ON(!ring->tx);
749 continue;
750 }
751 if (ring->tx) {
752 unmap_descbuffer(ring, meta->dmaaddr,
753 meta->skb->len, 1);
754 } else {
755 unmap_descbuffer(ring, meta->dmaaddr,
756 ring->rx_buffersize, 0);
757 }
758 free_descriptor_buffer(ring, meta);
759 }
760}
761
762static u64 supported_dma_mask(struct b43_wldev *dev)
763{
764 u32 tmp;
765 u16 mmio_base;
766
767 tmp = b43_read32(dev, SSB_TMSHIGH);
768 if (tmp & SSB_TMSHIGH_DMA64)
769 return DMA_64BIT_MASK;
770 mmio_base = b43_dmacontroller_base(0, 0);
771 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
772 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
773 if (tmp & B43_DMA32_TXADDREXT_MASK)
774 return DMA_32BIT_MASK;
775
776 return DMA_30BIT_MASK;
777}
778
779/* Main initialization function. */
780static
781struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
782 int controller_index,
b79caa68
MB		 783 int for_tx,
784 enum b43_dmatype type)
e4d6b795
MB		 785{
786 struct b43_dmaring *ring;
787 int err;
788 int nr_slots;
789 dma_addr_t dma_test;
790
791 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
792 if (!ring)
793 goto out;
b79caa68 794 ring->type = type;
e4d6b795
MB		 795
796 nr_slots = B43_RXRING_SLOTS;
797 if (for_tx)
798 nr_slots = B43_TXRING_SLOTS;
799
800 ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
801 GFP_KERNEL);
802 if (!ring->meta)
803 goto err_kfree_ring;
804 if (for_tx) {
805 ring->txhdr_cache = kcalloc(nr_slots,
eb189d8b 806 b43_txhdr_size(dev),
e4d6b795
MB		 807 GFP_KERNEL);
808 if (!ring->txhdr_cache)
809 goto err_kfree_meta;
810
811 /* test for ability to dma to txhdr_cache */
812 dma_test = dma_map_single(dev->dev->dev,
813 ring->txhdr_cache,
eb189d8b 814 b43_txhdr_size(dev),
e4d6b795
MB		 815 DMA_TO_DEVICE);
816
ffa9256a
MB		 817 if (b43_dma_mapping_error(ring, dma_test,
818 b43_txhdr_size(dev), 1)) {
e4d6b795
MB		 819 /* ugh realloc */
820 kfree(ring->txhdr_cache);
821 ring->txhdr_cache = kcalloc(nr_slots,
eb189d8b 822 b43_txhdr_size(dev),
e4d6b795
MB		 823 GFP_KERNEL | GFP_DMA);
824 if (!ring->txhdr_cache)
825 goto err_kfree_meta;
826
827 dma_test = dma_map_single(dev->dev->dev,
828 ring->txhdr_cache,
eb189d8b 829 b43_txhdr_size(dev),
e4d6b795
MB		 830 DMA_TO_DEVICE);
831
b79caa68 832 if (b43_dma_mapping_error(ring, dma_test,
539e6f8c
MB		 833 b43_txhdr_size(dev), 1)) {
834
835 b43err(dev->wl,
836 "TXHDR DMA allocation failed\n");
e4d6b795 837 goto err_kfree_txhdr_cache;
539e6f8c 838 }
e4d6b795
MB		 839 }
840
841 dma_unmap_single(dev->dev->dev,
eb189d8b 842 dma_test, b43_txhdr_size(dev),
e4d6b795
MB		 843 DMA_TO_DEVICE);
844 }
845
846 ring->dev = dev;
847 ring->nr_slots = nr_slots;
b79caa68 848 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
e4d6b795 849 ring->index = controller_index;
b79caa68 850 if (type == B43_DMA_64BIT)
e4d6b795
MB		 851 ring->ops = &dma64_ops;
852 else
853 ring->ops = &dma32_ops;
854 if (for_tx) {
855 ring->tx = 1;
856 ring->current_slot = -1;
857 } else {
858 if (ring->index == 0) {
859 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
860 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
861 } else if (ring->index == 3) {
862 ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
863 ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
864 } else
865 B43_WARN_ON(1);
866 }
867 spin_lock_init(&ring->lock);
868#ifdef CONFIG_B43_DEBUG
869 ring->last_injected_overflow = jiffies;
870#endif
871
872 err = alloc_ringmemory(ring);
873 if (err)
874 goto err_kfree_txhdr_cache;
875 err = dmacontroller_setup(ring);
876 if (err)
877 goto err_free_ringmemory;
878
879 out:
880 return ring;
881
882 err_free_ringmemory:
883 free_ringmemory(ring);
884 err_kfree_txhdr_cache:
885 kfree(ring->txhdr_cache);
886 err_kfree_meta:
887 kfree(ring->meta);
888 err_kfree_ring:
889 kfree(ring);
890 ring = NULL;
891 goto out;
892}
893
57df40d2
MB		 894#define divide(a, b) ({ \
895 typeof(a) __a = a; \
896 do_div(__a, b); \
897 __a; \
898 })
899
900#define modulo(a, b) ({ \
901 typeof(a) __a = a; \
902 do_div(__a, b); \
903 })
904
e4d6b795 905/* Main cleanup function. */
b27faf8e
MB		 906static void b43_destroy_dmaring(struct b43_dmaring *ring,
907 const char *ringname)
e4d6b795
MB		 908{
909 if (!ring)
910 return;
911
57df40d2
MB		 912#ifdef CONFIG_B43_DEBUG
913 {
914 /* Print some statistics. */
915 u64 failed_packets = ring->nr_failed_tx_packets;
916 u64 succeed_packets = ring->nr_succeed_tx_packets;
917 u64 nr_packets = failed_packets + succeed_packets;
918 u64 permille_failed = 0, average_tries = 0;
919
920 if (nr_packets)
921 permille_failed = divide(failed_packets * 1000, nr_packets);
922 if (nr_packets)
923 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
924
925 b43dbg(ring->dev->wl, "DMA-%u %s: "
926 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
927 "Average tries %llu.%02llu\n",
928 (unsigned int)(ring->type), ringname,
929 ring->max_used_slots,
930 ring->nr_slots,
931 (unsigned long long)failed_packets,
87d96114 932 (unsigned long long)nr_packets,
57df40d2
MB		 933 (unsigned long long)divide(permille_failed, 10),
934 (unsigned long long)modulo(permille_failed, 10),
935 (unsigned long long)divide(average_tries, 100),
936 (unsigned long long)modulo(average_tries, 100));
937 }
938#endif /* DEBUG */
939
e4d6b795
MB		 940 /* Device IRQs are disabled prior entering this function,
941 * so no need to take care of concurrency with rx handler stuff.
942 */
943 dmacontroller_cleanup(ring);
944 free_all_descbuffers(ring);
945 free_ringmemory(ring);
946
947 kfree(ring->txhdr_cache);
948 kfree(ring->meta);
949 kfree(ring);
950}
951
b27faf8e
MB		 952#define destroy_ring(dma, ring) do { \
953 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
954 (dma)->ring = NULL; \
955 } while (0)
956
e4d6b795
MB		 957void b43_dma_free(struct b43_wldev *dev)
958{
03b29773 959 struct b43_dma *dma = &dev->dma;
e4d6b795 960
b27faf8e
MB		 961 destroy_ring(dma, rx_ring);
962 destroy_ring(dma, tx_ring_AC_BK);
963 destroy_ring(dma, tx_ring_AC_BE);
964 destroy_ring(dma, tx_ring_AC_VI);
965 destroy_ring(dma, tx_ring_AC_VO);
966 destroy_ring(dma, tx_ring_mcast);
e4d6b795
MB		 967}
968
969int b43_dma_init(struct b43_wldev *dev)
970{
971 struct b43_dma *dma = &dev->dma;
e4d6b795
MB		 972 int err;
973 u64 dmamask;
b79caa68 974 enum b43_dmatype type;
e4d6b795
MB		 975
976 dmamask = supported_dma_mask(dev);
b79caa68
MB		 977 switch (dmamask) {
978 default:
979 B43_WARN_ON(1);
980 case DMA_30BIT_MASK:
981 type = B43_DMA_30BIT;
982 break;
983 case DMA_32BIT_MASK:
984 type = B43_DMA_32BIT;
985 break;
986 case DMA_64BIT_MASK:
987 type = B43_DMA_64BIT;
988 break;
989 }
e4d6b795
MB		 990 err = ssb_dma_set_mask(dev->dev, dmamask);
991 if (err) {
03b29773
MB		 992 b43err(dev->wl, "The machine/kernel does not support "
993 "the required DMA mask (0x%08X%08X)\n",
994 (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32),
995 (unsigned int)(dmamask & 0x00000000FFFFFFFFULL));
e4d6b795 996 return -EOPNOTSUPP;
e4d6b795
MB		 997 }
998
999 err = -ENOMEM;
1000 /* setup TX DMA channels. */
b27faf8e
MB		 1001 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1002 if (!dma->tx_ring_AC_BK)
e4d6b795 1003 goto out;
e4d6b795 1004
b27faf8e
MB		 1005 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1006 if (!dma->tx_ring_AC_BE)
1007 goto err_destroy_bk;
e4d6b795 1008
b27faf8e
MB		 1009 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1010 if (!dma->tx_ring_AC_VI)
1011 goto err_destroy_be;
e4d6b795 1012
b27faf8e
MB		 1013 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1014 if (!dma->tx_ring_AC_VO)
1015 goto err_destroy_vi;
e4d6b795 1016
b27faf8e
MB		 1017 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1018 if (!dma->tx_ring_mcast)
1019 goto err_destroy_vo;
e4d6b795 1020
b27faf8e
MB		 1021 /* setup RX DMA channel. */
1022 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1023 if (!dma->rx_ring)
1024 goto err_destroy_mcast;
e4d6b795 1025
b27faf8e
MB		 1026 /* No support for the TX status DMA ring. */
1027 B43_WARN_ON(dev->dev->id.revision < 5);
e4d6b795 1028
b79caa68
MB		 1029 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1030 (unsigned int)type);
e4d6b795 1031 err = 0;
b27faf8e 1032out:
e4d6b795
MB		 1033 return err;
1034
b27faf8e
MB		 1035err_destroy_mcast:
1036 destroy_ring(dma, tx_ring_mcast);
1037err_destroy_vo:
1038 destroy_ring(dma, tx_ring_AC_VO);
1039err_destroy_vi:
1040 destroy_ring(dma, tx_ring_AC_VI);
1041err_destroy_be:
1042 destroy_ring(dma, tx_ring_AC_BE);
1043err_destroy_bk:
1044 destroy_ring(dma, tx_ring_AC_BK);
1045 return err;
e4d6b795
MB		 1046}
1047
1048/* Generate a cookie for the TX header. */
1049static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1050{
b27faf8e 1051 u16 cookie;
e4d6b795
MB		 1052
1053 /* Use the upper 4 bits of the cookie as
1054 * DMA controller ID and store the slot number
1055 * in the lower 12 bits.
1056 * Note that the cookie must never be 0, as this
1057 * is a special value used in RX path.
280d0e16
MB		 1058 * It can also not be 0xFFFF because that is special
1059 * for multicast frames.
e4d6b795 1060 */
b27faf8e 1061 cookie = (((u16)ring->index + 1) << 12);
e4d6b795 1062 B43_WARN_ON(slot & ~0x0FFF);
b27faf8e 1063 cookie |= (u16)slot;
e4d6b795
MB		 1064
1065 return cookie;
1066}
1067
1068/* Inspect a cookie and find out to which controller/slot it belongs. */
1069static
1070struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1071{
1072 struct b43_dma *dma = &dev->dma;
1073 struct b43_dmaring *ring = NULL;
1074
1075 switch (cookie & 0xF000) {
280d0e16 1076 case 0x1000:
b27faf8e 1077 ring = dma->tx_ring_AC_BK;
e4d6b795 1078 break;
280d0e16 1079 case 0x2000:
b27faf8e 1080 ring = dma->tx_ring_AC_BE;
e4d6b795 1081 break;
280d0e16 1082 case 0x3000:
b27faf8e 1083 ring = dma->tx_ring_AC_VI;
e4d6b795 1084 break;
280d0e16 1085 case 0x4000:
b27faf8e 1086 ring = dma->tx_ring_AC_VO;
e4d6b795 1087 break;
280d0e16 1088 case 0x5000:
b27faf8e 1089 ring = dma->tx_ring_mcast;
e4d6b795
MB		 1090 break;
1091 default:
1092 B43_WARN_ON(1);
1093 }
1094 *slot = (cookie & 0x0FFF);
1095 B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1096
1097 return ring;
1098}
1099
1100static int dma_tx_fragment(struct b43_dmaring *ring,
1101 struct sk_buff *skb,
1102 struct ieee80211_tx_control *ctl)
1103{
1104 const struct b43_dma_ops *ops = ring->ops;
1105 u8 *header;
09552ccd 1106 int slot, old_top_slot, old_used_slots;
e4d6b795
MB		 1107 int err;
1108 struct b43_dmadesc_generic *desc;
1109 struct b43_dmadesc_meta *meta;
1110 struct b43_dmadesc_meta *meta_hdr;
1111 struct sk_buff *bounce_skb;
280d0e16 1112 u16 cookie;
eb189d8b 1113 size_t hdrsize = b43_txhdr_size(ring->dev);
e4d6b795
MB		 1114
1115#define SLOTS_PER_PACKET 2
1116 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
1117
09552ccd
MB		 1118 old_top_slot = ring->current_slot;
1119 old_used_slots = ring->used_slots;
1120
e4d6b795
MB		 1121 /* Get a slot for the header. */
1122 slot = request_slot(ring);
1123 desc = ops->idx2desc(ring, slot, &meta_hdr);
1124 memset(meta_hdr, 0, sizeof(*meta_hdr));
1125
eb189d8b 1126 header = &(ring->txhdr_cache[slot * hdrsize]);
280d0e16 1127 cookie = generate_cookie(ring, slot);
09552ccd
MB		 1128 err = b43_generate_txhdr(ring->dev, header,
1129 skb->data, skb->len, ctl, cookie);
1130 if (unlikely(err)) {
1131 ring->current_slot = old_top_slot;
1132 ring->used_slots = old_used_slots;
1133 return err;
1134 }
e4d6b795
MB		 1135
1136 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
eb189d8b 1137 hdrsize, 1);
ffa9256a 1138 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
09552ccd
MB		 1139 ring->current_slot = old_top_slot;
1140 ring->used_slots = old_used_slots;
e4d6b795 1141 return -EIO;
09552ccd 1142 }
e4d6b795 1143 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
eb189d8b 1144 hdrsize, 1, 0, 0);
e4d6b795
MB		 1145
1146 /* Get a slot for the payload. */
1147 slot = request_slot(ring);
1148 desc = ops->idx2desc(ring, slot, &meta);
1149 memset(meta, 0, sizeof(*meta));
1150
1151 memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1152 meta->skb = skb;
1153 meta->is_last_fragment = 1;
1154
1155 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1156 /* create a bounce buffer in zone_dma on mapping failure. */
ffa9256a 1157 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
e4d6b795
MB		 1158 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1159 if (!bounce_skb) {
09552ccd
MB		 1160 ring->current_slot = old_top_slot;
1161 ring->used_slots = old_used_slots;
e4d6b795
MB		 1162 err = -ENOMEM;
1163 goto out_unmap_hdr;
1164 }
1165
1166 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1167 dev_kfree_skb_any(skb);
1168 skb = bounce_skb;
1169 meta->skb = skb;
1170 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
ffa9256a 1171 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
09552ccd
MB		 1172 ring->current_slot = old_top_slot;
1173 ring->used_slots = old_used_slots;
e4d6b795
MB		 1174 err = -EIO;
1175 goto out_free_bounce;
1176 }
1177 }
1178
1179 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1180
280d0e16
MB		 1181 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1182 /* Tell the firmware about the cookie of the last
1183 * mcast frame, so it can clear the more-data bit in it. */
1184 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1185 B43_SHM_SH_MCASTCOOKIE, cookie);
1186 }
e4d6b795
MB		 1187 /* Now transfer the whole frame. */
1188 wmb();
1189 ops->poke_tx(ring, next_slot(ring, slot));
1190 return 0;
1191
280d0e16 1192out_free_bounce:
e4d6b795 1193 dev_kfree_skb_any(skb);
280d0e16 1194out_unmap_hdr:
e4d6b795 1195 unmap_descbuffer(ring, meta_hdr->dmaaddr,
eb189d8b 1196 hdrsize, 1);
e4d6b795
MB		 1197 return err;
1198}
1199
1200static inline int should_inject_overflow(struct b43_dmaring *ring)
1201{
1202#ifdef CONFIG_B43_DEBUG
1203 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1204 /* Check if we should inject another ringbuffer overflow
1205 * to test handling of this situation in the stack. */
1206 unsigned long next_overflow;
1207
1208 next_overflow = ring->last_injected_overflow + HZ;
1209 if (time_after(jiffies, next_overflow)) {
1210 ring->last_injected_overflow = jiffies;
1211 b43dbg(ring->dev->wl,
1212 "Injecting TX ring overflow on "
1213 "DMA controller %d\n", ring->index);
1214 return 1;
1215 }
1216 }
1217#endif /* CONFIG_B43_DEBUG */
1218 return 0;
1219}
1220
e6f5b934
MB		 1221/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1222static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev,
1223 u8 queue_prio)
1224{
1225 struct b43_dmaring *ring;
1226
1227 if (b43_modparam_qos) {
1228 /* 0 = highest priority */
1229 switch (queue_prio) {
1230 default:
1231 B43_WARN_ON(1);
1232 /* fallthrough */
1233 case 0:
b27faf8e 1234 ring = dev->dma.tx_ring_AC_VO;
e6f5b934
MB		 1235 break;
1236 case 1:
b27faf8e 1237 ring = dev->dma.tx_ring_AC_VI;
e6f5b934
MB		 1238 break;
1239 case 2:
b27faf8e 1240 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1241 break;
1242 case 3:
b27faf8e 1243 ring = dev->dma.tx_ring_AC_BK;
e6f5b934
MB		 1244 break;
1245 }
1246 } else
b27faf8e 1247 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1248
1249 return ring;
1250}
1251
e4d6b795
MB		 1252int b43_dma_tx(struct b43_wldev *dev,
1253 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1254{
1255 struct b43_dmaring *ring;
280d0e16 1256 struct ieee80211_hdr *hdr;
e4d6b795
MB		 1257 int err = 0;
1258 unsigned long flags;
1259
280d0e16
MB		 1260 if (unlikely(skb->len < 2 + 2 + 6)) {
1261 /* Too short, this can't be a valid frame. */
1262 return -EINVAL;
1263 }
1264
1265 hdr = (struct ieee80211_hdr *)skb->data;
1266 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1267 /* The multicast ring will be sent after the DTIM */
b27faf8e 1268 ring = dev->dma.tx_ring_mcast;
280d0e16
MB		 1269 /* Set the more-data bit. Ucode will clear it on
1270 * the last frame for us. */
1271 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1272 } else {
1273 /* Decide by priority where to put this frame. */
e6f5b934 1274 ring = select_ring_by_priority(dev, ctl->queue);
280d0e16
MB		 1275 }
1276
e4d6b795
MB		 1277 spin_lock_irqsave(&ring->lock, flags);
1278 B43_WARN_ON(!ring->tx);
1279 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1280 b43warn(dev->wl, "DMA queue overflow\n");
1281 err = -ENOSPC;
1282 goto out_unlock;
1283 }
1284 /* Check if the queue was stopped in mac80211,
1285 * but we got called nevertheless.
1286 * That would be a mac80211 bug. */
1287 B43_WARN_ON(ring->stopped);
1288
e6f5b934
MB		 1289 /* Assign the queue number to the ring (if not already done before)
1290 * so TX status handling can use it. The queue to ring mapping is
1291 * static, so we don't need to store it per frame. */
1292 ring->queue_prio = ctl->queue;
1293
e4d6b795 1294 err = dma_tx_fragment(ring, skb, ctl);
09552ccd
MB		 1295 if (unlikely(err == -ENOKEY)) {
1296 /* Drop this packet, as we don't have the encryption key
1297 * anymore and must not transmit it unencrypted. */
1298 dev_kfree_skb_any(skb);
1299 err = 0;
1300 goto out_unlock;
1301 }
e4d6b795
MB		 1302 if (unlikely(err)) {
1303 b43err(dev->wl, "DMA tx mapping failure\n");
1304 goto out_unlock;
1305 }
1306 ring->nr_tx_packets++;
1307 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1308 should_inject_overflow(ring)) {
1309 /* This TX ring is full. */
e6f5b934 1310 ieee80211_stop_queue(dev->wl->hw, ctl->queue);
e4d6b795
MB		 1311 ring->stopped = 1;
1312 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1313 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1314 }
1315 }
280d0e16 1316out_unlock:
e4d6b795
MB		 1317 spin_unlock_irqrestore(&ring->lock, flags);
1318
1319 return err;
1320}
1321
57df40d2
MB		 1322static void b43_fill_txstatus_report(struct b43_dmaring *ring,
1323 struct ieee80211_tx_status *report,
1324 const struct b43_txstatus *status)
1325{
1326 bool frame_failed = 0;
1327
1328 if (status->acked) {
1329 /* The frame was ACKed. */
1330 report->flags |= IEEE80211_TX_STATUS_ACK;
1331 } else {
1332 /* The frame was not ACKed... */
1333 if (!(report->control.flags & IEEE80211_TXCTL_NO_ACK)) {
1334 /* ...but we expected an ACK. */
1335 frame_failed = 1;
1336 report->excessive_retries = 1;
1337 }
1338 }
1339 if (status->frame_count == 0) {
1340 /* The frame was not transmitted at all. */
1341 report->retry_count = 0;
1342 } else {
1343 report->retry_count = status->frame_count - 1;
1344#ifdef CONFIG_B43_DEBUG
1345 if (frame_failed)
1346 ring->nr_failed_tx_packets++;
1347 else
1348 ring->nr_succeed_tx_packets++;
1349 ring->nr_total_packet_tries += status->frame_count;
1350#endif /* DEBUG */
1351 }
1352}
1353
7a193a5d 1354/* Called with IRQs disabled. */
e4d6b795
MB		 1355void b43_dma_handle_txstatus(struct b43_wldev *dev,
1356 const struct b43_txstatus *status)
1357{
1358 const struct b43_dma_ops *ops;
1359 struct b43_dmaring *ring;
1360 struct b43_dmadesc_generic *desc;
1361 struct b43_dmadesc_meta *meta;
1362 int slot;
1363
1364 ring = parse_cookie(dev, status->cookie, &slot);
1365 if (unlikely(!ring))
1366 return;
7a193a5d
MB		 1367
1368 spin_lock(&ring->lock); /* IRQs are already disabled. */
e4d6b795
MB		 1369
1370 B43_WARN_ON(!ring->tx);
1371 ops = ring->ops;
1372 while (1) {
1373 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1374 desc = ops->idx2desc(ring, slot, &meta);
1375
1376 if (meta->skb)
1377 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1378 1);
1379 else
1380 unmap_descbuffer(ring, meta->dmaaddr,
eb189d8b 1381 b43_txhdr_size(dev), 1);
e4d6b795
MB		 1382
1383 if (meta->is_last_fragment) {
1384 B43_WARN_ON(!meta->skb);
1385 /* Call back to inform the ieee80211 subsystem about the
1386 * status of the transmission.
1387 * Some fields of txstat are already filled in dma_tx().
1388 */
57df40d2 1389 b43_fill_txstatus_report(ring, &(meta->txstat), status);
e4d6b795
MB		 1390 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1391 &(meta->txstat));
1392 /* skb is freed by ieee80211_tx_status_irqsafe() */
1393 meta->skb = NULL;
1394 } else {
1395 /* No need to call free_descriptor_buffer here, as
1396 * this is only the txhdr, which is not allocated.
1397 */
1398 B43_WARN_ON(meta->skb);
1399 }
1400
1401 /* Everything unmapped and free'd. So it's not used anymore. */
1402 ring->used_slots--;
1403
1404 if (meta->is_last_fragment)
1405 break;
1406 slot = next_slot(ring, slot);
1407 }
1408 dev->stats.last_tx = jiffies;
1409 if (ring->stopped) {
1410 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
e6f5b934 1411 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
e4d6b795
MB		 1412 ring->stopped = 0;
1413 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1414 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1415 }
1416 }
1417
1418 spin_unlock(&ring->lock);
1419}
1420
1421void b43_dma_get_tx_stats(struct b43_wldev *dev,
1422 struct ieee80211_tx_queue_stats *stats)
1423{
1424 const int nr_queues = dev->wl->hw->queues;
1425 struct b43_dmaring *ring;
1426 struct ieee80211_tx_queue_stats_data *data;
1427 unsigned long flags;
1428 int i;
1429
1430 for (i = 0; i < nr_queues; i++) {
1431 data = &(stats->data[i]);
e6f5b934 1432 ring = select_ring_by_priority(dev, i);
e4d6b795
MB		 1433
1434 spin_lock_irqsave(&ring->lock, flags);
1435 data->len = ring->used_slots / SLOTS_PER_PACKET;
1436 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1437 data->count = ring->nr_tx_packets;
1438 spin_unlock_irqrestore(&ring->lock, flags);
1439 }
1440}
1441
1442static void dma_rx(struct b43_dmaring *ring, int *slot)
1443{
1444 const struct b43_dma_ops *ops = ring->ops;
1445 struct b43_dmadesc_generic *desc;
1446 struct b43_dmadesc_meta *meta;
1447 struct b43_rxhdr_fw4 *rxhdr;
1448 struct sk_buff *skb;
1449 u16 len;
1450 int err;
1451 dma_addr_t dmaaddr;
1452
1453 desc = ops->idx2desc(ring, *slot, &meta);
1454
1455 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1456 skb = meta->skb;
1457
e4d6b795
MB		 1458 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1459 len = le16_to_cpu(rxhdr->frame_len);
1460 if (len == 0) {
1461 int i = 0;
1462
1463 do {
1464 udelay(2);
1465 barrier();
1466 len = le16_to_cpu(rxhdr->frame_len);
1467 } while (len == 0 && i++ < 5);
1468 if (unlikely(len == 0)) {
1469 /* recycle the descriptor buffer. */
1470 sync_descbuffer_for_device(ring, meta->dmaaddr,
1471 ring->rx_buffersize);
1472 goto drop;
1473 }
1474 }
1475 if (unlikely(len > ring->rx_buffersize)) {
1476 /* The data did not fit into one descriptor buffer
1477 * and is split over multiple buffers.
1478 * This should never happen, as we try to allocate buffers
1479 * big enough. So simply ignore this packet.
1480 */
1481 int cnt = 0;
1482 s32 tmp = len;
1483
1484 while (1) {
1485 desc = ops->idx2desc(ring, *slot, &meta);
1486 /* recycle the descriptor buffer. */
1487 sync_descbuffer_for_device(ring, meta->dmaaddr,
1488 ring->rx_buffersize);
1489 *slot = next_slot(ring, *slot);
1490 cnt++;
1491 tmp -= ring->rx_buffersize;
1492 if (tmp <= 0)
1493 break;
1494 }
1495 b43err(ring->dev->wl, "DMA RX buffer too small "
1496 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1497 len, ring->rx_buffersize, cnt);
1498 goto drop;
1499 }
1500
1501 dmaaddr = meta->dmaaddr;
1502 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1503 if (unlikely(err)) {
1504 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1505 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1506 goto drop;
1507 }
1508
1509 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1510 skb_put(skb, len + ring->frameoffset);
1511 skb_pull(skb, ring->frameoffset);
1512
1513 b43_rx(ring->dev, skb, rxhdr);
b27faf8e 1514drop:
e4d6b795
MB		 1515 return;
1516}
1517
1518void b43_dma_rx(struct b43_dmaring *ring)
1519{
1520 const struct b43_dma_ops *ops = ring->ops;
1521 int slot, current_slot;
1522 int used_slots = 0;
1523
1524 B43_WARN_ON(ring->tx);
1525 current_slot = ops->get_current_rxslot(ring);
1526 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1527
1528 slot = ring->current_slot;
1529 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1530 dma_rx(ring, &slot);
1531 update_max_used_slots(ring, ++used_slots);
1532 }
1533 ops->set_current_rxslot(ring, slot);
1534 ring->current_slot = slot;
1535}
1536
1537static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1538{
1539 unsigned long flags;
1540
1541 spin_lock_irqsave(&ring->lock, flags);
1542 B43_WARN_ON(!ring->tx);
1543 ring->ops->tx_suspend(ring);
1544 spin_unlock_irqrestore(&ring->lock, flags);
1545}
1546
1547static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1548{
1549 unsigned long flags;
1550
1551 spin_lock_irqsave(&ring->lock, flags);
1552 B43_WARN_ON(!ring->tx);
1553 ring->ops->tx_resume(ring);
1554 spin_unlock_irqrestore(&ring->lock, flags);
1555}
1556
1557void b43_dma_tx_suspend(struct b43_wldev *dev)
1558{
1559 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
b27faf8e
MB		 1560 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1561 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1562 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1563 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1564 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
e4d6b795
MB		 1565}
1566
1567void b43_dma_tx_resume(struct b43_wldev *dev)
1568{
b27faf8e
MB		 1569 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1570 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1571 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1572 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1573 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
e4d6b795
MB		 1574 b43_power_saving_ctl_bits(dev, 0);
1575}
Linux kernel - Deliverables
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