projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for...
[deliverable/linux.git] / drivers / net / wireless / b43 / dma.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
eb032b98 7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
280d0e16 40#include <linux/etherdevice.h>
5a0e3ad6 41#include <linux/slab.h>
57df40d2 42#include <asm/div64.h>
280d0e16 43
e4d6b795 44
bdceeb2d
MB		 45/* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48#define TX_SLOTS_PER_FRAME 2
49
50
e4d6b795
MB		 51/* 32bit DMA ops. */
52static
53struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
54 int slot,
55 struct b43_dmadesc_meta **meta)
56{
57 struct b43_dmadesc32 *desc;
58
59 *meta = &(ring->meta[slot]);
60 desc = ring->descbase;
61 desc = &(desc[slot]);
62
63 return (struct b43_dmadesc_generic *)desc;
64}
65
66static void op32_fill_descriptor(struct b43_dmaring *ring,
67 struct b43_dmadesc_generic *desc,
68 dma_addr_t dmaaddr, u16 bufsize,
69 int start, int end, int irq)
70{
71 struct b43_dmadesc32 *descbase = ring->descbase;
72 int slot;
73 u32 ctl;
74 u32 addr;
75 u32 addrext;
76
77 slot = (int)(&(desc->dma32) - descbase);
78 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
79
80 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
81 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
82 >> SSB_DMA_TRANSLATION_SHIFT;
05100a29 83 addr |= ring->dev->dma.translation;
8eccb53f 84 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
e4d6b795
MB		 85 if (slot == ring->nr_slots - 1)
86 ctl |= B43_DMA32_DCTL_DTABLEEND;
87 if (start)
88 ctl |= B43_DMA32_DCTL_FRAMESTART;
89 if (end)
90 ctl |= B43_DMA32_DCTL_FRAMEEND;
91 if (irq)
92 ctl |= B43_DMA32_DCTL_IRQ;
93 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
94 & B43_DMA32_DCTL_ADDREXT_MASK;
95
96 desc->dma32.control = cpu_to_le32(ctl);
97 desc->dma32.address = cpu_to_le32(addr);
98}
99
100static void op32_poke_tx(struct b43_dmaring *ring, int slot)
101{
102 b43_dma_write(ring, B43_DMA32_TXINDEX,
103 (u32) (slot * sizeof(struct b43_dmadesc32)));
104}
105
106static void op32_tx_suspend(struct b43_dmaring *ring)
107{
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 | B43_DMA32_TXSUSPEND);
110}
111
112static void op32_tx_resume(struct b43_dmaring *ring)
113{
114 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
115 & ~B43_DMA32_TXSUSPEND);
116}
117
118static int op32_get_current_rxslot(struct b43_dmaring *ring)
119{
120 u32 val;
121
122 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
123 val &= B43_DMA32_RXDPTR;
124
125 return (val / sizeof(struct b43_dmadesc32));
126}
127
128static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
129{
130 b43_dma_write(ring, B43_DMA32_RXINDEX,
131 (u32) (slot * sizeof(struct b43_dmadesc32)));
132}
133
134static const struct b43_dma_ops dma32_ops = {
135 .idx2desc = op32_idx2desc,
136 .fill_descriptor = op32_fill_descriptor,
137 .poke_tx = op32_poke_tx,
138 .tx_suspend = op32_tx_suspend,
139 .tx_resume = op32_tx_resume,
140 .get_current_rxslot = op32_get_current_rxslot,
141 .set_current_rxslot = op32_set_current_rxslot,
142};
143
144/* 64bit DMA ops. */
145static
146struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
147 int slot,
148 struct b43_dmadesc_meta **meta)
149{
150 struct b43_dmadesc64 *desc;
151
152 *meta = &(ring->meta[slot]);
153 desc = ring->descbase;
154 desc = &(desc[slot]);
155
156 return (struct b43_dmadesc_generic *)desc;
157}
158
159static void op64_fill_descriptor(struct b43_dmaring *ring,
160 struct b43_dmadesc_generic *desc,
161 dma_addr_t dmaaddr, u16 bufsize,
162 int start, int end, int irq)
163{
164 struct b43_dmadesc64 *descbase = ring->descbase;
165 int slot;
166 u32 ctl0 = 0, ctl1 = 0;
167 u32 addrlo, addrhi;
168 u32 addrext;
169
170 slot = (int)(&(desc->dma64) - descbase);
171 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
a9770a81 177 addrhi |= ring->dev->dma.translation;
e4d6b795
MB		 178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
180 if (start)
181 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
182 if (end)
183 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
184 if (irq)
185 ctl0 |= B43_DMA64_DCTL0_IRQ;
8eccb53f 186 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
e4d6b795
MB		 187 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
188 & B43_DMA64_DCTL1_ADDREXT_MASK;
189
190 desc->dma64.control0 = cpu_to_le32(ctl0);
191 desc->dma64.control1 = cpu_to_le32(ctl1);
192 desc->dma64.address_low = cpu_to_le32(addrlo);
193 desc->dma64.address_high = cpu_to_le32(addrhi);
194}
195
196static void op64_poke_tx(struct b43_dmaring *ring, int slot)
197{
198 b43_dma_write(ring, B43_DMA64_TXINDEX,
199 (u32) (slot * sizeof(struct b43_dmadesc64)));
200}
201
202static void op64_tx_suspend(struct b43_dmaring *ring)
203{
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 | B43_DMA64_TXSUSPEND);
206}
207
208static void op64_tx_resume(struct b43_dmaring *ring)
209{
210 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
211 & ~B43_DMA64_TXSUSPEND);
212}
213
214static int op64_get_current_rxslot(struct b43_dmaring *ring)
215{
216 u32 val;
217
218 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
219 val &= B43_DMA64_RXSTATDPTR;
220
221 return (val / sizeof(struct b43_dmadesc64));
222}
223
224static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
225{
226 b43_dma_write(ring, B43_DMA64_RXINDEX,
227 (u32) (slot * sizeof(struct b43_dmadesc64)));
228}
229
230static const struct b43_dma_ops dma64_ops = {
231 .idx2desc = op64_idx2desc,
232 .fill_descriptor = op64_fill_descriptor,
233 .poke_tx = op64_poke_tx,
234 .tx_suspend = op64_tx_suspend,
235 .tx_resume = op64_tx_resume,
236 .get_current_rxslot = op64_get_current_rxslot,
237 .set_current_rxslot = op64_set_current_rxslot,
238};
239
240static inline int free_slots(struct b43_dmaring *ring)
241{
242 return (ring->nr_slots - ring->used_slots);
243}
244
245static inline int next_slot(struct b43_dmaring *ring, int slot)
246{
247 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
248 if (slot == ring->nr_slots - 1)
249 return 0;
250 return slot + 1;
251}
252
253static inline int prev_slot(struct b43_dmaring *ring, int slot)
254{
255 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
256 if (slot == 0)
257 return ring->nr_slots - 1;
258 return slot - 1;
259}
260
261#ifdef CONFIG_B43_DEBUG
262static void update_max_used_slots(struct b43_dmaring *ring,
263 int current_used_slots)
264{
265 if (current_used_slots <= ring->max_used_slots)
266 return;
267 ring->max_used_slots = current_used_slots;
268 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
269 b43dbg(ring->dev->wl,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring->max_used_slots,
272 ring->tx ? "TX" : "RX", ring->index);
273 }
274}
275#else
276static inline
277 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
278{
279}
280#endif /* DEBUG */
281
282/* Request a slot for usage. */
283static inline int request_slot(struct b43_dmaring *ring)
284{
285 int slot;
286
287 B43_WARN_ON(!ring->tx);
288 B43_WARN_ON(ring->stopped);
289 B43_WARN_ON(free_slots(ring) == 0);
290
291 slot = next_slot(ring, ring->current_slot);
292 ring->current_slot = slot;
293 ring->used_slots++;
294
295 update_max_used_slots(ring, ring->used_slots);
296
297 return slot;
298}
299
b79caa68 300static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
e4d6b795
MB		 301{
302 static const u16 map64[] = {
303 B43_MMIO_DMA64_BASE0,
304 B43_MMIO_DMA64_BASE1,
305 B43_MMIO_DMA64_BASE2,
306 B43_MMIO_DMA64_BASE3,
307 B43_MMIO_DMA64_BASE4,
308 B43_MMIO_DMA64_BASE5,
309 };
310 static const u16 map32[] = {
311 B43_MMIO_DMA32_BASE0,
312 B43_MMIO_DMA32_BASE1,
313 B43_MMIO_DMA32_BASE2,
314 B43_MMIO_DMA32_BASE3,
315 B43_MMIO_DMA32_BASE4,
316 B43_MMIO_DMA32_BASE5,
317 };
318
b79caa68 319 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 320 B43_WARN_ON(!(controller_idx >= 0 &&
321 controller_idx < ARRAY_SIZE(map64)));
322 return map64[controller_idx];
323 }
324 B43_WARN_ON(!(controller_idx >= 0 &&
325 controller_idx < ARRAY_SIZE(map32)));
326 return map32[controller_idx];
327}
328
329static inline
330 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
331 unsigned char *buf, size_t len, int tx)
332{
333 dma_addr_t dmaaddr;
334
335 if (tx) {
a18c715e 336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
718e8898 337 buf, len, DMA_TO_DEVICE);
e4d6b795 338 } else {
a18c715e 339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
718e8898 340 buf, len, DMA_FROM_DEVICE);
e4d6b795
MB		 341 }
342
343 return dmaaddr;
344}
345
346static inline
347 void unmap_descbuffer(struct b43_dmaring *ring,
348 dma_addr_t addr, size_t len, int tx)
349{
350 if (tx) {
a18c715e 351 dma_unmap_single(ring->dev->dev->dma_dev,
718e8898 352 addr, len, DMA_TO_DEVICE);
e4d6b795 353 } else {
a18c715e 354 dma_unmap_single(ring->dev->dev->dma_dev,
718e8898 355 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 356 }
357}
358
359static inline
360 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
361 dma_addr_t addr, size_t len)
362{
363 B43_WARN_ON(ring->tx);
a18c715e 364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
f225763a 365 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 366}
367
368static inline
369 void sync_descbuffer_for_device(struct b43_dmaring *ring,
370 dma_addr_t addr, size_t len)
371{
372 B43_WARN_ON(ring->tx);
a18c715e 373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
718e8898 374 addr, len, DMA_FROM_DEVICE);
e4d6b795
MB		 375}
376
377static inline
378 void free_descriptor_buffer(struct b43_dmaring *ring,
379 struct b43_dmadesc_meta *meta)
380{
381 if (meta->skb) {
382 dev_kfree_skb_any(meta->skb);
383 meta->skb = NULL;
384 }
385}
386
387static int alloc_ringmemory(struct b43_dmaring *ring)
388{
55afc80b
JL		 389 gfp_t flags = GFP_KERNEL;
390
391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
395 *
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
399 *
400 * The flags here must match the flags in free_ringmemory below!
013978b6 401 */
b79caa68 402 if (ring->type == B43_DMA_64BIT)
55afc80b 403 flags |= GFP_DMA;
a18c715e 404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
718e8898
FT		 405 B43_DMA_RINGMEMSIZE,
406 &(ring->dmabase), flags);
55afc80b
JL		 407 if (!ring->descbase) {
408 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
9bd568a5 409 return -ENOMEM;
e4d6b795 410 }
55afc80b 411 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
e4d6b795
MB		 412
413 return 0;
414}
415
416static void free_ringmemory(struct b43_dmaring *ring)
417{
a18c715e 418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
718e8898 419 ring->descbase, ring->dmabase);
e4d6b795
MB		 420}
421
422/* Reset the RX DMA channel */
b79caa68
MB		 423static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
424 enum b43_dmatype type)
e4d6b795
MB		 425{
426 int i;
427 u32 value;
428 u16 offset;
429
430 might_sleep();
431
b79caa68 432 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
e4d6b795
MB		 433 b43_write32(dev, mmio_base + offset, 0);
434 for (i = 0; i < 10; i++) {
b79caa68
MB		 435 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
436 B43_DMA32_RXSTATUS;
e4d6b795 437 value = b43_read32(dev, mmio_base + offset);
b79caa68 438 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 439 value &= B43_DMA64_RXSTAT;
440 if (value == B43_DMA64_RXSTAT_DISABLED) {
441 i = -1;
442 break;
443 }
444 } else {
445 value &= B43_DMA32_RXSTATE;
446 if (value == B43_DMA32_RXSTAT_DISABLED) {
447 i = -1;
448 break;
449 }
450 }
451 msleep(1);
452 }
453 if (i != -1) {
454 b43err(dev->wl, "DMA RX reset timed out\n");
455 return -ENODEV;
456 }
457
458 return 0;
459}
460
013978b6 461/* Reset the TX DMA channel */
b79caa68
MB		 462static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
e4d6b795
MB		 464{
465 int i;
466 u32 value;
467 u16 offset;
468
469 might_sleep();
470
471 for (i = 0; i < 10; i++) {
b79caa68
MB		 472 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
473 B43_DMA32_TXSTATUS;
e4d6b795 474 value = b43_read32(dev, mmio_base + offset);
b79caa68 475 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 476 value &= B43_DMA64_TXSTAT;
477 if (value == B43_DMA64_TXSTAT_DISABLED ||
478 value == B43_DMA64_TXSTAT_IDLEWAIT ||
479 value == B43_DMA64_TXSTAT_STOPPED)
480 break;
481 } else {
482 value &= B43_DMA32_TXSTATE;
483 if (value == B43_DMA32_TXSTAT_DISABLED ||
484 value == B43_DMA32_TXSTAT_IDLEWAIT ||
485 value == B43_DMA32_TXSTAT_STOPPED)
486 break;
487 }
488 msleep(1);
489 }
b79caa68 490 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
e4d6b795
MB		 491 b43_write32(dev, mmio_base + offset, 0);
492 for (i = 0; i < 10; i++) {
b79caa68
MB		 493 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
494 B43_DMA32_TXSTATUS;
e4d6b795 495 value = b43_read32(dev, mmio_base + offset);
b79caa68 496 if (type == B43_DMA_64BIT) {
e4d6b795
MB		 497 value &= B43_DMA64_TXSTAT;
498 if (value == B43_DMA64_TXSTAT_DISABLED) {
499 i = -1;
500 break;
501 }
502 } else {
503 value &= B43_DMA32_TXSTATE;
504 if (value == B43_DMA32_TXSTAT_DISABLED) {
505 i = -1;
506 break;
507 }
508 }
509 msleep(1);
510 }
511 if (i != -1) {
512 b43err(dev->wl, "DMA TX reset timed out\n");
513 return -ENODEV;
514 }
515 /* ensure the reset is completed. */
516 msleep(1);
517
518 return 0;
519}
520
b79caa68
MB		 521/* Check if a DMA mapping address is invalid. */
522static bool b43_dma_mapping_error(struct b43_dmaring *ring,
523 dma_addr_t addr,
ffa9256a 524 size_t buffersize, bool dma_to_device)
b79caa68 525{
a18c715e 526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
b79caa68
MB		 527 return 1;
528
55afc80b
JL		 529 switch (ring->type) {
530 case B43_DMA_30BIT:
531 if ((u64)addr + buffersize > (1ULL << 30))
532 goto address_error;
533 break;
534 case B43_DMA_32BIT:
535 if ((u64)addr + buffersize > (1ULL << 32))
536 goto address_error;
537 break;
538 case B43_DMA_64BIT:
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
541 break;
b79caa68
MB		 542 }
543
544 /* The address is OK. */
545 return 0;
55afc80b
JL		 546
547address_error:
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
550
551 return 1;
b79caa68
MB		 552}
553
ec9a1d8c
MB		 554static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
555{
556 unsigned char *f = skb->data + ring->frameoffset;
557
558 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
559}
560
561static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
562{
563 struct b43_rxhdr_fw4 *rxhdr;
564 unsigned char *frame;
565
566 /* This poisons the RX buffer to detect DMA failures. */
567
568 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
569 rxhdr->frame_len = 0;
570
571 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
572 frame = skb->data + ring->frameoffset;
573 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
574}
575
e4d6b795
MB		 576static int setup_rx_descbuffer(struct b43_dmaring *ring,
577 struct b43_dmadesc_generic *desc,
578 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
579{
e4d6b795
MB		 580 dma_addr_t dmaaddr;
581 struct sk_buff *skb;
582
583 B43_WARN_ON(ring->tx);
584
585 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
586 if (unlikely(!skb))
587 return -ENOMEM;
ec9a1d8c 588 b43_poison_rx_buffer(ring, skb);
e4d6b795 589 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
ffa9256a 590 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
e4d6b795
MB		 591 /* ugh. try to realloc in zone_dma */
592 gfp_flags |= GFP_DMA;
593
594 dev_kfree_skb_any(skb);
595
596 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
597 if (unlikely(!skb))
598 return -ENOMEM;
ec9a1d8c 599 b43_poison_rx_buffer(ring, skb);
e4d6b795
MB		 600 dmaaddr = map_descbuffer(ring, skb->data,
601 ring->rx_buffersize, 0);
bdceeb2d
MB		 602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
603 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb);
605 return -EIO;
606 }
e4d6b795
MB		 607 }
608
609 meta->skb = skb;
610 meta->dmaaddr = dmaaddr;
611 ring->ops->fill_descriptor(ring, desc, dmaaddr,
612 ring->rx_buffersize, 0, 0, 0);
613
e4d6b795
MB		 614 return 0;
615}
616
617/* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
619 */
620static int alloc_initial_descbuffers(struct b43_dmaring *ring)
621{
622 int i, err = -ENOMEM;
623 struct b43_dmadesc_generic *desc;
624 struct b43_dmadesc_meta *meta;
625
626 for (i = 0; i < ring->nr_slots; i++) {
627 desc = ring->ops->idx2desc(ring, i, &meta);
628
629 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
630 if (err) {
631 b43err(ring->dev->wl,
632 "Failed to allocate initial descbuffers\n");
633 goto err_unwind;
634 }
635 }
636 mb();
637 ring->used_slots = ring->nr_slots;
638 err = 0;
639 out:
640 return err;
641
642 err_unwind:
643 for (i--; i >= 0; i--) {
644 desc = ring->ops->idx2desc(ring, i, &meta);
645
646 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
647 dev_kfree_skb(meta->skb);
648 }
649 goto out;
650}
651
652/* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
655 */
656static int dmacontroller_setup(struct b43_dmaring *ring)
657{
658 int err = 0;
659 u32 value;
660 u32 addrext;
05100a29 661 u32 trans = ring->dev->dma.translation;
78c1ee7e 662 bool parity = ring->dev->dma.parity;
e4d6b795
MB		 663
664 if (ring->tx) {
b79caa68 665 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 666 u64 ringbase = (u64) (ring->dmabase);
667
668 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
669 >> SSB_DMA_TRANSLATION_SHIFT;
670 value = B43_DMA64_TXENABLE;
671 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
672 & B43_DMA64_TXADDREXT_MASK;
78c1ee7e
RM		 673 if (!parity)
674 value |= B43_DMA64_TXPARITYDISABLE;
e4d6b795
MB		 675 b43_dma_write(ring, B43_DMA64_TXCTL, value);
676 b43_dma_write(ring, B43_DMA64_TXRINGLO,
677 (ringbase & 0xFFFFFFFF));
678 b43_dma_write(ring, B43_DMA64_TXRINGHI,
679 ((ringbase >> 32) &
680 ~SSB_DMA_TRANSLATION_MASK)
a9770a81 681 | trans);
e4d6b795
MB		 682 } else {
683 u32 ringbase = (u32) (ring->dmabase);
684
685 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
686 >> SSB_DMA_TRANSLATION_SHIFT;
687 value = B43_DMA32_TXENABLE;
688 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
689 & B43_DMA32_TXADDREXT_MASK;
78c1ee7e
RM		 690 if (!parity)
691 value |= B43_DMA32_TXPARITYDISABLE;
e4d6b795
MB		 692 b43_dma_write(ring, B43_DMA32_TXCTL, value);
693 b43_dma_write(ring, B43_DMA32_TXRING,
694 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
695 | trans);
696 }
697 } else {
698 err = alloc_initial_descbuffers(ring);
699 if (err)
700 goto out;
b79caa68 701 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 702 u64 ringbase = (u64) (ring->dmabase);
703
704 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
705 >> SSB_DMA_TRANSLATION_SHIFT;
706 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
707 value |= B43_DMA64_RXENABLE;
708 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
709 & B43_DMA64_RXADDREXT_MASK;
78c1ee7e
RM		 710 if (!parity)
711 value |= B43_DMA64_RXPARITYDISABLE;
e4d6b795
MB		 712 b43_dma_write(ring, B43_DMA64_RXCTL, value);
713 b43_dma_write(ring, B43_DMA64_RXRINGLO,
714 (ringbase & 0xFFFFFFFF));
715 b43_dma_write(ring, B43_DMA64_RXRINGHI,
716 ((ringbase >> 32) &
717 ~SSB_DMA_TRANSLATION_MASK)
a9770a81 718 | trans);
013978b6
LF		 719 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
720 sizeof(struct b43_dmadesc64));
e4d6b795
MB		 721 } else {
722 u32 ringbase = (u32) (ring->dmabase);
723
724 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
725 >> SSB_DMA_TRANSLATION_SHIFT;
726 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
727 value |= B43_DMA32_RXENABLE;
728 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
729 & B43_DMA32_RXADDREXT_MASK;
78c1ee7e
RM		 730 if (!parity)
731 value |= B43_DMA32_RXPARITYDISABLE;
e4d6b795
MB		 732 b43_dma_write(ring, B43_DMA32_RXCTL, value);
733 b43_dma_write(ring, B43_DMA32_RXRING,
734 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
735 | trans);
013978b6
LF		 736 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
737 sizeof(struct b43_dmadesc32));
e4d6b795
MB		 738 }
739 }
740
013978b6 741out:
e4d6b795
MB		 742 return err;
743}
744
745/* Shutdown the DMA controller. */
746static void dmacontroller_cleanup(struct b43_dmaring *ring)
747{
748 if (ring->tx) {
749 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 750 ring->type);
751 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 752 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
753 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
754 } else
755 b43_dma_write(ring, B43_DMA32_TXRING, 0);
756 } else {
757 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
b79caa68
MB		 758 ring->type);
759 if (ring->type == B43_DMA_64BIT) {
e4d6b795
MB		 760 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
761 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
762 } else
763 b43_dma_write(ring, B43_DMA32_RXRING, 0);
764 }
765}
766
767static void free_all_descbuffers(struct b43_dmaring *ring)
768{
e4d6b795
MB		 769 struct b43_dmadesc_meta *meta;
770 int i;
771
772 if (!ring->used_slots)
773 return;
774 for (i = 0; i < ring->nr_slots; i++) {
9c1cacd2
LF		 775 /* get meta - ignore returned value */
776 ring->ops->idx2desc(ring, i, &meta);
e4d6b795 777
07681e21 778 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
e4d6b795
MB		 779 B43_WARN_ON(!ring->tx);
780 continue;
781 }
782 if (ring->tx) {
783 unmap_descbuffer(ring, meta->dmaaddr,
784 meta->skb->len, 1);
785 } else {
786 unmap_descbuffer(ring, meta->dmaaddr,
787 ring->rx_buffersize, 0);
788 }
789 free_descriptor_buffer(ring, meta);
790 }
791}
792
793static u64 supported_dma_mask(struct b43_wldev *dev)
794{
795 u32 tmp;
796 u16 mmio_base;
797
798 tmp = b43_read32(dev, SSB_TMSHIGH);
799 if (tmp & SSB_TMSHIGH_DMA64)
6a35528a 800 return DMA_BIT_MASK(64);
e4d6b795
MB		 801 mmio_base = b43_dmacontroller_base(0, 0);
802 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
803 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
804 if (tmp & B43_DMA32_TXADDREXT_MASK)
284901a9 805 return DMA_BIT_MASK(32);
e4d6b795 806
28b76796 807 return DMA_BIT_MASK(30);
e4d6b795
MB		 808}
809
5100d5ac
MB		 810static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
811{
28b76796 812 if (dmamask == DMA_BIT_MASK(30))
5100d5ac 813 return B43_DMA_30BIT;
284901a9 814 if (dmamask == DMA_BIT_MASK(32))
5100d5ac 815 return B43_DMA_32BIT;
6a35528a 816 if (dmamask == DMA_BIT_MASK(64))
5100d5ac
MB		 817 return B43_DMA_64BIT;
818 B43_WARN_ON(1);
819 return B43_DMA_30BIT;
820}
821
e4d6b795
MB		 822/* Main initialization function. */
823static
824struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
825 int controller_index,
b79caa68
MB		 826 int for_tx,
827 enum b43_dmatype type)
e4d6b795
MB		 828{
829 struct b43_dmaring *ring;
07681e21 830 int i, err;
e4d6b795
MB		 831 dma_addr_t dma_test;
832
833 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
834 if (!ring)
835 goto out;
836
028118a5 837 ring->nr_slots = B43_RXRING_SLOTS;
e4d6b795 838 if (for_tx)
028118a5 839 ring->nr_slots = B43_TXRING_SLOTS;
e4d6b795 840
028118a5 841 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
e4d6b795
MB		 842 GFP_KERNEL);
843 if (!ring->meta)
844 goto err_kfree_ring;
07681e21
MB		 845 for (i = 0; i < ring->nr_slots; i++)
846 ring->meta->skb = B43_DMA_PTR_POISON;
028118a5
MB		 847
848 ring->type = type;
849 ring->dev = dev;
850 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
851 ring->index = controller_index;
852 if (type == B43_DMA_64BIT)
853 ring->ops = &dma64_ops;
854 else
855 ring->ops = &dma32_ops;
e4d6b795 856 if (for_tx) {
028118a5
MB		 857 ring->tx = 1;
858 ring->current_slot = -1;
859 } else {
860 if (ring->index == 0) {
861 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
862 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
028118a5
MB		 863 } else
864 B43_WARN_ON(1);
865 }
028118a5
MB		 866#ifdef CONFIG_B43_DEBUG
867 ring->last_injected_overflow = jiffies;
868#endif
869
870 if (for_tx) {
2d071ca5
MB		 871 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
872 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
873
bdceeb2d 874 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
eb189d8b 875 b43_txhdr_size(dev),
e4d6b795
MB		 876 GFP_KERNEL);
877 if (!ring->txhdr_cache)
878 goto err_kfree_meta;
879
880 /* test for ability to dma to txhdr_cache */
a18c715e 881 dma_test = dma_map_single(dev->dev->dma_dev,
718e8898
FT		 882 ring->txhdr_cache,
883 b43_txhdr_size(dev),
884 DMA_TO_DEVICE);
e4d6b795 885
ffa9256a
MB		 886 if (b43_dma_mapping_error(ring, dma_test,
887 b43_txhdr_size(dev), 1)) {
e4d6b795
MB		 888 /* ugh realloc */
889 kfree(ring->txhdr_cache);
bdceeb2d 890 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
eb189d8b 891 b43_txhdr_size(dev),
e4d6b795
MB		 892 GFP_KERNEL | GFP_DMA);
893 if (!ring->txhdr_cache)
894 goto err_kfree_meta;
895
a18c715e 896 dma_test = dma_map_single(dev->dev->dma_dev,
718e8898
FT		 897 ring->txhdr_cache,
898 b43_txhdr_size(dev),
899 DMA_TO_DEVICE);
e4d6b795 900
b79caa68 901 if (b43_dma_mapping_error(ring, dma_test,
539e6f8c
MB		 902 b43_txhdr_size(dev), 1)) {
903
904 b43err(dev->wl,
905 "TXHDR DMA allocation failed\n");
e4d6b795 906 goto err_kfree_txhdr_cache;
539e6f8c 907 }
e4d6b795
MB		 908 }
909
a18c715e 910 dma_unmap_single(dev->dev->dma_dev,
718e8898
FT		 911 dma_test, b43_txhdr_size(dev),
912 DMA_TO_DEVICE);
e4d6b795
MB		 913 }
914
e4d6b795
MB		 915 err = alloc_ringmemory(ring);
916 if (err)
917 goto err_kfree_txhdr_cache;
918 err = dmacontroller_setup(ring);
919 if (err)
920 goto err_free_ringmemory;
921
922 out:
923 return ring;
924
925 err_free_ringmemory:
926 free_ringmemory(ring);
927 err_kfree_txhdr_cache:
928 kfree(ring->txhdr_cache);
929 err_kfree_meta:
930 kfree(ring->meta);
931 err_kfree_ring:
932 kfree(ring);
933 ring = NULL;
934 goto out;
935}
936
57df40d2
MB		 937#define divide(a, b) ({ \
938 typeof(a) __a = a; \
939 do_div(__a, b); \
940 __a; \
941 })
942
943#define modulo(a, b) ({ \
944 typeof(a) __a = a; \
945 do_div(__a, b); \
946 })
947
e4d6b795 948/* Main cleanup function. */
b27faf8e
MB		 949static void b43_destroy_dmaring(struct b43_dmaring *ring,
950 const char *ringname)
e4d6b795
MB		 951{
952 if (!ring)
953 return;
954
57df40d2
MB		 955#ifdef CONFIG_B43_DEBUG
956 {
957 /* Print some statistics. */
958 u64 failed_packets = ring->nr_failed_tx_packets;
959 u64 succeed_packets = ring->nr_succeed_tx_packets;
960 u64 nr_packets = failed_packets + succeed_packets;
961 u64 permille_failed = 0, average_tries = 0;
962
963 if (nr_packets)
964 permille_failed = divide(failed_packets * 1000, nr_packets);
965 if (nr_packets)
966 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
967
968 b43dbg(ring->dev->wl, "DMA-%u %s: "
969 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
970 "Average tries %llu.%02llu\n",
971 (unsigned int)(ring->type), ringname,
972 ring->max_used_slots,
973 ring->nr_slots,
974 (unsigned long long)failed_packets,
87d96114 975 (unsigned long long)nr_packets,
57df40d2
MB		 976 (unsigned long long)divide(permille_failed, 10),
977 (unsigned long long)modulo(permille_failed, 10),
978 (unsigned long long)divide(average_tries, 100),
979 (unsigned long long)modulo(average_tries, 100));
980 }
981#endif /* DEBUG */
982
e4d6b795
MB		 983 /* Device IRQs are disabled prior entering this function,
984 * so no need to take care of concurrency with rx handler stuff.
985 */
986 dmacontroller_cleanup(ring);
987 free_all_descbuffers(ring);
988 free_ringmemory(ring);
989
990 kfree(ring->txhdr_cache);
991 kfree(ring->meta);
992 kfree(ring);
993}
994
b27faf8e
MB		 995#define destroy_ring(dma, ring) do { \
996 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
997 (dma)->ring = NULL; \
998 } while (0)
999
e4d6b795
MB		 1000void b43_dma_free(struct b43_wldev *dev)
1001{
5100d5ac
MB		 1002 struct b43_dma *dma;
1003
1004 if (b43_using_pio_transfers(dev))
1005 return;
1006 dma = &dev->dma;
e4d6b795 1007
b27faf8e
MB		 1008 destroy_ring(dma, rx_ring);
1009 destroy_ring(dma, tx_ring_AC_BK);
1010 destroy_ring(dma, tx_ring_AC_BE);
1011 destroy_ring(dma, tx_ring_AC_VI);
1012 destroy_ring(dma, tx_ring_AC_VO);
1013 destroy_ring(dma, tx_ring_mcast);
e4d6b795
MB		 1014}
1015
1033b3ea
MB		 1016static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1017{
1018 u64 orig_mask = mask;
1019 bool fallback = 0;
1020 int err;
1021
1022 /* Try to set the DMA mask. If it fails, try falling back to a
1023 * lower mask, as we can always also support a lower one. */
1024 while (1) {
a18c715e 1025 err = dma_set_mask(dev->dev->dma_dev, mask);
718e8898 1026 if (!err) {
a18c715e 1027 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
718e8898
FT		 1028 if (!err)
1029 break;
1030 }
6a35528a 1031 if (mask == DMA_BIT_MASK(64)) {
284901a9 1032 mask = DMA_BIT_MASK(32);
1033b3ea
MB		 1033 fallback = 1;
1034 continue;
1035 }
284901a9 1036 if (mask == DMA_BIT_MASK(32)) {
28b76796 1037 mask = DMA_BIT_MASK(30);
1033b3ea
MB		 1038 fallback = 1;
1039 continue;
1040 }
1041 b43err(dev->wl, "The machine/kernel does not support "
1042 "the required %u-bit DMA mask\n",
1043 (unsigned int)dma_mask_to_engine_type(orig_mask));
1044 return -EOPNOTSUPP;
1045 }
1046 if (fallback) {
1047 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1048 (unsigned int)dma_mask_to_engine_type(orig_mask),
1049 (unsigned int)dma_mask_to_engine_type(mask));
1050 }
1051
1052 return 0;
1053}
1054
e4d6b795
MB		 1055int b43_dma_init(struct b43_wldev *dev)
1056{
1057 struct b43_dma *dma = &dev->dma;
e4d6b795
MB		 1058 int err;
1059 u64 dmamask;
b79caa68 1060 enum b43_dmatype type;
e4d6b795
MB		 1061
1062 dmamask = supported_dma_mask(dev);
5100d5ac 1063 type = dma_mask_to_engine_type(dmamask);
1033b3ea
MB		 1064 err = b43_dma_set_mask(dev, dmamask);
1065 if (err)
1066 return err;
6cbab0d9
RM		 1067
1068 switch (dev->dev->bus_type) {
eb90e9e8
RM		 1069#ifdef CONFIG_B43_BCMA
1070 case B43_BUS_BCMA:
1071 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1072 break;
1073#endif
6cbab0d9
RM		 1074#ifdef CONFIG_B43_SSB
1075 case B43_BUS_SSB:
1076 dma->translation = ssb_dma_translation(dev->dev->sdev);
1077 break;
1078#endif
1079 }
e4d6b795 1080
78c1ee7e
RM		 1081 dma->parity = true;
1082#ifdef CONFIG_B43_BCMA
1083 /* TODO: find out which SSB devices need disabling parity */
1084 if (dev->dev->bus_type == B43_BUS_BCMA)
1085 dma->parity = false;
1086#endif
1087
e4d6b795
MB		 1088 err = -ENOMEM;
1089 /* setup TX DMA channels. */
b27faf8e
MB		 1090 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1091 if (!dma->tx_ring_AC_BK)
e4d6b795 1092 goto out;
e4d6b795 1093
b27faf8e
MB		 1094 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1095 if (!dma->tx_ring_AC_BE)
1096 goto err_destroy_bk;
e4d6b795 1097
b27faf8e
MB		 1098 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1099 if (!dma->tx_ring_AC_VI)
1100 goto err_destroy_be;
e4d6b795 1101
b27faf8e
MB		 1102 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1103 if (!dma->tx_ring_AC_VO)
1104 goto err_destroy_vi;
e4d6b795 1105
b27faf8e
MB		 1106 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1107 if (!dma->tx_ring_mcast)
1108 goto err_destroy_vo;
e4d6b795 1109
b27faf8e
MB		 1110 /* setup RX DMA channel. */
1111 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1112 if (!dma->rx_ring)
1113 goto err_destroy_mcast;
e4d6b795 1114
b27faf8e 1115 /* No support for the TX status DMA ring. */
21d889d4 1116 B43_WARN_ON(dev->dev->core_rev < 5);
e4d6b795 1117
b79caa68
MB		 1118 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1119 (unsigned int)type);
e4d6b795 1120 err = 0;
b27faf8e 1121out:
e4d6b795
MB		 1122 return err;
1123
b27faf8e
MB		 1124err_destroy_mcast:
1125 destroy_ring(dma, tx_ring_mcast);
1126err_destroy_vo:
1127 destroy_ring(dma, tx_ring_AC_VO);
1128err_destroy_vi:
1129 destroy_ring(dma, tx_ring_AC_VI);
1130err_destroy_be:
1131 destroy_ring(dma, tx_ring_AC_BE);
1132err_destroy_bk:
1133 destroy_ring(dma, tx_ring_AC_BK);
1134 return err;
e4d6b795
MB		 1135}
1136
1137/* Generate a cookie for the TX header. */
1138static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1139{
b27faf8e 1140 u16 cookie;
e4d6b795
MB		 1141
1142 /* Use the upper 4 bits of the cookie as
1143 * DMA controller ID and store the slot number
1144 * in the lower 12 bits.
1145 * Note that the cookie must never be 0, as this
1146 * is a special value used in RX path.
280d0e16
MB		 1147 * It can also not be 0xFFFF because that is special
1148 * for multicast frames.
e4d6b795 1149 */
b27faf8e 1150 cookie = (((u16)ring->index + 1) << 12);
e4d6b795 1151 B43_WARN_ON(slot & ~0x0FFF);
b27faf8e 1152 cookie |= (u16)slot;
e4d6b795
MB		 1153
1154 return cookie;
1155}
1156
1157/* Inspect a cookie and find out to which controller/slot it belongs. */
1158static
1159struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1160{
1161 struct b43_dma *dma = &dev->dma;
1162 struct b43_dmaring *ring = NULL;
1163
1164 switch (cookie & 0xF000) {
280d0e16 1165 case 0x1000:
b27faf8e 1166 ring = dma->tx_ring_AC_BK;
e4d6b795 1167 break;
280d0e16 1168 case 0x2000:
b27faf8e 1169 ring = dma->tx_ring_AC_BE;
e4d6b795 1170 break;
280d0e16 1171 case 0x3000:
b27faf8e 1172 ring = dma->tx_ring_AC_VI;
e4d6b795 1173 break;
280d0e16 1174 case 0x4000:
b27faf8e 1175 ring = dma->tx_ring_AC_VO;
e4d6b795 1176 break;
280d0e16 1177 case 0x5000:
b27faf8e 1178 ring = dma->tx_ring_mcast;
e4d6b795 1179 break;
e4d6b795
MB		 1180 }
1181 *slot = (cookie & 0x0FFF);
07681e21
MB		 1182 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1183 b43dbg(dev->wl, "TX-status contains "
1184 "invalid cookie: 0x%04X\n", cookie);
1185 return NULL;
1186 }
e4d6b795
MB		 1187
1188 return ring;
1189}
1190
1191static int dma_tx_fragment(struct b43_dmaring *ring,
f54a5202 1192 struct sk_buff *skb)
e4d6b795
MB		 1193{
1194 const struct b43_dma_ops *ops = ring->ops;
e039fa4a 1195 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f54a5202 1196 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
e4d6b795 1197 u8 *header;
09552ccd 1198 int slot, old_top_slot, old_used_slots;
e4d6b795
MB		 1199 int err;
1200 struct b43_dmadesc_generic *desc;
1201 struct b43_dmadesc_meta *meta;
1202 struct b43_dmadesc_meta *meta_hdr;
280d0e16 1203 u16 cookie;
eb189d8b 1204 size_t hdrsize = b43_txhdr_size(ring->dev);
e4d6b795 1205
bdceeb2d
MB		 1206 /* Important note: If the number of used DMA slots per TX frame
1207 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1208 * the file has to be updated, too!
1209 */
e4d6b795 1210
09552ccd
MB		 1211 old_top_slot = ring->current_slot;
1212 old_used_slots = ring->used_slots;
1213
e4d6b795
MB		 1214 /* Get a slot for the header. */
1215 slot = request_slot(ring);
1216 desc = ops->idx2desc(ring, slot, &meta_hdr);
1217 memset(meta_hdr, 0, sizeof(*meta_hdr));
1218
bdceeb2d 1219 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
280d0e16 1220 cookie = generate_cookie(ring, slot);
09552ccd 1221 err = b43_generate_txhdr(ring->dev, header,
035d0243 1222 skb, info, cookie);
09552ccd
MB		 1223 if (unlikely(err)) {
1224 ring->current_slot = old_top_slot;
1225 ring->used_slots = old_used_slots;
1226 return err;
1227 }
e4d6b795
MB		 1228
1229 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
eb189d8b 1230 hdrsize, 1);
ffa9256a 1231 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
09552ccd
MB		 1232 ring->current_slot = old_top_slot;
1233 ring->used_slots = old_used_slots;
e4d6b795 1234 return -EIO;
09552ccd 1235 }
e4d6b795 1236 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
eb189d8b 1237 hdrsize, 1, 0, 0);
e4d6b795
MB		 1238
1239 /* Get a slot for the payload. */
1240 slot = request_slot(ring);
1241 desc = ops->idx2desc(ring, slot, &meta);
1242 memset(meta, 0, sizeof(*meta));
1243
e4d6b795
MB		 1244 meta->skb = skb;
1245 meta->is_last_fragment = 1;
f54a5202 1246 priv_info->bouncebuffer = NULL;
e4d6b795
MB		 1247
1248 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1249 /* create a bounce buffer in zone_dma on mapping failure. */
ffa9256a 1250 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
a61aac7c
JL		 1251 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1252 GFP_ATOMIC | GFP_DMA);
f54a5202 1253 if (!priv_info->bouncebuffer) {
09552ccd
MB		 1254 ring->current_slot = old_top_slot;
1255 ring->used_slots = old_used_slots;
e4d6b795
MB		 1256 err = -ENOMEM;
1257 goto out_unmap_hdr;
1258 }
1259
f54a5202 1260 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
ffa9256a 1261 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
f54a5202
MB		 1262 kfree(priv_info->bouncebuffer);
1263 priv_info->bouncebuffer = NULL;
09552ccd
MB		 1264 ring->current_slot = old_top_slot;
1265 ring->used_slots = old_used_slots;
e4d6b795 1266 err = -EIO;
f54a5202 1267 goto out_unmap_hdr;
e4d6b795
MB		 1268 }
1269 }
1270
1271 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1272
e039fa4a 1273 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
280d0e16
MB		 1274 /* Tell the firmware about the cookie of the last
1275 * mcast frame, so it can clear the more-data bit in it. */
1276 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1277 B43_SHM_SH_MCASTCOOKIE, cookie);
1278 }
e4d6b795
MB		 1279 /* Now transfer the whole frame. */
1280 wmb();
1281 ops->poke_tx(ring, next_slot(ring, slot));
1282 return 0;
1283
280d0e16 1284out_unmap_hdr:
e4d6b795 1285 unmap_descbuffer(ring, meta_hdr->dmaaddr,
eb189d8b 1286 hdrsize, 1);
e4d6b795
MB		 1287 return err;
1288}
1289
1290static inline int should_inject_overflow(struct b43_dmaring *ring)
1291{
1292#ifdef CONFIG_B43_DEBUG
1293 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1294 /* Check if we should inject another ringbuffer overflow
1295 * to test handling of this situation in the stack. */
1296 unsigned long next_overflow;
1297
1298 next_overflow = ring->last_injected_overflow + HZ;
1299 if (time_after(jiffies, next_overflow)) {
1300 ring->last_injected_overflow = jiffies;
1301 b43dbg(ring->dev->wl,
1302 "Injecting TX ring overflow on "
1303 "DMA controller %d\n", ring->index);
1304 return 1;
1305 }
1306 }
1307#endif /* CONFIG_B43_DEBUG */
1308 return 0;
1309}
1310
e6f5b934 1311/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
99da185a
JD		 1312static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1313 u8 queue_prio)
e6f5b934
MB		 1314{
1315 struct b43_dmaring *ring;
1316
403a3a13 1317 if (dev->qos_enabled) {
e6f5b934
MB		 1318 /* 0 = highest priority */
1319 switch (queue_prio) {
1320 default:
1321 B43_WARN_ON(1);
1322 /* fallthrough */
1323 case 0:
b27faf8e 1324 ring = dev->dma.tx_ring_AC_VO;
e6f5b934
MB		 1325 break;
1326 case 1:
b27faf8e 1327 ring = dev->dma.tx_ring_AC_VI;
e6f5b934
MB		 1328 break;
1329 case 2:
b27faf8e 1330 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1331 break;
1332 case 3:
b27faf8e 1333 ring = dev->dma.tx_ring_AC_BK;
e6f5b934
MB		 1334 break;
1335 }
1336 } else
b27faf8e 1337 ring = dev->dma.tx_ring_AC_BE;
e6f5b934
MB		 1338
1339 return ring;
1340}
1341
e039fa4a 1342int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
e4d6b795
MB		 1343{
1344 struct b43_dmaring *ring;
280d0e16 1345 struct ieee80211_hdr *hdr;
e4d6b795 1346 int err = 0;
e039fa4a 1347 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e4d6b795 1348
280d0e16 1349 hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 1350 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
280d0e16 1351 /* The multicast ring will be sent after the DTIM */
b27faf8e 1352 ring = dev->dma.tx_ring_mcast;
280d0e16
MB		 1353 /* Set the more-data bit. Ucode will clear it on
1354 * the last frame for us. */
1355 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1356 } else {
1357 /* Decide by priority where to put this frame. */
e2530083
JB		 1358 ring = select_ring_by_priority(
1359 dev, skb_get_queue_mapping(skb));
280d0e16
MB		 1360 }
1361
e4d6b795 1362 B43_WARN_ON(!ring->tx);
ca2d559e 1363
18c69510
LF		 1364 if (unlikely(ring->stopped)) {
1365 /* We get here only because of a bug in mac80211.
1366 * Because of a race, one packet may be queued after
1367 * the queue is stopped, thus we got called when we shouldn't.
1368 * For now, just refuse the transmit. */
1369 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1370 b43err(dev->wl, "Packet after queue stopped\n");
1371 err = -ENOSPC;
637dae3f 1372 goto out;
18c69510
LF		 1373 }
1374
1375 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1376 /* If we get here, we have a real error with the queue
1377 * full, but queues not stopped. */
1378 b43err(dev->wl, "DMA queue overflow\n");
e4d6b795 1379 err = -ENOSPC;
637dae3f 1380 goto out;
e4d6b795 1381 }
e4d6b795 1382
e6f5b934
MB		 1383 /* Assign the queue number to the ring (if not already done before)
1384 * so TX status handling can use it. The queue to ring mapping is
1385 * static, so we don't need to store it per frame. */
e2530083 1386 ring->queue_prio = skb_get_queue_mapping(skb);
e6f5b934 1387
f54a5202 1388 err = dma_tx_fragment(ring, skb);
09552ccd
MB		 1389 if (unlikely(err == -ENOKEY)) {
1390 /* Drop this packet, as we don't have the encryption key
1391 * anymore and must not transmit it unencrypted. */
1392 dev_kfree_skb_any(skb);
1393 err = 0;
637dae3f 1394 goto out;
09552ccd 1395 }
e4d6b795
MB		 1396 if (unlikely(err)) {
1397 b43err(dev->wl, "DMA tx mapping failure\n");
637dae3f 1398 goto out;
e4d6b795 1399 }
bdceeb2d 1400 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
e4d6b795
MB		 1401 should_inject_overflow(ring)) {
1402 /* This TX ring is full. */
e2530083 1403 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
e4d6b795
MB		 1404 ring->stopped = 1;
1405 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1406 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1407 }
1408 }
637dae3f 1409out:
e4d6b795
MB		 1410
1411 return err;
1412}
1413
1414void b43_dma_handle_txstatus(struct b43_wldev *dev,
1415 const struct b43_txstatus *status)
1416{
1417 const struct b43_dma_ops *ops;
1418 struct b43_dmaring *ring;
e4d6b795 1419 struct b43_dmadesc_meta *meta;
07681e21 1420 int slot, firstused;
5100d5ac 1421 bool frame_succeed;
e4d6b795
MB		 1422
1423 ring = parse_cookie(dev, status->cookie, &slot);
1424 if (unlikely(!ring))
1425 return;
e4d6b795 1426 B43_WARN_ON(!ring->tx);
07681e21
MB		 1427
1428 /* Sanity check: TX packets are processed in-order on one ring.
1429 * Check if the slot deduced from the cookie really is the first
1430 * used slot. */
1431 firstused = ring->current_slot - ring->used_slots + 1;
1432 if (firstused < 0)
1433 firstused = ring->nr_slots + firstused;
1434 if (unlikely(slot != firstused)) {
1435 /* This possibly is a firmware bug and will result in
1436 * malfunction, memory leaks and/or stall of DMA functionality. */
1437 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1438 "Expected %d, but got %d\n",
1439 ring->index, firstused, slot);
1440 return;
1441 }
1442
e4d6b795
MB		 1443 ops = ring->ops;
1444 while (1) {
07681e21 1445 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
9c1cacd2
LF		 1446 /* get meta - ignore returned value */
1447 ops->idx2desc(ring, slot, &meta);
e4d6b795 1448
07681e21
MB		 1449 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1450 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1451 "on ring %d\n",
1452 slot, firstused, ring->index);
1453 break;
1454 }
f54a5202
MB		 1455 if (meta->skb) {
1456 struct b43_private_tx_info *priv_info =
1457 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1458
1459 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1460 kfree(priv_info->bouncebuffer);
1461 priv_info->bouncebuffer = NULL;
1462 } else {
e4d6b795 1463 unmap_descbuffer(ring, meta->dmaaddr,
eb189d8b 1464 b43_txhdr_size(dev), 1);
f54a5202 1465 }
e4d6b795
MB		 1466
1467 if (meta->is_last_fragment) {
e039fa4a
JB		 1468 struct ieee80211_tx_info *info;
1469
07681e21
MB		 1470 if (unlikely(!meta->skb)) {
1471 /* This is a scatter-gather fragment of a frame, so
1472 * the skb pointer must not be NULL. */
1473 b43dbg(dev->wl, "TX status unexpected NULL skb "
1474 "at slot %d (first=%d) on ring %d\n",
1475 slot, firstused, ring->index);
1476 break;
1477 }
e039fa4a
JB		 1478
1479 info = IEEE80211_SKB_CB(meta->skb);
1480
e039fa4a
JB		 1481 /*
1482 * Call back to inform the ieee80211 subsystem about
1483 * the status of the transmission.
e4d6b795 1484 */
e6a9854b 1485 frame_succeed = b43_fill_txstatus_report(dev, info, status);
5100d5ac
MB		 1486#ifdef CONFIG_B43_DEBUG
1487 if (frame_succeed)
1488 ring->nr_succeed_tx_packets++;
1489 else
1490 ring->nr_failed_tx_packets++;
1491 ring->nr_total_packet_tries += status->frame_count;
1492#endif /* DEBUG */
ce6c4a13 1493 ieee80211_tx_status(dev->wl->hw, meta->skb);
e039fa4a 1494
07681e21
MB		 1495 /* skb will be freed by ieee80211_tx_status().
1496 * Poison our pointer. */
1497 meta->skb = B43_DMA_PTR_POISON;
e4d6b795
MB		 1498 } else {
1499 /* No need to call free_descriptor_buffer here, as
1500 * this is only the txhdr, which is not allocated.
1501 */
07681e21
MB		 1502 if (unlikely(meta->skb)) {
1503 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1504 "at slot %d (first=%d) on ring %d\n",
1505 slot, firstused, ring->index);
1506 break;
1507 }
e4d6b795
MB		 1508 }
1509
1510 /* Everything unmapped and free'd. So it's not used anymore. */
1511 ring->used_slots--;
1512
07681e21
MB		 1513 if (meta->is_last_fragment) {
1514 /* This is the last scatter-gather
1515 * fragment of the frame. We are done. */
e4d6b795 1516 break;
07681e21 1517 }
e4d6b795
MB		 1518 slot = next_slot(ring, slot);
1519 }
e4d6b795 1520 if (ring->stopped) {
bdceeb2d 1521 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
e6f5b934 1522 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
e4d6b795
MB		 1523 ring->stopped = 0;
1524 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1525 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1526 }
1527 }
e4d6b795
MB		 1528}
1529
e4d6b795
MB		 1530static void dma_rx(struct b43_dmaring *ring, int *slot)
1531{
1532 const struct b43_dma_ops *ops = ring->ops;
1533 struct b43_dmadesc_generic *desc;
1534 struct b43_dmadesc_meta *meta;
1535 struct b43_rxhdr_fw4 *rxhdr;
1536 struct sk_buff *skb;
1537 u16 len;
1538 int err;
1539 dma_addr_t dmaaddr;
1540
1541 desc = ops->idx2desc(ring, *slot, &meta);
1542
1543 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1544 skb = meta->skb;
1545
e4d6b795
MB		 1546 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1547 len = le16_to_cpu(rxhdr->frame_len);
1548 if (len == 0) {
1549 int i = 0;
1550
1551 do {
1552 udelay(2);
1553 barrier();
1554 len = le16_to_cpu(rxhdr->frame_len);
1555 } while (len == 0 && i++ < 5);
1556 if (unlikely(len == 0)) {
cf68636a
MB		 1557 dmaaddr = meta->dmaaddr;
1558 goto drop_recycle_buffer;
e4d6b795
MB		 1559 }
1560 }
ec9a1d8c
MB		 1561 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1562 /* Something went wrong with the DMA.
1563 * The device did not touch the buffer and did not overwrite the poison. */
1564 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
cf68636a
MB		 1565 dmaaddr = meta->dmaaddr;
1566 goto drop_recycle_buffer;
ec9a1d8c 1567 }
c85ce65e 1568 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
e4d6b795
MB		 1569 /* The data did not fit into one descriptor buffer
1570 * and is split over multiple buffers.
1571 * This should never happen, as we try to allocate buffers
1572 * big enough. So simply ignore this packet.
1573 */
1574 int cnt = 0;
1575 s32 tmp = len;
1576
1577 while (1) {
1578 desc = ops->idx2desc(ring, *slot, &meta);
1579 /* recycle the descriptor buffer. */
cf68636a 1580 b43_poison_rx_buffer(ring, meta->skb);
e4d6b795
MB		 1581 sync_descbuffer_for_device(ring, meta->dmaaddr,
1582 ring->rx_buffersize);
1583 *slot = next_slot(ring, *slot);
1584 cnt++;
1585 tmp -= ring->rx_buffersize;
1586 if (tmp <= 0)
1587 break;
1588 }
1589 b43err(ring->dev->wl, "DMA RX buffer too small "
1590 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1591 len, ring->rx_buffersize, cnt);
1592 goto drop;
1593 }
1594
1595 dmaaddr = meta->dmaaddr;
1596 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1597 if (unlikely(err)) {
1598 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
cf68636a 1599 goto drop_recycle_buffer;
e4d6b795
MB		 1600 }
1601
1602 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1603 skb_put(skb, len + ring->frameoffset);
1604 skb_pull(skb, ring->frameoffset);
1605
1606 b43_rx(ring->dev, skb, rxhdr);
b27faf8e 1607drop:
e4d6b795 1608 return;
cf68636a
MB		 1609
1610drop_recycle_buffer:
1611 /* Poison and recycle the RX buffer. */
1612 b43_poison_rx_buffer(ring, skb);
1613 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
e4d6b795
MB		 1614}
1615
1616void b43_dma_rx(struct b43_dmaring *ring)
1617{
1618 const struct b43_dma_ops *ops = ring->ops;
1619 int slot, current_slot;
1620 int used_slots = 0;
1621
1622 B43_WARN_ON(ring->tx);
1623 current_slot = ops->get_current_rxslot(ring);
1624 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1625
1626 slot = ring->current_slot;
1627 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1628 dma_rx(ring, &slot);
1629 update_max_used_slots(ring, ++used_slots);
1630 }
73e6cdcf 1631 wmb();
e4d6b795
MB		 1632 ops->set_current_rxslot(ring, slot);
1633 ring->current_slot = slot;
1634}
1635
1636static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1637{
e4d6b795
MB		 1638 B43_WARN_ON(!ring->tx);
1639 ring->ops->tx_suspend(ring);
e4d6b795
MB		 1640}
1641
1642static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1643{
e4d6b795
MB		 1644 B43_WARN_ON(!ring->tx);
1645 ring->ops->tx_resume(ring);
e4d6b795
MB		 1646}
1647
1648void b43_dma_tx_suspend(struct b43_wldev *dev)
1649{
1650 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
b27faf8e
MB		 1651 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1652 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1653 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1654 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1655 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
e4d6b795
MB		 1656}
1657
1658void b43_dma_tx_resume(struct b43_wldev *dev)
1659{
b27faf8e
MB		 1660 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1661 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1662 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1663 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1664 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
e4d6b795
MB		 1665 b43_power_saving_ctl_bits(dev, 0);
1666}
5100d5ac 1667
5100d5ac
MB		 1668static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1669 u16 mmio_base, bool enable)
1670{
1671 u32 ctl;
1672
1673 if (type == B43_DMA_64BIT) {
1674 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1675 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1676 if (enable)
1677 ctl |= B43_DMA64_RXDIRECTFIFO;
1678 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1679 } else {
1680 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1681 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1682 if (enable)
1683 ctl |= B43_DMA32_RXDIRECTFIFO;
1684 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1685 }
1686}
1687
1688/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1689 * This is called from PIO code, so DMA structures are not available. */
1690void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1691 unsigned int engine_index, bool enable)
1692{
1693 enum b43_dmatype type;
1694 u16 mmio_base;
1695
1696 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1697
1698 mmio_base = b43_dmacontroller_base(type, engine_index);
1699 direct_fifo_rx(dev, type, mmio_base, enable);
1700}
Linux kernel - Deliverables
This page took 0.624447 seconds and 5 git commands to generate.