Commit | Line | Data |
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e4d6b795 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | ||
5 | DMA ringbuffer and descriptor allocation/management | |
6 | ||
7 | Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> | |
8 | ||
9 | Some code in this file is derived from the b44.c driver | |
10 | Copyright (C) 2002 David S. Miller | |
11 | Copyright (C) Pekka Pietikainen | |
12 | ||
13 | This program is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2 of the License, or | |
16 | (at your option) any later version. | |
17 | ||
18 | This program is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with this program; see the file COPYING. If not, write to | |
25 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
26 | Boston, MA 02110-1301, USA. | |
27 | ||
28 | */ | |
29 | ||
30 | #include "b43.h" | |
31 | #include "dma.h" | |
32 | #include "main.h" | |
33 | #include "debugfs.h" | |
34 | #include "xmit.h" | |
35 | ||
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/skbuff.h> | |
280d0e16 MB |
40 | #include <linux/etherdevice.h> |
41 | ||
e4d6b795 MB |
42 | |
43 | /* 32bit DMA ops. */ | |
44 | static | |
45 | struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring, | |
46 | int slot, | |
47 | struct b43_dmadesc_meta **meta) | |
48 | { | |
49 | struct b43_dmadesc32 *desc; | |
50 | ||
51 | *meta = &(ring->meta[slot]); | |
52 | desc = ring->descbase; | |
53 | desc = &(desc[slot]); | |
54 | ||
55 | return (struct b43_dmadesc_generic *)desc; | |
56 | } | |
57 | ||
58 | static void op32_fill_descriptor(struct b43_dmaring *ring, | |
59 | struct b43_dmadesc_generic *desc, | |
60 | dma_addr_t dmaaddr, u16 bufsize, | |
61 | int start, int end, int irq) | |
62 | { | |
63 | struct b43_dmadesc32 *descbase = ring->descbase; | |
64 | int slot; | |
65 | u32 ctl; | |
66 | u32 addr; | |
67 | u32 addrext; | |
68 | ||
69 | slot = (int)(&(desc->dma32) - descbase); | |
70 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
71 | ||
72 | addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK); | |
73 | addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK) | |
74 | >> SSB_DMA_TRANSLATION_SHIFT; | |
75 | addr |= ssb_dma_translation(ring->dev->dev); | |
76 | ctl = (bufsize - ring->frameoffset) | |
77 | & B43_DMA32_DCTL_BYTECNT; | |
78 | if (slot == ring->nr_slots - 1) | |
79 | ctl |= B43_DMA32_DCTL_DTABLEEND; | |
80 | if (start) | |
81 | ctl |= B43_DMA32_DCTL_FRAMESTART; | |
82 | if (end) | |
83 | ctl |= B43_DMA32_DCTL_FRAMEEND; | |
84 | if (irq) | |
85 | ctl |= B43_DMA32_DCTL_IRQ; | |
86 | ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT) | |
87 | & B43_DMA32_DCTL_ADDREXT_MASK; | |
88 | ||
89 | desc->dma32.control = cpu_to_le32(ctl); | |
90 | desc->dma32.address = cpu_to_le32(addr); | |
91 | } | |
92 | ||
93 | static void op32_poke_tx(struct b43_dmaring *ring, int slot) | |
94 | { | |
95 | b43_dma_write(ring, B43_DMA32_TXINDEX, | |
96 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
97 | } | |
98 | ||
99 | static void op32_tx_suspend(struct b43_dmaring *ring) | |
100 | { | |
101 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
102 | | B43_DMA32_TXSUSPEND); | |
103 | } | |
104 | ||
105 | static void op32_tx_resume(struct b43_dmaring *ring) | |
106 | { | |
107 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
108 | & ~B43_DMA32_TXSUSPEND); | |
109 | } | |
110 | ||
111 | static int op32_get_current_rxslot(struct b43_dmaring *ring) | |
112 | { | |
113 | u32 val; | |
114 | ||
115 | val = b43_dma_read(ring, B43_DMA32_RXSTATUS); | |
116 | val &= B43_DMA32_RXDPTR; | |
117 | ||
118 | return (val / sizeof(struct b43_dmadesc32)); | |
119 | } | |
120 | ||
121 | static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
122 | { | |
123 | b43_dma_write(ring, B43_DMA32_RXINDEX, | |
124 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
125 | } | |
126 | ||
127 | static const struct b43_dma_ops dma32_ops = { | |
128 | .idx2desc = op32_idx2desc, | |
129 | .fill_descriptor = op32_fill_descriptor, | |
130 | .poke_tx = op32_poke_tx, | |
131 | .tx_suspend = op32_tx_suspend, | |
132 | .tx_resume = op32_tx_resume, | |
133 | .get_current_rxslot = op32_get_current_rxslot, | |
134 | .set_current_rxslot = op32_set_current_rxslot, | |
135 | }; | |
136 | ||
137 | /* 64bit DMA ops. */ | |
138 | static | |
139 | struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring, | |
140 | int slot, | |
141 | struct b43_dmadesc_meta **meta) | |
142 | { | |
143 | struct b43_dmadesc64 *desc; | |
144 | ||
145 | *meta = &(ring->meta[slot]); | |
146 | desc = ring->descbase; | |
147 | desc = &(desc[slot]); | |
148 | ||
149 | return (struct b43_dmadesc_generic *)desc; | |
150 | } | |
151 | ||
152 | static void op64_fill_descriptor(struct b43_dmaring *ring, | |
153 | struct b43_dmadesc_generic *desc, | |
154 | dma_addr_t dmaaddr, u16 bufsize, | |
155 | int start, int end, int irq) | |
156 | { | |
157 | struct b43_dmadesc64 *descbase = ring->descbase; | |
158 | int slot; | |
159 | u32 ctl0 = 0, ctl1 = 0; | |
160 | u32 addrlo, addrhi; | |
161 | u32 addrext; | |
162 | ||
163 | slot = (int)(&(desc->dma64) - descbase); | |
164 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
165 | ||
166 | addrlo = (u32) (dmaaddr & 0xFFFFFFFF); | |
167 | addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); | |
168 | addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) | |
169 | >> SSB_DMA_TRANSLATION_SHIFT; | |
013978b6 | 170 | addrhi |= (ssb_dma_translation(ring->dev->dev) << 1); |
e4d6b795 MB |
171 | if (slot == ring->nr_slots - 1) |
172 | ctl0 |= B43_DMA64_DCTL0_DTABLEEND; | |
173 | if (start) | |
174 | ctl0 |= B43_DMA64_DCTL0_FRAMESTART; | |
175 | if (end) | |
176 | ctl0 |= B43_DMA64_DCTL0_FRAMEEND; | |
177 | if (irq) | |
178 | ctl0 |= B43_DMA64_DCTL0_IRQ; | |
179 | ctl1 |= (bufsize - ring->frameoffset) | |
180 | & B43_DMA64_DCTL1_BYTECNT; | |
181 | ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) | |
182 | & B43_DMA64_DCTL1_ADDREXT_MASK; | |
183 | ||
184 | desc->dma64.control0 = cpu_to_le32(ctl0); | |
185 | desc->dma64.control1 = cpu_to_le32(ctl1); | |
186 | desc->dma64.address_low = cpu_to_le32(addrlo); | |
187 | desc->dma64.address_high = cpu_to_le32(addrhi); | |
188 | } | |
189 | ||
190 | static void op64_poke_tx(struct b43_dmaring *ring, int slot) | |
191 | { | |
192 | b43_dma_write(ring, B43_DMA64_TXINDEX, | |
193 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
194 | } | |
195 | ||
196 | static void op64_tx_suspend(struct b43_dmaring *ring) | |
197 | { | |
198 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
199 | | B43_DMA64_TXSUSPEND); | |
200 | } | |
201 | ||
202 | static void op64_tx_resume(struct b43_dmaring *ring) | |
203 | { | |
204 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
205 | & ~B43_DMA64_TXSUSPEND); | |
206 | } | |
207 | ||
208 | static int op64_get_current_rxslot(struct b43_dmaring *ring) | |
209 | { | |
210 | u32 val; | |
211 | ||
212 | val = b43_dma_read(ring, B43_DMA64_RXSTATUS); | |
213 | val &= B43_DMA64_RXSTATDPTR; | |
214 | ||
215 | return (val / sizeof(struct b43_dmadesc64)); | |
216 | } | |
217 | ||
218 | static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
219 | { | |
220 | b43_dma_write(ring, B43_DMA64_RXINDEX, | |
221 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
222 | } | |
223 | ||
224 | static const struct b43_dma_ops dma64_ops = { | |
225 | .idx2desc = op64_idx2desc, | |
226 | .fill_descriptor = op64_fill_descriptor, | |
227 | .poke_tx = op64_poke_tx, | |
228 | .tx_suspend = op64_tx_suspend, | |
229 | .tx_resume = op64_tx_resume, | |
230 | .get_current_rxslot = op64_get_current_rxslot, | |
231 | .set_current_rxslot = op64_set_current_rxslot, | |
232 | }; | |
233 | ||
234 | static inline int free_slots(struct b43_dmaring *ring) | |
235 | { | |
236 | return (ring->nr_slots - ring->used_slots); | |
237 | } | |
238 | ||
239 | static inline int next_slot(struct b43_dmaring *ring, int slot) | |
240 | { | |
241 | B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); | |
242 | if (slot == ring->nr_slots - 1) | |
243 | return 0; | |
244 | return slot + 1; | |
245 | } | |
246 | ||
247 | static inline int prev_slot(struct b43_dmaring *ring, int slot) | |
248 | { | |
249 | B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); | |
250 | if (slot == 0) | |
251 | return ring->nr_slots - 1; | |
252 | return slot - 1; | |
253 | } | |
254 | ||
255 | #ifdef CONFIG_B43_DEBUG | |
256 | static void update_max_used_slots(struct b43_dmaring *ring, | |
257 | int current_used_slots) | |
258 | { | |
259 | if (current_used_slots <= ring->max_used_slots) | |
260 | return; | |
261 | ring->max_used_slots = current_used_slots; | |
262 | if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) { | |
263 | b43dbg(ring->dev->wl, | |
264 | "max_used_slots increased to %d on %s ring %d\n", | |
265 | ring->max_used_slots, | |
266 | ring->tx ? "TX" : "RX", ring->index); | |
267 | } | |
268 | } | |
269 | #else | |
270 | static inline | |
271 | void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots) | |
272 | { | |
273 | } | |
274 | #endif /* DEBUG */ | |
275 | ||
276 | /* Request a slot for usage. */ | |
277 | static inline int request_slot(struct b43_dmaring *ring) | |
278 | { | |
279 | int slot; | |
280 | ||
281 | B43_WARN_ON(!ring->tx); | |
282 | B43_WARN_ON(ring->stopped); | |
283 | B43_WARN_ON(free_slots(ring) == 0); | |
284 | ||
285 | slot = next_slot(ring, ring->current_slot); | |
286 | ring->current_slot = slot; | |
287 | ring->used_slots++; | |
288 | ||
289 | update_max_used_slots(ring, ring->used_slots); | |
290 | ||
291 | return slot; | |
292 | } | |
293 | ||
b79caa68 | 294 | static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx) |
e4d6b795 MB |
295 | { |
296 | static const u16 map64[] = { | |
297 | B43_MMIO_DMA64_BASE0, | |
298 | B43_MMIO_DMA64_BASE1, | |
299 | B43_MMIO_DMA64_BASE2, | |
300 | B43_MMIO_DMA64_BASE3, | |
301 | B43_MMIO_DMA64_BASE4, | |
302 | B43_MMIO_DMA64_BASE5, | |
303 | }; | |
304 | static const u16 map32[] = { | |
305 | B43_MMIO_DMA32_BASE0, | |
306 | B43_MMIO_DMA32_BASE1, | |
307 | B43_MMIO_DMA32_BASE2, | |
308 | B43_MMIO_DMA32_BASE3, | |
309 | B43_MMIO_DMA32_BASE4, | |
310 | B43_MMIO_DMA32_BASE5, | |
311 | }; | |
312 | ||
b79caa68 | 313 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
314 | B43_WARN_ON(!(controller_idx >= 0 && |
315 | controller_idx < ARRAY_SIZE(map64))); | |
316 | return map64[controller_idx]; | |
317 | } | |
318 | B43_WARN_ON(!(controller_idx >= 0 && | |
319 | controller_idx < ARRAY_SIZE(map32))); | |
320 | return map32[controller_idx]; | |
321 | } | |
322 | ||
323 | static inline | |
324 | dma_addr_t map_descbuffer(struct b43_dmaring *ring, | |
325 | unsigned char *buf, size_t len, int tx) | |
326 | { | |
327 | dma_addr_t dmaaddr; | |
328 | ||
329 | if (tx) { | |
330 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
331 | buf, len, DMA_TO_DEVICE); | |
332 | } else { | |
333 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
334 | buf, len, DMA_FROM_DEVICE); | |
335 | } | |
336 | ||
337 | return dmaaddr; | |
338 | } | |
339 | ||
340 | static inline | |
341 | void unmap_descbuffer(struct b43_dmaring *ring, | |
342 | dma_addr_t addr, size_t len, int tx) | |
343 | { | |
344 | if (tx) { | |
345 | dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE); | |
346 | } else { | |
347 | dma_unmap_single(ring->dev->dev->dev, | |
348 | addr, len, DMA_FROM_DEVICE); | |
349 | } | |
350 | } | |
351 | ||
352 | static inline | |
353 | void sync_descbuffer_for_cpu(struct b43_dmaring *ring, | |
354 | dma_addr_t addr, size_t len) | |
355 | { | |
356 | B43_WARN_ON(ring->tx); | |
357 | dma_sync_single_for_cpu(ring->dev->dev->dev, | |
358 | addr, len, DMA_FROM_DEVICE); | |
359 | } | |
360 | ||
361 | static inline | |
362 | void sync_descbuffer_for_device(struct b43_dmaring *ring, | |
363 | dma_addr_t addr, size_t len) | |
364 | { | |
365 | B43_WARN_ON(ring->tx); | |
366 | dma_sync_single_for_device(ring->dev->dev->dev, | |
367 | addr, len, DMA_FROM_DEVICE); | |
368 | } | |
369 | ||
370 | static inline | |
371 | void free_descriptor_buffer(struct b43_dmaring *ring, | |
372 | struct b43_dmadesc_meta *meta) | |
373 | { | |
374 | if (meta->skb) { | |
375 | dev_kfree_skb_any(meta->skb); | |
376 | meta->skb = NULL; | |
377 | } | |
378 | } | |
379 | ||
380 | static int alloc_ringmemory(struct b43_dmaring *ring) | |
381 | { | |
382 | struct device *dev = ring->dev->dev->dev; | |
013978b6 LF |
383 | gfp_t flags = GFP_KERNEL; |
384 | ||
385 | /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K | |
386 | * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing | |
387 | * has shown that 4K is sufficient for the latter as long as the buffer | |
388 | * does not cross an 8K boundary. | |
389 | * | |
390 | * For unknown reasons - possibly a hardware error - the BCM4311 rev | |
391 | * 02, which uses 64-bit DMA, needs the ring buffer in very low memory, | |
392 | * which accounts for the GFP_DMA flag below. | |
393 | */ | |
b79caa68 | 394 | if (ring->type == B43_DMA_64BIT) |
013978b6 | 395 | flags |= GFP_DMA; |
e4d6b795 | 396 | ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE, |
013978b6 | 397 | &(ring->dmabase), flags); |
e4d6b795 MB |
398 | if (!ring->descbase) { |
399 | b43err(ring->dev->wl, "DMA ringmemory allocation failed\n"); | |
400 | return -ENOMEM; | |
401 | } | |
402 | memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static void free_ringmemory(struct b43_dmaring *ring) | |
408 | { | |
409 | struct device *dev = ring->dev->dev->dev; | |
410 | ||
411 | dma_free_coherent(dev, B43_DMA_RINGMEMSIZE, | |
412 | ring->descbase, ring->dmabase); | |
413 | } | |
414 | ||
415 | /* Reset the RX DMA channel */ | |
b79caa68 MB |
416 | static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, |
417 | enum b43_dmatype type) | |
e4d6b795 MB |
418 | { |
419 | int i; | |
420 | u32 value; | |
421 | u16 offset; | |
422 | ||
423 | might_sleep(); | |
424 | ||
b79caa68 | 425 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL; |
e4d6b795 MB |
426 | b43_write32(dev, mmio_base + offset, 0); |
427 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
428 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS : |
429 | B43_DMA32_RXSTATUS; | |
e4d6b795 | 430 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 431 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
432 | value &= B43_DMA64_RXSTAT; |
433 | if (value == B43_DMA64_RXSTAT_DISABLED) { | |
434 | i = -1; | |
435 | break; | |
436 | } | |
437 | } else { | |
438 | value &= B43_DMA32_RXSTATE; | |
439 | if (value == B43_DMA32_RXSTAT_DISABLED) { | |
440 | i = -1; | |
441 | break; | |
442 | } | |
443 | } | |
444 | msleep(1); | |
445 | } | |
446 | if (i != -1) { | |
447 | b43err(dev->wl, "DMA RX reset timed out\n"); | |
448 | return -ENODEV; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
013978b6 | 454 | /* Reset the TX DMA channel */ |
b79caa68 MB |
455 | static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, |
456 | enum b43_dmatype type) | |
e4d6b795 MB |
457 | { |
458 | int i; | |
459 | u32 value; | |
460 | u16 offset; | |
461 | ||
462 | might_sleep(); | |
463 | ||
464 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
465 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
466 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 467 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 468 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
469 | value &= B43_DMA64_TXSTAT; |
470 | if (value == B43_DMA64_TXSTAT_DISABLED || | |
471 | value == B43_DMA64_TXSTAT_IDLEWAIT || | |
472 | value == B43_DMA64_TXSTAT_STOPPED) | |
473 | break; | |
474 | } else { | |
475 | value &= B43_DMA32_TXSTATE; | |
476 | if (value == B43_DMA32_TXSTAT_DISABLED || | |
477 | value == B43_DMA32_TXSTAT_IDLEWAIT || | |
478 | value == B43_DMA32_TXSTAT_STOPPED) | |
479 | break; | |
480 | } | |
481 | msleep(1); | |
482 | } | |
b79caa68 | 483 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL; |
e4d6b795 MB |
484 | b43_write32(dev, mmio_base + offset, 0); |
485 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
486 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
487 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 488 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 489 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
490 | value &= B43_DMA64_TXSTAT; |
491 | if (value == B43_DMA64_TXSTAT_DISABLED) { | |
492 | i = -1; | |
493 | break; | |
494 | } | |
495 | } else { | |
496 | value &= B43_DMA32_TXSTATE; | |
497 | if (value == B43_DMA32_TXSTAT_DISABLED) { | |
498 | i = -1; | |
499 | break; | |
500 | } | |
501 | } | |
502 | msleep(1); | |
503 | } | |
504 | if (i != -1) { | |
505 | b43err(dev->wl, "DMA TX reset timed out\n"); | |
506 | return -ENODEV; | |
507 | } | |
508 | /* ensure the reset is completed. */ | |
509 | msleep(1); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
b79caa68 MB |
514 | /* Check if a DMA mapping address is invalid. */ |
515 | static bool b43_dma_mapping_error(struct b43_dmaring *ring, | |
516 | dma_addr_t addr, | |
517 | size_t buffersize) | |
518 | { | |
519 | if (unlikely(dma_mapping_error(addr))) | |
520 | return 1; | |
521 | ||
522 | switch (ring->type) { | |
523 | case B43_DMA_30BIT: | |
524 | if ((u64)addr + buffersize > (1ULL << 30)) | |
525 | return 1; | |
526 | break; | |
527 | case B43_DMA_32BIT: | |
528 | if ((u64)addr + buffersize > (1ULL << 32)) | |
529 | return 1; | |
530 | break; | |
531 | case B43_DMA_64BIT: | |
532 | /* Currently we can't have addresses beyond | |
533 | * 64bit in the kernel. */ | |
534 | break; | |
535 | } | |
536 | ||
537 | /* The address is OK. */ | |
538 | return 0; | |
539 | } | |
540 | ||
e4d6b795 MB |
541 | static int setup_rx_descbuffer(struct b43_dmaring *ring, |
542 | struct b43_dmadesc_generic *desc, | |
543 | struct b43_dmadesc_meta *meta, gfp_t gfp_flags) | |
544 | { | |
545 | struct b43_rxhdr_fw4 *rxhdr; | |
546 | struct b43_hwtxstatus *txstat; | |
547 | dma_addr_t dmaaddr; | |
548 | struct sk_buff *skb; | |
549 | ||
550 | B43_WARN_ON(ring->tx); | |
551 | ||
552 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
553 | if (unlikely(!skb)) | |
554 | return -ENOMEM; | |
555 | dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0); | |
b79caa68 | 556 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) { |
e4d6b795 MB |
557 | /* ugh. try to realloc in zone_dma */ |
558 | gfp_flags |= GFP_DMA; | |
559 | ||
560 | dev_kfree_skb_any(skb); | |
561 | ||
562 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
563 | if (unlikely(!skb)) | |
564 | return -ENOMEM; | |
565 | dmaaddr = map_descbuffer(ring, skb->data, | |
566 | ring->rx_buffersize, 0); | |
567 | } | |
568 | ||
b79caa68 | 569 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) { |
e4d6b795 MB |
570 | dev_kfree_skb_any(skb); |
571 | return -EIO; | |
572 | } | |
573 | ||
574 | meta->skb = skb; | |
575 | meta->dmaaddr = dmaaddr; | |
576 | ring->ops->fill_descriptor(ring, desc, dmaaddr, | |
577 | ring->rx_buffersize, 0, 0, 0); | |
578 | ||
579 | rxhdr = (struct b43_rxhdr_fw4 *)(skb->data); | |
580 | rxhdr->frame_len = 0; | |
581 | txstat = (struct b43_hwtxstatus *)(skb->data); | |
582 | txstat->cookie = 0; | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | /* Allocate the initial descbuffers. | |
588 | * This is used for an RX ring only. | |
589 | */ | |
590 | static int alloc_initial_descbuffers(struct b43_dmaring *ring) | |
591 | { | |
592 | int i, err = -ENOMEM; | |
593 | struct b43_dmadesc_generic *desc; | |
594 | struct b43_dmadesc_meta *meta; | |
595 | ||
596 | for (i = 0; i < ring->nr_slots; i++) { | |
597 | desc = ring->ops->idx2desc(ring, i, &meta); | |
598 | ||
599 | err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); | |
600 | if (err) { | |
601 | b43err(ring->dev->wl, | |
602 | "Failed to allocate initial descbuffers\n"); | |
603 | goto err_unwind; | |
604 | } | |
605 | } | |
606 | mb(); | |
607 | ring->used_slots = ring->nr_slots; | |
608 | err = 0; | |
609 | out: | |
610 | return err; | |
611 | ||
612 | err_unwind: | |
613 | for (i--; i >= 0; i--) { | |
614 | desc = ring->ops->idx2desc(ring, i, &meta); | |
615 | ||
616 | unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); | |
617 | dev_kfree_skb(meta->skb); | |
618 | } | |
619 | goto out; | |
620 | } | |
621 | ||
622 | /* Do initial setup of the DMA controller. | |
623 | * Reset the controller, write the ring busaddress | |
624 | * and switch the "enable" bit on. | |
625 | */ | |
626 | static int dmacontroller_setup(struct b43_dmaring *ring) | |
627 | { | |
628 | int err = 0; | |
629 | u32 value; | |
630 | u32 addrext; | |
631 | u32 trans = ssb_dma_translation(ring->dev->dev); | |
632 | ||
633 | if (ring->tx) { | |
b79caa68 | 634 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
635 | u64 ringbase = (u64) (ring->dmabase); |
636 | ||
637 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
638 | >> SSB_DMA_TRANSLATION_SHIFT; | |
639 | value = B43_DMA64_TXENABLE; | |
640 | value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) | |
641 | & B43_DMA64_TXADDREXT_MASK; | |
642 | b43_dma_write(ring, B43_DMA64_TXCTL, value); | |
643 | b43_dma_write(ring, B43_DMA64_TXRINGLO, | |
644 | (ringbase & 0xFFFFFFFF)); | |
645 | b43_dma_write(ring, B43_DMA64_TXRINGHI, | |
646 | ((ringbase >> 32) & | |
647 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 | 648 | | (trans << 1)); |
e4d6b795 MB |
649 | } else { |
650 | u32 ringbase = (u32) (ring->dmabase); | |
651 | ||
652 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
653 | >> SSB_DMA_TRANSLATION_SHIFT; | |
654 | value = B43_DMA32_TXENABLE; | |
655 | value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) | |
656 | & B43_DMA32_TXADDREXT_MASK; | |
657 | b43_dma_write(ring, B43_DMA32_TXCTL, value); | |
658 | b43_dma_write(ring, B43_DMA32_TXRING, | |
659 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
660 | | trans); | |
661 | } | |
662 | } else { | |
663 | err = alloc_initial_descbuffers(ring); | |
664 | if (err) | |
665 | goto out; | |
b79caa68 | 666 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
667 | u64 ringbase = (u64) (ring->dmabase); |
668 | ||
669 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
670 | >> SSB_DMA_TRANSLATION_SHIFT; | |
671 | value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT); | |
672 | value |= B43_DMA64_RXENABLE; | |
673 | value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) | |
674 | & B43_DMA64_RXADDREXT_MASK; | |
675 | b43_dma_write(ring, B43_DMA64_RXCTL, value); | |
676 | b43_dma_write(ring, B43_DMA64_RXRINGLO, | |
677 | (ringbase & 0xFFFFFFFF)); | |
678 | b43_dma_write(ring, B43_DMA64_RXRINGHI, | |
679 | ((ringbase >> 32) & | |
680 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 LF |
681 | | (trans << 1)); |
682 | b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * | |
683 | sizeof(struct b43_dmadesc64)); | |
e4d6b795 MB |
684 | } else { |
685 | u32 ringbase = (u32) (ring->dmabase); | |
686 | ||
687 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
688 | >> SSB_DMA_TRANSLATION_SHIFT; | |
689 | value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT); | |
690 | value |= B43_DMA32_RXENABLE; | |
691 | value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) | |
692 | & B43_DMA32_RXADDREXT_MASK; | |
693 | b43_dma_write(ring, B43_DMA32_RXCTL, value); | |
694 | b43_dma_write(ring, B43_DMA32_RXRING, | |
695 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
696 | | trans); | |
013978b6 LF |
697 | b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots * |
698 | sizeof(struct b43_dmadesc32)); | |
e4d6b795 MB |
699 | } |
700 | } | |
701 | ||
013978b6 | 702 | out: |
e4d6b795 MB |
703 | return err; |
704 | } | |
705 | ||
706 | /* Shutdown the DMA controller. */ | |
707 | static void dmacontroller_cleanup(struct b43_dmaring *ring) | |
708 | { | |
709 | if (ring->tx) { | |
710 | b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
711 | ring->type); |
712 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
713 | b43_dma_write(ring, B43_DMA64_TXRINGLO, 0); |
714 | b43_dma_write(ring, B43_DMA64_TXRINGHI, 0); | |
715 | } else | |
716 | b43_dma_write(ring, B43_DMA32_TXRING, 0); | |
717 | } else { | |
718 | b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
719 | ring->type); |
720 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
721 | b43_dma_write(ring, B43_DMA64_RXRINGLO, 0); |
722 | b43_dma_write(ring, B43_DMA64_RXRINGHI, 0); | |
723 | } else | |
724 | b43_dma_write(ring, B43_DMA32_RXRING, 0); | |
725 | } | |
726 | } | |
727 | ||
728 | static void free_all_descbuffers(struct b43_dmaring *ring) | |
729 | { | |
730 | struct b43_dmadesc_generic *desc; | |
731 | struct b43_dmadesc_meta *meta; | |
732 | int i; | |
733 | ||
734 | if (!ring->used_slots) | |
735 | return; | |
736 | for (i = 0; i < ring->nr_slots; i++) { | |
737 | desc = ring->ops->idx2desc(ring, i, &meta); | |
738 | ||
739 | if (!meta->skb) { | |
740 | B43_WARN_ON(!ring->tx); | |
741 | continue; | |
742 | } | |
743 | if (ring->tx) { | |
744 | unmap_descbuffer(ring, meta->dmaaddr, | |
745 | meta->skb->len, 1); | |
746 | } else { | |
747 | unmap_descbuffer(ring, meta->dmaaddr, | |
748 | ring->rx_buffersize, 0); | |
749 | } | |
750 | free_descriptor_buffer(ring, meta); | |
751 | } | |
752 | } | |
753 | ||
754 | static u64 supported_dma_mask(struct b43_wldev *dev) | |
755 | { | |
756 | u32 tmp; | |
757 | u16 mmio_base; | |
758 | ||
759 | tmp = b43_read32(dev, SSB_TMSHIGH); | |
760 | if (tmp & SSB_TMSHIGH_DMA64) | |
761 | return DMA_64BIT_MASK; | |
762 | mmio_base = b43_dmacontroller_base(0, 0); | |
763 | b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK); | |
764 | tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL); | |
765 | if (tmp & B43_DMA32_TXADDREXT_MASK) | |
766 | return DMA_32BIT_MASK; | |
767 | ||
768 | return DMA_30BIT_MASK; | |
769 | } | |
770 | ||
771 | /* Main initialization function. */ | |
772 | static | |
773 | struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev, | |
774 | int controller_index, | |
b79caa68 MB |
775 | int for_tx, |
776 | enum b43_dmatype type) | |
e4d6b795 MB |
777 | { |
778 | struct b43_dmaring *ring; | |
779 | int err; | |
780 | int nr_slots; | |
781 | dma_addr_t dma_test; | |
782 | ||
783 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
784 | if (!ring) | |
785 | goto out; | |
b79caa68 | 786 | ring->type = type; |
e4d6b795 MB |
787 | |
788 | nr_slots = B43_RXRING_SLOTS; | |
789 | if (for_tx) | |
790 | nr_slots = B43_TXRING_SLOTS; | |
791 | ||
792 | ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta), | |
793 | GFP_KERNEL); | |
794 | if (!ring->meta) | |
795 | goto err_kfree_ring; | |
796 | if (for_tx) { | |
797 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 798 | b43_txhdr_size(dev), |
e4d6b795 MB |
799 | GFP_KERNEL); |
800 | if (!ring->txhdr_cache) | |
801 | goto err_kfree_meta; | |
802 | ||
803 | /* test for ability to dma to txhdr_cache */ | |
804 | dma_test = dma_map_single(dev->dev->dev, | |
805 | ring->txhdr_cache, | |
eb189d8b | 806 | b43_txhdr_size(dev), |
e4d6b795 MB |
807 | DMA_TO_DEVICE); |
808 | ||
b79caa68 | 809 | if (b43_dma_mapping_error(ring, dma_test, b43_txhdr_size(dev))) { |
e4d6b795 MB |
810 | /* ugh realloc */ |
811 | kfree(ring->txhdr_cache); | |
812 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 813 | b43_txhdr_size(dev), |
e4d6b795 MB |
814 | GFP_KERNEL | GFP_DMA); |
815 | if (!ring->txhdr_cache) | |
816 | goto err_kfree_meta; | |
817 | ||
818 | dma_test = dma_map_single(dev->dev->dev, | |
819 | ring->txhdr_cache, | |
eb189d8b | 820 | b43_txhdr_size(dev), |
e4d6b795 MB |
821 | DMA_TO_DEVICE); |
822 | ||
b79caa68 MB |
823 | if (b43_dma_mapping_error(ring, dma_test, |
824 | b43_txhdr_size(dev))) | |
e4d6b795 MB |
825 | goto err_kfree_txhdr_cache; |
826 | } | |
827 | ||
828 | dma_unmap_single(dev->dev->dev, | |
eb189d8b | 829 | dma_test, b43_txhdr_size(dev), |
e4d6b795 MB |
830 | DMA_TO_DEVICE); |
831 | } | |
832 | ||
833 | ring->dev = dev; | |
834 | ring->nr_slots = nr_slots; | |
b79caa68 | 835 | ring->mmio_base = b43_dmacontroller_base(type, controller_index); |
e4d6b795 | 836 | ring->index = controller_index; |
b79caa68 | 837 | if (type == B43_DMA_64BIT) |
e4d6b795 MB |
838 | ring->ops = &dma64_ops; |
839 | else | |
840 | ring->ops = &dma32_ops; | |
841 | if (for_tx) { | |
842 | ring->tx = 1; | |
843 | ring->current_slot = -1; | |
844 | } else { | |
845 | if (ring->index == 0) { | |
846 | ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE; | |
847 | ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET; | |
848 | } else if (ring->index == 3) { | |
849 | ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE; | |
850 | ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET; | |
851 | } else | |
852 | B43_WARN_ON(1); | |
853 | } | |
854 | spin_lock_init(&ring->lock); | |
855 | #ifdef CONFIG_B43_DEBUG | |
856 | ring->last_injected_overflow = jiffies; | |
857 | #endif | |
858 | ||
859 | err = alloc_ringmemory(ring); | |
860 | if (err) | |
861 | goto err_kfree_txhdr_cache; | |
862 | err = dmacontroller_setup(ring); | |
863 | if (err) | |
864 | goto err_free_ringmemory; | |
865 | ||
866 | out: | |
867 | return ring; | |
868 | ||
869 | err_free_ringmemory: | |
870 | free_ringmemory(ring); | |
871 | err_kfree_txhdr_cache: | |
872 | kfree(ring->txhdr_cache); | |
873 | err_kfree_meta: | |
874 | kfree(ring->meta); | |
875 | err_kfree_ring: | |
876 | kfree(ring); | |
877 | ring = NULL; | |
878 | goto out; | |
879 | } | |
880 | ||
881 | /* Main cleanup function. */ | |
882 | static void b43_destroy_dmaring(struct b43_dmaring *ring) | |
883 | { | |
884 | if (!ring) | |
885 | return; | |
886 | ||
b79caa68 MB |
887 | b43dbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots: %d/%d\n", |
888 | (unsigned int)(ring->type), | |
e4d6b795 MB |
889 | ring->mmio_base, |
890 | (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots); | |
891 | /* Device IRQs are disabled prior entering this function, | |
892 | * so no need to take care of concurrency with rx handler stuff. | |
893 | */ | |
894 | dmacontroller_cleanup(ring); | |
895 | free_all_descbuffers(ring); | |
896 | free_ringmemory(ring); | |
897 | ||
898 | kfree(ring->txhdr_cache); | |
899 | kfree(ring->meta); | |
900 | kfree(ring); | |
901 | } | |
902 | ||
903 | void b43_dma_free(struct b43_wldev *dev) | |
904 | { | |
03b29773 | 905 | struct b43_dma *dma = &dev->dma; |
e4d6b795 MB |
906 | |
907 | b43_destroy_dmaring(dma->rx_ring3); | |
908 | dma->rx_ring3 = NULL; | |
909 | b43_destroy_dmaring(dma->rx_ring0); | |
910 | dma->rx_ring0 = NULL; | |
911 | ||
912 | b43_destroy_dmaring(dma->tx_ring5); | |
913 | dma->tx_ring5 = NULL; | |
914 | b43_destroy_dmaring(dma->tx_ring4); | |
915 | dma->tx_ring4 = NULL; | |
916 | b43_destroy_dmaring(dma->tx_ring3); | |
917 | dma->tx_ring3 = NULL; | |
918 | b43_destroy_dmaring(dma->tx_ring2); | |
919 | dma->tx_ring2 = NULL; | |
920 | b43_destroy_dmaring(dma->tx_ring1); | |
921 | dma->tx_ring1 = NULL; | |
922 | b43_destroy_dmaring(dma->tx_ring0); | |
923 | dma->tx_ring0 = NULL; | |
924 | } | |
925 | ||
926 | int b43_dma_init(struct b43_wldev *dev) | |
927 | { | |
928 | struct b43_dma *dma = &dev->dma; | |
929 | struct b43_dmaring *ring; | |
930 | int err; | |
931 | u64 dmamask; | |
b79caa68 | 932 | enum b43_dmatype type; |
e4d6b795 MB |
933 | |
934 | dmamask = supported_dma_mask(dev); | |
b79caa68 MB |
935 | switch (dmamask) { |
936 | default: | |
937 | B43_WARN_ON(1); | |
938 | case DMA_30BIT_MASK: | |
939 | type = B43_DMA_30BIT; | |
940 | break; | |
941 | case DMA_32BIT_MASK: | |
942 | type = B43_DMA_32BIT; | |
943 | break; | |
944 | case DMA_64BIT_MASK: | |
945 | type = B43_DMA_64BIT; | |
946 | break; | |
947 | } | |
e4d6b795 MB |
948 | err = ssb_dma_set_mask(dev->dev, dmamask); |
949 | if (err) { | |
03b29773 MB |
950 | b43err(dev->wl, "The machine/kernel does not support " |
951 | "the required DMA mask (0x%08X%08X)\n", | |
952 | (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32), | |
953 | (unsigned int)(dmamask & 0x00000000FFFFFFFFULL)); | |
e4d6b795 | 954 | return -EOPNOTSUPP; |
e4d6b795 MB |
955 | } |
956 | ||
957 | err = -ENOMEM; | |
958 | /* setup TX DMA channels. */ | |
b79caa68 | 959 | ring = b43_setup_dmaring(dev, 0, 1, type); |
e4d6b795 MB |
960 | if (!ring) |
961 | goto out; | |
962 | dma->tx_ring0 = ring; | |
963 | ||
b79caa68 | 964 | ring = b43_setup_dmaring(dev, 1, 1, type); |
e4d6b795 MB |
965 | if (!ring) |
966 | goto err_destroy_tx0; | |
967 | dma->tx_ring1 = ring; | |
968 | ||
b79caa68 | 969 | ring = b43_setup_dmaring(dev, 2, 1, type); |
e4d6b795 MB |
970 | if (!ring) |
971 | goto err_destroy_tx1; | |
972 | dma->tx_ring2 = ring; | |
973 | ||
b79caa68 | 974 | ring = b43_setup_dmaring(dev, 3, 1, type); |
e4d6b795 MB |
975 | if (!ring) |
976 | goto err_destroy_tx2; | |
977 | dma->tx_ring3 = ring; | |
978 | ||
b79caa68 | 979 | ring = b43_setup_dmaring(dev, 4, 1, type); |
e4d6b795 MB |
980 | if (!ring) |
981 | goto err_destroy_tx3; | |
982 | dma->tx_ring4 = ring; | |
983 | ||
b79caa68 | 984 | ring = b43_setup_dmaring(dev, 5, 1, type); |
e4d6b795 MB |
985 | if (!ring) |
986 | goto err_destroy_tx4; | |
987 | dma->tx_ring5 = ring; | |
988 | ||
989 | /* setup RX DMA channels. */ | |
b79caa68 | 990 | ring = b43_setup_dmaring(dev, 0, 0, type); |
e4d6b795 MB |
991 | if (!ring) |
992 | goto err_destroy_tx5; | |
993 | dma->rx_ring0 = ring; | |
994 | ||
995 | if (dev->dev->id.revision < 5) { | |
b79caa68 | 996 | ring = b43_setup_dmaring(dev, 3, 0, type); |
e4d6b795 MB |
997 | if (!ring) |
998 | goto err_destroy_rx0; | |
999 | dma->rx_ring3 = ring; | |
1000 | } | |
1001 | ||
b79caa68 MB |
1002 | b43dbg(dev->wl, "%u-bit DMA initialized\n", |
1003 | (unsigned int)type); | |
e4d6b795 MB |
1004 | err = 0; |
1005 | out: | |
1006 | return err; | |
1007 | ||
1008 | err_destroy_rx0: | |
1009 | b43_destroy_dmaring(dma->rx_ring0); | |
1010 | dma->rx_ring0 = NULL; | |
1011 | err_destroy_tx5: | |
1012 | b43_destroy_dmaring(dma->tx_ring5); | |
1013 | dma->tx_ring5 = NULL; | |
1014 | err_destroy_tx4: | |
1015 | b43_destroy_dmaring(dma->tx_ring4); | |
1016 | dma->tx_ring4 = NULL; | |
1017 | err_destroy_tx3: | |
1018 | b43_destroy_dmaring(dma->tx_ring3); | |
1019 | dma->tx_ring3 = NULL; | |
1020 | err_destroy_tx2: | |
1021 | b43_destroy_dmaring(dma->tx_ring2); | |
1022 | dma->tx_ring2 = NULL; | |
1023 | err_destroy_tx1: | |
1024 | b43_destroy_dmaring(dma->tx_ring1); | |
1025 | dma->tx_ring1 = NULL; | |
1026 | err_destroy_tx0: | |
1027 | b43_destroy_dmaring(dma->tx_ring0); | |
1028 | dma->tx_ring0 = NULL; | |
1029 | goto out; | |
1030 | } | |
1031 | ||
1032 | /* Generate a cookie for the TX header. */ | |
1033 | static u16 generate_cookie(struct b43_dmaring *ring, int slot) | |
1034 | { | |
1035 | u16 cookie = 0x1000; | |
1036 | ||
1037 | /* Use the upper 4 bits of the cookie as | |
1038 | * DMA controller ID and store the slot number | |
1039 | * in the lower 12 bits. | |
1040 | * Note that the cookie must never be 0, as this | |
1041 | * is a special value used in RX path. | |
280d0e16 MB |
1042 | * It can also not be 0xFFFF because that is special |
1043 | * for multicast frames. | |
e4d6b795 MB |
1044 | */ |
1045 | switch (ring->index) { | |
1046 | case 0: | |
280d0e16 | 1047 | cookie = 0x1000; |
e4d6b795 MB |
1048 | break; |
1049 | case 1: | |
280d0e16 | 1050 | cookie = 0x2000; |
e4d6b795 MB |
1051 | break; |
1052 | case 2: | |
280d0e16 | 1053 | cookie = 0x3000; |
e4d6b795 MB |
1054 | break; |
1055 | case 3: | |
280d0e16 | 1056 | cookie = 0x4000; |
e4d6b795 MB |
1057 | break; |
1058 | case 4: | |
280d0e16 | 1059 | cookie = 0x5000; |
e4d6b795 MB |
1060 | break; |
1061 | case 5: | |
280d0e16 | 1062 | cookie = 0x6000; |
e4d6b795 | 1063 | break; |
280d0e16 MB |
1064 | default: |
1065 | B43_WARN_ON(1); | |
e4d6b795 MB |
1066 | } |
1067 | B43_WARN_ON(slot & ~0x0FFF); | |
1068 | cookie |= (u16) slot; | |
1069 | ||
1070 | return cookie; | |
1071 | } | |
1072 | ||
1073 | /* Inspect a cookie and find out to which controller/slot it belongs. */ | |
1074 | static | |
1075 | struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot) | |
1076 | { | |
1077 | struct b43_dma *dma = &dev->dma; | |
1078 | struct b43_dmaring *ring = NULL; | |
1079 | ||
1080 | switch (cookie & 0xF000) { | |
280d0e16 | 1081 | case 0x1000: |
e4d6b795 MB |
1082 | ring = dma->tx_ring0; |
1083 | break; | |
280d0e16 | 1084 | case 0x2000: |
e4d6b795 MB |
1085 | ring = dma->tx_ring1; |
1086 | break; | |
280d0e16 | 1087 | case 0x3000: |
e4d6b795 MB |
1088 | ring = dma->tx_ring2; |
1089 | break; | |
280d0e16 | 1090 | case 0x4000: |
e4d6b795 MB |
1091 | ring = dma->tx_ring3; |
1092 | break; | |
280d0e16 | 1093 | case 0x5000: |
e4d6b795 MB |
1094 | ring = dma->tx_ring4; |
1095 | break; | |
280d0e16 | 1096 | case 0x6000: |
e4d6b795 MB |
1097 | ring = dma->tx_ring5; |
1098 | break; | |
1099 | default: | |
1100 | B43_WARN_ON(1); | |
1101 | } | |
1102 | *slot = (cookie & 0x0FFF); | |
1103 | B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots)); | |
1104 | ||
1105 | return ring; | |
1106 | } | |
1107 | ||
1108 | static int dma_tx_fragment(struct b43_dmaring *ring, | |
1109 | struct sk_buff *skb, | |
1110 | struct ieee80211_tx_control *ctl) | |
1111 | { | |
1112 | const struct b43_dma_ops *ops = ring->ops; | |
1113 | u8 *header; | |
09552ccd | 1114 | int slot, old_top_slot, old_used_slots; |
e4d6b795 MB |
1115 | int err; |
1116 | struct b43_dmadesc_generic *desc; | |
1117 | struct b43_dmadesc_meta *meta; | |
1118 | struct b43_dmadesc_meta *meta_hdr; | |
1119 | struct sk_buff *bounce_skb; | |
280d0e16 | 1120 | u16 cookie; |
eb189d8b | 1121 | size_t hdrsize = b43_txhdr_size(ring->dev); |
e4d6b795 MB |
1122 | |
1123 | #define SLOTS_PER_PACKET 2 | |
1124 | B43_WARN_ON(skb_shinfo(skb)->nr_frags); | |
1125 | ||
09552ccd MB |
1126 | old_top_slot = ring->current_slot; |
1127 | old_used_slots = ring->used_slots; | |
1128 | ||
e4d6b795 MB |
1129 | /* Get a slot for the header. */ |
1130 | slot = request_slot(ring); | |
1131 | desc = ops->idx2desc(ring, slot, &meta_hdr); | |
1132 | memset(meta_hdr, 0, sizeof(*meta_hdr)); | |
1133 | ||
eb189d8b | 1134 | header = &(ring->txhdr_cache[slot * hdrsize]); |
280d0e16 | 1135 | cookie = generate_cookie(ring, slot); |
09552ccd MB |
1136 | err = b43_generate_txhdr(ring->dev, header, |
1137 | skb->data, skb->len, ctl, cookie); | |
1138 | if (unlikely(err)) { | |
1139 | ring->current_slot = old_top_slot; | |
1140 | ring->used_slots = old_used_slots; | |
1141 | return err; | |
1142 | } | |
e4d6b795 MB |
1143 | |
1144 | meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, | |
eb189d8b | 1145 | hdrsize, 1); |
b79caa68 | 1146 | if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize)) { |
09552ccd MB |
1147 | ring->current_slot = old_top_slot; |
1148 | ring->used_slots = old_used_slots; | |
e4d6b795 | 1149 | return -EIO; |
09552ccd | 1150 | } |
e4d6b795 | 1151 | ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr, |
eb189d8b | 1152 | hdrsize, 1, 0, 0); |
e4d6b795 MB |
1153 | |
1154 | /* Get a slot for the payload. */ | |
1155 | slot = request_slot(ring); | |
1156 | desc = ops->idx2desc(ring, slot, &meta); | |
1157 | memset(meta, 0, sizeof(*meta)); | |
1158 | ||
1159 | memcpy(&meta->txstat.control, ctl, sizeof(*ctl)); | |
1160 | meta->skb = skb; | |
1161 | meta->is_last_fragment = 1; | |
1162 | ||
1163 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
1164 | /* create a bounce buffer in zone_dma on mapping failure. */ | |
b79caa68 | 1165 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) { |
e4d6b795 MB |
1166 | bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA); |
1167 | if (!bounce_skb) { | |
09552ccd MB |
1168 | ring->current_slot = old_top_slot; |
1169 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1170 | err = -ENOMEM; |
1171 | goto out_unmap_hdr; | |
1172 | } | |
1173 | ||
1174 | memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len); | |
1175 | dev_kfree_skb_any(skb); | |
1176 | skb = bounce_skb; | |
1177 | meta->skb = skb; | |
1178 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
b79caa68 | 1179 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) { |
09552ccd MB |
1180 | ring->current_slot = old_top_slot; |
1181 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1182 | err = -EIO; |
1183 | goto out_free_bounce; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); | |
1188 | ||
280d0e16 MB |
1189 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { |
1190 | /* Tell the firmware about the cookie of the last | |
1191 | * mcast frame, so it can clear the more-data bit in it. */ | |
1192 | b43_shm_write16(ring->dev, B43_SHM_SHARED, | |
1193 | B43_SHM_SH_MCASTCOOKIE, cookie); | |
1194 | } | |
e4d6b795 MB |
1195 | /* Now transfer the whole frame. */ |
1196 | wmb(); | |
1197 | ops->poke_tx(ring, next_slot(ring, slot)); | |
1198 | return 0; | |
1199 | ||
280d0e16 | 1200 | out_free_bounce: |
e4d6b795 | 1201 | dev_kfree_skb_any(skb); |
280d0e16 | 1202 | out_unmap_hdr: |
e4d6b795 | 1203 | unmap_descbuffer(ring, meta_hdr->dmaaddr, |
eb189d8b | 1204 | hdrsize, 1); |
e4d6b795 MB |
1205 | return err; |
1206 | } | |
1207 | ||
1208 | static inline int should_inject_overflow(struct b43_dmaring *ring) | |
1209 | { | |
1210 | #ifdef CONFIG_B43_DEBUG | |
1211 | if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) { | |
1212 | /* Check if we should inject another ringbuffer overflow | |
1213 | * to test handling of this situation in the stack. */ | |
1214 | unsigned long next_overflow; | |
1215 | ||
1216 | next_overflow = ring->last_injected_overflow + HZ; | |
1217 | if (time_after(jiffies, next_overflow)) { | |
1218 | ring->last_injected_overflow = jiffies; | |
1219 | b43dbg(ring->dev->wl, | |
1220 | "Injecting TX ring overflow on " | |
1221 | "DMA controller %d\n", ring->index); | |
1222 | return 1; | |
1223 | } | |
1224 | } | |
1225 | #endif /* CONFIG_B43_DEBUG */ | |
1226 | return 0; | |
1227 | } | |
1228 | ||
e6f5b934 MB |
1229 | /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */ |
1230 | static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev, | |
1231 | u8 queue_prio) | |
1232 | { | |
1233 | struct b43_dmaring *ring; | |
1234 | ||
1235 | if (b43_modparam_qos) { | |
1236 | /* 0 = highest priority */ | |
1237 | switch (queue_prio) { | |
1238 | default: | |
1239 | B43_WARN_ON(1); | |
1240 | /* fallthrough */ | |
1241 | case 0: | |
1242 | ring = dev->dma.tx_ring3; /* AC_VO */ | |
1243 | break; | |
1244 | case 1: | |
1245 | ring = dev->dma.tx_ring2; /* AC_VI */ | |
1246 | break; | |
1247 | case 2: | |
1248 | ring = dev->dma.tx_ring1; /* AC_BE */ | |
1249 | break; | |
1250 | case 3: | |
1251 | ring = dev->dma.tx_ring0; /* AC_BK */ | |
1252 | break; | |
1253 | } | |
1254 | } else | |
1255 | ring = dev->dma.tx_ring1; | |
1256 | ||
1257 | return ring; | |
1258 | } | |
1259 | ||
e4d6b795 MB |
1260 | int b43_dma_tx(struct b43_wldev *dev, |
1261 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) | |
1262 | { | |
1263 | struct b43_dmaring *ring; | |
280d0e16 | 1264 | struct ieee80211_hdr *hdr; |
e4d6b795 MB |
1265 | int err = 0; |
1266 | unsigned long flags; | |
1267 | ||
280d0e16 MB |
1268 | if (unlikely(skb->len < 2 + 2 + 6)) { |
1269 | /* Too short, this can't be a valid frame. */ | |
1270 | return -EINVAL; | |
1271 | } | |
1272 | ||
1273 | hdr = (struct ieee80211_hdr *)skb->data; | |
1274 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { | |
1275 | /* The multicast ring will be sent after the DTIM */ | |
1276 | ring = dev->dma.tx_ring4; | |
1277 | /* Set the more-data bit. Ucode will clear it on | |
1278 | * the last frame for us. */ | |
1279 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1280 | } else { | |
1281 | /* Decide by priority where to put this frame. */ | |
e6f5b934 | 1282 | ring = select_ring_by_priority(dev, ctl->queue); |
280d0e16 MB |
1283 | } |
1284 | ||
e4d6b795 MB |
1285 | spin_lock_irqsave(&ring->lock, flags); |
1286 | B43_WARN_ON(!ring->tx); | |
1287 | if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) { | |
1288 | b43warn(dev->wl, "DMA queue overflow\n"); | |
1289 | err = -ENOSPC; | |
1290 | goto out_unlock; | |
1291 | } | |
1292 | /* Check if the queue was stopped in mac80211, | |
1293 | * but we got called nevertheless. | |
1294 | * That would be a mac80211 bug. */ | |
1295 | B43_WARN_ON(ring->stopped); | |
1296 | ||
e6f5b934 MB |
1297 | /* Assign the queue number to the ring (if not already done before) |
1298 | * so TX status handling can use it. The queue to ring mapping is | |
1299 | * static, so we don't need to store it per frame. */ | |
1300 | ring->queue_prio = ctl->queue; | |
1301 | ||
e4d6b795 | 1302 | err = dma_tx_fragment(ring, skb, ctl); |
09552ccd MB |
1303 | if (unlikely(err == -ENOKEY)) { |
1304 | /* Drop this packet, as we don't have the encryption key | |
1305 | * anymore and must not transmit it unencrypted. */ | |
1306 | dev_kfree_skb_any(skb); | |
1307 | err = 0; | |
1308 | goto out_unlock; | |
1309 | } | |
e4d6b795 MB |
1310 | if (unlikely(err)) { |
1311 | b43err(dev->wl, "DMA tx mapping failure\n"); | |
1312 | goto out_unlock; | |
1313 | } | |
1314 | ring->nr_tx_packets++; | |
1315 | if ((free_slots(ring) < SLOTS_PER_PACKET) || | |
1316 | should_inject_overflow(ring)) { | |
1317 | /* This TX ring is full. */ | |
e6f5b934 | 1318 | ieee80211_stop_queue(dev->wl->hw, ctl->queue); |
e4d6b795 MB |
1319 | ring->stopped = 1; |
1320 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1321 | b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); | |
1322 | } | |
1323 | } | |
280d0e16 | 1324 | out_unlock: |
e4d6b795 MB |
1325 | spin_unlock_irqrestore(&ring->lock, flags); |
1326 | ||
1327 | return err; | |
1328 | } | |
1329 | ||
1330 | void b43_dma_handle_txstatus(struct b43_wldev *dev, | |
1331 | const struct b43_txstatus *status) | |
1332 | { | |
1333 | const struct b43_dma_ops *ops; | |
1334 | struct b43_dmaring *ring; | |
1335 | struct b43_dmadesc_generic *desc; | |
1336 | struct b43_dmadesc_meta *meta; | |
1337 | int slot; | |
1338 | ||
1339 | ring = parse_cookie(dev, status->cookie, &slot); | |
1340 | if (unlikely(!ring)) | |
1341 | return; | |
1342 | B43_WARN_ON(!irqs_disabled()); | |
1343 | spin_lock(&ring->lock); | |
1344 | ||
1345 | B43_WARN_ON(!ring->tx); | |
1346 | ops = ring->ops; | |
1347 | while (1) { | |
1348 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
1349 | desc = ops->idx2desc(ring, slot, &meta); | |
1350 | ||
1351 | if (meta->skb) | |
1352 | unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, | |
1353 | 1); | |
1354 | else | |
1355 | unmap_descbuffer(ring, meta->dmaaddr, | |
eb189d8b | 1356 | b43_txhdr_size(dev), 1); |
e4d6b795 MB |
1357 | |
1358 | if (meta->is_last_fragment) { | |
1359 | B43_WARN_ON(!meta->skb); | |
1360 | /* Call back to inform the ieee80211 subsystem about the | |
1361 | * status of the transmission. | |
1362 | * Some fields of txstat are already filled in dma_tx(). | |
1363 | */ | |
1364 | if (status->acked) { | |
1365 | meta->txstat.flags |= IEEE80211_TX_STATUS_ACK; | |
1366 | } else { | |
1367 | if (!(meta->txstat.control.flags | |
1368 | & IEEE80211_TXCTL_NO_ACK)) | |
1369 | meta->txstat.excessive_retries = 1; | |
1370 | } | |
1371 | if (status->frame_count == 0) { | |
1372 | /* The frame was not transmitted at all. */ | |
1373 | meta->txstat.retry_count = 0; | |
1374 | } else | |
1375 | meta->txstat.retry_count = status->frame_count - 1; | |
1376 | ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, | |
1377 | &(meta->txstat)); | |
1378 | /* skb is freed by ieee80211_tx_status_irqsafe() */ | |
1379 | meta->skb = NULL; | |
1380 | } else { | |
1381 | /* No need to call free_descriptor_buffer here, as | |
1382 | * this is only the txhdr, which is not allocated. | |
1383 | */ | |
1384 | B43_WARN_ON(meta->skb); | |
1385 | } | |
1386 | ||
1387 | /* Everything unmapped and free'd. So it's not used anymore. */ | |
1388 | ring->used_slots--; | |
1389 | ||
1390 | if (meta->is_last_fragment) | |
1391 | break; | |
1392 | slot = next_slot(ring, slot); | |
1393 | } | |
1394 | dev->stats.last_tx = jiffies; | |
1395 | if (ring->stopped) { | |
1396 | B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET); | |
e6f5b934 | 1397 | ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); |
e4d6b795 MB |
1398 | ring->stopped = 0; |
1399 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1400 | b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index); | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | spin_unlock(&ring->lock); | |
1405 | } | |
1406 | ||
1407 | void b43_dma_get_tx_stats(struct b43_wldev *dev, | |
1408 | struct ieee80211_tx_queue_stats *stats) | |
1409 | { | |
1410 | const int nr_queues = dev->wl->hw->queues; | |
1411 | struct b43_dmaring *ring; | |
1412 | struct ieee80211_tx_queue_stats_data *data; | |
1413 | unsigned long flags; | |
1414 | int i; | |
1415 | ||
1416 | for (i = 0; i < nr_queues; i++) { | |
1417 | data = &(stats->data[i]); | |
e6f5b934 | 1418 | ring = select_ring_by_priority(dev, i); |
e4d6b795 MB |
1419 | |
1420 | spin_lock_irqsave(&ring->lock, flags); | |
1421 | data->len = ring->used_slots / SLOTS_PER_PACKET; | |
1422 | data->limit = ring->nr_slots / SLOTS_PER_PACKET; | |
1423 | data->count = ring->nr_tx_packets; | |
1424 | spin_unlock_irqrestore(&ring->lock, flags); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | static void dma_rx(struct b43_dmaring *ring, int *slot) | |
1429 | { | |
1430 | const struct b43_dma_ops *ops = ring->ops; | |
1431 | struct b43_dmadesc_generic *desc; | |
1432 | struct b43_dmadesc_meta *meta; | |
1433 | struct b43_rxhdr_fw4 *rxhdr; | |
1434 | struct sk_buff *skb; | |
1435 | u16 len; | |
1436 | int err; | |
1437 | dma_addr_t dmaaddr; | |
1438 | ||
1439 | desc = ops->idx2desc(ring, *slot, &meta); | |
1440 | ||
1441 | sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); | |
1442 | skb = meta->skb; | |
1443 | ||
1444 | if (ring->index == 3) { | |
1445 | /* We received an xmit status. */ | |
1446 | struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data; | |
1447 | int i = 0; | |
1448 | ||
1449 | while (hw->cookie == 0) { | |
1450 | if (i > 100) | |
1451 | break; | |
1452 | i++; | |
1453 | udelay(2); | |
1454 | barrier(); | |
1455 | } | |
1456 | b43_handle_hwtxstatus(ring->dev, hw); | |
1457 | /* recycle the descriptor buffer. */ | |
1458 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1459 | ring->rx_buffersize); | |
1460 | ||
1461 | return; | |
1462 | } | |
1463 | rxhdr = (struct b43_rxhdr_fw4 *)skb->data; | |
1464 | len = le16_to_cpu(rxhdr->frame_len); | |
1465 | if (len == 0) { | |
1466 | int i = 0; | |
1467 | ||
1468 | do { | |
1469 | udelay(2); | |
1470 | barrier(); | |
1471 | len = le16_to_cpu(rxhdr->frame_len); | |
1472 | } while (len == 0 && i++ < 5); | |
1473 | if (unlikely(len == 0)) { | |
1474 | /* recycle the descriptor buffer. */ | |
1475 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1476 | ring->rx_buffersize); | |
1477 | goto drop; | |
1478 | } | |
1479 | } | |
1480 | if (unlikely(len > ring->rx_buffersize)) { | |
1481 | /* The data did not fit into one descriptor buffer | |
1482 | * and is split over multiple buffers. | |
1483 | * This should never happen, as we try to allocate buffers | |
1484 | * big enough. So simply ignore this packet. | |
1485 | */ | |
1486 | int cnt = 0; | |
1487 | s32 tmp = len; | |
1488 | ||
1489 | while (1) { | |
1490 | desc = ops->idx2desc(ring, *slot, &meta); | |
1491 | /* recycle the descriptor buffer. */ | |
1492 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1493 | ring->rx_buffersize); | |
1494 | *slot = next_slot(ring, *slot); | |
1495 | cnt++; | |
1496 | tmp -= ring->rx_buffersize; | |
1497 | if (tmp <= 0) | |
1498 | break; | |
1499 | } | |
1500 | b43err(ring->dev->wl, "DMA RX buffer too small " | |
1501 | "(len: %u, buffer: %u, nr-dropped: %d)\n", | |
1502 | len, ring->rx_buffersize, cnt); | |
1503 | goto drop; | |
1504 | } | |
1505 | ||
1506 | dmaaddr = meta->dmaaddr; | |
1507 | err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); | |
1508 | if (unlikely(err)) { | |
1509 | b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n"); | |
1510 | sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize); | |
1511 | goto drop; | |
1512 | } | |
1513 | ||
1514 | unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); | |
1515 | skb_put(skb, len + ring->frameoffset); | |
1516 | skb_pull(skb, ring->frameoffset); | |
1517 | ||
1518 | b43_rx(ring->dev, skb, rxhdr); | |
1519 | drop: | |
1520 | return; | |
1521 | } | |
1522 | ||
1523 | void b43_dma_rx(struct b43_dmaring *ring) | |
1524 | { | |
1525 | const struct b43_dma_ops *ops = ring->ops; | |
1526 | int slot, current_slot; | |
1527 | int used_slots = 0; | |
1528 | ||
1529 | B43_WARN_ON(ring->tx); | |
1530 | current_slot = ops->get_current_rxslot(ring); | |
1531 | B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots)); | |
1532 | ||
1533 | slot = ring->current_slot; | |
1534 | for (; slot != current_slot; slot = next_slot(ring, slot)) { | |
1535 | dma_rx(ring, &slot); | |
1536 | update_max_used_slots(ring, ++used_slots); | |
1537 | } | |
1538 | ops->set_current_rxslot(ring, slot); | |
1539 | ring->current_slot = slot; | |
1540 | } | |
1541 | ||
1542 | static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring) | |
1543 | { | |
1544 | unsigned long flags; | |
1545 | ||
1546 | spin_lock_irqsave(&ring->lock, flags); | |
1547 | B43_WARN_ON(!ring->tx); | |
1548 | ring->ops->tx_suspend(ring); | |
1549 | spin_unlock_irqrestore(&ring->lock, flags); | |
1550 | } | |
1551 | ||
1552 | static void b43_dma_tx_resume_ring(struct b43_dmaring *ring) | |
1553 | { | |
1554 | unsigned long flags; | |
1555 | ||
1556 | spin_lock_irqsave(&ring->lock, flags); | |
1557 | B43_WARN_ON(!ring->tx); | |
1558 | ring->ops->tx_resume(ring); | |
1559 | spin_unlock_irqrestore(&ring->lock, flags); | |
1560 | } | |
1561 | ||
1562 | void b43_dma_tx_suspend(struct b43_wldev *dev) | |
1563 | { | |
1564 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); | |
1565 | b43_dma_tx_suspend_ring(dev->dma.tx_ring0); | |
1566 | b43_dma_tx_suspend_ring(dev->dma.tx_ring1); | |
1567 | b43_dma_tx_suspend_ring(dev->dma.tx_ring2); | |
1568 | b43_dma_tx_suspend_ring(dev->dma.tx_ring3); | |
1569 | b43_dma_tx_suspend_ring(dev->dma.tx_ring4); | |
1570 | b43_dma_tx_suspend_ring(dev->dma.tx_ring5); | |
1571 | } | |
1572 | ||
1573 | void b43_dma_tx_resume(struct b43_wldev *dev) | |
1574 | { | |
1575 | b43_dma_tx_resume_ring(dev->dma.tx_ring5); | |
1576 | b43_dma_tx_resume_ring(dev->dma.tx_ring4); | |
1577 | b43_dma_tx_resume_ring(dev->dma.tx_ring3); | |
1578 | b43_dma_tx_resume_ring(dev->dma.tx_ring2); | |
1579 | b43_dma_tx_resume_ring(dev->dma.tx_ring1); | |
1580 | b43_dma_tx_resume_ring(dev->dma.tx_ring0); | |
1581 | b43_power_saving_ctl_bits(dev, 0); | |
1582 | } |