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1 | #ifndef B43_DMA_H_ |
2 | #define B43_DMA_H_ | |
3 | ||
07681e21 | 4 | #include <linux/err.h> |
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5 | |
6 | #include "b43.h" | |
7 | ||
8eccb53f | 8 | |
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9 | /* DMA-Interrupt reasons. */ |
10 | #define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \ | |
11 | | (1 << 14) | (1 << 15)) | |
12 | #define B43_DMAIRQ_NONFATALMASK (1 << 13) | |
13 | #define B43_DMAIRQ_RX_DONE (1 << 16) | |
14 | ||
15 | /*** 32-bit DMA Engine. ***/ | |
16 | ||
17 | /* 32-bit DMA controller registers. */ | |
18 | #define B43_DMA32_TXCTL 0x00 | |
19 | #define B43_DMA32_TXENABLE 0x00000001 | |
20 | #define B43_DMA32_TXSUSPEND 0x00000002 | |
21 | #define B43_DMA32_TXLOOPBACK 0x00000004 | |
22 | #define B43_DMA32_TXFLUSH 0x00000010 | |
78c1ee7e | 23 | #define B43_DMA32_TXPARITYDISABLE 0x00000800 |
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24 | #define B43_DMA32_TXADDREXT_MASK 0x00030000 |
25 | #define B43_DMA32_TXADDREXT_SHIFT 16 | |
26 | #define B43_DMA32_TXRING 0x04 | |
27 | #define B43_DMA32_TXINDEX 0x08 | |
28 | #define B43_DMA32_TXSTATUS 0x0C | |
29 | #define B43_DMA32_TXDPTR 0x00000FFF | |
30 | #define B43_DMA32_TXSTATE 0x0000F000 | |
31 | #define B43_DMA32_TXSTAT_DISABLED 0x00000000 | |
32 | #define B43_DMA32_TXSTAT_ACTIVE 0x00001000 | |
33 | #define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000 | |
34 | #define B43_DMA32_TXSTAT_STOPPED 0x00003000 | |
35 | #define B43_DMA32_TXSTAT_SUSP 0x00004000 | |
36 | #define B43_DMA32_TXERROR 0x000F0000 | |
37 | #define B43_DMA32_TXERR_NOERR 0x00000000 | |
38 | #define B43_DMA32_TXERR_PROT 0x00010000 | |
39 | #define B43_DMA32_TXERR_UNDERRUN 0x00020000 | |
40 | #define B43_DMA32_TXERR_BUFREAD 0x00030000 | |
41 | #define B43_DMA32_TXERR_DESCREAD 0x00040000 | |
42 | #define B43_DMA32_TXACTIVE 0xFFF00000 | |
43 | #define B43_DMA32_RXCTL 0x10 | |
44 | #define B43_DMA32_RXENABLE 0x00000001 | |
45 | #define B43_DMA32_RXFROFF_MASK 0x000000FE | |
46 | #define B43_DMA32_RXFROFF_SHIFT 1 | |
47 | #define B43_DMA32_RXDIRECTFIFO 0x00000100 | |
78c1ee7e | 48 | #define B43_DMA32_RXPARITYDISABLE 0x00000800 |
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49 | #define B43_DMA32_RXADDREXT_MASK 0x00030000 |
50 | #define B43_DMA32_RXADDREXT_SHIFT 16 | |
51 | #define B43_DMA32_RXRING 0x14 | |
52 | #define B43_DMA32_RXINDEX 0x18 | |
53 | #define B43_DMA32_RXSTATUS 0x1C | |
54 | #define B43_DMA32_RXDPTR 0x00000FFF | |
55 | #define B43_DMA32_RXSTATE 0x0000F000 | |
56 | #define B43_DMA32_RXSTAT_DISABLED 0x00000000 | |
57 | #define B43_DMA32_RXSTAT_ACTIVE 0x00001000 | |
58 | #define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000 | |
59 | #define B43_DMA32_RXSTAT_STOPPED 0x00003000 | |
60 | #define B43_DMA32_RXERROR 0x000F0000 | |
61 | #define B43_DMA32_RXERR_NOERR 0x00000000 | |
62 | #define B43_DMA32_RXERR_PROT 0x00010000 | |
63 | #define B43_DMA32_RXERR_OVERFLOW 0x00020000 | |
64 | #define B43_DMA32_RXERR_BUFWRITE 0x00030000 | |
65 | #define B43_DMA32_RXERR_DESCREAD 0x00040000 | |
66 | #define B43_DMA32_RXACTIVE 0xFFF00000 | |
67 | ||
68 | /* 32-bit DMA descriptor. */ | |
69 | struct b43_dmadesc32 { | |
70 | __le32 control; | |
71 | __le32 address; | |
ba2d3587 | 72 | } __packed; |
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73 | #define B43_DMA32_DCTL_BYTECNT 0x00001FFF |
74 | #define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000 | |
75 | #define B43_DMA32_DCTL_ADDREXT_SHIFT 16 | |
76 | #define B43_DMA32_DCTL_DTABLEEND 0x10000000 | |
77 | #define B43_DMA32_DCTL_IRQ 0x20000000 | |
78 | #define B43_DMA32_DCTL_FRAMEEND 0x40000000 | |
79 | #define B43_DMA32_DCTL_FRAMESTART 0x80000000 | |
80 | ||
81 | /*** 64-bit DMA Engine. ***/ | |
82 | ||
83 | /* 64-bit DMA controller registers. */ | |
84 | #define B43_DMA64_TXCTL 0x00 | |
85 | #define B43_DMA64_TXENABLE 0x00000001 | |
86 | #define B43_DMA64_TXSUSPEND 0x00000002 | |
87 | #define B43_DMA64_TXLOOPBACK 0x00000004 | |
88 | #define B43_DMA64_TXFLUSH 0x00000010 | |
78c1ee7e | 89 | #define B43_DMA64_TXPARITYDISABLE 0x00000800 |
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90 | #define B43_DMA64_TXADDREXT_MASK 0x00030000 |
91 | #define B43_DMA64_TXADDREXT_SHIFT 16 | |
92 | #define B43_DMA64_TXINDEX 0x04 | |
93 | #define B43_DMA64_TXRINGLO 0x08 | |
94 | #define B43_DMA64_TXRINGHI 0x0C | |
95 | #define B43_DMA64_TXSTATUS 0x10 | |
96 | #define B43_DMA64_TXSTATDPTR 0x00001FFF | |
97 | #define B43_DMA64_TXSTAT 0xF0000000 | |
98 | #define B43_DMA64_TXSTAT_DISABLED 0x00000000 | |
99 | #define B43_DMA64_TXSTAT_ACTIVE 0x10000000 | |
100 | #define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000 | |
101 | #define B43_DMA64_TXSTAT_STOPPED 0x30000000 | |
102 | #define B43_DMA64_TXSTAT_SUSP 0x40000000 | |
103 | #define B43_DMA64_TXERROR 0x14 | |
104 | #define B43_DMA64_TXERRDPTR 0x0001FFFF | |
105 | #define B43_DMA64_TXERR 0xF0000000 | |
106 | #define B43_DMA64_TXERR_NOERR 0x00000000 | |
107 | #define B43_DMA64_TXERR_PROT 0x10000000 | |
108 | #define B43_DMA64_TXERR_UNDERRUN 0x20000000 | |
109 | #define B43_DMA64_TXERR_TRANSFER 0x30000000 | |
110 | #define B43_DMA64_TXERR_DESCREAD 0x40000000 | |
111 | #define B43_DMA64_TXERR_CORE 0x50000000 | |
112 | #define B43_DMA64_RXCTL 0x20 | |
113 | #define B43_DMA64_RXENABLE 0x00000001 | |
114 | #define B43_DMA64_RXFROFF_MASK 0x000000FE | |
115 | #define B43_DMA64_RXFROFF_SHIFT 1 | |
116 | #define B43_DMA64_RXDIRECTFIFO 0x00000100 | |
78c1ee7e | 117 | #define B43_DMA64_RXPARITYDISABLE 0x00000800 |
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118 | #define B43_DMA64_RXADDREXT_MASK 0x00030000 |
119 | #define B43_DMA64_RXADDREXT_SHIFT 16 | |
120 | #define B43_DMA64_RXINDEX 0x24 | |
121 | #define B43_DMA64_RXRINGLO 0x28 | |
122 | #define B43_DMA64_RXRINGHI 0x2C | |
123 | #define B43_DMA64_RXSTATUS 0x30 | |
124 | #define B43_DMA64_RXSTATDPTR 0x00001FFF | |
125 | #define B43_DMA64_RXSTAT 0xF0000000 | |
126 | #define B43_DMA64_RXSTAT_DISABLED 0x00000000 | |
127 | #define B43_DMA64_RXSTAT_ACTIVE 0x10000000 | |
128 | #define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000 | |
129 | #define B43_DMA64_RXSTAT_STOPPED 0x30000000 | |
130 | #define B43_DMA64_RXSTAT_SUSP 0x40000000 | |
131 | #define B43_DMA64_RXERROR 0x34 | |
132 | #define B43_DMA64_RXERRDPTR 0x0001FFFF | |
133 | #define B43_DMA64_RXERR 0xF0000000 | |
134 | #define B43_DMA64_RXERR_NOERR 0x00000000 | |
135 | #define B43_DMA64_RXERR_PROT 0x10000000 | |
136 | #define B43_DMA64_RXERR_UNDERRUN 0x20000000 | |
137 | #define B43_DMA64_RXERR_TRANSFER 0x30000000 | |
138 | #define B43_DMA64_RXERR_DESCREAD 0x40000000 | |
139 | #define B43_DMA64_RXERR_CORE 0x50000000 | |
140 | ||
141 | /* 64-bit DMA descriptor. */ | |
142 | struct b43_dmadesc64 { | |
143 | __le32 control0; | |
144 | __le32 control1; | |
145 | __le32 address_low; | |
146 | __le32 address_high; | |
ba2d3587 | 147 | } __packed; |
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148 | #define B43_DMA64_DCTL0_DTABLEEND 0x10000000 |
149 | #define B43_DMA64_DCTL0_IRQ 0x20000000 | |
150 | #define B43_DMA64_DCTL0_FRAMEEND 0x40000000 | |
151 | #define B43_DMA64_DCTL0_FRAMESTART 0x80000000 | |
152 | #define B43_DMA64_DCTL1_BYTECNT 0x00001FFF | |
153 | #define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000 | |
154 | #define B43_DMA64_DCTL1_ADDREXT_SHIFT 16 | |
155 | ||
156 | struct b43_dmadesc_generic { | |
157 | union { | |
158 | struct b43_dmadesc32 dma32; | |
159 | struct b43_dmadesc64 dma64; | |
ba2d3587 ED |
160 | } __packed; |
161 | } __packed; | |
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162 | |
163 | /* Misc DMA constants */ | |
14a8083e RM |
164 | #define B43_DMA32_RINGMEMSIZE 4096 |
165 | #define B43_DMA64_RINGMEMSIZE 8192 | |
17030f48 RM |
166 | /* Offset of frame with actual data */ |
167 | #define B43_DMA0_RX_FW598_FO 38 | |
168 | #define B43_DMA0_RX_FW351_FO 30 | |
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169 | |
170 | /* DMA engine tuning knobs */ | |
bdceeb2d | 171 | #define B43_TXRING_SLOTS 256 |
e4d6b795 | 172 | #define B43_RXRING_SLOTS 64 |
17030f48 RM |
173 | #define B43_DMA0_RX_FW598_BUFSIZE (B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN) |
174 | #define B43_DMA0_RX_FW351_BUFSIZE (B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN) | |
8eccb53f | 175 | |
07681e21 MB |
176 | /* Pointer poison */ |
177 | #define B43_DMA_PTR_POISON ((void *)ERR_PTR(-ENOMEM)) | |
178 | #define b43_dma_ptr_is_poisoned(ptr) (unlikely((ptr) == B43_DMA_PTR_POISON)) | |
179 | ||
e4d6b795 | 180 | |
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181 | struct sk_buff; |
182 | struct b43_private; | |
183 | struct b43_txstatus; | |
184 | ||
185 | struct b43_dmadesc_meta { | |
186 | /* The kernel DMA-able buffer. */ | |
187 | struct sk_buff *skb; | |
188 | /* DMA base bus-address of the descriptor buffer. */ | |
189 | dma_addr_t dmaaddr; | |
190 | /* ieee80211 TX status. Only used once per 802.11 frag. */ | |
191 | bool is_last_fragment; | |
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192 | }; |
193 | ||
194 | struct b43_dmaring; | |
195 | ||
196 | /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */ | |
197 | struct b43_dma_ops { | |
198 | struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring, | |
199 | int slot, | |
200 | struct b43_dmadesc_meta ** | |
201 | meta); | |
202 | void (*fill_descriptor) (struct b43_dmaring * ring, | |
203 | struct b43_dmadesc_generic * desc, | |
204 | dma_addr_t dmaaddr, u16 bufsize, int start, | |
205 | int end, int irq); | |
206 | void (*poke_tx) (struct b43_dmaring * ring, int slot); | |
207 | void (*tx_suspend) (struct b43_dmaring * ring); | |
208 | void (*tx_resume) (struct b43_dmaring * ring); | |
209 | int (*get_current_rxslot) (struct b43_dmaring * ring); | |
210 | void (*set_current_rxslot) (struct b43_dmaring * ring, int slot); | |
211 | }; | |
212 | ||
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213 | enum b43_dmatype { |
214 | B43_DMA_30BIT = 30, | |
215 | B43_DMA_32BIT = 32, | |
216 | B43_DMA_64BIT = 64, | |
217 | }; | |
218 | ||
0cc9772a RM |
219 | enum b43_addrtype { |
220 | B43_DMA_ADDR_LOW, | |
221 | B43_DMA_ADDR_HIGH, | |
222 | B43_DMA_ADDR_EXT, | |
223 | }; | |
224 | ||
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225 | struct b43_dmaring { |
226 | /* Lowlevel DMA ops. */ | |
227 | const struct b43_dma_ops *ops; | |
228 | /* Kernel virtual base address of the ring memory. */ | |
229 | void *descbase; | |
230 | /* Meta data about all descriptors. */ | |
231 | struct b43_dmadesc_meta *meta; | |
bdceeb2d | 232 | /* Cache of TX headers for each TX frame. |
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233 | * This is to avoid an allocation on each TX. |
234 | * This is NULL for an RX ring. | |
235 | */ | |
236 | u8 *txhdr_cache; | |
237 | /* (Unadjusted) DMA base bus-address of the ring memory. */ | |
238 | dma_addr_t dmabase; | |
239 | /* Number of descriptor slots in the ring. */ | |
240 | int nr_slots; | |
241 | /* Number of used descriptor slots. */ | |
242 | int used_slots; | |
243 | /* Currently used slot in the ring. */ | |
244 | int current_slot; | |
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245 | /* Frameoffset in octets. */ |
246 | u32 frameoffset; | |
247 | /* Descriptor buffer size. */ | |
248 | u16 rx_buffersize; | |
249 | /* The MMIO base register of the DMA controller. */ | |
250 | u16 mmio_base; | |
251 | /* DMA controller index number (0-5). */ | |
252 | int index; | |
253 | /* Boolean. Is this a TX ring? */ | |
254 | bool tx; | |
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255 | /* The type of DMA engine used. */ |
256 | enum b43_dmatype type; | |
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257 | /* Boolean. Is this ring stopped at ieee80211 level? */ |
258 | bool stopped; | |
e6f5b934 MB |
259 | /* The QOS priority assigned to this ring. Only used for TX rings. |
260 | * This is the mac80211 "queue" value. */ | |
261 | u8 queue_prio; | |
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262 | struct b43_wldev *dev; |
263 | #ifdef CONFIG_B43_DEBUG | |
264 | /* Maximum number of used slots. */ | |
265 | int max_used_slots; | |
266 | /* Last time we injected a ring overflow. */ | |
267 | unsigned long last_injected_overflow; | |
57df40d2 MB |
268 | /* Statistics: Number of successfully transmitted packets */ |
269 | u64 nr_succeed_tx_packets; | |
270 | /* Statistics: Number of failed TX packets */ | |
271 | u64 nr_failed_tx_packets; | |
272 | /* Statistics: Total number of TX plus all retries. */ | |
273 | u64 nr_total_packet_tries; | |
274 | #endif /* CONFIG_B43_DEBUG */ | |
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275 | }; |
276 | ||
277 | static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset) | |
278 | { | |
279 | return b43_read32(ring->dev, ring->mmio_base + offset); | |
280 | } | |
281 | ||
b79caa68 | 282 | static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value) |
e4d6b795 MB |
283 | { |
284 | b43_write32(ring->dev, ring->mmio_base + offset, value); | |
285 | } | |
286 | ||
287 | int b43_dma_init(struct b43_wldev *dev); | |
288 | void b43_dma_free(struct b43_wldev *dev); | |
289 | ||
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290 | void b43_dma_tx_suspend(struct b43_wldev *dev); |
291 | void b43_dma_tx_resume(struct b43_wldev *dev); | |
292 | ||
e4d6b795 | 293 | int b43_dma_tx(struct b43_wldev *dev, |
e039fa4a | 294 | struct sk_buff *skb); |
e4d6b795 MB |
295 | void b43_dma_handle_txstatus(struct b43_wldev *dev, |
296 | const struct b43_txstatus *status); | |
297 | ||
298 | void b43_dma_rx(struct b43_dmaring *ring); | |
299 | ||
5100d5ac MB |
300 | void b43_dma_direct_fifo_rx(struct b43_wldev *dev, |
301 | unsigned int engine_index, bool enable); | |
302 | ||
e4d6b795 | 303 | #endif /* B43_DMA_H_ */ |