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b43: Add myself to module authors & to LP-PHY file copyright notices
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
0136e51e 61MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 62MODULE_LICENSE("GPL");
63
9c7d99d6
MB		 64MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
65
e4d6b795
MB		 66
67static int modparam_bad_frames_preempt;
68module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
69MODULE_PARM_DESC(bad_frames_preempt,
70 "enable(1) / disable(0) Bad Frames Preemption");
71
e4d6b795
MB		 72static char modparam_fwpostfix[16];
73module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
74MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75
e4d6b795
MB		 76static int modparam_hwpctl;
77module_param_named(hwpctl, modparam_hwpctl, int, 0444);
78MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79
80static int modparam_nohwcrypt;
81module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
82MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83
035d0243 84static int modparam_hwtkip;
85module_param_named(hwtkip, modparam_hwtkip, int, 0444);
86MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
87
403a3a13
MB		 88static int modparam_qos = 1;
89module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 90MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
91
1855ba78
MB		 92static int modparam_btcoex = 1;
93module_param_named(btcoex, modparam_btcoex, int, 0444);
94MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
95
060210f9
MB		 96int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
97module_param_named(verbose, b43_modparam_verbose, int, 0644);
98MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
99
e6f5b934 100
e4d6b795
MB		 101static const struct ssb_device_id b43_ssb_tbl[] = {
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 111 SSB_DEVTABLE_END
112};
113
114MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
115
116/* Channel and ratetables are shared for all devices.
117 * They can't be const, because ieee80211 puts some precalculated
118 * data in there. This data is the same for all devices, so we don't
119 * get concurrency issues */
120#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 121 { \
122 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
123 .hw_value = (_rateid), \
124 .flags = (_flags), \
e4d6b795 125 }
8318d78a
JB		 126
127/*
128 * NOTE: When changing this, sync with xmit.c's
129 * b43_plcp_get_bitrate_idx_* functions!
130 */
e4d6b795 131static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 132 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
133 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 144};
145
146#define b43_a_ratetable (__b43_ratetable + 4)
147#define b43_a_ratetable_size 8
148#define b43_b_ratetable (__b43_ratetable + 0)
149#define b43_b_ratetable_size 4
150#define b43_g_ratetable (__b43_ratetable + 0)
151#define b43_g_ratetable_size 12
152
bb1eeff1
MB		 153#define CHAN4G(_channel, _freq, _flags) { \
154 .band = IEEE80211_BAND_2GHZ, \
155 .center_freq = (_freq), \
156 .hw_value = (_channel), \
157 .flags = (_flags), \
158 .max_antenna_gain = 0, \
159 .max_power = 30, \
160}
96c755a3 161static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 162 CHAN4G(1, 2412, 0),
163 CHAN4G(2, 2417, 0),
164 CHAN4G(3, 2422, 0),
165 CHAN4G(4, 2427, 0),
166 CHAN4G(5, 2432, 0),
167 CHAN4G(6, 2437, 0),
168 CHAN4G(7, 2442, 0),
169 CHAN4G(8, 2447, 0),
170 CHAN4G(9, 2452, 0),
171 CHAN4G(10, 2457, 0),
172 CHAN4G(11, 2462, 0),
173 CHAN4G(12, 2467, 0),
174 CHAN4G(13, 2472, 0),
175 CHAN4G(14, 2484, 0),
176};
177#undef CHAN4G
178
179#define CHAN5G(_channel, _flags) { \
180 .band = IEEE80211_BAND_5GHZ, \
181 .center_freq = 5000 + (5 * (_channel)), \
182 .hw_value = (_channel), \
183 .flags = (_flags), \
184 .max_antenna_gain = 0, \
185 .max_power = 30, \
186}
187static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
188 CHAN5G(32, 0), CHAN5G(34, 0),
189 CHAN5G(36, 0), CHAN5G(38, 0),
190 CHAN5G(40, 0), CHAN5G(42, 0),
191 CHAN5G(44, 0), CHAN5G(46, 0),
192 CHAN5G(48, 0), CHAN5G(50, 0),
193 CHAN5G(52, 0), CHAN5G(54, 0),
194 CHAN5G(56, 0), CHAN5G(58, 0),
195 CHAN5G(60, 0), CHAN5G(62, 0),
196 CHAN5G(64, 0), CHAN5G(66, 0),
197 CHAN5G(68, 0), CHAN5G(70, 0),
198 CHAN5G(72, 0), CHAN5G(74, 0),
199 CHAN5G(76, 0), CHAN5G(78, 0),
200 CHAN5G(80, 0), CHAN5G(82, 0),
201 CHAN5G(84, 0), CHAN5G(86, 0),
202 CHAN5G(88, 0), CHAN5G(90, 0),
203 CHAN5G(92, 0), CHAN5G(94, 0),
204 CHAN5G(96, 0), CHAN5G(98, 0),
205 CHAN5G(100, 0), CHAN5G(102, 0),
206 CHAN5G(104, 0), CHAN5G(106, 0),
207 CHAN5G(108, 0), CHAN5G(110, 0),
208 CHAN5G(112, 0), CHAN5G(114, 0),
209 CHAN5G(116, 0), CHAN5G(118, 0),
210 CHAN5G(120, 0), CHAN5G(122, 0),
211 CHAN5G(124, 0), CHAN5G(126, 0),
212 CHAN5G(128, 0), CHAN5G(130, 0),
213 CHAN5G(132, 0), CHAN5G(134, 0),
214 CHAN5G(136, 0), CHAN5G(138, 0),
215 CHAN5G(140, 0), CHAN5G(142, 0),
216 CHAN5G(144, 0), CHAN5G(145, 0),
217 CHAN5G(146, 0), CHAN5G(147, 0),
218 CHAN5G(148, 0), CHAN5G(149, 0),
219 CHAN5G(150, 0), CHAN5G(151, 0),
220 CHAN5G(152, 0), CHAN5G(153, 0),
221 CHAN5G(154, 0), CHAN5G(155, 0),
222 CHAN5G(156, 0), CHAN5G(157, 0),
223 CHAN5G(158, 0), CHAN5G(159, 0),
224 CHAN5G(160, 0), CHAN5G(161, 0),
225 CHAN5G(162, 0), CHAN5G(163, 0),
226 CHAN5G(164, 0), CHAN5G(165, 0),
227 CHAN5G(166, 0), CHAN5G(168, 0),
228 CHAN5G(170, 0), CHAN5G(172, 0),
229 CHAN5G(174, 0), CHAN5G(176, 0),
230 CHAN5G(178, 0), CHAN5G(180, 0),
231 CHAN5G(182, 0), CHAN5G(184, 0),
232 CHAN5G(186, 0), CHAN5G(188, 0),
233 CHAN5G(190, 0), CHAN5G(192, 0),
234 CHAN5G(194, 0), CHAN5G(196, 0),
235 CHAN5G(198, 0), CHAN5G(200, 0),
236 CHAN5G(202, 0), CHAN5G(204, 0),
237 CHAN5G(206, 0), CHAN5G(208, 0),
238 CHAN5G(210, 0), CHAN5G(212, 0),
239 CHAN5G(214, 0), CHAN5G(216, 0),
240 CHAN5G(218, 0), CHAN5G(220, 0),
241 CHAN5G(222, 0), CHAN5G(224, 0),
242 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 243};
244
bb1eeff1
MB		 245static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
246 CHAN5G(34, 0), CHAN5G(36, 0),
247 CHAN5G(38, 0), CHAN5G(40, 0),
248 CHAN5G(42, 0), CHAN5G(44, 0),
249 CHAN5G(46, 0), CHAN5G(48, 0),
250 CHAN5G(52, 0), CHAN5G(56, 0),
251 CHAN5G(60, 0), CHAN5G(64, 0),
252 CHAN5G(100, 0), CHAN5G(104, 0),
253 CHAN5G(108, 0), CHAN5G(112, 0),
254 CHAN5G(116, 0), CHAN5G(120, 0),
255 CHAN5G(124, 0), CHAN5G(128, 0),
256 CHAN5G(132, 0), CHAN5G(136, 0),
257 CHAN5G(140, 0), CHAN5G(149, 0),
258 CHAN5G(153, 0), CHAN5G(157, 0),
259 CHAN5G(161, 0), CHAN5G(165, 0),
260 CHAN5G(184, 0), CHAN5G(188, 0),
261 CHAN5G(192, 0), CHAN5G(196, 0),
262 CHAN5G(200, 0), CHAN5G(204, 0),
263 CHAN5G(208, 0), CHAN5G(212, 0),
264 CHAN5G(216, 0),
265};
266#undef CHAN5G
267
268static struct ieee80211_supported_band b43_band_5GHz_nphy = {
269 .band = IEEE80211_BAND_5GHZ,
270 .channels = b43_5ghz_nphy_chantable,
271 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
272 .bitrates = b43_a_ratetable,
273 .n_bitrates = b43_a_ratetable_size,
e4d6b795 274};
8318d78a 275
bb1eeff1
MB		 276static struct ieee80211_supported_band b43_band_5GHz_aphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_aphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
8318d78a 282};
e4d6b795 283
8318d78a 284static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 285 .band = IEEE80211_BAND_2GHZ,
286 .channels = b43_2ghz_chantable,
287 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
288 .bitrates = b43_g_ratetable,
289 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 290};
291
e4d6b795
MB		 292static void b43_wireless_core_exit(struct b43_wldev *dev);
293static int b43_wireless_core_init(struct b43_wldev *dev);
294static void b43_wireless_core_stop(struct b43_wldev *dev);
295static int b43_wireless_core_start(struct b43_wldev *dev);
296
297static int b43_ratelimit(struct b43_wl *wl)
298{
299 if (!wl || !wl->current_dev)
300 return 1;
301 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
302 return 1;
303 /* We are up and running.
304 * Ratelimit the messages to avoid DoS over the net. */
305 return net_ratelimit();
306}
307
308void b43info(struct b43_wl *wl, const char *fmt, ...)
309{
310 va_list args;
311
060210f9
MB		 312 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
313 return;
e4d6b795
MB		 314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_INFO "b43-%s: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43err(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
060210f9
MB		 327 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
328 return;
e4d6b795
MB		 329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_ERR "b43-%s ERROR: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336}
337
338void b43warn(struct b43_wl *wl, const char *fmt, ...)
339{
340 va_list args;
341
060210f9
MB		 342 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
343 return;
e4d6b795
MB		 344 if (!b43_ratelimit(wl))
345 return;
346 va_start(args, fmt);
347 printk(KERN_WARNING "b43-%s warning: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 vprintk(fmt, args);
350 va_end(args);
351}
352
e4d6b795
MB		 353void b43dbg(struct b43_wl *wl, const char *fmt, ...)
354{
355 va_list args;
356
060210f9
MB		 357 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
358 return;
e4d6b795
MB		 359 va_start(args, fmt);
360 printk(KERN_DEBUG "b43-%s debug: ",
361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
362 vprintk(fmt, args);
363 va_end(args);
364}
e4d6b795
MB		 365
366static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
367{
368 u32 macctl;
369
370 B43_WARN_ON(offset % 4 != 0);
371
372 macctl = b43_read32(dev, B43_MMIO_MACCTL);
373 if (macctl & B43_MACCTL_BE)
374 val = swab32(val);
375
376 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
377 mmiowb();
378 b43_write32(dev, B43_MMIO_RAM_DATA, val);
379}
380
280d0e16
MB		 381static inline void b43_shm_control_word(struct b43_wldev *dev,
382 u16 routing, u16 offset)
e4d6b795
MB		 383{
384 u32 control;
385
386 /* "offset" is the WORD offset. */
e4d6b795
MB		 387 control = routing;
388 control <<= 16;
389 control |= offset;
390 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
391}
392
6bbc321a 393u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 394{
395 u32 ret;
396
397 if (routing == B43_SHM_SHARED) {
398 B43_WARN_ON(offset & 0x0001);
399 if (offset & 0x0003) {
400 /* Unaligned access */
401 b43_shm_control_word(dev, routing, offset >> 2);
402 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 403 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 404 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 405
280d0e16 406 goto out;
e4d6b795
MB		 407 }
408 offset >>= 2;
409 }
410 b43_shm_control_word(dev, routing, offset);
411 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 412out:
e4d6b795
MB		 413 return ret;
414}
415
6bbc321a 416u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 417{
280d0e16
MB		 418 struct b43_wl *wl = dev->wl;
419 unsigned long flags;
6bbc321a 420 u32 ret;
e4d6b795 421
280d0e16 422 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 423 ret = __b43_shm_read32(dev, routing, offset);
424 spin_unlock_irqrestore(&wl->shm_lock, flags);
425
426 return ret;
427}
428
429u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
430{
431 u16 ret;
432
e4d6b795
MB		 433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
438 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
439
280d0e16 440 goto out;
e4d6b795
MB		 441 }
442 offset >>= 2;
443 }
444 b43_shm_control_word(dev, routing, offset);
445 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 446out:
e4d6b795
MB		 447 return ret;
448}
449
6bbc321a 450u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 451{
280d0e16
MB		 452 struct b43_wl *wl = dev->wl;
453 unsigned long flags;
6bbc321a 454 u16 ret;
280d0e16
MB		 455
456 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 457 ret = __b43_shm_read16(dev, routing, offset);
458 spin_unlock_irqrestore(&wl->shm_lock, flags);
459
460 return ret;
461}
462
463void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
464{
e4d6b795
MB		 465 if (routing == B43_SHM_SHARED) {
466 B43_WARN_ON(offset & 0x0001);
467 if (offset & 0x0003) {
468 /* Unaligned access */
469 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 470 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 471 value & 0xFFFF);
e4d6b795 472 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 473 b43_write16(dev, B43_MMIO_SHM_DATA,
474 (value >> 16) & 0xFFFF);
6bbc321a 475 return;
e4d6b795
MB		 476 }
477 offset >>= 2;
478 }
479 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 480 b43_write32(dev, B43_MMIO_SHM_DATA, value);
481}
482
6bbc321a 483void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 484{
280d0e16
MB		 485 struct b43_wl *wl = dev->wl;
486 unsigned long flags;
487
488 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 489 __b43_shm_write32(dev, routing, offset, value);
490 spin_unlock_irqrestore(&wl->shm_lock, flags);
491}
492
493void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
494{
e4d6b795
MB		 495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 501 return;
e4d6b795
MB		 502 }
503 offset >>= 2;
504 }
505 b43_shm_control_word(dev, routing, offset);
e4d6b795 506 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 507}
508
509void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
510{
511 struct b43_wl *wl = dev->wl;
512 unsigned long flags;
513
514 spin_lock_irqsave(&wl->shm_lock, flags);
515 __b43_shm_write16(dev, routing, offset, value);
280d0e16 516 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 517}
518
519/* Read HostFlags */
99da185a 520u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 521{
35f0d354 522 u64 ret;
e4d6b795
MB		 523
524 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
525 ret <<= 16;
35f0d354
MB		 526 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
527 ret <<= 16;
e4d6b795
MB		 528 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
529
530 return ret;
531}
532
533/* Write HostFlags */
35f0d354 534void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 535{
35f0d354
MB		 536 u16 lo, mi, hi;
537
538 lo = (value & 0x00000000FFFFULL);
539 mi = (value & 0x0000FFFF0000ULL) >> 16;
540 hi = (value & 0xFFFF00000000ULL) >> 32;
541 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
542 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
543 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 544}
545
403a3a13
MB		 546/* Read the firmware capabilities bitmask (Opensource firmware only) */
547static u16 b43_fwcapa_read(struct b43_wldev *dev)
548{
549 B43_WARN_ON(!dev->fw.opensource);
550 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
551}
552
3ebbbb56 553void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 554{
3ebbbb56
MB		 555 u32 low, high;
556
557 B43_WARN_ON(dev->dev->id.revision < 3);
558
559 /* The hardware guarantees us an atomic read, if we
560 * read the low register first. */
561 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
562 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
563
564 *tsf = high;
565 *tsf <<= 32;
566 *tsf |= low;
e4d6b795
MB		 567}
568
569static void b43_time_lock(struct b43_wldev *dev)
570{
571 u32 macctl;
572
573 macctl = b43_read32(dev, B43_MMIO_MACCTL);
574 macctl |= B43_MACCTL_TBTTHOLD;
575 b43_write32(dev, B43_MMIO_MACCTL, macctl);
576 /* Commit the write */
577 b43_read32(dev, B43_MMIO_MACCTL);
578}
579
580static void b43_time_unlock(struct b43_wldev *dev)
581{
582 u32 macctl;
583
584 macctl = b43_read32(dev, B43_MMIO_MACCTL);
585 macctl &= ~B43_MACCTL_TBTTHOLD;
586 b43_write32(dev, B43_MMIO_MACCTL, macctl);
587 /* Commit the write */
588 b43_read32(dev, B43_MMIO_MACCTL);
589}
590
591static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
592{
3ebbbb56
MB		 593 u32 low, high;
594
595 B43_WARN_ON(dev->dev->id.revision < 3);
596
597 low = tsf;
598 high = (tsf >> 32);
599 /* The hardware guarantees us an atomic write, if we
600 * write the low register first. */
601 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
602 mmiowb();
603 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
604 mmiowb();
e4d6b795
MB		 605}
606
607void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
608{
609 b43_time_lock(dev);
610 b43_tsf_write_locked(dev, tsf);
611 b43_time_unlock(dev);
612}
613
614static
99da185a 615void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 616{
617 static const u8 zero_addr[ETH_ALEN] = { 0 };
618 u16 data;
619
620 if (!mac)
621 mac = zero_addr;
622
623 offset |= 0x0020;
624 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
625
626 data = mac[0];
627 data |= mac[1] << 8;
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
629 data = mac[2];
630 data |= mac[3] << 8;
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632 data = mac[4];
633 data |= mac[5] << 8;
634 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635}
636
637static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
638{
639 const u8 *mac;
640 const u8 *bssid;
641 u8 mac_bssid[ETH_ALEN * 2];
642 int i;
643 u32 tmp;
644
645 bssid = dev->wl->bssid;
646 mac = dev->wl->mac_addr;
647
648 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
649
650 memcpy(mac_bssid, mac, ETH_ALEN);
651 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
652
653 /* Write our MAC address and BSSID to template ram */
654 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
655 tmp = (u32) (mac_bssid[i + 0]);
656 tmp |= (u32) (mac_bssid[i + 1]) << 8;
657 tmp |= (u32) (mac_bssid[i + 2]) << 16;
658 tmp |= (u32) (mac_bssid[i + 3]) << 24;
659 b43_ram_write(dev, 0x20 + i, tmp);
660 }
661}
662
4150c572 663static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 664{
e4d6b795 665 b43_write_mac_bssid_templates(dev);
4150c572 666 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 667}
668
669static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
670{
671 /* slot_time is in usec. */
672 if (dev->phy.type != B43_PHYTYPE_G)
673 return;
674 b43_write16(dev, 0x684, 510 + slot_time);
675 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
676}
677
678static void b43_short_slot_timing_enable(struct b43_wldev *dev)
679{
680 b43_set_slot_time(dev, 9);
e4d6b795
MB		 681}
682
683static void b43_short_slot_timing_disable(struct b43_wldev *dev)
684{
685 b43_set_slot_time(dev, 20);
e4d6b795
MB		 686}
687
e4d6b795
MB		 688/* Synchronize IRQ top- and bottom-half.
689 * IRQs must be masked before calling this.
690 * This must not be called with the irq_lock held.
691 */
692static void b43_synchronize_irq(struct b43_wldev *dev)
693{
694 synchronize_irq(dev->dev->irq);
695 tasklet_kill(&dev->isr_tasklet);
696}
697
698/* DummyTransmission function, as documented on
2f19c287 699 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 700 */
2f19c287 701void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795 702{
21a75d77 703 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
706 u16 value;
707 u32 buffer[5] = {
708 0x00000000,
709 0x00D40000,
710 0x00000000,
711 0x01000000,
712 0x00000000,
713 };
714
2f19c287 715 if (ofdm) {
e4d6b795
MB		 716 max_loop = 0x1E;
717 buffer[0] = 0x000201CC;
2f19c287 718 } else {
e4d6b795
MB		 719 max_loop = 0xFA;
720 buffer[0] = 0x000B846E;
e4d6b795
MB		 721 }
722
21a75d77
MB		 723 spin_lock_irq(&wl->irq_lock);
724 write_lock(&wl->tx_lock);
725
e4d6b795
MB		 726 for (i = 0; i < 5; i++)
727 b43_ram_write(dev, i * 4, buffer[i]);
728
e4d6b795 729 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 730 if (dev->dev->id.revision < 11)
731 b43_write16(dev, 0x07C0, 0x0000);
732 else
733 b43_write16(dev, 0x07C0, 0x0100);
734 value = (ofdm ? 0x41 : 0x40);
e4d6b795 735 b43_write16(dev, 0x050C, value);
2f19c287
GS		 736 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
737 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 738 b43_write16(dev, 0x0508, 0x0000);
739 b43_write16(dev, 0x050A, 0x0000);
740 b43_write16(dev, 0x054C, 0x0000);
741 b43_write16(dev, 0x056A, 0x0014);
742 b43_write16(dev, 0x0568, 0x0826);
743 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 744 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
745 //SPEC TODO
746 }
747
748 switch (phy->type) {
749 case B43_PHYTYPE_N:
750 b43_write16(dev, 0x0502, 0x00D0);
751 break;
752 case B43_PHYTYPE_LP:
753 b43_write16(dev, 0x0502, 0x0050);
754 break;
755 default:
756 b43_write16(dev, 0x0502, 0x0030);
757 }
e4d6b795
MB		 758
759 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
760 b43_radio_write16(dev, 0x0051, 0x0017);
761 for (i = 0x00; i < max_loop; i++) {
762 value = b43_read16(dev, 0x050E);
763 if (value & 0x0080)
764 break;
765 udelay(10);
766 }
767 for (i = 0x00; i < 0x0A; i++) {
768 value = b43_read16(dev, 0x050E);
769 if (value & 0x0400)
770 break;
771 udelay(10);
772 }
1d280ddc 773 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 774 value = b43_read16(dev, 0x0690);
775 if (!(value & 0x0100))
776 break;
777 udelay(10);
778 }
779 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
780 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 781
782 write_unlock(&wl->tx_lock);
783 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 784}
785
786static void key_write(struct b43_wldev *dev,
99da185a 787 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 788{
789 unsigned int i;
790 u32 offset;
791 u16 value;
792 u16 kidx;
793
794 /* Key index/algo block */
795 kidx = b43_kidx_to_fw(dev, index);
796 value = ((kidx << 4) | algorithm);
797 b43_shm_write16(dev, B43_SHM_SHARED,
798 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
799
800 /* Write the key to the Key Table Pointer offset */
801 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
802 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
803 value = key[i];
804 value |= (u16) (key[i + 1]) << 8;
805 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
806 }
807}
808
99da185a 809static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 810{
811 u32 addrtmp[2] = { 0, 0, };
66d2d089 812 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 813
814 if (b43_new_kidx_api(dev))
66d2d089 815 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 816
66d2d089
MB		 817 B43_WARN_ON(index < pairwise_keys_start);
818 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 819 * Physical mac 0 is mapped to physical key 4 or 8, depending
820 * on the firmware version.
821 * So we must adjust the index here.
822 */
66d2d089
MB		 823 index -= pairwise_keys_start;
824 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 825
826 if (addr) {
827 addrtmp[0] = addr[0];
828 addrtmp[0] |= ((u32) (addr[1]) << 8);
829 addrtmp[0] |= ((u32) (addr[2]) << 16);
830 addrtmp[0] |= ((u32) (addr[3]) << 24);
831 addrtmp[1] = addr[4];
832 addrtmp[1] |= ((u32) (addr[5]) << 8);
833 }
834
66d2d089
MB		 835 /* Receive match transmitter address (RCMTA) mechanism */
836 b43_shm_write32(dev, B43_SHM_RCMTA,
837 (index * 2) + 0, addrtmp[0]);
838 b43_shm_write16(dev, B43_SHM_RCMTA,
839 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 840}
841
035d0243 842/* The ucode will use phase1 key with TEK key to decrypt rx packets.
843 * When a packet is received, the iv32 is checked.
844 * - if it doesn't the packet is returned without modification (and software
845 * decryption can be done). That's what happen when iv16 wrap.
846 * - if it does, the rc4 key is computed, and decryption is tried.
847 * Either it will success and B43_RX_MAC_DEC is returned,
848 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
849 * and the packet is not usable (it got modified by the ucode).
850 * So in order to never have B43_RX_MAC_DECERR, we should provide
851 * a iv32 and phase1key that match. Because we drop packets in case of
852 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
853 * packets will be lost without higher layer knowing (ie no resync possible
854 * until next wrap).
855 *
856 * NOTE : this should support 50 key like RCMTA because
857 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
858 */
859static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
860 u16 *phase1key)
861{
862 unsigned int i;
863 u32 offset;
864 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
865
866 if (!modparam_hwtkip)
867 return;
868
869 if (b43_new_kidx_api(dev))
870 pairwise_keys_start = B43_NR_GROUP_KEYS;
871
872 B43_WARN_ON(index < pairwise_keys_start);
873 /* We have four default TX keys and possibly four default RX keys.
874 * Physical mac 0 is mapped to physical key 4 or 8, depending
875 * on the firmware version.
876 * So we must adjust the index here.
877 */
878 index -= pairwise_keys_start;
879 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
880
881 if (b43_debug(dev, B43_DBG_KEYS)) {
882 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
883 index, iv32);
884 }
885 /* Write the key to the RX tkip shared mem */
886 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
887 for (i = 0; i < 10; i += 2) {
888 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
889 phase1key ? phase1key[i / 2] : 0);
890 }
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
893}
894
895static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
896 struct ieee80211_key_conf *keyconf, const u8 *addr,
897 u32 iv32, u16 *phase1key)
898{
899 struct b43_wl *wl = hw_to_b43_wl(hw);
900 struct b43_wldev *dev;
901 int index = keyconf->hw_key_idx;
902
903 if (B43_WARN_ON(!modparam_hwtkip))
904 return;
905
906 mutex_lock(&wl->mutex);
907
908 dev = wl->current_dev;
909 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
910 goto out_unlock;
911
912 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
913
914 rx_tkip_phase1_write(dev, index, iv32, phase1key);
915 keymac_write(dev, index, addr);
916
917out_unlock:
918 mutex_unlock(&wl->mutex);
919}
920
e4d6b795
MB		 921static void do_key_write(struct b43_wldev *dev,
922 u8 index, u8 algorithm,
99da185a 923 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 924{
925 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 926 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 927
928 if (b43_new_kidx_api(dev))
66d2d089 929 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 930
66d2d089 931 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 932 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
933
66d2d089 934 if (index >= pairwise_keys_start)
e4d6b795 935 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 936 if (algorithm == B43_SEC_ALGO_TKIP) {
937 /*
938 * We should provide an initial iv32, phase1key pair.
939 * We could start with iv32=0 and compute the corresponding
940 * phase1key, but this means calling ieee80211_get_tkip_key
941 * with a fake skb (or export other tkip function).
942 * Because we are lazy we hope iv32 won't start with
943 * 0xffffffff and let's b43_op_update_tkip_key provide a
944 * correct pair.
945 */
946 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
947 } else if (index >= pairwise_keys_start) /* clear it */
948 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 949 if (key)
950 memcpy(buf, key, key_len);
951 key_write(dev, index, algorithm, buf);
66d2d089 952 if (index >= pairwise_keys_start)
e4d6b795
MB		 953 keymac_write(dev, index, mac_addr);
954
955 dev->key[index].algorithm = algorithm;
956}
957
958static int b43_key_write(struct b43_wldev *dev,
959 int index, u8 algorithm,
99da185a
JD		 960 const u8 *key, size_t key_len,
961 const u8 *mac_addr,
e4d6b795
MB		 962 struct ieee80211_key_conf *keyconf)
963{
964 int i;
66d2d089 965 int pairwise_keys_start;
e4d6b795 966
035d0243 967 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
968 * - Temporal Encryption Key (128 bits)
969 * - Temporal Authenticator Tx MIC Key (64 bits)
970 * - Temporal Authenticator Rx MIC Key (64 bits)
971 *
972 * Hardware only store TEK
973 */
974 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
975 key_len = 16;
e4d6b795
MB		 976 if (key_len > B43_SEC_KEYSIZE)
977 return -EINVAL;
66d2d089 978 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 979 /* Check that we don't already have this key. */
980 B43_WARN_ON(dev->key[i].keyconf == keyconf);
981 }
982 if (index < 0) {
e808e586 983 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 984 if (b43_new_kidx_api(dev))
66d2d089 985 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 986 else
66d2d089
MB		 987 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
988 for (i = pairwise_keys_start;
989 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
990 i++) {
991 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 992 if (!dev->key[i].keyconf) {
993 /* found empty */
994 index = i;
995 break;
996 }
997 }
998 if (index < 0) {
e808e586 999 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1000 return -ENOSPC;
1001 }
1002 } else
1003 B43_WARN_ON(index > 3);
1004
1005 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1006 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1007 /* Default RX key */
1008 B43_WARN_ON(mac_addr);
1009 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1010 }
1011 keyconf->hw_key_idx = index;
1012 dev->key[index].keyconf = keyconf;
1013
1014 return 0;
1015}
1016
1017static int b43_key_clear(struct b43_wldev *dev, int index)
1018{
66d2d089 1019 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1020 return -EINVAL;
1021 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1022 NULL, B43_SEC_KEYSIZE, NULL);
1023 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1024 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 }
1027 dev->key[index].keyconf = NULL;
1028
1029 return 0;
1030}
1031
1032static void b43_clear_keys(struct b43_wldev *dev)
1033{
66d2d089 1034 int i, count;
e4d6b795 1035
66d2d089
MB		 1036 if (b43_new_kidx_api(dev))
1037 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1038 else
1039 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1040 for (i = 0; i < count; i++)
e4d6b795
MB		 1041 b43_key_clear(dev, i);
1042}
1043
9cf7f247
MB		 1044static void b43_dump_keymemory(struct b43_wldev *dev)
1045{
66d2d089 1046 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1047 u8 mac[ETH_ALEN];
1048 u16 algo;
1049 u32 rcmta0;
1050 u16 rcmta1;
1051 u64 hf;
1052 struct b43_key *key;
1053
1054 if (!b43_debug(dev, B43_DBG_KEYS))
1055 return;
1056
1057 hf = b43_hf_read(dev);
1058 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1059 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1060 if (b43_new_kidx_api(dev)) {
1061 pairwise_keys_start = B43_NR_GROUP_KEYS;
1062 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1063 } else {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1065 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1066 }
1067 for (index = 0; index < count; index++) {
9cf7f247
MB		 1068 key = &(dev->key[index]);
1069 printk(KERN_DEBUG "Key slot %02u: %s",
1070 index, (key->keyconf == NULL) ? " " : "*");
1071 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1072 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1073 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1074 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1075 }
1076
1077 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1078 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1079 printk(" Algo: %04X/%02X", algo, key->algorithm);
1080
66d2d089 1081 if (index >= pairwise_keys_start) {
035d0243 1082 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1083 printk(" TKIP: ");
1084 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1085 for (i = 0; i < 14; i += 2) {
1086 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1087 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1088 }
1089 }
9cf7f247 1090 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1091 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1092 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1093 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1094 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1095 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1096 printk(" MAC: %pM", mac);
9cf7f247
MB		 1097 } else
1098 printk(" DEFAULT KEY");
1099 printk("\n");
1100 }
1101}
1102
e4d6b795
MB		 1103void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1104{
1105 u32 macctl;
1106 u16 ucstat;
1107 bool hwps;
1108 bool awake;
1109 int i;
1110
1111 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1112 (ps_flags & B43_PS_DISABLED));
1113 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1114
1115 if (ps_flags & B43_PS_ENABLED) {
1116 hwps = 1;
1117 } else if (ps_flags & B43_PS_DISABLED) {
1118 hwps = 0;
1119 } else {
1120 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1121 // and thus is not an AP and we are associated, set bit 25
1122 }
1123 if (ps_flags & B43_PS_AWAKE) {
1124 awake = 1;
1125 } else if (ps_flags & B43_PS_ASLEEP) {
1126 awake = 0;
1127 } else {
1128 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1129 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1130 // successful, set bit26
1131 }
1132
1133/* FIXME: For now we force awake-on and hwps-off */
1134 hwps = 0;
1135 awake = 1;
1136
1137 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1138 if (hwps)
1139 macctl |= B43_MACCTL_HWPS;
1140 else
1141 macctl &= ~B43_MACCTL_HWPS;
1142 if (awake)
1143 macctl |= B43_MACCTL_AWAKE;
1144 else
1145 macctl &= ~B43_MACCTL_AWAKE;
1146 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1147 /* Commit write */
1148 b43_read32(dev, B43_MMIO_MACCTL);
1149 if (awake && dev->dev->id.revision >= 5) {
1150 /* Wait for the microcode to wake up. */
1151 for (i = 0; i < 100; i++) {
1152 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1153 B43_SHM_SH_UCODESTAT);
1154 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1155 break;
1156 udelay(10);
1157 }
1158 }
1159}
1160
e4d6b795
MB		 1161void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1162{
1163 u32 tmslow;
1164 u32 macctl;
1165
1166 flags |= B43_TMSLOW_PHYCLKEN;
1167 flags |= B43_TMSLOW_PHYRESET;
1168 ssb_device_enable(dev->dev, flags);
1169 msleep(2); /* Wait for the PLL to turn on. */
1170
1171 /* Now take the PHY out of Reset again */
1172 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1173 tmslow |= SSB_TMSLOW_FGC;
1174 tmslow &= ~B43_TMSLOW_PHYRESET;
1175 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1176 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1177 msleep(1);
1178 tmslow &= ~SSB_TMSLOW_FGC;
1179 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1180 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1181 msleep(1);
1182
fb11137a
MB		 1183 /* Turn Analog ON, but only if we already know the PHY-type.
1184 * This protects against very early setup where we don't know the
1185 * PHY-type, yet. wireless_core_reset will be called once again later,
1186 * when we know the PHY-type. */
1187 if (dev->phy.ops)
cb24f57f 1188 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1189
1190 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1191 macctl &= ~B43_MACCTL_GMODE;
1192 if (flags & B43_TMSLOW_GMODE)
1193 macctl |= B43_MACCTL_GMODE;
1194 macctl |= B43_MACCTL_IHR_ENABLED;
1195 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1196}
1197
1198static void handle_irq_transmit_status(struct b43_wldev *dev)
1199{
1200 u32 v0, v1;
1201 u16 tmp;
1202 struct b43_txstatus stat;
1203
1204 while (1) {
1205 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1206 if (!(v0 & 0x00000001))
1207 break;
1208 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1209
1210 stat.cookie = (v0 >> 16);
1211 stat.seq = (v1 & 0x0000FFFF);
1212 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1213 tmp = (v0 & 0x0000FFFF);
1214 stat.frame_count = ((tmp & 0xF000) >> 12);
1215 stat.rts_count = ((tmp & 0x0F00) >> 8);
1216 stat.supp_reason = ((tmp & 0x001C) >> 2);
1217 stat.pm_indicated = !!(tmp & 0x0080);
1218 stat.intermediate = !!(tmp & 0x0040);
1219 stat.for_ampdu = !!(tmp & 0x0020);
1220 stat.acked = !!(tmp & 0x0002);
1221
1222 b43_handle_txstatus(dev, &stat);
1223 }
1224}
1225
1226static void drain_txstatus_queue(struct b43_wldev *dev)
1227{
1228 u32 dummy;
1229
1230 if (dev->dev->id.revision < 5)
1231 return;
1232 /* Read all entries from the microcode TXstatus FIFO
1233 * and throw them away.
1234 */
1235 while (1) {
1236 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1237 if (!(dummy & 0x00000001))
1238 break;
1239 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1240 }
1241}
1242
1243static u32 b43_jssi_read(struct b43_wldev *dev)
1244{
1245 u32 val = 0;
1246
1247 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1248 val <<= 16;
1249 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1250
1251 return val;
1252}
1253
1254static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1255{
1256 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1257 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1258}
1259
1260static void b43_generate_noise_sample(struct b43_wldev *dev)
1261{
1262 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1263 b43_write32(dev, B43_MMIO_MACCMD,
1264 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1265}
1266
1267static void b43_calculate_link_quality(struct b43_wldev *dev)
1268{
1269 /* Top half of Link Quality calculation. */
1270
ef1a628d
MB		 1271 if (dev->phy.type != B43_PHYTYPE_G)
1272 return;
e4d6b795
MB		 1273 if (dev->noisecalc.calculation_running)
1274 return;
e4d6b795
MB		 1275 dev->noisecalc.calculation_running = 1;
1276 dev->noisecalc.nr_samples = 0;
1277
1278 b43_generate_noise_sample(dev);
1279}
1280
1281static void handle_irq_noise(struct b43_wldev *dev)
1282{
ef1a628d 1283 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1284 u16 tmp;
1285 u8 noise[4];
1286 u8 i, j;
1287 s32 average;
1288
1289 /* Bottom half of Link Quality calculation. */
1290
ef1a628d
MB		 1291 if (dev->phy.type != B43_PHYTYPE_G)
1292 return;
1293
98a3b2fe
MB		 1294 /* Possible race condition: It might be possible that the user
1295 * changed to a different channel in the meantime since we
1296 * started the calculation. We ignore that fact, since it's
1297 * not really that much of a problem. The background noise is
1298 * an estimation only anyway. Slightly wrong results will get damped
1299 * by the averaging of the 8 sample rounds. Additionally the
1300 * value is shortlived. So it will be replaced by the next noise
1301 * calculation round soon. */
1302
e4d6b795 1303 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1304 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1305 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1306 noise[2] == 0x7F || noise[3] == 0x7F)
1307 goto generate_new;
1308
1309 /* Get the noise samples. */
1310 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1311 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1312 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1313 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1314 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1315 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1316 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1317 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1318 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1319 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1320 dev->noisecalc.nr_samples++;
1321 if (dev->noisecalc.nr_samples == 8) {
1322 /* Calculate the Link Quality by the noise samples. */
1323 average = 0;
1324 for (i = 0; i < 8; i++) {
1325 for (j = 0; j < 4; j++)
1326 average += dev->noisecalc.samples[i][j];
1327 }
1328 average /= (8 * 4);
1329 average *= 125;
1330 average += 64;
1331 average /= 128;
1332 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1333 tmp = (tmp / 128) & 0x1F;
1334 if (tmp >= 8)
1335 average += 2;
1336 else
1337 average -= 25;
1338 if (tmp == 8)
1339 average -= 72;
1340 else
1341 average -= 48;
1342
1343 dev->stats.link_noise = average;
e4d6b795
MB		 1344 dev->noisecalc.calculation_running = 0;
1345 return;
1346 }
98a3b2fe 1347generate_new:
e4d6b795
MB		 1348 b43_generate_noise_sample(dev);
1349}
1350
1351static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1352{
05c914fe 1353 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1354 ///TODO: PS TBTT
1355 } else {
1356 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1357 b43_power_saving_ctl_bits(dev, 0);
1358 }
05c914fe 1359 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1360 dev->dfq_valid = 1;
e4d6b795
MB		 1361}
1362
1363static void handle_irq_atim_end(struct b43_wldev *dev)
1364{
aa6c7ae2
MB		 1365 if (dev->dfq_valid) {
1366 b43_write32(dev, B43_MMIO_MACCMD,
1367 b43_read32(dev, B43_MMIO_MACCMD)
1368 | B43_MACCMD_DFQ_VALID);
1369 dev->dfq_valid = 0;
1370 }
e4d6b795
MB		 1371}
1372
1373static void handle_irq_pmq(struct b43_wldev *dev)
1374{
1375 u32 tmp;
1376
1377 //TODO: AP mode.
1378
1379 while (1) {
1380 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1381 if (!(tmp & 0x00000008))
1382 break;
1383 }
1384 /* 16bit write is odd, but correct. */
1385 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1386}
1387
1388static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1389 const u8 *data, u16 size,
e4d6b795
MB		 1390 u16 ram_offset,
1391 u16 shm_size_offset, u8 rate)
1392{
1393 u32 i, tmp;
1394 struct b43_plcp_hdr4 plcp;
1395
1396 plcp.data = 0;
1397 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1398 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1399 ram_offset += sizeof(u32);
1400 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1401 * So leave the first two bytes of the next write blank.
1402 */
1403 tmp = (u32) (data[0]) << 16;
1404 tmp |= (u32) (data[1]) << 24;
1405 b43_ram_write(dev, ram_offset, tmp);
1406 ram_offset += sizeof(u32);
1407 for (i = 2; i < size; i += sizeof(u32)) {
1408 tmp = (u32) (data[i + 0]);
1409 if (i + 1 < size)
1410 tmp |= (u32) (data[i + 1]) << 8;
1411 if (i + 2 < size)
1412 tmp |= (u32) (data[i + 2]) << 16;
1413 if (i + 3 < size)
1414 tmp |= (u32) (data[i + 3]) << 24;
1415 b43_ram_write(dev, ram_offset + i - 2, tmp);
1416 }
1417 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1418 size + sizeof(struct b43_plcp_hdr6));
1419}
1420
5042c507
MB		 1421/* Check if the use of the antenna that ieee80211 told us to
1422 * use is possible. This will fall back to DEFAULT.
1423 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1424u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1425 u8 antenna_nr)
1426{
1427 u8 antenna_mask;
1428
1429 if (antenna_nr == 0) {
1430 /* Zero means "use default antenna". That's always OK. */
1431 return 0;
1432 }
1433
1434 /* Get the mask of available antennas. */
1435 if (dev->phy.gmode)
1436 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1437 else
1438 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1439
1440 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1441 /* This antenna is not available. Fall back to default. */
1442 return 0;
1443 }
1444
1445 return antenna_nr;
1446}
1447
5042c507
MB		 1448/* Convert a b43 antenna number value to the PHY TX control value. */
1449static u16 b43_antenna_to_phyctl(int antenna)
1450{
1451 switch (antenna) {
1452 case B43_ANTENNA0:
1453 return B43_TXH_PHY_ANT0;
1454 case B43_ANTENNA1:
1455 return B43_TXH_PHY_ANT1;
1456 case B43_ANTENNA2:
1457 return B43_TXH_PHY_ANT2;
1458 case B43_ANTENNA3:
1459 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1460 case B43_ANTENNA_AUTO0:
1461 case B43_ANTENNA_AUTO1:
5042c507
MB		 1462 return B43_TXH_PHY_ANT01AUTO;
1463 }
1464 B43_WARN_ON(1);
1465 return 0;
1466}
1467
e4d6b795
MB		 1468static void b43_write_beacon_template(struct b43_wldev *dev,
1469 u16 ram_offset,
5042c507 1470 u16 shm_size_offset)
e4d6b795 1471{
47f76ca3 1472 unsigned int i, len, variable_len;
e66fee6a
MB		 1473 const struct ieee80211_mgmt *bcn;
1474 const u8 *ie;
1475 bool tim_found = 0;
5042c507
MB		 1476 unsigned int rate;
1477 u16 ctl;
1478 int antenna;
e039fa4a 1479 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1480
e66fee6a
MB		 1481 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1482 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1483 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1484 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1485
1486 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1487 len, ram_offset, shm_size_offset, rate);
e66fee6a 1488
5042c507 1489 /* Write the PHY TX control parameters. */
0f4ac38b 1490 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1491 antenna = b43_antenna_to_phyctl(antenna);
1492 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1493 /* We can't send beacons with short preamble. Would get PHY errors. */
1494 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1495 ctl &= ~B43_TXH_PHY_ANT;
1496 ctl &= ~B43_TXH_PHY_ENC;
1497 ctl |= antenna;
1498 if (b43_is_cck_rate(rate))
1499 ctl |= B43_TXH_PHY_ENC_CCK;
1500 else
1501 ctl |= B43_TXH_PHY_ENC_OFDM;
1502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1503
e66fee6a
MB		 1504 /* Find the position of the TIM and the DTIM_period value
1505 * and write them to SHM. */
1506 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1507 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1508 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1509 uint8_t ie_id, ie_len;
1510
1511 ie_id = ie[i];
1512 ie_len = ie[i + 1];
1513 if (ie_id == 5) {
1514 u16 tim_position;
1515 u16 dtim_period;
1516 /* This is the TIM Information Element */
1517
1518 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1519 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1520 break;
1521 /* A valid TIM is at least 4 bytes long. */
1522 if (ie_len < 4)
1523 break;
1524 tim_found = 1;
1525
1526 tim_position = sizeof(struct b43_plcp_hdr6);
1527 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1528 tim_position += i;
1529
1530 dtim_period = ie[i + 3];
1531
1532 b43_shm_write16(dev, B43_SHM_SHARED,
1533 B43_SHM_SH_TIMBPOS, tim_position);
1534 b43_shm_write16(dev, B43_SHM_SHARED,
1535 B43_SHM_SH_DTIMPER, dtim_period);
1536 break;
1537 }
1538 i += ie_len + 2;
1539 }
1540 if (!tim_found) {
04dea136
JB		 1541 /*
1542 * If ucode wants to modify TIM do it behind the beacon, this
1543 * will happen, for example, when doing mesh networking.
1544 */
1545 b43_shm_write16(dev, B43_SHM_SHARED,
1546 B43_SHM_SH_TIMBPOS,
1547 len + sizeof(struct b43_plcp_hdr6));
1548 b43_shm_write16(dev, B43_SHM_SHARED,
1549 B43_SHM_SH_DTIMPER, 0);
1550 }
1551 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1552}
1553
6b4bec01
MB		 1554static void b43_upload_beacon0(struct b43_wldev *dev)
1555{
1556 struct b43_wl *wl = dev->wl;
1557
1558 if (wl->beacon0_uploaded)
1559 return;
1560 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1561 wl->beacon0_uploaded = 1;
1562}
1563
1564static void b43_upload_beacon1(struct b43_wldev *dev)
1565{
1566 struct b43_wl *wl = dev->wl;
1567
1568 if (wl->beacon1_uploaded)
1569 return;
1570 b43_write_beacon_template(dev, 0x468, 0x1A);
1571 wl->beacon1_uploaded = 1;
1572}
1573
c97a4ccc
MB		 1574static void handle_irq_beacon(struct b43_wldev *dev)
1575{
1576 struct b43_wl *wl = dev->wl;
1577 u32 cmd, beacon0_valid, beacon1_valid;
1578
05c914fe
JB		 1579 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1580 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1581 return;
1582
1583 /* This is the bottom half of the asynchronous beacon update. */
1584
1585 /* Ignore interrupt in the future. */
13790728 1586 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1587
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1590 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1591
1592 /* Schedule interrupt manually, if busy. */
1593 if (beacon0_valid && beacon1_valid) {
1594 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1595 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1596 return;
1597 }
1598
6b4bec01
MB		 1599 if (unlikely(wl->beacon_templates_virgin)) {
1600 /* We never uploaded a beacon before.
1601 * Upload both templates now, but only mark one valid. */
1602 wl->beacon_templates_virgin = 0;
1603 b43_upload_beacon0(dev);
1604 b43_upload_beacon1(dev);
c97a4ccc
MB		 1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON0_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1608 } else {
1609 if (!beacon0_valid) {
1610 b43_upload_beacon0(dev);
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 cmd |= B43_MACCMD_BEACON0_VALID;
1613 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1614 } else if (!beacon1_valid) {
1615 b43_upload_beacon1(dev);
1616 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1617 cmd |= B43_MACCMD_BEACON1_VALID;
1618 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1619 }
c97a4ccc
MB		 1620 }
1621}
1622
a82d9922
MB		 1623static void b43_beacon_update_trigger_work(struct work_struct *work)
1624{
1625 struct b43_wl *wl = container_of(work, struct b43_wl,
1626 beacon_update_trigger);
1627 struct b43_wldev *dev;
1628
1629 mutex_lock(&wl->mutex);
1630 dev = wl->current_dev;
1631 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1632 spin_lock_irq(&wl->irq_lock);
c97a4ccc 1633 /* update beacon right away or defer to irq */
c97a4ccc
MB		 1634 handle_irq_beacon(dev);
1635 /* The handler might have updated the IRQ mask. */
13790728 1636 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
c97a4ccc 1637 mmiowb();
a82d9922
MB		 1638 spin_unlock_irq(&wl->irq_lock);
1639 }
1640 mutex_unlock(&wl->mutex);
1641}
1642
d4df6f1a
MB		 1643/* Asynchronously update the packet templates in template RAM.
1644 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1645static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1646{
9d139c81
JB		 1647 struct sk_buff *beacon;
1648
e66fee6a
MB		 1649 /* This is the top half of the ansynchronous beacon update.
1650 * The bottom half is the beacon IRQ.
1651 * Beacon update must be asynchronous to avoid sending an
1652 * invalid beacon. This can happen for example, if the firmware
1653 * transmits a beacon while we are updating it. */
e4d6b795 1654
9d139c81
JB		 1655 /* We could modify the existing beacon and set the aid bit in
1656 * the TIM field, but that would probably require resizing and
1657 * moving of data within the beacon template.
1658 * Simply request a new beacon and let mac80211 do the hard work. */
1659 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1660 if (unlikely(!beacon))
1661 return;
1662
e66fee6a
MB		 1663 if (wl->current_beacon)
1664 dev_kfree_skb_any(wl->current_beacon);
1665 wl->current_beacon = beacon;
1666 wl->beacon0_uploaded = 0;
1667 wl->beacon1_uploaded = 0;
42935eca 1668 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1669}
1670
e4d6b795
MB		 1671static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1672{
1673 b43_time_lock(dev);
1674 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1675 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1676 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1677 } else {
1678 b43_write16(dev, 0x606, (beacon_int >> 6));
1679 b43_write16(dev, 0x610, beacon_int);
1680 }
1681 b43_time_unlock(dev);
a82d9922 1682 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1683}
1684
afa83e23
MB		 1685static void b43_handle_firmware_panic(struct b43_wldev *dev)
1686{
1687 u16 reason;
1688
1689 /* Read the register that contains the reason code for the panic. */
1690 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1691 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1692
1693 switch (reason) {
1694 default:
1695 b43dbg(dev->wl, "The panic reason is unknown.\n");
1696 /* fallthrough */
1697 case B43_FWPANIC_DIE:
1698 /* Do not restart the controller or firmware.
1699 * The device is nonfunctional from now on.
1700 * Restarting would result in this panic to trigger again,
1701 * so we avoid that recursion. */
1702 break;
1703 case B43_FWPANIC_RESTART:
1704 b43_controller_restart(dev, "Microcode panic");
1705 break;
1706 }
1707}
1708
e4d6b795
MB		 1709static void handle_irq_ucode_debug(struct b43_wldev *dev)
1710{
e48b0eeb 1711 unsigned int i, cnt;
53c06856 1712 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1713 __le16 *buf;
1714
1715 /* The proprietary firmware doesn't have this IRQ. */
1716 if (!dev->fw.opensource)
1717 return;
1718
afa83e23
MB		 1719 /* Read the register that contains the reason code for this IRQ. */
1720 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1721
e48b0eeb
MB		 1722 switch (reason) {
1723 case B43_DEBUGIRQ_PANIC:
afa83e23 1724 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1725 break;
1726 case B43_DEBUGIRQ_DUMP_SHM:
1727 if (!B43_DEBUG)
1728 break; /* Only with driver debugging enabled. */
1729 buf = kmalloc(4096, GFP_ATOMIC);
1730 if (!buf) {
1731 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1732 goto out;
1733 }
1734 for (i = 0; i < 4096; i += 2) {
1735 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1736 buf[i / 2] = cpu_to_le16(tmp);
1737 }
1738 b43info(dev->wl, "Shared memory dump:\n");
1739 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1740 16, 2, buf, 4096, 1);
1741 kfree(buf);
1742 break;
1743 case B43_DEBUGIRQ_DUMP_REGS:
1744 if (!B43_DEBUG)
1745 break; /* Only with driver debugging enabled. */
1746 b43info(dev->wl, "Microcode register dump:\n");
1747 for (i = 0, cnt = 0; i < 64; i++) {
1748 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1749 if (cnt == 0)
1750 printk(KERN_INFO);
1751 printk("r%02u: 0x%04X ", i, tmp);
1752 cnt++;
1753 if (cnt == 6) {
1754 printk("\n");
1755 cnt = 0;
1756 }
1757 }
1758 printk("\n");
1759 break;
53c06856
MB		 1760 case B43_DEBUGIRQ_MARKER:
1761 if (!B43_DEBUG)
1762 break; /* Only with driver debugging enabled. */
1763 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1764 B43_MARKER_ID_REG);
1765 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1766 B43_MARKER_LINE_REG);
1767 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1768 "at line number %u\n",
1769 marker_id, marker_line);
1770 break;
e48b0eeb
MB		 1771 default:
1772 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1773 reason);
1774 }
1775out:
afa83e23
MB		 1776 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1777 b43_shm_write16(dev, B43_SHM_SCRATCH,
1778 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1779}
1780
1781/* Interrupt handler bottom-half */
1782static void b43_interrupt_tasklet(struct b43_wldev *dev)
1783{
1784 u32 reason;
1785 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1786 u32 merged_dma_reason = 0;
21954c36 1787 int i;
e4d6b795
MB		 1788 unsigned long flags;
1789
1790 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1791
1792 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1793
1794 reason = dev->irq_reason;
1795 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1796 dma_reason[i] = dev->dma_reason[i];
1797 merged_dma_reason |= dma_reason[i];
1798 }
1799
1800 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1801 b43err(dev->wl, "MAC transmission error\n");
1802
00e0b8cb 1803 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1804 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1805 rmb();
1806 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1807 atomic_set(&dev->phy.txerr_cnt,
1808 B43_PHY_TX_BADNESS_LIMIT);
1809 b43err(dev->wl, "Too many PHY TX errors, "
1810 "restarting the controller\n");
1811 b43_controller_restart(dev, "PHY TX errors");
1812 }
1813 }
e4d6b795
MB		 1814
1815 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1816 B43_DMAIRQ_NONFATALMASK))) {
1817 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1818 b43err(dev->wl, "Fatal DMA error: "
1819 "0x%08X, 0x%08X, 0x%08X, "
1820 "0x%08X, 0x%08X, 0x%08X\n",
1821 dma_reason[0], dma_reason[1],
1822 dma_reason[2], dma_reason[3],
1823 dma_reason[4], dma_reason[5]);
1824 b43_controller_restart(dev, "DMA error");
1825 mmiowb();
1826 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1827 return;
1828 }
1829 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1830 b43err(dev->wl, "DMA error: "
1831 "0x%08X, 0x%08X, 0x%08X, "
1832 "0x%08X, 0x%08X, 0x%08X\n",
1833 dma_reason[0], dma_reason[1],
1834 dma_reason[2], dma_reason[3],
1835 dma_reason[4], dma_reason[5]);
1836 }
1837 }
1838
1839 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1840 handle_irq_ucode_debug(dev);
1841 if (reason & B43_IRQ_TBTT_INDI)
1842 handle_irq_tbtt_indication(dev);
1843 if (reason & B43_IRQ_ATIM_END)
1844 handle_irq_atim_end(dev);
1845 if (reason & B43_IRQ_BEACON)
1846 handle_irq_beacon(dev);
1847 if (reason & B43_IRQ_PMQ)
1848 handle_irq_pmq(dev);
21954c36
MB		 1849 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1850 ;/* TODO */
1851 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1852 handle_irq_noise(dev);
1853
1854 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1855 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1856 if (b43_using_pio_transfers(dev))
1857 b43_pio_rx(dev->pio.rx_queue);
1858 else
1859 b43_dma_rx(dev->dma.rx_ring);
1860 }
e4d6b795
MB		 1861 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1862 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1863 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1864 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1865 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1866
21954c36 1867 if (reason & B43_IRQ_TX_OK)
e4d6b795 1868 handle_irq_transmit_status(dev);
e4d6b795 1869
13790728 1870 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 1871 mmiowb();
1872 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1873}
1874
e4d6b795
MB		 1875static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1876{
e4d6b795
MB		 1877 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1878
1879 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1880 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1881 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1882 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1883 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
13790728 1884/* Unused ring
e4d6b795 1885 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
13790728 1886*/
e4d6b795
MB		 1887}
1888
1889/* Interrupt handler top-half */
1890static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1891{
1892 irqreturn_t ret = IRQ_NONE;
1893 struct b43_wldev *dev = dev_id;
1894 u32 reason;
1895
13790728 1896 B43_WARN_ON(!dev);
e4d6b795
MB		 1897
1898 spin_lock(&dev->wl->irq_lock);
1899
13790728
MB		 1900 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1901 /* This can only happen on shared IRQ lines. */
e4d6b795 1902 goto out;
13790728 1903 }
e4d6b795
MB		 1904 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1905 if (reason == 0xffffffff) /* shared IRQ */
1906 goto out;
1907 ret = IRQ_HANDLED;
13790728 1908 reason &= dev->irq_mask;
e4d6b795
MB		 1909 if (!reason)
1910 goto out;
1911
1912 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1913 & 0x0001DC00;
1914 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1915 & 0x0000DC00;
1916 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1917 & 0x0000DC00;
1918 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1919 & 0x0001DC00;
1920 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1921 & 0x0000DC00;
13790728 1922/* Unused ring
e4d6b795
MB		 1923 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1924 & 0x0000DC00;
13790728 1925*/
e4d6b795
MB		 1926
1927 b43_interrupt_ack(dev, reason);
1928 /* disable all IRQs. They are enabled again in the bottom half. */
13790728 1929 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
e4d6b795
MB		 1930 /* save the reason code and call our bottom half. */
1931 dev->irq_reason = reason;
1932 tasklet_schedule(&dev->isr_tasklet);
13790728 1933out:
e4d6b795
MB		 1934 mmiowb();
1935 spin_unlock(&dev->wl->irq_lock);
1936
1937 return ret;
1938}
1939
1a9f5093 1940void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1941{
1942 release_firmware(fw->data);
1943 fw->data = NULL;
1944 fw->filename = NULL;
1945}
1946
e4d6b795
MB		 1947static void b43_release_firmware(struct b43_wldev *dev)
1948{
1a9f5093
MB		 1949 b43_do_release_fw(&dev->fw.ucode);
1950 b43_do_release_fw(&dev->fw.pcm);
1951 b43_do_release_fw(&dev->fw.initvals);
1952 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1953}
1954
eb189d8b 1955static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1956{
fc68ed4f
HE		 1957 const char text[] =
1958 "You must go to " \
1959 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1960 "and download the correct firmware for this driver version. " \
1961 "Please carefully read all instructions on this website.\n";
eb189d8b 1962
eb189d8b
MB		 1963 if (error)
1964 b43err(wl, text);
1965 else
1966 b43warn(wl, text);
e4d6b795
MB		 1967}
1968
1a9f5093
MB		 1969int b43_do_request_fw(struct b43_request_fw_context *ctx,
1970 const char *name,
1971 struct b43_firmware_file *fw)
e4d6b795 1972{
61cb5dd6 1973 const struct firmware *blob;
e4d6b795
MB		 1974 struct b43_fw_header *hdr;
1975 u32 size;
1976 int err;
1977
61cb5dd6
MB		 1978 if (!name) {
1979 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1980 /* FIXME: We should probably keep it anyway, to save some headache
1981 * on suspend/resume with multiband devices. */
1982 b43_do_release_fw(fw);
e4d6b795 1983 return 0;
61cb5dd6
MB		 1984 }
1985 if (fw->filename) {
1a9f5093
MB		 1986 if ((fw->type == ctx->req_type) &&
1987 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1988 return 0; /* Already have this fw. */
1989 /* Free the cached firmware first. */
1a9f5093
MB		 1990 /* FIXME: We should probably do this later after we successfully
1991 * got the new fw. This could reduce headache with multiband devices.
1992 * We could also redesign this to cache the firmware for all possible
1993 * bands all the time. */
1994 b43_do_release_fw(fw);
61cb5dd6 1995 }
e4d6b795 1996
1a9f5093
MB		 1997 switch (ctx->req_type) {
1998 case B43_FWTYPE_PROPRIETARY:
1999 snprintf(ctx->fwname, sizeof(ctx->fwname),
2000 "b43%s/%s.fw",
2001 modparam_fwpostfix, name);
2002 break;
2003 case B43_FWTYPE_OPENSOURCE:
2004 snprintf(ctx->fwname, sizeof(ctx->fwname),
2005 "b43-open%s/%s.fw",
2006 modparam_fwpostfix, name);
2007 break;
2008 default:
2009 B43_WARN_ON(1);
2010 return -ENOSYS;
2011 }
2012 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2013 if (err == -ENOENT) {
1a9f5093
MB		 2014 snprintf(ctx->errors[ctx->req_type],
2015 sizeof(ctx->errors[ctx->req_type]),
2016 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2017 return err;
2018 } else if (err) {
1a9f5093
MB		 2019 snprintf(ctx->errors[ctx->req_type],
2020 sizeof(ctx->errors[ctx->req_type]),
2021 "Firmware file \"%s\" request failed (err=%d)\n",
2022 ctx->fwname, err);
e4d6b795
MB		 2023 return err;
2024 }
61cb5dd6 2025 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2026 goto err_format;
61cb5dd6 2027 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2028 switch (hdr->type) {
2029 case B43_FW_TYPE_UCODE:
2030 case B43_FW_TYPE_PCM:
2031 size = be32_to_cpu(hdr->size);
61cb5dd6 2032 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2033 goto err_format;
2034 /* fallthrough */
2035 case B43_FW_TYPE_IV:
2036 if (hdr->ver != 1)
2037 goto err_format;
2038 break;
2039 default:
2040 goto err_format;
2041 }
2042
61cb5dd6
MB		 2043 fw->data = blob;
2044 fw->filename = name;
1a9f5093 2045 fw->type = ctx->req_type;
61cb5dd6
MB		 2046
2047 return 0;
e4d6b795
MB		 2048
2049err_format:
1a9f5093
MB		 2050 snprintf(ctx->errors[ctx->req_type],
2051 sizeof(ctx->errors[ctx->req_type]),
2052 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2053 release_firmware(blob);
2054
e4d6b795
MB		 2055 return -EPROTO;
2056}
2057
1a9f5093 2058static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2059{
1a9f5093
MB		 2060 struct b43_wldev *dev = ctx->dev;
2061 struct b43_firmware *fw = &ctx->dev->fw;
2062 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2063 const char *filename;
2064 u32 tmshigh;
2065 int err;
2066
61cb5dd6 2067 /* Get microcode */
e4d6b795 2068 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2069 if ((rev >= 5) && (rev <= 10))
2070 filename = "ucode5";
2071 else if ((rev >= 11) && (rev <= 12))
2072 filename = "ucode11";
759b973b 2073 else if (rev == 13)
61cb5dd6 2074 filename = "ucode13";
759b973b
GS		 2075 else if (rev == 14)
2076 filename = "ucode14";
2077 else if (rev >= 15)
2078 filename = "ucode15";
61cb5dd6
MB		 2079 else
2080 goto err_no_ucode;
1a9f5093 2081 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2082 if (err)
2083 goto err_load;
2084
2085 /* Get PCM code */
2086 if ((rev >= 5) && (rev <= 10))
2087 filename = "pcm5";
2088 else if (rev >= 11)
2089 filename = NULL;
2090 else
2091 goto err_no_pcm;
68217832 2092 fw->pcm_request_failed = 0;
1a9f5093 2093 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2094 if (err == -ENOENT) {
2095 /* We did not find a PCM file? Not fatal, but
2096 * core rev <= 10 must do without hwcrypto then. */
2097 fw->pcm_request_failed = 1;
2098 } else if (err)
61cb5dd6
MB		 2099 goto err_load;
2100
2101 /* Get initvals */
2102 switch (dev->phy.type) {
2103 case B43_PHYTYPE_A:
2104 if ((rev >= 5) && (rev <= 10)) {
2105 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2106 filename = "a0g1initvals5";
2107 else
2108 filename = "a0g0initvals5";
2109 } else
2110 goto err_no_initvals;
2111 break;
2112 case B43_PHYTYPE_G:
e4d6b795 2113 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2114 filename = "b0g0initvals5";
e4d6b795 2115 else if (rev >= 13)
e9304882 2116 filename = "b0g0initvals13";
e4d6b795 2117 else
61cb5dd6
MB		 2118 goto err_no_initvals;
2119 break;
2120 case B43_PHYTYPE_N:
2121 if ((rev >= 11) && (rev <= 12))
2122 filename = "n0initvals11";
2123 else
2124 goto err_no_initvals;
2125 break;
759b973b
GS		 2126 case B43_PHYTYPE_LP:
2127 if (rev == 13)
2128 filename = "lp0initvals13";
2129 else if (rev == 14)
2130 filename = "lp0initvals14";
2131 else if (rev >= 15)
2132 filename = "lp0initvals15";
2133 else
2134 goto err_no_initvals;
2135 break;
61cb5dd6
MB		 2136 default:
2137 goto err_no_initvals;
e4d6b795 2138 }
1a9f5093 2139 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2140 if (err)
2141 goto err_load;
2142
2143 /* Get bandswitch initvals */
2144 switch (dev->phy.type) {
2145 case B43_PHYTYPE_A:
2146 if ((rev >= 5) && (rev <= 10)) {
2147 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2148 filename = "a0g1bsinitvals5";
2149 else
2150 filename = "a0g0bsinitvals5";
2151 } else if (rev >= 11)
2152 filename = NULL;
2153 else
2154 goto err_no_initvals;
2155 break;
2156 case B43_PHYTYPE_G:
e4d6b795 2157 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2158 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2159 else if (rev >= 11)
2160 filename = NULL;
2161 else
e4d6b795 2162 goto err_no_initvals;
61cb5dd6
MB		 2163 break;
2164 case B43_PHYTYPE_N:
2165 if ((rev >= 11) && (rev <= 12))
2166 filename = "n0bsinitvals11";
2167 else
e4d6b795 2168 goto err_no_initvals;
61cb5dd6 2169 break;
759b973b
GS		 2170 case B43_PHYTYPE_LP:
2171 if (rev == 13)
2172 filename = "lp0bsinitvals13";
2173 else if (rev == 14)
2174 filename = "lp0bsinitvals14";
2175 else if (rev >= 15)
2176 filename = "lp0bsinitvals15";
2177 else
2178 goto err_no_initvals;
2179 break;
61cb5dd6
MB		 2180 default:
2181 goto err_no_initvals;
e4d6b795 2182 }
1a9f5093 2183 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2184 if (err)
2185 goto err_load;
e4d6b795
MB		 2186
2187 return 0;
2188
e4d6b795 2189err_no_ucode:
1a9f5093
MB		 2190 err = ctx->fatal_failure = -EOPNOTSUPP;
2191 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2192 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2193 goto error;
2194
2195err_no_pcm:
1a9f5093
MB		 2196 err = ctx->fatal_failure = -EOPNOTSUPP;
2197 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2198 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2199 goto error;
2200
2201err_no_initvals:
1a9f5093
MB		 2202 err = ctx->fatal_failure = -EOPNOTSUPP;
2203 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2204 "is required for your device (wl-core rev %u)\n", rev);
2205 goto error;
2206
2207err_load:
2208 /* We failed to load this firmware image. The error message
2209 * already is in ctx->errors. Return and let our caller decide
2210 * what to do. */
e4d6b795
MB		 2211 goto error;
2212
2213error:
2214 b43_release_firmware(dev);
2215 return err;
2216}
2217
1a9f5093
MB		 2218static int b43_request_firmware(struct b43_wldev *dev)
2219{
2220 struct b43_request_fw_context *ctx;
2221 unsigned int i;
2222 int err;
2223 const char *errmsg;
2224
2225 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2226 if (!ctx)
2227 return -ENOMEM;
2228 ctx->dev = dev;
2229
2230 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2231 err = b43_try_request_fw(ctx);
2232 if (!err)
2233 goto out; /* Successfully loaded it. */
2234 err = ctx->fatal_failure;
2235 if (err)
2236 goto out;
2237
2238 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2239 err = b43_try_request_fw(ctx);
2240 if (!err)
2241 goto out; /* Successfully loaded it. */
2242 err = ctx->fatal_failure;
2243 if (err)
2244 goto out;
2245
2246 /* Could not find a usable firmware. Print the errors. */
2247 for (i = 0; i < B43_NR_FWTYPES; i++) {
2248 errmsg = ctx->errors[i];
2249 if (strlen(errmsg))
2250 b43err(dev->wl, errmsg);
2251 }
2252 b43_print_fw_helptext(dev->wl, 1);
2253 err = -ENOENT;
2254
2255out:
2256 kfree(ctx);
2257 return err;
2258}
2259
e4d6b795
MB		 2260static int b43_upload_microcode(struct b43_wldev *dev)
2261{
2262 const size_t hdr_len = sizeof(struct b43_fw_header);
2263 const __be32 *data;
2264 unsigned int i, len;
2265 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2266 u32 tmp, macctl;
e4d6b795
MB		 2267 int err = 0;
2268
1f7d87b0
MB		 2269 /* Jump the microcode PSM to offset 0 */
2270 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2271 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2272 macctl |= B43_MACCTL_PSM_JMP0;
2273 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2274 /* Zero out all microcode PSM registers and shared memory. */
2275 for (i = 0; i < 64; i++)
2276 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2277 for (i = 0; i < 4096; i += 2)
2278 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2279
e4d6b795 2280 /* Upload Microcode. */
61cb5dd6
MB		 2281 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2282 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2283 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2284 for (i = 0; i < len; i++) {
2285 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2286 udelay(10);
2287 }
2288
61cb5dd6 2289 if (dev->fw.pcm.data) {
e4d6b795 2290 /* Upload PCM data. */
61cb5dd6
MB		 2291 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2292 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2293 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2294 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2295 /* No need for autoinc bit in SHM_HW */
2296 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2297 for (i = 0; i < len; i++) {
2298 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2299 udelay(10);
2300 }
2301 }
2302
2303 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2304
2305 /* Start the microcode PSM */
2306 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2307 macctl &= ~B43_MACCTL_PSM_JMP0;
2308 macctl |= B43_MACCTL_PSM_RUN;
2309 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2310
2311 /* Wait for the microcode to load and respond */
2312 i = 0;
2313 while (1) {
2314 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2315 if (tmp == B43_IRQ_MAC_SUSPENDED)
2316 break;
2317 i++;
1f7d87b0 2318 if (i >= 20) {
e4d6b795 2319 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2320 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2321 err = -ENODEV;
1f7d87b0
MB		 2322 goto error;
2323 }
2324 msleep_interruptible(50);
2325 if (signal_pending(current)) {
2326 err = -EINTR;
2327 goto error;
e4d6b795 2328 }
e4d6b795
MB		 2329 }
2330 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2331
2332 /* Get and check the revisions. */
2333 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2334 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2335 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2336 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2337
2338 if (fwrev <= 0x128) {
2339 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2340 "binary drivers older than version 4.x is unsupported. "
2341 "You must upgrade your firmware files.\n");
eb189d8b 2342 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2343 err = -EOPNOTSUPP;
1f7d87b0 2344 goto error;
e4d6b795 2345 }
e4d6b795
MB		 2346 dev->fw.rev = fwrev;
2347 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2348 dev->fw.opensource = (fwdate == 0xFFFF);
2349
403a3a13
MB		 2350 /* Default to use-all-queues. */
2351 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2352 dev->qos_enabled = !!modparam_qos;
2353 /* Default to firmware/hardware crypto acceleration. */
2354 dev->hwcrypto_enabled = 1;
2355
e48b0eeb 2356 if (dev->fw.opensource) {
403a3a13
MB		 2357 u16 fwcapa;
2358
e48b0eeb
MB		 2359 /* Patchlevel info is encoded in the "time" field. */
2360 dev->fw.patch = fwtime;
403a3a13
MB		 2361 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2362 dev->fw.rev, dev->fw.patch);
2363
2364 fwcapa = b43_fwcapa_read(dev);
2365 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2366 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2367 /* Disable hardware crypto and fall back to software crypto. */
2368 dev->hwcrypto_enabled = 0;
2369 }
2370 if (!(fwcapa & B43_FWCAPA_QOS)) {
2371 b43info(dev->wl, "QoS not supported by firmware\n");
2372 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2373 * ieee80211_unregister to make sure the networking core can
2374 * properly free possible resources. */
2375 dev->wl->hw->queues = 1;
2376 dev->qos_enabled = 0;
2377 }
e48b0eeb
MB		 2378 } else {
2379 b43info(dev->wl, "Loading firmware version %u.%u "
2380 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2381 fwrev, fwpatch,
2382 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2383 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2384 if (dev->fw.pcm_request_failed) {
2385 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2386 "Hardware accelerated cryptography is disabled.\n");
2387 b43_print_fw_helptext(dev->wl, 0);
2388 }
e48b0eeb 2389 }
e4d6b795 2390
eb189d8b 2391 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2392 /* We're over the deadline, but we keep support for old fw
2393 * until it turns out to be in major conflict with something new. */
eb189d8b 2394 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2395 "Support for old firmware will be removed soon "
2396 "(official deadline was July 2008).\n");
eb189d8b
MB		 2397 b43_print_fw_helptext(dev->wl, 0);
2398 }
2399
1f7d87b0
MB		 2400 return 0;
2401
2402error:
2403 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2404 macctl &= ~B43_MACCTL_PSM_RUN;
2405 macctl |= B43_MACCTL_PSM_JMP0;
2406 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2407
e4d6b795
MB		 2408 return err;
2409}
2410
2411static int b43_write_initvals(struct b43_wldev *dev,
2412 const struct b43_iv *ivals,
2413 size_t count,
2414 size_t array_size)
2415{
2416 const struct b43_iv *iv;
2417 u16 offset;
2418 size_t i;
2419 bool bit32;
2420
2421 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2422 iv = ivals;
2423 for (i = 0; i < count; i++) {
2424 if (array_size < sizeof(iv->offset_size))
2425 goto err_format;
2426 array_size -= sizeof(iv->offset_size);
2427 offset = be16_to_cpu(iv->offset_size);
2428 bit32 = !!(offset & B43_IV_32BIT);
2429 offset &= B43_IV_OFFSET_MASK;
2430 if (offset >= 0x1000)
2431 goto err_format;
2432 if (bit32) {
2433 u32 value;
2434
2435 if (array_size < sizeof(iv->data.d32))
2436 goto err_format;
2437 array_size -= sizeof(iv->data.d32);
2438
533dd1b0 2439 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2440 b43_write32(dev, offset, value);
2441
2442 iv = (const struct b43_iv *)((const uint8_t *)iv +
2443 sizeof(__be16) +
2444 sizeof(__be32));
2445 } else {
2446 u16 value;
2447
2448 if (array_size < sizeof(iv->data.d16))
2449 goto err_format;
2450 array_size -= sizeof(iv->data.d16);
2451
2452 value = be16_to_cpu(iv->data.d16);
2453 b43_write16(dev, offset, value);
2454
2455 iv = (const struct b43_iv *)((const uint8_t *)iv +
2456 sizeof(__be16) +
2457 sizeof(__be16));
2458 }
2459 }
2460 if (array_size)
2461 goto err_format;
2462
2463 return 0;
2464
2465err_format:
2466 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2467 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2468
2469 return -EPROTO;
2470}
2471
2472static int b43_upload_initvals(struct b43_wldev *dev)
2473{
2474 const size_t hdr_len = sizeof(struct b43_fw_header);
2475 const struct b43_fw_header *hdr;
2476 struct b43_firmware *fw = &dev->fw;
2477 const struct b43_iv *ivals;
2478 size_t count;
2479 int err;
2480
61cb5dd6
MB		 2481 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2482 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2483 count = be32_to_cpu(hdr->size);
2484 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2485 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2486 if (err)
2487 goto out;
61cb5dd6
MB		 2488 if (fw->initvals_band.data) {
2489 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2490 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2491 count = be32_to_cpu(hdr->size);
2492 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2493 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2494 if (err)
2495 goto out;
2496 }
2497out:
2498
2499 return err;
2500}
2501
2502/* Initialize the GPIOs
2503 * http://bcm-specs.sipsolutions.net/GPIO
2504 */
2505static int b43_gpio_init(struct b43_wldev *dev)
2506{
2507 struct ssb_bus *bus = dev->dev->bus;
2508 struct ssb_device *gpiodev, *pcidev = NULL;
2509 u32 mask, set;
2510
2511 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2512 & ~B43_MACCTL_GPOUTSMSK);
2513
e4d6b795
MB		 2514 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2515 | 0x000F);
2516
2517 mask = 0x0000001F;
2518 set = 0x0000000F;
2519 if (dev->dev->bus->chip_id == 0x4301) {
2520 mask |= 0x0060;
2521 set |= 0x0060;
2522 }
2523 if (0 /* FIXME: conditional unknown */ ) {
2524 b43_write16(dev, B43_MMIO_GPIO_MASK,
2525 b43_read16(dev, B43_MMIO_GPIO_MASK)
2526 | 0x0100);
2527 mask |= 0x0180;
2528 set |= 0x0180;
2529 }
95de2841 2530 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2531 b43_write16(dev, B43_MMIO_GPIO_MASK,
2532 b43_read16(dev, B43_MMIO_GPIO_MASK)
2533 | 0x0200);
2534 mask |= 0x0200;
2535 set |= 0x0200;
2536 }
2537 if (dev->dev->id.revision >= 2)
2538 mask |= 0x0010; /* FIXME: This is redundant. */
2539
2540#ifdef CONFIG_SSB_DRIVER_PCICORE
2541 pcidev = bus->pcicore.dev;
2542#endif
2543 gpiodev = bus->chipco.dev ? : pcidev;
2544 if (!gpiodev)
2545 return 0;
2546 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2547 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2548 & mask) | set);
2549
2550 return 0;
2551}
2552
2553/* Turn off all GPIO stuff. Call this on module unload, for example. */
2554static void b43_gpio_cleanup(struct b43_wldev *dev)
2555{
2556 struct ssb_bus *bus = dev->dev->bus;
2557 struct ssb_device *gpiodev, *pcidev = NULL;
2558
2559#ifdef CONFIG_SSB_DRIVER_PCICORE
2560 pcidev = bus->pcicore.dev;
2561#endif
2562 gpiodev = bus->chipco.dev ? : pcidev;
2563 if (!gpiodev)
2564 return;
2565 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2566}
2567
2568/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2569void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2570{
923fd703
MB		 2571 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2572 u16 fwstate;
2573
2574 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2575 B43_SHM_SH_UCODESTAT);
2576 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2577 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2578 b43err(dev->wl, "b43_mac_enable(): The firmware "
2579 "should be suspended, but current state is %u\n",
2580 fwstate);
2581 }
2582 }
2583
e4d6b795
MB		 2584 dev->mac_suspended--;
2585 B43_WARN_ON(dev->mac_suspended < 0);
2586 if (dev->mac_suspended == 0) {
2587 b43_write32(dev, B43_MMIO_MACCTL,
2588 b43_read32(dev, B43_MMIO_MACCTL)
2589 | B43_MACCTL_ENABLED);
2590 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2591 B43_IRQ_MAC_SUSPENDED);
2592 /* Commit writes */
2593 b43_read32(dev, B43_MMIO_MACCTL);
2594 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2595 b43_power_saving_ctl_bits(dev, 0);
2596 }
2597}
2598
2599/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2600void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2601{
2602 int i;
2603 u32 tmp;
2604
05b64b36 2605 might_sleep();
e4d6b795 2606 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2607
e4d6b795
MB		 2608 if (dev->mac_suspended == 0) {
2609 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2610 b43_write32(dev, B43_MMIO_MACCTL,
2611 b43_read32(dev, B43_MMIO_MACCTL)
2612 & ~B43_MACCTL_ENABLED);
2613 /* force pci to flush the write */
2614 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2615 for (i = 35; i; i--) {
2616 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2617 if (tmp & B43_IRQ_MAC_SUSPENDED)
2618 goto out;
2619 udelay(10);
2620 }
2621 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2622 for (i = 40; i; i--) {
e4d6b795
MB		 2623 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2624 if (tmp & B43_IRQ_MAC_SUSPENDED)
2625 goto out;
05b64b36 2626 msleep(1);
e4d6b795
MB		 2627 }
2628 b43err(dev->wl, "MAC suspend failed\n");
2629 }
05b64b36 2630out:
e4d6b795
MB		 2631 dev->mac_suspended++;
2632}
2633
2634static void b43_adjust_opmode(struct b43_wldev *dev)
2635{
2636 struct b43_wl *wl = dev->wl;
2637 u32 ctl;
2638 u16 cfp_pretbtt;
2639
2640 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2641 /* Reset status to STA infrastructure mode. */
2642 ctl &= ~B43_MACCTL_AP;
2643 ctl &= ~B43_MACCTL_KEEP_CTL;
2644 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2645 ctl &= ~B43_MACCTL_KEEP_BAD;
2646 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2647 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2648 ctl |= B43_MACCTL_INFRA;
2649
05c914fe
JB		 2650 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2651 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2652 ctl |= B43_MACCTL_AP;
05c914fe 2653 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2654 ctl &= ~B43_MACCTL_INFRA;
2655
2656 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2657 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2658 if (wl->filter_flags & FIF_FCSFAIL)
2659 ctl |= B43_MACCTL_KEEP_BAD;
2660 if (wl->filter_flags & FIF_PLCPFAIL)
2661 ctl |= B43_MACCTL_KEEP_BADPLCP;
2662 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2663 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2664 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2665 ctl |= B43_MACCTL_BEACPROMISC;
2666
e4d6b795
MB		 2667 /* Workaround: On old hardware the HW-MAC-address-filter
2668 * doesn't work properly, so always run promisc in filter
2669 * it in software. */
2670 if (dev->dev->id.revision <= 4)
2671 ctl |= B43_MACCTL_PROMISC;
2672
2673 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2674
2675 cfp_pretbtt = 2;
2676 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2677 if (dev->dev->bus->chip_id == 0x4306 &&
2678 dev->dev->bus->chip_rev == 3)
2679 cfp_pretbtt = 100;
2680 else
2681 cfp_pretbtt = 50;
2682 }
2683 b43_write16(dev, 0x612, cfp_pretbtt);
2684}
2685
2686static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2687{
2688 u16 offset;
2689
2690 if (is_ofdm) {
2691 offset = 0x480;
2692 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2693 } else {
2694 offset = 0x4C0;
2695 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2696 }
2697 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2698 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2699}
2700
2701static void b43_rate_memory_init(struct b43_wldev *dev)
2702{
2703 switch (dev->phy.type) {
2704 case B43_PHYTYPE_A:
2705 case B43_PHYTYPE_G:
53a6e234 2706 case B43_PHYTYPE_N:
9d86a2d5 2707 case B43_PHYTYPE_LP:
e4d6b795
MB		 2708 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2709 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2710 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2711 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2712 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2713 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2714 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2715 if (dev->phy.type == B43_PHYTYPE_A)
2716 break;
2717 /* fallthrough */
2718 case B43_PHYTYPE_B:
2719 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2720 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2721 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2722 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2723 break;
2724 default:
2725 B43_WARN_ON(1);
2726 }
2727}
2728
5042c507
MB		 2729/* Set the default values for the PHY TX Control Words. */
2730static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2731{
2732 u16 ctl = 0;
2733
2734 ctl |= B43_TXH_PHY_ENC_CCK;
2735 ctl |= B43_TXH_PHY_ANT01AUTO;
2736 ctl |= B43_TXH_PHY_TXPWR;
2737
2738 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2739 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2740 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2741}
2742
e4d6b795
MB		 2743/* Set the TX-Antenna for management frames sent by firmware. */
2744static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2745{
5042c507 2746 u16 ant;
e4d6b795
MB		 2747 u16 tmp;
2748
5042c507 2749 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2750
e4d6b795
MB		 2751 /* For ACK/CTS */
2752 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2753 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2754 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2755 /* For Probe Resposes */
2756 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2757 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2758 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2759}
2760
2761/* This is the opposite of b43_chip_init() */
2762static void b43_chip_exit(struct b43_wldev *dev)
2763{
fb11137a 2764 b43_phy_exit(dev);
e4d6b795
MB		 2765 b43_gpio_cleanup(dev);
2766 /* firmware is released later */
2767}
2768
2769/* Initialize the chip
2770 * http://bcm-specs.sipsolutions.net/ChipInit
2771 */
2772static int b43_chip_init(struct b43_wldev *dev)
2773{
2774 struct b43_phy *phy = &dev->phy;
ef1a628d 2775 int err;
1f7d87b0 2776 u32 value32, macctl;
e4d6b795
MB		 2777 u16 value16;
2778
1f7d87b0
MB		 2779 /* Initialize the MAC control */
2780 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2781 if (dev->phy.gmode)
2782 macctl |= B43_MACCTL_GMODE;
2783 macctl |= B43_MACCTL_INFRA;
2784 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2785
2786 err = b43_request_firmware(dev);
2787 if (err)
2788 goto out;
2789 err = b43_upload_microcode(dev);
2790 if (err)
2791 goto out; /* firmware is released later */
2792
2793 err = b43_gpio_init(dev);
2794 if (err)
2795 goto out; /* firmware is released later */
21954c36 2796
e4d6b795
MB		 2797 err = b43_upload_initvals(dev);
2798 if (err)
1a8d1227 2799 goto err_gpio_clean;
e4d6b795 2800
0b7dcd96
MB		 2801 /* Turn the Analog on and initialize the PHY. */
2802 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2803 err = b43_phy_init(dev);
2804 if (err)
ef1a628d 2805 goto err_gpio_clean;
e4d6b795 2806
ef1a628d
MB		 2807 /* Disable Interference Mitigation. */
2808 if (phy->ops->interf_mitigation)
2809 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2810
ef1a628d
MB		 2811 /* Select the antennae */
2812 if (phy->ops->set_rx_antenna)
2813 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2814 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2815
2816 if (phy->type == B43_PHYTYPE_B) {
2817 value16 = b43_read16(dev, 0x005E);
2818 value16 |= 0x0004;
2819 b43_write16(dev, 0x005E, value16);
2820 }
2821 b43_write32(dev, 0x0100, 0x01000000);
2822 if (dev->dev->id.revision < 5)
2823 b43_write32(dev, 0x010C, 0x01000000);
2824
2825 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2826 & ~B43_MACCTL_INFRA);
2827 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2828 | B43_MACCTL_INFRA);
e4d6b795 2829
e4d6b795
MB		 2830 /* Probe Response Timeout value */
2831 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2832 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2833
2834 /* Initially set the wireless operation mode. */
2835 b43_adjust_opmode(dev);
2836
2837 if (dev->dev->id.revision < 3) {
2838 b43_write16(dev, 0x060E, 0x0000);
2839 b43_write16(dev, 0x0610, 0x8000);
2840 b43_write16(dev, 0x0604, 0x0000);
2841 b43_write16(dev, 0x0606, 0x0200);
2842 } else {
2843 b43_write32(dev, 0x0188, 0x80000000);
2844 b43_write32(dev, 0x018C, 0x02000000);
2845 }
2846 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2847 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2848 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2849 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2850 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2851 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2852 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2853
2854 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2855 value32 |= 0x00100000;
2856 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2857
2858 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2859 dev->dev->bus->chipco.fast_pwrup_delay);
2860
2861 err = 0;
2862 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2863out:
e4d6b795
MB		 2864 return err;
2865
1a8d1227 2866err_gpio_clean:
e4d6b795 2867 b43_gpio_cleanup(dev);
21954c36 2868 return err;
e4d6b795
MB		 2869}
2870
e4d6b795
MB		 2871static void b43_periodic_every60sec(struct b43_wldev *dev)
2872{
ef1a628d 2873 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2874
ef1a628d
MB		 2875 if (ops->pwork_60sec)
2876 ops->pwork_60sec(dev);
18c8adeb
MB		 2877
2878 /* Force check the TX power emission now. */
2879 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2880}
2881
2882static void b43_periodic_every30sec(struct b43_wldev *dev)
2883{
2884 /* Update device statistics. */
2885 b43_calculate_link_quality(dev);
2886}
2887
2888static void b43_periodic_every15sec(struct b43_wldev *dev)
2889{
2890 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2891 u16 wdr;
2892
2893 if (dev->fw.opensource) {
2894 /* Check if the firmware is still alive.
2895 * It will reset the watchdog counter to 0 in its idle loop. */
2896 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2897 if (unlikely(wdr)) {
2898 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2899 b43_controller_restart(dev, "Firmware watchdog");
2900 return;
2901 } else {
2902 b43_shm_write16(dev, B43_SHM_SCRATCH,
2903 B43_WATCHDOG_REG, 1);
2904 }
2905 }
e4d6b795 2906
ef1a628d
MB		 2907 if (phy->ops->pwork_15sec)
2908 phy->ops->pwork_15sec(dev);
2909
00e0b8cb
SB		 2910 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2911 wmb();
e4d6b795
MB		 2912}
2913
e4d6b795
MB		 2914static void do_periodic_work(struct b43_wldev *dev)
2915{
2916 unsigned int state;
2917
2918 state = dev->periodic_state;
42bb4cd5 2919 if (state % 4 == 0)
e4d6b795 2920 b43_periodic_every60sec(dev);
42bb4cd5 2921 if (state % 2 == 0)
e4d6b795 2922 b43_periodic_every30sec(dev);
42bb4cd5 2923 b43_periodic_every15sec(dev);
e4d6b795
MB		 2924}
2925
05b64b36
MB		 2926/* Periodic work locking policy:
2927 * The whole periodic work handler is protected by
2928 * wl->mutex. If another lock is needed somewhere in the
2929 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2930 */
e4d6b795
MB		 2931static void b43_periodic_work_handler(struct work_struct *work)
2932{
05b64b36
MB		 2933 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2934 periodic_work.work);
2935 struct b43_wl *wl = dev->wl;
2936 unsigned long delay;
e4d6b795 2937
05b64b36 2938 mutex_lock(&wl->mutex);
e4d6b795
MB		 2939
2940 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2941 goto out;
2942 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2943 goto out_requeue;
2944
05b64b36 2945 do_periodic_work(dev);
e4d6b795 2946
e4d6b795 2947 dev->periodic_state++;
42bb4cd5 2948out_requeue:
e4d6b795
MB		 2949 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2950 delay = msecs_to_jiffies(50);
2951 else
82cd682d 2952 delay = round_jiffies_relative(HZ * 15);
42935eca 2953 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 2954out:
05b64b36 2955 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2956}
2957
2958static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2959{
2960 struct delayed_work *work = &dev->periodic_work;
2961
2962 dev->periodic_state = 0;
2963 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 2964 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 2965}
2966
f3dd3fcc 2967/* Check if communication with the device works correctly. */
e4d6b795
MB		 2968static int b43_validate_chipaccess(struct b43_wldev *dev)
2969{
f62ae6cd 2970 u32 v, backup0, backup4;
e4d6b795 2971
f62ae6cd
MB		 2972 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2973 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 2974
2975 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2976 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2977 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2978 goto error;
f3dd3fcc
MB		 2979 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2980 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2981 goto error;
2982
f62ae6cd
MB		 2983 /* Check if unaligned 32bit SHM_SHARED access works properly.
2984 * However, don't bail out on failure, because it's noncritical. */
2985 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
2986 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
2987 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
2988 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
2989 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
2990 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
2991 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
2992 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
2993 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
2994 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
2995 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
2996 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
2997
2998 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
2999 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 3000
3001 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3002 /* The 32bit register shadows the two 16bit registers
3003 * with update sideeffects. Validate this. */
3004 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3005 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3006 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3007 goto error;
3008 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3009 goto error;
3010 }
3011 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3012
3013 v = b43_read32(dev, B43_MMIO_MACCTL);
3014 v |= B43_MACCTL_GMODE;
3015 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3016 goto error;
3017
3018 return 0;
f3dd3fcc 3019error:
e4d6b795
MB		 3020 b43err(dev->wl, "Failed to validate the chipaccess\n");
3021 return -ENODEV;
3022}
3023
3024static void b43_security_init(struct b43_wldev *dev)
3025{
e4d6b795
MB		 3026 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3027 /* KTP is a word address, but we address SHM bytewise.
3028 * So multiply by two.
3029 */
3030 dev->ktp *= 2;
66d2d089
MB		 3031 /* Number of RCMTA address slots */
3032 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3033 /* Clear the key memory. */
e4d6b795
MB		 3034 b43_clear_keys(dev);
3035}
3036
616de35d 3037#ifdef CONFIG_B43_HWRNG
99da185a 3038static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3039{
3040 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3041 unsigned long flags;
3042
3043 /* Don't take wl->mutex here, as it could deadlock with
3044 * hwrng internal locking. It's not needed to take
3045 * wl->mutex here, anyway. */
3046
3047 spin_lock_irqsave(&wl->irq_lock, flags);
3048 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
3049 spin_unlock_irqrestore(&wl->irq_lock, flags);
3050
3051 return (sizeof(u16));
3052}
616de35d 3053#endif /* CONFIG_B43_HWRNG */
e4d6b795 3054
b844eba2 3055static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3056{
616de35d 3057#ifdef CONFIG_B43_HWRNG
e4d6b795 3058 if (wl->rng_initialized)
b844eba2 3059 hwrng_unregister(&wl->rng);
616de35d 3060#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3061}
3062
3063static int b43_rng_init(struct b43_wl *wl)
3064{
616de35d 3065 int err = 0;
e4d6b795 3066
616de35d 3067#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3068 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3069 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3070 wl->rng.name = wl->rng_name;
3071 wl->rng.data_read = b43_rng_read;
3072 wl->rng.priv = (unsigned long)wl;
3073 wl->rng_initialized = 1;
3074 err = hwrng_register(&wl->rng);
3075 if (err) {
3076 wl->rng_initialized = 0;
3077 b43err(wl, "Failed to register the random "
3078 "number generator (%d)\n", err);
3079 }
616de35d 3080#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3081
3082 return err;
3083}
3084
40faacc4 3085static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 3086 struct sk_buff *skb)
e4d6b795
MB		 3087{
3088 struct b43_wl *wl = hw_to_b43_wl(hw);
3089 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 3090 unsigned long flags;
3091 int err;
e4d6b795 3092
5100d5ac
MB		 3093 if (unlikely(skb->len < 2 + 2 + 6)) {
3094 /* Too short, this can't be a valid frame. */
c9e8eae0 3095 goto drop_packet;
5100d5ac
MB		 3096 }
3097 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 3098 if (unlikely(!dev))
c9e8eae0 3099 goto drop_packet;
21a75d77
MB		 3100
3101 /* Transmissions on seperate queues can run concurrently. */
3102 read_lock_irqsave(&wl->tx_lock, flags);
3103
3104 err = -ENODEV;
3105 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3106 if (b43_using_pio_transfers(dev))
e039fa4a 3107 err = b43_pio_tx(dev, skb);
21a75d77 3108 else
e039fa4a 3109 err = b43_dma_tx(dev, skb);
21a75d77
MB		 3110 }
3111
3112 read_unlock_irqrestore(&wl->tx_lock, flags);
3113
e4d6b795 3114 if (unlikely(err))
c9e8eae0
MB		 3115 goto drop_packet;
3116 return NETDEV_TX_OK;
3117
3118drop_packet:
3119 /* We can not transmit this packet. Drop it. */
3120 dev_kfree_skb_any(skb);
e4d6b795
MB		 3121 return NETDEV_TX_OK;
3122}
3123
e6f5b934
MB		 3124/* Locking: wl->irq_lock */
3125static void b43_qos_params_upload(struct b43_wldev *dev,
3126 const struct ieee80211_tx_queue_params *p,
3127 u16 shm_offset)
3128{
3129 u16 params[B43_NR_QOSPARAMS];
0b57664c 3130 int bslots, tmp;
e6f5b934
MB		 3131 unsigned int i;
3132
0b57664c 3133 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3134
3135 memset(&params, 0, sizeof(params));
3136
3137 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3138 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3139 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3140 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3141 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3142 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3143 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3144
3145 for (i = 0; i < ARRAY_SIZE(params); i++) {
3146 if (i == B43_QOSPARAM_STATUS) {
3147 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3148 shm_offset + (i * 2));
3149 /* Mark the parameters as updated. */
3150 tmp |= 0x100;
3151 b43_shm_write16(dev, B43_SHM_SHARED,
3152 shm_offset + (i * 2),
3153 tmp);
3154 } else {
3155 b43_shm_write16(dev, B43_SHM_SHARED,
3156 shm_offset + (i * 2),
3157 params[i]);
3158 }
3159 }
3160}
3161
c40c1129
MB		 3162/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3163static const u16 b43_qos_shm_offsets[] = {
3164 /* [mac80211-queue-nr] = SHM_OFFSET, */
3165 [0] = B43_QOS_VOICE,
3166 [1] = B43_QOS_VIDEO,
3167 [2] = B43_QOS_BESTEFFORT,
3168 [3] = B43_QOS_BACKGROUND,
3169};
3170
5a5f3b40
MB		 3171/* Update all QOS parameters in hardware. */
3172static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3173{
3174 struct b43_wl *wl = dev->wl;
3175 struct b43_qos_params *params;
e6f5b934
MB		 3176 unsigned int i;
3177
c40c1129
MB		 3178 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3179 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3180
3181 b43_mac_suspend(dev);
e6f5b934
MB		 3182 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3183 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3184 b43_qos_params_upload(dev, &(params->p),
3185 b43_qos_shm_offsets[i]);
e6f5b934 3186 }
e6f5b934
MB		 3187 b43_mac_enable(dev);
3188}
3189
3190static void b43_qos_clear(struct b43_wl *wl)
3191{
3192 struct b43_qos_params *params;
3193 unsigned int i;
3194
c40c1129
MB		 3195 /* Initialize QoS parameters to sane defaults. */
3196
3197 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3198 ARRAY_SIZE(wl->qos_params));
3199
e6f5b934
MB		 3200 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3201 params = &(wl->qos_params[i]);
3202
c40c1129
MB		 3203 switch (b43_qos_shm_offsets[i]) {
3204 case B43_QOS_VOICE:
3205 params->p.txop = 0;
3206 params->p.aifs = 2;
3207 params->p.cw_min = 0x0001;
3208 params->p.cw_max = 0x0001;
3209 break;
3210 case B43_QOS_VIDEO:
3211 params->p.txop = 0;
3212 params->p.aifs = 2;
3213 params->p.cw_min = 0x0001;
3214 params->p.cw_max = 0x0001;
3215 break;
3216 case B43_QOS_BESTEFFORT:
3217 params->p.txop = 0;
3218 params->p.aifs = 3;
3219 params->p.cw_min = 0x0001;
3220 params->p.cw_max = 0x03FF;
3221 break;
3222 case B43_QOS_BACKGROUND:
3223 params->p.txop = 0;
3224 params->p.aifs = 7;
3225 params->p.cw_min = 0x0001;
3226 params->p.cw_max = 0x03FF;
3227 break;
3228 default:
3229 B43_WARN_ON(1);
3230 }
e6f5b934
MB		 3231 }
3232}
3233
3234/* Initialize the core's QOS capabilities */
3235static void b43_qos_init(struct b43_wldev *dev)
3236{
e6f5b934 3237 /* Upload the current QOS parameters. */
5a5f3b40 3238 b43_qos_upload_all(dev);
e6f5b934
MB		 3239
3240 /* Enable QOS support. */
3241 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3242 b43_write16(dev, B43_MMIO_IFSCTL,
3243 b43_read16(dev, B43_MMIO_IFSCTL)
3244 | B43_MMIO_IFSCTL_USE_EDCF);
3245}
3246
e100bb64 3247static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3248 const struct ieee80211_tx_queue_params *params)
e4d6b795 3249{
e6f5b934 3250 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3251 struct b43_wldev *dev;
e6f5b934 3252 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3253 int err = -ENODEV;
e6f5b934
MB		 3254
3255 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3256 /* Queue not available or don't support setting
3257 * params on this queue. Return success to not
3258 * confuse mac80211. */
3259 return 0;
3260 }
5a5f3b40
MB		 3261 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3262 ARRAY_SIZE(wl->qos_params));
e6f5b934 3263
5a5f3b40
MB		 3264 mutex_lock(&wl->mutex);
3265 dev = wl->current_dev;
3266 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3267 goto out_unlock;
e6f5b934 3268
5a5f3b40
MB		 3269 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3270 b43_mac_suspend(dev);
3271 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3272 b43_qos_shm_offsets[queue]);
3273 b43_mac_enable(dev);
3274 err = 0;
e6f5b934 3275
5a5f3b40
MB		 3276out_unlock:
3277 mutex_unlock(&wl->mutex);
3278
3279 return err;
e4d6b795
MB		 3280}
3281
40faacc4
MB		 3282static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3283 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3284{
3285 struct b43_wl *wl = hw_to_b43_wl(hw);
3286 struct b43_wldev *dev = wl->current_dev;
3287 unsigned long flags;
3288 int err = -ENODEV;
3289
3290 if (!dev)
3291 goto out;
3292 spin_lock_irqsave(&wl->irq_lock, flags);
3293 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3294 if (b43_using_pio_transfers(dev))
3295 b43_pio_get_tx_stats(dev, stats);
3296 else
3297 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3298 err = 0;
3299 }
3300 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3301out:
e4d6b795
MB		 3302 return err;
3303}
3304
40faacc4
MB		 3305static int b43_op_get_stats(struct ieee80211_hw *hw,
3306 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3307{
3308 struct b43_wl *wl = hw_to_b43_wl(hw);
3309 unsigned long flags;
3310
3311 spin_lock_irqsave(&wl->irq_lock, flags);
3312 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3313 spin_unlock_irqrestore(&wl->irq_lock, flags);
3314
3315 return 0;
3316}
3317
08e87a83
AF		 3318static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3319{
3320 struct b43_wl *wl = hw_to_b43_wl(hw);
3321 struct b43_wldev *dev;
3322 u64 tsf;
3323
3324 mutex_lock(&wl->mutex);
3325 spin_lock_irq(&wl->irq_lock);
3326 dev = wl->current_dev;
3327
3328 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3329 b43_tsf_read(dev, &tsf);
3330 else
3331 tsf = 0;
3332
3333 spin_unlock_irq(&wl->irq_lock);
3334 mutex_unlock(&wl->mutex);
3335
3336 return tsf;
3337}
3338
3339static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3340{
3341 struct b43_wl *wl = hw_to_b43_wl(hw);
3342 struct b43_wldev *dev;
3343
3344 mutex_lock(&wl->mutex);
3345 spin_lock_irq(&wl->irq_lock);
3346 dev = wl->current_dev;
3347
3348 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3349 b43_tsf_write(dev, tsf);
3350
3351 spin_unlock_irq(&wl->irq_lock);
3352 mutex_unlock(&wl->mutex);
3353}
3354
e4d6b795
MB		 3355static void b43_put_phy_into_reset(struct b43_wldev *dev)
3356{
3357 struct ssb_device *sdev = dev->dev;
3358 u32 tmslow;
3359
3360 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3361 tmslow &= ~B43_TMSLOW_GMODE;
3362 tmslow |= B43_TMSLOW_PHYRESET;
3363 tmslow |= SSB_TMSLOW_FGC;
3364 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3365 msleep(1);
3366
3367 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3368 tmslow &= ~SSB_TMSLOW_FGC;
3369 tmslow |= B43_TMSLOW_PHYRESET;
3370 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3371 msleep(1);
3372}
3373
99da185a 3374static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3375{
3376 switch (band) {
3377 case IEEE80211_BAND_5GHZ:
3378 return "5";
3379 case IEEE80211_BAND_2GHZ:
3380 return "2.4";
3381 default:
3382 break;
3383 }
3384 B43_WARN_ON(1);
3385 return "";
3386}
3387
e4d6b795 3388/* Expects wl->mutex locked */
bb1eeff1 3389static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3390{
bb1eeff1 3391 struct b43_wldev *up_dev = NULL;
e4d6b795 3392 struct b43_wldev *down_dev;
bb1eeff1 3393 struct b43_wldev *d;
e4d6b795 3394 int err;
922d8a0b 3395 bool uninitialized_var(gmode);
e4d6b795
MB		 3396 int prev_status;
3397
bb1eeff1
MB		 3398 /* Find a device and PHY which supports the band. */
3399 list_for_each_entry(d, &wl->devlist, list) {
3400 switch (chan->band) {
3401 case IEEE80211_BAND_5GHZ:
3402 if (d->phy.supports_5ghz) {
3403 up_dev = d;
3404 gmode = 0;
3405 }
3406 break;
3407 case IEEE80211_BAND_2GHZ:
3408 if (d->phy.supports_2ghz) {
3409 up_dev = d;
3410 gmode = 1;
3411 }
3412 break;
3413 default:
3414 B43_WARN_ON(1);
3415 return -EINVAL;
3416 }
3417 if (up_dev)
3418 break;
3419 }
3420 if (!up_dev) {
3421 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3422 band_to_string(chan->band));
3423 return -ENODEV;
e4d6b795
MB		 3424 }
3425 if ((up_dev == wl->current_dev) &&
3426 (!!wl->current_dev->phy.gmode == !!gmode)) {
3427 /* This device is already running. */
3428 return 0;
3429 }
bb1eeff1
MB		 3430 b43dbg(wl, "Switching to %s-GHz band\n",
3431 band_to_string(chan->band));
e4d6b795
MB		 3432 down_dev = wl->current_dev;
3433
3434 prev_status = b43_status(down_dev);
3435 /* Shutdown the currently running core. */
3436 if (prev_status >= B43_STAT_STARTED)
3437 b43_wireless_core_stop(down_dev);
3438 if (prev_status >= B43_STAT_INITIALIZED)
3439 b43_wireless_core_exit(down_dev);
3440
3441 if (down_dev != up_dev) {
3442 /* We switch to a different core, so we put PHY into
3443 * RESET on the old core. */
3444 b43_put_phy_into_reset(down_dev);
3445 }
3446
3447 /* Now start the new core. */
3448 up_dev->phy.gmode = gmode;
3449 if (prev_status >= B43_STAT_INITIALIZED) {
3450 err = b43_wireless_core_init(up_dev);
3451 if (err) {
3452 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3453 "selected %s-GHz band\n",
3454 band_to_string(chan->band));
e4d6b795
MB		 3455 goto init_failure;
3456 }
3457 }
3458 if (prev_status >= B43_STAT_STARTED) {
3459 err = b43_wireless_core_start(up_dev);
3460 if (err) {
3461 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3462 "selected %s-GHz band\n",
3463 band_to_string(chan->band));
e4d6b795
MB		 3464 b43_wireless_core_exit(up_dev);
3465 goto init_failure;
3466 }
3467 }
3468 B43_WARN_ON(b43_status(up_dev) != prev_status);
3469
3470 wl->current_dev = up_dev;
3471
3472 return 0;
bb1eeff1 3473init_failure:
e4d6b795
MB		 3474 /* Whoops, failed to init the new core. No core is operating now. */
3475 wl->current_dev = NULL;
3476 return err;
3477}
3478
9124b077
JB		 3479/* Write the short and long frame retry limit values. */
3480static void b43_set_retry_limits(struct b43_wldev *dev,
3481 unsigned int short_retry,
3482 unsigned int long_retry)
3483{
3484 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3485 * the chip-internal counter. */
3486 short_retry = min(short_retry, (unsigned int)0xF);
3487 long_retry = min(long_retry, (unsigned int)0xF);
3488
3489 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3490 short_retry);
3491 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3492 long_retry);
3493}
3494
e8975581 3495static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3496{
3497 struct b43_wl *wl = hw_to_b43_wl(hw);
3498 struct b43_wldev *dev;
3499 struct b43_phy *phy;
e8975581 3500 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3501 unsigned long flags;
9db1f6d7 3502 int antenna;
e4d6b795 3503 int err = 0;
e4d6b795 3504
e4d6b795
MB		 3505 mutex_lock(&wl->mutex);
3506
bb1eeff1
MB		 3507 /* Switch the band (if necessary). This might change the active core. */
3508 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3509 if (err)
3510 goto out_unlock_mutex;
3511 dev = wl->current_dev;
3512 phy = &dev->phy;
3513
d10d0e57
MB		 3514 b43_mac_suspend(dev);
3515
9124b077
JB		 3516 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3517 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3518 conf->long_frame_max_tx_count);
3519 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3520 if (!changed)
d10d0e57 3521 goto out_mac_enable;
e4d6b795
MB		 3522
3523 /* Switch to the requested channel.
3524 * The firmware takes care of races with the TX handler. */
8318d78a 3525 if (conf->channel->hw_value != phy->channel)
ef1a628d 3526 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3527
d42ce84a
JB		 3528 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3529
e4d6b795
MB		 3530 /* Adjust the desired TX power level. */
3531 if (conf->power_level != 0) {
18c8adeb
MB		 3532 spin_lock_irqsave(&wl->irq_lock, flags);
3533 if (conf->power_level != phy->desired_txpower) {
3534 phy->desired_txpower = conf->power_level;
3535 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3536 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3537 }
18c8adeb 3538 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3539 }
3540
3541 /* Antennas for RX and management frame TX. */
0f4ac38b 3542 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3543 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3544 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3545 if (phy->ops->set_rx_antenna)
3546 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3547
fd4973c5
LF		 3548 if (wl->radio_enabled != phy->radio_on) {
3549 if (wl->radio_enabled) {
19d337df 3550 b43_software_rfkill(dev, false);
fda9abcf
MB		 3551 b43info(dev->wl, "Radio turned on by software\n");
3552 if (!dev->radio_hw_enable) {
3553 b43info(dev->wl, "The hardware RF-kill button "
3554 "still turns the radio physically off. "
3555 "Press the button to turn it on.\n");
3556 }
3557 } else {
19d337df 3558 b43_software_rfkill(dev, true);
fda9abcf
MB		 3559 b43info(dev->wl, "Radio turned off by software\n");
3560 }
3561 }
3562
d10d0e57
MB		 3563out_mac_enable:
3564 b43_mac_enable(dev);
3565out_unlock_mutex:
e4d6b795
MB		 3566 mutex_unlock(&wl->mutex);
3567
3568 return err;
3569}
3570
881d948c 3571static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3572{
3573 struct ieee80211_supported_band *sband =
3574 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3575 struct ieee80211_rate *rate;
3576 int i;
3577 u16 basic, direct, offset, basic_offset, rateptr;
3578
3579 for (i = 0; i < sband->n_bitrates; i++) {
3580 rate = &sband->bitrates[i];
3581
3582 if (b43_is_cck_rate(rate->hw_value)) {
3583 direct = B43_SHM_SH_CCKDIRECT;
3584 basic = B43_SHM_SH_CCKBASIC;
3585 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3586 offset &= 0xF;
3587 } else {
3588 direct = B43_SHM_SH_OFDMDIRECT;
3589 basic = B43_SHM_SH_OFDMBASIC;
3590 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3591 offset &= 0xF;
3592 }
3593
3594 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3595
3596 if (b43_is_cck_rate(rate->hw_value)) {
3597 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3598 basic_offset &= 0xF;
3599 } else {
3600 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3601 basic_offset &= 0xF;
3602 }
3603
3604 /*
3605 * Get the pointer that we need to point to
3606 * from the direct map
3607 */
3608 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3609 direct + 2 * basic_offset);
3610 /* and write it to the basic map */
3611 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3612 rateptr);
3613 }
3614}
3615
3616static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3617 struct ieee80211_vif *vif,
3618 struct ieee80211_bss_conf *conf,
3619 u32 changed)
3620{
3621 struct b43_wl *wl = hw_to_b43_wl(hw);
3622 struct b43_wldev *dev;
2d0ddec5 3623 unsigned long flags;
c7ab5ef9
JB		 3624
3625 mutex_lock(&wl->mutex);
3626
3627 dev = wl->current_dev;
d10d0e57 3628 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3629 goto out_unlock_mutex;
2d0ddec5
JB		 3630
3631 B43_WARN_ON(wl->vif != vif);
3632
3f0d843b 3633 spin_lock_irqsave(&wl->irq_lock, flags);
2d0ddec5 3634 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3635 if (conf->bssid)
3636 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3637 else
3638 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3639 }
2d0ddec5 3640
3f0d843b
JB		 3641 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3642 if (changed & BSS_CHANGED_BEACON &&
3643 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3644 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3645 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3646 b43_update_templates(wl);
3647
3648 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3649 b43_write_mac_bssid_templates(dev);
2d0ddec5 3650 }
3f0d843b 3651 spin_unlock_irqrestore(&wl->irq_lock, flags);
2d0ddec5 3652
c7ab5ef9
JB		 3653 b43_mac_suspend(dev);
3654
57c4d7b4
JB		 3655 /* Update templates for AP/mesh mode. */
3656 if (changed & BSS_CHANGED_BEACON_INT &&
3657 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3658 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3659 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3660 b43_set_beacon_int(dev, conf->beacon_int);
3661
c7ab5ef9
JB		 3662 if (changed & BSS_CHANGED_BASIC_RATES)
3663 b43_update_basic_rates(dev, conf->basic_rates);
3664
3665 if (changed & BSS_CHANGED_ERP_SLOT) {
3666 if (conf->use_short_slot)
3667 b43_short_slot_timing_enable(dev);
3668 else
3669 b43_short_slot_timing_disable(dev);
3670 }
3671
3672 b43_mac_enable(dev);
d10d0e57 3673out_unlock_mutex:
c7ab5ef9 3674 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3675}
3676
40faacc4 3677static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3678 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3679 struct ieee80211_key_conf *key)
e4d6b795
MB		 3680{
3681 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3682 struct b43_wldev *dev;
e4d6b795
MB		 3683 u8 algorithm;
3684 u8 index;
c6dfc9a8 3685 int err;
060210f9 3686 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3687
3688 if (modparam_nohwcrypt)
3689 return -ENOSPC; /* User disabled HW-crypto */
3690
c6dfc9a8 3691 mutex_lock(&wl->mutex);
e808e586
MB		 3692 spin_lock_irq(&wl->irq_lock);
3693 write_lock(&wl->tx_lock);
3694 /* Why do we need all this locking here?
3695 * mutex -> Every config operation must take it.
3696 * irq_lock -> We modify the dev->key array, which is accessed
3697 * in the IRQ handlers.
3698 * tx_lock -> We modify the dev->key array, which is accessed
3699 * in the TX handler.
3700 */
c6dfc9a8
MB		 3701
3702 dev = wl->current_dev;
3703 err = -ENODEV;
3704 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3705 goto out_unlock;
3706
403a3a13 3707 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3708 /* We don't have firmware for the crypto engine.
3709 * Must use software-crypto. */
3710 err = -EOPNOTSUPP;
3711 goto out_unlock;
3712 }
3713
c6dfc9a8 3714 err = -EINVAL;
e4d6b795 3715 switch (key->alg) {
e4d6b795 3716 case ALG_WEP:
e31a16d6 3717 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3718 algorithm = B43_SEC_ALGO_WEP40;
3719 else
3720 algorithm = B43_SEC_ALGO_WEP104;
3721 break;
3722 case ALG_TKIP:
3723 algorithm = B43_SEC_ALGO_TKIP;
3724 break;
3725 case ALG_CCMP:
3726 algorithm = B43_SEC_ALGO_AES;
3727 break;
3728 default:
3729 B43_WARN_ON(1);
c6dfc9a8 3730 goto out_unlock;
e4d6b795 3731 }
e4d6b795
MB		 3732 index = (u8) (key->keyidx);
3733 if (index > 3)
e4d6b795 3734 goto out_unlock;
e4d6b795
MB		 3735
3736 switch (cmd) {
3737 case SET_KEY:
035d0243 3738 if (algorithm == B43_SEC_ALGO_TKIP &&
3739 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3740 !modparam_hwtkip)) {
3741 /* We support only pairwise key */
e4d6b795
MB		 3742 err = -EOPNOTSUPP;
3743 goto out_unlock;
3744 }
3745
e808e586 3746 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3747 if (WARN_ON(!sta)) {
3748 err = -EOPNOTSUPP;
3749 goto out_unlock;
3750 }
e808e586 3751 /* Pairwise key with an assigned MAC address. */
e4d6b795 3752 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3753 key->key, key->keylen,
3754 sta->addr, key);
e808e586
MB		 3755 } else {
3756 /* Group key */
3757 err = b43_key_write(dev, index, algorithm,
3758 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3759 }
3760 if (err)
3761 goto out_unlock;
3762
3763 if (algorithm == B43_SEC_ALGO_WEP40 ||
3764 algorithm == B43_SEC_ALGO_WEP104) {
3765 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3766 } else {
3767 b43_hf_write(dev,
3768 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3769 }
3770 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3771 if (algorithm == B43_SEC_ALGO_TKIP)
3772 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3773 break;
3774 case DISABLE_KEY: {
3775 err = b43_key_clear(dev, key->hw_key_idx);
3776 if (err)
3777 goto out_unlock;
3778 break;
3779 }
3780 default:
3781 B43_WARN_ON(1);
3782 }
9cf7f247 3783
e4d6b795 3784out_unlock:
e4d6b795
MB		 3785 if (!err) {
3786 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3787 "mac: %pM\n",
e4d6b795 3788 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3789 sta ? sta->addr : bcast_addr);
9cf7f247 3790 b43_dump_keymemory(dev);
e4d6b795 3791 }
e808e586
MB		 3792 write_unlock(&wl->tx_lock);
3793 spin_unlock_irq(&wl->irq_lock);
9cf7f247
MB		 3794 mutex_unlock(&wl->mutex);
3795
e4d6b795
MB		 3796 return err;
3797}
3798
40faacc4
MB		 3799static void b43_op_configure_filter(struct ieee80211_hw *hw,
3800 unsigned int changed, unsigned int *fflags,
3ac64bee 3801 u64 multicast)
e4d6b795
MB		 3802{
3803 struct b43_wl *wl = hw_to_b43_wl(hw);
3804 struct b43_wldev *dev = wl->current_dev;
3805 unsigned long flags;
3806
4150c572
JB		 3807 if (!dev) {
3808 *fflags = 0;
e4d6b795 3809 return;
e4d6b795 3810 }
4150c572
JB		 3811
3812 spin_lock_irqsave(&wl->irq_lock, flags);
3813 *fflags &= FIF_PROMISC_IN_BSS |
3814 FIF_ALLMULTI |
3815 FIF_FCSFAIL |
3816 FIF_PLCPFAIL |
3817 FIF_CONTROL |
3818 FIF_OTHER_BSS |
3819 FIF_BCN_PRBRESP_PROMISC;
3820
3821 changed &= FIF_PROMISC_IN_BSS |
3822 FIF_ALLMULTI |
3823 FIF_FCSFAIL |
3824 FIF_PLCPFAIL |
3825 FIF_CONTROL |
3826 FIF_OTHER_BSS |
3827 FIF_BCN_PRBRESP_PROMISC;
3828
3829 wl->filter_flags = *fflags;
3830
3831 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3832 b43_adjust_opmode(dev);
e4d6b795
MB		 3833 spin_unlock_irqrestore(&wl->irq_lock, flags);
3834}
3835
e4d6b795
MB		 3836/* Locking: wl->mutex */
3837static void b43_wireless_core_stop(struct b43_wldev *dev)
3838{
3839 struct b43_wl *wl = dev->wl;
3840 unsigned long flags;
3841
3842 if (b43_status(dev) < B43_STAT_STARTED)
3843 return;
a19d12d7
SB		 3844
3845 /* Disable and sync interrupts. We must do this before than
3846 * setting the status to INITIALIZED, as the interrupt handler
3847 * won't care about IRQs then. */
3848 spin_lock_irqsave(&wl->irq_lock, flags);
13790728 3849 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
a19d12d7
SB		 3850 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3851 spin_unlock_irqrestore(&wl->irq_lock, flags);
3852 b43_synchronize_irq(dev);
3853
21a75d77 3854 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3855 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3856 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3857
5100d5ac 3858 b43_pio_stop(dev);
e4d6b795
MB		 3859 mutex_unlock(&wl->mutex);
3860 /* Must unlock as it would otherwise deadlock. No races here.
3861 * Cancel the possibly running self-rearming periodic work. */
3862 cancel_delayed_work_sync(&dev->periodic_work);
3863 mutex_lock(&wl->mutex);
3864
e4d6b795
MB		 3865 b43_mac_suspend(dev);
3866 free_irq(dev->dev->irq, dev);
3867 b43dbg(wl, "Wireless interface stopped\n");
3868}
3869
3870/* Locking: wl->mutex */
3871static int b43_wireless_core_start(struct b43_wldev *dev)
3872{
3873 int err;
3874
3875 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3876
3877 drain_txstatus_queue(dev);
3878 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3879 IRQF_SHARED, KBUILD_MODNAME, dev);
3880 if (err) {
3881 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3882 goto out;
3883 }
3884
3885 /* We are ready to run. */
3886 b43_set_status(dev, B43_STAT_STARTED);
3887
3888 /* Start data flow (TX/RX). */
3889 b43_mac_enable(dev);
13790728 3890 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3891
3892 /* Start maintainance work */
3893 b43_periodic_tasks_setup(dev);
3894
3895 b43dbg(dev->wl, "Wireless interface started\n");
3896 out:
3897 return err;
3898}
3899
3900/* Get PHY and RADIO versioning numbers */
3901static int b43_phy_versioning(struct b43_wldev *dev)
3902{
3903 struct b43_phy *phy = &dev->phy;
3904 u32 tmp;
3905 u8 analog_type;
3906 u8 phy_type;
3907 u8 phy_rev;
3908 u16 radio_manuf;
3909 u16 radio_ver;
3910 u16 radio_rev;
3911 int unsupported = 0;
3912
3913 /* Get PHY versioning */
3914 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3915 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3916 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3917 phy_rev = (tmp & B43_PHYVER_VERSION);
3918 switch (phy_type) {
3919 case B43_PHYTYPE_A:
3920 if (phy_rev >= 4)
3921 unsupported = 1;
3922 break;
3923 case B43_PHYTYPE_B:
3924 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3925 && phy_rev != 7)
3926 unsupported = 1;
3927 break;
3928 case B43_PHYTYPE_G:
013978b6 3929 if (phy_rev > 9)
e4d6b795
MB		 3930 unsupported = 1;
3931 break;
d5c71e46
MB		 3932#ifdef CONFIG_B43_NPHY
3933 case B43_PHYTYPE_N:
bb519bee 3934 if (phy_rev > 4)
d5c71e46
MB		 3935 unsupported = 1;
3936 break;
6b1c7c67
MB		 3937#endif
3938#ifdef CONFIG_B43_PHY_LP
3939 case B43_PHYTYPE_LP:
9d86a2d5 3940 if (phy_rev > 2)
6b1c7c67
MB		 3941 unsupported = 1;
3942 break;
d5c71e46 3943#endif
e4d6b795
MB		 3944 default:
3945 unsupported = 1;
3946 };
3947 if (unsupported) {
3948 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3949 "(Analog %u, Type %u, Revision %u)\n",
3950 analog_type, phy_type, phy_rev);
3951 return -EOPNOTSUPP;
3952 }
3953 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3954 analog_type, phy_type, phy_rev);
3955
3956 /* Get RADIO versioning */
3957 if (dev->dev->bus->chip_id == 0x4317) {
3958 if (dev->dev->bus->chip_rev == 0)
3959 tmp = 0x3205017F;
3960 else if (dev->dev->bus->chip_rev == 1)
3961 tmp = 0x4205017F;
3962 else
3963 tmp = 0x5205017F;
3964 } else {
3965 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3966 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3967 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3968 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3969 }
3970 radio_manuf = (tmp & 0x00000FFF);
3971 radio_ver = (tmp & 0x0FFFF000) >> 12;
3972 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3973 if (radio_manuf != 0x17F /* Broadcom */)
3974 unsupported = 1;
e4d6b795
MB		 3975 switch (phy_type) {
3976 case B43_PHYTYPE_A:
3977 if (radio_ver != 0x2060)
3978 unsupported = 1;
3979 if (radio_rev != 1)
3980 unsupported = 1;
3981 if (radio_manuf != 0x17F)
3982 unsupported = 1;
3983 break;
3984 case B43_PHYTYPE_B:
3985 if ((radio_ver & 0xFFF0) != 0x2050)
3986 unsupported = 1;
3987 break;
3988 case B43_PHYTYPE_G:
3989 if (radio_ver != 0x2050)
3990 unsupported = 1;
3991 break;
96c755a3 3992 case B43_PHYTYPE_N:
bb519bee 3993 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3994 unsupported = 1;
3995 break;
6b1c7c67 3996 case B43_PHYTYPE_LP:
9d86a2d5 3997 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 3998 unsupported = 1;
3999 break;
e4d6b795
MB		 4000 default:
4001 B43_WARN_ON(1);
4002 }
4003 if (unsupported) {
4004 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4005 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4006 radio_manuf, radio_ver, radio_rev);
4007 return -EOPNOTSUPP;
4008 }
4009 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4010 radio_manuf, radio_ver, radio_rev);
4011
4012 phy->radio_manuf = radio_manuf;
4013 phy->radio_ver = radio_ver;
4014 phy->radio_rev = radio_rev;
4015
4016 phy->analog = analog_type;
4017 phy->type = phy_type;
4018 phy->rev = phy_rev;
4019
4020 return 0;
4021}
4022
4023static void setup_struct_phy_for_init(struct b43_wldev *dev,
4024 struct b43_phy *phy)
4025{
e4d6b795 4026 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4027 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4028 /* PHY TX errors counter. */
4029 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4030
4031#if B43_DEBUG
4032 phy->phy_locked = 0;
4033 phy->radio_locked = 0;
4034#endif
e4d6b795
MB		 4035}
4036
4037static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4038{
aa6c7ae2
MB		 4039 dev->dfq_valid = 0;
4040
6a724d68
MB		 4041 /* Assume the radio is enabled. If it's not enabled, the state will
4042 * immediately get fixed on the first periodic work run. */
4043 dev->radio_hw_enable = 1;
e4d6b795
MB		 4044
4045 /* Stats */
4046 memset(&dev->stats, 0, sizeof(dev->stats));
4047
4048 setup_struct_phy_for_init(dev, &dev->phy);
4049
4050 /* IRQ related flags */
4051 dev->irq_reason = 0;
4052 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4053 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4054 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4055 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4056
4057 dev->mac_suspended = 1;
4058
4059 /* Noise calculation context */
4060 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4061}
4062
4063static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4064{
4065 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4066 u64 hf;
e4d6b795 4067
1855ba78
MB		 4068 if (!modparam_btcoex)
4069 return;
95de2841 4070 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4071 return;
4072 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4073 return;
4074
4075 hf = b43_hf_read(dev);
95de2841 4076 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4077 hf |= B43_HF_BTCOEXALT;
4078 else
4079 hf |= B43_HF_BTCOEX;
4080 b43_hf_write(dev, hf);
e4d6b795
MB		 4081}
4082
4083static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4084{
4085 if (!modparam_btcoex)
4086 return;
4087 //TODO
e4d6b795
MB		 4088}
4089
4090static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4091{
4092#ifdef CONFIG_SSB_DRIVER_PCICORE
4093 struct ssb_bus *bus = dev->dev->bus;
4094 u32 tmp;
4095
4096 if (bus->pcicore.dev &&
4097 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4098 bus->pcicore.dev->id.revision <= 5) {
4099 /* IMCFGLO timeouts workaround. */
4100 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4101 tmp &= ~SSB_IMCFGLO_REQTO;
4102 tmp &= ~SSB_IMCFGLO_SERTO;
4103 switch (bus->bustype) {
4104 case SSB_BUSTYPE_PCI:
4105 case SSB_BUSTYPE_PCMCIA:
4106 tmp |= 0x32;
4107 break;
4108 case SSB_BUSTYPE_SSB:
4109 tmp |= 0x53;
4110 break;
4111 }
4112 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4113 }
4114#endif /* CONFIG_SSB_DRIVER_PCICORE */
4115}
4116
d59f720d
MB		 4117static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4118{
4119 u16 pu_delay;
4120
4121 /* The time value is in microseconds. */
4122 if (dev->phy.type == B43_PHYTYPE_A)
4123 pu_delay = 3700;
4124 else
4125 pu_delay = 1050;
05c914fe 4126 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4127 pu_delay = 500;
4128 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4129 pu_delay = max(pu_delay, (u16)2400);
4130
4131 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4132}
4133
4134/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4135static void b43_set_pretbtt(struct b43_wldev *dev)
4136{
4137 u16 pretbtt;
4138
4139 /* The time value is in microseconds. */
05c914fe 4140 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4141 pretbtt = 2;
4142 } else {
4143 if (dev->phy.type == B43_PHYTYPE_A)
4144 pretbtt = 120;
4145 else
4146 pretbtt = 250;
4147 }
4148 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4149 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4150}
4151
e4d6b795
MB		 4152/* Shutdown a wireless core */
4153/* Locking: wl->mutex */
4154static void b43_wireless_core_exit(struct b43_wldev *dev)
4155{
1f7d87b0 4156 u32 macctl;
e4d6b795
MB		 4157
4158 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4159 if (b43_status(dev) != B43_STAT_INITIALIZED)
4160 return;
4161 b43_set_status(dev, B43_STAT_UNINIT);
4162
1f7d87b0
MB		 4163 /* Stop the microcode PSM. */
4164 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4165 macctl &= ~B43_MACCTL_PSM_RUN;
4166 macctl |= B43_MACCTL_PSM_JMP0;
4167 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4168
3506e0c4
RW		 4169 if (!dev->suspend_in_progress) {
4170 b43_leds_exit(dev);
b844eba2 4171 b43_rng_exit(dev->wl);
3506e0c4 4172 }
e4d6b795 4173 b43_dma_free(dev);
5100d5ac 4174 b43_pio_free(dev);
e4d6b795 4175 b43_chip_exit(dev);
cb24f57f 4176 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4177 if (dev->wl->current_beacon) {
4178 dev_kfree_skb_any(dev->wl->current_beacon);
4179 dev->wl->current_beacon = NULL;
4180 }
4181
e4d6b795
MB		 4182 ssb_device_disable(dev->dev, 0);
4183 ssb_bus_may_powerdown(dev->dev->bus);
4184}
4185
4186/* Initialize a wireless core */
4187static int b43_wireless_core_init(struct b43_wldev *dev)
4188{
4189 struct b43_wl *wl = dev->wl;
4190 struct ssb_bus *bus = dev->dev->bus;
4191 struct ssb_sprom *sprom = &bus->sprom;
4192 struct b43_phy *phy = &dev->phy;
4193 int err;
a259d6a4
MB		 4194 u64 hf;
4195 u32 tmp;
e4d6b795
MB		 4196
4197 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4198
4199 err = ssb_bus_powerup(bus, 0);
4200 if (err)
4201 goto out;
4202 if (!ssb_device_is_enabled(dev->dev)) {
4203 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4204 b43_wireless_core_reset(dev, tmp);
4205 }
4206
fb11137a 4207 /* Reset all data structures. */
e4d6b795 4208 setup_struct_wldev_for_init(dev);
fb11137a 4209 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4210
4211 /* Enable IRQ routing to this device. */
4212 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4213
4214 b43_imcfglo_timeouts_workaround(dev);
4215 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4216 if (phy->ops->prepare_hardware) {
4217 err = phy->ops->prepare_hardware(dev);
ef1a628d 4218 if (err)
fb11137a 4219 goto err_busdown;
ef1a628d 4220 }
e4d6b795
MB		 4221 err = b43_chip_init(dev);
4222 if (err)
fb11137a 4223 goto err_busdown;
e4d6b795
MB		 4224 b43_shm_write16(dev, B43_SHM_SHARED,
4225 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4226 hf = b43_hf_read(dev);
4227 if (phy->type == B43_PHYTYPE_G) {
4228 hf |= B43_HF_SYMW;
4229 if (phy->rev == 1)
4230 hf |= B43_HF_GDCW;
95de2841 4231 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4232 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4233 }
4234 if (phy->radio_ver == 0x2050) {
4235 if (phy->radio_rev == 6)
4236 hf |= B43_HF_4318TSSI;
4237 if (phy->radio_rev < 6)
4238 hf |= B43_HF_VCORECALC;
e4d6b795 4239 }
1cc8f476
MB		 4240 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4241 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4242#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4243 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4244 (bus->pcicore.dev->id.revision <= 10))
4245 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4246#endif
25d3ef59 4247 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4248 b43_hf_write(dev, hf);
4249
74cfdba7
MB		 4250 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4251 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4252 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4253 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4254
4255 /* Disable sending probe responses from firmware.
4256 * Setting the MaxTime to one usec will always trigger
4257 * a timeout, so we never send any probe resp.
4258 * A timeout of zero is infinite. */
4259 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4260
4261 b43_rate_memory_init(dev);
5042c507 4262 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4263
4264 /* Minimum Contention Window */
4265 if (phy->type == B43_PHYTYPE_B) {
4266 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4267 } else {
4268 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4269 }
4270 /* Maximum Contention Window */
4271 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4272
5100d5ac
MB		 4273 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4274 dev->__using_pio_transfers = 1;
4275 err = b43_pio_init(dev);
4276 } else {
4277 dev->__using_pio_transfers = 0;
4278 err = b43_dma_init(dev);
4279 }
e4d6b795
MB		 4280 if (err)
4281 goto err_chip_exit;
03b29773 4282 b43_qos_init(dev);
d59f720d 4283 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4284 b43_bluetooth_coext_enable(dev);
4285
1cc8f476 4286 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4287 b43_upload_card_macaddress(dev);
e4d6b795 4288 b43_security_init(dev);
3506e0c4
RW		 4289 if (!dev->suspend_in_progress)
4290 b43_rng_init(wl);
e4d6b795
MB		 4291
4292 b43_set_status(dev, B43_STAT_INITIALIZED);
4293
3506e0c4
RW		 4294 if (!dev->suspend_in_progress)
4295 b43_leds_init(dev);
1a8d1227 4296out:
e4d6b795
MB		 4297 return err;
4298
ef1a628d 4299err_chip_exit:
e4d6b795 4300 b43_chip_exit(dev);
ef1a628d 4301err_busdown:
e4d6b795
MB		 4302 ssb_bus_may_powerdown(bus);
4303 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4304 return err;
4305}
4306
40faacc4
MB		 4307static int b43_op_add_interface(struct ieee80211_hw *hw,
4308 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4309{
4310 struct b43_wl *wl = hw_to_b43_wl(hw);
4311 struct b43_wldev *dev;
4312 unsigned long flags;
4313 int err = -EOPNOTSUPP;
4150c572
JB		 4314
4315 /* TODO: allow WDS/AP devices to coexist */
4316
05c914fe
JB		 4317 if (conf->type != NL80211_IFTYPE_AP &&
4318 conf->type != NL80211_IFTYPE_MESH_POINT &&
4319 conf->type != NL80211_IFTYPE_STATION &&
4320 conf->type != NL80211_IFTYPE_WDS &&
4321 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4322 return -EOPNOTSUPP;
e4d6b795
MB		 4323
4324 mutex_lock(&wl->mutex);
4150c572 4325 if (wl->operating)
e4d6b795
MB		 4326 goto out_mutex_unlock;
4327
4328 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4329
4330 dev = wl->current_dev;
4150c572 4331 wl->operating = 1;
32bfd35d 4332 wl->vif = conf->vif;
4150c572
JB		 4333 wl->if_type = conf->type;
4334 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4335
4336 spin_lock_irqsave(&wl->irq_lock, flags);
4337 b43_adjust_opmode(dev);
d59f720d
MB		 4338 b43_set_pretbtt(dev);
4339 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4340 b43_upload_card_macaddress(dev);
4341 spin_unlock_irqrestore(&wl->irq_lock, flags);
4342
4343 err = 0;
4344 out_mutex_unlock:
4345 mutex_unlock(&wl->mutex);
4346
4347 return err;
4348}
4349
40faacc4
MB		 4350static void b43_op_remove_interface(struct ieee80211_hw *hw,
4351 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4352{
4353 struct b43_wl *wl = hw_to_b43_wl(hw);
4354 struct b43_wldev *dev = wl->current_dev;
4355 unsigned long flags;
4356
4357 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4358
4359 mutex_lock(&wl->mutex);
4360
4361 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4362 B43_WARN_ON(wl->vif != conf->vif);
4363 wl->vif = NULL;
4150c572
JB		 4364
4365 wl->operating = 0;
4366
4367 spin_lock_irqsave(&wl->irq_lock, flags);
4368 b43_adjust_opmode(dev);
4369 memset(wl->mac_addr, 0, ETH_ALEN);
4370 b43_upload_card_macaddress(dev);
4371 spin_unlock_irqrestore(&wl->irq_lock, flags);
4372
4373 mutex_unlock(&wl->mutex);
4374}
4375
40faacc4 4376static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4377{
4378 struct b43_wl *wl = hw_to_b43_wl(hw);
4379 struct b43_wldev *dev = wl->current_dev;
4380 int did_init = 0;
923403b8 4381 int err = 0;
4150c572 4382
7be1bb6b
MB		 4383 /* Kill all old instance specific information to make sure
4384 * the card won't use it in the short timeframe between start
4385 * and mac80211 reconfiguring it. */
4386 memset(wl->bssid, 0, ETH_ALEN);
4387 memset(wl->mac_addr, 0, ETH_ALEN);
4388 wl->filter_flags = 0;
4389 wl->radiotap_enabled = 0;
e6f5b934 4390 b43_qos_clear(wl);
6b4bec01
MB		 4391 wl->beacon0_uploaded = 0;
4392 wl->beacon1_uploaded = 0;
4393 wl->beacon_templates_virgin = 1;
fd4973c5 4394 wl->radio_enabled = 1;
7be1bb6b 4395
4150c572
JB		 4396 mutex_lock(&wl->mutex);
4397
e4d6b795
MB		 4398 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4399 err = b43_wireless_core_init(dev);
f41f3f37 4400 if (err)
e4d6b795
MB		 4401 goto out_mutex_unlock;
4402 did_init = 1;
4403 }
4150c572 4404
e4d6b795
MB		 4405 if (b43_status(dev) < B43_STAT_STARTED) {
4406 err = b43_wireless_core_start(dev);
4407 if (err) {
4408 if (did_init)
4409 b43_wireless_core_exit(dev);
4410 goto out_mutex_unlock;
4411 }
4412 }
4413
f41f3f37
JB		 4414 /* XXX: only do if device doesn't support rfkill irq */
4415 wiphy_rfkill_start_polling(hw->wiphy);
4416
4150c572 4417 out_mutex_unlock:
e4d6b795
MB		 4418 mutex_unlock(&wl->mutex);
4419
4420 return err;
4421}
4422
40faacc4 4423static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4424{
4425 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4426 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4427
a82d9922 4428 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4429
e4d6b795 4430 mutex_lock(&wl->mutex);
4150c572
JB		 4431 if (b43_status(dev) >= B43_STAT_STARTED)
4432 b43_wireless_core_stop(dev);
4433 b43_wireless_core_exit(dev);
fd4973c5 4434 wl->radio_enabled = 0;
e4d6b795 4435 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4436
4437 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4438}
4439
17741cdc
JB		 4440static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4441 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4442{
4443 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4444 unsigned long flags;
e66fee6a 4445
d4df6f1a 4446 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4447 b43_update_templates(wl);
d4df6f1a 4448 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4449
4450 return 0;
4451}
4452
38968d09
JB		 4453static void b43_op_sta_notify(struct ieee80211_hw *hw,
4454 struct ieee80211_vif *vif,
4455 enum sta_notify_cmd notify_cmd,
17741cdc 4456 struct ieee80211_sta *sta)
38968d09
JB		 4457{
4458 struct b43_wl *wl = hw_to_b43_wl(hw);
4459
4460 B43_WARN_ON(!vif || wl->vif != vif);
4461}
4462
25d3ef59
MB		 4463static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4464{
4465 struct b43_wl *wl = hw_to_b43_wl(hw);
4466 struct b43_wldev *dev;
4467
4468 mutex_lock(&wl->mutex);
4469 dev = wl->current_dev;
4470 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4471 /* Disable CFP update during scan on other channels. */
4472 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4473 }
4474 mutex_unlock(&wl->mutex);
4475}
4476
4477static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4478{
4479 struct b43_wl *wl = hw_to_b43_wl(hw);
4480 struct b43_wldev *dev;
4481
4482 mutex_lock(&wl->mutex);
4483 dev = wl->current_dev;
4484 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4485 /* Re-enable CFP update. */
4486 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4487 }
4488 mutex_unlock(&wl->mutex);
4489}
4490
e4d6b795 4491static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4492 .tx = b43_op_tx,
4493 .conf_tx = b43_op_conf_tx,
4494 .add_interface = b43_op_add_interface,
4495 .remove_interface = b43_op_remove_interface,
4496 .config = b43_op_config,
c7ab5ef9 4497 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4498 .configure_filter = b43_op_configure_filter,
4499 .set_key = b43_op_set_key,
035d0243 4500 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4501 .get_stats = b43_op_get_stats,
4502 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4503 .get_tsf = b43_op_get_tsf,
4504 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4505 .start = b43_op_start,
4506 .stop = b43_op_stop,
e66fee6a 4507 .set_tim = b43_op_beacon_set_tim,
38968d09 4508 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4509 .sw_scan_start = b43_op_sw_scan_start_notifier,
4510 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4511 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4512};
4513
4514/* Hard-reset the chip. Do not call this directly.
4515 * Use b43_controller_restart()
4516 */
4517static void b43_chip_reset(struct work_struct *work)
4518{
4519 struct b43_wldev *dev =
4520 container_of(work, struct b43_wldev, restart_work);
4521 struct b43_wl *wl = dev->wl;
4522 int err = 0;
4523 int prev_status;
4524
4525 mutex_lock(&wl->mutex);
4526
4527 prev_status = b43_status(dev);
4528 /* Bring the device down... */
4529 if (prev_status >= B43_STAT_STARTED)
4530 b43_wireless_core_stop(dev);
4531 if (prev_status >= B43_STAT_INITIALIZED)
4532 b43_wireless_core_exit(dev);
4533
4534 /* ...and up again. */
4535 if (prev_status >= B43_STAT_INITIALIZED) {
4536 err = b43_wireless_core_init(dev);
4537 if (err)
4538 goto out;
4539 }
4540 if (prev_status >= B43_STAT_STARTED) {
4541 err = b43_wireless_core_start(dev);
4542 if (err) {
4543 b43_wireless_core_exit(dev);
4544 goto out;
4545 }
4546 }
3bf0a32e
MB		 4547out:
4548 if (err)
4549 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4550 mutex_unlock(&wl->mutex);
4551 if (err)
4552 b43err(wl, "Controller restart FAILED\n");
4553 else
4554 b43info(wl, "Controller restarted\n");
4555}
4556
bb1eeff1 4557static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4558 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4559{
4560 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4561
bb1eeff1
MB		 4562 if (have_2ghz_phy)
4563 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4564 if (dev->phy.type == B43_PHYTYPE_N) {
4565 if (have_5ghz_phy)
4566 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4567 } else {
4568 if (have_5ghz_phy)
4569 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4570 }
96c755a3 4571
bb1eeff1
MB		 4572 dev->phy.supports_2ghz = have_2ghz_phy;
4573 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4574
4575 return 0;
4576}
4577
4578static void b43_wireless_core_detach(struct b43_wldev *dev)
4579{
4580 /* We release firmware that late to not be required to re-request
4581 * is all the time when we reinit the core. */
4582 b43_release_firmware(dev);
fb11137a 4583 b43_phy_free(dev);
e4d6b795
MB		 4584}
4585
4586static int b43_wireless_core_attach(struct b43_wldev *dev)
4587{
4588 struct b43_wl *wl = dev->wl;
4589 struct ssb_bus *bus = dev->dev->bus;
4590 struct pci_dev *pdev = bus->host_pci;
4591 int err;
96c755a3 4592 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4593 u32 tmp;
4594
4595 /* Do NOT do any device initialization here.
4596 * Do it in wireless_core_init() instead.
4597 * This function is for gathering basic information about the HW, only.
4598 * Also some structs may be set up here. But most likely you want to have
4599 * that in core_init(), too.
4600 */
4601
4602 err = ssb_bus_powerup(bus, 0);
4603 if (err) {
4604 b43err(wl, "Bus powerup failed\n");
4605 goto out;
4606 }
4607 /* Get the PHY type. */
4608 if (dev->dev->id.revision >= 5) {
4609 u32 tmshigh;
4610
4611 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4612 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4613 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4614 } else
96c755a3 4615 B43_WARN_ON(1);
e4d6b795 4616
96c755a3 4617 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4618 dev->phy.radio_on = 1;
e4d6b795
MB		 4619 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4620 b43_wireless_core_reset(dev, tmp);
4621
4622 err = b43_phy_versioning(dev);
4623 if (err)
21954c36 4624 goto err_powerdown;
e4d6b795
MB		 4625 /* Check if this device supports multiband. */
4626 if (!pdev ||
4627 (pdev->device != 0x4312 &&
4628 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4629 /* No multiband support. */
96c755a3
MB		 4630 have_2ghz_phy = 0;
4631 have_5ghz_phy = 0;
e4d6b795
MB		 4632 switch (dev->phy.type) {
4633 case B43_PHYTYPE_A:
96c755a3 4634 have_5ghz_phy = 1;
e4d6b795 4635 break;
9d86a2d5 4636 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4637#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4638 have_5ghz_phy = 1;
86b2892a 4639#endif
e4d6b795 4640 case B43_PHYTYPE_G:
96c755a3
MB		 4641 case B43_PHYTYPE_N:
4642 have_2ghz_phy = 1;
e4d6b795
MB		 4643 break;
4644 default:
4645 B43_WARN_ON(1);
4646 }
4647 }
96c755a3
MB		 4648 if (dev->phy.type == B43_PHYTYPE_A) {
4649 /* FIXME */
4650 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4651 err = -EOPNOTSUPP;
4652 goto err_powerdown;
4653 }
2e35af14
MB		 4654 if (1 /* disable A-PHY */) {
4655 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4656 if (dev->phy.type != B43_PHYTYPE_N &&
4657 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4658 have_2ghz_phy = 1;
4659 have_5ghz_phy = 0;
4660 }
4661 }
4662
fb11137a
MB		 4663 err = b43_phy_allocate(dev);
4664 if (err)
4665 goto err_powerdown;
4666
96c755a3 4667 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4668 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4669 b43_wireless_core_reset(dev, tmp);
4670
4671 err = b43_validate_chipaccess(dev);
4672 if (err)
fb11137a 4673 goto err_phy_free;
bb1eeff1 4674 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4675 if (err)
fb11137a 4676 goto err_phy_free;
e4d6b795
MB		 4677
4678 /* Now set some default "current_dev" */
4679 if (!wl->current_dev)
4680 wl->current_dev = dev;
4681 INIT_WORK(&dev->restart_work, b43_chip_reset);
4682
cb24f57f 4683 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4684 ssb_device_disable(dev->dev, 0);
4685 ssb_bus_may_powerdown(bus);
4686
4687out:
4688 return err;
4689
fb11137a
MB		 4690err_phy_free:
4691 b43_phy_free(dev);
e4d6b795
MB		 4692err_powerdown:
4693 ssb_bus_may_powerdown(bus);
4694 return err;
4695}
4696
4697static void b43_one_core_detach(struct ssb_device *dev)
4698{
4699 struct b43_wldev *wldev;
4700 struct b43_wl *wl;
4701
3bf0a32e
MB		 4702 /* Do not cancel ieee80211-workqueue based work here.
4703 * See comment in b43_remove(). */
4704
e4d6b795
MB		 4705 wldev = ssb_get_drvdata(dev);
4706 wl = wldev->wl;
e4d6b795
MB		 4707 b43_debugfs_remove_device(wldev);
4708 b43_wireless_core_detach(wldev);
4709 list_del(&wldev->list);
4710 wl->nr_devs--;
4711 ssb_set_drvdata(dev, NULL);
4712 kfree(wldev);
4713}
4714
4715static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4716{
4717 struct b43_wldev *wldev;
4718 struct pci_dev *pdev;
4719 int err = -ENOMEM;
4720
4721 if (!list_empty(&wl->devlist)) {
4722 /* We are not the first core on this chip. */
4723 pdev = dev->bus->host_pci;
4724 /* Only special chips support more than one wireless
4725 * core, although some of the other chips have more than
4726 * one wireless core as well. Check for this and
4727 * bail out early.
4728 */
4729 if (!pdev ||
4730 ((pdev->device != 0x4321) &&
4731 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4732 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4733 return -ENODEV;
4734 }
4735 }
4736
4737 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4738 if (!wldev)
4739 goto out;
4740
4741 wldev->dev = dev;
4742 wldev->wl = wl;
4743 b43_set_status(wldev, B43_STAT_UNINIT);
4744 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4745 tasklet_init(&wldev->isr_tasklet,
4746 (void (*)(unsigned long))b43_interrupt_tasklet,
4747 (unsigned long)wldev);
e4d6b795
MB		 4748 INIT_LIST_HEAD(&wldev->list);
4749
4750 err = b43_wireless_core_attach(wldev);
4751 if (err)
4752 goto err_kfree_wldev;
4753
4754 list_add(&wldev->list, &wl->devlist);
4755 wl->nr_devs++;
4756 ssb_set_drvdata(dev, wldev);
4757 b43_debugfs_add_device(wldev);
4758
4759 out:
4760 return err;
4761
4762 err_kfree_wldev:
4763 kfree(wldev);
4764 return err;
4765}
4766
9fc38458
MB		 4767#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4768 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4769 (pdev->device == _device) && \
4770 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4771 (pdev->subsystem_device == _subdevice) )
4772
e4d6b795
MB		 4773static void b43_sprom_fixup(struct ssb_bus *bus)
4774{
1855ba78
MB		 4775 struct pci_dev *pdev;
4776
e4d6b795
MB		 4777 /* boardflags workarounds */
4778 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4779 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4780 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4781 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4782 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4783 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4784 if (bus->bustype == SSB_BUSTYPE_PCI) {
4785 pdev = bus->host_pci;
9fc38458 4786 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4787 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4788 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4789 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4790 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4791 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4792 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4793 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4794 }
e4d6b795
MB		 4795}
4796
4797static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4798{
4799 struct ieee80211_hw *hw = wl->hw;
4800
4801 ssb_set_devtypedata(dev, NULL);
4802 ieee80211_free_hw(hw);
4803}
4804
4805static int b43_wireless_init(struct ssb_device *dev)
4806{
4807 struct ssb_sprom *sprom = &dev->bus->sprom;
4808 struct ieee80211_hw *hw;
4809 struct b43_wl *wl;
4810 int err = -ENOMEM;
4811
4812 b43_sprom_fixup(dev->bus);
4813
4814 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4815 if (!hw) {
4816 b43err(NULL, "Could not allocate ieee80211 device\n");
4817 goto out;
4818 }
403a3a13 4819 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4820
4821 /* fill hw info */
605a0bd6 4822 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4823 IEEE80211_HW_SIGNAL_DBM |
4824 IEEE80211_HW_NOISE_DBM;
4825
f59ac048
LR		 4826 hw->wiphy->interface_modes =
4827 BIT(NL80211_IFTYPE_AP) |
4828 BIT(NL80211_IFTYPE_MESH_POINT) |
4829 BIT(NL80211_IFTYPE_STATION) |
4830 BIT(NL80211_IFTYPE_WDS) |
4831 BIT(NL80211_IFTYPE_ADHOC);
4832
403a3a13
MB		 4833 hw->queues = modparam_qos ? 4 : 1;
4834 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4835 hw->max_rates = 2;
e4d6b795 4836 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4837 if (is_valid_ether_addr(sprom->et1mac))
4838 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4839 else
95de2841 4840 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4841
403a3a13 4842 /* Initialize struct b43_wl */
e4d6b795
MB		 4843 wl->hw = hw;
4844 spin_lock_init(&wl->irq_lock);
21a75d77 4845 rwlock_init(&wl->tx_lock);
e4d6b795 4846 spin_lock_init(&wl->leds_lock);
280d0e16 4847 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4848 mutex_init(&wl->mutex);
4849 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4850 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4851 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4852
4853 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4854 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4855 dev->bus->chip_id, dev->id.revision);
e4d6b795 4856 err = 0;
060210f9 4857out:
e4d6b795
MB		 4858 return err;
4859}
4860
4861static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4862{
4863 struct b43_wl *wl;
4864 int err;
4865 int first = 0;
4866
4867 wl = ssb_get_devtypedata(dev);
4868 if (!wl) {
4869 /* Probing the first core. Must setup common struct b43_wl */
4870 first = 1;
4871 err = b43_wireless_init(dev);
4872 if (err)
4873 goto out;
4874 wl = ssb_get_devtypedata(dev);
4875 B43_WARN_ON(!wl);
4876 }
4877 err = b43_one_core_attach(dev, wl);
4878 if (err)
4879 goto err_wireless_exit;
4880
4881 if (first) {
4882 err = ieee80211_register_hw(wl->hw);
4883 if (err)
4884 goto err_one_core_detach;
4885 }
4886
4887 out:
4888 return err;
4889
4890 err_one_core_detach:
4891 b43_one_core_detach(dev);
4892 err_wireless_exit:
4893 if (first)
4894 b43_wireless_exit(dev, wl);
4895 return err;
4896}
4897
4898static void b43_remove(struct ssb_device *dev)
4899{
4900 struct b43_wl *wl = ssb_get_devtypedata(dev);
4901 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4902
3bf0a32e
MB		 4903 /* We must cancel any work here before unregistering from ieee80211,
4904 * as the ieee80211 unreg will destroy the workqueue. */
4905 cancel_work_sync(&wldev->restart_work);
4906
e4d6b795 4907 B43_WARN_ON(!wl);
403a3a13
MB		 4908 if (wl->current_dev == wldev) {
4909 /* Restore the queues count before unregistering, because firmware detect
4910 * might have modified it. Restoring is important, so the networking
4911 * stack can properly free resources. */
4912 wl->hw->queues = wl->mac80211_initially_registered_queues;
e4d6b795 4913 ieee80211_unregister_hw(wl->hw);
403a3a13 4914 }
e4d6b795
MB		 4915
4916 b43_one_core_detach(dev);
4917
4918 if (list_empty(&wl->devlist)) {
4919 /* Last core on the chip unregistered.
4920 * We can destroy common struct b43_wl.
4921 */
4922 b43_wireless_exit(dev, wl);
4923 }
4924}
4925
4926/* Perform a hardware reset. This can be called from any context. */
4927void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4928{
4929 /* Must avoid requeueing, if we are in shutdown. */
4930 if (b43_status(dev) < B43_STAT_INITIALIZED)
4931 return;
4932 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 4933 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 4934}
4935
4936#ifdef CONFIG_PM
4937
4938static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4939{
4940 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4941 struct b43_wl *wl = wldev->wl;
4942
4943 b43dbg(wl, "Suspending...\n");
4944
4945 mutex_lock(&wl->mutex);
3506e0c4 4946 wldev->suspend_in_progress = true;
e4d6b795
MB		 4947 wldev->suspend_init_status = b43_status(wldev);
4948 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4949 b43_wireless_core_stop(wldev);
4950 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4951 b43_wireless_core_exit(wldev);
4952 mutex_unlock(&wl->mutex);
4953
4954 b43dbg(wl, "Device suspended.\n");
4955
4956 return 0;
4957}
4958
4959static int b43_resume(struct ssb_device *dev)
4960{
4961 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4962 struct b43_wl *wl = wldev->wl;
4963 int err = 0;
4964
4965 b43dbg(wl, "Resuming...\n");
4966
4967 mutex_lock(&wl->mutex);
4968 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4969 err = b43_wireless_core_init(wldev);
4970 if (err) {
4971 b43err(wl, "Resume failed at core init\n");
4972 goto out;
4973 }
4974 }
4975 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4976 err = b43_wireless_core_start(wldev);
4977 if (err) {
3506e0c4 4978 b43_leds_exit(wldev);
b844eba2 4979 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4980 b43_wireless_core_exit(wldev);
4981 b43err(wl, "Resume failed at core start\n");
4982 goto out;
4983 }
4984 }
e4d6b795 4985 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4986 out:
4987 wldev->suspend_in_progress = false;
4988 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4989 return err;
4990}
4991
4992#else /* CONFIG_PM */
4993# define b43_suspend NULL
4994# define b43_resume NULL
4995#endif /* CONFIG_PM */
4996
4997static struct ssb_driver b43_ssb_driver = {
4998 .name = KBUILD_MODNAME,
4999 .id_table = b43_ssb_tbl,
5000 .probe = b43_probe,
5001 .remove = b43_remove,
5002 .suspend = b43_suspend,
5003 .resume = b43_resume,
5004};
5005
26bc783f
MB		 5006static void b43_print_driverinfo(void)
5007{
5008 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
f41f3f37 5009 *feat_leds = "";
26bc783f
MB		 5010
5011#ifdef CONFIG_B43_PCI_AUTOSELECT
5012 feat_pci = "P";
5013#endif
5014#ifdef CONFIG_B43_PCMCIA
5015 feat_pcmcia = "M";
5016#endif
5017#ifdef CONFIG_B43_NPHY
5018 feat_nphy = "N";
5019#endif
5020#ifdef CONFIG_B43_LEDS
5021 feat_leds = "L";
26bc783f
MB		 5022#endif
5023 printk(KERN_INFO "Broadcom 43xx driver loaded "
f41f3f37 5024 "[ Features: %s%s%s%s, Firmware-ID: "
26bc783f
MB		 5025 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5026 feat_pci, feat_pcmcia, feat_nphy,
f41f3f37 5027 feat_leds);
26bc783f
MB		 5028}
5029
e4d6b795
MB		 5030static int __init b43_init(void)
5031{
5032 int err;
5033
5034 b43_debugfs_init();
5035 err = b43_pcmcia_init();
5036 if (err)
5037 goto err_dfs_exit;
5038 err = ssb_driver_register(&b43_ssb_driver);
5039 if (err)
5040 goto err_pcmcia_exit;
26bc783f 5041 b43_print_driverinfo();
e4d6b795
MB		 5042
5043 return err;
5044
5045err_pcmcia_exit:
5046 b43_pcmcia_exit();
5047err_dfs_exit:
5048 b43_debugfs_exit();
5049 return err;
5050}
5051
5052static void __exit b43_exit(void)
5053{
5054 ssb_driver_unregister(&b43_ssb_driver);
5055 b43_pcmcia_exit();
5056 b43_debugfs_exit();
5057}
5058
5059module_init(b43_init)
5060module_exit(b43_exit)
Linux kernel - Deliverables
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