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b43: tell ucode the phy type and version
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
8960400e
RM		 116static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119
3c65ab62
RM		 120#ifdef CONFIG_B43_BCMA
121static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
15be8e89 125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
3c65ab62 126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
15be8e89
RM		 127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
3c65ab62
RM		 130 BCMA_CORETABLE_END
131};
132MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
133#endif
134
aec7ffdf 135#ifdef CONFIG_B43_SSB
e4d6b795
MB		 136static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 147 SSB_DEVTABLE_END
148};
e4d6b795 149MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 150#endif
e4d6b795
MB		 151
152/* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 157 { \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
160 .flags = (_flags), \
e4d6b795 161 }
8318d78a
JB		 162
163/*
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
166 */
e4d6b795 167static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 180};
181
182#define b43_a_ratetable (__b43_ratetable + 4)
183#define b43_a_ratetable_size 8
184#define b43_b_ratetable (__b43_ratetable + 0)
185#define b43_b_ratetable_size 4
186#define b43_g_ratetable (__b43_ratetable + 0)
187#define b43_g_ratetable_size 12
188
e9cdcb74 189#define CHAN2G(_channel, _freq, _flags) { \
bb1eeff1
MB		 190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
193 .flags = (_flags), \
194 .max_antenna_gain = 0, \
195 .max_power = 30, \
196}
96c755a3 197static struct ieee80211_channel b43_2ghz_chantable[] = {
e9cdcb74
RM		 198 CHAN2G(1, 2412, 0),
199 CHAN2G(2, 2417, 0),
200 CHAN2G(3, 2422, 0),
201 CHAN2G(4, 2427, 0),
202 CHAN2G(5, 2432, 0),
203 CHAN2G(6, 2437, 0),
204 CHAN2G(7, 2442, 0),
205 CHAN2G(8, 2447, 0),
206 CHAN2G(9, 2452, 0),
207 CHAN2G(10, 2457, 0),
208 CHAN2G(11, 2462, 0),
209 CHAN2G(12, 2467, 0),
210 CHAN2G(13, 2472, 0),
211 CHAN2G(14, 2484, 0),
bb1eeff1 212};
3695b932
RM		 213
214/* No support for the last 3 channels (12, 13, 14) */
215#define b43_2ghz_chantable_limited_size 11
e9cdcb74 216#undef CHAN2G
bb1eeff1 217
91211739
RM		 218#define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
222 .flags = (_flags), \
223 .max_antenna_gain = 0, \
224 .max_power = 30, \
225}
bb1eeff1
MB		 226#define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
230 .flags = (_flags), \
231 .max_antenna_gain = 0, \
232 .max_power = 30, \
233}
234static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
91211739
RM		 235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
246 CHAN4G(228, 0),
bb1eeff1
MB		 247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
91211739 290 CHAN5G(182, 0),
e4d6b795
MB		 291};
292
b453fda6
RM		 293static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
294 CHAN5G(36, 0), CHAN5G(40, 0),
295 CHAN5G(44, 0), CHAN5G(48, 0),
296 CHAN5G(149, 0), CHAN5G(153, 0),
297 CHAN5G(157, 0), CHAN5G(161, 0),
298 CHAN5G(165, 0),
299};
300
bb1eeff1
MB		 301static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
302 CHAN5G(34, 0), CHAN5G(36, 0),
303 CHAN5G(38, 0), CHAN5G(40, 0),
304 CHAN5G(42, 0), CHAN5G(44, 0),
305 CHAN5G(46, 0), CHAN5G(48, 0),
306 CHAN5G(52, 0), CHAN5G(56, 0),
307 CHAN5G(60, 0), CHAN5G(64, 0),
308 CHAN5G(100, 0), CHAN5G(104, 0),
309 CHAN5G(108, 0), CHAN5G(112, 0),
310 CHAN5G(116, 0), CHAN5G(120, 0),
311 CHAN5G(124, 0), CHAN5G(128, 0),
312 CHAN5G(132, 0), CHAN5G(136, 0),
313 CHAN5G(140, 0), CHAN5G(149, 0),
314 CHAN5G(153, 0), CHAN5G(157, 0),
315 CHAN5G(161, 0), CHAN5G(165, 0),
316 CHAN5G(184, 0), CHAN5G(188, 0),
317 CHAN5G(192, 0), CHAN5G(196, 0),
318 CHAN5G(200, 0), CHAN5G(204, 0),
319 CHAN5G(208, 0), CHAN5G(212, 0),
320 CHAN5G(216, 0),
321};
91211739 322#undef CHAN4G
bb1eeff1
MB		 323#undef CHAN5G
324
325static struct ieee80211_supported_band b43_band_5GHz_nphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_nphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
e4d6b795 331};
8318d78a 332
b453fda6
RM		 333static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
334 .band = IEEE80211_BAND_5GHZ,
335 .channels = b43_5ghz_nphy_chantable_limited,
336 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
337 .bitrates = b43_a_ratetable,
338 .n_bitrates = b43_a_ratetable_size,
339};
340
bb1eeff1
MB		 341static struct ieee80211_supported_band b43_band_5GHz_aphy = {
342 .band = IEEE80211_BAND_5GHZ,
343 .channels = b43_5ghz_aphy_chantable,
344 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
345 .bitrates = b43_a_ratetable,
346 .n_bitrates = b43_a_ratetable_size,
8318d78a 347};
e4d6b795 348
8318d78a 349static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 350 .band = IEEE80211_BAND_2GHZ,
351 .channels = b43_2ghz_chantable,
352 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
353 .bitrates = b43_g_ratetable,
354 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 355};
356
3695b932
RM		 357static struct ieee80211_supported_band b43_band_2ghz_limited = {
358 .band = IEEE80211_BAND_2GHZ,
359 .channels = b43_2ghz_chantable,
360 .n_channels = b43_2ghz_chantable_limited_size,
361 .bitrates = b43_g_ratetable,
362 .n_bitrates = b43_g_ratetable_size,
363};
364
e4d6b795
MB		 365static void b43_wireless_core_exit(struct b43_wldev *dev);
366static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 367static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 368static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 369static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
370 struct ieee80211_vif *vif,
371 struct ieee80211_bss_conf *conf,
372 u32 changed);
e4d6b795
MB		 373
374static int b43_ratelimit(struct b43_wl *wl)
375{
376 if (!wl || !wl->current_dev)
377 return 1;
378 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
379 return 1;
380 /* We are up and running.
381 * Ratelimit the messages to avoid DoS over the net. */
382 return net_ratelimit();
383}
384
385void b43info(struct b43_wl *wl, const char *fmt, ...)
386{
5b736d42 387 struct va_format vaf;
e4d6b795
MB		 388 va_list args;
389
060210f9
MB		 390 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
391 return;
e4d6b795
MB		 392 if (!b43_ratelimit(wl))
393 return;
5b736d42 394
e4d6b795 395 va_start(args, fmt);
5b736d42
JP		 396
397 vaf.fmt = fmt;
398 vaf.va = &args;
399
400 printk(KERN_INFO "b43-%s: %pV",
401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
402
e4d6b795
MB		 403 va_end(args);
404}
405
406void b43err(struct b43_wl *wl, const char *fmt, ...)
407{
5b736d42 408 struct va_format vaf;
e4d6b795
MB		 409 va_list args;
410
060210f9
MB		 411 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
412 return;
e4d6b795
MB		 413 if (!b43_ratelimit(wl))
414 return;
5b736d42 415
e4d6b795 416 va_start(args, fmt);
5b736d42
JP		 417
418 vaf.fmt = fmt;
419 vaf.va = &args;
420
421 printk(KERN_ERR "b43-%s ERROR: %pV",
422 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
423
e4d6b795
MB		 424 va_end(args);
425}
426
427void b43warn(struct b43_wl *wl, const char *fmt, ...)
428{
5b736d42 429 struct va_format vaf;
e4d6b795
MB		 430 va_list args;
431
060210f9
MB		 432 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
433 return;
e4d6b795
MB		 434 if (!b43_ratelimit(wl))
435 return;
5b736d42 436
e4d6b795 437 va_start(args, fmt);
5b736d42
JP		 438
439 vaf.fmt = fmt;
440 vaf.va = &args;
441
442 printk(KERN_WARNING "b43-%s warning: %pV",
443 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
444
e4d6b795
MB		 445 va_end(args);
446}
447
e4d6b795
MB		 448void b43dbg(struct b43_wl *wl, const char *fmt, ...)
449{
5b736d42 450 struct va_format vaf;
e4d6b795
MB		 451 va_list args;
452
060210f9
MB		 453 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
454 return;
5b736d42 455
e4d6b795 456 va_start(args, fmt);
5b736d42
JP		 457
458 vaf.fmt = fmt;
459 vaf.va = &args;
460
461 printk(KERN_DEBUG "b43-%s debug: %pV",
462 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
463
e4d6b795
MB		 464 va_end(args);
465}
e4d6b795
MB		 466
467static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
468{
469 u32 macctl;
470
471 B43_WARN_ON(offset % 4 != 0);
472
473 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 if (macctl & B43_MACCTL_BE)
475 val = swab32(val);
476
477 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
478 mmiowb();
479 b43_write32(dev, B43_MMIO_RAM_DATA, val);
480}
481
280d0e16
MB		 482static inline void b43_shm_control_word(struct b43_wldev *dev,
483 u16 routing, u16 offset)
e4d6b795
MB		 484{
485 u32 control;
486
487 /* "offset" is the WORD offset. */
e4d6b795
MB		 488 control = routing;
489 control <<= 16;
490 control |= offset;
491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
492}
493
69eddc8a 494u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 495{
496 u32 ret;
497
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 505 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 506
280d0e16 507 goto out;
e4d6b795
MB		 508 }
509 offset >>= 2;
510 }
511 b43_shm_control_word(dev, routing, offset);
512 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 513out:
e4d6b795
MB		 514 return ret;
515}
516
69eddc8a 517u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 518{
519 u16 ret;
520
e4d6b795
MB		 521 if (routing == B43_SHM_SHARED) {
522 B43_WARN_ON(offset & 0x0001);
523 if (offset & 0x0003) {
524 /* Unaligned access */
525 b43_shm_control_word(dev, routing, offset >> 2);
526 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
527
280d0e16 528 goto out;
e4d6b795
MB		 529 }
530 offset >>= 2;
531 }
532 b43_shm_control_word(dev, routing, offset);
533 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 534out:
e4d6b795
MB		 535 return ret;
536}
537
69eddc8a 538void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 539{
e4d6b795
MB		 540 if (routing == B43_SHM_SHARED) {
541 B43_WARN_ON(offset & 0x0001);
542 if (offset & 0x0003) {
543 /* Unaligned access */
544 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 545 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 546 value & 0xFFFF);
e4d6b795 547 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 548 b43_write16(dev, B43_MMIO_SHM_DATA,
549 (value >> 16) & 0xFFFF);
6bbc321a 550 return;
e4d6b795
MB		 551 }
552 offset >>= 2;
553 }
554 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 555 b43_write32(dev, B43_MMIO_SHM_DATA, value);
556}
557
69eddc8a 558void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 559{
e4d6b795
MB		 560 if (routing == B43_SHM_SHARED) {
561 B43_WARN_ON(offset & 0x0001);
562 if (offset & 0x0003) {
563 /* Unaligned access */
564 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 565 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 566 return;
e4d6b795
MB		 567 }
568 offset >>= 2;
569 }
570 b43_shm_control_word(dev, routing, offset);
e4d6b795 571 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 572}
573
e4d6b795 574/* Read HostFlags */
99da185a 575u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 576{
35f0d354 577 u64 ret;
e4d6b795 578
6e6a2cd5 579 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
e4d6b795 580 ret <<= 16;
6e6a2cd5 581 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
35f0d354 582 ret <<= 16;
6e6a2cd5 583 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
e4d6b795
MB		 584
585 return ret;
586}
587
588/* Write HostFlags */
35f0d354 589void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 590{
35f0d354
MB		 591 u16 lo, mi, hi;
592
593 lo = (value & 0x00000000FFFFULL);
594 mi = (value & 0x0000FFFF0000ULL) >> 16;
595 hi = (value & 0xFFFF00000000ULL) >> 32;
6e6a2cd5
RM		 596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
e4d6b795
MB		 599}
600
403a3a13
MB		 601/* Read the firmware capabilities bitmask (Opensource firmware only) */
602static u16 b43_fwcapa_read(struct b43_wldev *dev)
603{
604 B43_WARN_ON(!dev->fw.opensource);
605 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
606}
607
3ebbbb56 608void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 609{
3ebbbb56
MB		 610 u32 low, high;
611
21d889d4 612 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 613
614 /* The hardware guarantees us an atomic read, if we
615 * read the low register first. */
616 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
617 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
618
619 *tsf = high;
620 *tsf <<= 32;
621 *tsf |= low;
e4d6b795
MB		 622}
623
624static void b43_time_lock(struct b43_wldev *dev)
625{
5056635c 626 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 627 /* Commit the write */
628 b43_read32(dev, B43_MMIO_MACCTL);
629}
630
631static void b43_time_unlock(struct b43_wldev *dev)
632{
5056635c 633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 634 /* Commit the write */
635 b43_read32(dev, B43_MMIO_MACCTL);
636}
637
638static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
639{
3ebbbb56
MB		 640 u32 low, high;
641
21d889d4 642 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 643
644 low = tsf;
645 high = (tsf >> 32);
646 /* The hardware guarantees us an atomic write, if we
647 * write the low register first. */
648 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
649 mmiowb();
650 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
651 mmiowb();
e4d6b795
MB		 652}
653
654void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
655{
656 b43_time_lock(dev);
657 b43_tsf_write_locked(dev, tsf);
658 b43_time_unlock(dev);
659}
660
661static
99da185a 662void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 663{
664 static const u8 zero_addr[ETH_ALEN] = { 0 };
665 u16 data;
666
667 if (!mac)
668 mac = zero_addr;
669
670 offset |= 0x0020;
671 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
672
673 data = mac[0];
674 data |= mac[1] << 8;
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
676 data = mac[2];
677 data |= mac[3] << 8;
678 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
679 data = mac[4];
680 data |= mac[5] << 8;
681 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
682}
683
684static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
685{
686 const u8 *mac;
687 const u8 *bssid;
688 u8 mac_bssid[ETH_ALEN * 2];
689 int i;
690 u32 tmp;
691
692 bssid = dev->wl->bssid;
693 mac = dev->wl->mac_addr;
694
695 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
696
697 memcpy(mac_bssid, mac, ETH_ALEN);
698 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
699
700 /* Write our MAC address and BSSID to template ram */
701 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
702 tmp = (u32) (mac_bssid[i + 0]);
703 tmp |= (u32) (mac_bssid[i + 1]) << 8;
704 tmp |= (u32) (mac_bssid[i + 2]) << 16;
705 tmp |= (u32) (mac_bssid[i + 3]) << 24;
706 b43_ram_write(dev, 0x20 + i, tmp);
707 }
708}
709
4150c572 710static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 711{
e4d6b795 712 b43_write_mac_bssid_templates(dev);
4150c572 713 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 714}
715
716static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
717{
718 /* slot_time is in usec. */
b6c3f5be
LF		 719 /* This test used to exit for all but a G PHY. */
720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 721 return;
b6c3f5be
LF		 722 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
723 /* Shared memory location 0x0010 is the slot time and should be
724 * set to slot_time; however, this register is initially 0 and changing
725 * the value adversely affects the transmit rate for BCM4311
726 * devices. Until this behavior is unterstood, delete this step
727 *
728 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
729 */
e4d6b795
MB		 730}
731
732static void b43_short_slot_timing_enable(struct b43_wldev *dev)
733{
734 b43_set_slot_time(dev, 9);
e4d6b795
MB		 735}
736
737static void b43_short_slot_timing_disable(struct b43_wldev *dev)
738{
739 b43_set_slot_time(dev, 20);
e4d6b795
MB		 740}
741
e4d6b795 742/* DummyTransmission function, as documented on
2f19c287 743 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 744 */
2f19c287 745void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 746{
747 struct b43_phy *phy = &dev->phy;
748 unsigned int i, max_loop;
749 u16 value;
750 u32 buffer[5] = {
751 0x00000000,
752 0x00D40000,
753 0x00000000,
754 0x01000000,
755 0x00000000,
756 };
757
2f19c287 758 if (ofdm) {
e4d6b795
MB		 759 max_loop = 0x1E;
760 buffer[0] = 0x000201CC;
2f19c287 761 } else {
e4d6b795
MB		 762 max_loop = 0xFA;
763 buffer[0] = 0x000B846E;
e4d6b795
MB		 764 }
765
766 for (i = 0; i < 5; i++)
767 b43_ram_write(dev, i * 4, buffer[i]);
768
7955d87f
RM		 769 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
770
21d889d4 771 if (dev->dev->core_rev < 11)
7955d87f 772 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 773 else
7955d87f
RM		 774 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
775
2f19c287 776 value = (ofdm ? 0x41 : 0x40);
7955d87f 777 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 778 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
779 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 780 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
781
782 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
783 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
784
785 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
786 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
787 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
788 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 789
790 if (!pa_on && phy->type == B43_PHYTYPE_N)
791 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 792
793 switch (phy->type) {
794 case B43_PHYTYPE_N:
93dbd828 795 case B43_PHYTYPE_LCN:
7955d87f 796 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 797 break;
798 case B43_PHYTYPE_LP:
7955d87f 799 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 800 break;
801 default:
7955d87f 802 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 803 }
93dbd828 804 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 805
806 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
807 b43_radio_write16(dev, 0x0051, 0x0017);
808 for (i = 0x00; i < max_loop; i++) {
7955d87f 809 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 810 if (value & 0x0080)
811 break;
812 udelay(10);
813 }
814 for (i = 0x00; i < 0x0A; i++) {
7955d87f 815 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 816 if (value & 0x0400)
817 break;
818 udelay(10);
819 }
1d280ddc 820 for (i = 0x00; i < 0x19; i++) {
7955d87f 821 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 822 if (!(value & 0x0100))
823 break;
824 udelay(10);
825 }
826 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
827 b43_radio_write16(dev, 0x0051, 0x0037);
828}
829
830static void key_write(struct b43_wldev *dev,
99da185a 831 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 832{
833 unsigned int i;
834 u32 offset;
835 u16 value;
836 u16 kidx;
837
838 /* Key index/algo block */
839 kidx = b43_kidx_to_fw(dev, index);
840 value = ((kidx << 4) | algorithm);
841 b43_shm_write16(dev, B43_SHM_SHARED,
842 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
843
844 /* Write the key to the Key Table Pointer offset */
845 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
846 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
847 value = key[i];
848 value |= (u16) (key[i + 1]) << 8;
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
850 }
851}
852
99da185a 853static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 854{
855 u32 addrtmp[2] = { 0, 0, };
66d2d089 856 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 857
858 if (b43_new_kidx_api(dev))
66d2d089 859 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 860
66d2d089
MB		 861 B43_WARN_ON(index < pairwise_keys_start);
862 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 863 * Physical mac 0 is mapped to physical key 4 or 8, depending
864 * on the firmware version.
865 * So we must adjust the index here.
866 */
66d2d089
MB		 867 index -= pairwise_keys_start;
868 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 869
870 if (addr) {
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 }
878
66d2d089
MB		 879 /* Receive match transmitter address (RCMTA) mechanism */
880 b43_shm_write32(dev, B43_SHM_RCMTA,
881 (index * 2) + 0, addrtmp[0]);
882 b43_shm_write16(dev, B43_SHM_RCMTA,
883 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 884}
885
035d0243 886/* The ucode will use phase1 key with TEK key to decrypt rx packets.
887 * When a packet is received, the iv32 is checked.
888 * - if it doesn't the packet is returned without modification (and software
889 * decryption can be done). That's what happen when iv16 wrap.
890 * - if it does, the rc4 key is computed, and decryption is tried.
891 * Either it will success and B43_RX_MAC_DEC is returned,
892 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
893 * and the packet is not usable (it got modified by the ucode).
894 * So in order to never have B43_RX_MAC_DECERR, we should provide
895 * a iv32 and phase1key that match. Because we drop packets in case of
896 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
897 * packets will be lost without higher layer knowing (ie no resync possible
898 * until next wrap).
899 *
900 * NOTE : this should support 50 key like RCMTA because
901 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
902 */
903static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
904 u16 *phase1key)
905{
906 unsigned int i;
907 u32 offset;
908 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
909
910 if (!modparam_hwtkip)
911 return;
912
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
915
916 B43_WARN_ON(index < pairwise_keys_start);
917 /* We have four default TX keys and possibly four default RX keys.
918 * Physical mac 0 is mapped to physical key 4 or 8, depending
919 * on the firmware version.
920 * So we must adjust the index here.
921 */
922 index -= pairwise_keys_start;
923 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
924
925 if (b43_debug(dev, B43_DBG_KEYS)) {
926 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
927 index, iv32);
928 }
929 /* Write the key to the RX tkip shared mem */
930 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
931 for (i = 0; i < 10; i += 2) {
932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
933 phase1key ? phase1key[i / 2] : 0);
934 }
935 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
936 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
937}
938
939static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 940 struct ieee80211_vif *vif,
941 struct ieee80211_key_conf *keyconf,
942 struct ieee80211_sta *sta,
943 u32 iv32, u16 *phase1key)
035d0243 944{
945 struct b43_wl *wl = hw_to_b43_wl(hw);
946 struct b43_wldev *dev;
947 int index = keyconf->hw_key_idx;
948
949 if (B43_WARN_ON(!modparam_hwtkip))
950 return;
951
96869a39
MB		 952 /* This is only called from the RX path through mac80211, where
953 * our mutex is already locked. */
954 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 955 dev = wl->current_dev;
96869a39 956 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 957
958 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
959
960 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 961 /* only pairwise TKIP keys are supported right now */
962 if (WARN_ON(!sta))
96869a39 963 return;
b3fbdcf4 964 keymac_write(dev, index, sta->addr);
035d0243 965}
966
e4d6b795
MB		 967static void do_key_write(struct b43_wldev *dev,
968 u8 index, u8 algorithm,
99da185a 969 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 970{
971 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 972 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 973
974 if (b43_new_kidx_api(dev))
66d2d089 975 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 976
66d2d089 977 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 978 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
979
66d2d089 980 if (index >= pairwise_keys_start)
e4d6b795 981 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 982 if (algorithm == B43_SEC_ALGO_TKIP) {
983 /*
984 * We should provide an initial iv32, phase1key pair.
985 * We could start with iv32=0 and compute the corresponding
986 * phase1key, but this means calling ieee80211_get_tkip_key
987 * with a fake skb (or export other tkip function).
988 * Because we are lazy we hope iv32 won't start with
989 * 0xffffffff and let's b43_op_update_tkip_key provide a
990 * correct pair.
991 */
992 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
993 } else if (index >= pairwise_keys_start) /* clear it */
994 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 995 if (key)
996 memcpy(buf, key, key_len);
997 key_write(dev, index, algorithm, buf);
66d2d089 998 if (index >= pairwise_keys_start)
e4d6b795
MB		 999 keymac_write(dev, index, mac_addr);
1000
1001 dev->key[index].algorithm = algorithm;
1002}
1003
1004static int b43_key_write(struct b43_wldev *dev,
1005 int index, u8 algorithm,
99da185a
JD		 1006 const u8 *key, size_t key_len,
1007 const u8 *mac_addr,
e4d6b795
MB		 1008 struct ieee80211_key_conf *keyconf)
1009{
1010 int i;
66d2d089 1011 int pairwise_keys_start;
e4d6b795 1012
035d0243 1013 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1014 * - Temporal Encryption Key (128 bits)
1015 * - Temporal Authenticator Tx MIC Key (64 bits)
1016 * - Temporal Authenticator Rx MIC Key (64 bits)
1017 *
1018 * Hardware only store TEK
1019 */
1020 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1021 key_len = 16;
e4d6b795
MB		 1022 if (key_len > B43_SEC_KEYSIZE)
1023 return -EINVAL;
66d2d089 1024 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 1025 /* Check that we don't already have this key. */
1026 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1027 }
1028 if (index < 0) {
e808e586 1029 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 1030 if (b43_new_kidx_api(dev))
66d2d089 1031 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 1032 else
66d2d089
MB		 1033 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1034 for (i = pairwise_keys_start;
1035 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1036 i++) {
1037 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 1038 if (!dev->key[i].keyconf) {
1039 /* found empty */
1040 index = i;
1041 break;
1042 }
1043 }
1044 if (index < 0) {
e808e586 1045 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1046 return -ENOSPC;
1047 }
1048 } else
1049 B43_WARN_ON(index > 3);
1050
1051 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1052 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1053 /* Default RX key */
1054 B43_WARN_ON(mac_addr);
1055 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1056 }
1057 keyconf->hw_key_idx = index;
1058 dev->key[index].keyconf = keyconf;
1059
1060 return 0;
1061}
1062
1063static int b43_key_clear(struct b43_wldev *dev, int index)
1064{
66d2d089 1065 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1066 return -EINVAL;
1067 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1068 NULL, B43_SEC_KEYSIZE, NULL);
1069 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1070 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1071 NULL, B43_SEC_KEYSIZE, NULL);
1072 }
1073 dev->key[index].keyconf = NULL;
1074
1075 return 0;
1076}
1077
1078static void b43_clear_keys(struct b43_wldev *dev)
1079{
66d2d089 1080 int i, count;
e4d6b795 1081
66d2d089
MB		 1082 if (b43_new_kidx_api(dev))
1083 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1084 else
1085 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1086 for (i = 0; i < count; i++)
e4d6b795
MB		 1087 b43_key_clear(dev, i);
1088}
1089
9cf7f247
MB		 1090static void b43_dump_keymemory(struct b43_wldev *dev)
1091{
66d2d089 1092 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1093 u8 mac[ETH_ALEN];
1094 u16 algo;
1095 u32 rcmta0;
1096 u16 rcmta1;
1097 u64 hf;
1098 struct b43_key *key;
1099
1100 if (!b43_debug(dev, B43_DBG_KEYS))
1101 return;
1102
1103 hf = b43_hf_read(dev);
1104 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1105 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1106 if (b43_new_kidx_api(dev)) {
1107 pairwise_keys_start = B43_NR_GROUP_KEYS;
1108 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1109 } else {
1110 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1111 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1112 }
1113 for (index = 0; index < count; index++) {
9cf7f247
MB		 1114 key = &(dev->key[index]);
1115 printk(KERN_DEBUG "Key slot %02u: %s",
1116 index, (key->keyconf == NULL) ? " " : "*");
1117 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1118 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1119 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1120 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1121 }
1122
1123 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1124 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1125 printk(" Algo: %04X/%02X", algo, key->algorithm);
1126
66d2d089 1127 if (index >= pairwise_keys_start) {
035d0243 1128 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1129 printk(" TKIP: ");
1130 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1131 for (i = 0; i < 14; i += 2) {
1132 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1133 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1134 }
1135 }
9cf7f247 1136 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1137 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1138 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1139 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1140 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1141 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1142 printk(" MAC: %pM", mac);
9cf7f247
MB		 1143 } else
1144 printk(" DEFAULT KEY");
1145 printk("\n");
1146 }
1147}
1148
e4d6b795
MB		 1149void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1150{
1151 u32 macctl;
1152 u16 ucstat;
1153 bool hwps;
1154 bool awake;
1155 int i;
1156
1157 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1158 (ps_flags & B43_PS_DISABLED));
1159 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1160
1161 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1162 hwps = true;
e4d6b795 1163 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1164 hwps = false;
e4d6b795
MB		 1165 } else {
1166 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1167 // and thus is not an AP and we are associated, set bit 25
1168 }
1169 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1170 awake = true;
e4d6b795 1171 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1172 awake = false;
e4d6b795
MB		 1173 } else {
1174 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1175 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1176 // successful, set bit26
1177 }
1178
1179/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1180 hwps = false;
1181 awake = true;
e4d6b795
MB		 1182
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1184 if (hwps)
1185 macctl |= B43_MACCTL_HWPS;
1186 else
1187 macctl &= ~B43_MACCTL_HWPS;
1188 if (awake)
1189 macctl |= B43_MACCTL_AWAKE;
1190 else
1191 macctl &= ~B43_MACCTL_AWAKE;
1192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1193 /* Commit write */
1194 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1195 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1196 /* Wait for the microcode to wake up. */
1197 for (i = 0; i < 100; i++) {
1198 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1199 B43_SHM_SH_UCODESTAT);
1200 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1201 break;
1202 udelay(10);
1203 }
1204 }
1205}
1206
737f657f
RM		 1207/* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
1208void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1209{
1210 struct bcma_drv_cc *bcma_cc __maybe_unused;
1211 struct ssb_chipcommon *ssb_cc __maybe_unused;
1212
1213 switch (dev->dev->bus_type) {
1214#ifdef CONFIG_B43_BCMA
1215 case B43_BUS_BCMA:
1216 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1217
1218 bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
1219 bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
1220 bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
1221 bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
1222 break;
1223#endif
1224#ifdef CONFIG_B43_SSB
1225 case B43_BUS_SSB:
1226 ssb_cc = &dev->dev->sdev->bus->chipco;
1227
1228 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0);
1229 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1230 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4);
1231 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1232 break;
1233#endif
1234 }
1235}
1236
42c9a458 1237#ifdef CONFIG_B43_BCMA
49173592 1238static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1239{
49173592 1240 u32 flags;
42c9a458 1241
49173592
RM		 1242 /* Put PHY into reset */
1243 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1244 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1245 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1246 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1247 udelay(2);
1248
50c1b59e 1249 b43_phy_take_out_of_reset(dev);
49173592 1250}
42c9a458 1251
49173592
RM		 1252static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1253{
88cceab5
RM		 1254 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1255 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1256 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1257 B43_BCMA_CLKCTLST_PHY_PLL_ST;
6b9e03e6
RM		 1258 u32 flags;
1259
1260 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1261 if (gmode)
1262 flags |= B43_BCMA_IOCTL_GMODE;
1263 b43_device_enable(dev, flags);
88cceab5 1264
49173592
RM		 1265 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1266 b43_bcma_phy_reset(dev);
88cceab5 1267 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
42c9a458
RM		 1268}
1269#endif
1270
bd7c8a59 1271#ifdef CONFIG_B43_SSB
4da909e7 1272static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1273{
4da909e7 1274 u32 flags = 0;
e4d6b795 1275
4da909e7
RM		 1276 if (gmode)
1277 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1278 flags |= B43_TMSLOW_PHYCLKEN;
1279 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1280 if (dev->phy.type == B43_PHYTYPE_N)
1281 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1282 b43_device_enable(dev, flags);
e4d6b795
MB		 1283 msleep(2); /* Wait for the PLL to turn on. */
1284
50c1b59e 1285 b43_phy_take_out_of_reset(dev);
1495298d 1286}
bd7c8a59 1287#endif
1495298d 1288
4da909e7 1289void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1290{
1291 u32 macctl;
1292
6cbab0d9 1293 switch (dev->dev->bus_type) {
42c9a458
RM		 1294#ifdef CONFIG_B43_BCMA
1295 case B43_BUS_BCMA:
1296 b43_bcma_wireless_core_reset(dev, gmode);
1297 break;
1298#endif
6cbab0d9
RM		 1299#ifdef CONFIG_B43_SSB
1300 case B43_BUS_SSB:
1301 b43_ssb_wireless_core_reset(dev, gmode);
1302 break;
1303#endif
1304 }
e4d6b795 1305
fb11137a
MB		 1306 /* Turn Analog ON, but only if we already know the PHY-type.
1307 * This protects against very early setup where we don't know the
1308 * PHY-type, yet. wireless_core_reset will be called once again later,
1309 * when we know the PHY-type. */
1310 if (dev->phy.ops)
cb24f57f 1311 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1312
1313 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1314 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1315 if (gmode)
e4d6b795
MB		 1316 macctl |= B43_MACCTL_GMODE;
1317 macctl |= B43_MACCTL_IHR_ENABLED;
1318 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1319}
1320
1321static void handle_irq_transmit_status(struct b43_wldev *dev)
1322{
1323 u32 v0, v1;
1324 u16 tmp;
1325 struct b43_txstatus stat;
1326
1327 while (1) {
1328 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1329 if (!(v0 & 0x00000001))
1330 break;
1331 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1332
1333 stat.cookie = (v0 >> 16);
1334 stat.seq = (v1 & 0x0000FFFF);
1335 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1336 tmp = (v0 & 0x0000FFFF);
1337 stat.frame_count = ((tmp & 0xF000) >> 12);
1338 stat.rts_count = ((tmp & 0x0F00) >> 8);
1339 stat.supp_reason = ((tmp & 0x001C) >> 2);
1340 stat.pm_indicated = !!(tmp & 0x0080);
1341 stat.intermediate = !!(tmp & 0x0040);
1342 stat.for_ampdu = !!(tmp & 0x0020);
1343 stat.acked = !!(tmp & 0x0002);
1344
1345 b43_handle_txstatus(dev, &stat);
1346 }
1347}
1348
1349static void drain_txstatus_queue(struct b43_wldev *dev)
1350{
1351 u32 dummy;
1352
21d889d4 1353 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1354 return;
1355 /* Read all entries from the microcode TXstatus FIFO
1356 * and throw them away.
1357 */
1358 while (1) {
1359 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1360 if (!(dummy & 0x00000001))
1361 break;
1362 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1363 }
1364}
1365
1366static u32 b43_jssi_read(struct b43_wldev *dev)
1367{
1368 u32 val = 0;
1369
5c1da23b 1370 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
e4d6b795 1371 val <<= 16;
5c1da23b 1372 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
e4d6b795
MB		 1373
1374 return val;
1375}
1376
1377static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1378{
5c1da23b
HM		 1379 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1380 (jssi & 0x0000FFFF));
1381 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1382 (jssi & 0xFFFF0000) >> 16);
e4d6b795
MB		 1383}
1384
1385static void b43_generate_noise_sample(struct b43_wldev *dev)
1386{
1387 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1388 b43_write32(dev, B43_MMIO_MACCMD,
1389 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1390}
1391
1392static void b43_calculate_link_quality(struct b43_wldev *dev)
1393{
1394 /* Top half of Link Quality calculation. */
1395
ef1a628d
MB		 1396 if (dev->phy.type != B43_PHYTYPE_G)
1397 return;
e4d6b795
MB		 1398 if (dev->noisecalc.calculation_running)
1399 return;
3db1cd5c 1400 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1401 dev->noisecalc.nr_samples = 0;
1402
1403 b43_generate_noise_sample(dev);
1404}
1405
1406static void handle_irq_noise(struct b43_wldev *dev)
1407{
ef1a628d 1408 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1409 u16 tmp;
1410 u8 noise[4];
1411 u8 i, j;
1412 s32 average;
1413
1414 /* Bottom half of Link Quality calculation. */
1415
ef1a628d
MB		 1416 if (dev->phy.type != B43_PHYTYPE_G)
1417 return;
1418
98a3b2fe
MB		 1419 /* Possible race condition: It might be possible that the user
1420 * changed to a different channel in the meantime since we
1421 * started the calculation. We ignore that fact, since it's
1422 * not really that much of a problem. The background noise is
1423 * an estimation only anyway. Slightly wrong results will get damped
1424 * by the averaging of the 8 sample rounds. Additionally the
1425 * value is shortlived. So it will be replaced by the next noise
1426 * calculation round soon. */
1427
e4d6b795 1428 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1429 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1430 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1431 noise[2] == 0x7F || noise[3] == 0x7F)
1432 goto generate_new;
1433
1434 /* Get the noise samples. */
1435 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1436 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1437 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1438 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1439 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1440 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1441 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1442 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1443 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1444 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1445 dev->noisecalc.nr_samples++;
1446 if (dev->noisecalc.nr_samples == 8) {
1447 /* Calculate the Link Quality by the noise samples. */
1448 average = 0;
1449 for (i = 0; i < 8; i++) {
1450 for (j = 0; j < 4; j++)
1451 average += dev->noisecalc.samples[i][j];
1452 }
1453 average /= (8 * 4);
1454 average *= 125;
1455 average += 64;
1456 average /= 128;
1457 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1458 tmp = (tmp / 128) & 0x1F;
1459 if (tmp >= 8)
1460 average += 2;
1461 else
1462 average -= 25;
1463 if (tmp == 8)
1464 average -= 72;
1465 else
1466 average -= 48;
1467
1468 dev->stats.link_noise = average;
3db1cd5c 1469 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1470 return;
1471 }
98a3b2fe 1472generate_new:
e4d6b795
MB		 1473 b43_generate_noise_sample(dev);
1474}
1475
1476static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1477{
05c914fe 1478 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1479 ///TODO: PS TBTT
1480 } else {
1481 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1482 b43_power_saving_ctl_bits(dev, 0);
1483 }
05c914fe 1484 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1485 dev->dfq_valid = true;
e4d6b795
MB		 1486}
1487
1488static void handle_irq_atim_end(struct b43_wldev *dev)
1489{
aa6c7ae2
MB		 1490 if (dev->dfq_valid) {
1491 b43_write32(dev, B43_MMIO_MACCMD,
1492 b43_read32(dev, B43_MMIO_MACCMD)
1493 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1494 dev->dfq_valid = false;
aa6c7ae2 1495 }
e4d6b795
MB		 1496}
1497
1498static void handle_irq_pmq(struct b43_wldev *dev)
1499{
1500 u32 tmp;
1501
1502 //TODO: AP mode.
1503
1504 while (1) {
1505 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1506 if (!(tmp & 0x00000008))
1507 break;
1508 }
1509 /* 16bit write is odd, but correct. */
1510 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1511}
1512
1513static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1514 const u8 *data, u16 size,
e4d6b795
MB		 1515 u16 ram_offset,
1516 u16 shm_size_offset, u8 rate)
1517{
1518 u32 i, tmp;
1519 struct b43_plcp_hdr4 plcp;
1520
1521 plcp.data = 0;
1522 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1523 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1524 ram_offset += sizeof(u32);
1525 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1526 * So leave the first two bytes of the next write blank.
1527 */
1528 tmp = (u32) (data[0]) << 16;
1529 tmp |= (u32) (data[1]) << 24;
1530 b43_ram_write(dev, ram_offset, tmp);
1531 ram_offset += sizeof(u32);
1532 for (i = 2; i < size; i += sizeof(u32)) {
1533 tmp = (u32) (data[i + 0]);
1534 if (i + 1 < size)
1535 tmp |= (u32) (data[i + 1]) << 8;
1536 if (i + 2 < size)
1537 tmp |= (u32) (data[i + 2]) << 16;
1538 if (i + 3 < size)
1539 tmp |= (u32) (data[i + 3]) << 24;
1540 b43_ram_write(dev, ram_offset + i - 2, tmp);
1541 }
1542 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1543 size + sizeof(struct b43_plcp_hdr6));
1544}
1545
5042c507
MB		 1546/* Check if the use of the antenna that ieee80211 told us to
1547 * use is possible. This will fall back to DEFAULT.
1548 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1549u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1550 u8 antenna_nr)
1551{
1552 u8 antenna_mask;
1553
1554 if (antenna_nr == 0) {
1555 /* Zero means "use default antenna". That's always OK. */
1556 return 0;
1557 }
1558
1559 /* Get the mask of available antennas. */
1560 if (dev->phy.gmode)
0581483a 1561 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1562 else
0581483a 1563 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1564
1565 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1566 /* This antenna is not available. Fall back to default. */
1567 return 0;
1568 }
1569
1570 return antenna_nr;
1571}
1572
5042c507
MB		 1573/* Convert a b43 antenna number value to the PHY TX control value. */
1574static u16 b43_antenna_to_phyctl(int antenna)
1575{
1576 switch (antenna) {
1577 case B43_ANTENNA0:
1578 return B43_TXH_PHY_ANT0;
1579 case B43_ANTENNA1:
1580 return B43_TXH_PHY_ANT1;
1581 case B43_ANTENNA2:
1582 return B43_TXH_PHY_ANT2;
1583 case B43_ANTENNA3:
1584 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1585 case B43_ANTENNA_AUTO0:
1586 case B43_ANTENNA_AUTO1:
5042c507
MB		 1587 return B43_TXH_PHY_ANT01AUTO;
1588 }
1589 B43_WARN_ON(1);
1590 return 0;
1591}
1592
e4d6b795
MB		 1593static void b43_write_beacon_template(struct b43_wldev *dev,
1594 u16 ram_offset,
5042c507 1595 u16 shm_size_offset)
e4d6b795 1596{
47f76ca3 1597 unsigned int i, len, variable_len;
e66fee6a
MB		 1598 const struct ieee80211_mgmt *bcn;
1599 const u8 *ie;
3db1cd5c 1600 bool tim_found = false;
5042c507
MB		 1601 unsigned int rate;
1602 u16 ctl;
1603 int antenna;
e039fa4a 1604 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1605
e66fee6a 1606 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
c8e49556 1607 len = min_t(size_t, dev->wl->current_beacon->len,
e4d6b795 1608 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1609 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1610
1611 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1612 len, ram_offset, shm_size_offset, rate);
e66fee6a 1613
5042c507 1614 /* Write the PHY TX control parameters. */
0f4ac38b 1615 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1616 antenna = b43_antenna_to_phyctl(antenna);
1617 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1618 /* We can't send beacons with short preamble. Would get PHY errors. */
1619 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1620 ctl &= ~B43_TXH_PHY_ANT;
1621 ctl &= ~B43_TXH_PHY_ENC;
1622 ctl |= antenna;
1623 if (b43_is_cck_rate(rate))
1624 ctl |= B43_TXH_PHY_ENC_CCK;
1625 else
1626 ctl |= B43_TXH_PHY_ENC_OFDM;
1627 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1628
e66fee6a
MB		 1629 /* Find the position of the TIM and the DTIM_period value
1630 * and write them to SHM. */
1631 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1632 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1633 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1634 uint8_t ie_id, ie_len;
1635
1636 ie_id = ie[i];
1637 ie_len = ie[i + 1];
1638 if (ie_id == 5) {
1639 u16 tim_position;
1640 u16 dtim_period;
1641 /* This is the TIM Information Element */
1642
1643 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1644 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1645 break;
1646 /* A valid TIM is at least 4 bytes long. */
1647 if (ie_len < 4)
1648 break;
3db1cd5c 1649 tim_found = true;
e66fee6a
MB		 1650
1651 tim_position = sizeof(struct b43_plcp_hdr6);
1652 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1653 tim_position += i;
1654
1655 dtim_period = ie[i + 3];
1656
1657 b43_shm_write16(dev, B43_SHM_SHARED,
1658 B43_SHM_SH_TIMBPOS, tim_position);
1659 b43_shm_write16(dev, B43_SHM_SHARED,
1660 B43_SHM_SH_DTIMPER, dtim_period);
1661 break;
1662 }
1663 i += ie_len + 2;
1664 }
1665 if (!tim_found) {
04dea136
JB		 1666 /*
1667 * If ucode wants to modify TIM do it behind the beacon, this
1668 * will happen, for example, when doing mesh networking.
1669 */
1670 b43_shm_write16(dev, B43_SHM_SHARED,
1671 B43_SHM_SH_TIMBPOS,
1672 len + sizeof(struct b43_plcp_hdr6));
1673 b43_shm_write16(dev, B43_SHM_SHARED,
1674 B43_SHM_SH_DTIMPER, 0);
1675 }
1676 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1677}
1678
6b4bec01
MB		 1679static void b43_upload_beacon0(struct b43_wldev *dev)
1680{
1681 struct b43_wl *wl = dev->wl;
1682
1683 if (wl->beacon0_uploaded)
1684 return;
5c1da23b 1685 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
3db1cd5c 1686 wl->beacon0_uploaded = true;
6b4bec01
MB		 1687}
1688
1689static void b43_upload_beacon1(struct b43_wldev *dev)
1690{
1691 struct b43_wl *wl = dev->wl;
1692
1693 if (wl->beacon1_uploaded)
1694 return;
5c1da23b 1695 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
3db1cd5c 1696 wl->beacon1_uploaded = true;
6b4bec01
MB		 1697}
1698
c97a4ccc
MB		 1699static void handle_irq_beacon(struct b43_wldev *dev)
1700{
1701 struct b43_wl *wl = dev->wl;
1702 u32 cmd, beacon0_valid, beacon1_valid;
1703
05c914fe 1704 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1705 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1706 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1707 return;
1708
1709 /* This is the bottom half of the asynchronous beacon update. */
1710
1711 /* Ignore interrupt in the future. */
13790728 1712 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1713
1714 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1715 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1716 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1717
1718 /* Schedule interrupt manually, if busy. */
1719 if (beacon0_valid && beacon1_valid) {
1720 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1721 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1722 return;
1723 }
1724
6b4bec01
MB		 1725 if (unlikely(wl->beacon_templates_virgin)) {
1726 /* We never uploaded a beacon before.
1727 * Upload both templates now, but only mark one valid. */
3db1cd5c 1728 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1729 b43_upload_beacon0(dev);
1730 b43_upload_beacon1(dev);
c97a4ccc
MB		 1731 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1732 cmd |= B43_MACCMD_BEACON0_VALID;
1733 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1734 } else {
1735 if (!beacon0_valid) {
1736 b43_upload_beacon0(dev);
1737 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1738 cmd |= B43_MACCMD_BEACON0_VALID;
1739 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1740 } else if (!beacon1_valid) {
1741 b43_upload_beacon1(dev);
1742 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1743 cmd |= B43_MACCMD_BEACON1_VALID;
1744 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1745 }
c97a4ccc
MB		 1746 }
1747}
1748
36dbd954
MB		 1749static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1750{
1751 u32 old_irq_mask = dev->irq_mask;
1752
1753 /* update beacon right away or defer to irq */
1754 handle_irq_beacon(dev);
1755 if (old_irq_mask != dev->irq_mask) {
1756 /* The handler updated the IRQ mask. */
1757 B43_WARN_ON(!dev->irq_mask);
1758 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1759 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1760 } else {
1761 /* Device interrupts are currently disabled. That means
1762 * we just ran the hardirq handler and scheduled the
1763 * IRQ thread. The thread will write the IRQ mask when
1764 * it finished, so there's nothing to do here. Writing
1765 * the mask _here_ would incorrectly re-enable IRQs. */
1766 }
1767 }
1768}
1769
a82d9922
MB		 1770static void b43_beacon_update_trigger_work(struct work_struct *work)
1771{
1772 struct b43_wl *wl = container_of(work, struct b43_wl,
1773 beacon_update_trigger);
1774 struct b43_wldev *dev;
1775
1776 mutex_lock(&wl->mutex);
1777 dev = wl->current_dev;
1778 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1779 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1780 /* wl->mutex is enough. */
1781 b43_do_beacon_update_trigger_work(dev);
1782 mmiowb();
1783 } else {
1784 spin_lock_irq(&wl->hardirq_lock);
1785 b43_do_beacon_update_trigger_work(dev);
1786 mmiowb();
1787 spin_unlock_irq(&wl->hardirq_lock);
1788 }
a82d9922
MB		 1789 }
1790 mutex_unlock(&wl->mutex);
1791}
1792
d4df6f1a 1793/* Asynchronously update the packet templates in template RAM.
36dbd954 1794 * Locking: Requires wl->mutex to be locked. */
9d139c81 1795static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1796{
9d139c81
JB		 1797 struct sk_buff *beacon;
1798
e66fee6a
MB		 1799 /* This is the top half of the ansynchronous beacon update.
1800 * The bottom half is the beacon IRQ.
1801 * Beacon update must be asynchronous to avoid sending an
1802 * invalid beacon. This can happen for example, if the firmware
1803 * transmits a beacon while we are updating it. */
e4d6b795 1804
9d139c81
JB		 1805 /* We could modify the existing beacon and set the aid bit in
1806 * the TIM field, but that would probably require resizing and
1807 * moving of data within the beacon template.
1808 * Simply request a new beacon and let mac80211 do the hard work. */
1809 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1810 if (unlikely(!beacon))
1811 return;
1812
e66fee6a
MB		 1813 if (wl->current_beacon)
1814 dev_kfree_skb_any(wl->current_beacon);
1815 wl->current_beacon = beacon;
3db1cd5c
RR		 1816 wl->beacon0_uploaded = false;
1817 wl->beacon1_uploaded = false;
42935eca 1818 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1819}
1820
e4d6b795
MB		 1821static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1822{
1823 b43_time_lock(dev);
21d889d4 1824 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1825 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1826 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1827 } else {
1828 b43_write16(dev, 0x606, (beacon_int >> 6));
1829 b43_write16(dev, 0x610, beacon_int);
1830 }
1831 b43_time_unlock(dev);
a82d9922 1832 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1833}
1834
afa83e23
MB		 1835static void b43_handle_firmware_panic(struct b43_wldev *dev)
1836{
1837 u16 reason;
1838
1839 /* Read the register that contains the reason code for the panic. */
1840 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1841 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1842
1843 switch (reason) {
1844 default:
1845 b43dbg(dev->wl, "The panic reason is unknown.\n");
1846 /* fallthrough */
1847 case B43_FWPANIC_DIE:
1848 /* Do not restart the controller or firmware.
1849 * The device is nonfunctional from now on.
1850 * Restarting would result in this panic to trigger again,
1851 * so we avoid that recursion. */
1852 break;
1853 case B43_FWPANIC_RESTART:
1854 b43_controller_restart(dev, "Microcode panic");
1855 break;
1856 }
1857}
1858
e4d6b795
MB		 1859static void handle_irq_ucode_debug(struct b43_wldev *dev)
1860{
e48b0eeb 1861 unsigned int i, cnt;
53c06856 1862 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1863 __le16 *buf;
1864
1865 /* The proprietary firmware doesn't have this IRQ. */
1866 if (!dev->fw.opensource)
1867 return;
1868
afa83e23
MB		 1869 /* Read the register that contains the reason code for this IRQ. */
1870 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1871
e48b0eeb
MB		 1872 switch (reason) {
1873 case B43_DEBUGIRQ_PANIC:
afa83e23 1874 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1875 break;
1876 case B43_DEBUGIRQ_DUMP_SHM:
1877 if (!B43_DEBUG)
1878 break; /* Only with driver debugging enabled. */
1879 buf = kmalloc(4096, GFP_ATOMIC);
1880 if (!buf) {
1881 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1882 goto out;
1883 }
1884 for (i = 0; i < 4096; i += 2) {
1885 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1886 buf[i / 2] = cpu_to_le16(tmp);
1887 }
1888 b43info(dev->wl, "Shared memory dump:\n");
1889 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1890 16, 2, buf, 4096, 1);
1891 kfree(buf);
1892 break;
1893 case B43_DEBUGIRQ_DUMP_REGS:
1894 if (!B43_DEBUG)
1895 break; /* Only with driver debugging enabled. */
1896 b43info(dev->wl, "Microcode register dump:\n");
1897 for (i = 0, cnt = 0; i < 64; i++) {
1898 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1899 if (cnt == 0)
1900 printk(KERN_INFO);
1901 printk("r%02u: 0x%04X ", i, tmp);
1902 cnt++;
1903 if (cnt == 6) {
1904 printk("\n");
1905 cnt = 0;
1906 }
1907 }
1908 printk("\n");
1909 break;
53c06856
MB		 1910 case B43_DEBUGIRQ_MARKER:
1911 if (!B43_DEBUG)
1912 break; /* Only with driver debugging enabled. */
1913 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1914 B43_MARKER_ID_REG);
1915 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1916 B43_MARKER_LINE_REG);
1917 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1918 "at line number %u\n",
1919 marker_id, marker_line);
1920 break;
e48b0eeb
MB		 1921 default:
1922 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1923 reason);
1924 }
1925out:
afa83e23
MB		 1926 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1927 b43_shm_write16(dev, B43_SHM_SCRATCH,
1928 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1929}
1930
36dbd954 1931static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1932{
1933 u32 reason;
1934 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1935 u32 merged_dma_reason = 0;
21954c36 1936 int i;
e4d6b795 1937
36dbd954
MB		 1938 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1939 return;
e4d6b795
MB		 1940
1941 reason = dev->irq_reason;
1942 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1943 dma_reason[i] = dev->dma_reason[i];
1944 merged_dma_reason |= dma_reason[i];
1945 }
1946
1947 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1948 b43err(dev->wl, "MAC transmission error\n");
1949
00e0b8cb 1950 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1951 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1952 rmb();
1953 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1954 atomic_set(&dev->phy.txerr_cnt,
1955 B43_PHY_TX_BADNESS_LIMIT);
1956 b43err(dev->wl, "Too many PHY TX errors, "
1957 "restarting the controller\n");
1958 b43_controller_restart(dev, "PHY TX errors");
1959 }
1960 }
e4d6b795 1961
73b82bf0
TJ		 1962 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1963 b43err(dev->wl,
1964 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1965 dma_reason[0], dma_reason[1],
1966 dma_reason[2], dma_reason[3],
1967 dma_reason[4], dma_reason[5]);
1968 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1969 "on your system. It will now be switched to PIO.\n");
73b82bf0
TJ		 1970 /* Fall back to PIO transfers if we get fatal DMA errors! */
1971 dev->use_pio = true;
1972 b43_controller_restart(dev, "DMA error");
1973 return;
e4d6b795
MB		 1974 }
1975
1976 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1977 handle_irq_ucode_debug(dev);
1978 if (reason & B43_IRQ_TBTT_INDI)
1979 handle_irq_tbtt_indication(dev);
1980 if (reason & B43_IRQ_ATIM_END)
1981 handle_irq_atim_end(dev);
1982 if (reason & B43_IRQ_BEACON)
1983 handle_irq_beacon(dev);
1984 if (reason & B43_IRQ_PMQ)
1985 handle_irq_pmq(dev);
21954c36
MB		 1986 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1987 ;/* TODO */
1988 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1989 handle_irq_noise(dev);
1990
1991 /* Check the DMA reason registers for received data. */
73b82bf0
TJ		 1992 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1993 if (B43_DEBUG)
1994 b43warn(dev->wl, "RX descriptor underrun\n");
1995 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1996 }
5100d5ac
MB		 1997 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1998 if (b43_using_pio_transfers(dev))
1999 b43_pio_rx(dev->pio.rx_queue);
2000 else
2001 b43_dma_rx(dev->dma.rx_ring);
2002 }
e4d6b795
MB		 2003 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
2004 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 2005 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 2006 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
2007 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
2008
21954c36 2009 if (reason & B43_IRQ_TX_OK)
e4d6b795 2010 handle_irq_transmit_status(dev);
e4d6b795 2011
36dbd954 2012 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 2013 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 2014
2015#if B43_DEBUG
2016 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2017 dev->irq_count++;
2018 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2019 if (reason & (1 << i))
2020 dev->irq_bit_count[i]++;
2021 }
2022 }
2023#endif
e4d6b795
MB		 2024}
2025
36dbd954
MB		 2026/* Interrupt thread handler. Handles device interrupts in thread context. */
2027static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 2028{
36dbd954 2029 struct b43_wldev *dev = dev_id;
e4d6b795 2030
36dbd954
MB		 2031 mutex_lock(&dev->wl->mutex);
2032 b43_do_interrupt_thread(dev);
2033 mmiowb();
2034 mutex_unlock(&dev->wl->mutex);
2035
2036 return IRQ_HANDLED;
e4d6b795
MB		 2037}
2038
36dbd954 2039static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 2040{
e4d6b795
MB		 2041 u32 reason;
2042
36dbd954
MB		 2043 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2044 * On SDIO, this runs under wl->mutex. */
e4d6b795 2045
e4d6b795
MB		 2046 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2047 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 2048 return IRQ_NONE;
13790728 2049 reason &= dev->irq_mask;
e4d6b795 2050 if (!reason)
cae56147 2051 return IRQ_NONE;
e4d6b795
MB		 2052
2053 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
73b82bf0 2054 & 0x0001FC00;
e4d6b795
MB		 2055 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2056 & 0x0000DC00;
2057 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2058 & 0x0000DC00;
2059 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2060 & 0x0001DC00;
2061 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2062 & 0x0000DC00;
13790728 2063/* Unused ring
e4d6b795
MB		 2064 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2065 & 0x0000DC00;
13790728 2066*/
e4d6b795 2067
36dbd954
MB		 2068 /* ACK the interrupt. */
2069 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2070 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2071 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2072 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2073 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2074 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2075/* Unused ring
2076 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2077*/
2078
2079 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2080 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2081 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2082 dev->irq_reason = reason;
36dbd954
MB		 2083
2084 return IRQ_WAKE_THREAD;
2085}
2086
2087/* Interrupt handler top-half. This runs with interrupts disabled. */
2088static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2089{
2090 struct b43_wldev *dev = dev_id;
2091 irqreturn_t ret;
2092
2093 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2094 return IRQ_NONE;
2095
2096 spin_lock(&dev->wl->hardirq_lock);
2097 ret = b43_do_interrupt(dev);
e4d6b795 2098 mmiowb();
36dbd954 2099 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2100
2101 return ret;
2102}
2103
3dbba8e2
AH		 2104/* SDIO interrupt handler. This runs in process context. */
2105static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2106{
2107 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2108 irqreturn_t ret;
2109
3dbba8e2 2110 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2111
2112 ret = b43_do_interrupt(dev);
2113 if (ret == IRQ_WAKE_THREAD)
2114 b43_do_interrupt_thread(dev);
2115
3dbba8e2
AH		 2116 mutex_unlock(&wl->mutex);
2117}
2118
1a9f5093 2119void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2120{
2121 release_firmware(fw->data);
2122 fw->data = NULL;
2123 fw->filename = NULL;
2124}
2125
e4d6b795
MB		 2126static void b43_release_firmware(struct b43_wldev *dev)
2127{
0673effd 2128 complete(&dev->fw_load_complete);
1a9f5093
MB		 2129 b43_do_release_fw(&dev->fw.ucode);
2130 b43_do_release_fw(&dev->fw.pcm);
2131 b43_do_release_fw(&dev->fw.initvals);
2132 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2133}
2134
eb189d8b 2135static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2136{
fc68ed4f
HE		 2137 const char text[] =
2138 "You must go to " \
2139 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2140 "and download the correct firmware for this driver version. " \
2141 "Please carefully read all instructions on this website.\n";
eb189d8b 2142
eb189d8b
MB		 2143 if (error)
2144 b43err(wl, text);
2145 else
2146 b43warn(wl, text);
e4d6b795
MB		 2147}
2148
5e20a4b5
LF		 2149static void b43_fw_cb(const struct firmware *firmware, void *context)
2150{
2151 struct b43_request_fw_context *ctx = context;
2152
2153 ctx->blob = firmware;
0673effd 2154 complete(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2155}
2156
1a9f5093
MB		 2157int b43_do_request_fw(struct b43_request_fw_context *ctx,
2158 const char *name,
5e20a4b5 2159 struct b43_firmware_file *fw, bool async)
e4d6b795 2160{
e4d6b795
MB		 2161 struct b43_fw_header *hdr;
2162 u32 size;
2163 int err;
2164
61cb5dd6
MB		 2165 if (!name) {
2166 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2167 /* FIXME: We should probably keep it anyway, to save some headache
2168 * on suspend/resume with multiband devices. */
2169 b43_do_release_fw(fw);
e4d6b795 2170 return 0;
61cb5dd6
MB		 2171 }
2172 if (fw->filename) {
1a9f5093
MB		 2173 if ((fw->type == ctx->req_type) &&
2174 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2175 return 0; /* Already have this fw. */
2176 /* Free the cached firmware first. */
1a9f5093
MB		 2177 /* FIXME: We should probably do this later after we successfully
2178 * got the new fw. This could reduce headache with multiband devices.
2179 * We could also redesign this to cache the firmware for all possible
2180 * bands all the time. */
2181 b43_do_release_fw(fw);
61cb5dd6 2182 }
e4d6b795 2183
1a9f5093
MB		 2184 switch (ctx->req_type) {
2185 case B43_FWTYPE_PROPRIETARY:
2186 snprintf(ctx->fwname, sizeof(ctx->fwname),
2187 "b43%s/%s.fw",
2188 modparam_fwpostfix, name);
2189 break;
2190 case B43_FWTYPE_OPENSOURCE:
2191 snprintf(ctx->fwname, sizeof(ctx->fwname),
2192 "b43-open%s/%s.fw",
2193 modparam_fwpostfix, name);
2194 break;
2195 default:
2196 B43_WARN_ON(1);
2197 return -ENOSYS;
2198 }
5e20a4b5
LF		 2199 if (async) {
2200 /* do this part asynchronously */
0673effd 2201 init_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2202 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2203 ctx->dev->dev->dev, GFP_KERNEL,
2204 ctx, b43_fw_cb);
2205 if (err < 0) {
2206 pr_err("Unable to load firmware\n");
2207 return err;
2208 }
0673effd 2209 wait_for_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2210 if (ctx->blob)
2211 goto fw_ready;
2212 /* On some ARM systems, the async request will fail, but the next sync
0673effd 2213 * request works. For this reason, we fall through here
5e20a4b5
LF		 2214 */
2215 }
2216 err = request_firmware(&ctx->blob, ctx->fwname,
2217 ctx->dev->dev->dev);
68217832 2218 if (err == -ENOENT) {
1a9f5093
MB		 2219 snprintf(ctx->errors[ctx->req_type],
2220 sizeof(ctx->errors[ctx->req_type]),
5e20a4b5
LF		 2221 "Firmware file \"%s\" not found\n",
2222 ctx->fwname);
68217832
MB		 2223 return err;
2224 } else if (err) {
1a9f5093
MB		 2225 snprintf(ctx->errors[ctx->req_type],
2226 sizeof(ctx->errors[ctx->req_type]),
2227 "Firmware file \"%s\" request failed (err=%d)\n",
2228 ctx->fwname, err);
e4d6b795
MB		 2229 return err;
2230 }
5e20a4b5
LF		 2231fw_ready:
2232 if (ctx->blob->size < sizeof(struct b43_fw_header))
e4d6b795 2233 goto err_format;
5e20a4b5 2234 hdr = (struct b43_fw_header *)(ctx->blob->data);
e4d6b795
MB		 2235 switch (hdr->type) {
2236 case B43_FW_TYPE_UCODE:
2237 case B43_FW_TYPE_PCM:
2238 size = be32_to_cpu(hdr->size);
5e20a4b5 2239 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2240 goto err_format;
2241 /* fallthrough */
2242 case B43_FW_TYPE_IV:
2243 if (hdr->ver != 1)
2244 goto err_format;
2245 break;
2246 default:
2247 goto err_format;
2248 }
2249
5e20a4b5 2250 fw->data = ctx->blob;
61cb5dd6 2251 fw->filename = name;
1a9f5093 2252 fw->type = ctx->req_type;
61cb5dd6
MB		 2253
2254 return 0;
e4d6b795
MB		 2255
2256err_format:
1a9f5093
MB		 2257 snprintf(ctx->errors[ctx->req_type],
2258 sizeof(ctx->errors[ctx->req_type]),
2259 "Firmware file \"%s\" format error.\n", ctx->fwname);
5e20a4b5 2260 release_firmware(ctx->blob);
61cb5dd6 2261
e4d6b795
MB		 2262 return -EPROTO;
2263}
2264
a60f99f7 2265/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
1a9f5093 2266static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2267{
1a9f5093
MB		 2268 struct b43_wldev *dev = ctx->dev;
2269 struct b43_firmware *fw = &ctx->dev->fw;
a60f99f7 2270 struct b43_phy *phy = &dev->phy;
21d889d4 2271 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795 2272 const char *filename;
e4d6b795
MB		 2273 int err;
2274
61cb5dd6 2275 /* Get microcode */
a60f99f7
RM		 2276 filename = NULL;
2277 switch (rev) {
2278 case 42:
2279 if (phy->type == B43_PHYTYPE_AC)
2280 filename = "ucode42";
2281 break;
15be8e89
RM		 2282 case 40:
2283 if (phy->type == B43_PHYTYPE_AC)
2284 filename = "ucode40";
2285 break;
a60f99f7
RM		 2286 case 33:
2287 if (phy->type == B43_PHYTYPE_LCN40)
2288 filename = "ucode33_lcn40";
2289 break;
2290 case 30:
2291 if (phy->type == B43_PHYTYPE_N)
2292 filename = "ucode30_mimo";
2293 break;
2294 case 29:
2295 if (phy->type == B43_PHYTYPE_HT)
2296 filename = "ucode29_mimo";
2297 break;
2298 case 26:
2299 if (phy->type == B43_PHYTYPE_HT)
2300 filename = "ucode26_mimo";
2301 break;
2302 case 28:
2303 case 25:
2304 if (phy->type == B43_PHYTYPE_N)
2305 filename = "ucode25_mimo";
2306 else if (phy->type == B43_PHYTYPE_LCN)
2307 filename = "ucode25_lcn";
2308 break;
2309 case 24:
2310 if (phy->type == B43_PHYTYPE_LCN)
2311 filename = "ucode24_lcn";
2312 break;
2313 case 23:
2314 if (phy->type == B43_PHYTYPE_N)
2315 filename = "ucode16_mimo";
2316 break;
2317 case 16 ... 19:
2318 if (phy->type == B43_PHYTYPE_N)
2319 filename = "ucode16_mimo";
2320 else if (phy->type == B43_PHYTYPE_LP)
2321 filename = "ucode16_lp";
2322 break;
2323 case 15:
759b973b 2324 filename = "ucode15";
a60f99f7
RM		 2325 break;
2326 case 14:
2327 filename = "ucode14";
2328 break;
2329 case 13:
2330 filename = "ucode13";
2331 break;
2332 case 11 ... 12:
2333 filename = "ucode11";
2334 break;
2335 case 5 ... 10:
2336 filename = "ucode5";
2337 break;
6ff1e5cf 2338 }
a60f99f7
RM		 2339 if (!filename)
2340 goto err_no_ucode;
5e20a4b5 2341 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
61cb5dd6
MB		 2342 if (err)
2343 goto err_load;
2344
2345 /* Get PCM code */
2346 if ((rev >= 5) && (rev <= 10))
2347 filename = "pcm5";
2348 else if (rev >= 11)
2349 filename = NULL;
2350 else
2351 goto err_no_pcm;
3db1cd5c 2352 fw->pcm_request_failed = false;
5e20a4b5 2353 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
68217832
MB		 2354 if (err == -ENOENT) {
2355 /* We did not find a PCM file? Not fatal, but
2356 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2357 fw->pcm_request_failed = true;
68217832 2358 } else if (err)
61cb5dd6
MB		 2359 goto err_load;
2360
2361 /* Get initvals */
a60f99f7 2362 filename = NULL;
61cb5dd6 2363 switch (dev->phy.type) {
61cb5dd6 2364 case B43_PHYTYPE_G:
a60f99f7 2365 if (rev == 13)
e9304882 2366 filename = "b0g0initvals13";
a60f99f7
RM		 2367 else if (rev >= 5 && rev <= 10)
2368 filename = "b0g0initvals5";
61cb5dd6
MB		 2369 break;
2370 case B43_PHYTYPE_N:
a60f99f7
RM		 2371 if (rev == 30)
2372 filename = "n16initvals30";
2373 else if (rev == 28 || rev == 25)
2374 filename = "n0initvals25";
2375 else if (rev == 24)
2376 filename = "n0initvals24";
2377 else if (rev == 23)
2378 filename = "n0initvals16"; /* What about n0initvals22? */
2379 else if (rev >= 16 && rev <= 18)
e41596a1 2380 filename = "n0initvals16";
a60f99f7 2381 else if (rev >= 11 && rev <= 12)
61cb5dd6 2382 filename = "n0initvals11";
61cb5dd6 2383 break;
759b973b 2384 case B43_PHYTYPE_LP:
a60f99f7
RM		 2385 if (rev >= 16 && rev <= 18)
2386 filename = "lp0initvals16";
2387 else if (rev == 15)
2388 filename = "lp0initvals15";
759b973b
GS		 2389 else if (rev == 14)
2390 filename = "lp0initvals14";
a60f99f7
RM		 2391 else if (rev == 13)
2392 filename = "lp0initvals13";
759b973b 2393 break;
8b9bda75
RM		 2394 case B43_PHYTYPE_HT:
2395 if (rev == 29)
2396 filename = "ht0initvals29";
a60f99f7
RM		 2397 else if (rev == 26)
2398 filename = "ht0initvals26";
8b9bda75
RM		 2399 break;
2400 case B43_PHYTYPE_LCN:
2401 if (rev == 24)
2402 filename = "lcn0initvals24";
8b9bda75 2403 break;
a60f99f7
RM		 2404 case B43_PHYTYPE_LCN40:
2405 if (rev == 33)
2406 filename = "lcn400initvals33";
2407 break;
2408 case B43_PHYTYPE_AC:
2409 if (rev == 42)
2410 filename = "ac1initvals42";
15be8e89
RM		 2411 else if (rev == 40)
2412 filename = "ac0initvals40";
a60f99f7 2413 break;
e4d6b795 2414 }
a60f99f7
RM		 2415 if (!filename)
2416 goto err_no_initvals;
5e20a4b5 2417 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
61cb5dd6
MB		 2418 if (err)
2419 goto err_load;
2420
2421 /* Get bandswitch initvals */
a60f99f7 2422 filename = NULL;
61cb5dd6 2423 switch (dev->phy.type) {
61cb5dd6 2424 case B43_PHYTYPE_G:
a60f99f7
RM		 2425 if (rev == 13)
2426 filename = "b0g0bsinitvals13";
2427 else if (rev >= 5 && rev <= 10)
61cb5dd6 2428 filename = "b0g0bsinitvals5";
61cb5dd6
MB		 2429 break;
2430 case B43_PHYTYPE_N:
a60f99f7
RM		 2431 if (rev == 30)
2432 filename = "n16bsinitvals30";
2433 else if (rev == 28 || rev == 25)
2434 filename = "n0bsinitvals25";
2435 else if (rev == 24)
2436 filename = "n0bsinitvals24";
2437 else if (rev == 23)
2438 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2439 else if (rev >= 16 && rev <= 18)
e41596a1 2440 filename = "n0bsinitvals16";
a60f99f7 2441 else if (rev >= 11 && rev <= 12)
61cb5dd6 2442 filename = "n0bsinitvals11";
61cb5dd6 2443 break;
759b973b 2444 case B43_PHYTYPE_LP:
a60f99f7
RM		 2445 if (rev >= 16 && rev <= 18)
2446 filename = "lp0bsinitvals16";
2447 else if (rev == 15)
2448 filename = "lp0bsinitvals15";
759b973b
GS		 2449 else if (rev == 14)
2450 filename = "lp0bsinitvals14";
a60f99f7
RM		 2451 else if (rev == 13)
2452 filename = "lp0bsinitvals13";
759b973b 2453 break;
8b9bda75
RM		 2454 case B43_PHYTYPE_HT:
2455 if (rev == 29)
2456 filename = "ht0bsinitvals29";
a60f99f7
RM		 2457 else if (rev == 26)
2458 filename = "ht0bsinitvals26";
8b9bda75
RM		 2459 break;
2460 case B43_PHYTYPE_LCN:
2461 if (rev == 24)
2462 filename = "lcn0bsinitvals24";
8b9bda75 2463 break;
a60f99f7
RM		 2464 case B43_PHYTYPE_LCN40:
2465 if (rev == 33)
2466 filename = "lcn400bsinitvals33";
2467 break;
2468 case B43_PHYTYPE_AC:
2469 if (rev == 42)
2470 filename = "ac1bsinitvals42";
15be8e89
RM		 2471 else if (rev == 40)
2472 filename = "ac0bsinitvals40";
a60f99f7 2473 break;
e4d6b795 2474 }
a60f99f7
RM		 2475 if (!filename)
2476 goto err_no_initvals;
5e20a4b5 2477 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
61cb5dd6
MB		 2478 if (err)
2479 goto err_load;
e4d6b795 2480
097b0e1b
JB		 2481 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2482
e4d6b795
MB		 2483 return 0;
2484
e4d6b795 2485err_no_ucode:
1a9f5093
MB		 2486 err = ctx->fatal_failure = -EOPNOTSUPP;
2487 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2488 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2489 goto error;
2490
2491err_no_pcm:
1a9f5093
MB		 2492 err = ctx->fatal_failure = -EOPNOTSUPP;
2493 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2494 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2495 goto error;
2496
2497err_no_initvals:
1a9f5093
MB		 2498 err = ctx->fatal_failure = -EOPNOTSUPP;
2499 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2500 "is required for your device (wl-core rev %u)\n", rev);
2501 goto error;
2502
2503err_load:
2504 /* We failed to load this firmware image. The error message
2505 * already is in ctx->errors. Return and let our caller decide
2506 * what to do. */
e4d6b795
MB		 2507 goto error;
2508
2509error:
2510 b43_release_firmware(dev);
2511 return err;
2512}
2513
6b6fa586
LF		 2514static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2515static void b43_one_core_detach(struct b43_bus_dev *dev);
09164043 2516static int b43_rng_init(struct b43_wl *wl);
6b6fa586
LF		 2517
2518static void b43_request_firmware(struct work_struct *work)
1a9f5093 2519{
6b6fa586
LF		 2520 struct b43_wl *wl = container_of(work,
2521 struct b43_wl, firmware_load);
2522 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2523 struct b43_request_fw_context *ctx;
2524 unsigned int i;
2525 int err;
2526 const char *errmsg;
2527
2528 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2529 if (!ctx)
6b6fa586 2530 return;
1a9f5093
MB		 2531 ctx->dev = dev;
2532
2533 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2534 err = b43_try_request_fw(ctx);
2535 if (!err)
6b6fa586
LF		 2536 goto start_ieee80211; /* Successfully loaded it. */
2537 /* Was fw version known? */
2538 if (ctx->fatal_failure)
1a9f5093
MB		 2539 goto out;
2540
6b6fa586 2541 /* proprietary fw not found, try open source */
1a9f5093
MB		 2542 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2543 err = b43_try_request_fw(ctx);
2544 if (!err)
6b6fa586
LF		 2545 goto start_ieee80211; /* Successfully loaded it. */
2546 if(ctx->fatal_failure)
1a9f5093
MB		 2547 goto out;
2548
2549 /* Could not find a usable firmware. Print the errors. */
2550 for (i = 0; i < B43_NR_FWTYPES; i++) {
2551 errmsg = ctx->errors[i];
2552 if (strlen(errmsg))
e0e29b68 2553 b43err(dev->wl, "%s", errmsg);
1a9f5093
MB		 2554 }
2555 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2556 goto out;
2557
2558start_ieee80211:
097b0e1b
JB		 2559 wl->hw->queues = B43_QOS_QUEUE_NUM;
2560 if (!modparam_qos || dev->fw.opensource)
2561 wl->hw->queues = 1;
2562
6b6fa586
LF		 2563 err = ieee80211_register_hw(wl->hw);
2564 if (err)
2565 goto err_one_core_detach;
e64add27 2566 wl->hw_registred = true;
6b6fa586 2567 b43_leds_register(wl->current_dev);
09164043
LF		 2568
2569 /* Register HW RNG driver */
2570 b43_rng_init(wl);
2571
6b6fa586
LF		 2572 goto out;
2573
2574err_one_core_detach:
2575 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2576
2577out:
2578 kfree(ctx);
1a9f5093
MB		 2579}
2580
e4d6b795
MB		 2581static int b43_upload_microcode(struct b43_wldev *dev)
2582{
652caa5b 2583 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2584 const size_t hdr_len = sizeof(struct b43_fw_header);
2585 const __be32 *data;
2586 unsigned int i, len;
2587 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2588 u32 tmp, macctl;
e4d6b795
MB		 2589 int err = 0;
2590
1f7d87b0
MB		 2591 /* Jump the microcode PSM to offset 0 */
2592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2593 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2594 macctl |= B43_MACCTL_PSM_JMP0;
2595 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2596 /* Zero out all microcode PSM registers and shared memory. */
2597 for (i = 0; i < 64; i++)
2598 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2599 for (i = 0; i < 4096; i += 2)
2600 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2601
e4d6b795 2602 /* Upload Microcode. */
61cb5dd6
MB		 2603 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2604 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2605 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2606 for (i = 0; i < len; i++) {
2607 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2608 udelay(10);
2609 }
2610
61cb5dd6 2611 if (dev->fw.pcm.data) {
e4d6b795 2612 /* Upload PCM data. */
61cb5dd6
MB		 2613 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2614 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2615 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2616 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2617 /* No need for autoinc bit in SHM_HW */
2618 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2619 for (i = 0; i < len; i++) {
2620 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2621 udelay(10);
2622 }
2623 }
2624
2625 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2626
2627 /* Start the microcode PSM */
5056635c
RM		 2628 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2629 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2630
2631 /* Wait for the microcode to load and respond */
2632 i = 0;
2633 while (1) {
2634 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2635 if (tmp == B43_IRQ_MAC_SUSPENDED)
2636 break;
2637 i++;
1f7d87b0 2638 if (i >= 20) {
e4d6b795 2639 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2640 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2641 err = -ENODEV;
1f7d87b0
MB		 2642 goto error;
2643 }
e175e996 2644 msleep(50);
e4d6b795
MB		 2645 }
2646 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2647
2648 /* Get and check the revisions. */
2649 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2650 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2651 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2652 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2653
2654 if (fwrev <= 0x128) {
2655 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2656 "binary drivers older than version 4.x is unsupported. "
2657 "You must upgrade your firmware files.\n");
eb189d8b 2658 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2659 err = -EOPNOTSUPP;
1f7d87b0 2660 goto error;
e4d6b795 2661 }
e4d6b795
MB		 2662 dev->fw.rev = fwrev;
2663 dev->fw.patch = fwpatch;
5d852905
RM		 2664 if (dev->fw.rev >= 598)
2665 dev->fw.hdr_format = B43_FW_HDR_598;
2666 else if (dev->fw.rev >= 410)
efe0249b
RM		 2667 dev->fw.hdr_format = B43_FW_HDR_410;
2668 else
2669 dev->fw.hdr_format = B43_FW_HDR_351;
097b0e1b 2670 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
e48b0eeb 2671
097b0e1b 2672 dev->qos_enabled = dev->wl->hw->queues > 1;
403a3a13 2673 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2674 dev->hwcrypto_enabled = true;
403a3a13 2675
e48b0eeb 2676 if (dev->fw.opensource) {
403a3a13
MB		 2677 u16 fwcapa;
2678
e48b0eeb
MB		 2679 /* Patchlevel info is encoded in the "time" field. */
2680 dev->fw.patch = fwtime;
403a3a13
MB		 2681 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2682 dev->fw.rev, dev->fw.patch);
2683
2684 fwcapa = b43_fwcapa_read(dev);
2685 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2686 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2687 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2688 dev->hwcrypto_enabled = false;
403a3a13 2689 }
097b0e1b
JB		 2690 /* adding QoS support should use an offline discovery mechanism */
2691 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
e48b0eeb
MB		 2692 } else {
2693 b43info(dev->wl, "Loading firmware version %u.%u "
2694 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2695 fwrev, fwpatch,
2696 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2697 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2698 if (dev->fw.pcm_request_failed) {
2699 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2700 "Hardware accelerated cryptography is disabled.\n");
2701 b43_print_fw_helptext(dev->wl, 0);
2702 }
e48b0eeb 2703 }
e4d6b795 2704
652caa5b
JL		 2705 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2706 dev->fw.rev, dev->fw.patch);
21d889d4 2707 wiphy->hw_version = dev->dev->core_id;
652caa5b 2708
efe0249b 2709 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2710 /* We're over the deadline, but we keep support for old fw
2711 * until it turns out to be in major conflict with something new. */
eb189d8b 2712 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2713 "Support for old firmware will be removed soon "
2714 "(official deadline was July 2008).\n");
eb189d8b
MB		 2715 b43_print_fw_helptext(dev->wl, 0);
2716 }
2717
1f7d87b0
MB		 2718 return 0;
2719
2720error:
5056635c
RM		 2721 /* Stop the microcode PSM. */
2722 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2723 B43_MACCTL_PSM_JMP0);
1f7d87b0 2724
e4d6b795
MB		 2725 return err;
2726}
2727
2728static int b43_write_initvals(struct b43_wldev *dev,
2729 const struct b43_iv *ivals,
2730 size_t count,
2731 size_t array_size)
2732{
2733 const struct b43_iv *iv;
2734 u16 offset;
2735 size_t i;
2736 bool bit32;
2737
2738 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2739 iv = ivals;
2740 for (i = 0; i < count; i++) {
2741 if (array_size < sizeof(iv->offset_size))
2742 goto err_format;
2743 array_size -= sizeof(iv->offset_size);
2744 offset = be16_to_cpu(iv->offset_size);
2745 bit32 = !!(offset & B43_IV_32BIT);
2746 offset &= B43_IV_OFFSET_MASK;
2747 if (offset >= 0x1000)
2748 goto err_format;
2749 if (bit32) {
2750 u32 value;
2751
2752 if (array_size < sizeof(iv->data.d32))
2753 goto err_format;
2754 array_size -= sizeof(iv->data.d32);
2755
533dd1b0 2756 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2757 b43_write32(dev, offset, value);
2758
2759 iv = (const struct b43_iv *)((const uint8_t *)iv +
2760 sizeof(__be16) +
2761 sizeof(__be32));
2762 } else {
2763 u16 value;
2764
2765 if (array_size < sizeof(iv->data.d16))
2766 goto err_format;
2767 array_size -= sizeof(iv->data.d16);
2768
2769 value = be16_to_cpu(iv->data.d16);
2770 b43_write16(dev, offset, value);
2771
2772 iv = (const struct b43_iv *)((const uint8_t *)iv +
2773 sizeof(__be16) +
2774 sizeof(__be16));
2775 }
2776 }
2777 if (array_size)
2778 goto err_format;
2779
2780 return 0;
2781
2782err_format:
2783 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2784 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2785
2786 return -EPROTO;
2787}
2788
2789static int b43_upload_initvals(struct b43_wldev *dev)
2790{
2791 const size_t hdr_len = sizeof(struct b43_fw_header);
2792 const struct b43_fw_header *hdr;
2793 struct b43_firmware *fw = &dev->fw;
2794 const struct b43_iv *ivals;
2795 size_t count;
e4d6b795 2796
61cb5dd6
MB		 2797 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2798 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795 2799 count = be32_to_cpu(hdr->size);
0f68423f 2800 return b43_write_initvals(dev, ivals, count,
61cb5dd6 2801 fw->initvals.data->size - hdr_len);
0f68423f 2802}
e4d6b795 2803
0f68423f
RM		 2804static int b43_upload_initvals_band(struct b43_wldev *dev)
2805{
2806 const size_t hdr_len = sizeof(struct b43_fw_header);
2807 const struct b43_fw_header *hdr;
2808 struct b43_firmware *fw = &dev->fw;
2809 const struct b43_iv *ivals;
2810 size_t count;
2811
2812 if (!fw->initvals_band.data)
2813 return 0;
2814
2815 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2816 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2817 count = be32_to_cpu(hdr->size);
2818 return b43_write_initvals(dev, ivals, count,
2819 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2820}
2821
2822/* Initialize the GPIOs
2823 * http://bcm-specs.sipsolutions.net/GPIO
2824 */
bd7c8a59
RM		 2825
2826#ifdef CONFIG_B43_SSB
c4a2a081 2827static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2828{
d48ae5c8 2829 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2830
2831#ifdef CONFIG_SSB_DRIVER_PCICORE
2832 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2833#else
2834 return bus->chipco.dev;
2835#endif
2836}
bd7c8a59 2837#endif
c4a2a081 2838
e4d6b795
MB		 2839static int b43_gpio_init(struct b43_wldev *dev)
2840{
bd7c8a59 2841#ifdef CONFIG_B43_SSB
c4a2a081 2842 struct ssb_device *gpiodev;
bd7c8a59 2843#endif
e4d6b795
MB		 2844 u32 mask, set;
2845
5056635c
RM		 2846 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2847 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2848
2849 mask = 0x0000001F;
2850 set = 0x0000000F;
c244e08c 2851 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2852 mask |= 0x0060;
2853 set |= 0x0060;
828afd26
RM		 2854 } else if (dev->dev->chip_id == 0x5354) {
2855 /* Don't allow overtaking buttons GPIOs */
2856 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
e4d6b795 2857 }
828afd26 2858
e4d6b795
MB		 2859 if (0 /* FIXME: conditional unknown */ ) {
2860 b43_write16(dev, B43_MMIO_GPIO_MASK,
2861 b43_read16(dev, B43_MMIO_GPIO_MASK)
2862 | 0x0100);
828afd26
RM		 2863 /* BT Coexistance Input */
2864 mask |= 0x0080;
2865 set |= 0x0080;
2866 /* BT Coexistance Out */
2867 mask |= 0x0100;
2868 set |= 0x0100;
e4d6b795 2869 }
0581483a 2870 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
828afd26 2871 /* PA is controlled by gpio 9, let ucode handle it */
e4d6b795
MB		 2872 b43_write16(dev, B43_MMIO_GPIO_MASK,
2873 b43_read16(dev, B43_MMIO_GPIO_MASK)
2874 | 0x0200);
2875 mask |= 0x0200;
2876 set |= 0x0200;
2877 }
e4d6b795 2878
6cbab0d9 2879 switch (dev->dev->bus_type) {
42c9a458
RM		 2880#ifdef CONFIG_B43_BCMA
2881 case B43_BUS_BCMA:
0a64baea 2882 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
42c9a458
RM		 2883 break;
2884#endif
6cbab0d9
RM		 2885#ifdef CONFIG_B43_SSB
2886 case B43_BUS_SSB:
2887 gpiodev = b43_ssb_gpio_dev(dev);
2888 if (gpiodev)
2889 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2890 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
828afd26 2891 & ~mask) | set);
6cbab0d9
RM		 2892 break;
2893#endif
2894 }
e4d6b795
MB		 2895
2896 return 0;
2897}
2898
2899/* Turn off all GPIO stuff. Call this on module unload, for example. */
2900static void b43_gpio_cleanup(struct b43_wldev *dev)
2901{
bd7c8a59 2902#ifdef CONFIG_B43_SSB
c4a2a081 2903 struct ssb_device *gpiodev;
bd7c8a59 2904#endif
e4d6b795 2905
6cbab0d9 2906 switch (dev->dev->bus_type) {
42c9a458
RM		 2907#ifdef CONFIG_B43_BCMA
2908 case B43_BUS_BCMA:
0a64baea 2909 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
42c9a458
RM		 2910 break;
2911#endif
6cbab0d9
RM		 2912#ifdef CONFIG_B43_SSB
2913 case B43_BUS_SSB:
2914 gpiodev = b43_ssb_gpio_dev(dev);
2915 if (gpiodev)
2916 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2917 break;
2918#endif
2919 }
e4d6b795
MB		 2920}
2921
2922/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2923void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2924{
923fd703
MB		 2925 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2926 u16 fwstate;
2927
2928 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2929 B43_SHM_SH_UCODESTAT);
2930 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2931 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2932 b43err(dev->wl, "b43_mac_enable(): The firmware "
2933 "should be suspended, but current state is %u\n",
2934 fwstate);
2935 }
2936 }
2937
e4d6b795
MB		 2938 dev->mac_suspended--;
2939 B43_WARN_ON(dev->mac_suspended < 0);
2940 if (dev->mac_suspended == 0) {
5056635c 2941 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2942 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2943 B43_IRQ_MAC_SUSPENDED);
2944 /* Commit writes */
2945 b43_read32(dev, B43_MMIO_MACCTL);
2946 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2947 b43_power_saving_ctl_bits(dev, 0);
2948 }
2949}
2950
2951/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2952void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2953{
2954 int i;
2955 u32 tmp;
2956
05b64b36 2957 might_sleep();
e4d6b795 2958 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2959
e4d6b795
MB		 2960 if (dev->mac_suspended == 0) {
2961 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2962 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2963 /* force pci to flush the write */
2964 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2965 for (i = 35; i; i--) {
2966 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2967 if (tmp & B43_IRQ_MAC_SUSPENDED)
2968 goto out;
2969 udelay(10);
2970 }
2971 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2972 for (i = 40; i; i--) {
e4d6b795
MB		 2973 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2974 if (tmp & B43_IRQ_MAC_SUSPENDED)
2975 goto out;
05b64b36 2976 msleep(1);
e4d6b795
MB		 2977 }
2978 b43err(dev->wl, "MAC suspend failed\n");
2979 }
05b64b36 2980out:
e4d6b795
MB		 2981 dev->mac_suspended++;
2982}
2983
858a1652
RM		 2984/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2985void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2986{
6cbab0d9
RM		 2987 u32 tmp;
2988
2989 switch (dev->dev->bus_type) {
42c9a458
RM		 2990#ifdef CONFIG_B43_BCMA
2991 case B43_BUS_BCMA:
36677874 2992 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2993 if (on)
2994 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2995 else
2996 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2997 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2998 break;
2999#endif
6cbab0d9
RM		 3000#ifdef CONFIG_B43_SSB
3001 case B43_BUS_SSB:
3002 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3003 if (on)
3004 tmp |= B43_TMSLOW_MACPHYCLKEN;
3005 else
3006 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
3007 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3008 break;
3009#endif
3010 }
858a1652
RM		 3011}
3012
c2cb2c4c
RM		 3013/* brcms_b_switch_macfreq */
3014void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3015{
3016 u16 chip_id = dev->dev->chip_id;
3017
bc944506
RM		 3018 if (chip_id == BCMA_CHIP_ID_BCM4331) {
3019 switch (spurmode) {
3020 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
3021 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3022 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3023 break;
3024 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
3025 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3026 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3027 break;
3028 default: /* 160 Mhz: 2^26/160 = 0x66666 */
3029 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3030 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3031 break;
3032 }
3033 } else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
a67d19d4 3034 chip_id == BCMA_CHIP_ID_BCM43217 ||
c2cb2c4c
RM		 3035 chip_id == BCMA_CHIP_ID_BCM43222 ||
3036 chip_id == BCMA_CHIP_ID_BCM43224 ||
3037 chip_id == BCMA_CHIP_ID_BCM43225 ||
3038 chip_id == BCMA_CHIP_ID_BCM43227 ||
3039 chip_id == BCMA_CHIP_ID_BCM43228) {
3040 switch (spurmode) {
3041 case 2: /* 126 Mhz */
3042 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3043 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3044 break;
3045 case 1: /* 123 Mhz */
3046 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3047 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3048 break;
3049 default: /* 120 Mhz */
3050 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3051 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3052 break;
3053 }
3054 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3055 switch (spurmode) {
3056 case 1: /* 82 Mhz */
3057 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3058 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3059 break;
3060 default: /* 80 Mhz */
3061 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3062 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3063 break;
3064 }
3065 }
3066}
3067
e4d6b795
MB		 3068static void b43_adjust_opmode(struct b43_wldev *dev)
3069{
3070 struct b43_wl *wl = dev->wl;
3071 u32 ctl;
3072 u16 cfp_pretbtt;
3073
3074 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3075 /* Reset status to STA infrastructure mode. */
3076 ctl &= ~B43_MACCTL_AP;
3077 ctl &= ~B43_MACCTL_KEEP_CTL;
3078 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3079 ctl &= ~B43_MACCTL_KEEP_BAD;
3080 ctl &= ~B43_MACCTL_PROMISC;
4150c572 3081 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 3082 ctl |= B43_MACCTL_INFRA;
3083
05c914fe
JB		 3084 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3085 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 3086 ctl |= B43_MACCTL_AP;
05c914fe 3087 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 3088 ctl &= ~B43_MACCTL_INFRA;
3089
3090 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 3091 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 3092 if (wl->filter_flags & FIF_FCSFAIL)
3093 ctl |= B43_MACCTL_KEEP_BAD;
3094 if (wl->filter_flags & FIF_PLCPFAIL)
3095 ctl |= B43_MACCTL_KEEP_BADPLCP;
3096 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 3097 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 3098 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3099 ctl |= B43_MACCTL_BEACPROMISC;
3100
e4d6b795
MB		 3101 /* Workaround: On old hardware the HW-MAC-address-filter
3102 * doesn't work properly, so always run promisc in filter
3103 * it in software. */
21d889d4 3104 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 3105 ctl |= B43_MACCTL_PROMISC;
3106
3107 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3108
3109 cfp_pretbtt = 2;
3110 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 3111 if (dev->dev->chip_id == 0x4306 &&
3112 dev->dev->chip_rev == 3)
e4d6b795
MB		 3113 cfp_pretbtt = 100;
3114 else
3115 cfp_pretbtt = 50;
3116 }
3117 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 3118
3119 /* FIXME: We don't currently implement the PMQ mechanism,
3120 * so always disable it. If we want to implement PMQ,
3121 * we need to enable it here (clear DISCPMQ) in AP mode.
3122 */
5056635c
RM		 3123 if (0 /* ctl & B43_MACCTL_AP */)
3124 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3125 else
3126 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 3127}
3128
3129static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3130{
3131 u16 offset;
3132
3133 if (is_ofdm) {
3134 offset = 0x480;
3135 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3136 } else {
3137 offset = 0x4C0;
3138 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3139 }
3140 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3141 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3142}
3143
3144static void b43_rate_memory_init(struct b43_wldev *dev)
3145{
3146 switch (dev->phy.type) {
3147 case B43_PHYTYPE_A:
3148 case B43_PHYTYPE_G:
53a6e234 3149 case B43_PHYTYPE_N:
9d86a2d5 3150 case B43_PHYTYPE_LP:
6a461c23 3151 case B43_PHYTYPE_HT:
0b4ff45d 3152 case B43_PHYTYPE_LCN:
e4d6b795
MB		 3153 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3154 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3155 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3156 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3157 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3158 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3159 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3160 if (dev->phy.type == B43_PHYTYPE_A)
3161 break;
3162 /* fallthrough */
3163 case B43_PHYTYPE_B:
3164 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3165 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3166 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3167 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3168 break;
3169 default:
3170 B43_WARN_ON(1);
3171 }
3172}
3173
5042c507
MB		 3174/* Set the default values for the PHY TX Control Words. */
3175static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3176{
3177 u16 ctl = 0;
3178
3179 ctl |= B43_TXH_PHY_ENC_CCK;
3180 ctl |= B43_TXH_PHY_ANT01AUTO;
3181 ctl |= B43_TXH_PHY_TXPWR;
3182
3183 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3184 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3185 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3186}
3187
e4d6b795
MB		 3188/* Set the TX-Antenna for management frames sent by firmware. */
3189static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3190{
5042c507 3191 u16 ant;
e4d6b795
MB		 3192 u16 tmp;
3193
5042c507 3194 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3195
e4d6b795
MB		 3196 /* For ACK/CTS */
3197 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3198 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3199 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3200 /* For Probe Resposes */
3201 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3202 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3203 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3204}
3205
3206/* This is the opposite of b43_chip_init() */
3207static void b43_chip_exit(struct b43_wldev *dev)
3208{
fb11137a 3209 b43_phy_exit(dev);
e4d6b795
MB		 3210 b43_gpio_cleanup(dev);
3211 /* firmware is released later */
3212}
3213
3214/* Initialize the chip
3215 * http://bcm-specs.sipsolutions.net/ChipInit
3216 */
3217static int b43_chip_init(struct b43_wldev *dev)
3218{
3219 struct b43_phy *phy = &dev->phy;
ef1a628d 3220 int err;
858a1652 3221 u32 macctl;
e4d6b795
MB		 3222 u16 value16;
3223
1f7d87b0
MB		 3224 /* Initialize the MAC control */
3225 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3226 if (dev->phy.gmode)
3227 macctl |= B43_MACCTL_GMODE;
3228 macctl |= B43_MACCTL_INFRA;
3229 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3230
e4d6b795
MB		 3231 err = b43_upload_microcode(dev);
3232 if (err)
3233 goto out; /* firmware is released later */
3234
3235 err = b43_gpio_init(dev);
3236 if (err)
3237 goto out; /* firmware is released later */
21954c36 3238
e4d6b795
MB		 3239 err = b43_upload_initvals(dev);
3240 if (err)
1a8d1227 3241 goto err_gpio_clean;
e4d6b795 3242
0f68423f
RM		 3243 err = b43_upload_initvals_band(dev);
3244 if (err)
3245 goto err_gpio_clean;
3246
0b7dcd96
MB		 3247 /* Turn the Analog on and initialize the PHY. */
3248 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3249 err = b43_phy_init(dev);
3250 if (err)
ef1a628d 3251 goto err_gpio_clean;
e4d6b795 3252
ef1a628d
MB		 3253 /* Disable Interference Mitigation. */
3254 if (phy->ops->interf_mitigation)
3255 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3256
ef1a628d
MB		 3257 /* Select the antennae */
3258 if (phy->ops->set_rx_antenna)
3259 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3260 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3261
3262 if (phy->type == B43_PHYTYPE_B) {
3263 value16 = b43_read16(dev, 0x005E);
3264 value16 |= 0x0004;
3265 b43_write16(dev, 0x005E, value16);
3266 }
3267 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3268 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3269 b43_write32(dev, 0x010C, 0x01000000);
3270
5056635c
RM		 3271 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3272 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3273
e4d6b795
MB		 3274 /* Probe Response Timeout value */
3275 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
5c1da23b 3276 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
e4d6b795
MB		 3277
3278 /* Initially set the wireless operation mode. */
3279 b43_adjust_opmode(dev);
3280
21d889d4 3281 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3282 b43_write16(dev, 0x060E, 0x0000);
3283 b43_write16(dev, 0x0610, 0x8000);
3284 b43_write16(dev, 0x0604, 0x0000);
3285 b43_write16(dev, 0x0606, 0x0200);
3286 } else {
3287 b43_write32(dev, 0x0188, 0x80000000);
3288 b43_write32(dev, 0x018C, 0x02000000);
3289 }
3290 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
73b82bf0 3291 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
e4d6b795
MB		 3292 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3293 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3294 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3295 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3296 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3297
858a1652 3298 b43_mac_phy_clock_set(dev, true);
e4d6b795 3299
6cbab0d9 3300 switch (dev->dev->bus_type) {
42c9a458
RM		 3301#ifdef CONFIG_B43_BCMA
3302 case B43_BUS_BCMA:
3303 /* FIXME: 0xE74 is quite common, but should be read from CC */
3304 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3305 break;
3306#endif
6cbab0d9
RM		 3307#ifdef CONFIG_B43_SSB
3308 case B43_BUS_SSB:
3309 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3310 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3311 break;
3312#endif
3313 }
e4d6b795
MB		 3314
3315 err = 0;
3316 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3317out:
e4d6b795
MB		 3318 return err;
3319
1a8d1227 3320err_gpio_clean:
e4d6b795 3321 b43_gpio_cleanup(dev);
21954c36 3322 return err;
e4d6b795
MB		 3323}
3324
e4d6b795
MB		 3325static void b43_periodic_every60sec(struct b43_wldev *dev)
3326{
ef1a628d 3327 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3328
ef1a628d
MB		 3329 if (ops->pwork_60sec)
3330 ops->pwork_60sec(dev);
18c8adeb
MB		 3331
3332 /* Force check the TX power emission now. */
3333 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3334}
3335
3336static void b43_periodic_every30sec(struct b43_wldev *dev)
3337{
3338 /* Update device statistics. */
3339 b43_calculate_link_quality(dev);
3340}
3341
3342static void b43_periodic_every15sec(struct b43_wldev *dev)
3343{
3344 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3345 u16 wdr;
3346
3347 if (dev->fw.opensource) {
3348 /* Check if the firmware is still alive.
3349 * It will reset the watchdog counter to 0 in its idle loop. */
3350 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3351 if (unlikely(wdr)) {
3352 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3353 b43_controller_restart(dev, "Firmware watchdog");
3354 return;
3355 } else {
3356 b43_shm_write16(dev, B43_SHM_SCRATCH,
3357 B43_WATCHDOG_REG, 1);
3358 }
3359 }
e4d6b795 3360
ef1a628d
MB		 3361 if (phy->ops->pwork_15sec)
3362 phy->ops->pwork_15sec(dev);
3363
00e0b8cb
SB		 3364 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3365 wmb();
990b86f4
MB		 3366
3367#if B43_DEBUG
3368 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3369 unsigned int i;
3370
3371 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3372 dev->irq_count / 15,
3373 dev->tx_count / 15,
3374 dev->rx_count / 15);
3375 dev->irq_count = 0;
3376 dev->tx_count = 0;
3377 dev->rx_count = 0;
3378 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3379 if (dev->irq_bit_count[i]) {
3380 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3381 dev->irq_bit_count[i] / 15, i, (1 << i));
3382 dev->irq_bit_count[i] = 0;
3383 }
3384 }
3385 }
3386#endif
e4d6b795
MB		 3387}
3388
e4d6b795
MB		 3389static void do_periodic_work(struct b43_wldev *dev)
3390{
3391 unsigned int state;
3392
3393 state = dev->periodic_state;
42bb4cd5 3394 if (state % 4 == 0)
e4d6b795 3395 b43_periodic_every60sec(dev);
42bb4cd5 3396 if (state % 2 == 0)
e4d6b795 3397 b43_periodic_every30sec(dev);
42bb4cd5 3398 b43_periodic_every15sec(dev);
e4d6b795
MB		 3399}
3400
05b64b36
MB		 3401/* Periodic work locking policy:
3402 * The whole periodic work handler is protected by
3403 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3404 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3405 */
e4d6b795
MB		 3406static void b43_periodic_work_handler(struct work_struct *work)
3407{
05b64b36
MB		 3408 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3409 periodic_work.work);
3410 struct b43_wl *wl = dev->wl;
3411 unsigned long delay;
e4d6b795 3412
05b64b36 3413 mutex_lock(&wl->mutex);
e4d6b795
MB		 3414
3415 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3416 goto out;
3417 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3418 goto out_requeue;
3419
05b64b36 3420 do_periodic_work(dev);
e4d6b795 3421
e4d6b795 3422 dev->periodic_state++;
42bb4cd5 3423out_requeue:
e4d6b795
MB		 3424 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3425 delay = msecs_to_jiffies(50);
3426 else
82cd682d 3427 delay = round_jiffies_relative(HZ * 15);
42935eca 3428 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3429out:
05b64b36 3430 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3431}
3432
3433static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3434{
3435 struct delayed_work *work = &dev->periodic_work;
3436
3437 dev->periodic_state = 0;
3438 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3439 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3440}
3441
f3dd3fcc 3442/* Check if communication with the device works correctly. */
e4d6b795
MB		 3443static int b43_validate_chipaccess(struct b43_wldev *dev)
3444{
f62ae6cd 3445 u32 v, backup0, backup4;
e4d6b795 3446
f62ae6cd
MB		 3447 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3448 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3449
3450 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3451 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3452 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3453 goto error;
f3dd3fcc
MB		 3454 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3455 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3456 goto error;
3457
f62ae6cd
MB		 3458 /* Check if unaligned 32bit SHM_SHARED access works properly.
3459 * However, don't bail out on failure, because it's noncritical. */
3460 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3461 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3462 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3463 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3464 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3465 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3466 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3467 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3468 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3469 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3470 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3471 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3472
3473 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3474 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3475
21d889d4 3476 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3477 /* The 32bit register shadows the two 16bit registers
3478 * with update sideeffects. Validate this. */
3479 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3480 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3481 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3482 goto error;
3483 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3484 goto error;
3485 }
3486 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3487
3488 v = b43_read32(dev, B43_MMIO_MACCTL);
3489 v |= B43_MACCTL_GMODE;
3490 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3491 goto error;
3492
3493 return 0;
f3dd3fcc 3494error:
e4d6b795
MB		 3495 b43err(dev->wl, "Failed to validate the chipaccess\n");
3496 return -ENODEV;
3497}
3498
3499static void b43_security_init(struct b43_wldev *dev)
3500{
e4d6b795
MB		 3501 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3502 /* KTP is a word address, but we address SHM bytewise.
3503 * So multiply by two.
3504 */
3505 dev->ktp *= 2;
66d2d089
MB		 3506 /* Number of RCMTA address slots */
3507 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3508 /* Clear the key memory. */
e4d6b795
MB		 3509 b43_clear_keys(dev);
3510}
3511
616de35d 3512#ifdef CONFIG_B43_HWRNG
99da185a 3513static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3514{
3515 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3516 struct b43_wldev *dev;
3517 int count = -ENODEV;
e4d6b795 3518
a78b3bb2
MB		 3519 mutex_lock(&wl->mutex);
3520 dev = wl->current_dev;
3521 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3522 *data = b43_read16(dev, B43_MMIO_RNG);
3523 count = sizeof(u16);
3524 }
3525 mutex_unlock(&wl->mutex);
e4d6b795 3526
a78b3bb2 3527 return count;
e4d6b795 3528}
616de35d 3529#endif /* CONFIG_B43_HWRNG */
e4d6b795 3530
b844eba2 3531static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3532{
616de35d 3533#ifdef CONFIG_B43_HWRNG
e4d6b795 3534 if (wl->rng_initialized)
b844eba2 3535 hwrng_unregister(&wl->rng);
616de35d 3536#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3537}
3538
3539static int b43_rng_init(struct b43_wl *wl)
3540{
616de35d 3541 int err = 0;
e4d6b795 3542
616de35d 3543#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3544 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3545 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3546 wl->rng.name = wl->rng_name;
3547 wl->rng.data_read = b43_rng_read;
3548 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3549 wl->rng_initialized = true;
e4d6b795
MB		 3550 err = hwrng_register(&wl->rng);
3551 if (err) {
3db1cd5c 3552 wl->rng_initialized = false;
e4d6b795
MB		 3553 b43err(wl, "Failed to register the random "
3554 "number generator (%d)\n", err);
3555 }
616de35d 3556#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3557
3558 return err;
3559}
3560
f5d40eed 3561static void b43_tx_work(struct work_struct *work)
e4d6b795 3562{
f5d40eed
MB		 3563 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3564 struct b43_wldev *dev;
3565 struct sk_buff *skb;
bad69194 3566 int queue_num;
f5d40eed 3567 int err = 0;
e4d6b795 3568
f5d40eed
MB		 3569 mutex_lock(&wl->mutex);
3570 dev = wl->current_dev;
3571 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3572 mutex_unlock(&wl->mutex);
3573 return;
5100d5ac 3574 }
21a75d77 3575
bad69194 3576 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3577 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3578 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3579 if (b43_using_pio_transfers(dev))
3580 err = b43_pio_tx(dev, skb);
3581 else
3582 err = b43_dma_tx(dev, skb);
3583 if (err == -ENOSPC) {
3584 wl->tx_queue_stopped[queue_num] = 1;
3585 ieee80211_stop_queue(wl->hw, queue_num);
3586 skb_queue_head(&wl->tx_queue[queue_num], skb);
3587 break;
3588 }
3589 if (unlikely(err))
78f18df4 3590 ieee80211_free_txskb(wl->hw, skb);
bad69194 3591 err = 0;
3592 }
21a75d77 3593
bad69194 3594 if (!err)
3595 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3596 }
3597
990b86f4
MB		 3598#if B43_DEBUG
3599 dev->tx_count++;
3600#endif
f5d40eed
MB		 3601 mutex_unlock(&wl->mutex);
3602}
21a75d77 3603
7bb45683 3604static void b43_op_tx(struct ieee80211_hw *hw,
36323f81
TH		 3605 struct ieee80211_tx_control *control,
3606 struct sk_buff *skb)
f5d40eed
MB		 3607{
3608 struct b43_wl *wl = hw_to_b43_wl(hw);
3609
3610 if (unlikely(skb->len < 2 + 2 + 6)) {
3611 /* Too short, this can't be a valid frame. */
78f18df4 3612 ieee80211_free_txskb(hw, skb);
7bb45683 3613 return;
f5d40eed
MB		 3614 }
3615 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3616
bad69194 3617 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3618 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3619 ieee80211_queue_work(wl->hw, &wl->tx_work);
3620 } else {
3621 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3622 }
e4d6b795
MB		 3623}
3624
e6f5b934
MB		 3625static void b43_qos_params_upload(struct b43_wldev *dev,
3626 const struct ieee80211_tx_queue_params *p,
3627 u16 shm_offset)
3628{
3629 u16 params[B43_NR_QOSPARAMS];
0b57664c 3630 int bslots, tmp;
e6f5b934
MB		 3631 unsigned int i;
3632
b0544eb6
MB		 3633 if (!dev->qos_enabled)
3634 return;
3635
0b57664c 3636 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3637
3638 memset(&params, 0, sizeof(params));
3639
3640 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3641 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3642 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3643 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3644 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3645 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3646 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3647
3648 for (i = 0; i < ARRAY_SIZE(params); i++) {
3649 if (i == B43_QOSPARAM_STATUS) {
3650 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3651 shm_offset + (i * 2));
3652 /* Mark the parameters as updated. */
3653 tmp |= 0x100;
3654 b43_shm_write16(dev, B43_SHM_SHARED,
3655 shm_offset + (i * 2),
3656 tmp);
3657 } else {
3658 b43_shm_write16(dev, B43_SHM_SHARED,
3659 shm_offset + (i * 2),
3660 params[i]);
3661 }
3662 }
3663}
3664
c40c1129
MB		 3665/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3666static const u16 b43_qos_shm_offsets[] = {
3667 /* [mac80211-queue-nr] = SHM_OFFSET, */
3668 [0] = B43_QOS_VOICE,
3669 [1] = B43_QOS_VIDEO,
3670 [2] = B43_QOS_BESTEFFORT,
3671 [3] = B43_QOS_BACKGROUND,
3672};
3673
5a5f3b40
MB		 3674/* Update all QOS parameters in hardware. */
3675static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3676{
3677 struct b43_wl *wl = dev->wl;
3678 struct b43_qos_params *params;
e6f5b934
MB		 3679 unsigned int i;
3680
b0544eb6
MB		 3681 if (!dev->qos_enabled)
3682 return;
3683
c40c1129
MB		 3684 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3685 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3686
3687 b43_mac_suspend(dev);
e6f5b934
MB		 3688 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3689 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3690 b43_qos_params_upload(dev, &(params->p),
3691 b43_qos_shm_offsets[i]);
e6f5b934 3692 }
e6f5b934
MB		 3693 b43_mac_enable(dev);
3694}
3695
3696static void b43_qos_clear(struct b43_wl *wl)
3697{
3698 struct b43_qos_params *params;
3699 unsigned int i;
3700
c40c1129
MB		 3701 /* Initialize QoS parameters to sane defaults. */
3702
3703 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3704 ARRAY_SIZE(wl->qos_params));
3705
e6f5b934
MB		 3706 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3707 params = &(wl->qos_params[i]);
3708
c40c1129
MB		 3709 switch (b43_qos_shm_offsets[i]) {
3710 case B43_QOS_VOICE:
3711 params->p.txop = 0;
3712 params->p.aifs = 2;
3713 params->p.cw_min = 0x0001;
3714 params->p.cw_max = 0x0001;
3715 break;
3716 case B43_QOS_VIDEO:
3717 params->p.txop = 0;
3718 params->p.aifs = 2;
3719 params->p.cw_min = 0x0001;
3720 params->p.cw_max = 0x0001;
3721 break;
3722 case B43_QOS_BESTEFFORT:
3723 params->p.txop = 0;
3724 params->p.aifs = 3;
3725 params->p.cw_min = 0x0001;
3726 params->p.cw_max = 0x03FF;
3727 break;
3728 case B43_QOS_BACKGROUND:
3729 params->p.txop = 0;
3730 params->p.aifs = 7;
3731 params->p.cw_min = 0x0001;
3732 params->p.cw_max = 0x03FF;
3733 break;
3734 default:
3735 B43_WARN_ON(1);
3736 }
e6f5b934
MB		 3737 }
3738}
3739
3740/* Initialize the core's QOS capabilities */
3741static void b43_qos_init(struct b43_wldev *dev)
3742{
b0544eb6
MB		 3743 if (!dev->qos_enabled) {
3744 /* Disable QOS support. */
3745 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3746 b43_write16(dev, B43_MMIO_IFSCTL,
3747 b43_read16(dev, B43_MMIO_IFSCTL)
3748 & ~B43_MMIO_IFSCTL_USE_EDCF);
3749 b43dbg(dev->wl, "QoS disabled\n");
3750 return;
3751 }
3752
e6f5b934 3753 /* Upload the current QOS parameters. */
5a5f3b40 3754 b43_qos_upload_all(dev);
e6f5b934
MB		 3755
3756 /* Enable QOS support. */
3757 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3758 b43_write16(dev, B43_MMIO_IFSCTL,
3759 b43_read16(dev, B43_MMIO_IFSCTL)
3760 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3761 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3762}
3763
8a3a3c85
EP		 3764static int b43_op_conf_tx(struct ieee80211_hw *hw,
3765 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3766 const struct ieee80211_tx_queue_params *params)
e4d6b795 3767{
e6f5b934 3768 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3769 struct b43_wldev *dev;
e6f5b934 3770 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3771 int err = -ENODEV;
e6f5b934
MB		 3772
3773 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3774 /* Queue not available or don't support setting
3775 * params on this queue. Return success to not
3776 * confuse mac80211. */
3777 return 0;
3778 }
5a5f3b40
MB		 3779 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3780 ARRAY_SIZE(wl->qos_params));
e6f5b934 3781
5a5f3b40
MB		 3782 mutex_lock(&wl->mutex);
3783 dev = wl->current_dev;
3784 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3785 goto out_unlock;
e6f5b934 3786
5a5f3b40
MB		 3787 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3788 b43_mac_suspend(dev);
3789 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3790 b43_qos_shm_offsets[queue]);
3791 b43_mac_enable(dev);
3792 err = 0;
e6f5b934 3793
5a5f3b40
MB		 3794out_unlock:
3795 mutex_unlock(&wl->mutex);
3796
3797 return err;
e4d6b795
MB		 3798}
3799
40faacc4
MB		 3800static int b43_op_get_stats(struct ieee80211_hw *hw,
3801 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3802{
3803 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3804
36dbd954 3805 mutex_lock(&wl->mutex);
e4d6b795 3806 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3807 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3808
3809 return 0;
3810}
3811
37a41b4a 3812static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3813{
3814 struct b43_wl *wl = hw_to_b43_wl(hw);
3815 struct b43_wldev *dev;
3816 u64 tsf;
3817
3818 mutex_lock(&wl->mutex);
08e87a83
AF		 3819 dev = wl->current_dev;
3820
3821 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3822 b43_tsf_read(dev, &tsf);
3823 else
3824 tsf = 0;
3825
08e87a83
AF		 3826 mutex_unlock(&wl->mutex);
3827
3828 return tsf;
3829}
3830
37a41b4a
EP		 3831static void b43_op_set_tsf(struct ieee80211_hw *hw,
3832 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3833{
3834 struct b43_wl *wl = hw_to_b43_wl(hw);
3835 struct b43_wldev *dev;
3836
3837 mutex_lock(&wl->mutex);
08e87a83
AF		 3838 dev = wl->current_dev;
3839
3840 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3841 b43_tsf_write(dev, tsf);
3842
08e87a83
AF		 3843 mutex_unlock(&wl->mutex);
3844}
3845
99da185a 3846static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3847{
3848 switch (band) {
3849 case IEEE80211_BAND_5GHZ:
3850 return "5";
3851 case IEEE80211_BAND_2GHZ:
3852 return "2.4";
3853 default:
3854 break;
3855 }
3856 B43_WARN_ON(1);
3857 return "";
3858}
3859
e4d6b795 3860/* Expects wl->mutex locked */
7a8af8cf
RM		 3861static int b43_switch_band(struct b43_wldev *dev,
3862 struct ieee80211_channel *chan)
e4d6b795 3863{
7a8af8cf
RM		 3864 struct b43_phy *phy = &dev->phy;
3865 bool gmode;
3866 u32 tmp;
e4d6b795 3867
644aa4d6
RM		 3868 switch (chan->band) {
3869 case IEEE80211_BAND_5GHZ:
7a8af8cf 3870 gmode = false;
644aa4d6
RM		 3871 break;
3872 case IEEE80211_BAND_2GHZ:
7a8af8cf 3873 gmode = true;
644aa4d6
RM		 3874 break;
3875 default:
3876 B43_WARN_ON(1);
3877 return -EINVAL;
bb1eeff1 3878 }
644aa4d6 3879
7a8af8cf
RM		 3880 if (!((gmode && phy->supports_2ghz) ||
3881 (!gmode && phy->supports_5ghz))) {
3882 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
bb1eeff1
MB		 3883 band_to_string(chan->band));
3884 return -ENODEV;
e4d6b795 3885 }
7a8af8cf
RM		 3886
3887 if (!!phy->gmode == !!gmode) {
e4d6b795
MB		 3888 /* This device is already running. */
3889 return 0;
3890 }
7a8af8cf
RM		 3891
3892 b43dbg(dev->wl, "Switching to %s GHz band\n",
bb1eeff1 3893 band_to_string(chan->band));
7a8af8cf 3894
6fe55143
RM		 3895 /* Some new devices don't need disabling radio for band switching */
3896 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3897 b43_software_rfkill(dev, true);
7a8af8cf
RM		 3898
3899 phy->gmode = gmode;
3900 b43_phy_put_into_reset(dev);
3901 switch (dev->dev->bus_type) {
3902#ifdef CONFIG_B43_BCMA
3903 case B43_BUS_BCMA:
3904 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3905 if (gmode)
3906 tmp |= B43_BCMA_IOCTL_GMODE;
3907 else
3908 tmp &= ~B43_BCMA_IOCTL_GMODE;
3909 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3910 break;
3911#endif
3912#ifdef CONFIG_B43_SSB
3913 case B43_BUS_SSB:
3914 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3915 if (gmode)
3916 tmp |= B43_TMSLOW_GMODE;
3917 else
3918 tmp &= ~B43_TMSLOW_GMODE;
3919 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3920 break;
3921#endif
e4d6b795 3922 }
7a8af8cf 3923 b43_phy_take_out_of_reset(dev);
e4d6b795 3924
7a8af8cf
RM		 3925 b43_upload_initvals_band(dev);
3926
3927 b43_phy_init(dev);
e4d6b795
MB		 3928
3929 return 0;
e4d6b795
MB		 3930}
3931
9124b077
JB		 3932/* Write the short and long frame retry limit values. */
3933static void b43_set_retry_limits(struct b43_wldev *dev,
3934 unsigned int short_retry,
3935 unsigned int long_retry)
3936{
3937 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3938 * the chip-internal counter. */
3939 short_retry = min(short_retry, (unsigned int)0xF);
3940 long_retry = min(long_retry, (unsigned int)0xF);
3941
3942 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3943 short_retry);
3944 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3945 long_retry);
3946}
3947
e8975581 3948static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3949{
3950 struct b43_wl *wl = hw_to_b43_wl(hw);
53256511
RM		 3951 struct b43_wldev *dev = wl->current_dev;
3952 struct b43_phy *phy = &dev->phy;
e8975581 3953 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3954 int antenna;
e4d6b795 3955 int err = 0;
e4d6b795 3956
e4d6b795 3957 mutex_lock(&wl->mutex);
7a8af8cf
RM		 3958 b43_mac_suspend(dev);
3959
8c79e5ee 3960 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ea42e71c 3961 phy->chandef = &conf->chandef;
f9471e99 3962 phy->channel = conf->chandef.chan->hw_value;
2a190322 3963
8c79e5ee
RM		 3964 /* Switch the band (if necessary). */
3965 err = b43_switch_band(dev, conf->chandef.chan);
3966 if (err)
3967 goto out_mac_enable;
3968
3969 /* Switch to the requested channel.
3970 * The firmware takes care of races with the TX handler.
3971 */
f9471e99 3972 b43_switch_channel(dev, phy->channel);
8c79e5ee 3973 }
aa4c7b2a 3974
9124b077
JB		 3975 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3976 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3977 conf->long_frame_max_tx_count);
3978 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3979 if (!changed)
d10d0e57 3980 goto out_mac_enable;
e4d6b795 3981
0869aea0 3982 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3983
e4d6b795
MB		 3984 /* Adjust the desired TX power level. */
3985 if (conf->power_level != 0) {
18c8adeb
MB		 3986 if (conf->power_level != phy->desired_txpower) {
3987 phy->desired_txpower = conf->power_level;
3988 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3989 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3990 }
3991 }
3992
3993 /* Antennas for RX and management frame TX. */
0f4ac38b 3994 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3995 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3996 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3997 if (phy->ops->set_rx_antenna)
3998 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3999
fd4973c5
LF		 4000 if (wl->radio_enabled != phy->radio_on) {
4001 if (wl->radio_enabled) {
19d337df 4002 b43_software_rfkill(dev, false);
fda9abcf
MB		 4003 b43info(dev->wl, "Radio turned on by software\n");
4004 if (!dev->radio_hw_enable) {
4005 b43info(dev->wl, "The hardware RF-kill button "
4006 "still turns the radio physically off. "
4007 "Press the button to turn it on.\n");
4008 }
4009 } else {
19d337df 4010 b43_software_rfkill(dev, true);
fda9abcf
MB		 4011 b43info(dev->wl, "Radio turned off by software\n");
4012 }
4013 }
4014
d10d0e57
MB		 4015out_mac_enable:
4016 b43_mac_enable(dev);
e4d6b795
MB		 4017 mutex_unlock(&wl->mutex);
4018
4019 return err;
4020}
4021
881d948c 4022static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 4023{
4024 struct ieee80211_supported_band *sband =
4025 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4026 struct ieee80211_rate *rate;
4027 int i;
4028 u16 basic, direct, offset, basic_offset, rateptr;
4029
4030 for (i = 0; i < sband->n_bitrates; i++) {
4031 rate = &sband->bitrates[i];
4032
4033 if (b43_is_cck_rate(rate->hw_value)) {
4034 direct = B43_SHM_SH_CCKDIRECT;
4035 basic = B43_SHM_SH_CCKBASIC;
4036 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4037 offset &= 0xF;
4038 } else {
4039 direct = B43_SHM_SH_OFDMDIRECT;
4040 basic = B43_SHM_SH_OFDMBASIC;
4041 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4042 offset &= 0xF;
4043 }
4044
4045 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4046
4047 if (b43_is_cck_rate(rate->hw_value)) {
4048 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4049 basic_offset &= 0xF;
4050 } else {
4051 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4052 basic_offset &= 0xF;
4053 }
4054
4055 /*
4056 * Get the pointer that we need to point to
4057 * from the direct map
4058 */
4059 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4060 direct + 2 * basic_offset);
4061 /* and write it to the basic map */
4062 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4063 rateptr);
4064 }
4065}
4066
4067static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4068 struct ieee80211_vif *vif,
4069 struct ieee80211_bss_conf *conf,
4070 u32 changed)
4071{
4072 struct b43_wl *wl = hw_to_b43_wl(hw);
4073 struct b43_wldev *dev;
c7ab5ef9
JB		 4074
4075 mutex_lock(&wl->mutex);
4076
4077 dev = wl->current_dev;
d10d0e57 4078 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 4079 goto out_unlock_mutex;
2d0ddec5
JB		 4080
4081 B43_WARN_ON(wl->vif != vif);
4082
4083 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 4084 if (conf->bssid)
4085 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4086 else
4087 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 4088 }
2d0ddec5 4089
3f0d843b
JB		 4090 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4091 if (changed & BSS_CHANGED_BEACON &&
4092 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4093 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4094 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4095 b43_update_templates(wl);
4096
4097 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 4098 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 4099 }
4100
c7ab5ef9
JB		 4101 b43_mac_suspend(dev);
4102
57c4d7b4
JB		 4103 /* Update templates for AP/mesh mode. */
4104 if (changed & BSS_CHANGED_BEACON_INT &&
4105 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4106 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 4107 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4108 conf->beacon_int)
57c4d7b4
JB		 4109 b43_set_beacon_int(dev, conf->beacon_int);
4110
c7ab5ef9
JB		 4111 if (changed & BSS_CHANGED_BASIC_RATES)
4112 b43_update_basic_rates(dev, conf->basic_rates);
4113
4114 if (changed & BSS_CHANGED_ERP_SLOT) {
4115 if (conf->use_short_slot)
4116 b43_short_slot_timing_enable(dev);
4117 else
4118 b43_short_slot_timing_disable(dev);
4119 }
4120
4121 b43_mac_enable(dev);
d10d0e57 4122out_unlock_mutex:
c7ab5ef9 4123 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 4124}
4125
40faacc4 4126static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4127 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4128 struct ieee80211_key_conf *key)
e4d6b795
MB		 4129{
4130 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4131 struct b43_wldev *dev;
e4d6b795
MB		 4132 u8 algorithm;
4133 u8 index;
c6dfc9a8 4134 int err;
060210f9 4135 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4136
4137 if (modparam_nohwcrypt)
4138 return -ENOSPC; /* User disabled HW-crypto */
4139
78f9c850
AQ		 4140 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4141 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4142 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4143 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4144 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4145 /*
4146 * For now, disable hw crypto for the RSN IBSS group keys. This
4147 * could be optimized in the future, but until that gets
4148 * implemented, use of software crypto for group addressed
4149 * frames is a acceptable to allow RSN IBSS to be used.
4150 */
4151 return -EOPNOTSUPP;
4152 }
4153
c6dfc9a8 4154 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4155
4156 dev = wl->current_dev;
4157 err = -ENODEV;
4158 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4159 goto out_unlock;
4160
403a3a13 4161 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4162 /* We don't have firmware for the crypto engine.
4163 * Must use software-crypto. */
4164 err = -EOPNOTSUPP;
4165 goto out_unlock;
4166 }
4167
c6dfc9a8 4168 err = -EINVAL;
97359d12
JB		 4169 switch (key->cipher) {
4170 case WLAN_CIPHER_SUITE_WEP40:
4171 algorithm = B43_SEC_ALGO_WEP40;
4172 break;
4173 case WLAN_CIPHER_SUITE_WEP104:
4174 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4175 break;
97359d12 4176 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4177 algorithm = B43_SEC_ALGO_TKIP;
4178 break;
97359d12 4179 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4180 algorithm = B43_SEC_ALGO_AES;
4181 break;
4182 default:
4183 B43_WARN_ON(1);
c6dfc9a8 4184 goto out_unlock;
e4d6b795 4185 }
e4d6b795
MB		 4186 index = (u8) (key->keyidx);
4187 if (index > 3)
e4d6b795 4188 goto out_unlock;
e4d6b795
MB		 4189
4190 switch (cmd) {
4191 case SET_KEY:
035d0243 4192 if (algorithm == B43_SEC_ALGO_TKIP &&
4193 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4194 !modparam_hwtkip)) {
4195 /* We support only pairwise key */
e4d6b795
MB		 4196 err = -EOPNOTSUPP;
4197 goto out_unlock;
4198 }
4199
e808e586 4200 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4201 if (WARN_ON(!sta)) {
4202 err = -EOPNOTSUPP;
4203 goto out_unlock;
4204 }
e808e586 4205 /* Pairwise key with an assigned MAC address. */
e4d6b795 4206 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4207 key->key, key->keylen,
4208 sta->addr, key);
e808e586
MB		 4209 } else {
4210 /* Group key */
4211 err = b43_key_write(dev, index, algorithm,
4212 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4213 }
4214 if (err)
4215 goto out_unlock;
4216
4217 if (algorithm == B43_SEC_ALGO_WEP40 ||
4218 algorithm == B43_SEC_ALGO_WEP104) {
4219 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4220 } else {
4221 b43_hf_write(dev,
4222 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4223 }
4224 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4225 if (algorithm == B43_SEC_ALGO_TKIP)
4226 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4227 break;
4228 case DISABLE_KEY: {
4229 err = b43_key_clear(dev, key->hw_key_idx);
4230 if (err)
4231 goto out_unlock;
4232 break;
4233 }
4234 default:
4235 B43_WARN_ON(1);
4236 }
9cf7f247 4237
e4d6b795 4238out_unlock:
e4d6b795
MB		 4239 if (!err) {
4240 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4241 "mac: %pM\n",
e4d6b795 4242 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4243 sta ? sta->addr : bcast_addr);
9cf7f247 4244 b43_dump_keymemory(dev);
e4d6b795 4245 }
9cf7f247
MB		 4246 mutex_unlock(&wl->mutex);
4247
e4d6b795
MB		 4248 return err;
4249}
4250
40faacc4
MB		 4251static void b43_op_configure_filter(struct ieee80211_hw *hw,
4252 unsigned int changed, unsigned int *fflags,
3ac64bee 4253 u64 multicast)
e4d6b795
MB		 4254{
4255 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4256 struct b43_wldev *dev;
e4d6b795 4257
36dbd954
MB		 4258 mutex_lock(&wl->mutex);
4259 dev = wl->current_dev;
4150c572
JB		 4260 if (!dev) {
4261 *fflags = 0;
36dbd954 4262 goto out_unlock;
e4d6b795 4263 }
4150c572 4264
4150c572
JB		 4265 *fflags &= FIF_PROMISC_IN_BSS |
4266 FIF_ALLMULTI |
4267 FIF_FCSFAIL |
4268 FIF_PLCPFAIL |
4269 FIF_CONTROL |
4270 FIF_OTHER_BSS |
4271 FIF_BCN_PRBRESP_PROMISC;
4272
4273 changed &= FIF_PROMISC_IN_BSS |
4274 FIF_ALLMULTI |
4275 FIF_FCSFAIL |
4276 FIF_PLCPFAIL |
4277 FIF_CONTROL |
4278 FIF_OTHER_BSS |
4279 FIF_BCN_PRBRESP_PROMISC;
4280
4281 wl->filter_flags = *fflags;
4282
4283 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4284 b43_adjust_opmode(dev);
36dbd954
MB		 4285
4286out_unlock:
4287 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4288}
4289
36dbd954
MB		 4290/* Locking: wl->mutex
4291 * Returns the current dev. This might be different from the passed in dev,
4292 * because the core might be gone away while we unlocked the mutex. */
4293static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4294{
9a53bf54 4295 struct b43_wl *wl;
36dbd954 4296 struct b43_wldev *orig_dev;
49d965c8 4297 u32 mask;
bad69194 4298 int queue_num;
e4d6b795 4299
9a53bf54
LF		 4300 if (!dev)
4301 return NULL;
4302 wl = dev->wl;
36dbd954
MB		 4303redo:
4304 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4305 return dev;
a19d12d7 4306
f5d40eed 4307 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4308 mutex_unlock(&wl->mutex);
4309 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4310 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4311 mutex_lock(&wl->mutex);
4312 dev = wl->current_dev;
4313 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4314 /* Whoops, aliens ate up the device while we were unlocked. */
4315 return dev;
4316 }
a19d12d7 4317
36dbd954 4318 /* Disable interrupts on the device. */
e4d6b795 4319 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4320 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4321 /* wl->mutex is locked. That is enough. */
4322 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4323 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4324 } else {
4325 spin_lock_irq(&wl->hardirq_lock);
4326 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4327 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4328 spin_unlock_irq(&wl->hardirq_lock);
4329 }
176e9f6a 4330 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4331 orig_dev = dev;
e4d6b795 4332 mutex_unlock(&wl->mutex);
505fb019 4333 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4334 b43_sdio_free_irq(dev);
4335 } else {
a18c715e
RM		 4336 synchronize_irq(dev->dev->irq);
4337 free_irq(dev->dev->irq, dev);
176e9f6a 4338 }
e4d6b795 4339 mutex_lock(&wl->mutex);
36dbd954
MB		 4340 dev = wl->current_dev;
4341 if (!dev)
4342 return dev;
4343 if (dev != orig_dev) {
4344 if (b43_status(dev) >= B43_STAT_STARTED)
4345 goto redo;
4346 return dev;
4347 }
49d965c8
MB		 4348 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4349 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4350
bad69194 4351 /* Drain all TX queues. */
4352 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
78f18df4
FF		 4353 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4354 struct sk_buff *skb;
4355
4356 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4357 ieee80211_free_txskb(wl->hw, skb);
4358 }
bad69194 4359 }
f5d40eed 4360
e4d6b795 4361 b43_mac_suspend(dev);
a78b3bb2 4362 b43_leds_exit(dev);
e4d6b795 4363 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4364
4365 return dev;
e4d6b795
MB		 4366}
4367
4368/* Locking: wl->mutex */
4369static int b43_wireless_core_start(struct b43_wldev *dev)
4370{
4371 int err;
4372
4373 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4374
4375 drain_txstatus_queue(dev);
505fb019 4376 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4377 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4378 if (err) {
4379 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4380 goto out;
4381 }
4382 } else {
a18c715e 4383 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4384 b43_interrupt_thread_handler,
4385 IRQF_SHARED, KBUILD_MODNAME, dev);
4386 if (err) {
dedb1eb9 4387 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4388 dev->dev->irq);
3dbba8e2
AH		 4389 goto out;
4390 }
e4d6b795
MB		 4391 }
4392
4393 /* We are ready to run. */
0866b03c 4394 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4395 b43_set_status(dev, B43_STAT_STARTED);
4396
4397 /* Start data flow (TX/RX). */
4398 b43_mac_enable(dev);
13790728 4399 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4400
25985edc 4401 /* Start maintenance work */
e4d6b795
MB		 4402 b43_periodic_tasks_setup(dev);
4403
a78b3bb2
MB		 4404 b43_leds_init(dev);
4405
e4d6b795 4406 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4407out:
e4d6b795
MB		 4408 return err;
4409}
4410
2fdf8c54
RM		 4411static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4412{
4413 switch (phy_type) {
4414 case B43_PHYTYPE_A:
4415 return "A";
4416 case B43_PHYTYPE_B:
4417 return "B";
4418 case B43_PHYTYPE_G:
4419 return "G";
4420 case B43_PHYTYPE_N:
4421 return "N";
4422 case B43_PHYTYPE_LP:
4423 return "LP";
4424 case B43_PHYTYPE_SSLPN:
4425 return "SSLPN";
4426 case B43_PHYTYPE_HT:
4427 return "HT";
4428 case B43_PHYTYPE_LCN:
4429 return "LCN";
4430 case B43_PHYTYPE_LCNXN:
4431 return "LCNXN";
4432 case B43_PHYTYPE_LCN40:
4433 return "LCN40";
4434 case B43_PHYTYPE_AC:
4435 return "AC";
4436 }
4437 return "UNKNOWN";
4438}
4439
e4d6b795
MB		 4440/* Get PHY and RADIO versioning numbers */
4441static int b43_phy_versioning(struct b43_wldev *dev)
4442{
4443 struct b43_phy *phy = &dev->phy;
fe5e499f 4444 const u8 core_rev = dev->dev->core_rev;
e4d6b795
MB		 4445 u32 tmp;
4446 u8 analog_type;
4447 u8 phy_type;
4448 u8 phy_rev;
4449 u16 radio_manuf;
16e75453 4450 u16 radio_id;
e4d6b795 4451 u16 radio_rev;
16e75453 4452 u8 radio_ver;
e4d6b795
MB		 4453 int unsupported = 0;
4454
4455 /* Get PHY versioning */
4456 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4457 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4458 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4459 phy_rev = (tmp & B43_PHYVER_VERSION);
b49c3caf
RM		 4460
4461 /* LCNXN is continuation of N which run out of revisions */
4462 if (phy_type == B43_PHYTYPE_LCNXN) {
4463 phy_type = B43_PHYTYPE_N;
4464 phy_rev += 16;
4465 }
4466
e4d6b795 4467 switch (phy_type) {
418378fe 4468#ifdef CONFIG_B43_PHY_G
e4d6b795 4469 case B43_PHYTYPE_G:
013978b6 4470 if (phy_rev > 9)
e4d6b795
MB		 4471 unsupported = 1;
4472 break;
418378fe 4473#endif
692d2c0f 4474#ifdef CONFIG_B43_PHY_N
d5c71e46 4475 case B43_PHYTYPE_N:
40c68f20 4476 if (phy_rev >= 19)
d5c71e46
MB		 4477 unsupported = 1;
4478 break;
6b1c7c67
MB		 4479#endif
4480#ifdef CONFIG_B43_PHY_LP
4481 case B43_PHYTYPE_LP:
9d86a2d5 4482 if (phy_rev > 2)
6b1c7c67
MB		 4483 unsupported = 1;
4484 break;
d7520b1d
RM		 4485#endif
4486#ifdef CONFIG_B43_PHY_HT
4487 case B43_PHYTYPE_HT:
4488 if (phy_rev > 1)
4489 unsupported = 1;
4490 break;
1d738e64
RM		 4491#endif
4492#ifdef CONFIG_B43_PHY_LCN
4493 case B43_PHYTYPE_LCN:
4494 if (phy_rev > 1)
4495 unsupported = 1;
4496 break;
d5c71e46 4497#endif
e4d6b795
MB		 4498 default:
4499 unsupported = 1;
6403eab1 4500 }
e4d6b795 4501 if (unsupported) {
2fdf8c54
RM		 4502 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4503 analog_type, phy_type, b43_phy_name(dev, phy_type),
4504 phy_rev);
e4d6b795
MB		 4505 return -EOPNOTSUPP;
4506 }
2fdf8c54
RM		 4507 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4508 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
e4d6b795
MB		 4509
4510 /* Get RADIO versioning */
fe5e499f
RM		 4511 if (core_rev == 40 || core_rev == 42) {
4512 radio_manuf = 0x17F;
4513
25c15566 4514 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
fe5e499f
RM		 4515 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4516
25c15566 4517 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
16e75453
RM		 4518 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4519
4520 radio_ver = 0; /* Is there version somewhere? */
fe5e499f 4521 } else if (core_rev >= 24) {
544e5d8b
RM		 4522 u16 radio24[3];
4523
4524 for (tmp = 0; tmp < 3; tmp++) {
25c15566 4525 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
544e5d8b
RM		 4526 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4527 }
4528
544e5d8b 4529 radio_manuf = 0x17F;
16e75453 4530 radio_id = (radio24[2] << 8) | radio24[1];
544e5d8b 4531 radio_rev = (radio24[0] & 0xF);
16e75453 4532 radio_ver = (radio24[0] & 0xF0) >> 4;
e4d6b795 4533 } else {
3fd48508
RM		 4534 if (dev->dev->chip_id == 0x4317) {
4535 if (dev->dev->chip_rev == 0)
4536 tmp = 0x3205017F;
4537 else if (dev->dev->chip_rev == 1)
4538 tmp = 0x4205017F;
4539 else
4540 tmp = 0x5205017F;
4541 } else {
25c15566
RM		 4542 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4543 B43_RADIOCTL_ID);
3fd48508 4544 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
25c15566
RM		 4545 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4546 B43_RADIOCTL_ID);
4547 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3fd48508
RM		 4548 }
4549 radio_manuf = (tmp & 0x00000FFF);
16e75453 4550 radio_id = (tmp & 0x0FFFF000) >> 12;
3fd48508 4551 radio_rev = (tmp & 0xF0000000) >> 28;
16e75453 4552 radio_ver = 0; /* Probably not available on old hw */
e4d6b795 4553 }
3fd48508 4554
96c755a3
MB		 4555 if (radio_manuf != 0x17F /* Broadcom */)
4556 unsupported = 1;
e4d6b795
MB		 4557 switch (phy_type) {
4558 case B43_PHYTYPE_A:
16e75453 4559 if (radio_id != 0x2060)
e4d6b795
MB		 4560 unsupported = 1;
4561 if (radio_rev != 1)
4562 unsupported = 1;
4563 if (radio_manuf != 0x17F)
4564 unsupported = 1;
4565 break;
4566 case B43_PHYTYPE_B:
16e75453 4567 if ((radio_id & 0xFFF0) != 0x2050)
e4d6b795
MB		 4568 unsupported = 1;
4569 break;
4570 case B43_PHYTYPE_G:
16e75453 4571 if (radio_id != 0x2050)
e4d6b795
MB		 4572 unsupported = 1;
4573 break;
96c755a3 4574 case B43_PHYTYPE_N:
16e75453
RM		 4575 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4576 radio_id != 0x2057)
3695b932 4577 unsupported = 1;
16e75453 4578 if (radio_id == 0x2057 &&
c11082f0 4579 !(radio_rev == 9 || radio_rev == 14))
96c755a3
MB		 4580 unsupported = 1;
4581 break;
6b1c7c67 4582 case B43_PHYTYPE_LP:
16e75453 4583 if (radio_id != 0x2062 && radio_id != 0x2063)
6b1c7c67
MB		 4584 unsupported = 1;
4585 break;
d7520b1d 4586 case B43_PHYTYPE_HT:
16e75453 4587 if (radio_id != 0x2059)
d7520b1d
RM		 4588 unsupported = 1;
4589 break;
1d738e64 4590 case B43_PHYTYPE_LCN:
16e75453 4591 if (radio_id != 0x2064)
1d738e64
RM		 4592 unsupported = 1;
4593 break;
e4d6b795
MB		 4594 default:
4595 B43_WARN_ON(1);
4596 }
4597 if (unsupported) {
88d825bf 4598 b43err(dev->wl,
16e75453
RM		 4599 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4600 radio_manuf, radio_id, radio_rev, radio_ver);
e4d6b795
MB		 4601 return -EOPNOTSUPP;
4602 }
16e75453
RM		 4603 b43info(dev->wl,
4604 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4605 radio_manuf, radio_id, radio_rev, radio_ver);
e4d6b795 4606
16e75453 4607 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
e4d6b795 4608 phy->radio_manuf = radio_manuf;
16e75453 4609 phy->radio_ver = radio_id;
e4d6b795
MB		 4610 phy->radio_rev = radio_rev;
4611
4612 phy->analog = analog_type;
4613 phy->type = phy_type;
4614 phy->rev = phy_rev;
4615
4616 return 0;
4617}
4618
4619static void setup_struct_phy_for_init(struct b43_wldev *dev,
4620 struct b43_phy *phy)
4621{
e4d6b795 4622 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4623 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4624 /* PHY TX errors counter. */
4625 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4626
4627#if B43_DEBUG
3db1cd5c
RR		 4628 phy->phy_locked = false;
4629 phy->radio_locked = false;
591f3dc2 4630#endif
e4d6b795
MB		 4631}
4632
4633static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4634{
3db1cd5c 4635 dev->dfq_valid = false;
aa6c7ae2 4636
6a724d68
MB		 4637 /* Assume the radio is enabled. If it's not enabled, the state will
4638 * immediately get fixed on the first periodic work run. */
3db1cd5c 4639 dev->radio_hw_enable = true;
e4d6b795
MB		 4640
4641 /* Stats */
4642 memset(&dev->stats, 0, sizeof(dev->stats));
4643
4644 setup_struct_phy_for_init(dev, &dev->phy);
4645
4646 /* IRQ related flags */
4647 dev->irq_reason = 0;
4648 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4649 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4650 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4651 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4652
4653 dev->mac_suspended = 1;
4654
4655 /* Noise calculation context */
4656 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4657}
4658
4659static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4660{
0581483a 4661 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4662 u64 hf;
e4d6b795 4663
1855ba78
MB		 4664 if (!modparam_btcoex)
4665 return;
95de2841 4666 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4667 return;
4668 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4669 return;
4670
4671 hf = b43_hf_read(dev);
95de2841 4672 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4673 hf |= B43_HF_BTCOEXALT;
4674 else
4675 hf |= B43_HF_BTCOEX;
4676 b43_hf_write(dev, hf);
e4d6b795
MB		 4677}
4678
4679static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4680{
4681 if (!modparam_btcoex)
4682 return;
4683 //TODO
e4d6b795
MB		 4684}
4685
4686static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4687{
d48ae5c8 4688 struct ssb_bus *bus;
e4d6b795
MB		 4689 u32 tmp;
4690
bd7c8a59 4691#ifdef CONFIG_B43_SSB
d48ae5c8
RM		 4692 if (dev->dev->bus_type != B43_BUS_SSB)
4693 return;
bd7c8a59
RM		 4694#else
4695 return;
4696#endif
d48ae5c8
RM		 4697
4698 bus = dev->dev->sdev->bus;
4699
0fd82eaf
RM		 4700 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4701 (bus->chip_id == 0x4312)) {
d48ae5c8 4702 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4703 tmp &= ~SSB_IMCFGLO_REQTO;
4704 tmp &= ~SSB_IMCFGLO_SERTO;
4705 tmp |= 0x3;
d48ae5c8 4706 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4707 ssb_commit_settings(bus);
e4d6b795 4708 }
e4d6b795
MB		 4709}
4710
d59f720d
MB		 4711static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4712{
4713 u16 pu_delay;
4714
4715 /* The time value is in microseconds. */
4716 if (dev->phy.type == B43_PHYTYPE_A)
4717 pu_delay = 3700;
4718 else
4719 pu_delay = 1050;
05c914fe 4720 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4721 pu_delay = 500;
4722 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4723 pu_delay = max(pu_delay, (u16)2400);
4724
4725 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4726}
4727
4728/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4729static void b43_set_pretbtt(struct b43_wldev *dev)
4730{
4731 u16 pretbtt;
4732
4733 /* The time value is in microseconds. */
05c914fe 4734 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4735 pretbtt = 2;
4736 } else {
4737 if (dev->phy.type == B43_PHYTYPE_A)
4738 pretbtt = 120;
4739 else
4740 pretbtt = 250;
4741 }
4742 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4743 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4744}
4745
e4d6b795
MB		 4746/* Shutdown a wireless core */
4747/* Locking: wl->mutex */
4748static void b43_wireless_core_exit(struct b43_wldev *dev)
4749{
36dbd954
MB		 4750 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4751 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4752 return;
84c164a3 4753
e4d6b795
MB		 4754 b43_set_status(dev, B43_STAT_UNINIT);
4755
1f7d87b0 4756 /* Stop the microcode PSM. */
5056635c
RM		 4757 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4758 B43_MACCTL_PSM_JMP0);
1f7d87b0 4759
50023008
HM		 4760 switch (dev->dev->bus_type) {
4761#ifdef CONFIG_B43_BCMA
4762 case B43_BUS_BCMA:
4763 bcma_core_pci_down(dev->dev->bdev->bus);
4764 break;
4765#endif
4766#ifdef CONFIG_B43_SSB
4767 case B43_BUS_SSB:
4768 /* TODO */
4769 break;
4770#endif
4771 }
4772
e4d6b795 4773 b43_dma_free(dev);
5100d5ac 4774 b43_pio_free(dev);
e4d6b795 4775 b43_chip_exit(dev);
cb24f57f 4776 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4777 if (dev->wl->current_beacon) {
4778 dev_kfree_skb_any(dev->wl->current_beacon);
4779 dev->wl->current_beacon = NULL;
4780 }
4781
24ca39d6
RM		 4782 b43_device_disable(dev, 0);
4783 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4784}
4785
4786/* Initialize a wireless core */
4787static int b43_wireless_core_init(struct b43_wldev *dev)
4788{
0581483a 4789 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4790 struct b43_phy *phy = &dev->phy;
4791 int err;
a259d6a4 4792 u64 hf;
e4d6b795
MB		 4793
4794 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4795
24ca39d6 4796 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4797 if (err)
4798 goto out;
4da909e7
RM		 4799 if (!b43_device_is_enabled(dev))
4800 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4801
fb11137a 4802 /* Reset all data structures. */
e4d6b795 4803 setup_struct_wldev_for_init(dev);
fb11137a 4804 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4805
4806 /* Enable IRQ routing to this device. */
6cbab0d9 4807 switch (dev->dev->bus_type) {
42c9a458
RM		 4808#ifdef CONFIG_B43_BCMA
4809 case B43_BUS_BCMA:
dfae7143 4810 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
42c9a458 4811 dev->dev->bdev, true);
50023008 4812 bcma_core_pci_up(dev->dev->bdev->bus);
42c9a458
RM		 4813 break;
4814#endif
6cbab0d9
RM		 4815#ifdef CONFIG_B43_SSB
4816 case B43_BUS_SSB:
4817 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4818 dev->dev->sdev);
4819 break;
4820#endif
4821 }
e4d6b795
MB		 4822
4823 b43_imcfglo_timeouts_workaround(dev);
4824 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4825 if (phy->ops->prepare_hardware) {
4826 err = phy->ops->prepare_hardware(dev);
ef1a628d 4827 if (err)
fb11137a 4828 goto err_busdown;
ef1a628d 4829 }
e4d6b795
MB		 4830 err = b43_chip_init(dev);
4831 if (err)
fb11137a 4832 goto err_busdown;
e4d6b795 4833 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4834 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4835 hf = b43_hf_read(dev);
4836 if (phy->type == B43_PHYTYPE_G) {
4837 hf |= B43_HF_SYMW;
4838 if (phy->rev == 1)
4839 hf |= B43_HF_GDCW;
95de2841 4840 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4841 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4842 }
4843 if (phy->radio_ver == 0x2050) {
4844 if (phy->radio_rev == 6)
4845 hf |= B43_HF_4318TSSI;
4846 if (phy->radio_rev < 6)
4847 hf |= B43_HF_VCORECALC;
e4d6b795 4848 }
1cc8f476
MB		 4849 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4850 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
bd7c8a59 4851#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
6cbab0d9
RM		 4852 if (dev->dev->bus_type == B43_BUS_SSB &&
4853 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4854 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4855 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4856#endif
25d3ef59 4857 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4858 b43_hf_write(dev, hf);
4859
5eb3645e
HM		 4860 /* tell the ucode MAC capabilities */
4861 if (dev->dev->core_rev >= 13) {
4862 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4863
4864 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4865 mac_hw_cap & 0xffff);
4866 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4867 (mac_hw_cap >> 16) & 0xffff);
4868 }
4869
74cfdba7
MB		 4870 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4871 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4872 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4873 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4874
4875 /* Disable sending probe responses from firmware.
4876 * Setting the MaxTime to one usec will always trigger
4877 * a timeout, so we never send any probe resp.
4878 * A timeout of zero is infinite. */
4879 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4880
4881 b43_rate_memory_init(dev);
5042c507 4882 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4883
4884 /* Minimum Contention Window */
c5a079f4 4885 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4886 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4887 else
e4d6b795 4888 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4889 /* Maximum Contention Window */
4890 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4891
261b758b
HM		 4892 /* write phytype and phyvers */
4893 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4894 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4895
505fb019 4896 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4897 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4898 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4899 err = b43_pio_init(dev);
4900 } else if (dev->use_pio) {
4901 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4902 "This should not be needed and will result in lower "
4903 "performance.\n");
3db1cd5c 4904 dev->__using_pio_transfers = true;
5100d5ac
MB		 4905 err = b43_pio_init(dev);
4906 } else {
3db1cd5c 4907 dev->__using_pio_transfers = false;
5100d5ac
MB		 4908 err = b43_dma_init(dev);
4909 }
e4d6b795
MB		 4910 if (err)
4911 goto err_chip_exit;
03b29773 4912 b43_qos_init(dev);
d59f720d 4913 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4914 b43_bluetooth_coext_enable(dev);
4915
24ca39d6 4916 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4917 b43_upload_card_macaddress(dev);
e4d6b795 4918 b43_security_init(dev);
e4d6b795 4919
5ab9549a 4920 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4921
4922 b43_set_status(dev, B43_STAT_INITIALIZED);
4923
1a8d1227 4924out:
e4d6b795
MB		 4925 return err;
4926
ef1a628d 4927err_chip_exit:
e4d6b795 4928 b43_chip_exit(dev);
ef1a628d 4929err_busdown:
24ca39d6 4930 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4931 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4932 return err;
4933}
4934
40faacc4 4935static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4936 struct ieee80211_vif *vif)
e4d6b795
MB		 4937{
4938 struct b43_wl *wl = hw_to_b43_wl(hw);
4939 struct b43_wldev *dev;
e4d6b795 4940 int err = -EOPNOTSUPP;
4150c572
JB		 4941
4942 /* TODO: allow WDS/AP devices to coexist */
4943
1ed32e4f
JB		 4944 if (vif->type != NL80211_IFTYPE_AP &&
4945 vif->type != NL80211_IFTYPE_MESH_POINT &&
4946 vif->type != NL80211_IFTYPE_STATION &&
4947 vif->type != NL80211_IFTYPE_WDS &&
4948 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4949 return -EOPNOTSUPP;
e4d6b795
MB		 4950
4951 mutex_lock(&wl->mutex);
4150c572 4952 if (wl->operating)
e4d6b795
MB		 4953 goto out_mutex_unlock;
4954
1ed32e4f 4955 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4956
4957 dev = wl->current_dev;
3db1cd5c 4958 wl->operating = true;
1ed32e4f
JB		 4959 wl->vif = vif;
4960 wl->if_type = vif->type;
4961 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4962
4150c572 4963 b43_adjust_opmode(dev);
d59f720d
MB		 4964 b43_set_pretbtt(dev);
4965 b43_set_synth_pu_delay(dev, 0);
4150c572 4966 b43_upload_card_macaddress(dev);
4150c572
JB		 4967
4968 err = 0;
4969 out_mutex_unlock:
4970 mutex_unlock(&wl->mutex);
4971
2a190322
FF		 4972 if (err == 0)
4973 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4974
4150c572
JB		 4975 return err;
4976}
4977
40faacc4 4978static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4979 struct ieee80211_vif *vif)
4150c572
JB		 4980{
4981 struct b43_wl *wl = hw_to_b43_wl(hw);
4982 struct b43_wldev *dev = wl->current_dev;
4150c572 4983
1ed32e4f 4984 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4985
4986 mutex_lock(&wl->mutex);
4987
4988 B43_WARN_ON(!wl->operating);
1ed32e4f 4989 B43_WARN_ON(wl->vif != vif);
32bfd35d 4990 wl->vif = NULL;
4150c572 4991
3db1cd5c 4992 wl->operating = false;
4150c572 4993
4150c572
JB		 4994 b43_adjust_opmode(dev);
4995 memset(wl->mac_addr, 0, ETH_ALEN);
4996 b43_upload_card_macaddress(dev);
4150c572
JB		 4997
4998 mutex_unlock(&wl->mutex);
4999}
5000
40faacc4 5001static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 5002{
5003 struct b43_wl *wl = hw_to_b43_wl(hw);
5004 struct b43_wldev *dev = wl->current_dev;
5005 int did_init = 0;
923403b8 5006 int err = 0;
4150c572 5007
7be1bb6b
MB		 5008 /* Kill all old instance specific information to make sure
5009 * the card won't use it in the short timeframe between start
5010 * and mac80211 reconfiguring it. */
5011 memset(wl->bssid, 0, ETH_ALEN);
5012 memset(wl->mac_addr, 0, ETH_ALEN);
5013 wl->filter_flags = 0;
3db1cd5c 5014 wl->radiotap_enabled = false;
e6f5b934 5015 b43_qos_clear(wl);
3db1cd5c
RR		 5016 wl->beacon0_uploaded = false;
5017 wl->beacon1_uploaded = false;
5018 wl->beacon_templates_virgin = true;
5019 wl->radio_enabled = true;
7be1bb6b 5020
4150c572
JB		 5021 mutex_lock(&wl->mutex);
5022
e4d6b795
MB		 5023 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5024 err = b43_wireless_core_init(dev);
f41f3f37 5025 if (err)
e4d6b795
MB		 5026 goto out_mutex_unlock;
5027 did_init = 1;
5028 }
4150c572 5029
e4d6b795
MB		 5030 if (b43_status(dev) < B43_STAT_STARTED) {
5031 err = b43_wireless_core_start(dev);
5032 if (err) {
5033 if (did_init)
5034 b43_wireless_core_exit(dev);
5035 goto out_mutex_unlock;
5036 }
5037 }
5038
f41f3f37
JB		 5039 /* XXX: only do if device doesn't support rfkill irq */
5040 wiphy_rfkill_start_polling(hw->wiphy);
5041
4150c572 5042 out_mutex_unlock:
e4d6b795
MB		 5043 mutex_unlock(&wl->mutex);
5044
dbdedbdf
SF		 5045 /*
5046 * Configuration may have been overwritten during initialization.
5047 * Reload the configuration, but only if initialization was
5048 * successful. Reloading the configuration after a failed init
5049 * may hang the system.
5050 */
5051 if (!err)
5052 b43_op_config(hw, ~0);
2a190322 5053
e4d6b795
MB		 5054 return err;
5055}
5056
40faacc4 5057static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 5058{
5059 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 5060 struct b43_wldev *dev = wl->current_dev;
e4d6b795 5061
a82d9922 5062 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 5063
ccde8a45
GL		 5064 if (!dev)
5065 goto out;
5066
e4d6b795 5067 mutex_lock(&wl->mutex);
36dbd954
MB		 5068 if (b43_status(dev) >= B43_STAT_STARTED) {
5069 dev = b43_wireless_core_stop(dev);
5070 if (!dev)
5071 goto out_unlock;
5072 }
4150c572 5073 b43_wireless_core_exit(dev);
3db1cd5c 5074 wl->radio_enabled = false;
36dbd954
MB		 5075
5076out_unlock:
e4d6b795 5077 mutex_unlock(&wl->mutex);
ccde8a45 5078out:
18c8adeb 5079 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 5080}
5081
17741cdc
JB		 5082static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5083 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 5084{
5085 struct b43_wl *wl = hw_to_b43_wl(hw);
5086
8f611288 5087 /* FIXME: add locking */
9d139c81 5088 b43_update_templates(wl);
e66fee6a
MB		 5089
5090 return 0;
5091}
5092
38968d09
JB		 5093static void b43_op_sta_notify(struct ieee80211_hw *hw,
5094 struct ieee80211_vif *vif,
5095 enum sta_notify_cmd notify_cmd,
17741cdc 5096 struct ieee80211_sta *sta)
38968d09
JB		 5097{
5098 struct b43_wl *wl = hw_to_b43_wl(hw);
5099
5100 B43_WARN_ON(!vif || wl->vif != vif);
5101}
5102
25d3ef59
MB		 5103static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
5104{
5105 struct b43_wl *wl = hw_to_b43_wl(hw);
5106 struct b43_wldev *dev;
5107
5108 mutex_lock(&wl->mutex);
5109 dev = wl->current_dev;
5110 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5111 /* Disable CFP update during scan on other channels. */
5112 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5113 }
5114 mutex_unlock(&wl->mutex);
5115}
5116
5117static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
5118{
5119 struct b43_wl *wl = hw_to_b43_wl(hw);
5120 struct b43_wldev *dev;
5121
5122 mutex_lock(&wl->mutex);
5123 dev = wl->current_dev;
5124 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5125 /* Re-enable CFP update. */
5126 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5127 }
5128 mutex_unlock(&wl->mutex);
5129}
5130
354b4f04
JL		 5131static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5132 struct survey_info *survey)
5133{
5134 struct b43_wl *wl = hw_to_b43_wl(hw);
5135 struct b43_wldev *dev = wl->current_dev;
5136 struct ieee80211_conf *conf = &hw->conf;
5137
5138 if (idx != 0)
5139 return -ENOENT;
5140
675a0b04 5141 survey->channel = conf->chandef.chan;
354b4f04
JL		 5142 survey->filled = SURVEY_INFO_NOISE_DBM;
5143 survey->noise = dev->stats.link_noise;
5144
5145 return 0;
5146}
5147
e4d6b795 5148static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 5149 .tx = b43_op_tx,
5150 .conf_tx = b43_op_conf_tx,
5151 .add_interface = b43_op_add_interface,
5152 .remove_interface = b43_op_remove_interface,
5153 .config = b43_op_config,
c7ab5ef9 5154 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 5155 .configure_filter = b43_op_configure_filter,
5156 .set_key = b43_op_set_key,
035d0243 5157 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 5158 .get_stats = b43_op_get_stats,
08e87a83
AF		 5159 .get_tsf = b43_op_get_tsf,
5160 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 5161 .start = b43_op_start,
5162 .stop = b43_op_stop,
e66fee6a 5163 .set_tim = b43_op_beacon_set_tim,
38968d09 5164 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 5165 .sw_scan_start = b43_op_sw_scan_start_notifier,
5166 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 5167 .get_survey = b43_op_get_survey,
f41f3f37 5168 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 5169};
5170
5171/* Hard-reset the chip. Do not call this directly.
5172 * Use b43_controller_restart()
5173 */
5174static void b43_chip_reset(struct work_struct *work)
5175{
5176 struct b43_wldev *dev =
5177 container_of(work, struct b43_wldev, restart_work);
5178 struct b43_wl *wl = dev->wl;
5179 int err = 0;
5180 int prev_status;
5181
5182 mutex_lock(&wl->mutex);
5183
5184 prev_status = b43_status(dev);
5185 /* Bring the device down... */
36dbd954
MB		 5186 if (prev_status >= B43_STAT_STARTED) {
5187 dev = b43_wireless_core_stop(dev);
5188 if (!dev) {
5189 err = -ENODEV;
5190 goto out;
5191 }
5192 }
e4d6b795
MB		 5193 if (prev_status >= B43_STAT_INITIALIZED)
5194 b43_wireless_core_exit(dev);
5195
5196 /* ...and up again. */
5197 if (prev_status >= B43_STAT_INITIALIZED) {
5198 err = b43_wireless_core_init(dev);
5199 if (err)
5200 goto out;
5201 }
5202 if (prev_status >= B43_STAT_STARTED) {
5203 err = b43_wireless_core_start(dev);
5204 if (err) {
5205 b43_wireless_core_exit(dev);
5206 goto out;
5207 }
5208 }
3bf0a32e
MB		 5209out:
5210 if (err)
5211 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5212 mutex_unlock(&wl->mutex);
2a190322
FF		 5213
5214 if (err) {
e4d6b795 5215 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5216 return;
5217 }
5218
5219 /* reload configuration */
5220 b43_op_config(wl->hw, ~0);
5221 if (wl->vif)
5222 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5223
5224 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5225}
5226
bb1eeff1 5227static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5228 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5229{
5230 struct ieee80211_hw *hw = dev->wl->hw;
3695b932
RM		 5231 struct b43_phy *phy = &dev->phy;
5232 bool limited_2g;
b453fda6 5233 bool limited_5g;
3695b932
RM		 5234
5235 /* We don't support all 2 GHz channels on some devices */
c11082f0
RM		 5236 limited_2g = phy->radio_ver == 0x2057 &&
5237 (phy->radio_rev == 9 || phy->radio_rev == 14);
b453fda6
RM		 5238 limited_5g = phy->radio_ver == 0x2057 &&
5239 phy->radio_rev == 9;
e4d6b795 5240
bb1eeff1 5241 if (have_2ghz_phy)
3695b932
RM		 5242 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5243 &b43_band_2ghz_limited : &b43_band_2GHz;
bb1eeff1
MB		 5244 if (dev->phy.type == B43_PHYTYPE_N) {
5245 if (have_5ghz_phy)
b453fda6
RM		 5246 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ?
5247 &b43_band_5GHz_nphy_limited :
5248 &b43_band_5GHz_nphy;
bb1eeff1
MB		 5249 } else {
5250 if (have_5ghz_phy)
5251 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5252 }
96c755a3 5253
bb1eeff1
MB		 5254 dev->phy.supports_2ghz = have_2ghz_phy;
5255 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5256
5257 return 0;
5258}
5259
5260static void b43_wireless_core_detach(struct b43_wldev *dev)
5261{
5262 /* We release firmware that late to not be required to re-request
5263 * is all the time when we reinit the core. */
5264 b43_release_firmware(dev);
fb11137a 5265 b43_phy_free(dev);
e4d6b795
MB		 5266}
5267
075ca604
RM		 5268static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5269 bool *have_5ghz_phy)
5270{
5271 u16 dev_id = 0;
5272
773cfc50
RM		 5273#ifdef CONFIG_B43_BCMA
5274 if (dev->dev->bus_type == B43_BUS_BCMA &&
5275 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5276 dev_id = dev->dev->bdev->bus->host_pci->device;
5277#endif
075ca604
RM		 5278#ifdef CONFIG_B43_SSB
5279 if (dev->dev->bus_type == B43_BUS_SSB &&
5280 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5281 dev_id = dev->dev->sdev->bus->host_pci->device;
5282#endif
773cfc50
RM		 5283 /* Override with SPROM value if available */
5284 if (dev->dev->bus_sprom->dev_id)
5285 dev_id = dev->dev->bus_sprom->dev_id;
075ca604
RM		 5286
5287 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5288 switch (dev_id) {
5289 case 0x4324: /* BCM4306 */
5290 case 0x4312: /* BCM4311 */
5291 case 0x4319: /* BCM4318 */
773cfc50
RM		 5292 case 0x4328: /* BCM4321 */
5293 case 0x432b: /* BCM4322 */
5294 case 0x4350: /* BCM43222 */
5295 case 0x4353: /* BCM43224 */
5296 case 0x0576: /* BCM43224 */
5297 case 0x435f: /* BCM6362 */
5298 case 0x4331: /* BCM4331 */
5299 case 0x4359: /* BCM43228 */
5300 case 0x43a0: /* BCM4360 */
5301 case 0x43b1: /* BCM4352 */
075ca604
RM		 5302 /* Dual band devices */
5303 *have_2ghz_phy = true;
5304 *have_5ghz_phy = true;
5305 return;
773cfc50
RM		 5306 case 0x4321: /* BCM4306 */
5307 case 0x4313: /* BCM4311 */
5308 case 0x431a: /* BCM4318 */
5309 case 0x432a: /* BCM4321 */
5310 case 0x432d: /* BCM4322 */
5311 case 0x4352: /* BCM43222 */
5312 case 0x4333: /* BCM4331 */
5313 case 0x43a2: /* BCM4360 */
5314 case 0x43b3: /* BCM4352 */
5315 /* 5 GHz only devices */
5316 *have_2ghz_phy = false;
5317 *have_5ghz_phy = true;
5318 return;
075ca604
RM		 5319 }
5320
5321 /* As a fallback, try to guess using PHY type */
5322 switch (dev->phy.type) {
5323 case B43_PHYTYPE_A:
5324 *have_2ghz_phy = false;
5325 *have_5ghz_phy = true;
5326 return;
5327 case B43_PHYTYPE_G:
5328 case B43_PHYTYPE_N:
5329 case B43_PHYTYPE_LP:
5330 case B43_PHYTYPE_HT:
5331 case B43_PHYTYPE_LCN:
5332 *have_2ghz_phy = true;
5333 *have_5ghz_phy = false;
5334 return;
5335 }
5336
5337 B43_WARN_ON(1);
5338}
5339
e4d6b795
MB		 5340static int b43_wireless_core_attach(struct b43_wldev *dev)
5341{
5342 struct b43_wl *wl = dev->wl;
09951ad4 5343 struct b43_phy *phy = &dev->phy;
e4d6b795 5344 int err;
40c62269 5345 u32 tmp;
3db1cd5c 5346 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5347
5348 /* Do NOT do any device initialization here.
5349 * Do it in wireless_core_init() instead.
5350 * This function is for gathering basic information about the HW, only.
5351 * Also some structs may be set up here. But most likely you want to have
5352 * that in core_init(), too.
5353 */
5354
24ca39d6 5355 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5356 if (err) {
5357 b43err(wl, "Bus powerup failed\n");
5358 goto out;
5359 }
e4d6b795 5360
09951ad4
RM		 5361 phy->do_full_init = true;
5362
075ca604 5363 /* Try to guess supported bands for the first init needs */
6cbab0d9 5364 switch (dev->dev->bus_type) {
42c9a458
RM		 5365#ifdef CONFIG_B43_BCMA
5366 case B43_BUS_BCMA:
40c62269
RM		 5367 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5368 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5369 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5370 break;
5371#endif
6cbab0d9
RM		 5372#ifdef CONFIG_B43_SSB
5373 case B43_BUS_SSB:
5374 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5375 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5376 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5377 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5378 } else
5379 B43_WARN_ON(1);
5380 break;
5381#endif
5382 }
e4d6b795 5383
96c755a3 5384 dev->phy.gmode = have_2ghz_phy;
4da909e7 5385 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795 5386
075ca604 5387 /* Get the PHY type. */
e4d6b795
MB		 5388 err = b43_phy_versioning(dev);
5389 if (err)
21954c36 5390 goto err_powerdown;
075ca604
RM		 5391
5392 /* Get real info about supported bands */
5393 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5394
5395 /* We don't support 5 GHz on some PHYs yet */
72fcd3d1
RM		 5396 if (have_5ghz_phy) {
5397 switch (dev->phy.type) {
5398 case B43_PHYTYPE_A:
5399 case B43_PHYTYPE_G:
72fcd3d1
RM		 5400 case B43_PHYTYPE_LP:
5401 case B43_PHYTYPE_HT:
5402 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5403 have_5ghz_phy = false;
5404 }
e4d6b795 5405 }
075ca604
RM		 5406
5407 if (!have_2ghz_phy && !have_5ghz_phy) {
5408 b43err(wl, "b43 can't support any band on this device\n");
96c755a3
MB		 5409 err = -EOPNOTSUPP;
5410 goto err_powerdown;
5411 }
2e35af14 5412
fb11137a
MB		 5413 err = b43_phy_allocate(dev);
5414 if (err)
5415 goto err_powerdown;
5416
96c755a3 5417 dev->phy.gmode = have_2ghz_phy;
4da909e7 5418 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5419
5420 err = b43_validate_chipaccess(dev);
5421 if (err)
fb11137a 5422 goto err_phy_free;
bb1eeff1 5423 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5424 if (err)
fb11137a 5425 goto err_phy_free;
e4d6b795
MB		 5426
5427 /* Now set some default "current_dev" */
5428 if (!wl->current_dev)
5429 wl->current_dev = dev;
5430 INIT_WORK(&dev->restart_work, b43_chip_reset);
5431
cb24f57f 5432 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5433 b43_device_disable(dev, 0);
5434 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5435
5436out:
5437 return err;
5438
fb11137a
MB		 5439err_phy_free:
5440 b43_phy_free(dev);
e4d6b795 5441err_powerdown:
24ca39d6 5442 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5443 return err;
5444}
5445
482f0538 5446static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5447{
5448 struct b43_wldev *wldev;
5449 struct b43_wl *wl;
5450
3bf0a32e
MB		 5451 /* Do not cancel ieee80211-workqueue based work here.
5452 * See comment in b43_remove(). */
5453
74abacb6 5454 wldev = b43_bus_get_wldev(dev);
e4d6b795 5455 wl = wldev->wl;
e4d6b795
MB		 5456 b43_debugfs_remove_device(wldev);
5457 b43_wireless_core_detach(wldev);
5458 list_del(&wldev->list);
74abacb6 5459 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5460 kfree(wldev);
5461}
5462
482f0538 5463static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5464{
5465 struct b43_wldev *wldev;
e4d6b795
MB		 5466 int err = -ENOMEM;
5467
e4d6b795
MB		 5468 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5469 if (!wldev)
5470 goto out;
5471
9e3bd919 5472 wldev->use_pio = b43_modparam_pio;
482f0538 5473 wldev->dev = dev;
e4d6b795
MB		 5474 wldev->wl = wl;
5475 b43_set_status(wldev, B43_STAT_UNINIT);
5476 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5477 INIT_LIST_HEAD(&wldev->list);
5478
5479 err = b43_wireless_core_attach(wldev);
5480 if (err)
5481 goto err_kfree_wldev;
5482
74abacb6 5483 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5484 b43_debugfs_add_device(wldev);
5485
5486 out:
5487 return err;
5488
5489 err_kfree_wldev:
5490 kfree(wldev);
5491 return err;
5492}
5493
9fc38458
MB		 5494#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5495 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5496 (pdev->device == _device) && \
5497 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5498 (pdev->subsystem_device == _subdevice) )
5499
bd7c8a59 5500#ifdef CONFIG_B43_SSB
e4d6b795
MB		 5501static void b43_sprom_fixup(struct ssb_bus *bus)
5502{
1855ba78
MB		 5503 struct pci_dev *pdev;
5504
e4d6b795
MB		 5505 /* boardflags workarounds */
5506 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5507 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5508 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5509 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5510 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5511 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5512 if (bus->bustype == SSB_BUSTYPE_PCI) {
5513 pdev = bus->host_pci;
9fc38458 5514 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5515 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5516 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5517 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5518 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5519 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5520 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5521 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5522 }
e4d6b795
MB		 5523}
5524
482f0538 5525static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5526{
5527 struct ieee80211_hw *hw = wl->hw;
5528
482f0538 5529 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5530 ieee80211_free_hw(hw);
5531}
bd7c8a59 5532#endif
e4d6b795 5533
d1507051 5534static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5535{
d1507051 5536 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5537 struct ieee80211_hw *hw;
5538 struct b43_wl *wl;
2729df25 5539 char chip_name[6];
bad69194 5540 int queue_num;
e4d6b795
MB		 5541
5542 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5543 if (!hw) {
5544 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5545 return ERR_PTR(-ENOMEM);
e4d6b795 5546 }
403a3a13 5547 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5548
5549 /* fill hw info */
605a0bd6 5550 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5551 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5552
f59ac048
LR		 5553 hw->wiphy->interface_modes =
5554 BIT(NL80211_IFTYPE_AP) |
5555 BIT(NL80211_IFTYPE_MESH_POINT) |
5556 BIT(NL80211_IFTYPE_STATION) |
5557 BIT(NL80211_IFTYPE_WDS) |
5558 BIT(NL80211_IFTYPE_ADHOC);
5559
78f9c850
AQ		 5560 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5561
e64add27 5562 wl->hw_registred = false;
e6a9854b 5563 hw->max_rates = 2;
e4d6b795 5564 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5565 if (is_valid_ether_addr(sprom->et1mac))
5566 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5567 else
95de2841 5568 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5569
403a3a13 5570 /* Initialize struct b43_wl */
e4d6b795 5571 wl->hw = hw;
e4d6b795 5572 mutex_init(&wl->mutex);
36dbd954 5573 spin_lock_init(&wl->hardirq_lock);
a82d9922 5574 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5575 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5576 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5577
5578 /* Initialize queues and flags. */
5579 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5580 skb_queue_head_init(&wl->tx_queue[queue_num]);
5581 wl->tx_queue_stopped[queue_num] = 0;
5582 }
e4d6b795 5583
2729df25
RM		 5584 snprintf(chip_name, ARRAY_SIZE(chip_name),
5585 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5586 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5587 dev->core_rev);
0355a345 5588 return wl;
e4d6b795
MB		 5589}
5590
3c65ab62
RM		 5591#ifdef CONFIG_B43_BCMA
5592static int b43_bcma_probe(struct bcma_device *core)
5593{
397915c3 5594 struct b43_bus_dev *dev;
24aad3f4
RM		 5595 struct b43_wl *wl;
5596 int err;
397915c3 5597
8960400e
RM		 5598 if (!modparam_allhwsupport &&
5599 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5600 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5601 return -ENOTSUPP;
5602 }
5603
397915c3
RM		 5604 dev = b43_bus_dev_bcma_init(core);
5605 if (!dev)
5606 return -ENODEV;
5607
24aad3f4
RM		 5608 wl = b43_wireless_init(dev);
5609 if (IS_ERR(wl)) {
5610 err = PTR_ERR(wl);
5611 goto bcma_out;
5612 }
5613
5614 err = b43_one_core_attach(dev, wl);
5615 if (err)
5616 goto bcma_err_wireless_exit;
5617
6b6fa586
LF		 5618 /* setup and start work to load firmware */
5619 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5620 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5621
5622bcma_out:
5623 return err;
5624
24aad3f4
RM		 5625bcma_err_wireless_exit:
5626 ieee80211_free_hw(wl->hw);
5627 return err;
3c65ab62
RM		 5628}
5629
5630static void b43_bcma_remove(struct bcma_device *core)
5631{
24aad3f4
RM		 5632 struct b43_wldev *wldev = bcma_get_drvdata(core);
5633 struct b43_wl *wl = wldev->wl;
5634
5635 /* We must cancel any work here before unregistering from ieee80211,
5636 * as the ieee80211 unreg will destroy the workqueue. */
5637 cancel_work_sync(&wldev->restart_work);
63a02ce1 5638 cancel_work_sync(&wl->firmware_load);
24aad3f4 5639
e64add27 5640 B43_WARN_ON(!wl);
f89ff644
LF		 5641 if (!wldev->fw.ucode.data)
5642 return; /* NULL if firmware never loaded */
e64add27 5643 if (wl->current_dev == wldev && wl->hw_registred) {
e64add27
OR		 5644 b43_leds_stop(wldev);
5645 ieee80211_unregister_hw(wl->hw);
5646 }
24aad3f4
RM		 5647
5648 b43_one_core_detach(wldev->dev);
5649
09164043
LF		 5650 /* Unregister HW RNG driver */
5651 b43_rng_exit(wl);
5652
24aad3f4
RM		 5653 b43_leds_unregister(wl);
5654
5655 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5656}
5657
5658static struct bcma_driver b43_bcma_driver = {
5659 .name = KBUILD_MODNAME,
5660 .id_table = b43_bcma_tbl,
5661 .probe = b43_bcma_probe,
5662 .remove = b43_bcma_remove,
5663};
5664#endif
5665
aec7ffdf 5666#ifdef CONFIG_B43_SSB
aa63418a
RM		 5667static
5668int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5669{
482f0538 5670 struct b43_bus_dev *dev;
e4d6b795
MB		 5671 struct b43_wl *wl;
5672 int err;
e4d6b795 5673
482f0538 5674 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5675 if (!dev)
5676 return -ENOMEM;
482f0538 5677
aa63418a 5678 wl = ssb_get_devtypedata(sdev);
8f15e287
RM		 5679 if (wl) {
5680 b43err(NULL, "Dual-core devices are not supported\n");
5681 err = -ENOTSUPP;
5682 goto err_ssb_kfree_dev;
e4d6b795 5683 }
8f15e287
RM		 5684
5685 b43_sprom_fixup(sdev->bus);
5686
5687 wl = b43_wireless_init(dev);
5688 if (IS_ERR(wl)) {
5689 err = PTR_ERR(wl);
5690 goto err_ssb_kfree_dev;
5691 }
5692 ssb_set_devtypedata(sdev, wl);
5693 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5694
e4d6b795
MB		 5695 err = b43_one_core_attach(dev, wl);
5696 if (err)
8f15e287 5697 goto err_ssb_wireless_exit;
e4d6b795 5698
6b6fa586
LF		 5699 /* setup and start work to load firmware */
5700 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5701 schedule_work(&wl->firmware_load);
e4d6b795 5702
e4d6b795
MB		 5703 return err;
5704
8f15e287
RM		 5705err_ssb_wireless_exit:
5706 b43_wireless_exit(dev, wl);
5707err_ssb_kfree_dev:
5708 kfree(dev);
e4d6b795
MB		 5709 return err;
5710}
5711
aa63418a 5712static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5713{
aa63418a
RM		 5714 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5715 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5716 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5717
3bf0a32e
MB		 5718 /* We must cancel any work here before unregistering from ieee80211,
5719 * as the ieee80211 unreg will destroy the workqueue. */
5720 cancel_work_sync(&wldev->restart_work);
63a02ce1 5721 cancel_work_sync(&wl->firmware_load);
3bf0a32e 5722
e4d6b795 5723 B43_WARN_ON(!wl);
f89ff644
LF		 5724 if (!wldev->fw.ucode.data)
5725 return; /* NULL if firmware never loaded */
e64add27 5726 if (wl->current_dev == wldev && wl->hw_registred) {
82905ace 5727 b43_leds_stop(wldev);
e4d6b795 5728 ieee80211_unregister_hw(wl->hw);
403a3a13 5729 }
e4d6b795 5730
e61b52d1 5731 b43_one_core_detach(dev);
e4d6b795 5732
09164043
LF		 5733 /* Unregister HW RNG driver */
5734 b43_rng_exit(wl);
5735
644aa4d6
RM		 5736 b43_leds_unregister(wl);
5737 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5738}
5739
aec7ffdf
RM		 5740static struct ssb_driver b43_ssb_driver = {
5741 .name = KBUILD_MODNAME,
5742 .id_table = b43_ssb_tbl,
5743 .probe = b43_ssb_probe,
5744 .remove = b43_ssb_remove,
5745};
5746#endif /* CONFIG_B43_SSB */
5747
e4d6b795
MB		 5748/* Perform a hardware reset. This can be called from any context. */
5749void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5750{
5751 /* Must avoid requeueing, if we are in shutdown. */
5752 if (b43_status(dev) < B43_STAT_INITIALIZED)
5753 return;
5754 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5755 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5756}
5757
26bc783f
MB		 5758static void b43_print_driverinfo(void)
5759{
5760 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5761 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5762
5763#ifdef CONFIG_B43_PCI_AUTOSELECT
5764 feat_pci = "P";
5765#endif
5766#ifdef CONFIG_B43_PCMCIA
5767 feat_pcmcia = "M";
5768#endif
692d2c0f 5769#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5770 feat_nphy = "N";
5771#endif
5772#ifdef CONFIG_B43_LEDS
5773 feat_leds = "L";
3dbba8e2
AH		 5774#endif
5775#ifdef CONFIG_B43_SDIO
5776 feat_sdio = "S";
26bc783f
MB		 5777#endif
5778 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5779 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5780 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5781 feat_leds, feat_sdio);
26bc783f
MB		 5782}
5783
e4d6b795
MB		 5784static int __init b43_init(void)
5785{
5786 int err;
5787
5788 b43_debugfs_init();
5789 err = b43_pcmcia_init();
5790 if (err)
5791 goto err_dfs_exit;
3dbba8e2 5792 err = b43_sdio_init();
e4d6b795
MB		 5793 if (err)
5794 goto err_pcmcia_exit;
3c65ab62
RM		 5795#ifdef CONFIG_B43_BCMA
5796 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5797 if (err)
5798 goto err_sdio_exit;
3c65ab62 5799#endif
aec7ffdf 5800#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5801 err = ssb_driver_register(&b43_ssb_driver);
5802 if (err)
5803 goto err_bcma_driver_exit;
aec7ffdf 5804#endif
26bc783f 5805 b43_print_driverinfo();
e4d6b795
MB		 5806
5807 return err;
5808
aec7ffdf 5809#ifdef CONFIG_B43_SSB
3c65ab62 5810err_bcma_driver_exit:
aec7ffdf 5811#endif
3c65ab62
RM		 5812#ifdef CONFIG_B43_BCMA
5813 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5814err_sdio_exit:
3c65ab62 5815#endif
3dbba8e2 5816 b43_sdio_exit();
e4d6b795
MB		 5817err_pcmcia_exit:
5818 b43_pcmcia_exit();
5819err_dfs_exit:
5820 b43_debugfs_exit();
5821 return err;
5822}
5823
5824static void __exit b43_exit(void)
5825{
aec7ffdf 5826#ifdef CONFIG_B43_SSB
e4d6b795 5827 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5828#endif
3c65ab62
RM		 5829#ifdef CONFIG_B43_BCMA
5830 bcma_driver_unregister(&b43_bcma_driver);
5831#endif
3dbba8e2 5832 b43_sdio_exit();
e4d6b795
MB		 5833 b43_pcmcia_exit();
5834 b43_debugfs_exit();
5835}
5836
5837module_init(b43_init)
5838module_exit(b43_exit)
Linux kernel - Deliverables
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