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b43: enable radio 0x2057 rev 9 (AKA BCM43228) support
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
8960400e
RM		 116static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119
3c65ab62
RM		 120#ifdef CONFIG_B43_BCMA
121static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
15be8e89 125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
3c65ab62 126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
15be8e89
RM		 127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
3c65ab62
RM		 130 BCMA_CORETABLE_END
131};
132MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
133#endif
134
aec7ffdf 135#ifdef CONFIG_B43_SSB
e4d6b795
MB		 136static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 147 SSB_DEVTABLE_END
148};
e4d6b795 149MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 150#endif
e4d6b795
MB		 151
152/* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 157 { \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
160 .flags = (_flags), \
e4d6b795 161 }
8318d78a
JB		 162
163/*
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
166 */
e4d6b795 167static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 180};
181
182#define b43_a_ratetable (__b43_ratetable + 4)
183#define b43_a_ratetable_size 8
184#define b43_b_ratetable (__b43_ratetable + 0)
185#define b43_b_ratetable_size 4
186#define b43_g_ratetable (__b43_ratetable + 0)
187#define b43_g_ratetable_size 12
188
e9cdcb74 189#define CHAN2G(_channel, _freq, _flags) { \
bb1eeff1
MB		 190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
193 .flags = (_flags), \
194 .max_antenna_gain = 0, \
195 .max_power = 30, \
196}
96c755a3 197static struct ieee80211_channel b43_2ghz_chantable[] = {
e9cdcb74
RM		 198 CHAN2G(1, 2412, 0),
199 CHAN2G(2, 2417, 0),
200 CHAN2G(3, 2422, 0),
201 CHAN2G(4, 2427, 0),
202 CHAN2G(5, 2432, 0),
203 CHAN2G(6, 2437, 0),
204 CHAN2G(7, 2442, 0),
205 CHAN2G(8, 2447, 0),
206 CHAN2G(9, 2452, 0),
207 CHAN2G(10, 2457, 0),
208 CHAN2G(11, 2462, 0),
209 CHAN2G(12, 2467, 0),
210 CHAN2G(13, 2472, 0),
211 CHAN2G(14, 2484, 0),
bb1eeff1 212};
3695b932
RM		 213
214/* No support for the last 3 channels (12, 13, 14) */
215#define b43_2ghz_chantable_limited_size 11
e9cdcb74 216#undef CHAN2G
bb1eeff1 217
91211739
RM		 218#define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
222 .flags = (_flags), \
223 .max_antenna_gain = 0, \
224 .max_power = 30, \
225}
bb1eeff1
MB		 226#define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
230 .flags = (_flags), \
231 .max_antenna_gain = 0, \
232 .max_power = 30, \
233}
234static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
91211739
RM		 235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
246 CHAN4G(228, 0),
bb1eeff1
MB		 247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
91211739 290 CHAN5G(182, 0),
e4d6b795
MB		 291};
292
bb1eeff1
MB		 293static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
294 CHAN5G(34, 0), CHAN5G(36, 0),
295 CHAN5G(38, 0), CHAN5G(40, 0),
296 CHAN5G(42, 0), CHAN5G(44, 0),
297 CHAN5G(46, 0), CHAN5G(48, 0),
298 CHAN5G(52, 0), CHAN5G(56, 0),
299 CHAN5G(60, 0), CHAN5G(64, 0),
300 CHAN5G(100, 0), CHAN5G(104, 0),
301 CHAN5G(108, 0), CHAN5G(112, 0),
302 CHAN5G(116, 0), CHAN5G(120, 0),
303 CHAN5G(124, 0), CHAN5G(128, 0),
304 CHAN5G(132, 0), CHAN5G(136, 0),
305 CHAN5G(140, 0), CHAN5G(149, 0),
306 CHAN5G(153, 0), CHAN5G(157, 0),
307 CHAN5G(161, 0), CHAN5G(165, 0),
308 CHAN5G(184, 0), CHAN5G(188, 0),
309 CHAN5G(192, 0), CHAN5G(196, 0),
310 CHAN5G(200, 0), CHAN5G(204, 0),
311 CHAN5G(208, 0), CHAN5G(212, 0),
312 CHAN5G(216, 0),
313};
91211739 314#undef CHAN4G
bb1eeff1
MB		 315#undef CHAN5G
316
317static struct ieee80211_supported_band b43_band_5GHz_nphy = {
318 .band = IEEE80211_BAND_5GHZ,
319 .channels = b43_5ghz_nphy_chantable,
320 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
321 .bitrates = b43_a_ratetable,
322 .n_bitrates = b43_a_ratetable_size,
e4d6b795 323};
8318d78a 324
bb1eeff1
MB		 325static struct ieee80211_supported_band b43_band_5GHz_aphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_aphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
8318d78a 331};
e4d6b795 332
8318d78a 333static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 334 .band = IEEE80211_BAND_2GHZ,
335 .channels = b43_2ghz_chantable,
336 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
337 .bitrates = b43_g_ratetable,
338 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 339};
340
3695b932
RM		 341static struct ieee80211_supported_band b43_band_2ghz_limited = {
342 .band = IEEE80211_BAND_2GHZ,
343 .channels = b43_2ghz_chantable,
344 .n_channels = b43_2ghz_chantable_limited_size,
345 .bitrates = b43_g_ratetable,
346 .n_bitrates = b43_g_ratetable_size,
347};
348
e4d6b795
MB		 349static void b43_wireless_core_exit(struct b43_wldev *dev);
350static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 351static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 352static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 353static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
354 struct ieee80211_vif *vif,
355 struct ieee80211_bss_conf *conf,
356 u32 changed);
e4d6b795
MB		 357
358static int b43_ratelimit(struct b43_wl *wl)
359{
360 if (!wl || !wl->current_dev)
361 return 1;
362 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
363 return 1;
364 /* We are up and running.
365 * Ratelimit the messages to avoid DoS over the net. */
366 return net_ratelimit();
367}
368
369void b43info(struct b43_wl *wl, const char *fmt, ...)
370{
5b736d42 371 struct va_format vaf;
e4d6b795
MB		 372 va_list args;
373
060210f9
MB		 374 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
375 return;
e4d6b795
MB		 376 if (!b43_ratelimit(wl))
377 return;
5b736d42 378
e4d6b795 379 va_start(args, fmt);
5b736d42
JP		 380
381 vaf.fmt = fmt;
382 vaf.va = &args;
383
384 printk(KERN_INFO "b43-%s: %pV",
385 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
386
e4d6b795
MB		 387 va_end(args);
388}
389
390void b43err(struct b43_wl *wl, const char *fmt, ...)
391{
5b736d42 392 struct va_format vaf;
e4d6b795
MB		 393 va_list args;
394
060210f9
MB		 395 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
396 return;
e4d6b795
MB		 397 if (!b43_ratelimit(wl))
398 return;
5b736d42 399
e4d6b795 400 va_start(args, fmt);
5b736d42
JP		 401
402 vaf.fmt = fmt;
403 vaf.va = &args;
404
405 printk(KERN_ERR "b43-%s ERROR: %pV",
406 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
407
e4d6b795
MB		 408 va_end(args);
409}
410
411void b43warn(struct b43_wl *wl, const char *fmt, ...)
412{
5b736d42 413 struct va_format vaf;
e4d6b795
MB		 414 va_list args;
415
060210f9
MB		 416 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
417 return;
e4d6b795
MB		 418 if (!b43_ratelimit(wl))
419 return;
5b736d42 420
e4d6b795 421 va_start(args, fmt);
5b736d42
JP		 422
423 vaf.fmt = fmt;
424 vaf.va = &args;
425
426 printk(KERN_WARNING "b43-%s warning: %pV",
427 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
428
e4d6b795
MB		 429 va_end(args);
430}
431
e4d6b795
MB		 432void b43dbg(struct b43_wl *wl, const char *fmt, ...)
433{
5b736d42 434 struct va_format vaf;
e4d6b795
MB		 435 va_list args;
436
060210f9
MB		 437 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
438 return;
5b736d42 439
e4d6b795 440 va_start(args, fmt);
5b736d42
JP		 441
442 vaf.fmt = fmt;
443 vaf.va = &args;
444
445 printk(KERN_DEBUG "b43-%s debug: %pV",
446 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
447
e4d6b795
MB		 448 va_end(args);
449}
e4d6b795
MB		 450
451static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
452{
453 u32 macctl;
454
455 B43_WARN_ON(offset % 4 != 0);
456
457 macctl = b43_read32(dev, B43_MMIO_MACCTL);
458 if (macctl & B43_MACCTL_BE)
459 val = swab32(val);
460
461 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
462 mmiowb();
463 b43_write32(dev, B43_MMIO_RAM_DATA, val);
464}
465
280d0e16
MB		 466static inline void b43_shm_control_word(struct b43_wldev *dev,
467 u16 routing, u16 offset)
e4d6b795
MB		 468{
469 u32 control;
470
471 /* "offset" is the WORD offset. */
e4d6b795
MB		 472 control = routing;
473 control <<= 16;
474 control |= offset;
475 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
476}
477
69eddc8a 478u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 479{
480 u32 ret;
481
482 if (routing == B43_SHM_SHARED) {
483 B43_WARN_ON(offset & 0x0001);
484 if (offset & 0x0003) {
485 /* Unaligned access */
486 b43_shm_control_word(dev, routing, offset >> 2);
487 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 488 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 489 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 490
280d0e16 491 goto out;
e4d6b795
MB		 492 }
493 offset >>= 2;
494 }
495 b43_shm_control_word(dev, routing, offset);
496 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 497out:
e4d6b795
MB		 498 return ret;
499}
500
69eddc8a 501u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 502{
503 u16 ret;
504
e4d6b795
MB		 505 if (routing == B43_SHM_SHARED) {
506 B43_WARN_ON(offset & 0x0001);
507 if (offset & 0x0003) {
508 /* Unaligned access */
509 b43_shm_control_word(dev, routing, offset >> 2);
510 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
511
280d0e16 512 goto out;
e4d6b795
MB		 513 }
514 offset >>= 2;
515 }
516 b43_shm_control_word(dev, routing, offset);
517 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 518out:
e4d6b795
MB		 519 return ret;
520}
521
69eddc8a 522void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 523{
e4d6b795
MB		 524 if (routing == B43_SHM_SHARED) {
525 B43_WARN_ON(offset & 0x0001);
526 if (offset & 0x0003) {
527 /* Unaligned access */
528 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 529 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 530 value & 0xFFFF);
e4d6b795 531 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 532 b43_write16(dev, B43_MMIO_SHM_DATA,
533 (value >> 16) & 0xFFFF);
6bbc321a 534 return;
e4d6b795
MB		 535 }
536 offset >>= 2;
537 }
538 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 539 b43_write32(dev, B43_MMIO_SHM_DATA, value);
540}
541
69eddc8a 542void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 543{
e4d6b795
MB		 544 if (routing == B43_SHM_SHARED) {
545 B43_WARN_ON(offset & 0x0001);
546 if (offset & 0x0003) {
547 /* Unaligned access */
548 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 549 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 550 return;
e4d6b795
MB		 551 }
552 offset >>= 2;
553 }
554 b43_shm_control_word(dev, routing, offset);
e4d6b795 555 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 556}
557
e4d6b795 558/* Read HostFlags */
99da185a 559u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 560{
35f0d354 561 u64 ret;
e4d6b795 562
6e6a2cd5 563 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
e4d6b795 564 ret <<= 16;
6e6a2cd5 565 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
35f0d354 566 ret <<= 16;
6e6a2cd5 567 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
e4d6b795
MB		 568
569 return ret;
570}
571
572/* Write HostFlags */
35f0d354 573void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 574{
35f0d354
MB		 575 u16 lo, mi, hi;
576
577 lo = (value & 0x00000000FFFFULL);
578 mi = (value & 0x0000FFFF0000ULL) >> 16;
579 hi = (value & 0xFFFF00000000ULL) >> 32;
6e6a2cd5
RM		 580 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
581 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
582 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
e4d6b795
MB		 583}
584
403a3a13
MB		 585/* Read the firmware capabilities bitmask (Opensource firmware only) */
586static u16 b43_fwcapa_read(struct b43_wldev *dev)
587{
588 B43_WARN_ON(!dev->fw.opensource);
589 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
590}
591
3ebbbb56 592void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 593{
3ebbbb56
MB		 594 u32 low, high;
595
21d889d4 596 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 597
598 /* The hardware guarantees us an atomic read, if we
599 * read the low register first. */
600 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
601 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
602
603 *tsf = high;
604 *tsf <<= 32;
605 *tsf |= low;
e4d6b795
MB		 606}
607
608static void b43_time_lock(struct b43_wldev *dev)
609{
5056635c 610 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 611 /* Commit the write */
612 b43_read32(dev, B43_MMIO_MACCTL);
613}
614
615static void b43_time_unlock(struct b43_wldev *dev)
616{
5056635c 617 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 618 /* Commit the write */
619 b43_read32(dev, B43_MMIO_MACCTL);
620}
621
622static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
623{
3ebbbb56
MB		 624 u32 low, high;
625
21d889d4 626 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 627
628 low = tsf;
629 high = (tsf >> 32);
630 /* The hardware guarantees us an atomic write, if we
631 * write the low register first. */
632 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
633 mmiowb();
634 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
635 mmiowb();
e4d6b795
MB		 636}
637
638void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
639{
640 b43_time_lock(dev);
641 b43_tsf_write_locked(dev, tsf);
642 b43_time_unlock(dev);
643}
644
645static
99da185a 646void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 647{
648 static const u8 zero_addr[ETH_ALEN] = { 0 };
649 u16 data;
650
651 if (!mac)
652 mac = zero_addr;
653
654 offset |= 0x0020;
655 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
656
657 data = mac[0];
658 data |= mac[1] << 8;
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
660 data = mac[2];
661 data |= mac[3] << 8;
662 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
663 data = mac[4];
664 data |= mac[5] << 8;
665 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
666}
667
668static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
669{
670 const u8 *mac;
671 const u8 *bssid;
672 u8 mac_bssid[ETH_ALEN * 2];
673 int i;
674 u32 tmp;
675
676 bssid = dev->wl->bssid;
677 mac = dev->wl->mac_addr;
678
679 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
680
681 memcpy(mac_bssid, mac, ETH_ALEN);
682 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
683
684 /* Write our MAC address and BSSID to template ram */
685 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
686 tmp = (u32) (mac_bssid[i + 0]);
687 tmp |= (u32) (mac_bssid[i + 1]) << 8;
688 tmp |= (u32) (mac_bssid[i + 2]) << 16;
689 tmp |= (u32) (mac_bssid[i + 3]) << 24;
690 b43_ram_write(dev, 0x20 + i, tmp);
691 }
692}
693
4150c572 694static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 695{
e4d6b795 696 b43_write_mac_bssid_templates(dev);
4150c572 697 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 698}
699
700static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
701{
702 /* slot_time is in usec. */
b6c3f5be
LF		 703 /* This test used to exit for all but a G PHY. */
704 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 705 return;
b6c3f5be
LF		 706 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
707 /* Shared memory location 0x0010 is the slot time and should be
708 * set to slot_time; however, this register is initially 0 and changing
709 * the value adversely affects the transmit rate for BCM4311
710 * devices. Until this behavior is unterstood, delete this step
711 *
712 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
713 */
e4d6b795
MB		 714}
715
716static void b43_short_slot_timing_enable(struct b43_wldev *dev)
717{
718 b43_set_slot_time(dev, 9);
e4d6b795
MB		 719}
720
721static void b43_short_slot_timing_disable(struct b43_wldev *dev)
722{
723 b43_set_slot_time(dev, 20);
e4d6b795
MB		 724}
725
e4d6b795 726/* DummyTransmission function, as documented on
2f19c287 727 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 728 */
2f19c287 729void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 730{
731 struct b43_phy *phy = &dev->phy;
732 unsigned int i, max_loop;
733 u16 value;
734 u32 buffer[5] = {
735 0x00000000,
736 0x00D40000,
737 0x00000000,
738 0x01000000,
739 0x00000000,
740 };
741
2f19c287 742 if (ofdm) {
e4d6b795
MB		 743 max_loop = 0x1E;
744 buffer[0] = 0x000201CC;
2f19c287 745 } else {
e4d6b795
MB		 746 max_loop = 0xFA;
747 buffer[0] = 0x000B846E;
e4d6b795
MB		 748 }
749
750 for (i = 0; i < 5; i++)
751 b43_ram_write(dev, i * 4, buffer[i]);
752
7955d87f
RM		 753 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
754
21d889d4 755 if (dev->dev->core_rev < 11)
7955d87f 756 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 757 else
7955d87f
RM		 758 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
759
2f19c287 760 value = (ofdm ? 0x41 : 0x40);
7955d87f 761 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 762 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
763 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 764 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
765
766 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
767 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
768
769 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
770 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
771 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
772 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 773
774 if (!pa_on && phy->type == B43_PHYTYPE_N)
775 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 776
777 switch (phy->type) {
778 case B43_PHYTYPE_N:
93dbd828 779 case B43_PHYTYPE_LCN:
7955d87f 780 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 781 break;
782 case B43_PHYTYPE_LP:
7955d87f 783 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 784 break;
785 default:
7955d87f 786 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 787 }
93dbd828 788 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 789
790 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
791 b43_radio_write16(dev, 0x0051, 0x0017);
792 for (i = 0x00; i < max_loop; i++) {
7955d87f 793 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 794 if (value & 0x0080)
795 break;
796 udelay(10);
797 }
798 for (i = 0x00; i < 0x0A; i++) {
7955d87f 799 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 800 if (value & 0x0400)
801 break;
802 udelay(10);
803 }
1d280ddc 804 for (i = 0x00; i < 0x19; i++) {
7955d87f 805 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 806 if (!(value & 0x0100))
807 break;
808 udelay(10);
809 }
810 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
811 b43_radio_write16(dev, 0x0051, 0x0037);
812}
813
814static void key_write(struct b43_wldev *dev,
99da185a 815 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 816{
817 unsigned int i;
818 u32 offset;
819 u16 value;
820 u16 kidx;
821
822 /* Key index/algo block */
823 kidx = b43_kidx_to_fw(dev, index);
824 value = ((kidx << 4) | algorithm);
825 b43_shm_write16(dev, B43_SHM_SHARED,
826 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
827
828 /* Write the key to the Key Table Pointer offset */
829 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
830 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
831 value = key[i];
832 value |= (u16) (key[i + 1]) << 8;
833 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
834 }
835}
836
99da185a 837static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 838{
839 u32 addrtmp[2] = { 0, 0, };
66d2d089 840 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 841
842 if (b43_new_kidx_api(dev))
66d2d089 843 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 844
66d2d089
MB		 845 B43_WARN_ON(index < pairwise_keys_start);
846 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 847 * Physical mac 0 is mapped to physical key 4 or 8, depending
848 * on the firmware version.
849 * So we must adjust the index here.
850 */
66d2d089
MB		 851 index -= pairwise_keys_start;
852 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 853
854 if (addr) {
855 addrtmp[0] = addr[0];
856 addrtmp[0] |= ((u32) (addr[1]) << 8);
857 addrtmp[0] |= ((u32) (addr[2]) << 16);
858 addrtmp[0] |= ((u32) (addr[3]) << 24);
859 addrtmp[1] = addr[4];
860 addrtmp[1] |= ((u32) (addr[5]) << 8);
861 }
862
66d2d089
MB		 863 /* Receive match transmitter address (RCMTA) mechanism */
864 b43_shm_write32(dev, B43_SHM_RCMTA,
865 (index * 2) + 0, addrtmp[0]);
866 b43_shm_write16(dev, B43_SHM_RCMTA,
867 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 868}
869
035d0243 870/* The ucode will use phase1 key with TEK key to decrypt rx packets.
871 * When a packet is received, the iv32 is checked.
872 * - if it doesn't the packet is returned without modification (and software
873 * decryption can be done). That's what happen when iv16 wrap.
874 * - if it does, the rc4 key is computed, and decryption is tried.
875 * Either it will success and B43_RX_MAC_DEC is returned,
876 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
877 * and the packet is not usable (it got modified by the ucode).
878 * So in order to never have B43_RX_MAC_DECERR, we should provide
879 * a iv32 and phase1key that match. Because we drop packets in case of
880 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
881 * packets will be lost without higher layer knowing (ie no resync possible
882 * until next wrap).
883 *
884 * NOTE : this should support 50 key like RCMTA because
885 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
886 */
887static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
888 u16 *phase1key)
889{
890 unsigned int i;
891 u32 offset;
892 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
893
894 if (!modparam_hwtkip)
895 return;
896
897 if (b43_new_kidx_api(dev))
898 pairwise_keys_start = B43_NR_GROUP_KEYS;
899
900 B43_WARN_ON(index < pairwise_keys_start);
901 /* We have four default TX keys and possibly four default RX keys.
902 * Physical mac 0 is mapped to physical key 4 or 8, depending
903 * on the firmware version.
904 * So we must adjust the index here.
905 */
906 index -= pairwise_keys_start;
907 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
908
909 if (b43_debug(dev, B43_DBG_KEYS)) {
910 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
911 index, iv32);
912 }
913 /* Write the key to the RX tkip shared mem */
914 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
915 for (i = 0; i < 10; i += 2) {
916 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
917 phase1key ? phase1key[i / 2] : 0);
918 }
919 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
920 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
921}
922
923static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 924 struct ieee80211_vif *vif,
925 struct ieee80211_key_conf *keyconf,
926 struct ieee80211_sta *sta,
927 u32 iv32, u16 *phase1key)
035d0243 928{
929 struct b43_wl *wl = hw_to_b43_wl(hw);
930 struct b43_wldev *dev;
931 int index = keyconf->hw_key_idx;
932
933 if (B43_WARN_ON(!modparam_hwtkip))
934 return;
935
96869a39
MB		 936 /* This is only called from the RX path through mac80211, where
937 * our mutex is already locked. */
938 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 939 dev = wl->current_dev;
96869a39 940 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 941
942 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
943
944 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 945 /* only pairwise TKIP keys are supported right now */
946 if (WARN_ON(!sta))
96869a39 947 return;
b3fbdcf4 948 keymac_write(dev, index, sta->addr);
035d0243 949}
950
e4d6b795
MB		 951static void do_key_write(struct b43_wldev *dev,
952 u8 index, u8 algorithm,
99da185a 953 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 954{
955 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 956 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 957
958 if (b43_new_kidx_api(dev))
66d2d089 959 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 960
66d2d089 961 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 962 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
963
66d2d089 964 if (index >= pairwise_keys_start)
e4d6b795 965 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 966 if (algorithm == B43_SEC_ALGO_TKIP) {
967 /*
968 * We should provide an initial iv32, phase1key pair.
969 * We could start with iv32=0 and compute the corresponding
970 * phase1key, but this means calling ieee80211_get_tkip_key
971 * with a fake skb (or export other tkip function).
972 * Because we are lazy we hope iv32 won't start with
973 * 0xffffffff and let's b43_op_update_tkip_key provide a
974 * correct pair.
975 */
976 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
977 } else if (index >= pairwise_keys_start) /* clear it */
978 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 979 if (key)
980 memcpy(buf, key, key_len);
981 key_write(dev, index, algorithm, buf);
66d2d089 982 if (index >= pairwise_keys_start)
e4d6b795
MB		 983 keymac_write(dev, index, mac_addr);
984
985 dev->key[index].algorithm = algorithm;
986}
987
988static int b43_key_write(struct b43_wldev *dev,
989 int index, u8 algorithm,
99da185a
JD		 990 const u8 *key, size_t key_len,
991 const u8 *mac_addr,
e4d6b795
MB		 992 struct ieee80211_key_conf *keyconf)
993{
994 int i;
66d2d089 995 int pairwise_keys_start;
e4d6b795 996
035d0243 997 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
998 * - Temporal Encryption Key (128 bits)
999 * - Temporal Authenticator Tx MIC Key (64 bits)
1000 * - Temporal Authenticator Rx MIC Key (64 bits)
1001 *
1002 * Hardware only store TEK
1003 */
1004 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1005 key_len = 16;
e4d6b795
MB		 1006 if (key_len > B43_SEC_KEYSIZE)
1007 return -EINVAL;
66d2d089 1008 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 1009 /* Check that we don't already have this key. */
1010 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1011 }
1012 if (index < 0) {
e808e586 1013 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 1014 if (b43_new_kidx_api(dev))
66d2d089 1015 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 1016 else
66d2d089
MB		 1017 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1018 for (i = pairwise_keys_start;
1019 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1020 i++) {
1021 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 1022 if (!dev->key[i].keyconf) {
1023 /* found empty */
1024 index = i;
1025 break;
1026 }
1027 }
1028 if (index < 0) {
e808e586 1029 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1030 return -ENOSPC;
1031 }
1032 } else
1033 B43_WARN_ON(index > 3);
1034
1035 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1036 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1037 /* Default RX key */
1038 B43_WARN_ON(mac_addr);
1039 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1040 }
1041 keyconf->hw_key_idx = index;
1042 dev->key[index].keyconf = keyconf;
1043
1044 return 0;
1045}
1046
1047static int b43_key_clear(struct b43_wldev *dev, int index)
1048{
66d2d089 1049 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1050 return -EINVAL;
1051 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1052 NULL, B43_SEC_KEYSIZE, NULL);
1053 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1054 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1055 NULL, B43_SEC_KEYSIZE, NULL);
1056 }
1057 dev->key[index].keyconf = NULL;
1058
1059 return 0;
1060}
1061
1062static void b43_clear_keys(struct b43_wldev *dev)
1063{
66d2d089 1064 int i, count;
e4d6b795 1065
66d2d089
MB		 1066 if (b43_new_kidx_api(dev))
1067 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1068 else
1069 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1070 for (i = 0; i < count; i++)
e4d6b795
MB		 1071 b43_key_clear(dev, i);
1072}
1073
9cf7f247
MB		 1074static void b43_dump_keymemory(struct b43_wldev *dev)
1075{
66d2d089 1076 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1077 u8 mac[ETH_ALEN];
1078 u16 algo;
1079 u32 rcmta0;
1080 u16 rcmta1;
1081 u64 hf;
1082 struct b43_key *key;
1083
1084 if (!b43_debug(dev, B43_DBG_KEYS))
1085 return;
1086
1087 hf = b43_hf_read(dev);
1088 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1089 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1090 if (b43_new_kidx_api(dev)) {
1091 pairwise_keys_start = B43_NR_GROUP_KEYS;
1092 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1093 } else {
1094 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1095 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1096 }
1097 for (index = 0; index < count; index++) {
9cf7f247
MB		 1098 key = &(dev->key[index]);
1099 printk(KERN_DEBUG "Key slot %02u: %s",
1100 index, (key->keyconf == NULL) ? " " : "*");
1101 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1102 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1103 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1104 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1105 }
1106
1107 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1108 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1109 printk(" Algo: %04X/%02X", algo, key->algorithm);
1110
66d2d089 1111 if (index >= pairwise_keys_start) {
035d0243 1112 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1113 printk(" TKIP: ");
1114 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1115 for (i = 0; i < 14; i += 2) {
1116 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1117 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1118 }
1119 }
9cf7f247 1120 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1121 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1122 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1123 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1124 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1125 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1126 printk(" MAC: %pM", mac);
9cf7f247
MB		 1127 } else
1128 printk(" DEFAULT KEY");
1129 printk("\n");
1130 }
1131}
1132
e4d6b795
MB		 1133void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1134{
1135 u32 macctl;
1136 u16 ucstat;
1137 bool hwps;
1138 bool awake;
1139 int i;
1140
1141 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1142 (ps_flags & B43_PS_DISABLED));
1143 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1144
1145 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1146 hwps = true;
e4d6b795 1147 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1148 hwps = false;
e4d6b795
MB		 1149 } else {
1150 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1151 // and thus is not an AP and we are associated, set bit 25
1152 }
1153 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1154 awake = true;
e4d6b795 1155 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1156 awake = false;
e4d6b795
MB		 1157 } else {
1158 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1159 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1160 // successful, set bit26
1161 }
1162
1163/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1164 hwps = false;
1165 awake = true;
e4d6b795
MB		 1166
1167 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1168 if (hwps)
1169 macctl |= B43_MACCTL_HWPS;
1170 else
1171 macctl &= ~B43_MACCTL_HWPS;
1172 if (awake)
1173 macctl |= B43_MACCTL_AWAKE;
1174 else
1175 macctl &= ~B43_MACCTL_AWAKE;
1176 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1177 /* Commit write */
1178 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1179 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1180 /* Wait for the microcode to wake up. */
1181 for (i = 0; i < 100; i++) {
1182 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1183 B43_SHM_SH_UCODESTAT);
1184 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1185 break;
1186 udelay(10);
1187 }
1188 }
1189}
1190
42c9a458 1191#ifdef CONFIG_B43_BCMA
49173592 1192static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1193{
49173592 1194 u32 flags;
42c9a458 1195
49173592
RM		 1196 /* Put PHY into reset */
1197 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1198 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1199 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1200 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1201 udelay(2);
1202
50c1b59e 1203 b43_phy_take_out_of_reset(dev);
49173592 1204}
42c9a458 1205
49173592
RM		 1206static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1207{
88cceab5
RM		 1208 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1209 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1210 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1211 B43_BCMA_CLKCTLST_PHY_PLL_ST;
6b9e03e6
RM		 1212 u32 flags;
1213
1214 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1215 if (gmode)
1216 flags |= B43_BCMA_IOCTL_GMODE;
1217 b43_device_enable(dev, flags);
88cceab5 1218
49173592
RM		 1219 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1220 b43_bcma_phy_reset(dev);
88cceab5 1221 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
42c9a458
RM		 1222}
1223#endif
1224
bd7c8a59 1225#ifdef CONFIG_B43_SSB
4da909e7 1226static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1227{
4da909e7 1228 u32 flags = 0;
e4d6b795 1229
4da909e7
RM		 1230 if (gmode)
1231 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1232 flags |= B43_TMSLOW_PHYCLKEN;
1233 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1234 if (dev->phy.type == B43_PHYTYPE_N)
1235 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1236 b43_device_enable(dev, flags);
e4d6b795
MB		 1237 msleep(2); /* Wait for the PLL to turn on. */
1238
50c1b59e 1239 b43_phy_take_out_of_reset(dev);
1495298d 1240}
bd7c8a59 1241#endif
1495298d 1242
4da909e7 1243void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1244{
1245 u32 macctl;
1246
6cbab0d9 1247 switch (dev->dev->bus_type) {
42c9a458
RM		 1248#ifdef CONFIG_B43_BCMA
1249 case B43_BUS_BCMA:
1250 b43_bcma_wireless_core_reset(dev, gmode);
1251 break;
1252#endif
6cbab0d9
RM		 1253#ifdef CONFIG_B43_SSB
1254 case B43_BUS_SSB:
1255 b43_ssb_wireless_core_reset(dev, gmode);
1256 break;
1257#endif
1258 }
e4d6b795 1259
fb11137a
MB		 1260 /* Turn Analog ON, but only if we already know the PHY-type.
1261 * This protects against very early setup where we don't know the
1262 * PHY-type, yet. wireless_core_reset will be called once again later,
1263 * when we know the PHY-type. */
1264 if (dev->phy.ops)
cb24f57f 1265 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1266
1267 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1268 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1269 if (gmode)
e4d6b795
MB		 1270 macctl |= B43_MACCTL_GMODE;
1271 macctl |= B43_MACCTL_IHR_ENABLED;
1272 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1273}
1274
1275static void handle_irq_transmit_status(struct b43_wldev *dev)
1276{
1277 u32 v0, v1;
1278 u16 tmp;
1279 struct b43_txstatus stat;
1280
1281 while (1) {
1282 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1283 if (!(v0 & 0x00000001))
1284 break;
1285 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1286
1287 stat.cookie = (v0 >> 16);
1288 stat.seq = (v1 & 0x0000FFFF);
1289 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1290 tmp = (v0 & 0x0000FFFF);
1291 stat.frame_count = ((tmp & 0xF000) >> 12);
1292 stat.rts_count = ((tmp & 0x0F00) >> 8);
1293 stat.supp_reason = ((tmp & 0x001C) >> 2);
1294 stat.pm_indicated = !!(tmp & 0x0080);
1295 stat.intermediate = !!(tmp & 0x0040);
1296 stat.for_ampdu = !!(tmp & 0x0020);
1297 stat.acked = !!(tmp & 0x0002);
1298
1299 b43_handle_txstatus(dev, &stat);
1300 }
1301}
1302
1303static void drain_txstatus_queue(struct b43_wldev *dev)
1304{
1305 u32 dummy;
1306
21d889d4 1307 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1308 return;
1309 /* Read all entries from the microcode TXstatus FIFO
1310 * and throw them away.
1311 */
1312 while (1) {
1313 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1314 if (!(dummy & 0x00000001))
1315 break;
1316 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1317 }
1318}
1319
1320static u32 b43_jssi_read(struct b43_wldev *dev)
1321{
1322 u32 val = 0;
1323
5c1da23b 1324 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
e4d6b795 1325 val <<= 16;
5c1da23b 1326 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
e4d6b795
MB		 1327
1328 return val;
1329}
1330
1331static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1332{
5c1da23b
HM		 1333 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1334 (jssi & 0x0000FFFF));
1335 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1336 (jssi & 0xFFFF0000) >> 16);
e4d6b795
MB		 1337}
1338
1339static void b43_generate_noise_sample(struct b43_wldev *dev)
1340{
1341 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1342 b43_write32(dev, B43_MMIO_MACCMD,
1343 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1344}
1345
1346static void b43_calculate_link_quality(struct b43_wldev *dev)
1347{
1348 /* Top half of Link Quality calculation. */
1349
ef1a628d
MB		 1350 if (dev->phy.type != B43_PHYTYPE_G)
1351 return;
e4d6b795
MB		 1352 if (dev->noisecalc.calculation_running)
1353 return;
3db1cd5c 1354 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1355 dev->noisecalc.nr_samples = 0;
1356
1357 b43_generate_noise_sample(dev);
1358}
1359
1360static void handle_irq_noise(struct b43_wldev *dev)
1361{
ef1a628d 1362 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1363 u16 tmp;
1364 u8 noise[4];
1365 u8 i, j;
1366 s32 average;
1367
1368 /* Bottom half of Link Quality calculation. */
1369
ef1a628d
MB		 1370 if (dev->phy.type != B43_PHYTYPE_G)
1371 return;
1372
98a3b2fe
MB		 1373 /* Possible race condition: It might be possible that the user
1374 * changed to a different channel in the meantime since we
1375 * started the calculation. We ignore that fact, since it's
1376 * not really that much of a problem. The background noise is
1377 * an estimation only anyway. Slightly wrong results will get damped
1378 * by the averaging of the 8 sample rounds. Additionally the
1379 * value is shortlived. So it will be replaced by the next noise
1380 * calculation round soon. */
1381
e4d6b795 1382 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1383 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1384 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1385 noise[2] == 0x7F || noise[3] == 0x7F)
1386 goto generate_new;
1387
1388 /* Get the noise samples. */
1389 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1390 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1391 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1392 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1393 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1394 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1395 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1396 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1397 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1398 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1399 dev->noisecalc.nr_samples++;
1400 if (dev->noisecalc.nr_samples == 8) {
1401 /* Calculate the Link Quality by the noise samples. */
1402 average = 0;
1403 for (i = 0; i < 8; i++) {
1404 for (j = 0; j < 4; j++)
1405 average += dev->noisecalc.samples[i][j];
1406 }
1407 average /= (8 * 4);
1408 average *= 125;
1409 average += 64;
1410 average /= 128;
1411 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1412 tmp = (tmp / 128) & 0x1F;
1413 if (tmp >= 8)
1414 average += 2;
1415 else
1416 average -= 25;
1417 if (tmp == 8)
1418 average -= 72;
1419 else
1420 average -= 48;
1421
1422 dev->stats.link_noise = average;
3db1cd5c 1423 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1424 return;
1425 }
98a3b2fe 1426generate_new:
e4d6b795
MB		 1427 b43_generate_noise_sample(dev);
1428}
1429
1430static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1431{
05c914fe 1432 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1433 ///TODO: PS TBTT
1434 } else {
1435 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1436 b43_power_saving_ctl_bits(dev, 0);
1437 }
05c914fe 1438 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1439 dev->dfq_valid = true;
e4d6b795
MB		 1440}
1441
1442static void handle_irq_atim_end(struct b43_wldev *dev)
1443{
aa6c7ae2
MB		 1444 if (dev->dfq_valid) {
1445 b43_write32(dev, B43_MMIO_MACCMD,
1446 b43_read32(dev, B43_MMIO_MACCMD)
1447 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1448 dev->dfq_valid = false;
aa6c7ae2 1449 }
e4d6b795
MB		 1450}
1451
1452static void handle_irq_pmq(struct b43_wldev *dev)
1453{
1454 u32 tmp;
1455
1456 //TODO: AP mode.
1457
1458 while (1) {
1459 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1460 if (!(tmp & 0x00000008))
1461 break;
1462 }
1463 /* 16bit write is odd, but correct. */
1464 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1465}
1466
1467static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1468 const u8 *data, u16 size,
e4d6b795
MB		 1469 u16 ram_offset,
1470 u16 shm_size_offset, u8 rate)
1471{
1472 u32 i, tmp;
1473 struct b43_plcp_hdr4 plcp;
1474
1475 plcp.data = 0;
1476 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1477 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1478 ram_offset += sizeof(u32);
1479 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1480 * So leave the first two bytes of the next write blank.
1481 */
1482 tmp = (u32) (data[0]) << 16;
1483 tmp |= (u32) (data[1]) << 24;
1484 b43_ram_write(dev, ram_offset, tmp);
1485 ram_offset += sizeof(u32);
1486 for (i = 2; i < size; i += sizeof(u32)) {
1487 tmp = (u32) (data[i + 0]);
1488 if (i + 1 < size)
1489 tmp |= (u32) (data[i + 1]) << 8;
1490 if (i + 2 < size)
1491 tmp |= (u32) (data[i + 2]) << 16;
1492 if (i + 3 < size)
1493 tmp |= (u32) (data[i + 3]) << 24;
1494 b43_ram_write(dev, ram_offset + i - 2, tmp);
1495 }
1496 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1497 size + sizeof(struct b43_plcp_hdr6));
1498}
1499
5042c507
MB		 1500/* Check if the use of the antenna that ieee80211 told us to
1501 * use is possible. This will fall back to DEFAULT.
1502 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1503u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1504 u8 antenna_nr)
1505{
1506 u8 antenna_mask;
1507
1508 if (antenna_nr == 0) {
1509 /* Zero means "use default antenna". That's always OK. */
1510 return 0;
1511 }
1512
1513 /* Get the mask of available antennas. */
1514 if (dev->phy.gmode)
0581483a 1515 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1516 else
0581483a 1517 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1518
1519 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1520 /* This antenna is not available. Fall back to default. */
1521 return 0;
1522 }
1523
1524 return antenna_nr;
1525}
1526
5042c507
MB		 1527/* Convert a b43 antenna number value to the PHY TX control value. */
1528static u16 b43_antenna_to_phyctl(int antenna)
1529{
1530 switch (antenna) {
1531 case B43_ANTENNA0:
1532 return B43_TXH_PHY_ANT0;
1533 case B43_ANTENNA1:
1534 return B43_TXH_PHY_ANT1;
1535 case B43_ANTENNA2:
1536 return B43_TXH_PHY_ANT2;
1537 case B43_ANTENNA3:
1538 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1539 case B43_ANTENNA_AUTO0:
1540 case B43_ANTENNA_AUTO1:
5042c507
MB		 1541 return B43_TXH_PHY_ANT01AUTO;
1542 }
1543 B43_WARN_ON(1);
1544 return 0;
1545}
1546
e4d6b795
MB		 1547static void b43_write_beacon_template(struct b43_wldev *dev,
1548 u16 ram_offset,
5042c507 1549 u16 shm_size_offset)
e4d6b795 1550{
47f76ca3 1551 unsigned int i, len, variable_len;
e66fee6a
MB		 1552 const struct ieee80211_mgmt *bcn;
1553 const u8 *ie;
3db1cd5c 1554 bool tim_found = false;
5042c507
MB		 1555 unsigned int rate;
1556 u16 ctl;
1557 int antenna;
e039fa4a 1558 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1559
e66fee6a 1560 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
c8e49556 1561 len = min_t(size_t, dev->wl->current_beacon->len,
e4d6b795 1562 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1563 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1564
1565 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1566 len, ram_offset, shm_size_offset, rate);
e66fee6a 1567
5042c507 1568 /* Write the PHY TX control parameters. */
0f4ac38b 1569 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1570 antenna = b43_antenna_to_phyctl(antenna);
1571 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1572 /* We can't send beacons with short preamble. Would get PHY errors. */
1573 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1574 ctl &= ~B43_TXH_PHY_ANT;
1575 ctl &= ~B43_TXH_PHY_ENC;
1576 ctl |= antenna;
1577 if (b43_is_cck_rate(rate))
1578 ctl |= B43_TXH_PHY_ENC_CCK;
1579 else
1580 ctl |= B43_TXH_PHY_ENC_OFDM;
1581 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1582
e66fee6a
MB		 1583 /* Find the position of the TIM and the DTIM_period value
1584 * and write them to SHM. */
1585 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1586 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1587 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1588 uint8_t ie_id, ie_len;
1589
1590 ie_id = ie[i];
1591 ie_len = ie[i + 1];
1592 if (ie_id == 5) {
1593 u16 tim_position;
1594 u16 dtim_period;
1595 /* This is the TIM Information Element */
1596
1597 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1598 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1599 break;
1600 /* A valid TIM is at least 4 bytes long. */
1601 if (ie_len < 4)
1602 break;
3db1cd5c 1603 tim_found = true;
e66fee6a
MB		 1604
1605 tim_position = sizeof(struct b43_plcp_hdr6);
1606 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1607 tim_position += i;
1608
1609 dtim_period = ie[i + 3];
1610
1611 b43_shm_write16(dev, B43_SHM_SHARED,
1612 B43_SHM_SH_TIMBPOS, tim_position);
1613 b43_shm_write16(dev, B43_SHM_SHARED,
1614 B43_SHM_SH_DTIMPER, dtim_period);
1615 break;
1616 }
1617 i += ie_len + 2;
1618 }
1619 if (!tim_found) {
04dea136
JB		 1620 /*
1621 * If ucode wants to modify TIM do it behind the beacon, this
1622 * will happen, for example, when doing mesh networking.
1623 */
1624 b43_shm_write16(dev, B43_SHM_SHARED,
1625 B43_SHM_SH_TIMBPOS,
1626 len + sizeof(struct b43_plcp_hdr6));
1627 b43_shm_write16(dev, B43_SHM_SHARED,
1628 B43_SHM_SH_DTIMPER, 0);
1629 }
1630 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1631}
1632
6b4bec01
MB		 1633static void b43_upload_beacon0(struct b43_wldev *dev)
1634{
1635 struct b43_wl *wl = dev->wl;
1636
1637 if (wl->beacon0_uploaded)
1638 return;
5c1da23b 1639 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
3db1cd5c 1640 wl->beacon0_uploaded = true;
6b4bec01
MB		 1641}
1642
1643static void b43_upload_beacon1(struct b43_wldev *dev)
1644{
1645 struct b43_wl *wl = dev->wl;
1646
1647 if (wl->beacon1_uploaded)
1648 return;
5c1da23b 1649 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
3db1cd5c 1650 wl->beacon1_uploaded = true;
6b4bec01
MB		 1651}
1652
c97a4ccc
MB		 1653static void handle_irq_beacon(struct b43_wldev *dev)
1654{
1655 struct b43_wl *wl = dev->wl;
1656 u32 cmd, beacon0_valid, beacon1_valid;
1657
05c914fe 1658 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1659 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1660 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1661 return;
1662
1663 /* This is the bottom half of the asynchronous beacon update. */
1664
1665 /* Ignore interrupt in the future. */
13790728 1666 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1667
1668 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1669 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1670 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1671
1672 /* Schedule interrupt manually, if busy. */
1673 if (beacon0_valid && beacon1_valid) {
1674 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1675 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1676 return;
1677 }
1678
6b4bec01
MB		 1679 if (unlikely(wl->beacon_templates_virgin)) {
1680 /* We never uploaded a beacon before.
1681 * Upload both templates now, but only mark one valid. */
3db1cd5c 1682 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1683 b43_upload_beacon0(dev);
1684 b43_upload_beacon1(dev);
c97a4ccc
MB		 1685 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1686 cmd |= B43_MACCMD_BEACON0_VALID;
1687 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1688 } else {
1689 if (!beacon0_valid) {
1690 b43_upload_beacon0(dev);
1691 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1692 cmd |= B43_MACCMD_BEACON0_VALID;
1693 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1694 } else if (!beacon1_valid) {
1695 b43_upload_beacon1(dev);
1696 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1697 cmd |= B43_MACCMD_BEACON1_VALID;
1698 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1699 }
c97a4ccc
MB		 1700 }
1701}
1702
36dbd954
MB		 1703static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1704{
1705 u32 old_irq_mask = dev->irq_mask;
1706
1707 /* update beacon right away or defer to irq */
1708 handle_irq_beacon(dev);
1709 if (old_irq_mask != dev->irq_mask) {
1710 /* The handler updated the IRQ mask. */
1711 B43_WARN_ON(!dev->irq_mask);
1712 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1713 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1714 } else {
1715 /* Device interrupts are currently disabled. That means
1716 * we just ran the hardirq handler and scheduled the
1717 * IRQ thread. The thread will write the IRQ mask when
1718 * it finished, so there's nothing to do here. Writing
1719 * the mask _here_ would incorrectly re-enable IRQs. */
1720 }
1721 }
1722}
1723
a82d9922
MB		 1724static void b43_beacon_update_trigger_work(struct work_struct *work)
1725{
1726 struct b43_wl *wl = container_of(work, struct b43_wl,
1727 beacon_update_trigger);
1728 struct b43_wldev *dev;
1729
1730 mutex_lock(&wl->mutex);
1731 dev = wl->current_dev;
1732 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1733 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1734 /* wl->mutex is enough. */
1735 b43_do_beacon_update_trigger_work(dev);
1736 mmiowb();
1737 } else {
1738 spin_lock_irq(&wl->hardirq_lock);
1739 b43_do_beacon_update_trigger_work(dev);
1740 mmiowb();
1741 spin_unlock_irq(&wl->hardirq_lock);
1742 }
a82d9922
MB		 1743 }
1744 mutex_unlock(&wl->mutex);
1745}
1746
d4df6f1a 1747/* Asynchronously update the packet templates in template RAM.
36dbd954 1748 * Locking: Requires wl->mutex to be locked. */
9d139c81 1749static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1750{
9d139c81
JB		 1751 struct sk_buff *beacon;
1752
e66fee6a
MB		 1753 /* This is the top half of the ansynchronous beacon update.
1754 * The bottom half is the beacon IRQ.
1755 * Beacon update must be asynchronous to avoid sending an
1756 * invalid beacon. This can happen for example, if the firmware
1757 * transmits a beacon while we are updating it. */
e4d6b795 1758
9d139c81
JB		 1759 /* We could modify the existing beacon and set the aid bit in
1760 * the TIM field, but that would probably require resizing and
1761 * moving of data within the beacon template.
1762 * Simply request a new beacon and let mac80211 do the hard work. */
1763 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1764 if (unlikely(!beacon))
1765 return;
1766
e66fee6a
MB		 1767 if (wl->current_beacon)
1768 dev_kfree_skb_any(wl->current_beacon);
1769 wl->current_beacon = beacon;
3db1cd5c
RR		 1770 wl->beacon0_uploaded = false;
1771 wl->beacon1_uploaded = false;
42935eca 1772 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1773}
1774
e4d6b795
MB		 1775static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1776{
1777 b43_time_lock(dev);
21d889d4 1778 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1779 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1780 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1781 } else {
1782 b43_write16(dev, 0x606, (beacon_int >> 6));
1783 b43_write16(dev, 0x610, beacon_int);
1784 }
1785 b43_time_unlock(dev);
a82d9922 1786 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1787}
1788
afa83e23
MB		 1789static void b43_handle_firmware_panic(struct b43_wldev *dev)
1790{
1791 u16 reason;
1792
1793 /* Read the register that contains the reason code for the panic. */
1794 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1795 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1796
1797 switch (reason) {
1798 default:
1799 b43dbg(dev->wl, "The panic reason is unknown.\n");
1800 /* fallthrough */
1801 case B43_FWPANIC_DIE:
1802 /* Do not restart the controller or firmware.
1803 * The device is nonfunctional from now on.
1804 * Restarting would result in this panic to trigger again,
1805 * so we avoid that recursion. */
1806 break;
1807 case B43_FWPANIC_RESTART:
1808 b43_controller_restart(dev, "Microcode panic");
1809 break;
1810 }
1811}
1812
e4d6b795
MB		 1813static void handle_irq_ucode_debug(struct b43_wldev *dev)
1814{
e48b0eeb 1815 unsigned int i, cnt;
53c06856 1816 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1817 __le16 *buf;
1818
1819 /* The proprietary firmware doesn't have this IRQ. */
1820 if (!dev->fw.opensource)
1821 return;
1822
afa83e23
MB		 1823 /* Read the register that contains the reason code for this IRQ. */
1824 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1825
e48b0eeb
MB		 1826 switch (reason) {
1827 case B43_DEBUGIRQ_PANIC:
afa83e23 1828 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1829 break;
1830 case B43_DEBUGIRQ_DUMP_SHM:
1831 if (!B43_DEBUG)
1832 break; /* Only with driver debugging enabled. */
1833 buf = kmalloc(4096, GFP_ATOMIC);
1834 if (!buf) {
1835 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1836 goto out;
1837 }
1838 for (i = 0; i < 4096; i += 2) {
1839 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1840 buf[i / 2] = cpu_to_le16(tmp);
1841 }
1842 b43info(dev->wl, "Shared memory dump:\n");
1843 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1844 16, 2, buf, 4096, 1);
1845 kfree(buf);
1846 break;
1847 case B43_DEBUGIRQ_DUMP_REGS:
1848 if (!B43_DEBUG)
1849 break; /* Only with driver debugging enabled. */
1850 b43info(dev->wl, "Microcode register dump:\n");
1851 for (i = 0, cnt = 0; i < 64; i++) {
1852 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1853 if (cnt == 0)
1854 printk(KERN_INFO);
1855 printk("r%02u: 0x%04X ", i, tmp);
1856 cnt++;
1857 if (cnt == 6) {
1858 printk("\n");
1859 cnt = 0;
1860 }
1861 }
1862 printk("\n");
1863 break;
53c06856
MB		 1864 case B43_DEBUGIRQ_MARKER:
1865 if (!B43_DEBUG)
1866 break; /* Only with driver debugging enabled. */
1867 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1868 B43_MARKER_ID_REG);
1869 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1870 B43_MARKER_LINE_REG);
1871 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1872 "at line number %u\n",
1873 marker_id, marker_line);
1874 break;
e48b0eeb
MB		 1875 default:
1876 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1877 reason);
1878 }
1879out:
afa83e23
MB		 1880 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1881 b43_shm_write16(dev, B43_SHM_SCRATCH,
1882 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1883}
1884
36dbd954 1885static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1886{
1887 u32 reason;
1888 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1889 u32 merged_dma_reason = 0;
21954c36 1890 int i;
e4d6b795 1891
36dbd954
MB		 1892 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1893 return;
e4d6b795
MB		 1894
1895 reason = dev->irq_reason;
1896 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1897 dma_reason[i] = dev->dma_reason[i];
1898 merged_dma_reason |= dma_reason[i];
1899 }
1900
1901 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1902 b43err(dev->wl, "MAC transmission error\n");
1903
00e0b8cb 1904 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1905 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1906 rmb();
1907 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1908 atomic_set(&dev->phy.txerr_cnt,
1909 B43_PHY_TX_BADNESS_LIMIT);
1910 b43err(dev->wl, "Too many PHY TX errors, "
1911 "restarting the controller\n");
1912 b43_controller_restart(dev, "PHY TX errors");
1913 }
1914 }
e4d6b795 1915
73b82bf0
TJ		 1916 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1917 b43err(dev->wl,
1918 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1919 dma_reason[0], dma_reason[1],
1920 dma_reason[2], dma_reason[3],
1921 dma_reason[4], dma_reason[5]);
1922 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1923 "on your system. It will now be switched to PIO.\n");
73b82bf0
TJ		 1924 /* Fall back to PIO transfers if we get fatal DMA errors! */
1925 dev->use_pio = true;
1926 b43_controller_restart(dev, "DMA error");
1927 return;
e4d6b795
MB		 1928 }
1929
1930 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1931 handle_irq_ucode_debug(dev);
1932 if (reason & B43_IRQ_TBTT_INDI)
1933 handle_irq_tbtt_indication(dev);
1934 if (reason & B43_IRQ_ATIM_END)
1935 handle_irq_atim_end(dev);
1936 if (reason & B43_IRQ_BEACON)
1937 handle_irq_beacon(dev);
1938 if (reason & B43_IRQ_PMQ)
1939 handle_irq_pmq(dev);
21954c36
MB		 1940 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1941 ;/* TODO */
1942 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1943 handle_irq_noise(dev);
1944
1945 /* Check the DMA reason registers for received data. */
73b82bf0
TJ		 1946 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1947 if (B43_DEBUG)
1948 b43warn(dev->wl, "RX descriptor underrun\n");
1949 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1950 }
5100d5ac
MB		 1951 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1952 if (b43_using_pio_transfers(dev))
1953 b43_pio_rx(dev->pio.rx_queue);
1954 else
1955 b43_dma_rx(dev->dma.rx_ring);
1956 }
e4d6b795
MB		 1957 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1958 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1959 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1960 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1961 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1962
21954c36 1963 if (reason & B43_IRQ_TX_OK)
e4d6b795 1964 handle_irq_transmit_status(dev);
e4d6b795 1965
36dbd954 1966 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1967 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1968
1969#if B43_DEBUG
1970 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1971 dev->irq_count++;
1972 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1973 if (reason & (1 << i))
1974 dev->irq_bit_count[i]++;
1975 }
1976 }
1977#endif
e4d6b795
MB		 1978}
1979
36dbd954
MB		 1980/* Interrupt thread handler. Handles device interrupts in thread context. */
1981static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1982{
36dbd954 1983 struct b43_wldev *dev = dev_id;
e4d6b795 1984
36dbd954
MB		 1985 mutex_lock(&dev->wl->mutex);
1986 b43_do_interrupt_thread(dev);
1987 mmiowb();
1988 mutex_unlock(&dev->wl->mutex);
1989
1990 return IRQ_HANDLED;
e4d6b795
MB		 1991}
1992
36dbd954 1993static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1994{
e4d6b795
MB		 1995 u32 reason;
1996
36dbd954
MB		 1997 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1998 * On SDIO, this runs under wl->mutex. */
e4d6b795 1999
e4d6b795
MB		 2000 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2001 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 2002 return IRQ_NONE;
13790728 2003 reason &= dev->irq_mask;
e4d6b795 2004 if (!reason)
cae56147 2005 return IRQ_NONE;
e4d6b795
MB		 2006
2007 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
73b82bf0 2008 & 0x0001FC00;
e4d6b795
MB		 2009 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2010 & 0x0000DC00;
2011 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2012 & 0x0000DC00;
2013 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2014 & 0x0001DC00;
2015 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2016 & 0x0000DC00;
13790728 2017/* Unused ring
e4d6b795
MB		 2018 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2019 & 0x0000DC00;
13790728 2020*/
e4d6b795 2021
36dbd954
MB		 2022 /* ACK the interrupt. */
2023 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2024 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2025 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2026 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2027 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2028 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2029/* Unused ring
2030 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2031*/
2032
2033 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2034 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2035 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2036 dev->irq_reason = reason;
36dbd954
MB		 2037
2038 return IRQ_WAKE_THREAD;
2039}
2040
2041/* Interrupt handler top-half. This runs with interrupts disabled. */
2042static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2043{
2044 struct b43_wldev *dev = dev_id;
2045 irqreturn_t ret;
2046
2047 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2048 return IRQ_NONE;
2049
2050 spin_lock(&dev->wl->hardirq_lock);
2051 ret = b43_do_interrupt(dev);
e4d6b795 2052 mmiowb();
36dbd954 2053 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2054
2055 return ret;
2056}
2057
3dbba8e2
AH		 2058/* SDIO interrupt handler. This runs in process context. */
2059static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2060{
2061 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2062 irqreturn_t ret;
2063
3dbba8e2 2064 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2065
2066 ret = b43_do_interrupt(dev);
2067 if (ret == IRQ_WAKE_THREAD)
2068 b43_do_interrupt_thread(dev);
2069
3dbba8e2
AH		 2070 mutex_unlock(&wl->mutex);
2071}
2072
1a9f5093 2073void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2074{
2075 release_firmware(fw->data);
2076 fw->data = NULL;
2077 fw->filename = NULL;
2078}
2079
e4d6b795
MB		 2080static void b43_release_firmware(struct b43_wldev *dev)
2081{
0673effd 2082 complete(&dev->fw_load_complete);
1a9f5093
MB		 2083 b43_do_release_fw(&dev->fw.ucode);
2084 b43_do_release_fw(&dev->fw.pcm);
2085 b43_do_release_fw(&dev->fw.initvals);
2086 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2087}
2088
eb189d8b 2089static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2090{
fc68ed4f
HE		 2091 const char text[] =
2092 "You must go to " \
2093 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2094 "and download the correct firmware for this driver version. " \
2095 "Please carefully read all instructions on this website.\n";
eb189d8b 2096
eb189d8b
MB		 2097 if (error)
2098 b43err(wl, text);
2099 else
2100 b43warn(wl, text);
e4d6b795
MB		 2101}
2102
5e20a4b5
LF		 2103static void b43_fw_cb(const struct firmware *firmware, void *context)
2104{
2105 struct b43_request_fw_context *ctx = context;
2106
2107 ctx->blob = firmware;
0673effd 2108 complete(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2109}
2110
1a9f5093
MB		 2111int b43_do_request_fw(struct b43_request_fw_context *ctx,
2112 const char *name,
5e20a4b5 2113 struct b43_firmware_file *fw, bool async)
e4d6b795 2114{
e4d6b795
MB		 2115 struct b43_fw_header *hdr;
2116 u32 size;
2117 int err;
2118
61cb5dd6
MB		 2119 if (!name) {
2120 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2121 /* FIXME: We should probably keep it anyway, to save some headache
2122 * on suspend/resume with multiband devices. */
2123 b43_do_release_fw(fw);
e4d6b795 2124 return 0;
61cb5dd6
MB		 2125 }
2126 if (fw->filename) {
1a9f5093
MB		 2127 if ((fw->type == ctx->req_type) &&
2128 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2129 return 0; /* Already have this fw. */
2130 /* Free the cached firmware first. */
1a9f5093
MB		 2131 /* FIXME: We should probably do this later after we successfully
2132 * got the new fw. This could reduce headache with multiband devices.
2133 * We could also redesign this to cache the firmware for all possible
2134 * bands all the time. */
2135 b43_do_release_fw(fw);
61cb5dd6 2136 }
e4d6b795 2137
1a9f5093
MB		 2138 switch (ctx->req_type) {
2139 case B43_FWTYPE_PROPRIETARY:
2140 snprintf(ctx->fwname, sizeof(ctx->fwname),
2141 "b43%s/%s.fw",
2142 modparam_fwpostfix, name);
2143 break;
2144 case B43_FWTYPE_OPENSOURCE:
2145 snprintf(ctx->fwname, sizeof(ctx->fwname),
2146 "b43-open%s/%s.fw",
2147 modparam_fwpostfix, name);
2148 break;
2149 default:
2150 B43_WARN_ON(1);
2151 return -ENOSYS;
2152 }
5e20a4b5
LF		 2153 if (async) {
2154 /* do this part asynchronously */
0673effd 2155 init_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2156 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2157 ctx->dev->dev->dev, GFP_KERNEL,
2158 ctx, b43_fw_cb);
2159 if (err < 0) {
2160 pr_err("Unable to load firmware\n");
2161 return err;
2162 }
0673effd 2163 wait_for_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2164 if (ctx->blob)
2165 goto fw_ready;
2166 /* On some ARM systems, the async request will fail, but the next sync
0673effd 2167 * request works. For this reason, we fall through here
5e20a4b5
LF		 2168 */
2169 }
2170 err = request_firmware(&ctx->blob, ctx->fwname,
2171 ctx->dev->dev->dev);
68217832 2172 if (err == -ENOENT) {
1a9f5093
MB		 2173 snprintf(ctx->errors[ctx->req_type],
2174 sizeof(ctx->errors[ctx->req_type]),
5e20a4b5
LF		 2175 "Firmware file \"%s\" not found\n",
2176 ctx->fwname);
68217832
MB		 2177 return err;
2178 } else if (err) {
1a9f5093
MB		 2179 snprintf(ctx->errors[ctx->req_type],
2180 sizeof(ctx->errors[ctx->req_type]),
2181 "Firmware file \"%s\" request failed (err=%d)\n",
2182 ctx->fwname, err);
e4d6b795
MB		 2183 return err;
2184 }
5e20a4b5
LF		 2185fw_ready:
2186 if (ctx->blob->size < sizeof(struct b43_fw_header))
e4d6b795 2187 goto err_format;
5e20a4b5 2188 hdr = (struct b43_fw_header *)(ctx->blob->data);
e4d6b795
MB		 2189 switch (hdr->type) {
2190 case B43_FW_TYPE_UCODE:
2191 case B43_FW_TYPE_PCM:
2192 size = be32_to_cpu(hdr->size);
5e20a4b5 2193 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2194 goto err_format;
2195 /* fallthrough */
2196 case B43_FW_TYPE_IV:
2197 if (hdr->ver != 1)
2198 goto err_format;
2199 break;
2200 default:
2201 goto err_format;
2202 }
2203
5e20a4b5 2204 fw->data = ctx->blob;
61cb5dd6 2205 fw->filename = name;
1a9f5093 2206 fw->type = ctx->req_type;
61cb5dd6
MB		 2207
2208 return 0;
e4d6b795
MB		 2209
2210err_format:
1a9f5093
MB		 2211 snprintf(ctx->errors[ctx->req_type],
2212 sizeof(ctx->errors[ctx->req_type]),
2213 "Firmware file \"%s\" format error.\n", ctx->fwname);
5e20a4b5 2214 release_firmware(ctx->blob);
61cb5dd6 2215
e4d6b795
MB		 2216 return -EPROTO;
2217}
2218
a60f99f7 2219/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
1a9f5093 2220static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2221{
1a9f5093
MB		 2222 struct b43_wldev *dev = ctx->dev;
2223 struct b43_firmware *fw = &ctx->dev->fw;
a60f99f7 2224 struct b43_phy *phy = &dev->phy;
21d889d4 2225 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795 2226 const char *filename;
e4d6b795
MB		 2227 int err;
2228
61cb5dd6 2229 /* Get microcode */
a60f99f7
RM		 2230 filename = NULL;
2231 switch (rev) {
2232 case 42:
2233 if (phy->type == B43_PHYTYPE_AC)
2234 filename = "ucode42";
2235 break;
15be8e89
RM		 2236 case 40:
2237 if (phy->type == B43_PHYTYPE_AC)
2238 filename = "ucode40";
2239 break;
a60f99f7
RM		 2240 case 33:
2241 if (phy->type == B43_PHYTYPE_LCN40)
2242 filename = "ucode33_lcn40";
2243 break;
2244 case 30:
2245 if (phy->type == B43_PHYTYPE_N)
2246 filename = "ucode30_mimo";
2247 break;
2248 case 29:
2249 if (phy->type == B43_PHYTYPE_HT)
2250 filename = "ucode29_mimo";
2251 break;
2252 case 26:
2253 if (phy->type == B43_PHYTYPE_HT)
2254 filename = "ucode26_mimo";
2255 break;
2256 case 28:
2257 case 25:
2258 if (phy->type == B43_PHYTYPE_N)
2259 filename = "ucode25_mimo";
2260 else if (phy->type == B43_PHYTYPE_LCN)
2261 filename = "ucode25_lcn";
2262 break;
2263 case 24:
2264 if (phy->type == B43_PHYTYPE_LCN)
2265 filename = "ucode24_lcn";
2266 break;
2267 case 23:
2268 if (phy->type == B43_PHYTYPE_N)
2269 filename = "ucode16_mimo";
2270 break;
2271 case 16 ... 19:
2272 if (phy->type == B43_PHYTYPE_N)
2273 filename = "ucode16_mimo";
2274 else if (phy->type == B43_PHYTYPE_LP)
2275 filename = "ucode16_lp";
2276 break;
2277 case 15:
759b973b 2278 filename = "ucode15";
a60f99f7
RM		 2279 break;
2280 case 14:
2281 filename = "ucode14";
2282 break;
2283 case 13:
2284 filename = "ucode13";
2285 break;
2286 case 11 ... 12:
2287 filename = "ucode11";
2288 break;
2289 case 5 ... 10:
2290 filename = "ucode5";
2291 break;
6ff1e5cf 2292 }
a60f99f7
RM		 2293 if (!filename)
2294 goto err_no_ucode;
5e20a4b5 2295 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
61cb5dd6
MB		 2296 if (err)
2297 goto err_load;
2298
2299 /* Get PCM code */
2300 if ((rev >= 5) && (rev <= 10))
2301 filename = "pcm5";
2302 else if (rev >= 11)
2303 filename = NULL;
2304 else
2305 goto err_no_pcm;
3db1cd5c 2306 fw->pcm_request_failed = false;
5e20a4b5 2307 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
68217832
MB		 2308 if (err == -ENOENT) {
2309 /* We did not find a PCM file? Not fatal, but
2310 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2311 fw->pcm_request_failed = true;
68217832 2312 } else if (err)
61cb5dd6
MB		 2313 goto err_load;
2314
2315 /* Get initvals */
a60f99f7 2316 filename = NULL;
61cb5dd6 2317 switch (dev->phy.type) {
61cb5dd6 2318 case B43_PHYTYPE_G:
a60f99f7 2319 if (rev == 13)
e9304882 2320 filename = "b0g0initvals13";
a60f99f7
RM		 2321 else if (rev >= 5 && rev <= 10)
2322 filename = "b0g0initvals5";
61cb5dd6
MB		 2323 break;
2324 case B43_PHYTYPE_N:
a60f99f7
RM		 2325 if (rev == 30)
2326 filename = "n16initvals30";
2327 else if (rev == 28 || rev == 25)
2328 filename = "n0initvals25";
2329 else if (rev == 24)
2330 filename = "n0initvals24";
2331 else if (rev == 23)
2332 filename = "n0initvals16"; /* What about n0initvals22? */
2333 else if (rev >= 16 && rev <= 18)
e41596a1 2334 filename = "n0initvals16";
a60f99f7 2335 else if (rev >= 11 && rev <= 12)
61cb5dd6 2336 filename = "n0initvals11";
61cb5dd6 2337 break;
759b973b 2338 case B43_PHYTYPE_LP:
a60f99f7
RM		 2339 if (rev >= 16 && rev <= 18)
2340 filename = "lp0initvals16";
2341 else if (rev == 15)
2342 filename = "lp0initvals15";
759b973b
GS		 2343 else if (rev == 14)
2344 filename = "lp0initvals14";
a60f99f7
RM		 2345 else if (rev == 13)
2346 filename = "lp0initvals13";
759b973b 2347 break;
8b9bda75
RM		 2348 case B43_PHYTYPE_HT:
2349 if (rev == 29)
2350 filename = "ht0initvals29";
a60f99f7
RM		 2351 else if (rev == 26)
2352 filename = "ht0initvals26";
8b9bda75
RM		 2353 break;
2354 case B43_PHYTYPE_LCN:
2355 if (rev == 24)
2356 filename = "lcn0initvals24";
8b9bda75 2357 break;
a60f99f7
RM		 2358 case B43_PHYTYPE_LCN40:
2359 if (rev == 33)
2360 filename = "lcn400initvals33";
2361 break;
2362 case B43_PHYTYPE_AC:
2363 if (rev == 42)
2364 filename = "ac1initvals42";
15be8e89
RM		 2365 else if (rev == 40)
2366 filename = "ac0initvals40";
a60f99f7 2367 break;
e4d6b795 2368 }
a60f99f7
RM		 2369 if (!filename)
2370 goto err_no_initvals;
5e20a4b5 2371 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
61cb5dd6
MB		 2372 if (err)
2373 goto err_load;
2374
2375 /* Get bandswitch initvals */
a60f99f7 2376 filename = NULL;
61cb5dd6 2377 switch (dev->phy.type) {
61cb5dd6 2378 case B43_PHYTYPE_G:
a60f99f7
RM		 2379 if (rev == 13)
2380 filename = "b0g0bsinitvals13";
2381 else if (rev >= 5 && rev <= 10)
61cb5dd6 2382 filename = "b0g0bsinitvals5";
61cb5dd6
MB		 2383 break;
2384 case B43_PHYTYPE_N:
a60f99f7
RM		 2385 if (rev == 30)
2386 filename = "n16bsinitvals30";
2387 else if (rev == 28 || rev == 25)
2388 filename = "n0bsinitvals25";
2389 else if (rev == 24)
2390 filename = "n0bsinitvals24";
2391 else if (rev == 23)
2392 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2393 else if (rev >= 16 && rev <= 18)
e41596a1 2394 filename = "n0bsinitvals16";
a60f99f7 2395 else if (rev >= 11 && rev <= 12)
61cb5dd6 2396 filename = "n0bsinitvals11";
61cb5dd6 2397 break;
759b973b 2398 case B43_PHYTYPE_LP:
a60f99f7
RM		 2399 if (rev >= 16 && rev <= 18)
2400 filename = "lp0bsinitvals16";
2401 else if (rev == 15)
2402 filename = "lp0bsinitvals15";
759b973b
GS		 2403 else if (rev == 14)
2404 filename = "lp0bsinitvals14";
a60f99f7
RM		 2405 else if (rev == 13)
2406 filename = "lp0bsinitvals13";
759b973b 2407 break;
8b9bda75
RM		 2408 case B43_PHYTYPE_HT:
2409 if (rev == 29)
2410 filename = "ht0bsinitvals29";
a60f99f7
RM		 2411 else if (rev == 26)
2412 filename = "ht0bsinitvals26";
8b9bda75
RM		 2413 break;
2414 case B43_PHYTYPE_LCN:
2415 if (rev == 24)
2416 filename = "lcn0bsinitvals24";
8b9bda75 2417 break;
a60f99f7
RM		 2418 case B43_PHYTYPE_LCN40:
2419 if (rev == 33)
2420 filename = "lcn400bsinitvals33";
2421 break;
2422 case B43_PHYTYPE_AC:
2423 if (rev == 42)
2424 filename = "ac1bsinitvals42";
15be8e89
RM		 2425 else if (rev == 40)
2426 filename = "ac0bsinitvals40";
a60f99f7 2427 break;
e4d6b795 2428 }
a60f99f7
RM		 2429 if (!filename)
2430 goto err_no_initvals;
5e20a4b5 2431 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
61cb5dd6
MB		 2432 if (err)
2433 goto err_load;
e4d6b795 2434
097b0e1b
JB		 2435 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2436
e4d6b795
MB		 2437 return 0;
2438
e4d6b795 2439err_no_ucode:
1a9f5093
MB		 2440 err = ctx->fatal_failure = -EOPNOTSUPP;
2441 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2442 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2443 goto error;
2444
2445err_no_pcm:
1a9f5093
MB		 2446 err = ctx->fatal_failure = -EOPNOTSUPP;
2447 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2448 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2449 goto error;
2450
2451err_no_initvals:
1a9f5093
MB		 2452 err = ctx->fatal_failure = -EOPNOTSUPP;
2453 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2454 "is required for your device (wl-core rev %u)\n", rev);
2455 goto error;
2456
2457err_load:
2458 /* We failed to load this firmware image. The error message
2459 * already is in ctx->errors. Return and let our caller decide
2460 * what to do. */
e4d6b795
MB		 2461 goto error;
2462
2463error:
2464 b43_release_firmware(dev);
2465 return err;
2466}
2467
6b6fa586
LF		 2468static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2469static void b43_one_core_detach(struct b43_bus_dev *dev);
09164043 2470static int b43_rng_init(struct b43_wl *wl);
6b6fa586
LF		 2471
2472static void b43_request_firmware(struct work_struct *work)
1a9f5093 2473{
6b6fa586
LF		 2474 struct b43_wl *wl = container_of(work,
2475 struct b43_wl, firmware_load);
2476 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2477 struct b43_request_fw_context *ctx;
2478 unsigned int i;
2479 int err;
2480 const char *errmsg;
2481
2482 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2483 if (!ctx)
6b6fa586 2484 return;
1a9f5093
MB		 2485 ctx->dev = dev;
2486
2487 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2488 err = b43_try_request_fw(ctx);
2489 if (!err)
6b6fa586
LF		 2490 goto start_ieee80211; /* Successfully loaded it. */
2491 /* Was fw version known? */
2492 if (ctx->fatal_failure)
1a9f5093
MB		 2493 goto out;
2494
6b6fa586 2495 /* proprietary fw not found, try open source */
1a9f5093
MB		 2496 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2497 err = b43_try_request_fw(ctx);
2498 if (!err)
6b6fa586
LF		 2499 goto start_ieee80211; /* Successfully loaded it. */
2500 if(ctx->fatal_failure)
1a9f5093
MB		 2501 goto out;
2502
2503 /* Could not find a usable firmware. Print the errors. */
2504 for (i = 0; i < B43_NR_FWTYPES; i++) {
2505 errmsg = ctx->errors[i];
2506 if (strlen(errmsg))
e0e29b68 2507 b43err(dev->wl, "%s", errmsg);
1a9f5093
MB		 2508 }
2509 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2510 goto out;
2511
2512start_ieee80211:
097b0e1b
JB		 2513 wl->hw->queues = B43_QOS_QUEUE_NUM;
2514 if (!modparam_qos || dev->fw.opensource)
2515 wl->hw->queues = 1;
2516
6b6fa586
LF		 2517 err = ieee80211_register_hw(wl->hw);
2518 if (err)
2519 goto err_one_core_detach;
e64add27 2520 wl->hw_registred = true;
6b6fa586 2521 b43_leds_register(wl->current_dev);
09164043
LF		 2522
2523 /* Register HW RNG driver */
2524 b43_rng_init(wl);
2525
6b6fa586
LF		 2526 goto out;
2527
2528err_one_core_detach:
2529 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2530
2531out:
2532 kfree(ctx);
1a9f5093
MB		 2533}
2534
e4d6b795
MB		 2535static int b43_upload_microcode(struct b43_wldev *dev)
2536{
652caa5b 2537 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2538 const size_t hdr_len = sizeof(struct b43_fw_header);
2539 const __be32 *data;
2540 unsigned int i, len;
2541 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2542 u32 tmp, macctl;
e4d6b795
MB		 2543 int err = 0;
2544
1f7d87b0
MB		 2545 /* Jump the microcode PSM to offset 0 */
2546 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2547 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2548 macctl |= B43_MACCTL_PSM_JMP0;
2549 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2550 /* Zero out all microcode PSM registers and shared memory. */
2551 for (i = 0; i < 64; i++)
2552 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2553 for (i = 0; i < 4096; i += 2)
2554 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2555
e4d6b795 2556 /* Upload Microcode. */
61cb5dd6
MB		 2557 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2558 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2559 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2560 for (i = 0; i < len; i++) {
2561 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2562 udelay(10);
2563 }
2564
61cb5dd6 2565 if (dev->fw.pcm.data) {
e4d6b795 2566 /* Upload PCM data. */
61cb5dd6
MB		 2567 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2568 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2569 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2570 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2571 /* No need for autoinc bit in SHM_HW */
2572 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2573 for (i = 0; i < len; i++) {
2574 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2575 udelay(10);
2576 }
2577 }
2578
2579 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2580
2581 /* Start the microcode PSM */
5056635c
RM		 2582 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2583 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2584
2585 /* Wait for the microcode to load and respond */
2586 i = 0;
2587 while (1) {
2588 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2589 if (tmp == B43_IRQ_MAC_SUSPENDED)
2590 break;
2591 i++;
1f7d87b0 2592 if (i >= 20) {
e4d6b795 2593 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2594 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2595 err = -ENODEV;
1f7d87b0
MB		 2596 goto error;
2597 }
e175e996 2598 msleep(50);
e4d6b795
MB		 2599 }
2600 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2601
2602 /* Get and check the revisions. */
2603 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2604 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2605 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2606 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2607
2608 if (fwrev <= 0x128) {
2609 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2610 "binary drivers older than version 4.x is unsupported. "
2611 "You must upgrade your firmware files.\n");
eb189d8b 2612 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2613 err = -EOPNOTSUPP;
1f7d87b0 2614 goto error;
e4d6b795 2615 }
e4d6b795
MB		 2616 dev->fw.rev = fwrev;
2617 dev->fw.patch = fwpatch;
5d852905
RM		 2618 if (dev->fw.rev >= 598)
2619 dev->fw.hdr_format = B43_FW_HDR_598;
2620 else if (dev->fw.rev >= 410)
efe0249b
RM		 2621 dev->fw.hdr_format = B43_FW_HDR_410;
2622 else
2623 dev->fw.hdr_format = B43_FW_HDR_351;
097b0e1b 2624 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
e48b0eeb 2625
097b0e1b 2626 dev->qos_enabled = dev->wl->hw->queues > 1;
403a3a13 2627 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2628 dev->hwcrypto_enabled = true;
403a3a13 2629
e48b0eeb 2630 if (dev->fw.opensource) {
403a3a13
MB		 2631 u16 fwcapa;
2632
e48b0eeb
MB		 2633 /* Patchlevel info is encoded in the "time" field. */
2634 dev->fw.patch = fwtime;
403a3a13
MB		 2635 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2636 dev->fw.rev, dev->fw.patch);
2637
2638 fwcapa = b43_fwcapa_read(dev);
2639 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2640 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2641 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2642 dev->hwcrypto_enabled = false;
403a3a13 2643 }
097b0e1b
JB		 2644 /* adding QoS support should use an offline discovery mechanism */
2645 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
e48b0eeb
MB		 2646 } else {
2647 b43info(dev->wl, "Loading firmware version %u.%u "
2648 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2649 fwrev, fwpatch,
2650 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2651 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2652 if (dev->fw.pcm_request_failed) {
2653 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2654 "Hardware accelerated cryptography is disabled.\n");
2655 b43_print_fw_helptext(dev->wl, 0);
2656 }
e48b0eeb 2657 }
e4d6b795 2658
652caa5b
JL		 2659 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2660 dev->fw.rev, dev->fw.patch);
21d889d4 2661 wiphy->hw_version = dev->dev->core_id;
652caa5b 2662
efe0249b 2663 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2664 /* We're over the deadline, but we keep support for old fw
2665 * until it turns out to be in major conflict with something new. */
eb189d8b 2666 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2667 "Support for old firmware will be removed soon "
2668 "(official deadline was July 2008).\n");
eb189d8b
MB		 2669 b43_print_fw_helptext(dev->wl, 0);
2670 }
2671
1f7d87b0
MB		 2672 return 0;
2673
2674error:
5056635c
RM		 2675 /* Stop the microcode PSM. */
2676 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2677 B43_MACCTL_PSM_JMP0);
1f7d87b0 2678
e4d6b795
MB		 2679 return err;
2680}
2681
2682static int b43_write_initvals(struct b43_wldev *dev,
2683 const struct b43_iv *ivals,
2684 size_t count,
2685 size_t array_size)
2686{
2687 const struct b43_iv *iv;
2688 u16 offset;
2689 size_t i;
2690 bool bit32;
2691
2692 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2693 iv = ivals;
2694 for (i = 0; i < count; i++) {
2695 if (array_size < sizeof(iv->offset_size))
2696 goto err_format;
2697 array_size -= sizeof(iv->offset_size);
2698 offset = be16_to_cpu(iv->offset_size);
2699 bit32 = !!(offset & B43_IV_32BIT);
2700 offset &= B43_IV_OFFSET_MASK;
2701 if (offset >= 0x1000)
2702 goto err_format;
2703 if (bit32) {
2704 u32 value;
2705
2706 if (array_size < sizeof(iv->data.d32))
2707 goto err_format;
2708 array_size -= sizeof(iv->data.d32);
2709
533dd1b0 2710 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2711 b43_write32(dev, offset, value);
2712
2713 iv = (const struct b43_iv *)((const uint8_t *)iv +
2714 sizeof(__be16) +
2715 sizeof(__be32));
2716 } else {
2717 u16 value;
2718
2719 if (array_size < sizeof(iv->data.d16))
2720 goto err_format;
2721 array_size -= sizeof(iv->data.d16);
2722
2723 value = be16_to_cpu(iv->data.d16);
2724 b43_write16(dev, offset, value);
2725
2726 iv = (const struct b43_iv *)((const uint8_t *)iv +
2727 sizeof(__be16) +
2728 sizeof(__be16));
2729 }
2730 }
2731 if (array_size)
2732 goto err_format;
2733
2734 return 0;
2735
2736err_format:
2737 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2738 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2739
2740 return -EPROTO;
2741}
2742
2743static int b43_upload_initvals(struct b43_wldev *dev)
2744{
2745 const size_t hdr_len = sizeof(struct b43_fw_header);
2746 const struct b43_fw_header *hdr;
2747 struct b43_firmware *fw = &dev->fw;
2748 const struct b43_iv *ivals;
2749 size_t count;
e4d6b795 2750
61cb5dd6
MB		 2751 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2752 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795 2753 count = be32_to_cpu(hdr->size);
0f68423f 2754 return b43_write_initvals(dev, ivals, count,
61cb5dd6 2755 fw->initvals.data->size - hdr_len);
0f68423f 2756}
e4d6b795 2757
0f68423f
RM		 2758static int b43_upload_initvals_band(struct b43_wldev *dev)
2759{
2760 const size_t hdr_len = sizeof(struct b43_fw_header);
2761 const struct b43_fw_header *hdr;
2762 struct b43_firmware *fw = &dev->fw;
2763 const struct b43_iv *ivals;
2764 size_t count;
2765
2766 if (!fw->initvals_band.data)
2767 return 0;
2768
2769 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2770 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2771 count = be32_to_cpu(hdr->size);
2772 return b43_write_initvals(dev, ivals, count,
2773 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2774}
2775
2776/* Initialize the GPIOs
2777 * http://bcm-specs.sipsolutions.net/GPIO
2778 */
bd7c8a59
RM		 2779
2780#ifdef CONFIG_B43_SSB
c4a2a081 2781static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2782{
d48ae5c8 2783 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2784
2785#ifdef CONFIG_SSB_DRIVER_PCICORE
2786 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2787#else
2788 return bus->chipco.dev;
2789#endif
2790}
bd7c8a59 2791#endif
c4a2a081 2792
e4d6b795
MB		 2793static int b43_gpio_init(struct b43_wldev *dev)
2794{
bd7c8a59 2795#ifdef CONFIG_B43_SSB
c4a2a081 2796 struct ssb_device *gpiodev;
bd7c8a59 2797#endif
e4d6b795
MB		 2798 u32 mask, set;
2799
5056635c
RM		 2800 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2801 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2802
2803 mask = 0x0000001F;
2804 set = 0x0000000F;
c244e08c 2805 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2806 mask |= 0x0060;
2807 set |= 0x0060;
828afd26
RM		 2808 } else if (dev->dev->chip_id == 0x5354) {
2809 /* Don't allow overtaking buttons GPIOs */
2810 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
e4d6b795 2811 }
828afd26 2812
e4d6b795
MB		 2813 if (0 /* FIXME: conditional unknown */ ) {
2814 b43_write16(dev, B43_MMIO_GPIO_MASK,
2815 b43_read16(dev, B43_MMIO_GPIO_MASK)
2816 | 0x0100);
828afd26
RM		 2817 /* BT Coexistance Input */
2818 mask |= 0x0080;
2819 set |= 0x0080;
2820 /* BT Coexistance Out */
2821 mask |= 0x0100;
2822 set |= 0x0100;
e4d6b795 2823 }
0581483a 2824 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
828afd26 2825 /* PA is controlled by gpio 9, let ucode handle it */
e4d6b795
MB		 2826 b43_write16(dev, B43_MMIO_GPIO_MASK,
2827 b43_read16(dev, B43_MMIO_GPIO_MASK)
2828 | 0x0200);
2829 mask |= 0x0200;
2830 set |= 0x0200;
2831 }
e4d6b795 2832
6cbab0d9 2833 switch (dev->dev->bus_type) {
42c9a458
RM		 2834#ifdef CONFIG_B43_BCMA
2835 case B43_BUS_BCMA:
0a64baea 2836 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
42c9a458
RM		 2837 break;
2838#endif
6cbab0d9
RM		 2839#ifdef CONFIG_B43_SSB
2840 case B43_BUS_SSB:
2841 gpiodev = b43_ssb_gpio_dev(dev);
2842 if (gpiodev)
2843 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2844 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
828afd26 2845 & ~mask) | set);
6cbab0d9
RM		 2846 break;
2847#endif
2848 }
e4d6b795
MB		 2849
2850 return 0;
2851}
2852
2853/* Turn off all GPIO stuff. Call this on module unload, for example. */
2854static void b43_gpio_cleanup(struct b43_wldev *dev)
2855{
bd7c8a59 2856#ifdef CONFIG_B43_SSB
c4a2a081 2857 struct ssb_device *gpiodev;
bd7c8a59 2858#endif
e4d6b795 2859
6cbab0d9 2860 switch (dev->dev->bus_type) {
42c9a458
RM		 2861#ifdef CONFIG_B43_BCMA
2862 case B43_BUS_BCMA:
0a64baea 2863 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
42c9a458
RM		 2864 break;
2865#endif
6cbab0d9
RM		 2866#ifdef CONFIG_B43_SSB
2867 case B43_BUS_SSB:
2868 gpiodev = b43_ssb_gpio_dev(dev);
2869 if (gpiodev)
2870 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2871 break;
2872#endif
2873 }
e4d6b795
MB		 2874}
2875
2876/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2877void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2878{
923fd703
MB		 2879 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2880 u16 fwstate;
2881
2882 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2883 B43_SHM_SH_UCODESTAT);
2884 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2885 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2886 b43err(dev->wl, "b43_mac_enable(): The firmware "
2887 "should be suspended, but current state is %u\n",
2888 fwstate);
2889 }
2890 }
2891
e4d6b795
MB		 2892 dev->mac_suspended--;
2893 B43_WARN_ON(dev->mac_suspended < 0);
2894 if (dev->mac_suspended == 0) {
5056635c 2895 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2896 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2897 B43_IRQ_MAC_SUSPENDED);
2898 /* Commit writes */
2899 b43_read32(dev, B43_MMIO_MACCTL);
2900 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2901 b43_power_saving_ctl_bits(dev, 0);
2902 }
2903}
2904
2905/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2906void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2907{
2908 int i;
2909 u32 tmp;
2910
05b64b36 2911 might_sleep();
e4d6b795 2912 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2913
e4d6b795
MB		 2914 if (dev->mac_suspended == 0) {
2915 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2916 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2917 /* force pci to flush the write */
2918 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2919 for (i = 35; i; i--) {
2920 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2921 if (tmp & B43_IRQ_MAC_SUSPENDED)
2922 goto out;
2923 udelay(10);
2924 }
2925 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2926 for (i = 40; i; i--) {
e4d6b795
MB		 2927 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2928 if (tmp & B43_IRQ_MAC_SUSPENDED)
2929 goto out;
05b64b36 2930 msleep(1);
e4d6b795
MB		 2931 }
2932 b43err(dev->wl, "MAC suspend failed\n");
2933 }
05b64b36 2934out:
e4d6b795
MB		 2935 dev->mac_suspended++;
2936}
2937
858a1652
RM		 2938/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2939void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2940{
6cbab0d9
RM		 2941 u32 tmp;
2942
2943 switch (dev->dev->bus_type) {
42c9a458
RM		 2944#ifdef CONFIG_B43_BCMA
2945 case B43_BUS_BCMA:
36677874 2946 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2947 if (on)
2948 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2949 else
2950 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2951 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2952 break;
2953#endif
6cbab0d9
RM		 2954#ifdef CONFIG_B43_SSB
2955 case B43_BUS_SSB:
2956 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2957 if (on)
2958 tmp |= B43_TMSLOW_MACPHYCLKEN;
2959 else
2960 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2961 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2962 break;
2963#endif
2964 }
858a1652
RM		 2965}
2966
e4d6b795
MB		 2967static void b43_adjust_opmode(struct b43_wldev *dev)
2968{
2969 struct b43_wl *wl = dev->wl;
2970 u32 ctl;
2971 u16 cfp_pretbtt;
2972
2973 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2974 /* Reset status to STA infrastructure mode. */
2975 ctl &= ~B43_MACCTL_AP;
2976 ctl &= ~B43_MACCTL_KEEP_CTL;
2977 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2978 ctl &= ~B43_MACCTL_KEEP_BAD;
2979 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2980 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2981 ctl |= B43_MACCTL_INFRA;
2982
05c914fe
JB		 2983 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2984 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2985 ctl |= B43_MACCTL_AP;
05c914fe 2986 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2987 ctl &= ~B43_MACCTL_INFRA;
2988
2989 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2990 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2991 if (wl->filter_flags & FIF_FCSFAIL)
2992 ctl |= B43_MACCTL_KEEP_BAD;
2993 if (wl->filter_flags & FIF_PLCPFAIL)
2994 ctl |= B43_MACCTL_KEEP_BADPLCP;
2995 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2996 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2997 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2998 ctl |= B43_MACCTL_BEACPROMISC;
2999
e4d6b795
MB		 3000 /* Workaround: On old hardware the HW-MAC-address-filter
3001 * doesn't work properly, so always run promisc in filter
3002 * it in software. */
21d889d4 3003 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 3004 ctl |= B43_MACCTL_PROMISC;
3005
3006 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3007
3008 cfp_pretbtt = 2;
3009 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 3010 if (dev->dev->chip_id == 0x4306 &&
3011 dev->dev->chip_rev == 3)
e4d6b795
MB		 3012 cfp_pretbtt = 100;
3013 else
3014 cfp_pretbtt = 50;
3015 }
3016 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 3017
3018 /* FIXME: We don't currently implement the PMQ mechanism,
3019 * so always disable it. If we want to implement PMQ,
3020 * we need to enable it here (clear DISCPMQ) in AP mode.
3021 */
5056635c
RM		 3022 if (0 /* ctl & B43_MACCTL_AP */)
3023 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3024 else
3025 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 3026}
3027
3028static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3029{
3030 u16 offset;
3031
3032 if (is_ofdm) {
3033 offset = 0x480;
3034 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3035 } else {
3036 offset = 0x4C0;
3037 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3038 }
3039 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3040 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3041}
3042
3043static void b43_rate_memory_init(struct b43_wldev *dev)
3044{
3045 switch (dev->phy.type) {
3046 case B43_PHYTYPE_A:
3047 case B43_PHYTYPE_G:
53a6e234 3048 case B43_PHYTYPE_N:
9d86a2d5 3049 case B43_PHYTYPE_LP:
6a461c23 3050 case B43_PHYTYPE_HT:
0b4ff45d 3051 case B43_PHYTYPE_LCN:
e4d6b795
MB		 3052 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3053 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3054 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3055 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3056 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3057 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3058 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3059 if (dev->phy.type == B43_PHYTYPE_A)
3060 break;
3061 /* fallthrough */
3062 case B43_PHYTYPE_B:
3063 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3064 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3065 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3066 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3067 break;
3068 default:
3069 B43_WARN_ON(1);
3070 }
3071}
3072
5042c507
MB		 3073/* Set the default values for the PHY TX Control Words. */
3074static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3075{
3076 u16 ctl = 0;
3077
3078 ctl |= B43_TXH_PHY_ENC_CCK;
3079 ctl |= B43_TXH_PHY_ANT01AUTO;
3080 ctl |= B43_TXH_PHY_TXPWR;
3081
3082 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3083 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3084 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3085}
3086
e4d6b795
MB		 3087/* Set the TX-Antenna for management frames sent by firmware. */
3088static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3089{
5042c507 3090 u16 ant;
e4d6b795
MB		 3091 u16 tmp;
3092
5042c507 3093 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3094
e4d6b795
MB		 3095 /* For ACK/CTS */
3096 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3097 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3098 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3099 /* For Probe Resposes */
3100 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3101 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3102 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3103}
3104
3105/* This is the opposite of b43_chip_init() */
3106static void b43_chip_exit(struct b43_wldev *dev)
3107{
fb11137a 3108 b43_phy_exit(dev);
e4d6b795
MB		 3109 b43_gpio_cleanup(dev);
3110 /* firmware is released later */
3111}
3112
3113/* Initialize the chip
3114 * http://bcm-specs.sipsolutions.net/ChipInit
3115 */
3116static int b43_chip_init(struct b43_wldev *dev)
3117{
3118 struct b43_phy *phy = &dev->phy;
ef1a628d 3119 int err;
858a1652 3120 u32 macctl;
e4d6b795
MB		 3121 u16 value16;
3122
1f7d87b0
MB		 3123 /* Initialize the MAC control */
3124 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3125 if (dev->phy.gmode)
3126 macctl |= B43_MACCTL_GMODE;
3127 macctl |= B43_MACCTL_INFRA;
3128 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3129
e4d6b795
MB		 3130 err = b43_upload_microcode(dev);
3131 if (err)
3132 goto out; /* firmware is released later */
3133
3134 err = b43_gpio_init(dev);
3135 if (err)
3136 goto out; /* firmware is released later */
21954c36 3137
e4d6b795
MB		 3138 err = b43_upload_initvals(dev);
3139 if (err)
1a8d1227 3140 goto err_gpio_clean;
e4d6b795 3141
0f68423f
RM		 3142 err = b43_upload_initvals_band(dev);
3143 if (err)
3144 goto err_gpio_clean;
3145
0b7dcd96
MB		 3146 /* Turn the Analog on and initialize the PHY. */
3147 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3148 err = b43_phy_init(dev);
3149 if (err)
ef1a628d 3150 goto err_gpio_clean;
e4d6b795 3151
ef1a628d
MB		 3152 /* Disable Interference Mitigation. */
3153 if (phy->ops->interf_mitigation)
3154 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3155
ef1a628d
MB		 3156 /* Select the antennae */
3157 if (phy->ops->set_rx_antenna)
3158 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3159 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3160
3161 if (phy->type == B43_PHYTYPE_B) {
3162 value16 = b43_read16(dev, 0x005E);
3163 value16 |= 0x0004;
3164 b43_write16(dev, 0x005E, value16);
3165 }
3166 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3167 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3168 b43_write32(dev, 0x010C, 0x01000000);
3169
5056635c
RM		 3170 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3171 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3172
e4d6b795
MB		 3173 /* Probe Response Timeout value */
3174 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
5c1da23b 3175 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
e4d6b795
MB		 3176
3177 /* Initially set the wireless operation mode. */
3178 b43_adjust_opmode(dev);
3179
21d889d4 3180 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3181 b43_write16(dev, 0x060E, 0x0000);
3182 b43_write16(dev, 0x0610, 0x8000);
3183 b43_write16(dev, 0x0604, 0x0000);
3184 b43_write16(dev, 0x0606, 0x0200);
3185 } else {
3186 b43_write32(dev, 0x0188, 0x80000000);
3187 b43_write32(dev, 0x018C, 0x02000000);
3188 }
3189 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
73b82bf0 3190 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
e4d6b795
MB		 3191 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3192 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3193 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3194 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3195 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3196
858a1652 3197 b43_mac_phy_clock_set(dev, true);
e4d6b795 3198
6cbab0d9 3199 switch (dev->dev->bus_type) {
42c9a458
RM		 3200#ifdef CONFIG_B43_BCMA
3201 case B43_BUS_BCMA:
3202 /* FIXME: 0xE74 is quite common, but should be read from CC */
3203 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3204 break;
3205#endif
6cbab0d9
RM		 3206#ifdef CONFIG_B43_SSB
3207 case B43_BUS_SSB:
3208 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3209 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3210 break;
3211#endif
3212 }
e4d6b795
MB		 3213
3214 err = 0;
3215 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3216out:
e4d6b795
MB		 3217 return err;
3218
1a8d1227 3219err_gpio_clean:
e4d6b795 3220 b43_gpio_cleanup(dev);
21954c36 3221 return err;
e4d6b795
MB		 3222}
3223
e4d6b795
MB		 3224static void b43_periodic_every60sec(struct b43_wldev *dev)
3225{
ef1a628d 3226 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3227
ef1a628d
MB		 3228 if (ops->pwork_60sec)
3229 ops->pwork_60sec(dev);
18c8adeb
MB		 3230
3231 /* Force check the TX power emission now. */
3232 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3233}
3234
3235static void b43_periodic_every30sec(struct b43_wldev *dev)
3236{
3237 /* Update device statistics. */
3238 b43_calculate_link_quality(dev);
3239}
3240
3241static void b43_periodic_every15sec(struct b43_wldev *dev)
3242{
3243 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3244 u16 wdr;
3245
3246 if (dev->fw.opensource) {
3247 /* Check if the firmware is still alive.
3248 * It will reset the watchdog counter to 0 in its idle loop. */
3249 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3250 if (unlikely(wdr)) {
3251 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3252 b43_controller_restart(dev, "Firmware watchdog");
3253 return;
3254 } else {
3255 b43_shm_write16(dev, B43_SHM_SCRATCH,
3256 B43_WATCHDOG_REG, 1);
3257 }
3258 }
e4d6b795 3259
ef1a628d
MB		 3260 if (phy->ops->pwork_15sec)
3261 phy->ops->pwork_15sec(dev);
3262
00e0b8cb
SB		 3263 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3264 wmb();
990b86f4
MB		 3265
3266#if B43_DEBUG
3267 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3268 unsigned int i;
3269
3270 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3271 dev->irq_count / 15,
3272 dev->tx_count / 15,
3273 dev->rx_count / 15);
3274 dev->irq_count = 0;
3275 dev->tx_count = 0;
3276 dev->rx_count = 0;
3277 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3278 if (dev->irq_bit_count[i]) {
3279 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3280 dev->irq_bit_count[i] / 15, i, (1 << i));
3281 dev->irq_bit_count[i] = 0;
3282 }
3283 }
3284 }
3285#endif
e4d6b795
MB		 3286}
3287
e4d6b795
MB		 3288static void do_periodic_work(struct b43_wldev *dev)
3289{
3290 unsigned int state;
3291
3292 state = dev->periodic_state;
42bb4cd5 3293 if (state % 4 == 0)
e4d6b795 3294 b43_periodic_every60sec(dev);
42bb4cd5 3295 if (state % 2 == 0)
e4d6b795 3296 b43_periodic_every30sec(dev);
42bb4cd5 3297 b43_periodic_every15sec(dev);
e4d6b795
MB		 3298}
3299
05b64b36
MB		 3300/* Periodic work locking policy:
3301 * The whole periodic work handler is protected by
3302 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3303 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3304 */
e4d6b795
MB		 3305static void b43_periodic_work_handler(struct work_struct *work)
3306{
05b64b36
MB		 3307 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3308 periodic_work.work);
3309 struct b43_wl *wl = dev->wl;
3310 unsigned long delay;
e4d6b795 3311
05b64b36 3312 mutex_lock(&wl->mutex);
e4d6b795
MB		 3313
3314 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3315 goto out;
3316 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3317 goto out_requeue;
3318
05b64b36 3319 do_periodic_work(dev);
e4d6b795 3320
e4d6b795 3321 dev->periodic_state++;
42bb4cd5 3322out_requeue:
e4d6b795
MB		 3323 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3324 delay = msecs_to_jiffies(50);
3325 else
82cd682d 3326 delay = round_jiffies_relative(HZ * 15);
42935eca 3327 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3328out:
05b64b36 3329 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3330}
3331
3332static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3333{
3334 struct delayed_work *work = &dev->periodic_work;
3335
3336 dev->periodic_state = 0;
3337 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3338 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3339}
3340
f3dd3fcc 3341/* Check if communication with the device works correctly. */
e4d6b795
MB		 3342static int b43_validate_chipaccess(struct b43_wldev *dev)
3343{
f62ae6cd 3344 u32 v, backup0, backup4;
e4d6b795 3345
f62ae6cd
MB		 3346 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3347 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3348
3349 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3350 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3351 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3352 goto error;
f3dd3fcc
MB		 3353 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3354 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3355 goto error;
3356
f62ae6cd
MB		 3357 /* Check if unaligned 32bit SHM_SHARED access works properly.
3358 * However, don't bail out on failure, because it's noncritical. */
3359 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3360 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3361 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3362 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3363 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3364 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3365 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3366 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3367 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3368 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3369 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3370 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3371
3372 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3373 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3374
21d889d4 3375 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3376 /* The 32bit register shadows the two 16bit registers
3377 * with update sideeffects. Validate this. */
3378 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3379 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3380 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3381 goto error;
3382 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3383 goto error;
3384 }
3385 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3386
3387 v = b43_read32(dev, B43_MMIO_MACCTL);
3388 v |= B43_MACCTL_GMODE;
3389 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3390 goto error;
3391
3392 return 0;
f3dd3fcc 3393error:
e4d6b795
MB		 3394 b43err(dev->wl, "Failed to validate the chipaccess\n");
3395 return -ENODEV;
3396}
3397
3398static void b43_security_init(struct b43_wldev *dev)
3399{
e4d6b795
MB		 3400 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3401 /* KTP is a word address, but we address SHM bytewise.
3402 * So multiply by two.
3403 */
3404 dev->ktp *= 2;
66d2d089
MB		 3405 /* Number of RCMTA address slots */
3406 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3407 /* Clear the key memory. */
e4d6b795
MB		 3408 b43_clear_keys(dev);
3409}
3410
616de35d 3411#ifdef CONFIG_B43_HWRNG
99da185a 3412static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3413{
3414 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3415 struct b43_wldev *dev;
3416 int count = -ENODEV;
e4d6b795 3417
a78b3bb2
MB		 3418 mutex_lock(&wl->mutex);
3419 dev = wl->current_dev;
3420 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3421 *data = b43_read16(dev, B43_MMIO_RNG);
3422 count = sizeof(u16);
3423 }
3424 mutex_unlock(&wl->mutex);
e4d6b795 3425
a78b3bb2 3426 return count;
e4d6b795 3427}
616de35d 3428#endif /* CONFIG_B43_HWRNG */
e4d6b795 3429
b844eba2 3430static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3431{
616de35d 3432#ifdef CONFIG_B43_HWRNG
e4d6b795 3433 if (wl->rng_initialized)
b844eba2 3434 hwrng_unregister(&wl->rng);
616de35d 3435#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3436}
3437
3438static int b43_rng_init(struct b43_wl *wl)
3439{
616de35d 3440 int err = 0;
e4d6b795 3441
616de35d 3442#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3443 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3444 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3445 wl->rng.name = wl->rng_name;
3446 wl->rng.data_read = b43_rng_read;
3447 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3448 wl->rng_initialized = true;
e4d6b795
MB		 3449 err = hwrng_register(&wl->rng);
3450 if (err) {
3db1cd5c 3451 wl->rng_initialized = false;
e4d6b795
MB		 3452 b43err(wl, "Failed to register the random "
3453 "number generator (%d)\n", err);
3454 }
616de35d 3455#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3456
3457 return err;
3458}
3459
f5d40eed 3460static void b43_tx_work(struct work_struct *work)
e4d6b795 3461{
f5d40eed
MB		 3462 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3463 struct b43_wldev *dev;
3464 struct sk_buff *skb;
bad69194 3465 int queue_num;
f5d40eed 3466 int err = 0;
e4d6b795 3467
f5d40eed
MB		 3468 mutex_lock(&wl->mutex);
3469 dev = wl->current_dev;
3470 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3471 mutex_unlock(&wl->mutex);
3472 return;
5100d5ac 3473 }
21a75d77 3474
bad69194 3475 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3476 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3477 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3478 if (b43_using_pio_transfers(dev))
3479 err = b43_pio_tx(dev, skb);
3480 else
3481 err = b43_dma_tx(dev, skb);
3482 if (err == -ENOSPC) {
3483 wl->tx_queue_stopped[queue_num] = 1;
3484 ieee80211_stop_queue(wl->hw, queue_num);
3485 skb_queue_head(&wl->tx_queue[queue_num], skb);
3486 break;
3487 }
3488 if (unlikely(err))
78f18df4 3489 ieee80211_free_txskb(wl->hw, skb);
bad69194 3490 err = 0;
3491 }
21a75d77 3492
bad69194 3493 if (!err)
3494 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3495 }
3496
990b86f4
MB		 3497#if B43_DEBUG
3498 dev->tx_count++;
3499#endif
f5d40eed
MB		 3500 mutex_unlock(&wl->mutex);
3501}
21a75d77 3502
7bb45683 3503static void b43_op_tx(struct ieee80211_hw *hw,
36323f81
TH		 3504 struct ieee80211_tx_control *control,
3505 struct sk_buff *skb)
f5d40eed
MB		 3506{
3507 struct b43_wl *wl = hw_to_b43_wl(hw);
3508
3509 if (unlikely(skb->len < 2 + 2 + 6)) {
3510 /* Too short, this can't be a valid frame. */
78f18df4 3511 ieee80211_free_txskb(hw, skb);
7bb45683 3512 return;
f5d40eed
MB		 3513 }
3514 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3515
bad69194 3516 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3517 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3518 ieee80211_queue_work(wl->hw, &wl->tx_work);
3519 } else {
3520 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3521 }
e4d6b795
MB		 3522}
3523
e6f5b934
MB		 3524static void b43_qos_params_upload(struct b43_wldev *dev,
3525 const struct ieee80211_tx_queue_params *p,
3526 u16 shm_offset)
3527{
3528 u16 params[B43_NR_QOSPARAMS];
0b57664c 3529 int bslots, tmp;
e6f5b934
MB		 3530 unsigned int i;
3531
b0544eb6
MB		 3532 if (!dev->qos_enabled)
3533 return;
3534
0b57664c 3535 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3536
3537 memset(&params, 0, sizeof(params));
3538
3539 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3540 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3541 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3542 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3543 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3544 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3545 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3546
3547 for (i = 0; i < ARRAY_SIZE(params); i++) {
3548 if (i == B43_QOSPARAM_STATUS) {
3549 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3550 shm_offset + (i * 2));
3551 /* Mark the parameters as updated. */
3552 tmp |= 0x100;
3553 b43_shm_write16(dev, B43_SHM_SHARED,
3554 shm_offset + (i * 2),
3555 tmp);
3556 } else {
3557 b43_shm_write16(dev, B43_SHM_SHARED,
3558 shm_offset + (i * 2),
3559 params[i]);
3560 }
3561 }
3562}
3563
c40c1129
MB		 3564/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3565static const u16 b43_qos_shm_offsets[] = {
3566 /* [mac80211-queue-nr] = SHM_OFFSET, */
3567 [0] = B43_QOS_VOICE,
3568 [1] = B43_QOS_VIDEO,
3569 [2] = B43_QOS_BESTEFFORT,
3570 [3] = B43_QOS_BACKGROUND,
3571};
3572
5a5f3b40
MB		 3573/* Update all QOS parameters in hardware. */
3574static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3575{
3576 struct b43_wl *wl = dev->wl;
3577 struct b43_qos_params *params;
e6f5b934
MB		 3578 unsigned int i;
3579
b0544eb6
MB		 3580 if (!dev->qos_enabled)
3581 return;
3582
c40c1129
MB		 3583 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3584 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3585
3586 b43_mac_suspend(dev);
e6f5b934
MB		 3587 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3588 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3589 b43_qos_params_upload(dev, &(params->p),
3590 b43_qos_shm_offsets[i]);
e6f5b934 3591 }
e6f5b934
MB		 3592 b43_mac_enable(dev);
3593}
3594
3595static void b43_qos_clear(struct b43_wl *wl)
3596{
3597 struct b43_qos_params *params;
3598 unsigned int i;
3599
c40c1129
MB		 3600 /* Initialize QoS parameters to sane defaults. */
3601
3602 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3603 ARRAY_SIZE(wl->qos_params));
3604
e6f5b934
MB		 3605 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3606 params = &(wl->qos_params[i]);
3607
c40c1129
MB		 3608 switch (b43_qos_shm_offsets[i]) {
3609 case B43_QOS_VOICE:
3610 params->p.txop = 0;
3611 params->p.aifs = 2;
3612 params->p.cw_min = 0x0001;
3613 params->p.cw_max = 0x0001;
3614 break;
3615 case B43_QOS_VIDEO:
3616 params->p.txop = 0;
3617 params->p.aifs = 2;
3618 params->p.cw_min = 0x0001;
3619 params->p.cw_max = 0x0001;
3620 break;
3621 case B43_QOS_BESTEFFORT:
3622 params->p.txop = 0;
3623 params->p.aifs = 3;
3624 params->p.cw_min = 0x0001;
3625 params->p.cw_max = 0x03FF;
3626 break;
3627 case B43_QOS_BACKGROUND:
3628 params->p.txop = 0;
3629 params->p.aifs = 7;
3630 params->p.cw_min = 0x0001;
3631 params->p.cw_max = 0x03FF;
3632 break;
3633 default:
3634 B43_WARN_ON(1);
3635 }
e6f5b934
MB		 3636 }
3637}
3638
3639/* Initialize the core's QOS capabilities */
3640static void b43_qos_init(struct b43_wldev *dev)
3641{
b0544eb6
MB		 3642 if (!dev->qos_enabled) {
3643 /* Disable QOS support. */
3644 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3645 b43_write16(dev, B43_MMIO_IFSCTL,
3646 b43_read16(dev, B43_MMIO_IFSCTL)
3647 & ~B43_MMIO_IFSCTL_USE_EDCF);
3648 b43dbg(dev->wl, "QoS disabled\n");
3649 return;
3650 }
3651
e6f5b934 3652 /* Upload the current QOS parameters. */
5a5f3b40 3653 b43_qos_upload_all(dev);
e6f5b934
MB		 3654
3655 /* Enable QOS support. */
3656 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3657 b43_write16(dev, B43_MMIO_IFSCTL,
3658 b43_read16(dev, B43_MMIO_IFSCTL)
3659 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3660 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3661}
3662
8a3a3c85
EP		 3663static int b43_op_conf_tx(struct ieee80211_hw *hw,
3664 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3665 const struct ieee80211_tx_queue_params *params)
e4d6b795 3666{
e6f5b934 3667 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3668 struct b43_wldev *dev;
e6f5b934 3669 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3670 int err = -ENODEV;
e6f5b934
MB		 3671
3672 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3673 /* Queue not available or don't support setting
3674 * params on this queue. Return success to not
3675 * confuse mac80211. */
3676 return 0;
3677 }
5a5f3b40
MB		 3678 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3679 ARRAY_SIZE(wl->qos_params));
e6f5b934 3680
5a5f3b40
MB		 3681 mutex_lock(&wl->mutex);
3682 dev = wl->current_dev;
3683 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3684 goto out_unlock;
e6f5b934 3685
5a5f3b40
MB		 3686 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3687 b43_mac_suspend(dev);
3688 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3689 b43_qos_shm_offsets[queue]);
3690 b43_mac_enable(dev);
3691 err = 0;
e6f5b934 3692
5a5f3b40
MB		 3693out_unlock:
3694 mutex_unlock(&wl->mutex);
3695
3696 return err;
e4d6b795
MB		 3697}
3698
40faacc4
MB		 3699static int b43_op_get_stats(struct ieee80211_hw *hw,
3700 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3701{
3702 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3703
36dbd954 3704 mutex_lock(&wl->mutex);
e4d6b795 3705 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3706 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3707
3708 return 0;
3709}
3710
37a41b4a 3711static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3712{
3713 struct b43_wl *wl = hw_to_b43_wl(hw);
3714 struct b43_wldev *dev;
3715 u64 tsf;
3716
3717 mutex_lock(&wl->mutex);
08e87a83
AF		 3718 dev = wl->current_dev;
3719
3720 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3721 b43_tsf_read(dev, &tsf);
3722 else
3723 tsf = 0;
3724
08e87a83
AF		 3725 mutex_unlock(&wl->mutex);
3726
3727 return tsf;
3728}
3729
37a41b4a
EP		 3730static void b43_op_set_tsf(struct ieee80211_hw *hw,
3731 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3732{
3733 struct b43_wl *wl = hw_to_b43_wl(hw);
3734 struct b43_wldev *dev;
3735
3736 mutex_lock(&wl->mutex);
08e87a83
AF		 3737 dev = wl->current_dev;
3738
3739 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3740 b43_tsf_write(dev, tsf);
3741
08e87a83
AF		 3742 mutex_unlock(&wl->mutex);
3743}
3744
99da185a 3745static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3746{
3747 switch (band) {
3748 case IEEE80211_BAND_5GHZ:
3749 return "5";
3750 case IEEE80211_BAND_2GHZ:
3751 return "2.4";
3752 default:
3753 break;
3754 }
3755 B43_WARN_ON(1);
3756 return "";
3757}
3758
e4d6b795 3759/* Expects wl->mutex locked */
7a8af8cf
RM		 3760static int b43_switch_band(struct b43_wldev *dev,
3761 struct ieee80211_channel *chan)
e4d6b795 3762{
7a8af8cf
RM		 3763 struct b43_phy *phy = &dev->phy;
3764 bool gmode;
3765 u32 tmp;
e4d6b795 3766
644aa4d6
RM		 3767 switch (chan->band) {
3768 case IEEE80211_BAND_5GHZ:
7a8af8cf 3769 gmode = false;
644aa4d6
RM		 3770 break;
3771 case IEEE80211_BAND_2GHZ:
7a8af8cf 3772 gmode = true;
644aa4d6
RM		 3773 break;
3774 default:
3775 B43_WARN_ON(1);
3776 return -EINVAL;
bb1eeff1 3777 }
644aa4d6 3778
7a8af8cf
RM		 3779 if (!((gmode && phy->supports_2ghz) ||
3780 (!gmode && phy->supports_5ghz))) {
3781 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
bb1eeff1
MB		 3782 band_to_string(chan->band));
3783 return -ENODEV;
e4d6b795 3784 }
7a8af8cf
RM		 3785
3786 if (!!phy->gmode == !!gmode) {
e4d6b795
MB		 3787 /* This device is already running. */
3788 return 0;
3789 }
7a8af8cf
RM		 3790
3791 b43dbg(dev->wl, "Switching to %s GHz band\n",
bb1eeff1 3792 band_to_string(chan->band));
7a8af8cf 3793
6fe55143
RM		 3794 /* Some new devices don't need disabling radio for band switching */
3795 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3796 b43_software_rfkill(dev, true);
7a8af8cf
RM		 3797
3798 phy->gmode = gmode;
3799 b43_phy_put_into_reset(dev);
3800 switch (dev->dev->bus_type) {
3801#ifdef CONFIG_B43_BCMA
3802 case B43_BUS_BCMA:
3803 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3804 if (gmode)
3805 tmp |= B43_BCMA_IOCTL_GMODE;
3806 else
3807 tmp &= ~B43_BCMA_IOCTL_GMODE;
3808 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3809 break;
3810#endif
3811#ifdef CONFIG_B43_SSB
3812 case B43_BUS_SSB:
3813 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3814 if (gmode)
3815 tmp |= B43_TMSLOW_GMODE;
3816 else
3817 tmp &= ~B43_TMSLOW_GMODE;
3818 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3819 break;
3820#endif
e4d6b795 3821 }
7a8af8cf 3822 b43_phy_take_out_of_reset(dev);
e4d6b795 3823
7a8af8cf
RM		 3824 b43_upload_initvals_band(dev);
3825
3826 b43_phy_init(dev);
e4d6b795
MB		 3827
3828 return 0;
e4d6b795
MB		 3829}
3830
9124b077
JB		 3831/* Write the short and long frame retry limit values. */
3832static void b43_set_retry_limits(struct b43_wldev *dev,
3833 unsigned int short_retry,
3834 unsigned int long_retry)
3835{
3836 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3837 * the chip-internal counter. */
3838 short_retry = min(short_retry, (unsigned int)0xF);
3839 long_retry = min(long_retry, (unsigned int)0xF);
3840
3841 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3842 short_retry);
3843 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3844 long_retry);
3845}
3846
e8975581 3847static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3848{
3849 struct b43_wl *wl = hw_to_b43_wl(hw);
53256511
RM		 3850 struct b43_wldev *dev = wl->current_dev;
3851 struct b43_phy *phy = &dev->phy;
e8975581 3852 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3853 int antenna;
e4d6b795 3854 int err = 0;
e4d6b795 3855
e4d6b795 3856 mutex_lock(&wl->mutex);
7a8af8cf
RM		 3857 b43_mac_suspend(dev);
3858
8c79e5ee 3859 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ea42e71c 3860 phy->chandef = &conf->chandef;
f9471e99 3861 phy->channel = conf->chandef.chan->hw_value;
2a190322 3862
8c79e5ee
RM		 3863 /* Switch the band (if necessary). */
3864 err = b43_switch_band(dev, conf->chandef.chan);
3865 if (err)
3866 goto out_mac_enable;
3867
3868 /* Switch to the requested channel.
3869 * The firmware takes care of races with the TX handler.
3870 */
f9471e99 3871 b43_switch_channel(dev, phy->channel);
8c79e5ee 3872 }
aa4c7b2a 3873
9124b077
JB		 3874 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3875 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3876 conf->long_frame_max_tx_count);
3877 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3878 if (!changed)
d10d0e57 3879 goto out_mac_enable;
e4d6b795 3880
0869aea0 3881 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3882
e4d6b795
MB		 3883 /* Adjust the desired TX power level. */
3884 if (conf->power_level != 0) {
18c8adeb
MB		 3885 if (conf->power_level != phy->desired_txpower) {
3886 phy->desired_txpower = conf->power_level;
3887 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3888 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3889 }
3890 }
3891
3892 /* Antennas for RX and management frame TX. */
0f4ac38b 3893 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3894 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3895 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3896 if (phy->ops->set_rx_antenna)
3897 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3898
fd4973c5
LF		 3899 if (wl->radio_enabled != phy->radio_on) {
3900 if (wl->radio_enabled) {
19d337df 3901 b43_software_rfkill(dev, false);
fda9abcf
MB		 3902 b43info(dev->wl, "Radio turned on by software\n");
3903 if (!dev->radio_hw_enable) {
3904 b43info(dev->wl, "The hardware RF-kill button "
3905 "still turns the radio physically off. "
3906 "Press the button to turn it on.\n");
3907 }
3908 } else {
19d337df 3909 b43_software_rfkill(dev, true);
fda9abcf
MB		 3910 b43info(dev->wl, "Radio turned off by software\n");
3911 }
3912 }
3913
d10d0e57
MB		 3914out_mac_enable:
3915 b43_mac_enable(dev);
e4d6b795
MB		 3916 mutex_unlock(&wl->mutex);
3917
3918 return err;
3919}
3920
881d948c 3921static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3922{
3923 struct ieee80211_supported_band *sband =
3924 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3925 struct ieee80211_rate *rate;
3926 int i;
3927 u16 basic, direct, offset, basic_offset, rateptr;
3928
3929 for (i = 0; i < sband->n_bitrates; i++) {
3930 rate = &sband->bitrates[i];
3931
3932 if (b43_is_cck_rate(rate->hw_value)) {
3933 direct = B43_SHM_SH_CCKDIRECT;
3934 basic = B43_SHM_SH_CCKBASIC;
3935 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3936 offset &= 0xF;
3937 } else {
3938 direct = B43_SHM_SH_OFDMDIRECT;
3939 basic = B43_SHM_SH_OFDMBASIC;
3940 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3941 offset &= 0xF;
3942 }
3943
3944 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3945
3946 if (b43_is_cck_rate(rate->hw_value)) {
3947 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3948 basic_offset &= 0xF;
3949 } else {
3950 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3951 basic_offset &= 0xF;
3952 }
3953
3954 /*
3955 * Get the pointer that we need to point to
3956 * from the direct map
3957 */
3958 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3959 direct + 2 * basic_offset);
3960 /* and write it to the basic map */
3961 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3962 rateptr);
3963 }
3964}
3965
3966static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3967 struct ieee80211_vif *vif,
3968 struct ieee80211_bss_conf *conf,
3969 u32 changed)
3970{
3971 struct b43_wl *wl = hw_to_b43_wl(hw);
3972 struct b43_wldev *dev;
c7ab5ef9
JB		 3973
3974 mutex_lock(&wl->mutex);
3975
3976 dev = wl->current_dev;
d10d0e57 3977 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3978 goto out_unlock_mutex;
2d0ddec5
JB		 3979
3980 B43_WARN_ON(wl->vif != vif);
3981
3982 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3983 if (conf->bssid)
3984 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3985 else
3986 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3987 }
2d0ddec5 3988
3f0d843b
JB		 3989 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3990 if (changed & BSS_CHANGED_BEACON &&
3991 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3992 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3993 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3994 b43_update_templates(wl);
3995
3996 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3997 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3998 }
3999
c7ab5ef9
JB		 4000 b43_mac_suspend(dev);
4001
57c4d7b4
JB		 4002 /* Update templates for AP/mesh mode. */
4003 if (changed & BSS_CHANGED_BEACON_INT &&
4004 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4005 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 4006 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4007 conf->beacon_int)
57c4d7b4
JB		 4008 b43_set_beacon_int(dev, conf->beacon_int);
4009
c7ab5ef9
JB		 4010 if (changed & BSS_CHANGED_BASIC_RATES)
4011 b43_update_basic_rates(dev, conf->basic_rates);
4012
4013 if (changed & BSS_CHANGED_ERP_SLOT) {
4014 if (conf->use_short_slot)
4015 b43_short_slot_timing_enable(dev);
4016 else
4017 b43_short_slot_timing_disable(dev);
4018 }
4019
4020 b43_mac_enable(dev);
d10d0e57 4021out_unlock_mutex:
c7ab5ef9 4022 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 4023}
4024
40faacc4 4025static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4026 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4027 struct ieee80211_key_conf *key)
e4d6b795
MB		 4028{
4029 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4030 struct b43_wldev *dev;
e4d6b795
MB		 4031 u8 algorithm;
4032 u8 index;
c6dfc9a8 4033 int err;
060210f9 4034 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4035
4036 if (modparam_nohwcrypt)
4037 return -ENOSPC; /* User disabled HW-crypto */
4038
78f9c850
AQ		 4039 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4040 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4041 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4042 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4043 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4044 /*
4045 * For now, disable hw crypto for the RSN IBSS group keys. This
4046 * could be optimized in the future, but until that gets
4047 * implemented, use of software crypto for group addressed
4048 * frames is a acceptable to allow RSN IBSS to be used.
4049 */
4050 return -EOPNOTSUPP;
4051 }
4052
c6dfc9a8 4053 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4054
4055 dev = wl->current_dev;
4056 err = -ENODEV;
4057 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4058 goto out_unlock;
4059
403a3a13 4060 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4061 /* We don't have firmware for the crypto engine.
4062 * Must use software-crypto. */
4063 err = -EOPNOTSUPP;
4064 goto out_unlock;
4065 }
4066
c6dfc9a8 4067 err = -EINVAL;
97359d12
JB		 4068 switch (key->cipher) {
4069 case WLAN_CIPHER_SUITE_WEP40:
4070 algorithm = B43_SEC_ALGO_WEP40;
4071 break;
4072 case WLAN_CIPHER_SUITE_WEP104:
4073 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4074 break;
97359d12 4075 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4076 algorithm = B43_SEC_ALGO_TKIP;
4077 break;
97359d12 4078 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4079 algorithm = B43_SEC_ALGO_AES;
4080 break;
4081 default:
4082 B43_WARN_ON(1);
c6dfc9a8 4083 goto out_unlock;
e4d6b795 4084 }
e4d6b795
MB		 4085 index = (u8) (key->keyidx);
4086 if (index > 3)
e4d6b795 4087 goto out_unlock;
e4d6b795
MB		 4088
4089 switch (cmd) {
4090 case SET_KEY:
035d0243 4091 if (algorithm == B43_SEC_ALGO_TKIP &&
4092 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4093 !modparam_hwtkip)) {
4094 /* We support only pairwise key */
e4d6b795
MB		 4095 err = -EOPNOTSUPP;
4096 goto out_unlock;
4097 }
4098
e808e586 4099 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4100 if (WARN_ON(!sta)) {
4101 err = -EOPNOTSUPP;
4102 goto out_unlock;
4103 }
e808e586 4104 /* Pairwise key with an assigned MAC address. */
e4d6b795 4105 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4106 key->key, key->keylen,
4107 sta->addr, key);
e808e586
MB		 4108 } else {
4109 /* Group key */
4110 err = b43_key_write(dev, index, algorithm,
4111 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4112 }
4113 if (err)
4114 goto out_unlock;
4115
4116 if (algorithm == B43_SEC_ALGO_WEP40 ||
4117 algorithm == B43_SEC_ALGO_WEP104) {
4118 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4119 } else {
4120 b43_hf_write(dev,
4121 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4122 }
4123 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4124 if (algorithm == B43_SEC_ALGO_TKIP)
4125 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4126 break;
4127 case DISABLE_KEY: {
4128 err = b43_key_clear(dev, key->hw_key_idx);
4129 if (err)
4130 goto out_unlock;
4131 break;
4132 }
4133 default:
4134 B43_WARN_ON(1);
4135 }
9cf7f247 4136
e4d6b795 4137out_unlock:
e4d6b795
MB		 4138 if (!err) {
4139 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4140 "mac: %pM\n",
e4d6b795 4141 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4142 sta ? sta->addr : bcast_addr);
9cf7f247 4143 b43_dump_keymemory(dev);
e4d6b795 4144 }
9cf7f247
MB		 4145 mutex_unlock(&wl->mutex);
4146
e4d6b795
MB		 4147 return err;
4148}
4149
40faacc4
MB		 4150static void b43_op_configure_filter(struct ieee80211_hw *hw,
4151 unsigned int changed, unsigned int *fflags,
3ac64bee 4152 u64 multicast)
e4d6b795
MB		 4153{
4154 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4155 struct b43_wldev *dev;
e4d6b795 4156
36dbd954
MB		 4157 mutex_lock(&wl->mutex);
4158 dev = wl->current_dev;
4150c572
JB		 4159 if (!dev) {
4160 *fflags = 0;
36dbd954 4161 goto out_unlock;
e4d6b795 4162 }
4150c572 4163
4150c572
JB		 4164 *fflags &= FIF_PROMISC_IN_BSS |
4165 FIF_ALLMULTI |
4166 FIF_FCSFAIL |
4167 FIF_PLCPFAIL |
4168 FIF_CONTROL |
4169 FIF_OTHER_BSS |
4170 FIF_BCN_PRBRESP_PROMISC;
4171
4172 changed &= FIF_PROMISC_IN_BSS |
4173 FIF_ALLMULTI |
4174 FIF_FCSFAIL |
4175 FIF_PLCPFAIL |
4176 FIF_CONTROL |
4177 FIF_OTHER_BSS |
4178 FIF_BCN_PRBRESP_PROMISC;
4179
4180 wl->filter_flags = *fflags;
4181
4182 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4183 b43_adjust_opmode(dev);
36dbd954
MB		 4184
4185out_unlock:
4186 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4187}
4188
36dbd954
MB		 4189/* Locking: wl->mutex
4190 * Returns the current dev. This might be different from the passed in dev,
4191 * because the core might be gone away while we unlocked the mutex. */
4192static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4193{
9a53bf54 4194 struct b43_wl *wl;
36dbd954 4195 struct b43_wldev *orig_dev;
49d965c8 4196 u32 mask;
bad69194 4197 int queue_num;
e4d6b795 4198
9a53bf54
LF		 4199 if (!dev)
4200 return NULL;
4201 wl = dev->wl;
36dbd954
MB		 4202redo:
4203 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4204 return dev;
a19d12d7 4205
f5d40eed 4206 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4207 mutex_unlock(&wl->mutex);
4208 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4209 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4210 mutex_lock(&wl->mutex);
4211 dev = wl->current_dev;
4212 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4213 /* Whoops, aliens ate up the device while we were unlocked. */
4214 return dev;
4215 }
a19d12d7 4216
36dbd954 4217 /* Disable interrupts on the device. */
e4d6b795 4218 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4219 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4220 /* wl->mutex is locked. That is enough. */
4221 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4222 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4223 } else {
4224 spin_lock_irq(&wl->hardirq_lock);
4225 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4226 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4227 spin_unlock_irq(&wl->hardirq_lock);
4228 }
176e9f6a 4229 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4230 orig_dev = dev;
e4d6b795 4231 mutex_unlock(&wl->mutex);
505fb019 4232 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4233 b43_sdio_free_irq(dev);
4234 } else {
a18c715e
RM		 4235 synchronize_irq(dev->dev->irq);
4236 free_irq(dev->dev->irq, dev);
176e9f6a 4237 }
e4d6b795 4238 mutex_lock(&wl->mutex);
36dbd954
MB		 4239 dev = wl->current_dev;
4240 if (!dev)
4241 return dev;
4242 if (dev != orig_dev) {
4243 if (b43_status(dev) >= B43_STAT_STARTED)
4244 goto redo;
4245 return dev;
4246 }
49d965c8
MB		 4247 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4248 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4249
bad69194 4250 /* Drain all TX queues. */
4251 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
78f18df4
FF		 4252 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4253 struct sk_buff *skb;
4254
4255 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4256 ieee80211_free_txskb(wl->hw, skb);
4257 }
bad69194 4258 }
f5d40eed 4259
e4d6b795 4260 b43_mac_suspend(dev);
a78b3bb2 4261 b43_leds_exit(dev);
e4d6b795 4262 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4263
4264 return dev;
e4d6b795
MB		 4265}
4266
4267/* Locking: wl->mutex */
4268static int b43_wireless_core_start(struct b43_wldev *dev)
4269{
4270 int err;
4271
4272 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4273
4274 drain_txstatus_queue(dev);
505fb019 4275 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4276 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4277 if (err) {
4278 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4279 goto out;
4280 }
4281 } else {
a18c715e 4282 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4283 b43_interrupt_thread_handler,
4284 IRQF_SHARED, KBUILD_MODNAME, dev);
4285 if (err) {
dedb1eb9 4286 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4287 dev->dev->irq);
3dbba8e2
AH		 4288 goto out;
4289 }
e4d6b795
MB		 4290 }
4291
4292 /* We are ready to run. */
0866b03c 4293 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4294 b43_set_status(dev, B43_STAT_STARTED);
4295
4296 /* Start data flow (TX/RX). */
4297 b43_mac_enable(dev);
13790728 4298 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4299
25985edc 4300 /* Start maintenance work */
e4d6b795
MB		 4301 b43_periodic_tasks_setup(dev);
4302
a78b3bb2
MB		 4303 b43_leds_init(dev);
4304
e4d6b795 4305 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4306out:
e4d6b795
MB		 4307 return err;
4308}
4309
2fdf8c54
RM		 4310static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4311{
4312 switch (phy_type) {
4313 case B43_PHYTYPE_A:
4314 return "A";
4315 case B43_PHYTYPE_B:
4316 return "B";
4317 case B43_PHYTYPE_G:
4318 return "G";
4319 case B43_PHYTYPE_N:
4320 return "N";
4321 case B43_PHYTYPE_LP:
4322 return "LP";
4323 case B43_PHYTYPE_SSLPN:
4324 return "SSLPN";
4325 case B43_PHYTYPE_HT:
4326 return "HT";
4327 case B43_PHYTYPE_LCN:
4328 return "LCN";
4329 case B43_PHYTYPE_LCNXN:
4330 return "LCNXN";
4331 case B43_PHYTYPE_LCN40:
4332 return "LCN40";
4333 case B43_PHYTYPE_AC:
4334 return "AC";
4335 }
4336 return "UNKNOWN";
4337}
4338
e4d6b795
MB		 4339/* Get PHY and RADIO versioning numbers */
4340static int b43_phy_versioning(struct b43_wldev *dev)
4341{
4342 struct b43_phy *phy = &dev->phy;
fe5e499f 4343 const u8 core_rev = dev->dev->core_rev;
e4d6b795
MB		 4344 u32 tmp;
4345 u8 analog_type;
4346 u8 phy_type;
4347 u8 phy_rev;
4348 u16 radio_manuf;
4349 u16 radio_ver;
4350 u16 radio_rev;
4351 int unsupported = 0;
4352
4353 /* Get PHY versioning */
4354 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4355 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4356 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4357 phy_rev = (tmp & B43_PHYVER_VERSION);
b49c3caf
RM		 4358
4359 /* LCNXN is continuation of N which run out of revisions */
4360 if (phy_type == B43_PHYTYPE_LCNXN) {
4361 phy_type = B43_PHYTYPE_N;
4362 phy_rev += 16;
4363 }
4364
e4d6b795 4365 switch (phy_type) {
418378fe 4366#ifdef CONFIG_B43_PHY_G
e4d6b795 4367 case B43_PHYTYPE_G:
013978b6 4368 if (phy_rev > 9)
e4d6b795
MB		 4369 unsupported = 1;
4370 break;
418378fe 4371#endif
692d2c0f 4372#ifdef CONFIG_B43_PHY_N
d5c71e46 4373 case B43_PHYTYPE_N:
40c68f20 4374 if (phy_rev >= 19)
d5c71e46
MB		 4375 unsupported = 1;
4376 break;
6b1c7c67
MB		 4377#endif
4378#ifdef CONFIG_B43_PHY_LP
4379 case B43_PHYTYPE_LP:
9d86a2d5 4380 if (phy_rev > 2)
6b1c7c67
MB		 4381 unsupported = 1;
4382 break;
d7520b1d
RM		 4383#endif
4384#ifdef CONFIG_B43_PHY_HT
4385 case B43_PHYTYPE_HT:
4386 if (phy_rev > 1)
4387 unsupported = 1;
4388 break;
1d738e64
RM		 4389#endif
4390#ifdef CONFIG_B43_PHY_LCN
4391 case B43_PHYTYPE_LCN:
4392 if (phy_rev > 1)
4393 unsupported = 1;
4394 break;
d5c71e46 4395#endif
e4d6b795
MB		 4396 default:
4397 unsupported = 1;
6403eab1 4398 }
e4d6b795 4399 if (unsupported) {
2fdf8c54
RM		 4400 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4401 analog_type, phy_type, b43_phy_name(dev, phy_type),
4402 phy_rev);
e4d6b795
MB		 4403 return -EOPNOTSUPP;
4404 }
2fdf8c54
RM		 4405 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4406 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
e4d6b795
MB		 4407
4408 /* Get RADIO versioning */
fe5e499f
RM		 4409 if (core_rev == 40 || core_rev == 42) {
4410 radio_manuf = 0x17F;
4411
4412 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 0);
4413 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4414
4415 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1);
4416 radio_ver = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4417 } else if (core_rev >= 24) {
544e5d8b
RM		 4418 u16 radio24[3];
4419
4420 for (tmp = 0; tmp < 3; tmp++) {
4421 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4422 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4423 }
4424
4425 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4426 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4427
4428 radio_manuf = 0x17F;
4429 radio_ver = (radio24[2] << 8) | radio24[1];
4430 radio_rev = (radio24[0] & 0xF);
e4d6b795 4431 } else {
3fd48508
RM		 4432 if (dev->dev->chip_id == 0x4317) {
4433 if (dev->dev->chip_rev == 0)
4434 tmp = 0x3205017F;
4435 else if (dev->dev->chip_rev == 1)
4436 tmp = 0x4205017F;
4437 else
4438 tmp = 0x5205017F;
4439 } else {
4440 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4441 B43_RADIOCTL_ID);
4442 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4443 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4444 B43_RADIOCTL_ID);
4445 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4446 << 16;
4447 }
4448 radio_manuf = (tmp & 0x00000FFF);
4449 radio_ver = (tmp & 0x0FFFF000) >> 12;
4450 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4451 }
3fd48508 4452
96c755a3
MB		 4453 if (radio_manuf != 0x17F /* Broadcom */)
4454 unsupported = 1;
e4d6b795
MB		 4455 switch (phy_type) {
4456 case B43_PHYTYPE_A:
4457 if (radio_ver != 0x2060)
4458 unsupported = 1;
4459 if (radio_rev != 1)
4460 unsupported = 1;
4461 if (radio_manuf != 0x17F)
4462 unsupported = 1;
4463 break;
4464 case B43_PHYTYPE_B:
4465 if ((radio_ver & 0xFFF0) != 0x2050)
4466 unsupported = 1;
4467 break;
4468 case B43_PHYTYPE_G:
4469 if (radio_ver != 0x2050)
4470 unsupported = 1;
4471 break;
96c755a3 4472 case B43_PHYTYPE_N:
3695b932
RM		 4473 if (radio_ver != 0x2055 && radio_ver != 0x2056 &&
4474 radio_ver != 0x2057)
4475 unsupported = 1;
4476 if (radio_ver == 0x2057 && !(radio_rev == 9))
96c755a3
MB		 4477 unsupported = 1;
4478 break;
6b1c7c67 4479 case B43_PHYTYPE_LP:
9d86a2d5 4480 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4481 unsupported = 1;
4482 break;
d7520b1d
RM		 4483 case B43_PHYTYPE_HT:
4484 if (radio_ver != 0x2059)
4485 unsupported = 1;
4486 break;
1d738e64
RM		 4487 case B43_PHYTYPE_LCN:
4488 if (radio_ver != 0x2064)
4489 unsupported = 1;
4490 break;
e4d6b795
MB		 4491 default:
4492 B43_WARN_ON(1);
4493 }
4494 if (unsupported) {
88d825bf
RM		 4495 b43err(dev->wl,
4496 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u)\n",
e4d6b795
MB		 4497 radio_manuf, radio_ver, radio_rev);
4498 return -EOPNOTSUPP;
4499 }
88d825bf
RM		 4500 b43info(dev->wl, "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u\n",
4501 radio_manuf, radio_ver, radio_rev);
e4d6b795
MB		 4502
4503 phy->radio_manuf = radio_manuf;
4504 phy->radio_ver = radio_ver;
4505 phy->radio_rev = radio_rev;
4506
4507 phy->analog = analog_type;
4508 phy->type = phy_type;
4509 phy->rev = phy_rev;
4510
4511 return 0;
4512}
4513
4514static void setup_struct_phy_for_init(struct b43_wldev *dev,
4515 struct b43_phy *phy)
4516{
e4d6b795 4517 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4518 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4519 /* PHY TX errors counter. */
4520 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4521
4522#if B43_DEBUG
3db1cd5c
RR		 4523 phy->phy_locked = false;
4524 phy->radio_locked = false;
591f3dc2 4525#endif
e4d6b795
MB		 4526}
4527
4528static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4529{
3db1cd5c 4530 dev->dfq_valid = false;
aa6c7ae2 4531
6a724d68
MB		 4532 /* Assume the radio is enabled. If it's not enabled, the state will
4533 * immediately get fixed on the first periodic work run. */
3db1cd5c 4534 dev->radio_hw_enable = true;
e4d6b795
MB		 4535
4536 /* Stats */
4537 memset(&dev->stats, 0, sizeof(dev->stats));
4538
4539 setup_struct_phy_for_init(dev, &dev->phy);
4540
4541 /* IRQ related flags */
4542 dev->irq_reason = 0;
4543 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4544 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4545 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4546 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4547
4548 dev->mac_suspended = 1;
4549
4550 /* Noise calculation context */
4551 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4552}
4553
4554static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4555{
0581483a 4556 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4557 u64 hf;
e4d6b795 4558
1855ba78
MB		 4559 if (!modparam_btcoex)
4560 return;
95de2841 4561 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4562 return;
4563 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4564 return;
4565
4566 hf = b43_hf_read(dev);
95de2841 4567 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4568 hf |= B43_HF_BTCOEXALT;
4569 else
4570 hf |= B43_HF_BTCOEX;
4571 b43_hf_write(dev, hf);
e4d6b795
MB		 4572}
4573
4574static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4575{
4576 if (!modparam_btcoex)
4577 return;
4578 //TODO
e4d6b795
MB		 4579}
4580
4581static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4582{
d48ae5c8 4583 struct ssb_bus *bus;
e4d6b795
MB		 4584 u32 tmp;
4585
bd7c8a59 4586#ifdef CONFIG_B43_SSB
d48ae5c8
RM		 4587 if (dev->dev->bus_type != B43_BUS_SSB)
4588 return;
bd7c8a59
RM		 4589#else
4590 return;
4591#endif
d48ae5c8
RM		 4592
4593 bus = dev->dev->sdev->bus;
4594
0fd82eaf
RM		 4595 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4596 (bus->chip_id == 0x4312)) {
d48ae5c8 4597 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4598 tmp &= ~SSB_IMCFGLO_REQTO;
4599 tmp &= ~SSB_IMCFGLO_SERTO;
4600 tmp |= 0x3;
d48ae5c8 4601 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4602 ssb_commit_settings(bus);
e4d6b795 4603 }
e4d6b795
MB		 4604}
4605
d59f720d
MB		 4606static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4607{
4608 u16 pu_delay;
4609
4610 /* The time value is in microseconds. */
4611 if (dev->phy.type == B43_PHYTYPE_A)
4612 pu_delay = 3700;
4613 else
4614 pu_delay = 1050;
05c914fe 4615 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4616 pu_delay = 500;
4617 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4618 pu_delay = max(pu_delay, (u16)2400);
4619
4620 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4621}
4622
4623/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4624static void b43_set_pretbtt(struct b43_wldev *dev)
4625{
4626 u16 pretbtt;
4627
4628 /* The time value is in microseconds. */
05c914fe 4629 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4630 pretbtt = 2;
4631 } else {
4632 if (dev->phy.type == B43_PHYTYPE_A)
4633 pretbtt = 120;
4634 else
4635 pretbtt = 250;
4636 }
4637 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4638 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4639}
4640
e4d6b795
MB		 4641/* Shutdown a wireless core */
4642/* Locking: wl->mutex */
4643static void b43_wireless_core_exit(struct b43_wldev *dev)
4644{
36dbd954
MB		 4645 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4646 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4647 return;
84c164a3 4648
e4d6b795
MB		 4649 b43_set_status(dev, B43_STAT_UNINIT);
4650
1f7d87b0 4651 /* Stop the microcode PSM. */
5056635c
RM		 4652 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4653 B43_MACCTL_PSM_JMP0);
1f7d87b0 4654
50023008
HM		 4655 switch (dev->dev->bus_type) {
4656#ifdef CONFIG_B43_BCMA
4657 case B43_BUS_BCMA:
4658 bcma_core_pci_down(dev->dev->bdev->bus);
4659 break;
4660#endif
4661#ifdef CONFIG_B43_SSB
4662 case B43_BUS_SSB:
4663 /* TODO */
4664 break;
4665#endif
4666 }
4667
e4d6b795 4668 b43_dma_free(dev);
5100d5ac 4669 b43_pio_free(dev);
e4d6b795 4670 b43_chip_exit(dev);
cb24f57f 4671 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4672 if (dev->wl->current_beacon) {
4673 dev_kfree_skb_any(dev->wl->current_beacon);
4674 dev->wl->current_beacon = NULL;
4675 }
4676
24ca39d6
RM		 4677 b43_device_disable(dev, 0);
4678 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4679}
4680
4681/* Initialize a wireless core */
4682static int b43_wireless_core_init(struct b43_wldev *dev)
4683{
0581483a 4684 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4685 struct b43_phy *phy = &dev->phy;
4686 int err;
a259d6a4 4687 u64 hf;
e4d6b795
MB		 4688
4689 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4690
24ca39d6 4691 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4692 if (err)
4693 goto out;
4da909e7
RM		 4694 if (!b43_device_is_enabled(dev))
4695 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4696
fb11137a 4697 /* Reset all data structures. */
e4d6b795 4698 setup_struct_wldev_for_init(dev);
fb11137a 4699 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4700
4701 /* Enable IRQ routing to this device. */
6cbab0d9 4702 switch (dev->dev->bus_type) {
42c9a458
RM		 4703#ifdef CONFIG_B43_BCMA
4704 case B43_BUS_BCMA:
dfae7143 4705 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
42c9a458 4706 dev->dev->bdev, true);
50023008 4707 bcma_core_pci_up(dev->dev->bdev->bus);
42c9a458
RM		 4708 break;
4709#endif
6cbab0d9
RM		 4710#ifdef CONFIG_B43_SSB
4711 case B43_BUS_SSB:
4712 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4713 dev->dev->sdev);
4714 break;
4715#endif
4716 }
e4d6b795
MB		 4717
4718 b43_imcfglo_timeouts_workaround(dev);
4719 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4720 if (phy->ops->prepare_hardware) {
4721 err = phy->ops->prepare_hardware(dev);
ef1a628d 4722 if (err)
fb11137a 4723 goto err_busdown;
ef1a628d 4724 }
e4d6b795
MB		 4725 err = b43_chip_init(dev);
4726 if (err)
fb11137a 4727 goto err_busdown;
e4d6b795 4728 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4729 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4730 hf = b43_hf_read(dev);
4731 if (phy->type == B43_PHYTYPE_G) {
4732 hf |= B43_HF_SYMW;
4733 if (phy->rev == 1)
4734 hf |= B43_HF_GDCW;
95de2841 4735 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4736 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4737 }
4738 if (phy->radio_ver == 0x2050) {
4739 if (phy->radio_rev == 6)
4740 hf |= B43_HF_4318TSSI;
4741 if (phy->radio_rev < 6)
4742 hf |= B43_HF_VCORECALC;
e4d6b795 4743 }
1cc8f476
MB		 4744 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4745 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
bd7c8a59 4746#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
6cbab0d9
RM		 4747 if (dev->dev->bus_type == B43_BUS_SSB &&
4748 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4749 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4750 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4751#endif
25d3ef59 4752 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4753 b43_hf_write(dev, hf);
4754
74cfdba7
MB		 4755 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4756 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4757 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4758 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4759
4760 /* Disable sending probe responses from firmware.
4761 * Setting the MaxTime to one usec will always trigger
4762 * a timeout, so we never send any probe resp.
4763 * A timeout of zero is infinite. */
4764 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4765
4766 b43_rate_memory_init(dev);
5042c507 4767 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4768
4769 /* Minimum Contention Window */
c5a079f4 4770 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4771 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4772 else
e4d6b795 4773 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4774 /* Maximum Contention Window */
4775 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4776
505fb019 4777 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4778 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4779 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4780 err = b43_pio_init(dev);
4781 } else if (dev->use_pio) {
4782 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4783 "This should not be needed and will result in lower "
4784 "performance.\n");
3db1cd5c 4785 dev->__using_pio_transfers = true;
5100d5ac
MB		 4786 err = b43_pio_init(dev);
4787 } else {
3db1cd5c 4788 dev->__using_pio_transfers = false;
5100d5ac
MB		 4789 err = b43_dma_init(dev);
4790 }
e4d6b795
MB		 4791 if (err)
4792 goto err_chip_exit;
03b29773 4793 b43_qos_init(dev);
d59f720d 4794 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4795 b43_bluetooth_coext_enable(dev);
4796
24ca39d6 4797 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4798 b43_upload_card_macaddress(dev);
e4d6b795 4799 b43_security_init(dev);
e4d6b795 4800
5ab9549a 4801 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4802
4803 b43_set_status(dev, B43_STAT_INITIALIZED);
4804
1a8d1227 4805out:
e4d6b795
MB		 4806 return err;
4807
ef1a628d 4808err_chip_exit:
e4d6b795 4809 b43_chip_exit(dev);
ef1a628d 4810err_busdown:
24ca39d6 4811 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4812 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4813 return err;
4814}
4815
40faacc4 4816static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4817 struct ieee80211_vif *vif)
e4d6b795
MB		 4818{
4819 struct b43_wl *wl = hw_to_b43_wl(hw);
4820 struct b43_wldev *dev;
e4d6b795 4821 int err = -EOPNOTSUPP;
4150c572
JB		 4822
4823 /* TODO: allow WDS/AP devices to coexist */
4824
1ed32e4f
JB		 4825 if (vif->type != NL80211_IFTYPE_AP &&
4826 vif->type != NL80211_IFTYPE_MESH_POINT &&
4827 vif->type != NL80211_IFTYPE_STATION &&
4828 vif->type != NL80211_IFTYPE_WDS &&
4829 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4830 return -EOPNOTSUPP;
e4d6b795
MB		 4831
4832 mutex_lock(&wl->mutex);
4150c572 4833 if (wl->operating)
e4d6b795
MB		 4834 goto out_mutex_unlock;
4835
1ed32e4f 4836 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4837
4838 dev = wl->current_dev;
3db1cd5c 4839 wl->operating = true;
1ed32e4f
JB		 4840 wl->vif = vif;
4841 wl->if_type = vif->type;
4842 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4843
4150c572 4844 b43_adjust_opmode(dev);
d59f720d
MB		 4845 b43_set_pretbtt(dev);
4846 b43_set_synth_pu_delay(dev, 0);
4150c572 4847 b43_upload_card_macaddress(dev);
4150c572
JB		 4848
4849 err = 0;
4850 out_mutex_unlock:
4851 mutex_unlock(&wl->mutex);
4852
2a190322
FF		 4853 if (err == 0)
4854 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4855
4150c572
JB		 4856 return err;
4857}
4858
40faacc4 4859static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4860 struct ieee80211_vif *vif)
4150c572
JB		 4861{
4862 struct b43_wl *wl = hw_to_b43_wl(hw);
4863 struct b43_wldev *dev = wl->current_dev;
4150c572 4864
1ed32e4f 4865 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4866
4867 mutex_lock(&wl->mutex);
4868
4869 B43_WARN_ON(!wl->operating);
1ed32e4f 4870 B43_WARN_ON(wl->vif != vif);
32bfd35d 4871 wl->vif = NULL;
4150c572 4872
3db1cd5c 4873 wl->operating = false;
4150c572 4874
4150c572
JB		 4875 b43_adjust_opmode(dev);
4876 memset(wl->mac_addr, 0, ETH_ALEN);
4877 b43_upload_card_macaddress(dev);
4150c572
JB		 4878
4879 mutex_unlock(&wl->mutex);
4880}
4881
40faacc4 4882static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4883{
4884 struct b43_wl *wl = hw_to_b43_wl(hw);
4885 struct b43_wldev *dev = wl->current_dev;
4886 int did_init = 0;
923403b8 4887 int err = 0;
4150c572 4888
7be1bb6b
MB		 4889 /* Kill all old instance specific information to make sure
4890 * the card won't use it in the short timeframe between start
4891 * and mac80211 reconfiguring it. */
4892 memset(wl->bssid, 0, ETH_ALEN);
4893 memset(wl->mac_addr, 0, ETH_ALEN);
4894 wl->filter_flags = 0;
3db1cd5c 4895 wl->radiotap_enabled = false;
e6f5b934 4896 b43_qos_clear(wl);
3db1cd5c
RR		 4897 wl->beacon0_uploaded = false;
4898 wl->beacon1_uploaded = false;
4899 wl->beacon_templates_virgin = true;
4900 wl->radio_enabled = true;
7be1bb6b 4901
4150c572
JB		 4902 mutex_lock(&wl->mutex);
4903
e4d6b795
MB		 4904 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4905 err = b43_wireless_core_init(dev);
f41f3f37 4906 if (err)
e4d6b795
MB		 4907 goto out_mutex_unlock;
4908 did_init = 1;
4909 }
4150c572 4910
e4d6b795
MB		 4911 if (b43_status(dev) < B43_STAT_STARTED) {
4912 err = b43_wireless_core_start(dev);
4913 if (err) {
4914 if (did_init)
4915 b43_wireless_core_exit(dev);
4916 goto out_mutex_unlock;
4917 }
4918 }
4919
f41f3f37
JB		 4920 /* XXX: only do if device doesn't support rfkill irq */
4921 wiphy_rfkill_start_polling(hw->wiphy);
4922
4150c572 4923 out_mutex_unlock:
e4d6b795
MB		 4924 mutex_unlock(&wl->mutex);
4925
dbdedbdf
SF		 4926 /*
4927 * Configuration may have been overwritten during initialization.
4928 * Reload the configuration, but only if initialization was
4929 * successful. Reloading the configuration after a failed init
4930 * may hang the system.
4931 */
4932 if (!err)
4933 b43_op_config(hw, ~0);
2a190322 4934
e4d6b795
MB		 4935 return err;
4936}
4937
40faacc4 4938static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4939{
4940 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4941 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4942
a82d9922 4943 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4944
ccde8a45
GL		 4945 if (!dev)
4946 goto out;
4947
e4d6b795 4948 mutex_lock(&wl->mutex);
36dbd954
MB		 4949 if (b43_status(dev) >= B43_STAT_STARTED) {
4950 dev = b43_wireless_core_stop(dev);
4951 if (!dev)
4952 goto out_unlock;
4953 }
4150c572 4954 b43_wireless_core_exit(dev);
3db1cd5c 4955 wl->radio_enabled = false;
36dbd954
MB		 4956
4957out_unlock:
e4d6b795 4958 mutex_unlock(&wl->mutex);
ccde8a45 4959out:
18c8adeb 4960 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4961}
4962
17741cdc
JB		 4963static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4964 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4965{
4966 struct b43_wl *wl = hw_to_b43_wl(hw);
4967
8f611288 4968 /* FIXME: add locking */
9d139c81 4969 b43_update_templates(wl);
e66fee6a
MB		 4970
4971 return 0;
4972}
4973
38968d09
JB		 4974static void b43_op_sta_notify(struct ieee80211_hw *hw,
4975 struct ieee80211_vif *vif,
4976 enum sta_notify_cmd notify_cmd,
17741cdc 4977 struct ieee80211_sta *sta)
38968d09
JB		 4978{
4979 struct b43_wl *wl = hw_to_b43_wl(hw);
4980
4981 B43_WARN_ON(!vif || wl->vif != vif);
4982}
4983
25d3ef59
MB		 4984static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4985{
4986 struct b43_wl *wl = hw_to_b43_wl(hw);
4987 struct b43_wldev *dev;
4988
4989 mutex_lock(&wl->mutex);
4990 dev = wl->current_dev;
4991 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4992 /* Disable CFP update during scan on other channels. */
4993 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4994 }
4995 mutex_unlock(&wl->mutex);
4996}
4997
4998static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4999{
5000 struct b43_wl *wl = hw_to_b43_wl(hw);
5001 struct b43_wldev *dev;
5002
5003 mutex_lock(&wl->mutex);
5004 dev = wl->current_dev;
5005 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5006 /* Re-enable CFP update. */
5007 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5008 }
5009 mutex_unlock(&wl->mutex);
5010}
5011
354b4f04
JL		 5012static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5013 struct survey_info *survey)
5014{
5015 struct b43_wl *wl = hw_to_b43_wl(hw);
5016 struct b43_wldev *dev = wl->current_dev;
5017 struct ieee80211_conf *conf = &hw->conf;
5018
5019 if (idx != 0)
5020 return -ENOENT;
5021
675a0b04 5022 survey->channel = conf->chandef.chan;
354b4f04
JL		 5023 survey->filled = SURVEY_INFO_NOISE_DBM;
5024 survey->noise = dev->stats.link_noise;
5025
5026 return 0;
5027}
5028
e4d6b795 5029static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 5030 .tx = b43_op_tx,
5031 .conf_tx = b43_op_conf_tx,
5032 .add_interface = b43_op_add_interface,
5033 .remove_interface = b43_op_remove_interface,
5034 .config = b43_op_config,
c7ab5ef9 5035 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 5036 .configure_filter = b43_op_configure_filter,
5037 .set_key = b43_op_set_key,
035d0243 5038 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 5039 .get_stats = b43_op_get_stats,
08e87a83
AF		 5040 .get_tsf = b43_op_get_tsf,
5041 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 5042 .start = b43_op_start,
5043 .stop = b43_op_stop,
e66fee6a 5044 .set_tim = b43_op_beacon_set_tim,
38968d09 5045 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 5046 .sw_scan_start = b43_op_sw_scan_start_notifier,
5047 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 5048 .get_survey = b43_op_get_survey,
f41f3f37 5049 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 5050};
5051
5052/* Hard-reset the chip. Do not call this directly.
5053 * Use b43_controller_restart()
5054 */
5055static void b43_chip_reset(struct work_struct *work)
5056{
5057 struct b43_wldev *dev =
5058 container_of(work, struct b43_wldev, restart_work);
5059 struct b43_wl *wl = dev->wl;
5060 int err = 0;
5061 int prev_status;
5062
5063 mutex_lock(&wl->mutex);
5064
5065 prev_status = b43_status(dev);
5066 /* Bring the device down... */
36dbd954
MB		 5067 if (prev_status >= B43_STAT_STARTED) {
5068 dev = b43_wireless_core_stop(dev);
5069 if (!dev) {
5070 err = -ENODEV;
5071 goto out;
5072 }
5073 }
e4d6b795
MB		 5074 if (prev_status >= B43_STAT_INITIALIZED)
5075 b43_wireless_core_exit(dev);
5076
5077 /* ...and up again. */
5078 if (prev_status >= B43_STAT_INITIALIZED) {
5079 err = b43_wireless_core_init(dev);
5080 if (err)
5081 goto out;
5082 }
5083 if (prev_status >= B43_STAT_STARTED) {
5084 err = b43_wireless_core_start(dev);
5085 if (err) {
5086 b43_wireless_core_exit(dev);
5087 goto out;
5088 }
5089 }
3bf0a32e
MB		 5090out:
5091 if (err)
5092 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5093 mutex_unlock(&wl->mutex);
2a190322
FF		 5094
5095 if (err) {
e4d6b795 5096 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5097 return;
5098 }
5099
5100 /* reload configuration */
5101 b43_op_config(wl->hw, ~0);
5102 if (wl->vif)
5103 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5104
5105 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5106}
5107
bb1eeff1 5108static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5109 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5110{
5111 struct ieee80211_hw *hw = dev->wl->hw;
3695b932
RM		 5112 struct b43_phy *phy = &dev->phy;
5113 bool limited_2g;
5114
5115 /* We don't support all 2 GHz channels on some devices */
5116 limited_2g = phy->radio_ver == 0x2057 && phy->radio_rev == 9;
e4d6b795 5117
bb1eeff1 5118 if (have_2ghz_phy)
3695b932
RM		 5119 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5120 &b43_band_2ghz_limited : &b43_band_2GHz;
bb1eeff1
MB		 5121 if (dev->phy.type == B43_PHYTYPE_N) {
5122 if (have_5ghz_phy)
5123 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5124 } else {
5125 if (have_5ghz_phy)
5126 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5127 }
96c755a3 5128
bb1eeff1
MB		 5129 dev->phy.supports_2ghz = have_2ghz_phy;
5130 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5131
5132 return 0;
5133}
5134
5135static void b43_wireless_core_detach(struct b43_wldev *dev)
5136{
5137 /* We release firmware that late to not be required to re-request
5138 * is all the time when we reinit the core. */
5139 b43_release_firmware(dev);
fb11137a 5140 b43_phy_free(dev);
e4d6b795
MB		 5141}
5142
075ca604
RM		 5143static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5144 bool *have_5ghz_phy)
5145{
5146 u16 dev_id = 0;
5147
773cfc50
RM		 5148#ifdef CONFIG_B43_BCMA
5149 if (dev->dev->bus_type == B43_BUS_BCMA &&
5150 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5151 dev_id = dev->dev->bdev->bus->host_pci->device;
5152#endif
075ca604
RM		 5153#ifdef CONFIG_B43_SSB
5154 if (dev->dev->bus_type == B43_BUS_SSB &&
5155 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5156 dev_id = dev->dev->sdev->bus->host_pci->device;
5157#endif
773cfc50
RM		 5158 /* Override with SPROM value if available */
5159 if (dev->dev->bus_sprom->dev_id)
5160 dev_id = dev->dev->bus_sprom->dev_id;
075ca604
RM		 5161
5162 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5163 switch (dev_id) {
5164 case 0x4324: /* BCM4306 */
5165 case 0x4312: /* BCM4311 */
5166 case 0x4319: /* BCM4318 */
773cfc50
RM		 5167 case 0x4328: /* BCM4321 */
5168 case 0x432b: /* BCM4322 */
5169 case 0x4350: /* BCM43222 */
5170 case 0x4353: /* BCM43224 */
5171 case 0x0576: /* BCM43224 */
5172 case 0x435f: /* BCM6362 */
5173 case 0x4331: /* BCM4331 */
5174 case 0x4359: /* BCM43228 */
5175 case 0x43a0: /* BCM4360 */
5176 case 0x43b1: /* BCM4352 */
075ca604
RM		 5177 /* Dual band devices */
5178 *have_2ghz_phy = true;
5179 *have_5ghz_phy = true;
5180 return;
773cfc50
RM		 5181 case 0x4321: /* BCM4306 */
5182 case 0x4313: /* BCM4311 */
5183 case 0x431a: /* BCM4318 */
5184 case 0x432a: /* BCM4321 */
5185 case 0x432d: /* BCM4322 */
5186 case 0x4352: /* BCM43222 */
5187 case 0x4333: /* BCM4331 */
5188 case 0x43a2: /* BCM4360 */
5189 case 0x43b3: /* BCM4352 */
5190 /* 5 GHz only devices */
5191 *have_2ghz_phy = false;
5192 *have_5ghz_phy = true;
5193 return;
075ca604
RM		 5194 }
5195
5196 /* As a fallback, try to guess using PHY type */
5197 switch (dev->phy.type) {
5198 case B43_PHYTYPE_A:
5199 *have_2ghz_phy = false;
5200 *have_5ghz_phy = true;
5201 return;
5202 case B43_PHYTYPE_G:
5203 case B43_PHYTYPE_N:
5204 case B43_PHYTYPE_LP:
5205 case B43_PHYTYPE_HT:
5206 case B43_PHYTYPE_LCN:
5207 *have_2ghz_phy = true;
5208 *have_5ghz_phy = false;
5209 return;
5210 }
5211
5212 B43_WARN_ON(1);
5213}
5214
e4d6b795
MB		 5215static int b43_wireless_core_attach(struct b43_wldev *dev)
5216{
5217 struct b43_wl *wl = dev->wl;
09951ad4 5218 struct b43_phy *phy = &dev->phy;
e4d6b795 5219 int err;
40c62269 5220 u32 tmp;
3db1cd5c 5221 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5222
5223 /* Do NOT do any device initialization here.
5224 * Do it in wireless_core_init() instead.
5225 * This function is for gathering basic information about the HW, only.
5226 * Also some structs may be set up here. But most likely you want to have
5227 * that in core_init(), too.
5228 */
5229
24ca39d6 5230 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5231 if (err) {
5232 b43err(wl, "Bus powerup failed\n");
5233 goto out;
5234 }
e4d6b795 5235
09951ad4
RM		 5236 phy->do_full_init = true;
5237
075ca604 5238 /* Try to guess supported bands for the first init needs */
6cbab0d9 5239 switch (dev->dev->bus_type) {
42c9a458
RM		 5240#ifdef CONFIG_B43_BCMA
5241 case B43_BUS_BCMA:
40c62269
RM		 5242 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5243 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5244 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5245 break;
5246#endif
6cbab0d9
RM		 5247#ifdef CONFIG_B43_SSB
5248 case B43_BUS_SSB:
5249 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5250 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5251 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5252 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5253 } else
5254 B43_WARN_ON(1);
5255 break;
5256#endif
5257 }
e4d6b795 5258
96c755a3 5259 dev->phy.gmode = have_2ghz_phy;
4da909e7 5260 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795 5261
075ca604 5262 /* Get the PHY type. */
e4d6b795
MB		 5263 err = b43_phy_versioning(dev);
5264 if (err)
21954c36 5265 goto err_powerdown;
075ca604
RM		 5266
5267 /* Get real info about supported bands */
5268 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5269
5270 /* We don't support 5 GHz on some PHYs yet */
5271 switch (dev->phy.type) {
5272 case B43_PHYTYPE_A:
f15ec345 5273 case B43_PHYTYPE_G:
075ca604
RM		 5274 case B43_PHYTYPE_N:
5275 case B43_PHYTYPE_LP:
773cfc50 5276 case B43_PHYTYPE_HT:
075ca604 5277 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
3db1cd5c 5278 have_5ghz_phy = false;
e4d6b795 5279 }
075ca604
RM		 5280
5281 if (!have_2ghz_phy && !have_5ghz_phy) {
5282 b43err(wl, "b43 can't support any band on this device\n");
96c755a3
MB		 5283 err = -EOPNOTSUPP;
5284 goto err_powerdown;
5285 }
2e35af14 5286
fb11137a
MB		 5287 err = b43_phy_allocate(dev);
5288 if (err)
5289 goto err_powerdown;
5290
96c755a3 5291 dev->phy.gmode = have_2ghz_phy;
4da909e7 5292 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5293
5294 err = b43_validate_chipaccess(dev);
5295 if (err)
fb11137a 5296 goto err_phy_free;
bb1eeff1 5297 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5298 if (err)
fb11137a 5299 goto err_phy_free;
e4d6b795
MB		 5300
5301 /* Now set some default "current_dev" */
5302 if (!wl->current_dev)
5303 wl->current_dev = dev;
5304 INIT_WORK(&dev->restart_work, b43_chip_reset);
5305
cb24f57f 5306 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5307 b43_device_disable(dev, 0);
5308 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5309
5310out:
5311 return err;
5312
fb11137a
MB		 5313err_phy_free:
5314 b43_phy_free(dev);
e4d6b795 5315err_powerdown:
24ca39d6 5316 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5317 return err;
5318}
5319
482f0538 5320static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5321{
5322 struct b43_wldev *wldev;
5323 struct b43_wl *wl;
5324
3bf0a32e
MB		 5325 /* Do not cancel ieee80211-workqueue based work here.
5326 * See comment in b43_remove(). */
5327
74abacb6 5328 wldev = b43_bus_get_wldev(dev);
e4d6b795 5329 wl = wldev->wl;
e4d6b795
MB		 5330 b43_debugfs_remove_device(wldev);
5331 b43_wireless_core_detach(wldev);
5332 list_del(&wldev->list);
74abacb6 5333 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5334 kfree(wldev);
5335}
5336
482f0538 5337static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5338{
5339 struct b43_wldev *wldev;
e4d6b795
MB		 5340 int err = -ENOMEM;
5341
e4d6b795
MB		 5342 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5343 if (!wldev)
5344 goto out;
5345
9e3bd919 5346 wldev->use_pio = b43_modparam_pio;
482f0538 5347 wldev->dev = dev;
e4d6b795
MB		 5348 wldev->wl = wl;
5349 b43_set_status(wldev, B43_STAT_UNINIT);
5350 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5351 INIT_LIST_HEAD(&wldev->list);
5352
5353 err = b43_wireless_core_attach(wldev);
5354 if (err)
5355 goto err_kfree_wldev;
5356
74abacb6 5357 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5358 b43_debugfs_add_device(wldev);
5359
5360 out:
5361 return err;
5362
5363 err_kfree_wldev:
5364 kfree(wldev);
5365 return err;
5366}
5367
9fc38458
MB		 5368#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5369 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5370 (pdev->device == _device) && \
5371 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5372 (pdev->subsystem_device == _subdevice) )
5373
bd7c8a59 5374#ifdef CONFIG_B43_SSB
e4d6b795
MB		 5375static void b43_sprom_fixup(struct ssb_bus *bus)
5376{
1855ba78
MB		 5377 struct pci_dev *pdev;
5378
e4d6b795
MB		 5379 /* boardflags workarounds */
5380 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5381 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5382 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5383 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5384 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5385 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5386 if (bus->bustype == SSB_BUSTYPE_PCI) {
5387 pdev = bus->host_pci;
9fc38458 5388 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5389 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5390 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5391 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5392 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5393 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5394 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5395 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5396 }
e4d6b795
MB		 5397}
5398
482f0538 5399static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5400{
5401 struct ieee80211_hw *hw = wl->hw;
5402
482f0538 5403 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5404 ieee80211_free_hw(hw);
5405}
bd7c8a59 5406#endif
e4d6b795 5407
d1507051 5408static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5409{
d1507051 5410 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5411 struct ieee80211_hw *hw;
5412 struct b43_wl *wl;
2729df25 5413 char chip_name[6];
bad69194 5414 int queue_num;
e4d6b795
MB		 5415
5416 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5417 if (!hw) {
5418 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5419 return ERR_PTR(-ENOMEM);
e4d6b795 5420 }
403a3a13 5421 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5422
5423 /* fill hw info */
605a0bd6 5424 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5425 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5426
f59ac048
LR		 5427 hw->wiphy->interface_modes =
5428 BIT(NL80211_IFTYPE_AP) |
5429 BIT(NL80211_IFTYPE_MESH_POINT) |
5430 BIT(NL80211_IFTYPE_STATION) |
5431 BIT(NL80211_IFTYPE_WDS) |
5432 BIT(NL80211_IFTYPE_ADHOC);
5433
78f9c850
AQ		 5434 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5435
e64add27 5436 wl->hw_registred = false;
e6a9854b 5437 hw->max_rates = 2;
e4d6b795 5438 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5439 if (is_valid_ether_addr(sprom->et1mac))
5440 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5441 else
95de2841 5442 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5443
403a3a13 5444 /* Initialize struct b43_wl */
e4d6b795 5445 wl->hw = hw;
e4d6b795 5446 mutex_init(&wl->mutex);
36dbd954 5447 spin_lock_init(&wl->hardirq_lock);
a82d9922 5448 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5449 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5450 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5451
5452 /* Initialize queues and flags. */
5453 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5454 skb_queue_head_init(&wl->tx_queue[queue_num]);
5455 wl->tx_queue_stopped[queue_num] = 0;
5456 }
e4d6b795 5457
2729df25
RM		 5458 snprintf(chip_name, ARRAY_SIZE(chip_name),
5459 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5460 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5461 dev->core_rev);
0355a345 5462 return wl;
e4d6b795
MB		 5463}
5464
3c65ab62
RM		 5465#ifdef CONFIG_B43_BCMA
5466static int b43_bcma_probe(struct bcma_device *core)
5467{
397915c3 5468 struct b43_bus_dev *dev;
24aad3f4
RM		 5469 struct b43_wl *wl;
5470 int err;
397915c3 5471
8960400e
RM		 5472 if (!modparam_allhwsupport &&
5473 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5474 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5475 return -ENOTSUPP;
5476 }
5477
397915c3
RM		 5478 dev = b43_bus_dev_bcma_init(core);
5479 if (!dev)
5480 return -ENODEV;
5481
24aad3f4
RM		 5482 wl = b43_wireless_init(dev);
5483 if (IS_ERR(wl)) {
5484 err = PTR_ERR(wl);
5485 goto bcma_out;
5486 }
5487
5488 err = b43_one_core_attach(dev, wl);
5489 if (err)
5490 goto bcma_err_wireless_exit;
5491
6b6fa586
LF		 5492 /* setup and start work to load firmware */
5493 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5494 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5495
5496bcma_out:
5497 return err;
5498
24aad3f4
RM		 5499bcma_err_wireless_exit:
5500 ieee80211_free_hw(wl->hw);
5501 return err;
3c65ab62
RM		 5502}
5503
5504static void b43_bcma_remove(struct bcma_device *core)
5505{
24aad3f4
RM		 5506 struct b43_wldev *wldev = bcma_get_drvdata(core);
5507 struct b43_wl *wl = wldev->wl;
5508
5509 /* We must cancel any work here before unregistering from ieee80211,
5510 * as the ieee80211 unreg will destroy the workqueue. */
5511 cancel_work_sync(&wldev->restart_work);
63a02ce1 5512 cancel_work_sync(&wl->firmware_load);
24aad3f4 5513
e64add27 5514 B43_WARN_ON(!wl);
f89ff644
LF		 5515 if (!wldev->fw.ucode.data)
5516 return; /* NULL if firmware never loaded */
e64add27 5517 if (wl->current_dev == wldev && wl->hw_registred) {
e64add27
OR		 5518 b43_leds_stop(wldev);
5519 ieee80211_unregister_hw(wl->hw);
5520 }
24aad3f4
RM		 5521
5522 b43_one_core_detach(wldev->dev);
5523
09164043
LF		 5524 /* Unregister HW RNG driver */
5525 b43_rng_exit(wl);
5526
24aad3f4
RM		 5527 b43_leds_unregister(wl);
5528
5529 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5530}
5531
5532static struct bcma_driver b43_bcma_driver = {
5533 .name = KBUILD_MODNAME,
5534 .id_table = b43_bcma_tbl,
5535 .probe = b43_bcma_probe,
5536 .remove = b43_bcma_remove,
5537};
5538#endif
5539
aec7ffdf 5540#ifdef CONFIG_B43_SSB
aa63418a
RM		 5541static
5542int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5543{
482f0538 5544 struct b43_bus_dev *dev;
e4d6b795
MB		 5545 struct b43_wl *wl;
5546 int err;
e4d6b795 5547
482f0538 5548 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5549 if (!dev)
5550 return -ENOMEM;
482f0538 5551
aa63418a 5552 wl = ssb_get_devtypedata(sdev);
8f15e287
RM		 5553 if (wl) {
5554 b43err(NULL, "Dual-core devices are not supported\n");
5555 err = -ENOTSUPP;
5556 goto err_ssb_kfree_dev;
e4d6b795 5557 }
8f15e287
RM		 5558
5559 b43_sprom_fixup(sdev->bus);
5560
5561 wl = b43_wireless_init(dev);
5562 if (IS_ERR(wl)) {
5563 err = PTR_ERR(wl);
5564 goto err_ssb_kfree_dev;
5565 }
5566 ssb_set_devtypedata(sdev, wl);
5567 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5568
e4d6b795
MB		 5569 err = b43_one_core_attach(dev, wl);
5570 if (err)
8f15e287 5571 goto err_ssb_wireless_exit;
e4d6b795 5572
6b6fa586
LF		 5573 /* setup and start work to load firmware */
5574 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5575 schedule_work(&wl->firmware_load);
e4d6b795 5576
e4d6b795
MB		 5577 return err;
5578
8f15e287
RM		 5579err_ssb_wireless_exit:
5580 b43_wireless_exit(dev, wl);
5581err_ssb_kfree_dev:
5582 kfree(dev);
e4d6b795
MB		 5583 return err;
5584}
5585
aa63418a 5586static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5587{
aa63418a
RM		 5588 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5589 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5590 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5591
3bf0a32e
MB		 5592 /* We must cancel any work here before unregistering from ieee80211,
5593 * as the ieee80211 unreg will destroy the workqueue. */
5594 cancel_work_sync(&wldev->restart_work);
63a02ce1 5595 cancel_work_sync(&wl->firmware_load);
3bf0a32e 5596
e4d6b795 5597 B43_WARN_ON(!wl);
f89ff644
LF		 5598 if (!wldev->fw.ucode.data)
5599 return; /* NULL if firmware never loaded */
e64add27 5600 if (wl->current_dev == wldev && wl->hw_registred) {
82905ace 5601 b43_leds_stop(wldev);
e4d6b795 5602 ieee80211_unregister_hw(wl->hw);
403a3a13 5603 }
e4d6b795 5604
e61b52d1 5605 b43_one_core_detach(dev);
e4d6b795 5606
09164043
LF		 5607 /* Unregister HW RNG driver */
5608 b43_rng_exit(wl);
5609
644aa4d6
RM		 5610 b43_leds_unregister(wl);
5611 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5612}
5613
aec7ffdf
RM		 5614static struct ssb_driver b43_ssb_driver = {
5615 .name = KBUILD_MODNAME,
5616 .id_table = b43_ssb_tbl,
5617 .probe = b43_ssb_probe,
5618 .remove = b43_ssb_remove,
5619};
5620#endif /* CONFIG_B43_SSB */
5621
e4d6b795
MB		 5622/* Perform a hardware reset. This can be called from any context. */
5623void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5624{
5625 /* Must avoid requeueing, if we are in shutdown. */
5626 if (b43_status(dev) < B43_STAT_INITIALIZED)
5627 return;
5628 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5629 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5630}
5631
26bc783f
MB		 5632static void b43_print_driverinfo(void)
5633{
5634 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5635 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5636
5637#ifdef CONFIG_B43_PCI_AUTOSELECT
5638 feat_pci = "P";
5639#endif
5640#ifdef CONFIG_B43_PCMCIA
5641 feat_pcmcia = "M";
5642#endif
692d2c0f 5643#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5644 feat_nphy = "N";
5645#endif
5646#ifdef CONFIG_B43_LEDS
5647 feat_leds = "L";
3dbba8e2
AH		 5648#endif
5649#ifdef CONFIG_B43_SDIO
5650 feat_sdio = "S";
26bc783f
MB		 5651#endif
5652 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5653 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5654 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5655 feat_leds, feat_sdio);
26bc783f
MB		 5656}
5657
e4d6b795
MB		 5658static int __init b43_init(void)
5659{
5660 int err;
5661
5662 b43_debugfs_init();
5663 err = b43_pcmcia_init();
5664 if (err)
5665 goto err_dfs_exit;
3dbba8e2 5666 err = b43_sdio_init();
e4d6b795
MB		 5667 if (err)
5668 goto err_pcmcia_exit;
3c65ab62
RM		 5669#ifdef CONFIG_B43_BCMA
5670 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5671 if (err)
5672 goto err_sdio_exit;
3c65ab62 5673#endif
aec7ffdf 5674#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5675 err = ssb_driver_register(&b43_ssb_driver);
5676 if (err)
5677 goto err_bcma_driver_exit;
aec7ffdf 5678#endif
26bc783f 5679 b43_print_driverinfo();
e4d6b795
MB		 5680
5681 return err;
5682
aec7ffdf 5683#ifdef CONFIG_B43_SSB
3c65ab62 5684err_bcma_driver_exit:
aec7ffdf 5685#endif
3c65ab62
RM		 5686#ifdef CONFIG_B43_BCMA
5687 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5688err_sdio_exit:
3c65ab62 5689#endif
3dbba8e2 5690 b43_sdio_exit();
e4d6b795
MB		 5691err_pcmcia_exit:
5692 b43_pcmcia_exit();
5693err_dfs_exit:
5694 b43_debugfs_exit();
5695 return err;
5696}
5697
5698static void __exit b43_exit(void)
5699{
aec7ffdf 5700#ifdef CONFIG_B43_SSB
e4d6b795 5701 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5702#endif
3c65ab62
RM		 5703#ifdef CONFIG_B43_BCMA
5704 bcma_driver_unregister(&b43_bcma_driver);
5705#endif
3dbba8e2 5706 b43_sdio_exit();
e4d6b795
MB		 5707 b43_pcmcia_exit();
5708 b43_debugfs_exit();
5709}
5710
5711module_init(b43_init)
5712module_exit(b43_exit)
Linux kernel - Deliverables
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