projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: add ieee80211_vif param to tsf functions
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/moduleparam.h>
38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
3c65ab62
RM		 116#ifdef CONFIG_B43_BCMA
117static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
122 BCMA_CORETABLE_END
123};
124MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
125#endif
126
aec7ffdf 127#ifdef CONFIG_B43_SSB
e4d6b795
MB		 128static const struct ssb_device_id b43_ssb_tbl[] = {
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 139 SSB_DEVTABLE_END
140};
e4d6b795 141MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 142#endif
e4d6b795
MB		 143
144/* Channel and ratetables are shared for all devices.
145 * They can't be const, because ieee80211 puts some precalculated
146 * data in there. This data is the same for all devices, so we don't
147 * get concurrency issues */
148#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 149 { \
150 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
151 .hw_value = (_rateid), \
152 .flags = (_flags), \
e4d6b795 153 }
8318d78a
JB		 154
155/*
156 * NOTE: When changing this, sync with xmit.c's
157 * b43_plcp_get_bitrate_idx_* functions!
158 */
e4d6b795 159static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 160 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
161 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 172};
173
174#define b43_a_ratetable (__b43_ratetable + 4)
175#define b43_a_ratetable_size 8
176#define b43_b_ratetable (__b43_ratetable + 0)
177#define b43_b_ratetable_size 4
178#define b43_g_ratetable (__b43_ratetable + 0)
179#define b43_g_ratetable_size 12
180
bb1eeff1
MB		 181#define CHAN4G(_channel, _freq, _flags) { \
182 .band = IEEE80211_BAND_2GHZ, \
183 .center_freq = (_freq), \
184 .hw_value = (_channel), \
185 .flags = (_flags), \
186 .max_antenna_gain = 0, \
187 .max_power = 30, \
188}
96c755a3 189static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 190 CHAN4G(1, 2412, 0),
191 CHAN4G(2, 2417, 0),
192 CHAN4G(3, 2422, 0),
193 CHAN4G(4, 2427, 0),
194 CHAN4G(5, 2432, 0),
195 CHAN4G(6, 2437, 0),
196 CHAN4G(7, 2442, 0),
197 CHAN4G(8, 2447, 0),
198 CHAN4G(9, 2452, 0),
199 CHAN4G(10, 2457, 0),
200 CHAN4G(11, 2462, 0),
201 CHAN4G(12, 2467, 0),
202 CHAN4G(13, 2472, 0),
203 CHAN4G(14, 2484, 0),
204};
205#undef CHAN4G
206
207#define CHAN5G(_channel, _flags) { \
208 .band = IEEE80211_BAND_5GHZ, \
209 .center_freq = 5000 + (5 * (_channel)), \
210 .hw_value = (_channel), \
211 .flags = (_flags), \
212 .max_antenna_gain = 0, \
213 .max_power = 30, \
214}
215static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
216 CHAN5G(32, 0), CHAN5G(34, 0),
217 CHAN5G(36, 0), CHAN5G(38, 0),
218 CHAN5G(40, 0), CHAN5G(42, 0),
219 CHAN5G(44, 0), CHAN5G(46, 0),
220 CHAN5G(48, 0), CHAN5G(50, 0),
221 CHAN5G(52, 0), CHAN5G(54, 0),
222 CHAN5G(56, 0), CHAN5G(58, 0),
223 CHAN5G(60, 0), CHAN5G(62, 0),
224 CHAN5G(64, 0), CHAN5G(66, 0),
225 CHAN5G(68, 0), CHAN5G(70, 0),
226 CHAN5G(72, 0), CHAN5G(74, 0),
227 CHAN5G(76, 0), CHAN5G(78, 0),
228 CHAN5G(80, 0), CHAN5G(82, 0),
229 CHAN5G(84, 0), CHAN5G(86, 0),
230 CHAN5G(88, 0), CHAN5G(90, 0),
231 CHAN5G(92, 0), CHAN5G(94, 0),
232 CHAN5G(96, 0), CHAN5G(98, 0),
233 CHAN5G(100, 0), CHAN5G(102, 0),
234 CHAN5G(104, 0), CHAN5G(106, 0),
235 CHAN5G(108, 0), CHAN5G(110, 0),
236 CHAN5G(112, 0), CHAN5G(114, 0),
237 CHAN5G(116, 0), CHAN5G(118, 0),
238 CHAN5G(120, 0), CHAN5G(122, 0),
239 CHAN5G(124, 0), CHAN5G(126, 0),
240 CHAN5G(128, 0), CHAN5G(130, 0),
241 CHAN5G(132, 0), CHAN5G(134, 0),
242 CHAN5G(136, 0), CHAN5G(138, 0),
243 CHAN5G(140, 0), CHAN5G(142, 0),
244 CHAN5G(144, 0), CHAN5G(145, 0),
245 CHAN5G(146, 0), CHAN5G(147, 0),
246 CHAN5G(148, 0), CHAN5G(149, 0),
247 CHAN5G(150, 0), CHAN5G(151, 0),
248 CHAN5G(152, 0), CHAN5G(153, 0),
249 CHAN5G(154, 0), CHAN5G(155, 0),
250 CHAN5G(156, 0), CHAN5G(157, 0),
251 CHAN5G(158, 0), CHAN5G(159, 0),
252 CHAN5G(160, 0), CHAN5G(161, 0),
253 CHAN5G(162, 0), CHAN5G(163, 0),
254 CHAN5G(164, 0), CHAN5G(165, 0),
255 CHAN5G(166, 0), CHAN5G(168, 0),
256 CHAN5G(170, 0), CHAN5G(172, 0),
257 CHAN5G(174, 0), CHAN5G(176, 0),
258 CHAN5G(178, 0), CHAN5G(180, 0),
259 CHAN5G(182, 0), CHAN5G(184, 0),
260 CHAN5G(186, 0), CHAN5G(188, 0),
261 CHAN5G(190, 0), CHAN5G(192, 0),
262 CHAN5G(194, 0), CHAN5G(196, 0),
263 CHAN5G(198, 0), CHAN5G(200, 0),
264 CHAN5G(202, 0), CHAN5G(204, 0),
265 CHAN5G(206, 0), CHAN5G(208, 0),
266 CHAN5G(210, 0), CHAN5G(212, 0),
267 CHAN5G(214, 0), CHAN5G(216, 0),
268 CHAN5G(218, 0), CHAN5G(220, 0),
269 CHAN5G(222, 0), CHAN5G(224, 0),
270 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 271};
272
bb1eeff1
MB		 273static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
274 CHAN5G(34, 0), CHAN5G(36, 0),
275 CHAN5G(38, 0), CHAN5G(40, 0),
276 CHAN5G(42, 0), CHAN5G(44, 0),
277 CHAN5G(46, 0), CHAN5G(48, 0),
278 CHAN5G(52, 0), CHAN5G(56, 0),
279 CHAN5G(60, 0), CHAN5G(64, 0),
280 CHAN5G(100, 0), CHAN5G(104, 0),
281 CHAN5G(108, 0), CHAN5G(112, 0),
282 CHAN5G(116, 0), CHAN5G(120, 0),
283 CHAN5G(124, 0), CHAN5G(128, 0),
284 CHAN5G(132, 0), CHAN5G(136, 0),
285 CHAN5G(140, 0), CHAN5G(149, 0),
286 CHAN5G(153, 0), CHAN5G(157, 0),
287 CHAN5G(161, 0), CHAN5G(165, 0),
288 CHAN5G(184, 0), CHAN5G(188, 0),
289 CHAN5G(192, 0), CHAN5G(196, 0),
290 CHAN5G(200, 0), CHAN5G(204, 0),
291 CHAN5G(208, 0), CHAN5G(212, 0),
292 CHAN5G(216, 0),
293};
294#undef CHAN5G
295
296static struct ieee80211_supported_band b43_band_5GHz_nphy = {
297 .band = IEEE80211_BAND_5GHZ,
298 .channels = b43_5ghz_nphy_chantable,
299 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
300 .bitrates = b43_a_ratetable,
301 .n_bitrates = b43_a_ratetable_size,
e4d6b795 302};
8318d78a 303
bb1eeff1
MB		 304static struct ieee80211_supported_band b43_band_5GHz_aphy = {
305 .band = IEEE80211_BAND_5GHZ,
306 .channels = b43_5ghz_aphy_chantable,
307 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
308 .bitrates = b43_a_ratetable,
309 .n_bitrates = b43_a_ratetable_size,
8318d78a 310};
e4d6b795 311
8318d78a 312static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 313 .band = IEEE80211_BAND_2GHZ,
314 .channels = b43_2ghz_chantable,
315 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
316 .bitrates = b43_g_ratetable,
317 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 318};
319
e4d6b795
MB		 320static void b43_wireless_core_exit(struct b43_wldev *dev);
321static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 322static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 323static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 324static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
325 struct ieee80211_vif *vif,
326 struct ieee80211_bss_conf *conf,
327 u32 changed);
e4d6b795
MB		 328
329static int b43_ratelimit(struct b43_wl *wl)
330{
331 if (!wl || !wl->current_dev)
332 return 1;
333 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
334 return 1;
335 /* We are up and running.
336 * Ratelimit the messages to avoid DoS over the net. */
337 return net_ratelimit();
338}
339
340void b43info(struct b43_wl *wl, const char *fmt, ...)
341{
5b736d42 342 struct va_format vaf;
e4d6b795
MB		 343 va_list args;
344
060210f9
MB		 345 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
346 return;
e4d6b795
MB		 347 if (!b43_ratelimit(wl))
348 return;
5b736d42 349
e4d6b795 350 va_start(args, fmt);
5b736d42
JP		 351
352 vaf.fmt = fmt;
353 vaf.va = &args;
354
355 printk(KERN_INFO "b43-%s: %pV",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
357
e4d6b795
MB		 358 va_end(args);
359}
360
361void b43err(struct b43_wl *wl, const char *fmt, ...)
362{
5b736d42 363 struct va_format vaf;
e4d6b795
MB		 364 va_list args;
365
060210f9
MB		 366 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
367 return;
e4d6b795
MB		 368 if (!b43_ratelimit(wl))
369 return;
5b736d42 370
e4d6b795 371 va_start(args, fmt);
5b736d42
JP		 372
373 vaf.fmt = fmt;
374 vaf.va = &args;
375
376 printk(KERN_ERR "b43-%s ERROR: %pV",
377 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
378
e4d6b795
MB		 379 va_end(args);
380}
381
382void b43warn(struct b43_wl *wl, const char *fmt, ...)
383{
5b736d42 384 struct va_format vaf;
e4d6b795
MB		 385 va_list args;
386
060210f9
MB		 387 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
388 return;
e4d6b795
MB		 389 if (!b43_ratelimit(wl))
390 return;
5b736d42 391
e4d6b795 392 va_start(args, fmt);
5b736d42
JP		 393
394 vaf.fmt = fmt;
395 vaf.va = &args;
396
397 printk(KERN_WARNING "b43-%s warning: %pV",
398 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
399
e4d6b795
MB		 400 va_end(args);
401}
402
e4d6b795
MB		 403void b43dbg(struct b43_wl *wl, const char *fmt, ...)
404{
5b736d42 405 struct va_format vaf;
e4d6b795
MB		 406 va_list args;
407
060210f9
MB		 408 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
409 return;
5b736d42 410
e4d6b795 411 va_start(args, fmt);
5b736d42
JP		 412
413 vaf.fmt = fmt;
414 vaf.va = &args;
415
416 printk(KERN_DEBUG "b43-%s debug: %pV",
417 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
418
e4d6b795
MB		 419 va_end(args);
420}
e4d6b795
MB		 421
422static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
423{
424 u32 macctl;
425
426 B43_WARN_ON(offset % 4 != 0);
427
428 macctl = b43_read32(dev, B43_MMIO_MACCTL);
429 if (macctl & B43_MACCTL_BE)
430 val = swab32(val);
431
432 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
433 mmiowb();
434 b43_write32(dev, B43_MMIO_RAM_DATA, val);
435}
436
280d0e16
MB		 437static inline void b43_shm_control_word(struct b43_wldev *dev,
438 u16 routing, u16 offset)
e4d6b795
MB		 439{
440 u32 control;
441
442 /* "offset" is the WORD offset. */
e4d6b795
MB		 443 control = routing;
444 control <<= 16;
445 control |= offset;
446 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
447}
448
69eddc8a 449u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 450{
451 u32 ret;
452
453 if (routing == B43_SHM_SHARED) {
454 B43_WARN_ON(offset & 0x0001);
455 if (offset & 0x0003) {
456 /* Unaligned access */
457 b43_shm_control_word(dev, routing, offset >> 2);
458 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 459 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 460 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 461
280d0e16 462 goto out;
e4d6b795
MB		 463 }
464 offset >>= 2;
465 }
466 b43_shm_control_word(dev, routing, offset);
467 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 468out:
e4d6b795
MB		 469 return ret;
470}
471
69eddc8a 472u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 473{
474 u16 ret;
475
e4d6b795
MB		 476 if (routing == B43_SHM_SHARED) {
477 B43_WARN_ON(offset & 0x0001);
478 if (offset & 0x0003) {
479 /* Unaligned access */
480 b43_shm_control_word(dev, routing, offset >> 2);
481 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
482
280d0e16 483 goto out;
e4d6b795
MB		 484 }
485 offset >>= 2;
486 }
487 b43_shm_control_word(dev, routing, offset);
488 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 489out:
e4d6b795
MB		 490 return ret;
491}
492
69eddc8a 493void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 494{
e4d6b795
MB		 495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 501 value & 0xFFFF);
e4d6b795 502 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 503 b43_write16(dev, B43_MMIO_SHM_DATA,
504 (value >> 16) & 0xFFFF);
6bbc321a 505 return;
e4d6b795
MB		 506 }
507 offset >>= 2;
508 }
509 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 510 b43_write32(dev, B43_MMIO_SHM_DATA, value);
511}
512
69eddc8a 513void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 514{
e4d6b795
MB		 515 if (routing == B43_SHM_SHARED) {
516 B43_WARN_ON(offset & 0x0001);
517 if (offset & 0x0003) {
518 /* Unaligned access */
519 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 520 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 521 return;
e4d6b795
MB		 522 }
523 offset >>= 2;
524 }
525 b43_shm_control_word(dev, routing, offset);
e4d6b795 526 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 527}
528
e4d6b795 529/* Read HostFlags */
99da185a 530u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 531{
35f0d354 532 u64 ret;
e4d6b795
MB		 533
534 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
535 ret <<= 16;
35f0d354
MB		 536 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
537 ret <<= 16;
e4d6b795
MB		 538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
539
540 return ret;
541}
542
543/* Write HostFlags */
35f0d354 544void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 545{
35f0d354
MB		 546 u16 lo, mi, hi;
547
548 lo = (value & 0x00000000FFFFULL);
549 mi = (value & 0x0000FFFF0000ULL) >> 16;
550 hi = (value & 0xFFFF00000000ULL) >> 32;
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 554}
555
403a3a13
MB		 556/* Read the firmware capabilities bitmask (Opensource firmware only) */
557static u16 b43_fwcapa_read(struct b43_wldev *dev)
558{
559 B43_WARN_ON(!dev->fw.opensource);
560 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
561}
562
3ebbbb56 563void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 564{
3ebbbb56
MB		 565 u32 low, high;
566
21d889d4 567 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 568
569 /* The hardware guarantees us an atomic read, if we
570 * read the low register first. */
571 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
572 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
573
574 *tsf = high;
575 *tsf <<= 32;
576 *tsf |= low;
e4d6b795
MB		 577}
578
579static void b43_time_lock(struct b43_wldev *dev)
580{
581 u32 macctl;
582
583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
584 macctl |= B43_MACCTL_TBTTHOLD;
585 b43_write32(dev, B43_MMIO_MACCTL, macctl);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
588}
589
590static void b43_time_unlock(struct b43_wldev *dev)
591{
592 u32 macctl;
593
594 macctl = b43_read32(dev, B43_MMIO_MACCTL);
595 macctl &= ~B43_MACCTL_TBTTHOLD;
596 b43_write32(dev, B43_MMIO_MACCTL, macctl);
597 /* Commit the write */
598 b43_read32(dev, B43_MMIO_MACCTL);
599}
600
601static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
602{
3ebbbb56
MB		 603 u32 low, high;
604
21d889d4 605 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 606
607 low = tsf;
608 high = (tsf >> 32);
609 /* The hardware guarantees us an atomic write, if we
610 * write the low register first. */
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
614 mmiowb();
e4d6b795
MB		 615}
616
617void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
618{
619 b43_time_lock(dev);
620 b43_tsf_write_locked(dev, tsf);
621 b43_time_unlock(dev);
622}
623
624static
99da185a 625void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 626{
627 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 u16 data;
629
630 if (!mac)
631 mac = zero_addr;
632
633 offset |= 0x0020;
634 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
635
636 data = mac[0];
637 data |= mac[1] << 8;
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 data = mac[2];
640 data |= mac[3] << 8;
641 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
642 data = mac[4];
643 data |= mac[5] << 8;
644 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
645}
646
647static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
648{
649 const u8 *mac;
650 const u8 *bssid;
651 u8 mac_bssid[ETH_ALEN * 2];
652 int i;
653 u32 tmp;
654
655 bssid = dev->wl->bssid;
656 mac = dev->wl->mac_addr;
657
658 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
659
660 memcpy(mac_bssid, mac, ETH_ALEN);
661 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
662
663 /* Write our MAC address and BSSID to template ram */
664 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
665 tmp = (u32) (mac_bssid[i + 0]);
666 tmp |= (u32) (mac_bssid[i + 1]) << 8;
667 tmp |= (u32) (mac_bssid[i + 2]) << 16;
668 tmp |= (u32) (mac_bssid[i + 3]) << 24;
669 b43_ram_write(dev, 0x20 + i, tmp);
670 }
671}
672
4150c572 673static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 674{
e4d6b795 675 b43_write_mac_bssid_templates(dev);
4150c572 676 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 677}
678
679static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
680{
681 /* slot_time is in usec. */
b6c3f5be
LF		 682 /* This test used to exit for all but a G PHY. */
683 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 684 return;
b6c3f5be
LF		 685 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
686 /* Shared memory location 0x0010 is the slot time and should be
687 * set to slot_time; however, this register is initially 0 and changing
688 * the value adversely affects the transmit rate for BCM4311
689 * devices. Until this behavior is unterstood, delete this step
690 *
691 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
692 */
e4d6b795
MB		 693}
694
695static void b43_short_slot_timing_enable(struct b43_wldev *dev)
696{
697 b43_set_slot_time(dev, 9);
e4d6b795
MB		 698}
699
700static void b43_short_slot_timing_disable(struct b43_wldev *dev)
701{
702 b43_set_slot_time(dev, 20);
e4d6b795
MB		 703}
704
e4d6b795 705/* DummyTransmission function, as documented on
2f19c287 706 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 707 */
2f19c287 708void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 709{
710 struct b43_phy *phy = &dev->phy;
711 unsigned int i, max_loop;
712 u16 value;
713 u32 buffer[5] = {
714 0x00000000,
715 0x00D40000,
716 0x00000000,
717 0x01000000,
718 0x00000000,
719 };
720
2f19c287 721 if (ofdm) {
e4d6b795
MB		 722 max_loop = 0x1E;
723 buffer[0] = 0x000201CC;
2f19c287 724 } else {
e4d6b795
MB		 725 max_loop = 0xFA;
726 buffer[0] = 0x000B846E;
e4d6b795
MB		 727 }
728
729 for (i = 0; i < 5; i++)
730 b43_ram_write(dev, i * 4, buffer[i]);
731
e4d6b795 732 b43_write16(dev, 0x0568, 0x0000);
21d889d4 733 if (dev->dev->core_rev < 11)
2f19c287
GS		 734 b43_write16(dev, 0x07C0, 0x0000);
735 else
736 b43_write16(dev, 0x07C0, 0x0100);
737 value = (ofdm ? 0x41 : 0x40);
e4d6b795 738 b43_write16(dev, 0x050C, value);
2f19c287
GS		 739 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
740 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 741 b43_write16(dev, 0x0508, 0x0000);
742 b43_write16(dev, 0x050A, 0x0000);
743 b43_write16(dev, 0x054C, 0x0000);
744 b43_write16(dev, 0x056A, 0x0014);
745 b43_write16(dev, 0x0568, 0x0826);
746 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 747 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
748 //SPEC TODO
749 }
750
751 switch (phy->type) {
752 case B43_PHYTYPE_N:
753 b43_write16(dev, 0x0502, 0x00D0);
754 break;
755 case B43_PHYTYPE_LP:
756 b43_write16(dev, 0x0502, 0x0050);
757 break;
758 default:
759 b43_write16(dev, 0x0502, 0x0030);
760 }
e4d6b795
MB		 761
762 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
763 b43_radio_write16(dev, 0x0051, 0x0017);
764 for (i = 0x00; i < max_loop; i++) {
765 value = b43_read16(dev, 0x050E);
766 if (value & 0x0080)
767 break;
768 udelay(10);
769 }
770 for (i = 0x00; i < 0x0A; i++) {
771 value = b43_read16(dev, 0x050E);
772 if (value & 0x0400)
773 break;
774 udelay(10);
775 }
1d280ddc 776 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 777 value = b43_read16(dev, 0x0690);
778 if (!(value & 0x0100))
779 break;
780 udelay(10);
781 }
782 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
783 b43_radio_write16(dev, 0x0051, 0x0037);
784}
785
786static void key_write(struct b43_wldev *dev,
99da185a 787 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 788{
789 unsigned int i;
790 u32 offset;
791 u16 value;
792 u16 kidx;
793
794 /* Key index/algo block */
795 kidx = b43_kidx_to_fw(dev, index);
796 value = ((kidx << 4) | algorithm);
797 b43_shm_write16(dev, B43_SHM_SHARED,
798 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
799
800 /* Write the key to the Key Table Pointer offset */
801 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
802 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
803 value = key[i];
804 value |= (u16) (key[i + 1]) << 8;
805 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
806 }
807}
808
99da185a 809static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 810{
811 u32 addrtmp[2] = { 0, 0, };
66d2d089 812 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 813
814 if (b43_new_kidx_api(dev))
66d2d089 815 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 816
66d2d089
MB		 817 B43_WARN_ON(index < pairwise_keys_start);
818 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 819 * Physical mac 0 is mapped to physical key 4 or 8, depending
820 * on the firmware version.
821 * So we must adjust the index here.
822 */
66d2d089
MB		 823 index -= pairwise_keys_start;
824 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 825
826 if (addr) {
827 addrtmp[0] = addr[0];
828 addrtmp[0] |= ((u32) (addr[1]) << 8);
829 addrtmp[0] |= ((u32) (addr[2]) << 16);
830 addrtmp[0] |= ((u32) (addr[3]) << 24);
831 addrtmp[1] = addr[4];
832 addrtmp[1] |= ((u32) (addr[5]) << 8);
833 }
834
66d2d089
MB		 835 /* Receive match transmitter address (RCMTA) mechanism */
836 b43_shm_write32(dev, B43_SHM_RCMTA,
837 (index * 2) + 0, addrtmp[0]);
838 b43_shm_write16(dev, B43_SHM_RCMTA,
839 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 840}
841
035d0243 842/* The ucode will use phase1 key with TEK key to decrypt rx packets.
843 * When a packet is received, the iv32 is checked.
844 * - if it doesn't the packet is returned without modification (and software
845 * decryption can be done). That's what happen when iv16 wrap.
846 * - if it does, the rc4 key is computed, and decryption is tried.
847 * Either it will success and B43_RX_MAC_DEC is returned,
848 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
849 * and the packet is not usable (it got modified by the ucode).
850 * So in order to never have B43_RX_MAC_DECERR, we should provide
851 * a iv32 and phase1key that match. Because we drop packets in case of
852 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
853 * packets will be lost without higher layer knowing (ie no resync possible
854 * until next wrap).
855 *
856 * NOTE : this should support 50 key like RCMTA because
857 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
858 */
859static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
860 u16 *phase1key)
861{
862 unsigned int i;
863 u32 offset;
864 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
865
866 if (!modparam_hwtkip)
867 return;
868
869 if (b43_new_kidx_api(dev))
870 pairwise_keys_start = B43_NR_GROUP_KEYS;
871
872 B43_WARN_ON(index < pairwise_keys_start);
873 /* We have four default TX keys and possibly four default RX keys.
874 * Physical mac 0 is mapped to physical key 4 or 8, depending
875 * on the firmware version.
876 * So we must adjust the index here.
877 */
878 index -= pairwise_keys_start;
879 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
880
881 if (b43_debug(dev, B43_DBG_KEYS)) {
882 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
883 index, iv32);
884 }
885 /* Write the key to the RX tkip shared mem */
886 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
887 for (i = 0; i < 10; i += 2) {
888 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
889 phase1key ? phase1key[i / 2] : 0);
890 }
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
893}
894
895static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 896 struct ieee80211_vif *vif,
897 struct ieee80211_key_conf *keyconf,
898 struct ieee80211_sta *sta,
899 u32 iv32, u16 *phase1key)
035d0243 900{
901 struct b43_wl *wl = hw_to_b43_wl(hw);
902 struct b43_wldev *dev;
903 int index = keyconf->hw_key_idx;
904
905 if (B43_WARN_ON(!modparam_hwtkip))
906 return;
907
96869a39
MB		 908 /* This is only called from the RX path through mac80211, where
909 * our mutex is already locked. */
910 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 911 dev = wl->current_dev;
96869a39 912 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 913
914 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
915
916 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 917 /* only pairwise TKIP keys are supported right now */
918 if (WARN_ON(!sta))
96869a39 919 return;
b3fbdcf4 920 keymac_write(dev, index, sta->addr);
035d0243 921}
922
e4d6b795
MB		 923static void do_key_write(struct b43_wldev *dev,
924 u8 index, u8 algorithm,
99da185a 925 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 926{
927 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 928 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 929
930 if (b43_new_kidx_api(dev))
66d2d089 931 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 932
66d2d089 933 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 934 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
935
66d2d089 936 if (index >= pairwise_keys_start)
e4d6b795 937 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 938 if (algorithm == B43_SEC_ALGO_TKIP) {
939 /*
940 * We should provide an initial iv32, phase1key pair.
941 * We could start with iv32=0 and compute the corresponding
942 * phase1key, but this means calling ieee80211_get_tkip_key
943 * with a fake skb (or export other tkip function).
944 * Because we are lazy we hope iv32 won't start with
945 * 0xffffffff and let's b43_op_update_tkip_key provide a
946 * correct pair.
947 */
948 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
949 } else if (index >= pairwise_keys_start) /* clear it */
950 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 951 if (key)
952 memcpy(buf, key, key_len);
953 key_write(dev, index, algorithm, buf);
66d2d089 954 if (index >= pairwise_keys_start)
e4d6b795
MB		 955 keymac_write(dev, index, mac_addr);
956
957 dev->key[index].algorithm = algorithm;
958}
959
960static int b43_key_write(struct b43_wldev *dev,
961 int index, u8 algorithm,
99da185a
JD		 962 const u8 *key, size_t key_len,
963 const u8 *mac_addr,
e4d6b795
MB		 964 struct ieee80211_key_conf *keyconf)
965{
966 int i;
66d2d089 967 int pairwise_keys_start;
e4d6b795 968
035d0243 969 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
970 * - Temporal Encryption Key (128 bits)
971 * - Temporal Authenticator Tx MIC Key (64 bits)
972 * - Temporal Authenticator Rx MIC Key (64 bits)
973 *
974 * Hardware only store TEK
975 */
976 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
977 key_len = 16;
e4d6b795
MB		 978 if (key_len > B43_SEC_KEYSIZE)
979 return -EINVAL;
66d2d089 980 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 981 /* Check that we don't already have this key. */
982 B43_WARN_ON(dev->key[i].keyconf == keyconf);
983 }
984 if (index < 0) {
e808e586 985 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 986 if (b43_new_kidx_api(dev))
66d2d089 987 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 988 else
66d2d089
MB		 989 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
990 for (i = pairwise_keys_start;
991 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
992 i++) {
993 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 994 if (!dev->key[i].keyconf) {
995 /* found empty */
996 index = i;
997 break;
998 }
999 }
1000 if (index < 0) {
e808e586 1001 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1002 return -ENOSPC;
1003 }
1004 } else
1005 B43_WARN_ON(index > 3);
1006
1007 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1008 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009 /* Default RX key */
1010 B43_WARN_ON(mac_addr);
1011 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1012 }
1013 keyconf->hw_key_idx = index;
1014 dev->key[index].keyconf = keyconf;
1015
1016 return 0;
1017}
1018
1019static int b43_key_clear(struct b43_wldev *dev, int index)
1020{
66d2d089 1021 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1022 return -EINVAL;
1023 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1024 NULL, B43_SEC_KEYSIZE, NULL);
1025 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1026 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1027 NULL, B43_SEC_KEYSIZE, NULL);
1028 }
1029 dev->key[index].keyconf = NULL;
1030
1031 return 0;
1032}
1033
1034static void b43_clear_keys(struct b43_wldev *dev)
1035{
66d2d089 1036 int i, count;
e4d6b795 1037
66d2d089
MB		 1038 if (b43_new_kidx_api(dev))
1039 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1040 else
1041 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1042 for (i = 0; i < count; i++)
e4d6b795
MB		 1043 b43_key_clear(dev, i);
1044}
1045
9cf7f247
MB		 1046static void b43_dump_keymemory(struct b43_wldev *dev)
1047{
66d2d089 1048 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1049 u8 mac[ETH_ALEN];
1050 u16 algo;
1051 u32 rcmta0;
1052 u16 rcmta1;
1053 u64 hf;
1054 struct b43_key *key;
1055
1056 if (!b43_debug(dev, B43_DBG_KEYS))
1057 return;
1058
1059 hf = b43_hf_read(dev);
1060 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1061 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1062 if (b43_new_kidx_api(dev)) {
1063 pairwise_keys_start = B43_NR_GROUP_KEYS;
1064 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1065 } else {
1066 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1067 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1068 }
1069 for (index = 0; index < count; index++) {
9cf7f247
MB		 1070 key = &(dev->key[index]);
1071 printk(KERN_DEBUG "Key slot %02u: %s",
1072 index, (key->keyconf == NULL) ? " " : "*");
1073 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1074 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1075 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1076 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1077 }
1078
1079 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1080 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1081 printk(" Algo: %04X/%02X", algo, key->algorithm);
1082
66d2d089 1083 if (index >= pairwise_keys_start) {
035d0243 1084 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1085 printk(" TKIP: ");
1086 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1087 for (i = 0; i < 14; i += 2) {
1088 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1089 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1090 }
1091 }
9cf7f247 1092 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1093 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1094 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1095 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1096 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1097 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1098 printk(" MAC: %pM", mac);
9cf7f247
MB		 1099 } else
1100 printk(" DEFAULT KEY");
1101 printk("\n");
1102 }
1103}
1104
e4d6b795
MB		 1105void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1106{
1107 u32 macctl;
1108 u16 ucstat;
1109 bool hwps;
1110 bool awake;
1111 int i;
1112
1113 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1114 (ps_flags & B43_PS_DISABLED));
1115 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1116
1117 if (ps_flags & B43_PS_ENABLED) {
1118 hwps = 1;
1119 } else if (ps_flags & B43_PS_DISABLED) {
1120 hwps = 0;
1121 } else {
1122 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1123 // and thus is not an AP and we are associated, set bit 25
1124 }
1125 if (ps_flags & B43_PS_AWAKE) {
1126 awake = 1;
1127 } else if (ps_flags & B43_PS_ASLEEP) {
1128 awake = 0;
1129 } else {
1130 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1131 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1132 // successful, set bit26
1133 }
1134
1135/* FIXME: For now we force awake-on and hwps-off */
1136 hwps = 0;
1137 awake = 1;
1138
1139 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1140 if (hwps)
1141 macctl |= B43_MACCTL_HWPS;
1142 else
1143 macctl &= ~B43_MACCTL_HWPS;
1144 if (awake)
1145 macctl |= B43_MACCTL_AWAKE;
1146 else
1147 macctl &= ~B43_MACCTL_AWAKE;
1148 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1149 /* Commit write */
1150 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1151 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1152 /* Wait for the microcode to wake up. */
1153 for (i = 0; i < 100; i++) {
1154 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1155 B43_SHM_SH_UCODESTAT);
1156 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1157 break;
1158 udelay(10);
1159 }
1160 }
1161}
1162
42c9a458 1163#ifdef CONFIG_B43_BCMA
49173592 1164static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1165{
49173592 1166 u32 flags;
42c9a458 1167
49173592
RM		 1168 /* Put PHY into reset */
1169 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1170 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1171 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1172 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1173 udelay(2);
1174
1175 /* Take PHY out of reset */
1176 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1177 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1178 flags |= BCMA_IOCTL_FGC;
1179 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1180 udelay(1);
1181
1182 /* Do not force clock anymore */
1183 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1184 flags &= ~BCMA_IOCTL_FGC;
1185 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1186 udelay(1);
1187}
42c9a458 1188
49173592
RM		 1189static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1190{
1191 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1192 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1193 b43_bcma_phy_reset(dev);
1194 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
42c9a458
RM		 1195}
1196#endif
1197
4da909e7 1198static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1199{
d48ae5c8 1200 struct ssb_device *sdev = dev->dev->sdev;
e4d6b795 1201 u32 tmslow;
4da909e7 1202 u32 flags = 0;
e4d6b795 1203
4da909e7
RM		 1204 if (gmode)
1205 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1206 flags |= B43_TMSLOW_PHYCLKEN;
1207 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1208 if (dev->phy.type == B43_PHYTYPE_N)
1209 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1210 b43_device_enable(dev, flags);
e4d6b795
MB		 1211 msleep(2); /* Wait for the PLL to turn on. */
1212
1213 /* Now take the PHY out of Reset again */
d48ae5c8 1214 tmslow = ssb_read32(sdev, SSB_TMSLOW);
e4d6b795
MB		 1215 tmslow |= SSB_TMSLOW_FGC;
1216 tmslow &= ~B43_TMSLOW_PHYRESET;
d48ae5c8
RM		 1217 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1218 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795
MB		 1219 msleep(1);
1220 tmslow &= ~SSB_TMSLOW_FGC;
d48ae5c8
RM		 1221 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1222 ssb_read32(sdev, SSB_TMSLOW); /* flush */
e4d6b795 1223 msleep(1);
1495298d
RM		 1224}
1225
4da909e7 1226void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1227{
1228 u32 macctl;
1229
6cbab0d9 1230 switch (dev->dev->bus_type) {
42c9a458
RM		 1231#ifdef CONFIG_B43_BCMA
1232 case B43_BUS_BCMA:
1233 b43_bcma_wireless_core_reset(dev, gmode);
1234 break;
1235#endif
6cbab0d9
RM		 1236#ifdef CONFIG_B43_SSB
1237 case B43_BUS_SSB:
1238 b43_ssb_wireless_core_reset(dev, gmode);
1239 break;
1240#endif
1241 }
e4d6b795 1242
fb11137a
MB		 1243 /* Turn Analog ON, but only if we already know the PHY-type.
1244 * This protects against very early setup where we don't know the
1245 * PHY-type, yet. wireless_core_reset will be called once again later,
1246 * when we know the PHY-type. */
1247 if (dev->phy.ops)
cb24f57f 1248 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1249
1250 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1251 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1252 if (gmode)
e4d6b795
MB		 1253 macctl |= B43_MACCTL_GMODE;
1254 macctl |= B43_MACCTL_IHR_ENABLED;
1255 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1256}
1257
1258static void handle_irq_transmit_status(struct b43_wldev *dev)
1259{
1260 u32 v0, v1;
1261 u16 tmp;
1262 struct b43_txstatus stat;
1263
1264 while (1) {
1265 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1266 if (!(v0 & 0x00000001))
1267 break;
1268 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1269
1270 stat.cookie = (v0 >> 16);
1271 stat.seq = (v1 & 0x0000FFFF);
1272 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1273 tmp = (v0 & 0x0000FFFF);
1274 stat.frame_count = ((tmp & 0xF000) >> 12);
1275 stat.rts_count = ((tmp & 0x0F00) >> 8);
1276 stat.supp_reason = ((tmp & 0x001C) >> 2);
1277 stat.pm_indicated = !!(tmp & 0x0080);
1278 stat.intermediate = !!(tmp & 0x0040);
1279 stat.for_ampdu = !!(tmp & 0x0020);
1280 stat.acked = !!(tmp & 0x0002);
1281
1282 b43_handle_txstatus(dev, &stat);
1283 }
1284}
1285
1286static void drain_txstatus_queue(struct b43_wldev *dev)
1287{
1288 u32 dummy;
1289
21d889d4 1290 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1291 return;
1292 /* Read all entries from the microcode TXstatus FIFO
1293 * and throw them away.
1294 */
1295 while (1) {
1296 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1297 if (!(dummy & 0x00000001))
1298 break;
1299 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1300 }
1301}
1302
1303static u32 b43_jssi_read(struct b43_wldev *dev)
1304{
1305 u32 val = 0;
1306
1307 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1308 val <<= 16;
1309 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1310
1311 return val;
1312}
1313
1314static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1315{
1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1318}
1319
1320static void b43_generate_noise_sample(struct b43_wldev *dev)
1321{
1322 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1323 b43_write32(dev, B43_MMIO_MACCMD,
1324 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1325}
1326
1327static void b43_calculate_link_quality(struct b43_wldev *dev)
1328{
1329 /* Top half of Link Quality calculation. */
1330
ef1a628d
MB		 1331 if (dev->phy.type != B43_PHYTYPE_G)
1332 return;
e4d6b795
MB		 1333 if (dev->noisecalc.calculation_running)
1334 return;
e4d6b795
MB		 1335 dev->noisecalc.calculation_running = 1;
1336 dev->noisecalc.nr_samples = 0;
1337
1338 b43_generate_noise_sample(dev);
1339}
1340
1341static void handle_irq_noise(struct b43_wldev *dev)
1342{
ef1a628d 1343 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1344 u16 tmp;
1345 u8 noise[4];
1346 u8 i, j;
1347 s32 average;
1348
1349 /* Bottom half of Link Quality calculation. */
1350
ef1a628d
MB		 1351 if (dev->phy.type != B43_PHYTYPE_G)
1352 return;
1353
98a3b2fe
MB		 1354 /* Possible race condition: It might be possible that the user
1355 * changed to a different channel in the meantime since we
1356 * started the calculation. We ignore that fact, since it's
1357 * not really that much of a problem. The background noise is
1358 * an estimation only anyway. Slightly wrong results will get damped
1359 * by the averaging of the 8 sample rounds. Additionally the
1360 * value is shortlived. So it will be replaced by the next noise
1361 * calculation round soon. */
1362
e4d6b795 1363 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1364 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1365 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1366 noise[2] == 0x7F || noise[3] == 0x7F)
1367 goto generate_new;
1368
1369 /* Get the noise samples. */
1370 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1371 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1372 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1373 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1376 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1377 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1378 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1379 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1380 dev->noisecalc.nr_samples++;
1381 if (dev->noisecalc.nr_samples == 8) {
1382 /* Calculate the Link Quality by the noise samples. */
1383 average = 0;
1384 for (i = 0; i < 8; i++) {
1385 for (j = 0; j < 4; j++)
1386 average += dev->noisecalc.samples[i][j];
1387 }
1388 average /= (8 * 4);
1389 average *= 125;
1390 average += 64;
1391 average /= 128;
1392 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1393 tmp = (tmp / 128) & 0x1F;
1394 if (tmp >= 8)
1395 average += 2;
1396 else
1397 average -= 25;
1398 if (tmp == 8)
1399 average -= 72;
1400 else
1401 average -= 48;
1402
1403 dev->stats.link_noise = average;
e4d6b795
MB		 1404 dev->noisecalc.calculation_running = 0;
1405 return;
1406 }
98a3b2fe 1407generate_new:
e4d6b795
MB		 1408 b43_generate_noise_sample(dev);
1409}
1410
1411static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1412{
05c914fe 1413 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1414 ///TODO: PS TBTT
1415 } else {
1416 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1417 b43_power_saving_ctl_bits(dev, 0);
1418 }
05c914fe 1419 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1420 dev->dfq_valid = 1;
e4d6b795
MB		 1421}
1422
1423static void handle_irq_atim_end(struct b43_wldev *dev)
1424{
aa6c7ae2
MB		 1425 if (dev->dfq_valid) {
1426 b43_write32(dev, B43_MMIO_MACCMD,
1427 b43_read32(dev, B43_MMIO_MACCMD)
1428 | B43_MACCMD_DFQ_VALID);
1429 dev->dfq_valid = 0;
1430 }
e4d6b795
MB		 1431}
1432
1433static void handle_irq_pmq(struct b43_wldev *dev)
1434{
1435 u32 tmp;
1436
1437 //TODO: AP mode.
1438
1439 while (1) {
1440 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1441 if (!(tmp & 0x00000008))
1442 break;
1443 }
1444 /* 16bit write is odd, but correct. */
1445 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1446}
1447
1448static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1449 const u8 *data, u16 size,
e4d6b795
MB		 1450 u16 ram_offset,
1451 u16 shm_size_offset, u8 rate)
1452{
1453 u32 i, tmp;
1454 struct b43_plcp_hdr4 plcp;
1455
1456 plcp.data = 0;
1457 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1458 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1459 ram_offset += sizeof(u32);
1460 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1461 * So leave the first two bytes of the next write blank.
1462 */
1463 tmp = (u32) (data[0]) << 16;
1464 tmp |= (u32) (data[1]) << 24;
1465 b43_ram_write(dev, ram_offset, tmp);
1466 ram_offset += sizeof(u32);
1467 for (i = 2; i < size; i += sizeof(u32)) {
1468 tmp = (u32) (data[i + 0]);
1469 if (i + 1 < size)
1470 tmp |= (u32) (data[i + 1]) << 8;
1471 if (i + 2 < size)
1472 tmp |= (u32) (data[i + 2]) << 16;
1473 if (i + 3 < size)
1474 tmp |= (u32) (data[i + 3]) << 24;
1475 b43_ram_write(dev, ram_offset + i - 2, tmp);
1476 }
1477 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1478 size + sizeof(struct b43_plcp_hdr6));
1479}
1480
5042c507
MB		 1481/* Check if the use of the antenna that ieee80211 told us to
1482 * use is possible. This will fall back to DEFAULT.
1483 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1484u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1485 u8 antenna_nr)
1486{
1487 u8 antenna_mask;
1488
1489 if (antenna_nr == 0) {
1490 /* Zero means "use default antenna". That's always OK. */
1491 return 0;
1492 }
1493
1494 /* Get the mask of available antennas. */
1495 if (dev->phy.gmode)
0581483a 1496 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1497 else
0581483a 1498 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1499
1500 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1501 /* This antenna is not available. Fall back to default. */
1502 return 0;
1503 }
1504
1505 return antenna_nr;
1506}
1507
5042c507
MB		 1508/* Convert a b43 antenna number value to the PHY TX control value. */
1509static u16 b43_antenna_to_phyctl(int antenna)
1510{
1511 switch (antenna) {
1512 case B43_ANTENNA0:
1513 return B43_TXH_PHY_ANT0;
1514 case B43_ANTENNA1:
1515 return B43_TXH_PHY_ANT1;
1516 case B43_ANTENNA2:
1517 return B43_TXH_PHY_ANT2;
1518 case B43_ANTENNA3:
1519 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1520 case B43_ANTENNA_AUTO0:
1521 case B43_ANTENNA_AUTO1:
5042c507
MB		 1522 return B43_TXH_PHY_ANT01AUTO;
1523 }
1524 B43_WARN_ON(1);
1525 return 0;
1526}
1527
e4d6b795
MB		 1528static void b43_write_beacon_template(struct b43_wldev *dev,
1529 u16 ram_offset,
5042c507 1530 u16 shm_size_offset)
e4d6b795 1531{
47f76ca3 1532 unsigned int i, len, variable_len;
e66fee6a
MB		 1533 const struct ieee80211_mgmt *bcn;
1534 const u8 *ie;
1535 bool tim_found = 0;
5042c507
MB		 1536 unsigned int rate;
1537 u16 ctl;
1538 int antenna;
e039fa4a 1539 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1540
e66fee6a
MB		 1541 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1542 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1543 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1544 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1545
1546 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1547 len, ram_offset, shm_size_offset, rate);
e66fee6a 1548
5042c507 1549 /* Write the PHY TX control parameters. */
0f4ac38b 1550 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1551 antenna = b43_antenna_to_phyctl(antenna);
1552 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1553 /* We can't send beacons with short preamble. Would get PHY errors. */
1554 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1555 ctl &= ~B43_TXH_PHY_ANT;
1556 ctl &= ~B43_TXH_PHY_ENC;
1557 ctl |= antenna;
1558 if (b43_is_cck_rate(rate))
1559 ctl |= B43_TXH_PHY_ENC_CCK;
1560 else
1561 ctl |= B43_TXH_PHY_ENC_OFDM;
1562 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1563
e66fee6a
MB		 1564 /* Find the position of the TIM and the DTIM_period value
1565 * and write them to SHM. */
1566 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1567 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1568 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1569 uint8_t ie_id, ie_len;
1570
1571 ie_id = ie[i];
1572 ie_len = ie[i + 1];
1573 if (ie_id == 5) {
1574 u16 tim_position;
1575 u16 dtim_period;
1576 /* This is the TIM Information Element */
1577
1578 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1579 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1580 break;
1581 /* A valid TIM is at least 4 bytes long. */
1582 if (ie_len < 4)
1583 break;
1584 tim_found = 1;
1585
1586 tim_position = sizeof(struct b43_plcp_hdr6);
1587 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1588 tim_position += i;
1589
1590 dtim_period = ie[i + 3];
1591
1592 b43_shm_write16(dev, B43_SHM_SHARED,
1593 B43_SHM_SH_TIMBPOS, tim_position);
1594 b43_shm_write16(dev, B43_SHM_SHARED,
1595 B43_SHM_SH_DTIMPER, dtim_period);
1596 break;
1597 }
1598 i += ie_len + 2;
1599 }
1600 if (!tim_found) {
04dea136
JB		 1601 /*
1602 * If ucode wants to modify TIM do it behind the beacon, this
1603 * will happen, for example, when doing mesh networking.
1604 */
1605 b43_shm_write16(dev, B43_SHM_SHARED,
1606 B43_SHM_SH_TIMBPOS,
1607 len + sizeof(struct b43_plcp_hdr6));
1608 b43_shm_write16(dev, B43_SHM_SHARED,
1609 B43_SHM_SH_DTIMPER, 0);
1610 }
1611 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1612}
1613
6b4bec01
MB		 1614static void b43_upload_beacon0(struct b43_wldev *dev)
1615{
1616 struct b43_wl *wl = dev->wl;
1617
1618 if (wl->beacon0_uploaded)
1619 return;
1620 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1621 wl->beacon0_uploaded = 1;
1622}
1623
1624static void b43_upload_beacon1(struct b43_wldev *dev)
1625{
1626 struct b43_wl *wl = dev->wl;
1627
1628 if (wl->beacon1_uploaded)
1629 return;
1630 b43_write_beacon_template(dev, 0x468, 0x1A);
1631 wl->beacon1_uploaded = 1;
1632}
1633
c97a4ccc
MB		 1634static void handle_irq_beacon(struct b43_wldev *dev)
1635{
1636 struct b43_wl *wl = dev->wl;
1637 u32 cmd, beacon0_valid, beacon1_valid;
1638
05c914fe 1639 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1640 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1641 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1642 return;
1643
1644 /* This is the bottom half of the asynchronous beacon update. */
1645
1646 /* Ignore interrupt in the future. */
13790728 1647 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1648
1649 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1650 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1651 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1652
1653 /* Schedule interrupt manually, if busy. */
1654 if (beacon0_valid && beacon1_valid) {
1655 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1656 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1657 return;
1658 }
1659
6b4bec01
MB		 1660 if (unlikely(wl->beacon_templates_virgin)) {
1661 /* We never uploaded a beacon before.
1662 * Upload both templates now, but only mark one valid. */
1663 wl->beacon_templates_virgin = 0;
1664 b43_upload_beacon0(dev);
1665 b43_upload_beacon1(dev);
c97a4ccc
MB		 1666 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1667 cmd |= B43_MACCMD_BEACON0_VALID;
1668 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1669 } else {
1670 if (!beacon0_valid) {
1671 b43_upload_beacon0(dev);
1672 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1673 cmd |= B43_MACCMD_BEACON0_VALID;
1674 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1675 } else if (!beacon1_valid) {
1676 b43_upload_beacon1(dev);
1677 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1678 cmd |= B43_MACCMD_BEACON1_VALID;
1679 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1680 }
c97a4ccc
MB		 1681 }
1682}
1683
36dbd954
MB		 1684static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1685{
1686 u32 old_irq_mask = dev->irq_mask;
1687
1688 /* update beacon right away or defer to irq */
1689 handle_irq_beacon(dev);
1690 if (old_irq_mask != dev->irq_mask) {
1691 /* The handler updated the IRQ mask. */
1692 B43_WARN_ON(!dev->irq_mask);
1693 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1694 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1695 } else {
1696 /* Device interrupts are currently disabled. That means
1697 * we just ran the hardirq handler and scheduled the
1698 * IRQ thread. The thread will write the IRQ mask when
1699 * it finished, so there's nothing to do here. Writing
1700 * the mask _here_ would incorrectly re-enable IRQs. */
1701 }
1702 }
1703}
1704
a82d9922
MB		 1705static void b43_beacon_update_trigger_work(struct work_struct *work)
1706{
1707 struct b43_wl *wl = container_of(work, struct b43_wl,
1708 beacon_update_trigger);
1709 struct b43_wldev *dev;
1710
1711 mutex_lock(&wl->mutex);
1712 dev = wl->current_dev;
1713 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1714 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1715 /* wl->mutex is enough. */
1716 b43_do_beacon_update_trigger_work(dev);
1717 mmiowb();
1718 } else {
1719 spin_lock_irq(&wl->hardirq_lock);
1720 b43_do_beacon_update_trigger_work(dev);
1721 mmiowb();
1722 spin_unlock_irq(&wl->hardirq_lock);
1723 }
a82d9922
MB		 1724 }
1725 mutex_unlock(&wl->mutex);
1726}
1727
d4df6f1a 1728/* Asynchronously update the packet templates in template RAM.
36dbd954 1729 * Locking: Requires wl->mutex to be locked. */
9d139c81 1730static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1731{
9d139c81
JB		 1732 struct sk_buff *beacon;
1733
e66fee6a
MB		 1734 /* This is the top half of the ansynchronous beacon update.
1735 * The bottom half is the beacon IRQ.
1736 * Beacon update must be asynchronous to avoid sending an
1737 * invalid beacon. This can happen for example, if the firmware
1738 * transmits a beacon while we are updating it. */
e4d6b795 1739
9d139c81
JB		 1740 /* We could modify the existing beacon and set the aid bit in
1741 * the TIM field, but that would probably require resizing and
1742 * moving of data within the beacon template.
1743 * Simply request a new beacon and let mac80211 do the hard work. */
1744 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1745 if (unlikely(!beacon))
1746 return;
1747
e66fee6a
MB		 1748 if (wl->current_beacon)
1749 dev_kfree_skb_any(wl->current_beacon);
1750 wl->current_beacon = beacon;
1751 wl->beacon0_uploaded = 0;
1752 wl->beacon1_uploaded = 0;
42935eca 1753 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1754}
1755
e4d6b795
MB		 1756static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1757{
1758 b43_time_lock(dev);
21d889d4 1759 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1760 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1761 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1762 } else {
1763 b43_write16(dev, 0x606, (beacon_int >> 6));
1764 b43_write16(dev, 0x610, beacon_int);
1765 }
1766 b43_time_unlock(dev);
a82d9922 1767 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1768}
1769
afa83e23
MB		 1770static void b43_handle_firmware_panic(struct b43_wldev *dev)
1771{
1772 u16 reason;
1773
1774 /* Read the register that contains the reason code for the panic. */
1775 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1776 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1777
1778 switch (reason) {
1779 default:
1780 b43dbg(dev->wl, "The panic reason is unknown.\n");
1781 /* fallthrough */
1782 case B43_FWPANIC_DIE:
1783 /* Do not restart the controller or firmware.
1784 * The device is nonfunctional from now on.
1785 * Restarting would result in this panic to trigger again,
1786 * so we avoid that recursion. */
1787 break;
1788 case B43_FWPANIC_RESTART:
1789 b43_controller_restart(dev, "Microcode panic");
1790 break;
1791 }
1792}
1793
e4d6b795
MB		 1794static void handle_irq_ucode_debug(struct b43_wldev *dev)
1795{
e48b0eeb 1796 unsigned int i, cnt;
53c06856 1797 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1798 __le16 *buf;
1799
1800 /* The proprietary firmware doesn't have this IRQ. */
1801 if (!dev->fw.opensource)
1802 return;
1803
afa83e23
MB		 1804 /* Read the register that contains the reason code for this IRQ. */
1805 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1806
e48b0eeb
MB		 1807 switch (reason) {
1808 case B43_DEBUGIRQ_PANIC:
afa83e23 1809 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1810 break;
1811 case B43_DEBUGIRQ_DUMP_SHM:
1812 if (!B43_DEBUG)
1813 break; /* Only with driver debugging enabled. */
1814 buf = kmalloc(4096, GFP_ATOMIC);
1815 if (!buf) {
1816 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1817 goto out;
1818 }
1819 for (i = 0; i < 4096; i += 2) {
1820 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1821 buf[i / 2] = cpu_to_le16(tmp);
1822 }
1823 b43info(dev->wl, "Shared memory dump:\n");
1824 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1825 16, 2, buf, 4096, 1);
1826 kfree(buf);
1827 break;
1828 case B43_DEBUGIRQ_DUMP_REGS:
1829 if (!B43_DEBUG)
1830 break; /* Only with driver debugging enabled. */
1831 b43info(dev->wl, "Microcode register dump:\n");
1832 for (i = 0, cnt = 0; i < 64; i++) {
1833 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1834 if (cnt == 0)
1835 printk(KERN_INFO);
1836 printk("r%02u: 0x%04X ", i, tmp);
1837 cnt++;
1838 if (cnt == 6) {
1839 printk("\n");
1840 cnt = 0;
1841 }
1842 }
1843 printk("\n");
1844 break;
53c06856
MB		 1845 case B43_DEBUGIRQ_MARKER:
1846 if (!B43_DEBUG)
1847 break; /* Only with driver debugging enabled. */
1848 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1849 B43_MARKER_ID_REG);
1850 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1851 B43_MARKER_LINE_REG);
1852 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1853 "at line number %u\n",
1854 marker_id, marker_line);
1855 break;
e48b0eeb
MB		 1856 default:
1857 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1858 reason);
1859 }
1860out:
afa83e23
MB		 1861 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1862 b43_shm_write16(dev, B43_SHM_SCRATCH,
1863 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1864}
1865
36dbd954 1866static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1867{
1868 u32 reason;
1869 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1870 u32 merged_dma_reason = 0;
21954c36 1871 int i;
e4d6b795 1872
36dbd954
MB		 1873 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1874 return;
e4d6b795
MB		 1875
1876 reason = dev->irq_reason;
1877 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1878 dma_reason[i] = dev->dma_reason[i];
1879 merged_dma_reason |= dma_reason[i];
1880 }
1881
1882 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1883 b43err(dev->wl, "MAC transmission error\n");
1884
00e0b8cb 1885 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1886 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1887 rmb();
1888 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1889 atomic_set(&dev->phy.txerr_cnt,
1890 B43_PHY_TX_BADNESS_LIMIT);
1891 b43err(dev->wl, "Too many PHY TX errors, "
1892 "restarting the controller\n");
1893 b43_controller_restart(dev, "PHY TX errors");
1894 }
1895 }
e4d6b795
MB		 1896
1897 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1898 B43_DMAIRQ_NONFATALMASK))) {
1899 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1900 b43err(dev->wl, "Fatal DMA error: "
1901 "0x%08X, 0x%08X, 0x%08X, "
1902 "0x%08X, 0x%08X, 0x%08X\n",
1903 dma_reason[0], dma_reason[1],
1904 dma_reason[2], dma_reason[3],
1905 dma_reason[4], dma_reason[5]);
214ac9a4 1906 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1907 "on your system. It will now be switched to PIO.\n");
9e3bd919
LT		 1908 /* Fall back to PIO transfers if we get fatal DMA errors! */
1909 dev->use_pio = 1;
1910 b43_controller_restart(dev, "DMA error");
e4d6b795
MB		 1911 return;
1912 }
1913 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1914 b43err(dev->wl, "DMA error: "
1915 "0x%08X, 0x%08X, 0x%08X, "
1916 "0x%08X, 0x%08X, 0x%08X\n",
1917 dma_reason[0], dma_reason[1],
1918 dma_reason[2], dma_reason[3],
1919 dma_reason[4], dma_reason[5]);
1920 }
1921 }
1922
1923 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1924 handle_irq_ucode_debug(dev);
1925 if (reason & B43_IRQ_TBTT_INDI)
1926 handle_irq_tbtt_indication(dev);
1927 if (reason & B43_IRQ_ATIM_END)
1928 handle_irq_atim_end(dev);
1929 if (reason & B43_IRQ_BEACON)
1930 handle_irq_beacon(dev);
1931 if (reason & B43_IRQ_PMQ)
1932 handle_irq_pmq(dev);
21954c36
MB		 1933 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1934 ;/* TODO */
1935 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1936 handle_irq_noise(dev);
1937
1938 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1939 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1940 if (b43_using_pio_transfers(dev))
1941 b43_pio_rx(dev->pio.rx_queue);
1942 else
1943 b43_dma_rx(dev->dma.rx_ring);
1944 }
e4d6b795
MB		 1945 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1946 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1947 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1948 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1949 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1950
21954c36 1951 if (reason & B43_IRQ_TX_OK)
e4d6b795 1952 handle_irq_transmit_status(dev);
e4d6b795 1953
36dbd954 1954 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1955 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1956
1957#if B43_DEBUG
1958 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1959 dev->irq_count++;
1960 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1961 if (reason & (1 << i))
1962 dev->irq_bit_count[i]++;
1963 }
1964 }
1965#endif
e4d6b795
MB		 1966}
1967
36dbd954
MB		 1968/* Interrupt thread handler. Handles device interrupts in thread context. */
1969static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1970{
36dbd954 1971 struct b43_wldev *dev = dev_id;
e4d6b795 1972
36dbd954
MB		 1973 mutex_lock(&dev->wl->mutex);
1974 b43_do_interrupt_thread(dev);
1975 mmiowb();
1976 mutex_unlock(&dev->wl->mutex);
1977
1978 return IRQ_HANDLED;
e4d6b795
MB		 1979}
1980
36dbd954 1981static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1982{
e4d6b795
MB		 1983 u32 reason;
1984
36dbd954
MB		 1985 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1986 * On SDIO, this runs under wl->mutex. */
e4d6b795 1987
e4d6b795
MB		 1988 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1989 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1990 return IRQ_NONE;
13790728 1991 reason &= dev->irq_mask;
e4d6b795 1992 if (!reason)
cae56147 1993 return IRQ_NONE;
e4d6b795
MB		 1994
1995 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1996 & 0x0001DC00;
1997 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1998 & 0x0000DC00;
1999 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2000 & 0x0000DC00;
2001 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2002 & 0x0001DC00;
2003 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2004 & 0x0000DC00;
13790728 2005/* Unused ring
e4d6b795
MB		 2006 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2007 & 0x0000DC00;
13790728 2008*/
e4d6b795 2009
36dbd954
MB		 2010 /* ACK the interrupt. */
2011 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2012 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2013 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2014 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2015 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2016 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2017/* Unused ring
2018 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2019*/
2020
2021 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2022 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2023 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2024 dev->irq_reason = reason;
36dbd954
MB		 2025
2026 return IRQ_WAKE_THREAD;
2027}
2028
2029/* Interrupt handler top-half. This runs with interrupts disabled. */
2030static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2031{
2032 struct b43_wldev *dev = dev_id;
2033 irqreturn_t ret;
2034
2035 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2036 return IRQ_NONE;
2037
2038 spin_lock(&dev->wl->hardirq_lock);
2039 ret = b43_do_interrupt(dev);
e4d6b795 2040 mmiowb();
36dbd954 2041 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2042
2043 return ret;
2044}
2045
3dbba8e2
AH		 2046/* SDIO interrupt handler. This runs in process context. */
2047static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2048{
2049 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2050 irqreturn_t ret;
2051
3dbba8e2 2052 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2053
2054 ret = b43_do_interrupt(dev);
2055 if (ret == IRQ_WAKE_THREAD)
2056 b43_do_interrupt_thread(dev);
2057
3dbba8e2
AH		 2058 mutex_unlock(&wl->mutex);
2059}
2060
1a9f5093 2061void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2062{
2063 release_firmware(fw->data);
2064 fw->data = NULL;
2065 fw->filename = NULL;
2066}
2067
e4d6b795
MB		 2068static void b43_release_firmware(struct b43_wldev *dev)
2069{
1a9f5093
MB		 2070 b43_do_release_fw(&dev->fw.ucode);
2071 b43_do_release_fw(&dev->fw.pcm);
2072 b43_do_release_fw(&dev->fw.initvals);
2073 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2074}
2075
eb189d8b 2076static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2077{
fc68ed4f
HE		 2078 const char text[] =
2079 "You must go to " \
2080 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2081 "and download the correct firmware for this driver version. " \
2082 "Please carefully read all instructions on this website.\n";
eb189d8b 2083
eb189d8b
MB		 2084 if (error)
2085 b43err(wl, text);
2086 else
2087 b43warn(wl, text);
e4d6b795
MB		 2088}
2089
1a9f5093
MB		 2090int b43_do_request_fw(struct b43_request_fw_context *ctx,
2091 const char *name,
2092 struct b43_firmware_file *fw)
e4d6b795 2093{
61cb5dd6 2094 const struct firmware *blob;
e4d6b795
MB		 2095 struct b43_fw_header *hdr;
2096 u32 size;
2097 int err;
2098
61cb5dd6
MB		 2099 if (!name) {
2100 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2101 /* FIXME: We should probably keep it anyway, to save some headache
2102 * on suspend/resume with multiband devices. */
2103 b43_do_release_fw(fw);
e4d6b795 2104 return 0;
61cb5dd6
MB		 2105 }
2106 if (fw->filename) {
1a9f5093
MB		 2107 if ((fw->type == ctx->req_type) &&
2108 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2109 return 0; /* Already have this fw. */
2110 /* Free the cached firmware first. */
1a9f5093
MB		 2111 /* FIXME: We should probably do this later after we successfully
2112 * got the new fw. This could reduce headache with multiband devices.
2113 * We could also redesign this to cache the firmware for all possible
2114 * bands all the time. */
2115 b43_do_release_fw(fw);
61cb5dd6 2116 }
e4d6b795 2117
1a9f5093
MB		 2118 switch (ctx->req_type) {
2119 case B43_FWTYPE_PROPRIETARY:
2120 snprintf(ctx->fwname, sizeof(ctx->fwname),
2121 "b43%s/%s.fw",
2122 modparam_fwpostfix, name);
2123 break;
2124 case B43_FWTYPE_OPENSOURCE:
2125 snprintf(ctx->fwname, sizeof(ctx->fwname),
2126 "b43-open%s/%s.fw",
2127 modparam_fwpostfix, name);
2128 break;
2129 default:
2130 B43_WARN_ON(1);
2131 return -ENOSYS;
2132 }
a18c715e 2133 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2134 if (err == -ENOENT) {
1a9f5093
MB		 2135 snprintf(ctx->errors[ctx->req_type],
2136 sizeof(ctx->errors[ctx->req_type]),
2137 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2138 return err;
2139 } else if (err) {
1a9f5093
MB		 2140 snprintf(ctx->errors[ctx->req_type],
2141 sizeof(ctx->errors[ctx->req_type]),
2142 "Firmware file \"%s\" request failed (err=%d)\n",
2143 ctx->fwname, err);
e4d6b795
MB		 2144 return err;
2145 }
61cb5dd6 2146 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2147 goto err_format;
61cb5dd6 2148 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2149 switch (hdr->type) {
2150 case B43_FW_TYPE_UCODE:
2151 case B43_FW_TYPE_PCM:
2152 size = be32_to_cpu(hdr->size);
61cb5dd6 2153 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2154 goto err_format;
2155 /* fallthrough */
2156 case B43_FW_TYPE_IV:
2157 if (hdr->ver != 1)
2158 goto err_format;
2159 break;
2160 default:
2161 goto err_format;
2162 }
2163
61cb5dd6
MB		 2164 fw->data = blob;
2165 fw->filename = name;
1a9f5093 2166 fw->type = ctx->req_type;
61cb5dd6
MB		 2167
2168 return 0;
e4d6b795
MB		 2169
2170err_format:
1a9f5093
MB		 2171 snprintf(ctx->errors[ctx->req_type],
2172 sizeof(ctx->errors[ctx->req_type]),
2173 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2174 release_firmware(blob);
2175
e4d6b795
MB		 2176 return -EPROTO;
2177}
2178
1a9f5093 2179static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2180{
1a9f5093
MB		 2181 struct b43_wldev *dev = ctx->dev;
2182 struct b43_firmware *fw = &ctx->dev->fw;
21d889d4 2183 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795
MB		 2184 const char *filename;
2185 u32 tmshigh;
2186 int err;
2187
8b9bda75
RM		 2188 /* Files for HT and LCN were found by trying one by one */
2189
61cb5dd6 2190 /* Get microcode */
6ff1e5cf 2191 if ((rev >= 5) && (rev <= 10)) {
61cb5dd6 2192 filename = "ucode5";
6ff1e5cf 2193 } else if ((rev >= 11) && (rev <= 12)) {
61cb5dd6 2194 filename = "ucode11";
6ff1e5cf 2195 } else if (rev == 13) {
61cb5dd6 2196 filename = "ucode13";
6ff1e5cf 2197 } else if (rev == 14) {
759b973b 2198 filename = "ucode14";
6ff1e5cf 2199 } else if (rev == 15) {
759b973b 2200 filename = "ucode15";
6ff1e5cf
RM		 2201 } else {
2202 switch (dev->phy.type) {
2203 case B43_PHYTYPE_N:
2204 if (rev >= 16)
2205 filename = "ucode16_mimo";
2206 else
2207 goto err_no_ucode;
2208 break;
8b9bda75
RM		 2209 case B43_PHYTYPE_HT:
2210 if (rev == 29)
2211 filename = "ucode29_mimo";
2212 else
2213 goto err_no_ucode;
2214 break;
2215 case B43_PHYTYPE_LCN:
2216 if (rev == 24)
2217 filename = "ucode24_mimo";
2218 else
2219 goto err_no_ucode;
2220 break;
6ff1e5cf
RM		 2221 default:
2222 goto err_no_ucode;
2223 }
2224 }
1a9f5093 2225 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2226 if (err)
2227 goto err_load;
2228
2229 /* Get PCM code */
2230 if ((rev >= 5) && (rev <= 10))
2231 filename = "pcm5";
2232 else if (rev >= 11)
2233 filename = NULL;
2234 else
2235 goto err_no_pcm;
68217832 2236 fw->pcm_request_failed = 0;
1a9f5093 2237 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2238 if (err == -ENOENT) {
2239 /* We did not find a PCM file? Not fatal, but
2240 * core rev <= 10 must do without hwcrypto then. */
2241 fw->pcm_request_failed = 1;
2242 } else if (err)
61cb5dd6
MB		 2243 goto err_load;
2244
2245 /* Get initvals */
2246 switch (dev->phy.type) {
2247 case B43_PHYTYPE_A:
2248 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2249 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2250 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2251 filename = "a0g1initvals5";
2252 else
2253 filename = "a0g0initvals5";
2254 } else
2255 goto err_no_initvals;
2256 break;
2257 case B43_PHYTYPE_G:
e4d6b795 2258 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2259 filename = "b0g0initvals5";
e4d6b795 2260 else if (rev >= 13)
e9304882 2261 filename = "b0g0initvals13";
e4d6b795 2262 else
61cb5dd6
MB		 2263 goto err_no_initvals;
2264 break;
2265 case B43_PHYTYPE_N:
e41596a1
RM		 2266 if (rev >= 16)
2267 filename = "n0initvals16";
2268 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2269 filename = "n0initvals11";
2270 else
2271 goto err_no_initvals;
2272 break;
759b973b
GS		 2273 case B43_PHYTYPE_LP:
2274 if (rev == 13)
2275 filename = "lp0initvals13";
2276 else if (rev == 14)
2277 filename = "lp0initvals14";
2278 else if (rev >= 15)
2279 filename = "lp0initvals15";
2280 else
2281 goto err_no_initvals;
2282 break;
8b9bda75
RM		 2283 case B43_PHYTYPE_HT:
2284 if (rev == 29)
2285 filename = "ht0initvals29";
2286 else
2287 goto err_no_initvals;
2288 break;
2289 case B43_PHYTYPE_LCN:
2290 if (rev == 24)
2291 filename = "lcn0initvals24";
2292 else
2293 goto err_no_initvals;
2294 break;
61cb5dd6
MB		 2295 default:
2296 goto err_no_initvals;
e4d6b795 2297 }
1a9f5093 2298 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2299 if (err)
2300 goto err_load;
2301
2302 /* Get bandswitch initvals */
2303 switch (dev->phy.type) {
2304 case B43_PHYTYPE_A:
2305 if ((rev >= 5) && (rev <= 10)) {
d48ae5c8 2306 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
61cb5dd6
MB		 2307 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2308 filename = "a0g1bsinitvals5";
2309 else
2310 filename = "a0g0bsinitvals5";
2311 } else if (rev >= 11)
2312 filename = NULL;
2313 else
2314 goto err_no_initvals;
2315 break;
2316 case B43_PHYTYPE_G:
e4d6b795 2317 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2318 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2319 else if (rev >= 11)
2320 filename = NULL;
2321 else
e4d6b795 2322 goto err_no_initvals;
61cb5dd6
MB		 2323 break;
2324 case B43_PHYTYPE_N:
e41596a1
RM		 2325 if (rev >= 16)
2326 filename = "n0bsinitvals16";
2327 else if ((rev >= 11) && (rev <= 12))
61cb5dd6
MB		 2328 filename = "n0bsinitvals11";
2329 else
e4d6b795 2330 goto err_no_initvals;
61cb5dd6 2331 break;
759b973b
GS		 2332 case B43_PHYTYPE_LP:
2333 if (rev == 13)
2334 filename = "lp0bsinitvals13";
2335 else if (rev == 14)
2336 filename = "lp0bsinitvals14";
2337 else if (rev >= 15)
2338 filename = "lp0bsinitvals15";
2339 else
2340 goto err_no_initvals;
2341 break;
8b9bda75
RM		 2342 case B43_PHYTYPE_HT:
2343 if (rev == 29)
2344 filename = "ht0bsinitvals29";
2345 else
2346 goto err_no_initvals;
2347 break;
2348 case B43_PHYTYPE_LCN:
2349 if (rev == 24)
2350 filename = "lcn0bsinitvals24";
2351 else
2352 goto err_no_initvals;
2353 break;
61cb5dd6
MB		 2354 default:
2355 goto err_no_initvals;
e4d6b795 2356 }
1a9f5093 2357 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2358 if (err)
2359 goto err_load;
e4d6b795
MB		 2360
2361 return 0;
2362
e4d6b795 2363err_no_ucode:
1a9f5093
MB		 2364 err = ctx->fatal_failure = -EOPNOTSUPP;
2365 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2366 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2367 goto error;
2368
2369err_no_pcm:
1a9f5093
MB		 2370 err = ctx->fatal_failure = -EOPNOTSUPP;
2371 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2372 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2373 goto error;
2374
2375err_no_initvals:
1a9f5093
MB		 2376 err = ctx->fatal_failure = -EOPNOTSUPP;
2377 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2378 "is required for your device (wl-core rev %u)\n", rev);
2379 goto error;
2380
2381err_load:
2382 /* We failed to load this firmware image. The error message
2383 * already is in ctx->errors. Return and let our caller decide
2384 * what to do. */
e4d6b795
MB		 2385 goto error;
2386
2387error:
2388 b43_release_firmware(dev);
2389 return err;
2390}
2391
1a9f5093
MB		 2392static int b43_request_firmware(struct b43_wldev *dev)
2393{
2394 struct b43_request_fw_context *ctx;
2395 unsigned int i;
2396 int err;
2397 const char *errmsg;
2398
2399 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2400 if (!ctx)
2401 return -ENOMEM;
2402 ctx->dev = dev;
2403
2404 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2405 err = b43_try_request_fw(ctx);
2406 if (!err)
2407 goto out; /* Successfully loaded it. */
2408 err = ctx->fatal_failure;
2409 if (err)
2410 goto out;
2411
2412 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2413 err = b43_try_request_fw(ctx);
2414 if (!err)
2415 goto out; /* Successfully loaded it. */
2416 err = ctx->fatal_failure;
2417 if (err)
2418 goto out;
2419
2420 /* Could not find a usable firmware. Print the errors. */
2421 for (i = 0; i < B43_NR_FWTYPES; i++) {
2422 errmsg = ctx->errors[i];
2423 if (strlen(errmsg))
2424 b43err(dev->wl, errmsg);
2425 }
2426 b43_print_fw_helptext(dev->wl, 1);
2427 err = -ENOENT;
2428
2429out:
2430 kfree(ctx);
2431 return err;
2432}
2433
e4d6b795
MB		 2434static int b43_upload_microcode(struct b43_wldev *dev)
2435{
652caa5b 2436 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2437 const size_t hdr_len = sizeof(struct b43_fw_header);
2438 const __be32 *data;
2439 unsigned int i, len;
2440 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2441 u32 tmp, macctl;
e4d6b795
MB		 2442 int err = 0;
2443
1f7d87b0
MB		 2444 /* Jump the microcode PSM to offset 0 */
2445 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2446 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2447 macctl |= B43_MACCTL_PSM_JMP0;
2448 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2449 /* Zero out all microcode PSM registers and shared memory. */
2450 for (i = 0; i < 64; i++)
2451 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2452 for (i = 0; i < 4096; i += 2)
2453 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2454
e4d6b795 2455 /* Upload Microcode. */
61cb5dd6
MB		 2456 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2457 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2458 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2459 for (i = 0; i < len; i++) {
2460 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2461 udelay(10);
2462 }
2463
61cb5dd6 2464 if (dev->fw.pcm.data) {
e4d6b795 2465 /* Upload PCM data. */
61cb5dd6
MB		 2466 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2467 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2468 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2469 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2470 /* No need for autoinc bit in SHM_HW */
2471 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2472 for (i = 0; i < len; i++) {
2473 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2474 udelay(10);
2475 }
2476 }
2477
2478 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2479
2480 /* Start the microcode PSM */
2481 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2482 macctl &= ~B43_MACCTL_PSM_JMP0;
2483 macctl |= B43_MACCTL_PSM_RUN;
2484 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2485
2486 /* Wait for the microcode to load and respond */
2487 i = 0;
2488 while (1) {
2489 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2490 if (tmp == B43_IRQ_MAC_SUSPENDED)
2491 break;
2492 i++;
1f7d87b0 2493 if (i >= 20) {
e4d6b795 2494 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2495 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2496 err = -ENODEV;
1f7d87b0
MB		 2497 goto error;
2498 }
e175e996 2499 msleep(50);
e4d6b795
MB		 2500 }
2501 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2502
2503 /* Get and check the revisions. */
2504 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2505 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2506 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2507 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2508
2509 if (fwrev <= 0x128) {
2510 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2511 "binary drivers older than version 4.x is unsupported. "
2512 "You must upgrade your firmware files.\n");
eb189d8b 2513 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2514 err = -EOPNOTSUPP;
1f7d87b0 2515 goto error;
e4d6b795 2516 }
e4d6b795
MB		 2517 dev->fw.rev = fwrev;
2518 dev->fw.patch = fwpatch;
5d852905
RM		 2519 if (dev->fw.rev >= 598)
2520 dev->fw.hdr_format = B43_FW_HDR_598;
2521 else if (dev->fw.rev >= 410)
efe0249b
RM		 2522 dev->fw.hdr_format = B43_FW_HDR_410;
2523 else
2524 dev->fw.hdr_format = B43_FW_HDR_351;
e48b0eeb
MB		 2525 dev->fw.opensource = (fwdate == 0xFFFF);
2526
403a3a13
MB		 2527 /* Default to use-all-queues. */
2528 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2529 dev->qos_enabled = !!modparam_qos;
2530 /* Default to firmware/hardware crypto acceleration. */
2531 dev->hwcrypto_enabled = 1;
2532
e48b0eeb 2533 if (dev->fw.opensource) {
403a3a13
MB		 2534 u16 fwcapa;
2535
e48b0eeb
MB		 2536 /* Patchlevel info is encoded in the "time" field. */
2537 dev->fw.patch = fwtime;
403a3a13
MB		 2538 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2539 dev->fw.rev, dev->fw.patch);
2540
2541 fwcapa = b43_fwcapa_read(dev);
2542 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2543 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2544 /* Disable hardware crypto and fall back to software crypto. */
2545 dev->hwcrypto_enabled = 0;
2546 }
2547 if (!(fwcapa & B43_FWCAPA_QOS)) {
2548 b43info(dev->wl, "QoS not supported by firmware\n");
2549 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2550 * ieee80211_unregister to make sure the networking core can
2551 * properly free possible resources. */
2552 dev->wl->hw->queues = 1;
2553 dev->qos_enabled = 0;
2554 }
e48b0eeb
MB		 2555 } else {
2556 b43info(dev->wl, "Loading firmware version %u.%u "
2557 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2558 fwrev, fwpatch,
2559 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2560 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2561 if (dev->fw.pcm_request_failed) {
2562 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2563 "Hardware accelerated cryptography is disabled.\n");
2564 b43_print_fw_helptext(dev->wl, 0);
2565 }
e48b0eeb 2566 }
e4d6b795 2567
652caa5b
JL		 2568 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2569 dev->fw.rev, dev->fw.patch);
21d889d4 2570 wiphy->hw_version = dev->dev->core_id;
652caa5b 2571
efe0249b 2572 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2573 /* We're over the deadline, but we keep support for old fw
2574 * until it turns out to be in major conflict with something new. */
eb189d8b 2575 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2576 "Support for old firmware will be removed soon "
2577 "(official deadline was July 2008).\n");
eb189d8b
MB		 2578 b43_print_fw_helptext(dev->wl, 0);
2579 }
2580
1f7d87b0
MB		 2581 return 0;
2582
2583error:
2584 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2585 macctl &= ~B43_MACCTL_PSM_RUN;
2586 macctl |= B43_MACCTL_PSM_JMP0;
2587 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2588
e4d6b795
MB		 2589 return err;
2590}
2591
2592static int b43_write_initvals(struct b43_wldev *dev,
2593 const struct b43_iv *ivals,
2594 size_t count,
2595 size_t array_size)
2596{
2597 const struct b43_iv *iv;
2598 u16 offset;
2599 size_t i;
2600 bool bit32;
2601
2602 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2603 iv = ivals;
2604 for (i = 0; i < count; i++) {
2605 if (array_size < sizeof(iv->offset_size))
2606 goto err_format;
2607 array_size -= sizeof(iv->offset_size);
2608 offset = be16_to_cpu(iv->offset_size);
2609 bit32 = !!(offset & B43_IV_32BIT);
2610 offset &= B43_IV_OFFSET_MASK;
2611 if (offset >= 0x1000)
2612 goto err_format;
2613 if (bit32) {
2614 u32 value;
2615
2616 if (array_size < sizeof(iv->data.d32))
2617 goto err_format;
2618 array_size -= sizeof(iv->data.d32);
2619
533dd1b0 2620 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2621 b43_write32(dev, offset, value);
2622
2623 iv = (const struct b43_iv *)((const uint8_t *)iv +
2624 sizeof(__be16) +
2625 sizeof(__be32));
2626 } else {
2627 u16 value;
2628
2629 if (array_size < sizeof(iv->data.d16))
2630 goto err_format;
2631 array_size -= sizeof(iv->data.d16);
2632
2633 value = be16_to_cpu(iv->data.d16);
2634 b43_write16(dev, offset, value);
2635
2636 iv = (const struct b43_iv *)((const uint8_t *)iv +
2637 sizeof(__be16) +
2638 sizeof(__be16));
2639 }
2640 }
2641 if (array_size)
2642 goto err_format;
2643
2644 return 0;
2645
2646err_format:
2647 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2648 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2649
2650 return -EPROTO;
2651}
2652
2653static int b43_upload_initvals(struct b43_wldev *dev)
2654{
2655 const size_t hdr_len = sizeof(struct b43_fw_header);
2656 const struct b43_fw_header *hdr;
2657 struct b43_firmware *fw = &dev->fw;
2658 const struct b43_iv *ivals;
2659 size_t count;
2660 int err;
2661
61cb5dd6
MB		 2662 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2663 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2664 count = be32_to_cpu(hdr->size);
2665 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2666 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2667 if (err)
2668 goto out;
61cb5dd6
MB		 2669 if (fw->initvals_band.data) {
2670 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2671 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2672 count = be32_to_cpu(hdr->size);
2673 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2674 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2675 if (err)
2676 goto out;
2677 }
2678out:
2679
2680 return err;
2681}
2682
2683/* Initialize the GPIOs
2684 * http://bcm-specs.sipsolutions.net/GPIO
2685 */
c4a2a081 2686static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2687{
d48ae5c8 2688 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2689
2690#ifdef CONFIG_SSB_DRIVER_PCICORE
2691 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2692#else
2693 return bus->chipco.dev;
2694#endif
2695}
2696
e4d6b795
MB		 2697static int b43_gpio_init(struct b43_wldev *dev)
2698{
c4a2a081 2699 struct ssb_device *gpiodev;
e4d6b795
MB		 2700 u32 mask, set;
2701
2702 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2703 & ~B43_MACCTL_GPOUTSMSK);
2704
e4d6b795
MB		 2705 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2706 | 0x000F);
2707
2708 mask = 0x0000001F;
2709 set = 0x0000000F;
c244e08c 2710 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2711 mask |= 0x0060;
2712 set |= 0x0060;
2713 }
2714 if (0 /* FIXME: conditional unknown */ ) {
2715 b43_write16(dev, B43_MMIO_GPIO_MASK,
2716 b43_read16(dev, B43_MMIO_GPIO_MASK)
2717 | 0x0100);
2718 mask |= 0x0180;
2719 set |= 0x0180;
2720 }
0581483a 2721 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2722 b43_write16(dev, B43_MMIO_GPIO_MASK,
2723 b43_read16(dev, B43_MMIO_GPIO_MASK)
2724 | 0x0200);
2725 mask |= 0x0200;
2726 set |= 0x0200;
2727 }
21d889d4 2728 if (dev->dev->core_rev >= 2)
e4d6b795
MB		 2729 mask |= 0x0010; /* FIXME: This is redundant. */
2730
6cbab0d9 2731 switch (dev->dev->bus_type) {
42c9a458
RM		 2732#ifdef CONFIG_B43_BCMA
2733 case B43_BUS_BCMA:
2734 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2735 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2736 BCMA_CC_GPIOCTL) & mask) | set);
2737 break;
2738#endif
6cbab0d9
RM		 2739#ifdef CONFIG_B43_SSB
2740 case B43_BUS_SSB:
2741 gpiodev = b43_ssb_gpio_dev(dev);
2742 if (gpiodev)
2743 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2744 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2745 & mask) | set);
2746 break;
2747#endif
2748 }
e4d6b795
MB		 2749
2750 return 0;
2751}
2752
2753/* Turn off all GPIO stuff. Call this on module unload, for example. */
2754static void b43_gpio_cleanup(struct b43_wldev *dev)
2755{
c4a2a081 2756 struct ssb_device *gpiodev;
e4d6b795 2757
6cbab0d9 2758 switch (dev->dev->bus_type) {
42c9a458
RM		 2759#ifdef CONFIG_B43_BCMA
2760 case B43_BUS_BCMA:
2761 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2762 0);
2763 break;
2764#endif
6cbab0d9
RM		 2765#ifdef CONFIG_B43_SSB
2766 case B43_BUS_SSB:
2767 gpiodev = b43_ssb_gpio_dev(dev);
2768 if (gpiodev)
2769 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2770 break;
2771#endif
2772 }
e4d6b795
MB		 2773}
2774
2775/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2776void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2777{
923fd703
MB		 2778 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2779 u16 fwstate;
2780
2781 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2782 B43_SHM_SH_UCODESTAT);
2783 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2784 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2785 b43err(dev->wl, "b43_mac_enable(): The firmware "
2786 "should be suspended, but current state is %u\n",
2787 fwstate);
2788 }
2789 }
2790
e4d6b795
MB		 2791 dev->mac_suspended--;
2792 B43_WARN_ON(dev->mac_suspended < 0);
2793 if (dev->mac_suspended == 0) {
2794 b43_write32(dev, B43_MMIO_MACCTL,
2795 b43_read32(dev, B43_MMIO_MACCTL)
2796 | B43_MACCTL_ENABLED);
2797 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2798 B43_IRQ_MAC_SUSPENDED);
2799 /* Commit writes */
2800 b43_read32(dev, B43_MMIO_MACCTL);
2801 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2802 b43_power_saving_ctl_bits(dev, 0);
2803 }
2804}
2805
2806/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2807void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2808{
2809 int i;
2810 u32 tmp;
2811
05b64b36 2812 might_sleep();
e4d6b795 2813 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2814
e4d6b795
MB		 2815 if (dev->mac_suspended == 0) {
2816 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2817 b43_write32(dev, B43_MMIO_MACCTL,
2818 b43_read32(dev, B43_MMIO_MACCTL)
2819 & ~B43_MACCTL_ENABLED);
2820 /* force pci to flush the write */
2821 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2822 for (i = 35; i; i--) {
2823 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2824 if (tmp & B43_IRQ_MAC_SUSPENDED)
2825 goto out;
2826 udelay(10);
2827 }
2828 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2829 for (i = 40; i; i--) {
e4d6b795
MB		 2830 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2831 if (tmp & B43_IRQ_MAC_SUSPENDED)
2832 goto out;
05b64b36 2833 msleep(1);
e4d6b795
MB		 2834 }
2835 b43err(dev->wl, "MAC suspend failed\n");
2836 }
05b64b36 2837out:
e4d6b795
MB		 2838 dev->mac_suspended++;
2839}
2840
858a1652
RM		 2841/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2842void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2843{
6cbab0d9
RM		 2844 u32 tmp;
2845
2846 switch (dev->dev->bus_type) {
42c9a458
RM		 2847#ifdef CONFIG_B43_BCMA
2848 case B43_BUS_BCMA:
36677874 2849 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2850 if (on)
2851 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2852 else
2853 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2854 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2855 break;
2856#endif
6cbab0d9
RM		 2857#ifdef CONFIG_B43_SSB
2858 case B43_BUS_SSB:
2859 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2860 if (on)
2861 tmp |= B43_TMSLOW_MACPHYCLKEN;
2862 else
2863 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2864 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2865 break;
2866#endif
2867 }
858a1652
RM		 2868}
2869
e4d6b795
MB		 2870static void b43_adjust_opmode(struct b43_wldev *dev)
2871{
2872 struct b43_wl *wl = dev->wl;
2873 u32 ctl;
2874 u16 cfp_pretbtt;
2875
2876 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2877 /* Reset status to STA infrastructure mode. */
2878 ctl &= ~B43_MACCTL_AP;
2879 ctl &= ~B43_MACCTL_KEEP_CTL;
2880 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2881 ctl &= ~B43_MACCTL_KEEP_BAD;
2882 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2883 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2884 ctl |= B43_MACCTL_INFRA;
2885
05c914fe
JB		 2886 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2887 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2888 ctl |= B43_MACCTL_AP;
05c914fe 2889 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2890 ctl &= ~B43_MACCTL_INFRA;
2891
2892 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2893 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2894 if (wl->filter_flags & FIF_FCSFAIL)
2895 ctl |= B43_MACCTL_KEEP_BAD;
2896 if (wl->filter_flags & FIF_PLCPFAIL)
2897 ctl |= B43_MACCTL_KEEP_BADPLCP;
2898 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2899 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2900 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2901 ctl |= B43_MACCTL_BEACPROMISC;
2902
e4d6b795
MB		 2903 /* Workaround: On old hardware the HW-MAC-address-filter
2904 * doesn't work properly, so always run promisc in filter
2905 * it in software. */
21d889d4 2906 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2907 ctl |= B43_MACCTL_PROMISC;
2908
2909 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2910
2911 cfp_pretbtt = 2;
2912 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2913 if (dev->dev->chip_id == 0x4306 &&
2914 dev->dev->chip_rev == 3)
e4d6b795
MB		 2915 cfp_pretbtt = 100;
2916 else
2917 cfp_pretbtt = 50;
2918 }
2919 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2920
2921 /* FIXME: We don't currently implement the PMQ mechanism,
2922 * so always disable it. If we want to implement PMQ,
2923 * we need to enable it here (clear DISCPMQ) in AP mode.
2924 */
2925 if (0 /* ctl & B43_MACCTL_AP */) {
2926 b43_write32(dev, B43_MMIO_MACCTL,
2927 b43_read32(dev, B43_MMIO_MACCTL)
2928 & ~B43_MACCTL_DISCPMQ);
2929 } else {
2930 b43_write32(dev, B43_MMIO_MACCTL,
2931 b43_read32(dev, B43_MMIO_MACCTL)
2932 | B43_MACCTL_DISCPMQ);
2933 }
e4d6b795
MB		 2934}
2935
2936static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2937{
2938 u16 offset;
2939
2940 if (is_ofdm) {
2941 offset = 0x480;
2942 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2943 } else {
2944 offset = 0x4C0;
2945 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2946 }
2947 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2948 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2949}
2950
2951static void b43_rate_memory_init(struct b43_wldev *dev)
2952{
2953 switch (dev->phy.type) {
2954 case B43_PHYTYPE_A:
2955 case B43_PHYTYPE_G:
53a6e234 2956 case B43_PHYTYPE_N:
9d86a2d5 2957 case B43_PHYTYPE_LP:
6a461c23 2958 case B43_PHYTYPE_HT:
0b4ff45d 2959 case B43_PHYTYPE_LCN:
e4d6b795
MB		 2960 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2961 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2962 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2963 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2967 if (dev->phy.type == B43_PHYTYPE_A)
2968 break;
2969 /* fallthrough */
2970 case B43_PHYTYPE_B:
2971 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2972 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2973 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2974 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2975 break;
2976 default:
2977 B43_WARN_ON(1);
2978 }
2979}
2980
5042c507
MB		 2981/* Set the default values for the PHY TX Control Words. */
2982static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2983{
2984 u16 ctl = 0;
2985
2986 ctl |= B43_TXH_PHY_ENC_CCK;
2987 ctl |= B43_TXH_PHY_ANT01AUTO;
2988 ctl |= B43_TXH_PHY_TXPWR;
2989
2990 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2991 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2992 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2993}
2994
e4d6b795
MB		 2995/* Set the TX-Antenna for management frames sent by firmware. */
2996static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2997{
5042c507 2998 u16 ant;
e4d6b795
MB		 2999 u16 tmp;
3000
5042c507 3001 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3002
e4d6b795
MB		 3003 /* For ACK/CTS */
3004 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3005 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3006 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3007 /* For Probe Resposes */
3008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3009 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3011}
3012
3013/* This is the opposite of b43_chip_init() */
3014static void b43_chip_exit(struct b43_wldev *dev)
3015{
fb11137a 3016 b43_phy_exit(dev);
e4d6b795
MB		 3017 b43_gpio_cleanup(dev);
3018 /* firmware is released later */
3019}
3020
3021/* Initialize the chip
3022 * http://bcm-specs.sipsolutions.net/ChipInit
3023 */
3024static int b43_chip_init(struct b43_wldev *dev)
3025{
3026 struct b43_phy *phy = &dev->phy;
ef1a628d 3027 int err;
858a1652 3028 u32 macctl;
e4d6b795
MB		 3029 u16 value16;
3030
1f7d87b0
MB		 3031 /* Initialize the MAC control */
3032 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3033 if (dev->phy.gmode)
3034 macctl |= B43_MACCTL_GMODE;
3035 macctl |= B43_MACCTL_INFRA;
3036 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 3037
3038 err = b43_request_firmware(dev);
3039 if (err)
3040 goto out;
3041 err = b43_upload_microcode(dev);
3042 if (err)
3043 goto out; /* firmware is released later */
3044
3045 err = b43_gpio_init(dev);
3046 if (err)
3047 goto out; /* firmware is released later */
21954c36 3048
e4d6b795
MB		 3049 err = b43_upload_initvals(dev);
3050 if (err)
1a8d1227 3051 goto err_gpio_clean;
e4d6b795 3052
0b7dcd96
MB		 3053 /* Turn the Analog on and initialize the PHY. */
3054 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3055 err = b43_phy_init(dev);
3056 if (err)
ef1a628d 3057 goto err_gpio_clean;
e4d6b795 3058
ef1a628d
MB		 3059 /* Disable Interference Mitigation. */
3060 if (phy->ops->interf_mitigation)
3061 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3062
ef1a628d
MB		 3063 /* Select the antennae */
3064 if (phy->ops->set_rx_antenna)
3065 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3066 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3067
3068 if (phy->type == B43_PHYTYPE_B) {
3069 value16 = b43_read16(dev, 0x005E);
3070 value16 |= 0x0004;
3071 b43_write16(dev, 0x005E, value16);
3072 }
3073 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3074 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3075 b43_write32(dev, 0x010C, 0x01000000);
3076
3077 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3078 & ~B43_MACCTL_INFRA);
3079 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3080 | B43_MACCTL_INFRA);
e4d6b795 3081
e4d6b795
MB		 3082 /* Probe Response Timeout value */
3083 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3084 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3085
3086 /* Initially set the wireless operation mode. */
3087 b43_adjust_opmode(dev);
3088
21d889d4 3089 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3090 b43_write16(dev, 0x060E, 0x0000);
3091 b43_write16(dev, 0x0610, 0x8000);
3092 b43_write16(dev, 0x0604, 0x0000);
3093 b43_write16(dev, 0x0606, 0x0200);
3094 } else {
3095 b43_write32(dev, 0x0188, 0x80000000);
3096 b43_write32(dev, 0x018C, 0x02000000);
3097 }
3098 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3099 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3100 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3102 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3103 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3104 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3105
858a1652 3106 b43_mac_phy_clock_set(dev, true);
e4d6b795 3107
6cbab0d9 3108 switch (dev->dev->bus_type) {
42c9a458
RM		 3109#ifdef CONFIG_B43_BCMA
3110 case B43_BUS_BCMA:
3111 /* FIXME: 0xE74 is quite common, but should be read from CC */
3112 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3113 break;
3114#endif
6cbab0d9
RM		 3115#ifdef CONFIG_B43_SSB
3116 case B43_BUS_SSB:
3117 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3118 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3119 break;
3120#endif
3121 }
e4d6b795
MB		 3122
3123 err = 0;
3124 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3125out:
e4d6b795
MB		 3126 return err;
3127
1a8d1227 3128err_gpio_clean:
e4d6b795 3129 b43_gpio_cleanup(dev);
21954c36 3130 return err;
e4d6b795
MB		 3131}
3132
e4d6b795
MB		 3133static void b43_periodic_every60sec(struct b43_wldev *dev)
3134{
ef1a628d 3135 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3136
ef1a628d
MB		 3137 if (ops->pwork_60sec)
3138 ops->pwork_60sec(dev);
18c8adeb
MB		 3139
3140 /* Force check the TX power emission now. */
3141 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3142}
3143
3144static void b43_periodic_every30sec(struct b43_wldev *dev)
3145{
3146 /* Update device statistics. */
3147 b43_calculate_link_quality(dev);
3148}
3149
3150static void b43_periodic_every15sec(struct b43_wldev *dev)
3151{
3152 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3153 u16 wdr;
3154
3155 if (dev->fw.opensource) {
3156 /* Check if the firmware is still alive.
3157 * It will reset the watchdog counter to 0 in its idle loop. */
3158 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3159 if (unlikely(wdr)) {
3160 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3161 b43_controller_restart(dev, "Firmware watchdog");
3162 return;
3163 } else {
3164 b43_shm_write16(dev, B43_SHM_SCRATCH,
3165 B43_WATCHDOG_REG, 1);
3166 }
3167 }
e4d6b795 3168
ef1a628d
MB		 3169 if (phy->ops->pwork_15sec)
3170 phy->ops->pwork_15sec(dev);
3171
00e0b8cb
SB		 3172 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3173 wmb();
990b86f4
MB		 3174
3175#if B43_DEBUG
3176 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3177 unsigned int i;
3178
3179 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3180 dev->irq_count / 15,
3181 dev->tx_count / 15,
3182 dev->rx_count / 15);
3183 dev->irq_count = 0;
3184 dev->tx_count = 0;
3185 dev->rx_count = 0;
3186 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3187 if (dev->irq_bit_count[i]) {
3188 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3189 dev->irq_bit_count[i] / 15, i, (1 << i));
3190 dev->irq_bit_count[i] = 0;
3191 }
3192 }
3193 }
3194#endif
e4d6b795
MB		 3195}
3196
e4d6b795
MB		 3197static void do_periodic_work(struct b43_wldev *dev)
3198{
3199 unsigned int state;
3200
3201 state = dev->periodic_state;
42bb4cd5 3202 if (state % 4 == 0)
e4d6b795 3203 b43_periodic_every60sec(dev);
42bb4cd5 3204 if (state % 2 == 0)
e4d6b795 3205 b43_periodic_every30sec(dev);
42bb4cd5 3206 b43_periodic_every15sec(dev);
e4d6b795
MB		 3207}
3208
05b64b36
MB		 3209/* Periodic work locking policy:
3210 * The whole periodic work handler is protected by
3211 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3212 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3213 */
e4d6b795
MB		 3214static void b43_periodic_work_handler(struct work_struct *work)
3215{
05b64b36
MB		 3216 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3217 periodic_work.work);
3218 struct b43_wl *wl = dev->wl;
3219 unsigned long delay;
e4d6b795 3220
05b64b36 3221 mutex_lock(&wl->mutex);
e4d6b795
MB		 3222
3223 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3224 goto out;
3225 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3226 goto out_requeue;
3227
05b64b36 3228 do_periodic_work(dev);
e4d6b795 3229
e4d6b795 3230 dev->periodic_state++;
42bb4cd5 3231out_requeue:
e4d6b795
MB		 3232 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3233 delay = msecs_to_jiffies(50);
3234 else
82cd682d 3235 delay = round_jiffies_relative(HZ * 15);
42935eca 3236 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3237out:
05b64b36 3238 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3239}
3240
3241static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3242{
3243 struct delayed_work *work = &dev->periodic_work;
3244
3245 dev->periodic_state = 0;
3246 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3247 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3248}
3249
f3dd3fcc 3250/* Check if communication with the device works correctly. */
e4d6b795
MB		 3251static int b43_validate_chipaccess(struct b43_wldev *dev)
3252{
f62ae6cd 3253 u32 v, backup0, backup4;
e4d6b795 3254
f62ae6cd
MB		 3255 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3256 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3257
3258 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3259 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3260 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3261 goto error;
f3dd3fcc
MB		 3262 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3263 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3264 goto error;
3265
f62ae6cd
MB		 3266 /* Check if unaligned 32bit SHM_SHARED access works properly.
3267 * However, don't bail out on failure, because it's noncritical. */
3268 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3269 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3270 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3271 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3272 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3273 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3274 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3275 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3276 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3277 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3278 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3279 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3280
3281 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3282 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3283
21d889d4 3284 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3285 /* The 32bit register shadows the two 16bit registers
3286 * with update sideeffects. Validate this. */
3287 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3288 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3289 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3290 goto error;
3291 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3292 goto error;
3293 }
3294 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3295
3296 v = b43_read32(dev, B43_MMIO_MACCTL);
3297 v |= B43_MACCTL_GMODE;
3298 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3299 goto error;
3300
3301 return 0;
f3dd3fcc 3302error:
e4d6b795
MB		 3303 b43err(dev->wl, "Failed to validate the chipaccess\n");
3304 return -ENODEV;
3305}
3306
3307static void b43_security_init(struct b43_wldev *dev)
3308{
e4d6b795
MB		 3309 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3310 /* KTP is a word address, but we address SHM bytewise.
3311 * So multiply by two.
3312 */
3313 dev->ktp *= 2;
66d2d089
MB		 3314 /* Number of RCMTA address slots */
3315 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3316 /* Clear the key memory. */
e4d6b795
MB		 3317 b43_clear_keys(dev);
3318}
3319
616de35d 3320#ifdef CONFIG_B43_HWRNG
99da185a 3321static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3322{
3323 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3324 struct b43_wldev *dev;
3325 int count = -ENODEV;
e4d6b795 3326
a78b3bb2
MB		 3327 mutex_lock(&wl->mutex);
3328 dev = wl->current_dev;
3329 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3330 *data = b43_read16(dev, B43_MMIO_RNG);
3331 count = sizeof(u16);
3332 }
3333 mutex_unlock(&wl->mutex);
e4d6b795 3334
a78b3bb2 3335 return count;
e4d6b795 3336}
616de35d 3337#endif /* CONFIG_B43_HWRNG */
e4d6b795 3338
b844eba2 3339static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3340{
616de35d 3341#ifdef CONFIG_B43_HWRNG
e4d6b795 3342 if (wl->rng_initialized)
b844eba2 3343 hwrng_unregister(&wl->rng);
616de35d 3344#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3345}
3346
3347static int b43_rng_init(struct b43_wl *wl)
3348{
616de35d 3349 int err = 0;
e4d6b795 3350
616de35d 3351#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3352 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3353 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3354 wl->rng.name = wl->rng_name;
3355 wl->rng.data_read = b43_rng_read;
3356 wl->rng.priv = (unsigned long)wl;
3357 wl->rng_initialized = 1;
3358 err = hwrng_register(&wl->rng);
3359 if (err) {
3360 wl->rng_initialized = 0;
3361 b43err(wl, "Failed to register the random "
3362 "number generator (%d)\n", err);
3363 }
616de35d 3364#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3365
3366 return err;
3367}
3368
f5d40eed 3369static void b43_tx_work(struct work_struct *work)
e4d6b795 3370{
f5d40eed
MB		 3371 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3372 struct b43_wldev *dev;
3373 struct sk_buff *skb;
3374 int err = 0;
e4d6b795 3375
f5d40eed
MB		 3376 mutex_lock(&wl->mutex);
3377 dev = wl->current_dev;
3378 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3379 mutex_unlock(&wl->mutex);
3380 return;
5100d5ac 3381 }
21a75d77 3382
f5d40eed
MB		 3383 while (skb_queue_len(&wl->tx_queue)) {
3384 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3385
21a75d77 3386 if (b43_using_pio_transfers(dev))
e039fa4a 3387 err = b43_pio_tx(dev, skb);
21a75d77 3388 else
e039fa4a 3389 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3390 if (unlikely(err))
3391 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3392 }
3393
990b86f4
MB		 3394#if B43_DEBUG
3395 dev->tx_count++;
3396#endif
f5d40eed
MB		 3397 mutex_unlock(&wl->mutex);
3398}
21a75d77 3399
7bb45683 3400static void b43_op_tx(struct ieee80211_hw *hw,
f5d40eed
MB		 3401 struct sk_buff *skb)
3402{
3403 struct b43_wl *wl = hw_to_b43_wl(hw);
3404
3405 if (unlikely(skb->len < 2 + 2 + 6)) {
3406 /* Too short, this can't be a valid frame. */
3407 dev_kfree_skb_any(skb);
7bb45683 3408 return;
f5d40eed
MB		 3409 }
3410 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3411
3412 skb_queue_tail(&wl->tx_queue, skb);
3413 ieee80211_queue_work(wl->hw, &wl->tx_work);
e4d6b795
MB		 3414}
3415
e6f5b934
MB		 3416static void b43_qos_params_upload(struct b43_wldev *dev,
3417 const struct ieee80211_tx_queue_params *p,
3418 u16 shm_offset)
3419{
3420 u16 params[B43_NR_QOSPARAMS];
0b57664c 3421 int bslots, tmp;
e6f5b934
MB		 3422 unsigned int i;
3423
b0544eb6
MB		 3424 if (!dev->qos_enabled)
3425 return;
3426
0b57664c 3427 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3428
3429 memset(&params, 0, sizeof(params));
3430
3431 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3432 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3433 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3434 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3435 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3436 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3437 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3438
3439 for (i = 0; i < ARRAY_SIZE(params); i++) {
3440 if (i == B43_QOSPARAM_STATUS) {
3441 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3442 shm_offset + (i * 2));
3443 /* Mark the parameters as updated. */
3444 tmp |= 0x100;
3445 b43_shm_write16(dev, B43_SHM_SHARED,
3446 shm_offset + (i * 2),
3447 tmp);
3448 } else {
3449 b43_shm_write16(dev, B43_SHM_SHARED,
3450 shm_offset + (i * 2),
3451 params[i]);
3452 }
3453 }
3454}
3455
c40c1129
MB		 3456/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3457static const u16 b43_qos_shm_offsets[] = {
3458 /* [mac80211-queue-nr] = SHM_OFFSET, */
3459 [0] = B43_QOS_VOICE,
3460 [1] = B43_QOS_VIDEO,
3461 [2] = B43_QOS_BESTEFFORT,
3462 [3] = B43_QOS_BACKGROUND,
3463};
3464
5a5f3b40
MB		 3465/* Update all QOS parameters in hardware. */
3466static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3467{
3468 struct b43_wl *wl = dev->wl;
3469 struct b43_qos_params *params;
e6f5b934
MB		 3470 unsigned int i;
3471
b0544eb6
MB		 3472 if (!dev->qos_enabled)
3473 return;
3474
c40c1129
MB		 3475 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3476 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3477
3478 b43_mac_suspend(dev);
e6f5b934
MB		 3479 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3480 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3481 b43_qos_params_upload(dev, &(params->p),
3482 b43_qos_shm_offsets[i]);
e6f5b934 3483 }
e6f5b934
MB		 3484 b43_mac_enable(dev);
3485}
3486
3487static void b43_qos_clear(struct b43_wl *wl)
3488{
3489 struct b43_qos_params *params;
3490 unsigned int i;
3491
c40c1129
MB		 3492 /* Initialize QoS parameters to sane defaults. */
3493
3494 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3495 ARRAY_SIZE(wl->qos_params));
3496
e6f5b934
MB		 3497 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3498 params = &(wl->qos_params[i]);
3499
c40c1129
MB		 3500 switch (b43_qos_shm_offsets[i]) {
3501 case B43_QOS_VOICE:
3502 params->p.txop = 0;
3503 params->p.aifs = 2;
3504 params->p.cw_min = 0x0001;
3505 params->p.cw_max = 0x0001;
3506 break;
3507 case B43_QOS_VIDEO:
3508 params->p.txop = 0;
3509 params->p.aifs = 2;
3510 params->p.cw_min = 0x0001;
3511 params->p.cw_max = 0x0001;
3512 break;
3513 case B43_QOS_BESTEFFORT:
3514 params->p.txop = 0;
3515 params->p.aifs = 3;
3516 params->p.cw_min = 0x0001;
3517 params->p.cw_max = 0x03FF;
3518 break;
3519 case B43_QOS_BACKGROUND:
3520 params->p.txop = 0;
3521 params->p.aifs = 7;
3522 params->p.cw_min = 0x0001;
3523 params->p.cw_max = 0x03FF;
3524 break;
3525 default:
3526 B43_WARN_ON(1);
3527 }
e6f5b934
MB		 3528 }
3529}
3530
3531/* Initialize the core's QOS capabilities */
3532static void b43_qos_init(struct b43_wldev *dev)
3533{
b0544eb6
MB		 3534 if (!dev->qos_enabled) {
3535 /* Disable QOS support. */
3536 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3537 b43_write16(dev, B43_MMIO_IFSCTL,
3538 b43_read16(dev, B43_MMIO_IFSCTL)
3539 & ~B43_MMIO_IFSCTL_USE_EDCF);
3540 b43dbg(dev->wl, "QoS disabled\n");
3541 return;
3542 }
3543
e6f5b934 3544 /* Upload the current QOS parameters. */
5a5f3b40 3545 b43_qos_upload_all(dev);
e6f5b934
MB		 3546
3547 /* Enable QOS support. */
3548 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3549 b43_write16(dev, B43_MMIO_IFSCTL,
3550 b43_read16(dev, B43_MMIO_IFSCTL)
3551 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3552 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3553}
3554
e100bb64 3555static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3556 const struct ieee80211_tx_queue_params *params)
e4d6b795 3557{
e6f5b934 3558 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3559 struct b43_wldev *dev;
e6f5b934 3560 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3561 int err = -ENODEV;
e6f5b934
MB		 3562
3563 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3564 /* Queue not available or don't support setting
3565 * params on this queue. Return success to not
3566 * confuse mac80211. */
3567 return 0;
3568 }
5a5f3b40
MB		 3569 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3570 ARRAY_SIZE(wl->qos_params));
e6f5b934 3571
5a5f3b40
MB		 3572 mutex_lock(&wl->mutex);
3573 dev = wl->current_dev;
3574 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3575 goto out_unlock;
e6f5b934 3576
5a5f3b40
MB		 3577 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3578 b43_mac_suspend(dev);
3579 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3580 b43_qos_shm_offsets[queue]);
3581 b43_mac_enable(dev);
3582 err = 0;
e6f5b934 3583
5a5f3b40
MB		 3584out_unlock:
3585 mutex_unlock(&wl->mutex);
3586
3587 return err;
e4d6b795
MB		 3588}
3589
40faacc4
MB		 3590static int b43_op_get_stats(struct ieee80211_hw *hw,
3591 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3592{
3593 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3594
36dbd954 3595 mutex_lock(&wl->mutex);
e4d6b795 3596 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3597 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3598
3599 return 0;
3600}
3601
37a41b4a 3602static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3603{
3604 struct b43_wl *wl = hw_to_b43_wl(hw);
3605 struct b43_wldev *dev;
3606 u64 tsf;
3607
3608 mutex_lock(&wl->mutex);
08e87a83
AF		 3609 dev = wl->current_dev;
3610
3611 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3612 b43_tsf_read(dev, &tsf);
3613 else
3614 tsf = 0;
3615
08e87a83
AF		 3616 mutex_unlock(&wl->mutex);
3617
3618 return tsf;
3619}
3620
37a41b4a
EP		 3621static void b43_op_set_tsf(struct ieee80211_hw *hw,
3622 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3623{
3624 struct b43_wl *wl = hw_to_b43_wl(hw);
3625 struct b43_wldev *dev;
3626
3627 mutex_lock(&wl->mutex);
08e87a83
AF		 3628 dev = wl->current_dev;
3629
3630 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3631 b43_tsf_write(dev, tsf);
3632
08e87a83
AF		 3633 mutex_unlock(&wl->mutex);
3634}
3635
e4d6b795
MB		 3636static void b43_put_phy_into_reset(struct b43_wldev *dev)
3637{
6cbab0d9 3638 u32 tmp;
e4d6b795 3639
6cbab0d9 3640 switch (dev->dev->bus_type) {
42c9a458
RM		 3641#ifdef CONFIG_B43_BCMA
3642 case B43_BUS_BCMA:
3643 b43err(dev->wl,
3644 "Putting PHY into reset not supported on BCMA\n");
3645 break;
3646#endif
6cbab0d9
RM		 3647#ifdef CONFIG_B43_SSB
3648 case B43_BUS_SSB:
3649 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3650 tmp &= ~B43_TMSLOW_GMODE;
3651 tmp |= B43_TMSLOW_PHYRESET;
3652 tmp |= SSB_TMSLOW_FGC;
3653 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3654 msleep(1);
3655
3656 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3657 tmp &= ~SSB_TMSLOW_FGC;
3658 tmp |= B43_TMSLOW_PHYRESET;
3659 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3660 msleep(1);
e4d6b795 3661
6cbab0d9
RM		 3662 break;
3663#endif
3664 }
e4d6b795
MB		 3665}
3666
99da185a 3667static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3668{
3669 switch (band) {
3670 case IEEE80211_BAND_5GHZ:
3671 return "5";
3672 case IEEE80211_BAND_2GHZ:
3673 return "2.4";
3674 default:
3675 break;
3676 }
3677 B43_WARN_ON(1);
3678 return "";
3679}
3680
e4d6b795 3681/* Expects wl->mutex locked */
bb1eeff1 3682static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3683{
bb1eeff1 3684 struct b43_wldev *up_dev = NULL;
e4d6b795 3685 struct b43_wldev *down_dev;
bb1eeff1 3686 struct b43_wldev *d;
e4d6b795 3687 int err;
922d8a0b 3688 bool uninitialized_var(gmode);
e4d6b795
MB		 3689 int prev_status;
3690
bb1eeff1
MB		 3691 /* Find a device and PHY which supports the band. */
3692 list_for_each_entry(d, &wl->devlist, list) {
3693 switch (chan->band) {
3694 case IEEE80211_BAND_5GHZ:
3695 if (d->phy.supports_5ghz) {
3696 up_dev = d;
3697 gmode = 0;
3698 }
3699 break;
3700 case IEEE80211_BAND_2GHZ:
3701 if (d->phy.supports_2ghz) {
3702 up_dev = d;
3703 gmode = 1;
3704 }
3705 break;
3706 default:
3707 B43_WARN_ON(1);
3708 return -EINVAL;
3709 }
3710 if (up_dev)
3711 break;
3712 }
3713 if (!up_dev) {
3714 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3715 band_to_string(chan->band));
3716 return -ENODEV;
e4d6b795
MB		 3717 }
3718 if ((up_dev == wl->current_dev) &&
3719 (!!wl->current_dev->phy.gmode == !!gmode)) {
3720 /* This device is already running. */
3721 return 0;
3722 }
bb1eeff1
MB		 3723 b43dbg(wl, "Switching to %s-GHz band\n",
3724 band_to_string(chan->band));
e4d6b795
MB		 3725 down_dev = wl->current_dev;
3726
3727 prev_status = b43_status(down_dev);
3728 /* Shutdown the currently running core. */
3729 if (prev_status >= B43_STAT_STARTED)
36dbd954 3730 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3731 if (prev_status >= B43_STAT_INITIALIZED)
3732 b43_wireless_core_exit(down_dev);
3733
3734 if (down_dev != up_dev) {
3735 /* We switch to a different core, so we put PHY into
3736 * RESET on the old core. */
3737 b43_put_phy_into_reset(down_dev);
3738 }
3739
3740 /* Now start the new core. */
3741 up_dev->phy.gmode = gmode;
3742 if (prev_status >= B43_STAT_INITIALIZED) {
3743 err = b43_wireless_core_init(up_dev);
3744 if (err) {
3745 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3746 "selected %s-GHz band\n",
3747 band_to_string(chan->band));
e4d6b795
MB		 3748 goto init_failure;
3749 }
3750 }
3751 if (prev_status >= B43_STAT_STARTED) {
3752 err = b43_wireless_core_start(up_dev);
3753 if (err) {
3754 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3755 "selected %s-GHz band\n",
3756 band_to_string(chan->band));
e4d6b795
MB		 3757 b43_wireless_core_exit(up_dev);
3758 goto init_failure;
3759 }
3760 }
3761 B43_WARN_ON(b43_status(up_dev) != prev_status);
3762
3763 wl->current_dev = up_dev;
3764
3765 return 0;
bb1eeff1 3766init_failure:
e4d6b795
MB		 3767 /* Whoops, failed to init the new core. No core is operating now. */
3768 wl->current_dev = NULL;
3769 return err;
3770}
3771
9124b077
JB		 3772/* Write the short and long frame retry limit values. */
3773static void b43_set_retry_limits(struct b43_wldev *dev,
3774 unsigned int short_retry,
3775 unsigned int long_retry)
3776{
3777 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3778 * the chip-internal counter. */
3779 short_retry = min(short_retry, (unsigned int)0xF);
3780 long_retry = min(long_retry, (unsigned int)0xF);
3781
3782 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3783 short_retry);
3784 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3785 long_retry);
3786}
3787
e8975581 3788static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3789{
3790 struct b43_wl *wl = hw_to_b43_wl(hw);
3791 struct b43_wldev *dev;
3792 struct b43_phy *phy;
e8975581 3793 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3794 int antenna;
e4d6b795 3795 int err = 0;
2a190322 3796 bool reload_bss = false;
e4d6b795 3797
e4d6b795
MB		 3798 mutex_lock(&wl->mutex);
3799
2a190322
FF		 3800 dev = wl->current_dev;
3801
bb1eeff1
MB		 3802 /* Switch the band (if necessary). This might change the active core. */
3803 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3804 if (err)
3805 goto out_unlock_mutex;
2a190322
FF		 3806
3807 /* Need to reload all settings if the core changed */
3808 if (dev != wl->current_dev) {
3809 dev = wl->current_dev;
3810 changed = ~0;
3811 reload_bss = true;
3812 }
3813
e4d6b795
MB		 3814 phy = &dev->phy;
3815
aa4c7b2a
RM		 3816 if (conf_is_ht(conf))
3817 phy->is_40mhz =
3818 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3819 else
3820 phy->is_40mhz = false;
3821
d10d0e57
MB		 3822 b43_mac_suspend(dev);
3823
9124b077
JB		 3824 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3825 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3826 conf->long_frame_max_tx_count);
3827 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3828 if (!changed)
d10d0e57 3829 goto out_mac_enable;
e4d6b795
MB		 3830
3831 /* Switch to the requested channel.
3832 * The firmware takes care of races with the TX handler. */
8318d78a 3833 if (conf->channel->hw_value != phy->channel)
ef1a628d 3834 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3835
0869aea0 3836 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3837
e4d6b795
MB		 3838 /* Adjust the desired TX power level. */
3839 if (conf->power_level != 0) {
18c8adeb
MB		 3840 if (conf->power_level != phy->desired_txpower) {
3841 phy->desired_txpower = conf->power_level;
3842 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3843 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3844 }
3845 }
3846
3847 /* Antennas for RX and management frame TX. */
0f4ac38b 3848 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3849 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3850 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3851 if (phy->ops->set_rx_antenna)
3852 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3853
fd4973c5
LF		 3854 if (wl->radio_enabled != phy->radio_on) {
3855 if (wl->radio_enabled) {
19d337df 3856 b43_software_rfkill(dev, false);
fda9abcf
MB		 3857 b43info(dev->wl, "Radio turned on by software\n");
3858 if (!dev->radio_hw_enable) {
3859 b43info(dev->wl, "The hardware RF-kill button "
3860 "still turns the radio physically off. "
3861 "Press the button to turn it on.\n");
3862 }
3863 } else {
19d337df 3864 b43_software_rfkill(dev, true);
fda9abcf
MB		 3865 b43info(dev->wl, "Radio turned off by software\n");
3866 }
3867 }
3868
d10d0e57
MB		 3869out_mac_enable:
3870 b43_mac_enable(dev);
3871out_unlock_mutex:
e4d6b795
MB		 3872 mutex_unlock(&wl->mutex);
3873
2a190322
FF		 3874 if (wl->vif && reload_bss)
3875 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3876
e4d6b795
MB		 3877 return err;
3878}
3879
881d948c 3880static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3881{
3882 struct ieee80211_supported_band *sband =
3883 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3884 struct ieee80211_rate *rate;
3885 int i;
3886 u16 basic, direct, offset, basic_offset, rateptr;
3887
3888 for (i = 0; i < sband->n_bitrates; i++) {
3889 rate = &sband->bitrates[i];
3890
3891 if (b43_is_cck_rate(rate->hw_value)) {
3892 direct = B43_SHM_SH_CCKDIRECT;
3893 basic = B43_SHM_SH_CCKBASIC;
3894 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3895 offset &= 0xF;
3896 } else {
3897 direct = B43_SHM_SH_OFDMDIRECT;
3898 basic = B43_SHM_SH_OFDMBASIC;
3899 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3900 offset &= 0xF;
3901 }
3902
3903 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3904
3905 if (b43_is_cck_rate(rate->hw_value)) {
3906 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3907 basic_offset &= 0xF;
3908 } else {
3909 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3910 basic_offset &= 0xF;
3911 }
3912
3913 /*
3914 * Get the pointer that we need to point to
3915 * from the direct map
3916 */
3917 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3918 direct + 2 * basic_offset);
3919 /* and write it to the basic map */
3920 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3921 rateptr);
3922 }
3923}
3924
3925static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3926 struct ieee80211_vif *vif,
3927 struct ieee80211_bss_conf *conf,
3928 u32 changed)
3929{
3930 struct b43_wl *wl = hw_to_b43_wl(hw);
3931 struct b43_wldev *dev;
c7ab5ef9
JB		 3932
3933 mutex_lock(&wl->mutex);
3934
3935 dev = wl->current_dev;
d10d0e57 3936 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3937 goto out_unlock_mutex;
2d0ddec5
JB		 3938
3939 B43_WARN_ON(wl->vif != vif);
3940
3941 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3942 if (conf->bssid)
3943 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3944 else
3945 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3946 }
2d0ddec5 3947
3f0d843b
JB		 3948 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3949 if (changed & BSS_CHANGED_BEACON &&
3950 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3951 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3952 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3953 b43_update_templates(wl);
3954
3955 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3956 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3957 }
3958
c7ab5ef9
JB		 3959 b43_mac_suspend(dev);
3960
57c4d7b4
JB		 3961 /* Update templates for AP/mesh mode. */
3962 if (changed & BSS_CHANGED_BEACON_INT &&
3963 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3964 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3965 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3966 conf->beacon_int)
57c4d7b4
JB		 3967 b43_set_beacon_int(dev, conf->beacon_int);
3968
c7ab5ef9
JB		 3969 if (changed & BSS_CHANGED_BASIC_RATES)
3970 b43_update_basic_rates(dev, conf->basic_rates);
3971
3972 if (changed & BSS_CHANGED_ERP_SLOT) {
3973 if (conf->use_short_slot)
3974 b43_short_slot_timing_enable(dev);
3975 else
3976 b43_short_slot_timing_disable(dev);
3977 }
3978
3979 b43_mac_enable(dev);
d10d0e57 3980out_unlock_mutex:
c7ab5ef9 3981 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3982}
3983
40faacc4 3984static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3985 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3986 struct ieee80211_key_conf *key)
e4d6b795
MB		 3987{
3988 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3989 struct b43_wldev *dev;
e4d6b795
MB		 3990 u8 algorithm;
3991 u8 index;
c6dfc9a8 3992 int err;
060210f9 3993 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3994
3995 if (modparam_nohwcrypt)
3996 return -ENOSPC; /* User disabled HW-crypto */
3997
c6dfc9a8 3998 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3999
4000 dev = wl->current_dev;
4001 err = -ENODEV;
4002 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4003 goto out_unlock;
4004
403a3a13 4005 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4006 /* We don't have firmware for the crypto engine.
4007 * Must use software-crypto. */
4008 err = -EOPNOTSUPP;
4009 goto out_unlock;
4010 }
4011
c6dfc9a8 4012 err = -EINVAL;
97359d12
JB		 4013 switch (key->cipher) {
4014 case WLAN_CIPHER_SUITE_WEP40:
4015 algorithm = B43_SEC_ALGO_WEP40;
4016 break;
4017 case WLAN_CIPHER_SUITE_WEP104:
4018 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4019 break;
97359d12 4020 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4021 algorithm = B43_SEC_ALGO_TKIP;
4022 break;
97359d12 4023 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4024 algorithm = B43_SEC_ALGO_AES;
4025 break;
4026 default:
4027 B43_WARN_ON(1);
c6dfc9a8 4028 goto out_unlock;
e4d6b795 4029 }
e4d6b795
MB		 4030 index = (u8) (key->keyidx);
4031 if (index > 3)
e4d6b795 4032 goto out_unlock;
e4d6b795
MB		 4033
4034 switch (cmd) {
4035 case SET_KEY:
035d0243 4036 if (algorithm == B43_SEC_ALGO_TKIP &&
4037 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4038 !modparam_hwtkip)) {
4039 /* We support only pairwise key */
e4d6b795
MB		 4040 err = -EOPNOTSUPP;
4041 goto out_unlock;
4042 }
4043
e808e586 4044 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4045 if (WARN_ON(!sta)) {
4046 err = -EOPNOTSUPP;
4047 goto out_unlock;
4048 }
e808e586 4049 /* Pairwise key with an assigned MAC address. */
e4d6b795 4050 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4051 key->key, key->keylen,
4052 sta->addr, key);
e808e586
MB		 4053 } else {
4054 /* Group key */
4055 err = b43_key_write(dev, index, algorithm,
4056 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4057 }
4058 if (err)
4059 goto out_unlock;
4060
4061 if (algorithm == B43_SEC_ALGO_WEP40 ||
4062 algorithm == B43_SEC_ALGO_WEP104) {
4063 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4064 } else {
4065 b43_hf_write(dev,
4066 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4067 }
4068 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4069 if (algorithm == B43_SEC_ALGO_TKIP)
4070 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4071 break;
4072 case DISABLE_KEY: {
4073 err = b43_key_clear(dev, key->hw_key_idx);
4074 if (err)
4075 goto out_unlock;
4076 break;
4077 }
4078 default:
4079 B43_WARN_ON(1);
4080 }
9cf7f247 4081
e4d6b795 4082out_unlock:
e4d6b795
MB		 4083 if (!err) {
4084 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4085 "mac: %pM\n",
e4d6b795 4086 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4087 sta ? sta->addr : bcast_addr);
9cf7f247 4088 b43_dump_keymemory(dev);
e4d6b795 4089 }
9cf7f247
MB		 4090 mutex_unlock(&wl->mutex);
4091
e4d6b795
MB		 4092 return err;
4093}
4094
40faacc4
MB		 4095static void b43_op_configure_filter(struct ieee80211_hw *hw,
4096 unsigned int changed, unsigned int *fflags,
3ac64bee 4097 u64 multicast)
e4d6b795
MB		 4098{
4099 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4100 struct b43_wldev *dev;
e4d6b795 4101
36dbd954
MB		 4102 mutex_lock(&wl->mutex);
4103 dev = wl->current_dev;
4150c572
JB		 4104 if (!dev) {
4105 *fflags = 0;
36dbd954 4106 goto out_unlock;
e4d6b795 4107 }
4150c572 4108
4150c572
JB		 4109 *fflags &= FIF_PROMISC_IN_BSS |
4110 FIF_ALLMULTI |
4111 FIF_FCSFAIL |
4112 FIF_PLCPFAIL |
4113 FIF_CONTROL |
4114 FIF_OTHER_BSS |
4115 FIF_BCN_PRBRESP_PROMISC;
4116
4117 changed &= FIF_PROMISC_IN_BSS |
4118 FIF_ALLMULTI |
4119 FIF_FCSFAIL |
4120 FIF_PLCPFAIL |
4121 FIF_CONTROL |
4122 FIF_OTHER_BSS |
4123 FIF_BCN_PRBRESP_PROMISC;
4124
4125 wl->filter_flags = *fflags;
4126
4127 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4128 b43_adjust_opmode(dev);
36dbd954
MB		 4129
4130out_unlock:
4131 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4132}
4133
36dbd954
MB		 4134/* Locking: wl->mutex
4135 * Returns the current dev. This might be different from the passed in dev,
4136 * because the core might be gone away while we unlocked the mutex. */
4137static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4138{
9a53bf54 4139 struct b43_wl *wl;
36dbd954 4140 struct b43_wldev *orig_dev;
49d965c8 4141 u32 mask;
e4d6b795 4142
9a53bf54
LF		 4143 if (!dev)
4144 return NULL;
4145 wl = dev->wl;
36dbd954
MB		 4146redo:
4147 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4148 return dev;
a19d12d7 4149
f5d40eed 4150 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4151 mutex_unlock(&wl->mutex);
4152 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4153 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4154 mutex_lock(&wl->mutex);
4155 dev = wl->current_dev;
4156 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4157 /* Whoops, aliens ate up the device while we were unlocked. */
4158 return dev;
4159 }
a19d12d7 4160
36dbd954 4161 /* Disable interrupts on the device. */
e4d6b795 4162 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4163 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4164 /* wl->mutex is locked. That is enough. */
4165 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4166 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4167 } else {
4168 spin_lock_irq(&wl->hardirq_lock);
4169 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4170 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4171 spin_unlock_irq(&wl->hardirq_lock);
4172 }
176e9f6a 4173 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4174 orig_dev = dev;
e4d6b795 4175 mutex_unlock(&wl->mutex);
505fb019 4176 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4177 b43_sdio_free_irq(dev);
4178 } else {
a18c715e
RM		 4179 synchronize_irq(dev->dev->irq);
4180 free_irq(dev->dev->irq, dev);
176e9f6a 4181 }
e4d6b795 4182 mutex_lock(&wl->mutex);
36dbd954
MB		 4183 dev = wl->current_dev;
4184 if (!dev)
4185 return dev;
4186 if (dev != orig_dev) {
4187 if (b43_status(dev) >= B43_STAT_STARTED)
4188 goto redo;
4189 return dev;
4190 }
49d965c8
MB		 4191 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4192 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4193
f5d40eed
MB		 4194 /* Drain the TX queue */
4195 while (skb_queue_len(&wl->tx_queue))
4196 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4197
e4d6b795 4198 b43_mac_suspend(dev);
a78b3bb2 4199 b43_leds_exit(dev);
e4d6b795 4200 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4201
4202 return dev;
e4d6b795
MB		 4203}
4204
4205/* Locking: wl->mutex */
4206static int b43_wireless_core_start(struct b43_wldev *dev)
4207{
4208 int err;
4209
4210 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4211
4212 drain_txstatus_queue(dev);
505fb019 4213 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4214 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4215 if (err) {
4216 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4217 goto out;
4218 }
4219 } else {
a18c715e 4220 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4221 b43_interrupt_thread_handler,
4222 IRQF_SHARED, KBUILD_MODNAME, dev);
4223 if (err) {
dedb1eb9 4224 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4225 dev->dev->irq);
3dbba8e2
AH		 4226 goto out;
4227 }
e4d6b795
MB		 4228 }
4229
4230 /* We are ready to run. */
0866b03c 4231 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4232 b43_set_status(dev, B43_STAT_STARTED);
4233
4234 /* Start data flow (TX/RX). */
4235 b43_mac_enable(dev);
13790728 4236 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4237
25985edc 4238 /* Start maintenance work */
e4d6b795
MB		 4239 b43_periodic_tasks_setup(dev);
4240
a78b3bb2
MB		 4241 b43_leds_init(dev);
4242
e4d6b795 4243 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4244out:
e4d6b795
MB		 4245 return err;
4246}
4247
4248/* Get PHY and RADIO versioning numbers */
4249static int b43_phy_versioning(struct b43_wldev *dev)
4250{
4251 struct b43_phy *phy = &dev->phy;
4252 u32 tmp;
4253 u8 analog_type;
4254 u8 phy_type;
4255 u8 phy_rev;
4256 u16 radio_manuf;
4257 u16 radio_ver;
4258 u16 radio_rev;
4259 int unsupported = 0;
4260
4261 /* Get PHY versioning */
4262 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4263 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4264 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4265 phy_rev = (tmp & B43_PHYVER_VERSION);
4266 switch (phy_type) {
4267 case B43_PHYTYPE_A:
4268 if (phy_rev >= 4)
4269 unsupported = 1;
4270 break;
4271 case B43_PHYTYPE_B:
4272 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4273 && phy_rev != 7)
4274 unsupported = 1;
4275 break;
4276 case B43_PHYTYPE_G:
013978b6 4277 if (phy_rev > 9)
e4d6b795
MB		 4278 unsupported = 1;
4279 break;
692d2c0f 4280#ifdef CONFIG_B43_PHY_N
d5c71e46 4281 case B43_PHYTYPE_N:
ab72efdf 4282 if (phy_rev > 9)
d5c71e46
MB		 4283 unsupported = 1;
4284 break;
6b1c7c67
MB		 4285#endif
4286#ifdef CONFIG_B43_PHY_LP
4287 case B43_PHYTYPE_LP:
9d86a2d5 4288 if (phy_rev > 2)
6b1c7c67
MB		 4289 unsupported = 1;
4290 break;
d7520b1d
RM		 4291#endif
4292#ifdef CONFIG_B43_PHY_HT
4293 case B43_PHYTYPE_HT:
4294 if (phy_rev > 1)
4295 unsupported = 1;
4296 break;
1d738e64
RM		 4297#endif
4298#ifdef CONFIG_B43_PHY_LCN
4299 case B43_PHYTYPE_LCN:
4300 if (phy_rev > 1)
4301 unsupported = 1;
4302 break;
d5c71e46 4303#endif
e4d6b795
MB		 4304 default:
4305 unsupported = 1;
6403eab1 4306 }
e4d6b795
MB		 4307 if (unsupported) {
4308 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4309 "(Analog %u, Type %u, Revision %u)\n",
4310 analog_type, phy_type, phy_rev);
4311 return -EOPNOTSUPP;
4312 }
4313 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4314 analog_type, phy_type, phy_rev);
4315
4316 /* Get RADIO versioning */
3fd48508 4317 if (dev->dev->core_rev >= 24) {
544e5d8b
RM		 4318 u16 radio24[3];
4319
4320 for (tmp = 0; tmp < 3; tmp++) {
4321 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4322 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4323 }
4324
4325 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4326 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4327
4328 radio_manuf = 0x17F;
4329 radio_ver = (radio24[2] << 8) | radio24[1];
4330 radio_rev = (radio24[0] & 0xF);
e4d6b795 4331 } else {
3fd48508
RM		 4332 if (dev->dev->chip_id == 0x4317) {
4333 if (dev->dev->chip_rev == 0)
4334 tmp = 0x3205017F;
4335 else if (dev->dev->chip_rev == 1)
4336 tmp = 0x4205017F;
4337 else
4338 tmp = 0x5205017F;
4339 } else {
4340 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4341 B43_RADIOCTL_ID);
4342 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4343 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4344 B43_RADIOCTL_ID);
4345 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4346 << 16;
4347 }
4348 radio_manuf = (tmp & 0x00000FFF);
4349 radio_ver = (tmp & 0x0FFFF000) >> 12;
4350 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4351 }
3fd48508 4352
96c755a3
MB		 4353 if (radio_manuf != 0x17F /* Broadcom */)
4354 unsupported = 1;
e4d6b795
MB		 4355 switch (phy_type) {
4356 case B43_PHYTYPE_A:
4357 if (radio_ver != 0x2060)
4358 unsupported = 1;
4359 if (radio_rev != 1)
4360 unsupported = 1;
4361 if (radio_manuf != 0x17F)
4362 unsupported = 1;
4363 break;
4364 case B43_PHYTYPE_B:
4365 if ((radio_ver & 0xFFF0) != 0x2050)
4366 unsupported = 1;
4367 break;
4368 case B43_PHYTYPE_G:
4369 if (radio_ver != 0x2050)
4370 unsupported = 1;
4371 break;
96c755a3 4372 case B43_PHYTYPE_N:
bb519bee 4373 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4374 unsupported = 1;
4375 break;
6b1c7c67 4376 case B43_PHYTYPE_LP:
9d86a2d5 4377 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4378 unsupported = 1;
4379 break;
d7520b1d
RM		 4380 case B43_PHYTYPE_HT:
4381 if (radio_ver != 0x2059)
4382 unsupported = 1;
4383 break;
1d738e64
RM		 4384 case B43_PHYTYPE_LCN:
4385 if (radio_ver != 0x2064)
4386 unsupported = 1;
4387 break;
e4d6b795
MB		 4388 default:
4389 B43_WARN_ON(1);
4390 }
4391 if (unsupported) {
4392 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4393 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4394 radio_manuf, radio_ver, radio_rev);
4395 return -EOPNOTSUPP;
4396 }
4397 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4398 radio_manuf, radio_ver, radio_rev);
4399
4400 phy->radio_manuf = radio_manuf;
4401 phy->radio_ver = radio_ver;
4402 phy->radio_rev = radio_rev;
4403
4404 phy->analog = analog_type;
4405 phy->type = phy_type;
4406 phy->rev = phy_rev;
4407
4408 return 0;
4409}
4410
4411static void setup_struct_phy_for_init(struct b43_wldev *dev,
4412 struct b43_phy *phy)
4413{
e4d6b795 4414 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4415 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4416 /* PHY TX errors counter. */
4417 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4418
4419#if B43_DEBUG
4420 phy->phy_locked = 0;
4421 phy->radio_locked = 0;
4422#endif
e4d6b795
MB		 4423}
4424
4425static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4426{
aa6c7ae2
MB		 4427 dev->dfq_valid = 0;
4428
6a724d68
MB		 4429 /* Assume the radio is enabled. If it's not enabled, the state will
4430 * immediately get fixed on the first periodic work run. */
4431 dev->radio_hw_enable = 1;
e4d6b795
MB		 4432
4433 /* Stats */
4434 memset(&dev->stats, 0, sizeof(dev->stats));
4435
4436 setup_struct_phy_for_init(dev, &dev->phy);
4437
4438 /* IRQ related flags */
4439 dev->irq_reason = 0;
4440 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4441 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4442 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4443 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4444
4445 dev->mac_suspended = 1;
4446
4447 /* Noise calculation context */
4448 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4449}
4450
4451static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4452{
0581483a 4453 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4454 u64 hf;
e4d6b795 4455
1855ba78
MB		 4456 if (!modparam_btcoex)
4457 return;
95de2841 4458 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4459 return;
4460 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4461 return;
4462
4463 hf = b43_hf_read(dev);
95de2841 4464 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4465 hf |= B43_HF_BTCOEXALT;
4466 else
4467 hf |= B43_HF_BTCOEX;
4468 b43_hf_write(dev, hf);
e4d6b795
MB		 4469}
4470
4471static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4472{
4473 if (!modparam_btcoex)
4474 return;
4475 //TODO
e4d6b795
MB		 4476}
4477
4478static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4479{
d48ae5c8 4480 struct ssb_bus *bus;
e4d6b795
MB		 4481 u32 tmp;
4482
d48ae5c8
RM		 4483 if (dev->dev->bus_type != B43_BUS_SSB)
4484 return;
4485
4486 bus = dev->dev->sdev->bus;
4487
0fd82eaf
RM		 4488 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4489 (bus->chip_id == 0x4312)) {
d48ae5c8 4490 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4491 tmp &= ~SSB_IMCFGLO_REQTO;
4492 tmp &= ~SSB_IMCFGLO_SERTO;
4493 tmp |= 0x3;
d48ae5c8 4494 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4495 ssb_commit_settings(bus);
e4d6b795 4496 }
e4d6b795
MB		 4497}
4498
d59f720d
MB		 4499static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4500{
4501 u16 pu_delay;
4502
4503 /* The time value is in microseconds. */
4504 if (dev->phy.type == B43_PHYTYPE_A)
4505 pu_delay = 3700;
4506 else
4507 pu_delay = 1050;
05c914fe 4508 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4509 pu_delay = 500;
4510 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4511 pu_delay = max(pu_delay, (u16)2400);
4512
4513 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4514}
4515
4516/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4517static void b43_set_pretbtt(struct b43_wldev *dev)
4518{
4519 u16 pretbtt;
4520
4521 /* The time value is in microseconds. */
05c914fe 4522 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4523 pretbtt = 2;
4524 } else {
4525 if (dev->phy.type == B43_PHYTYPE_A)
4526 pretbtt = 120;
4527 else
4528 pretbtt = 250;
4529 }
4530 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4531 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4532}
4533
e4d6b795
MB		 4534/* Shutdown a wireless core */
4535/* Locking: wl->mutex */
4536static void b43_wireless_core_exit(struct b43_wldev *dev)
4537{
1f7d87b0 4538 u32 macctl;
e4d6b795 4539
36dbd954
MB		 4540 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4541 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4542 return;
84c164a3
JL		 4543
4544 /* Unregister HW RNG driver */
4545 b43_rng_exit(dev->wl);
4546
e4d6b795
MB		 4547 b43_set_status(dev, B43_STAT_UNINIT);
4548
1f7d87b0
MB		 4549 /* Stop the microcode PSM. */
4550 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4551 macctl &= ~B43_MACCTL_PSM_RUN;
4552 macctl |= B43_MACCTL_PSM_JMP0;
4553 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4554
e4d6b795 4555 b43_dma_free(dev);
5100d5ac 4556 b43_pio_free(dev);
e4d6b795 4557 b43_chip_exit(dev);
cb24f57f 4558 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4559 if (dev->wl->current_beacon) {
4560 dev_kfree_skb_any(dev->wl->current_beacon);
4561 dev->wl->current_beacon = NULL;
4562 }
4563
24ca39d6
RM		 4564 b43_device_disable(dev, 0);
4565 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4566}
4567
4568/* Initialize a wireless core */
4569static int b43_wireless_core_init(struct b43_wldev *dev)
4570{
0581483a 4571 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4572 struct b43_phy *phy = &dev->phy;
4573 int err;
a259d6a4 4574 u64 hf;
e4d6b795
MB		 4575
4576 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4577
24ca39d6 4578 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4579 if (err)
4580 goto out;
4da909e7
RM		 4581 if (!b43_device_is_enabled(dev))
4582 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4583
fb11137a 4584 /* Reset all data structures. */
e4d6b795 4585 setup_struct_wldev_for_init(dev);
fb11137a 4586 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4587
4588 /* Enable IRQ routing to this device. */
6cbab0d9 4589 switch (dev->dev->bus_type) {
42c9a458
RM		 4590#ifdef CONFIG_B43_BCMA
4591 case B43_BUS_BCMA:
4592 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4593 dev->dev->bdev, true);
4594 break;
4595#endif
6cbab0d9
RM		 4596#ifdef CONFIG_B43_SSB
4597 case B43_BUS_SSB:
4598 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4599 dev->dev->sdev);
4600 break;
4601#endif
4602 }
e4d6b795
MB		 4603
4604 b43_imcfglo_timeouts_workaround(dev);
4605 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4606 if (phy->ops->prepare_hardware) {
4607 err = phy->ops->prepare_hardware(dev);
ef1a628d 4608 if (err)
fb11137a 4609 goto err_busdown;
ef1a628d 4610 }
e4d6b795
MB		 4611 err = b43_chip_init(dev);
4612 if (err)
fb11137a 4613 goto err_busdown;
e4d6b795 4614 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4615 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4616 hf = b43_hf_read(dev);
4617 if (phy->type == B43_PHYTYPE_G) {
4618 hf |= B43_HF_SYMW;
4619 if (phy->rev == 1)
4620 hf |= B43_HF_GDCW;
95de2841 4621 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4622 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4623 }
4624 if (phy->radio_ver == 0x2050) {
4625 if (phy->radio_rev == 6)
4626 hf |= B43_HF_4318TSSI;
4627 if (phy->radio_rev < 6)
4628 hf |= B43_HF_VCORECALC;
e4d6b795 4629 }
1cc8f476
MB		 4630 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4631 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4632#ifdef CONFIG_SSB_DRIVER_PCICORE
6cbab0d9
RM		 4633 if (dev->dev->bus_type == B43_BUS_SSB &&
4634 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4635 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4636 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4637#endif
25d3ef59 4638 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4639 b43_hf_write(dev, hf);
4640
74cfdba7
MB		 4641 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4642 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4643 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4644 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4645
4646 /* Disable sending probe responses from firmware.
4647 * Setting the MaxTime to one usec will always trigger
4648 * a timeout, so we never send any probe resp.
4649 * A timeout of zero is infinite. */
4650 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4651
4652 b43_rate_memory_init(dev);
5042c507 4653 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4654
4655 /* Minimum Contention Window */
c5a079f4 4656 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4657 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4658 else
e4d6b795 4659 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4660 /* Maximum Contention Window */
4661 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4662
505fb019 4663 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a
RM		 4664 b43_bus_host_is_sdio(dev->dev)) {
4665 dev->__using_pio_transfers = 1;
4666 err = b43_pio_init(dev);
4667 } else if (dev->use_pio) {
4668 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4669 "This should not be needed and will result in lower "
4670 "performance.\n");
5100d5ac
MB		 4671 dev->__using_pio_transfers = 1;
4672 err = b43_pio_init(dev);
4673 } else {
4674 dev->__using_pio_transfers = 0;
4675 err = b43_dma_init(dev);
4676 }
e4d6b795
MB		 4677 if (err)
4678 goto err_chip_exit;
03b29773 4679 b43_qos_init(dev);
d59f720d 4680 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4681 b43_bluetooth_coext_enable(dev);
4682
24ca39d6 4683 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4684 b43_upload_card_macaddress(dev);
e4d6b795 4685 b43_security_init(dev);
e4d6b795 4686
5ab9549a 4687 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4688
4689 b43_set_status(dev, B43_STAT_INITIALIZED);
4690
84c164a3
JL		 4691 /* Register HW RNG driver */
4692 b43_rng_init(dev->wl);
4693
1a8d1227 4694out:
e4d6b795
MB		 4695 return err;
4696
ef1a628d 4697err_chip_exit:
e4d6b795 4698 b43_chip_exit(dev);
ef1a628d 4699err_busdown:
24ca39d6 4700 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4701 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4702 return err;
4703}
4704
40faacc4 4705static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4706 struct ieee80211_vif *vif)
e4d6b795
MB		 4707{
4708 struct b43_wl *wl = hw_to_b43_wl(hw);
4709 struct b43_wldev *dev;
e4d6b795 4710 int err = -EOPNOTSUPP;
4150c572
JB		 4711
4712 /* TODO: allow WDS/AP devices to coexist */
4713
1ed32e4f
JB		 4714 if (vif->type != NL80211_IFTYPE_AP &&
4715 vif->type != NL80211_IFTYPE_MESH_POINT &&
4716 vif->type != NL80211_IFTYPE_STATION &&
4717 vif->type != NL80211_IFTYPE_WDS &&
4718 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4719 return -EOPNOTSUPP;
e4d6b795
MB		 4720
4721 mutex_lock(&wl->mutex);
4150c572 4722 if (wl->operating)
e4d6b795
MB		 4723 goto out_mutex_unlock;
4724
1ed32e4f 4725 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4726
4727 dev = wl->current_dev;
4150c572 4728 wl->operating = 1;
1ed32e4f
JB		 4729 wl->vif = vif;
4730 wl->if_type = vif->type;
4731 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4732
4150c572 4733 b43_adjust_opmode(dev);
d59f720d
MB		 4734 b43_set_pretbtt(dev);
4735 b43_set_synth_pu_delay(dev, 0);
4150c572 4736 b43_upload_card_macaddress(dev);
4150c572
JB		 4737
4738 err = 0;
4739 out_mutex_unlock:
4740 mutex_unlock(&wl->mutex);
4741
2a190322
FF		 4742 if (err == 0)
4743 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4744
4150c572
JB		 4745 return err;
4746}
4747
40faacc4 4748static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4749 struct ieee80211_vif *vif)
4150c572
JB		 4750{
4751 struct b43_wl *wl = hw_to_b43_wl(hw);
4752 struct b43_wldev *dev = wl->current_dev;
4150c572 4753
1ed32e4f 4754 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4755
4756 mutex_lock(&wl->mutex);
4757
4758 B43_WARN_ON(!wl->operating);
1ed32e4f 4759 B43_WARN_ON(wl->vif != vif);
32bfd35d 4760 wl->vif = NULL;
4150c572
JB		 4761
4762 wl->operating = 0;
4763
4150c572
JB		 4764 b43_adjust_opmode(dev);
4765 memset(wl->mac_addr, 0, ETH_ALEN);
4766 b43_upload_card_macaddress(dev);
4150c572
JB		 4767
4768 mutex_unlock(&wl->mutex);
4769}
4770
40faacc4 4771static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4772{
4773 struct b43_wl *wl = hw_to_b43_wl(hw);
4774 struct b43_wldev *dev = wl->current_dev;
4775 int did_init = 0;
923403b8 4776 int err = 0;
4150c572 4777
7be1bb6b
MB		 4778 /* Kill all old instance specific information to make sure
4779 * the card won't use it in the short timeframe between start
4780 * and mac80211 reconfiguring it. */
4781 memset(wl->bssid, 0, ETH_ALEN);
4782 memset(wl->mac_addr, 0, ETH_ALEN);
4783 wl->filter_flags = 0;
4784 wl->radiotap_enabled = 0;
e6f5b934 4785 b43_qos_clear(wl);
6b4bec01
MB		 4786 wl->beacon0_uploaded = 0;
4787 wl->beacon1_uploaded = 0;
4788 wl->beacon_templates_virgin = 1;
fd4973c5 4789 wl->radio_enabled = 1;
7be1bb6b 4790
4150c572
JB		 4791 mutex_lock(&wl->mutex);
4792
e4d6b795
MB		 4793 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4794 err = b43_wireless_core_init(dev);
f41f3f37 4795 if (err)
e4d6b795
MB		 4796 goto out_mutex_unlock;
4797 did_init = 1;
4798 }
4150c572 4799
e4d6b795
MB		 4800 if (b43_status(dev) < B43_STAT_STARTED) {
4801 err = b43_wireless_core_start(dev);
4802 if (err) {
4803 if (did_init)
4804 b43_wireless_core_exit(dev);
4805 goto out_mutex_unlock;
4806 }
4807 }
4808
f41f3f37
JB		 4809 /* XXX: only do if device doesn't support rfkill irq */
4810 wiphy_rfkill_start_polling(hw->wiphy);
4811
4150c572 4812 out_mutex_unlock:
e4d6b795
MB		 4813 mutex_unlock(&wl->mutex);
4814
2a190322
FF		 4815 /* reload configuration */
4816 b43_op_config(hw, ~0);
4817
e4d6b795
MB		 4818 return err;
4819}
4820
40faacc4 4821static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4822{
4823 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4824 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4825
a82d9922 4826 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4827
e4d6b795 4828 mutex_lock(&wl->mutex);
36dbd954
MB		 4829 if (b43_status(dev) >= B43_STAT_STARTED) {
4830 dev = b43_wireless_core_stop(dev);
4831 if (!dev)
4832 goto out_unlock;
4833 }
4150c572 4834 b43_wireless_core_exit(dev);
fd4973c5 4835 wl->radio_enabled = 0;
36dbd954
MB		 4836
4837out_unlock:
e4d6b795 4838 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4839
4840 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4841}
4842
17741cdc
JB		 4843static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4844 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4845{
4846 struct b43_wl *wl = hw_to_b43_wl(hw);
4847
8f611288 4848 /* FIXME: add locking */
9d139c81 4849 b43_update_templates(wl);
e66fee6a
MB		 4850
4851 return 0;
4852}
4853
38968d09
JB		 4854static void b43_op_sta_notify(struct ieee80211_hw *hw,
4855 struct ieee80211_vif *vif,
4856 enum sta_notify_cmd notify_cmd,
17741cdc 4857 struct ieee80211_sta *sta)
38968d09
JB		 4858{
4859 struct b43_wl *wl = hw_to_b43_wl(hw);
4860
4861 B43_WARN_ON(!vif || wl->vif != vif);
4862}
4863
25d3ef59
MB		 4864static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4865{
4866 struct b43_wl *wl = hw_to_b43_wl(hw);
4867 struct b43_wldev *dev;
4868
4869 mutex_lock(&wl->mutex);
4870 dev = wl->current_dev;
4871 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4872 /* Disable CFP update during scan on other channels. */
4873 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4874 }
4875 mutex_unlock(&wl->mutex);
4876}
4877
4878static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4879{
4880 struct b43_wl *wl = hw_to_b43_wl(hw);
4881 struct b43_wldev *dev;
4882
4883 mutex_lock(&wl->mutex);
4884 dev = wl->current_dev;
4885 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4886 /* Re-enable CFP update. */
4887 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4888 }
4889 mutex_unlock(&wl->mutex);
4890}
4891
354b4f04
JL		 4892static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4893 struct survey_info *survey)
4894{
4895 struct b43_wl *wl = hw_to_b43_wl(hw);
4896 struct b43_wldev *dev = wl->current_dev;
4897 struct ieee80211_conf *conf = &hw->conf;
4898
4899 if (idx != 0)
4900 return -ENOENT;
4901
4902 survey->channel = conf->channel;
4903 survey->filled = SURVEY_INFO_NOISE_DBM;
4904 survey->noise = dev->stats.link_noise;
4905
4906 return 0;
4907}
4908
e4d6b795 4909static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4910 .tx = b43_op_tx,
4911 .conf_tx = b43_op_conf_tx,
4912 .add_interface = b43_op_add_interface,
4913 .remove_interface = b43_op_remove_interface,
4914 .config = b43_op_config,
c7ab5ef9 4915 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4916 .configure_filter = b43_op_configure_filter,
4917 .set_key = b43_op_set_key,
035d0243 4918 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 4919 .get_stats = b43_op_get_stats,
08e87a83
AF		 4920 .get_tsf = b43_op_get_tsf,
4921 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4922 .start = b43_op_start,
4923 .stop = b43_op_stop,
e66fee6a 4924 .set_tim = b43_op_beacon_set_tim,
38968d09 4925 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4926 .sw_scan_start = b43_op_sw_scan_start_notifier,
4927 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 4928 .get_survey = b43_op_get_survey,
f41f3f37 4929 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4930};
4931
4932/* Hard-reset the chip. Do not call this directly.
4933 * Use b43_controller_restart()
4934 */
4935static void b43_chip_reset(struct work_struct *work)
4936{
4937 struct b43_wldev *dev =
4938 container_of(work, struct b43_wldev, restart_work);
4939 struct b43_wl *wl = dev->wl;
4940 int err = 0;
4941 int prev_status;
4942
4943 mutex_lock(&wl->mutex);
4944
4945 prev_status = b43_status(dev);
4946 /* Bring the device down... */
36dbd954
MB		 4947 if (prev_status >= B43_STAT_STARTED) {
4948 dev = b43_wireless_core_stop(dev);
4949 if (!dev) {
4950 err = -ENODEV;
4951 goto out;
4952 }
4953 }
e4d6b795
MB		 4954 if (prev_status >= B43_STAT_INITIALIZED)
4955 b43_wireless_core_exit(dev);
4956
4957 /* ...and up again. */
4958 if (prev_status >= B43_STAT_INITIALIZED) {
4959 err = b43_wireless_core_init(dev);
4960 if (err)
4961 goto out;
4962 }
4963 if (prev_status >= B43_STAT_STARTED) {
4964 err = b43_wireless_core_start(dev);
4965 if (err) {
4966 b43_wireless_core_exit(dev);
4967 goto out;
4968 }
4969 }
3bf0a32e
MB		 4970out:
4971 if (err)
4972 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 4973 mutex_unlock(&wl->mutex);
2a190322
FF		 4974
4975 if (err) {
e4d6b795 4976 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 4977 return;
4978 }
4979
4980 /* reload configuration */
4981 b43_op_config(wl->hw, ~0);
4982 if (wl->vif)
4983 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4984
4985 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 4986}
4987
bb1eeff1 4988static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4989 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4990{
4991 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4992
bb1eeff1
MB		 4993 if (have_2ghz_phy)
4994 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4995 if (dev->phy.type == B43_PHYTYPE_N) {
4996 if (have_5ghz_phy)
4997 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4998 } else {
4999 if (have_5ghz_phy)
5000 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5001 }
96c755a3 5002
bb1eeff1
MB		 5003 dev->phy.supports_2ghz = have_2ghz_phy;
5004 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5005
5006 return 0;
5007}
5008
5009static void b43_wireless_core_detach(struct b43_wldev *dev)
5010{
5011 /* We release firmware that late to not be required to re-request
5012 * is all the time when we reinit the core. */
5013 b43_release_firmware(dev);
fb11137a 5014 b43_phy_free(dev);
e4d6b795
MB		 5015}
5016
5017static int b43_wireless_core_attach(struct b43_wldev *dev)
5018{
5019 struct b43_wl *wl = dev->wl;
6cbab0d9 5020 struct pci_dev *pdev = NULL;
e4d6b795 5021 int err;
40c62269 5022 u32 tmp;
96c755a3 5023 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 5024
5025 /* Do NOT do any device initialization here.
5026 * Do it in wireless_core_init() instead.
5027 * This function is for gathering basic information about the HW, only.
5028 * Also some structs may be set up here. But most likely you want to have
5029 * that in core_init(), too.
5030 */
5031
6cbab0d9
RM		 5032#ifdef CONFIG_B43_SSB
5033 if (dev->dev->bus_type == B43_BUS_SSB &&
5034 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5035 pdev = dev->dev->sdev->bus->host_pci;
5036#endif
5037
24ca39d6 5038 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5039 if (err) {
5040 b43err(wl, "Bus powerup failed\n");
5041 goto out;
5042 }
e4d6b795 5043
6cbab0d9
RM		 5044 /* Get the PHY type. */
5045 switch (dev->dev->bus_type) {
42c9a458
RM		 5046#ifdef CONFIG_B43_BCMA
5047 case B43_BUS_BCMA:
40c62269
RM		 5048 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5049 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5050 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5051 break;
5052#endif
6cbab0d9
RM		 5053#ifdef CONFIG_B43_SSB
5054 case B43_BUS_SSB:
5055 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5056 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5057 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5058 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5059 } else
5060 B43_WARN_ON(1);
5061 break;
5062#endif
5063 }
e4d6b795 5064
96c755a3 5065 dev->phy.gmode = have_2ghz_phy;
fd4973c5 5066 dev->phy.radio_on = 1;
4da909e7 5067 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5068
5069 err = b43_phy_versioning(dev);
5070 if (err)
21954c36 5071 goto err_powerdown;
e4d6b795
MB		 5072 /* Check if this device supports multiband. */
5073 if (!pdev ||
5074 (pdev->device != 0x4312 &&
5075 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5076 /* No multiband support. */
96c755a3
MB		 5077 have_2ghz_phy = 0;
5078 have_5ghz_phy = 0;
e4d6b795
MB		 5079 switch (dev->phy.type) {
5080 case B43_PHYTYPE_A:
96c755a3 5081 have_5ghz_phy = 1;
e4d6b795 5082 break;
9d86a2d5 5083 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 5084#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 5085 have_5ghz_phy = 1;
86b2892a 5086#endif
e4d6b795 5087 case B43_PHYTYPE_G:
96c755a3 5088 case B43_PHYTYPE_N:
8b9bda75
RM		 5089 case B43_PHYTYPE_HT:
5090 case B43_PHYTYPE_LCN:
96c755a3 5091 have_2ghz_phy = 1;
e4d6b795
MB		 5092 break;
5093 default:
5094 B43_WARN_ON(1);
5095 }
5096 }
96c755a3
MB		 5097 if (dev->phy.type == B43_PHYTYPE_A) {
5098 /* FIXME */
5099 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5100 err = -EOPNOTSUPP;
5101 goto err_powerdown;
5102 }
2e35af14
MB		 5103 if (1 /* disable A-PHY */) {
5104 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 5105 if (dev->phy.type != B43_PHYTYPE_N &&
5106 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 5107 have_2ghz_phy = 1;
5108 have_5ghz_phy = 0;
5109 }
5110 }
5111
fb11137a
MB		 5112 err = b43_phy_allocate(dev);
5113 if (err)
5114 goto err_powerdown;
5115
96c755a3 5116 dev->phy.gmode = have_2ghz_phy;
4da909e7 5117 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5118
5119 err = b43_validate_chipaccess(dev);
5120 if (err)
fb11137a 5121 goto err_phy_free;
bb1eeff1 5122 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5123 if (err)
fb11137a 5124 goto err_phy_free;
e4d6b795
MB		 5125
5126 /* Now set some default "current_dev" */
5127 if (!wl->current_dev)
5128 wl->current_dev = dev;
5129 INIT_WORK(&dev->restart_work, b43_chip_reset);
5130
cb24f57f 5131 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5132 b43_device_disable(dev, 0);
5133 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5134
5135out:
5136 return err;
5137
fb11137a
MB		 5138err_phy_free:
5139 b43_phy_free(dev);
e4d6b795 5140err_powerdown:
24ca39d6 5141 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5142 return err;
5143}
5144
482f0538 5145static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5146{
5147 struct b43_wldev *wldev;
5148 struct b43_wl *wl;
5149
3bf0a32e
MB		 5150 /* Do not cancel ieee80211-workqueue based work here.
5151 * See comment in b43_remove(). */
5152
74abacb6 5153 wldev = b43_bus_get_wldev(dev);
e4d6b795 5154 wl = wldev->wl;
e4d6b795
MB		 5155 b43_debugfs_remove_device(wldev);
5156 b43_wireless_core_detach(wldev);
5157 list_del(&wldev->list);
5158 wl->nr_devs--;
74abacb6 5159 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5160 kfree(wldev);
5161}
5162
482f0538 5163static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5164{
5165 struct b43_wldev *wldev;
e4d6b795
MB		 5166 int err = -ENOMEM;
5167
e4d6b795
MB		 5168 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5169 if (!wldev)
5170 goto out;
5171
9e3bd919 5172 wldev->use_pio = b43_modparam_pio;
482f0538 5173 wldev->dev = dev;
e4d6b795
MB		 5174 wldev->wl = wl;
5175 b43_set_status(wldev, B43_STAT_UNINIT);
5176 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5177 INIT_LIST_HEAD(&wldev->list);
5178
5179 err = b43_wireless_core_attach(wldev);
5180 if (err)
5181 goto err_kfree_wldev;
5182
5183 list_add(&wldev->list, &wl->devlist);
5184 wl->nr_devs++;
74abacb6 5185 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5186 b43_debugfs_add_device(wldev);
5187
5188 out:
5189 return err;
5190
5191 err_kfree_wldev:
5192 kfree(wldev);
5193 return err;
5194}
5195
9fc38458
MB		 5196#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5197 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5198 (pdev->device == _device) && \
5199 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5200 (pdev->subsystem_device == _subdevice) )
5201
e4d6b795
MB		 5202static void b43_sprom_fixup(struct ssb_bus *bus)
5203{
1855ba78
MB		 5204 struct pci_dev *pdev;
5205
e4d6b795
MB		 5206 /* boardflags workarounds */
5207 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5208 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 5209 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 5210 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5211 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 5212 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5213 if (bus->bustype == SSB_BUSTYPE_PCI) {
5214 pdev = bus->host_pci;
9fc38458 5215 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5216 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5217 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5218 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5219 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5220 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5221 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5222 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5223 }
e4d6b795
MB		 5224}
5225
482f0538 5226static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5227{
5228 struct ieee80211_hw *hw = wl->hw;
5229
482f0538 5230 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5231 ieee80211_free_hw(hw);
5232}
5233
d1507051 5234static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5235{
d1507051 5236 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5237 struct ieee80211_hw *hw;
5238 struct b43_wl *wl;
2729df25 5239 char chip_name[6];
e4d6b795
MB		 5240
5241 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5242 if (!hw) {
5243 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5244 return ERR_PTR(-ENOMEM);
e4d6b795 5245 }
403a3a13 5246 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5247
5248 /* fill hw info */
605a0bd6 5249 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5250 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5251
f59ac048
LR		 5252 hw->wiphy->interface_modes =
5253 BIT(NL80211_IFTYPE_AP) |
5254 BIT(NL80211_IFTYPE_MESH_POINT) |
5255 BIT(NL80211_IFTYPE_STATION) |
5256 BIT(NL80211_IFTYPE_WDS) |
5257 BIT(NL80211_IFTYPE_ADHOC);
5258
403a3a13
MB		 5259 hw->queues = modparam_qos ? 4 : 1;
5260 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 5261 hw->max_rates = 2;
e4d6b795 5262 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5263 if (is_valid_ether_addr(sprom->et1mac))
5264 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5265 else
95de2841 5266 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5267
403a3a13 5268 /* Initialize struct b43_wl */
e4d6b795 5269 wl->hw = hw;
e4d6b795 5270 mutex_init(&wl->mutex);
36dbd954 5271 spin_lock_init(&wl->hardirq_lock);
e4d6b795 5272 INIT_LIST_HEAD(&wl->devlist);
a82d9922 5273 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5274 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 5275 INIT_WORK(&wl->tx_work, b43_tx_work);
5276 skb_queue_head_init(&wl->tx_queue);
e4d6b795 5277
2729df25
RM		 5278 snprintf(chip_name, ARRAY_SIZE(chip_name),
5279 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5280 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5281 dev->core_rev);
0355a345 5282 return wl;
e4d6b795
MB		 5283}
5284
3c65ab62
RM		 5285#ifdef CONFIG_B43_BCMA
5286static int b43_bcma_probe(struct bcma_device *core)
5287{
397915c3 5288 struct b43_bus_dev *dev;
24aad3f4
RM		 5289 struct b43_wl *wl;
5290 int err;
397915c3
RM		 5291
5292 dev = b43_bus_dev_bcma_init(core);
5293 if (!dev)
5294 return -ENODEV;
5295
24aad3f4
RM		 5296 wl = b43_wireless_init(dev);
5297 if (IS_ERR(wl)) {
5298 err = PTR_ERR(wl);
5299 goto bcma_out;
5300 }
5301
5302 err = b43_one_core_attach(dev, wl);
5303 if (err)
5304 goto bcma_err_wireless_exit;
5305
5306 err = ieee80211_register_hw(wl->hw);
5307 if (err)
5308 goto bcma_err_one_core_detach;
5309 b43_leds_register(wl->current_dev);
5310
5311bcma_out:
5312 return err;
5313
5314bcma_err_one_core_detach:
5315 b43_one_core_detach(dev);
5316bcma_err_wireless_exit:
5317 ieee80211_free_hw(wl->hw);
5318 return err;
3c65ab62
RM		 5319}
5320
5321static void b43_bcma_remove(struct bcma_device *core)
5322{
24aad3f4
RM		 5323 struct b43_wldev *wldev = bcma_get_drvdata(core);
5324 struct b43_wl *wl = wldev->wl;
5325
5326 /* We must cancel any work here before unregistering from ieee80211,
5327 * as the ieee80211 unreg will destroy the workqueue. */
5328 cancel_work_sync(&wldev->restart_work);
5329
5330 /* Restore the queues count before unregistering, because firmware detect
5331 * might have modified it. Restoring is important, so the networking
5332 * stack can properly free resources. */
5333 wl->hw->queues = wl->mac80211_initially_registered_queues;
5334 b43_leds_stop(wldev);
5335 ieee80211_unregister_hw(wl->hw);
5336
5337 b43_one_core_detach(wldev->dev);
5338
5339 b43_leds_unregister(wl);
5340
5341 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5342}
5343
5344static struct bcma_driver b43_bcma_driver = {
5345 .name = KBUILD_MODNAME,
5346 .id_table = b43_bcma_tbl,
5347 .probe = b43_bcma_probe,
5348 .remove = b43_bcma_remove,
5349};
5350#endif
5351
aec7ffdf 5352#ifdef CONFIG_B43_SSB
aa63418a
RM		 5353static
5354int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5355{
482f0538 5356 struct b43_bus_dev *dev;
e4d6b795
MB		 5357 struct b43_wl *wl;
5358 int err;
5359 int first = 0;
5360
482f0538 5361 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5362 if (!dev)
5363 return -ENOMEM;
482f0538 5364
aa63418a 5365 wl = ssb_get_devtypedata(sdev);
e4d6b795
MB		 5366 if (!wl) {
5367 /* Probing the first core. Must setup common struct b43_wl */
5368 first = 1;
aa63418a 5369 b43_sprom_fixup(sdev->bus);
d1507051 5370 wl = b43_wireless_init(dev);
0355a345
RM		 5371 if (IS_ERR(wl)) {
5372 err = PTR_ERR(wl);
e4d6b795 5373 goto out;
0355a345 5374 }
aa63418a
RM		 5375 ssb_set_devtypedata(sdev, wl);
5376 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
e4d6b795
MB		 5377 }
5378 err = b43_one_core_attach(dev, wl);
5379 if (err)
5380 goto err_wireless_exit;
5381
5382 if (first) {
5383 err = ieee80211_register_hw(wl->hw);
5384 if (err)
5385 goto err_one_core_detach;
a78b3bb2 5386 b43_leds_register(wl->current_dev);
e4d6b795
MB		 5387 }
5388
5389 out:
5390 return err;
5391
5392 err_one_core_detach:
5393 b43_one_core_detach(dev);
5394 err_wireless_exit:
5395 if (first)
5396 b43_wireless_exit(dev, wl);
5397 return err;
5398}
5399
aa63418a 5400static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5401{
aa63418a
RM		 5402 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5403 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5404 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5405
3bf0a32e
MB		 5406 /* We must cancel any work here before unregistering from ieee80211,
5407 * as the ieee80211 unreg will destroy the workqueue. */
5408 cancel_work_sync(&wldev->restart_work);
5409
e4d6b795 5410 B43_WARN_ON(!wl);
403a3a13
MB		 5411 if (wl->current_dev == wldev) {
5412 /* Restore the queues count before unregistering, because firmware detect
5413 * might have modified it. Restoring is important, so the networking
5414 * stack can properly free resources. */
5415 wl->hw->queues = wl->mac80211_initially_registered_queues;
82905ace 5416 b43_leds_stop(wldev);
e4d6b795 5417 ieee80211_unregister_hw(wl->hw);
403a3a13 5418 }
e4d6b795 5419
e61b52d1 5420 b43_one_core_detach(dev);
e4d6b795
MB		 5421
5422 if (list_empty(&wl->devlist)) {
727c9885 5423 b43_leds_unregister(wl);
e4d6b795
MB		 5424 /* Last core on the chip unregistered.
5425 * We can destroy common struct b43_wl.
5426 */
e61b52d1 5427 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5428 }
5429}
5430
aec7ffdf
RM		 5431static struct ssb_driver b43_ssb_driver = {
5432 .name = KBUILD_MODNAME,
5433 .id_table = b43_ssb_tbl,
5434 .probe = b43_ssb_probe,
5435 .remove = b43_ssb_remove,
5436};
5437#endif /* CONFIG_B43_SSB */
5438
e4d6b795
MB		 5439/* Perform a hardware reset. This can be called from any context. */
5440void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5441{
5442 /* Must avoid requeueing, if we are in shutdown. */
5443 if (b43_status(dev) < B43_STAT_INITIALIZED)
5444 return;
5445 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5446 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5447}
5448
26bc783f
MB		 5449static void b43_print_driverinfo(void)
5450{
5451 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5452 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5453
5454#ifdef CONFIG_B43_PCI_AUTOSELECT
5455 feat_pci = "P";
5456#endif
5457#ifdef CONFIG_B43_PCMCIA
5458 feat_pcmcia = "M";
5459#endif
692d2c0f 5460#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5461 feat_nphy = "N";
5462#endif
5463#ifdef CONFIG_B43_LEDS
5464 feat_leds = "L";
3dbba8e2
AH		 5465#endif
5466#ifdef CONFIG_B43_SDIO
5467 feat_sdio = "S";
26bc783f
MB		 5468#endif
5469 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5470 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5471 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5472 feat_leds, feat_sdio);
26bc783f
MB		 5473}
5474
e4d6b795
MB		 5475static int __init b43_init(void)
5476{
5477 int err;
5478
5479 b43_debugfs_init();
5480 err = b43_pcmcia_init();
5481 if (err)
5482 goto err_dfs_exit;
3dbba8e2 5483 err = b43_sdio_init();
e4d6b795
MB		 5484 if (err)
5485 goto err_pcmcia_exit;
3c65ab62
RM		 5486#ifdef CONFIG_B43_BCMA
5487 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5488 if (err)
5489 goto err_sdio_exit;
3c65ab62 5490#endif
aec7ffdf 5491#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5492 err = ssb_driver_register(&b43_ssb_driver);
5493 if (err)
5494 goto err_bcma_driver_exit;
aec7ffdf 5495#endif
26bc783f 5496 b43_print_driverinfo();
e4d6b795
MB		 5497
5498 return err;
5499
aec7ffdf 5500#ifdef CONFIG_B43_SSB
3c65ab62 5501err_bcma_driver_exit:
aec7ffdf 5502#endif
3c65ab62
RM		 5503#ifdef CONFIG_B43_BCMA
5504 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5505err_sdio_exit:
3c65ab62 5506#endif
3dbba8e2 5507 b43_sdio_exit();
e4d6b795
MB		 5508err_pcmcia_exit:
5509 b43_pcmcia_exit();
5510err_dfs_exit:
5511 b43_debugfs_exit();
5512 return err;
5513}
5514
5515static void __exit b43_exit(void)
5516{
aec7ffdf 5517#ifdef CONFIG_B43_SSB
e4d6b795 5518 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5519#endif
3c65ab62
RM		 5520#ifdef CONFIG_B43_BCMA
5521 bcma_driver_unregister(&b43_bcma_driver);
5522#endif
3dbba8e2 5523 b43_sdio_exit();
e4d6b795
MB		 5524 b43_pcmcia_exit();
5525 b43_debugfs_exit();
5526}
5527
5528module_init(b43_init)
5529module_exit(b43_exit)
Linux kernel - Deliverables
This page took 1.17165 seconds and 5 git commands to generate.