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mac80211: implement EU regulatory domain
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
96cf49a2 41#include <linux/io.h>
e4d6b795
MB		 42#include <linux/dma-mapping.h>
43#include <asm/unaligned.h>
44
45#include "b43.h"
46#include "main.h"
47#include "debugfs.h"
48#include "phy.h"
7b584163 49#include "nphy.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
e6f5b934 91
e4d6b795
MB		 92static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 100 SSB_DEVTABLE_END
101};
102
103MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105/* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
e4d6b795 114 }
8318d78a
JB		 115
116/*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
e4d6b795 120static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 133};
134
135#define b43_a_ratetable (__b43_ratetable + 4)
136#define b43_a_ratetable_size 8
137#define b43_b_ratetable (__b43_ratetable + 0)
138#define b43_b_ratetable_size 4
139#define b43_g_ratetable (__b43_ratetable + 0)
140#define b43_g_ratetable_size 12
141
bb1eeff1
MB		 142#define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149}
96c755a3 150static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165};
166#undef CHAN4G
167
168#define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175}
176static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 232};
233
bb1eeff1
MB		 234static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254};
255#undef CHAN5G
256
257static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
e4d6b795 263};
8318d78a 264
bb1eeff1
MB		 265static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
8318d78a 271};
e4d6b795 272
8318d78a 273static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 279};
280
e4d6b795
MB		 281static void b43_wireless_core_exit(struct b43_wldev *dev);
282static int b43_wireless_core_init(struct b43_wldev *dev);
283static void b43_wireless_core_stop(struct b43_wldev *dev);
284static int b43_wireless_core_start(struct b43_wldev *dev);
285
286static int b43_ratelimit(struct b43_wl *wl)
287{
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295}
296
297void b43info(struct b43_wl *wl, const char *fmt, ...)
298{
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308}
309
310void b43err(struct b43_wl *wl, const char *fmt, ...)
311{
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43warn(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334}
335
336#if B43_DEBUG
337void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338{
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347#endif /* DEBUG */
348
349static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350{
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362}
363
280d0e16
MB		 364static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
e4d6b795
MB		 366{
367 u32 control;
368
369 /* "offset" is the WORD offset. */
e4d6b795
MB		 370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374}
375
376u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
377{
280d0e16
MB		 378 struct b43_wl *wl = dev->wl;
379 unsigned long flags;
e4d6b795
MB		 380 u32 ret;
381
280d0e16 382 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 383 if (routing == B43_SHM_SHARED) {
384 B43_WARN_ON(offset & 0x0001);
385 if (offset & 0x0003) {
386 /* Unaligned access */
387 b43_shm_control_word(dev, routing, offset >> 2);
388 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
389 ret <<= 16;
390 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
391 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
392
280d0e16 393 goto out;
e4d6b795
MB		 394 }
395 offset >>= 2;
396 }
397 b43_shm_control_word(dev, routing, offset);
398 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 399out:
400 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 401
402 return ret;
403}
404
405u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
406{
280d0e16
MB		 407 struct b43_wl *wl = dev->wl;
408 unsigned long flags;
e4d6b795
MB		 409 u16 ret;
410
280d0e16 411 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 412 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev, routing, offset >> 2);
417 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
418
280d0e16 419 goto out;
e4d6b795
MB		 420 }
421 offset >>= 2;
422 }
423 b43_shm_control_word(dev, routing, offset);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16
MB		 425out:
426 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 427
428 return ret;
429}
430
431void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
432{
280d0e16
MB		 433 struct b43_wl *wl = dev->wl;
434 unsigned long flags;
435
436 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 437 if (routing == B43_SHM_SHARED) {
438 B43_WARN_ON(offset & 0x0001);
439 if (offset & 0x0003) {
440 /* Unaligned access */
441 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 442 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
443 (value >> 16) & 0xffff);
e4d6b795 444 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 445 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
280d0e16 446 goto out;
e4d6b795
MB		 447 }
448 offset >>= 2;
449 }
450 b43_shm_control_word(dev, routing, offset);
e4d6b795 451 b43_write32(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 452out:
453 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 454}
455
456void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
457{
280d0e16
MB		 458 struct b43_wl *wl = dev->wl;
459 unsigned long flags;
460
461 spin_lock_irqsave(&wl->shm_lock, flags);
e4d6b795
MB		 462 if (routing == B43_SHM_SHARED) {
463 B43_WARN_ON(offset & 0x0001);
464 if (offset & 0x0003) {
465 /* Unaligned access */
466 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 467 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
280d0e16 468 goto out;
e4d6b795
MB		 469 }
470 offset >>= 2;
471 }
472 b43_shm_control_word(dev, routing, offset);
e4d6b795 473 b43_write16(dev, B43_MMIO_SHM_DATA, value);
280d0e16
MB		 474out:
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 476}
477
478/* Read HostFlags */
35f0d354 479u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 480{
35f0d354 481 u64 ret;
e4d6b795
MB		 482
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
484 ret <<= 16;
35f0d354
MB		 485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
486 ret <<= 16;
e4d6b795
MB		 487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488
489 return ret;
490}
491
492/* Write HostFlags */
35f0d354 493void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 494{
35f0d354
MB		 495 u16 lo, mi, hi;
496
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 503}
504
505void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
506{
507 /* We need to be careful. As we read the TSF from multiple
508 * registers, we should take care of register overflows.
509 * In theory, the whole tsf read process should be atomic.
510 * We try to be atomic here, by restaring the read process,
511 * if any of the high registers changed (overflew).
512 */
513 if (dev->dev->id.revision >= 3) {
514 u32 low, high, high2;
515
516 do {
517 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
518 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
519 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
520 } while (unlikely(high != high2));
521
522 *tsf = high;
523 *tsf <<= 32;
524 *tsf |= low;
525 } else {
526 u64 tmp;
527 u16 v0, v1, v2, v3;
528 u16 test1, test2, test3;
529
530 do {
531 v3 = b43_read16(dev, B43_MMIO_TSF_3);
532 v2 = b43_read16(dev, B43_MMIO_TSF_2);
533 v1 = b43_read16(dev, B43_MMIO_TSF_1);
534 v0 = b43_read16(dev, B43_MMIO_TSF_0);
535
536 test3 = b43_read16(dev, B43_MMIO_TSF_3);
537 test2 = b43_read16(dev, B43_MMIO_TSF_2);
538 test1 = b43_read16(dev, B43_MMIO_TSF_1);
539 } while (v3 != test3 || v2 != test2 || v1 != test1);
540
541 *tsf = v3;
542 *tsf <<= 48;
543 tmp = v2;
544 tmp <<= 32;
545 *tsf |= tmp;
546 tmp = v1;
547 tmp <<= 16;
548 *tsf |= tmp;
549 *tsf |= v0;
550 }
551}
552
553static void b43_time_lock(struct b43_wldev *dev)
554{
555 u32 macctl;
556
557 macctl = b43_read32(dev, B43_MMIO_MACCTL);
558 macctl |= B43_MACCTL_TBTTHOLD;
559 b43_write32(dev, B43_MMIO_MACCTL, macctl);
560 /* Commit the write */
561 b43_read32(dev, B43_MMIO_MACCTL);
562}
563
564static void b43_time_unlock(struct b43_wldev *dev)
565{
566 u32 macctl;
567
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl &= ~B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
573}
574
575static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
576{
577 /* Be careful with the in-progress timer.
578 * First zero out the low register, so we have a full
579 * register-overflow duration to complete the operation.
580 */
581 if (dev->dev->id.revision >= 3) {
582 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
583 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
584
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
586 mmiowb();
587 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
588 mmiowb();
589 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
590 } else {
591 u16 v0 = (tsf & 0x000000000000FFFFULL);
592 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
593 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
594 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
595
596 b43_write16(dev, B43_MMIO_TSF_0, 0);
597 mmiowb();
598 b43_write16(dev, B43_MMIO_TSF_3, v3);
599 mmiowb();
600 b43_write16(dev, B43_MMIO_TSF_2, v2);
601 mmiowb();
602 b43_write16(dev, B43_MMIO_TSF_1, v1);
603 mmiowb();
604 b43_write16(dev, B43_MMIO_TSF_0, v0);
605 }
606}
607
608void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
609{
610 b43_time_lock(dev);
611 b43_tsf_write_locked(dev, tsf);
612 b43_time_unlock(dev);
613}
614
615static
616void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
617{
618 static const u8 zero_addr[ETH_ALEN] = { 0 };
619 u16 data;
620
621 if (!mac)
622 mac = zero_addr;
623
624 offset |= 0x0020;
625 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
626
627 data = mac[0];
628 data |= mac[1] << 8;
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630 data = mac[2];
631 data |= mac[3] << 8;
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
633 data = mac[4];
634 data |= mac[5] << 8;
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636}
637
638static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
639{
640 const u8 *mac;
641 const u8 *bssid;
642 u8 mac_bssid[ETH_ALEN * 2];
643 int i;
644 u32 tmp;
645
646 bssid = dev->wl->bssid;
647 mac = dev->wl->mac_addr;
648
649 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
650
651 memcpy(mac_bssid, mac, ETH_ALEN);
652 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
653
654 /* Write our MAC address and BSSID to template ram */
655 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
656 tmp = (u32) (mac_bssid[i + 0]);
657 tmp |= (u32) (mac_bssid[i + 1]) << 8;
658 tmp |= (u32) (mac_bssid[i + 2]) << 16;
659 tmp |= (u32) (mac_bssid[i + 3]) << 24;
660 b43_ram_write(dev, 0x20 + i, tmp);
661 }
662}
663
4150c572 664static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 665{
e4d6b795 666 b43_write_mac_bssid_templates(dev);
4150c572 667 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 668}
669
670static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
671{
672 /* slot_time is in usec. */
673 if (dev->phy.type != B43_PHYTYPE_G)
674 return;
675 b43_write16(dev, 0x684, 510 + slot_time);
676 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
677}
678
679static void b43_short_slot_timing_enable(struct b43_wldev *dev)
680{
681 b43_set_slot_time(dev, 9);
682 dev->short_slot = 1;
683}
684
685static void b43_short_slot_timing_disable(struct b43_wldev *dev)
686{
687 b43_set_slot_time(dev, 20);
688 dev->short_slot = 0;
689}
690
691/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
692 * Returns the _previously_ enabled IRQ mask.
693 */
694static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
695{
696 u32 old_mask;
697
698 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
699 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
700
701 return old_mask;
702}
703
704/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
705 * Returns the _previously_ enabled IRQ mask.
706 */
707static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
708{
709 u32 old_mask;
710
711 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
712 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
713
714 return old_mask;
715}
716
717/* Synchronize IRQ top- and bottom-half.
718 * IRQs must be masked before calling this.
719 * This must not be called with the irq_lock held.
720 */
721static void b43_synchronize_irq(struct b43_wldev *dev)
722{
723 synchronize_irq(dev->dev->irq);
724 tasklet_kill(&dev->isr_tasklet);
725}
726
727/* DummyTransmission function, as documented on
728 * http://bcm-specs.sipsolutions.net/DummyTransmission
729 */
730void b43_dummy_transmission(struct b43_wldev *dev)
731{
21a75d77 732 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 733 struct b43_phy *phy = &dev->phy;
734 unsigned int i, max_loop;
735 u16 value;
736 u32 buffer[5] = {
737 0x00000000,
738 0x00D40000,
739 0x00000000,
740 0x01000000,
741 0x00000000,
742 };
743
744 switch (phy->type) {
745 case B43_PHYTYPE_A:
746 max_loop = 0x1E;
747 buffer[0] = 0x000201CC;
748 break;
749 case B43_PHYTYPE_B:
750 case B43_PHYTYPE_G:
751 max_loop = 0xFA;
752 buffer[0] = 0x000B846E;
753 break;
754 default:
755 B43_WARN_ON(1);
756 return;
757 }
758
21a75d77
MB		 759 spin_lock_irq(&wl->irq_lock);
760 write_lock(&wl->tx_lock);
761
e4d6b795
MB		 762 for (i = 0; i < 5; i++)
763 b43_ram_write(dev, i * 4, buffer[i]);
764
765 /* Commit writes */
766 b43_read32(dev, B43_MMIO_MACCTL);
767
768 b43_write16(dev, 0x0568, 0x0000);
769 b43_write16(dev, 0x07C0, 0x0000);
770 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
771 b43_write16(dev, 0x050C, value);
772 b43_write16(dev, 0x0508, 0x0000);
773 b43_write16(dev, 0x050A, 0x0000);
774 b43_write16(dev, 0x054C, 0x0000);
775 b43_write16(dev, 0x056A, 0x0014);
776 b43_write16(dev, 0x0568, 0x0826);
777 b43_write16(dev, 0x0500, 0x0000);
778 b43_write16(dev, 0x0502, 0x0030);
779
780 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
781 b43_radio_write16(dev, 0x0051, 0x0017);
782 for (i = 0x00; i < max_loop; i++) {
783 value = b43_read16(dev, 0x050E);
784 if (value & 0x0080)
785 break;
786 udelay(10);
787 }
788 for (i = 0x00; i < 0x0A; i++) {
789 value = b43_read16(dev, 0x050E);
790 if (value & 0x0400)
791 break;
792 udelay(10);
793 }
794 for (i = 0x00; i < 0x0A; i++) {
795 value = b43_read16(dev, 0x0690);
796 if (!(value & 0x0100))
797 break;
798 udelay(10);
799 }
800 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
801 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 802
803 write_unlock(&wl->tx_lock);
804 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 805}
806
807static void key_write(struct b43_wldev *dev,
808 u8 index, u8 algorithm, const u8 * key)
809{
810 unsigned int i;
811 u32 offset;
812 u16 value;
813 u16 kidx;
814
815 /* Key index/algo block */
816 kidx = b43_kidx_to_fw(dev, index);
817 value = ((kidx << 4) | algorithm);
818 b43_shm_write16(dev, B43_SHM_SHARED,
819 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
820
821 /* Write the key to the Key Table Pointer offset */
822 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
823 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
824 value = key[i];
825 value |= (u16) (key[i + 1]) << 8;
826 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
827 }
828}
829
830static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
831{
832 u32 addrtmp[2] = { 0, 0, };
833 u8 per_sta_keys_start = 8;
834
835 if (b43_new_kidx_api(dev))
836 per_sta_keys_start = 4;
837
838 B43_WARN_ON(index < per_sta_keys_start);
839 /* We have two default TX keys and possibly two default RX keys.
840 * Physical mac 0 is mapped to physical key 4 or 8, depending
841 * on the firmware version.
842 * So we must adjust the index here.
843 */
844 index -= per_sta_keys_start;
845
846 if (addr) {
847 addrtmp[0] = addr[0];
848 addrtmp[0] |= ((u32) (addr[1]) << 8);
849 addrtmp[0] |= ((u32) (addr[2]) << 16);
850 addrtmp[0] |= ((u32) (addr[3]) << 24);
851 addrtmp[1] = addr[4];
852 addrtmp[1] |= ((u32) (addr[5]) << 8);
853 }
854
855 if (dev->dev->id.revision >= 5) {
856 /* Receive match transmitter address mechanism */
857 b43_shm_write32(dev, B43_SHM_RCMTA,
858 (index * 2) + 0, addrtmp[0]);
859 b43_shm_write16(dev, B43_SHM_RCMTA,
860 (index * 2) + 1, addrtmp[1]);
861 } else {
862 /* RXE (Receive Engine) and
863 * PSM (Programmable State Machine) mechanism
864 */
865 if (index < 8) {
866 /* TODO write to RCM 16, 19, 22 and 25 */
867 } else {
868 b43_shm_write32(dev, B43_SHM_SHARED,
869 B43_SHM_SH_PSM + (index * 6) + 0,
870 addrtmp[0]);
871 b43_shm_write16(dev, B43_SHM_SHARED,
872 B43_SHM_SH_PSM + (index * 6) + 4,
873 addrtmp[1]);
874 }
875 }
876}
877
878static void do_key_write(struct b43_wldev *dev,
879 u8 index, u8 algorithm,
880 const u8 * key, size_t key_len, const u8 * mac_addr)
881{
882 u8 buf[B43_SEC_KEYSIZE] = { 0, };
883 u8 per_sta_keys_start = 8;
884
885 if (b43_new_kidx_api(dev))
886 per_sta_keys_start = 4;
887
888 B43_WARN_ON(index >= dev->max_nr_keys);
889 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
890
891 if (index >= per_sta_keys_start)
892 keymac_write(dev, index, NULL); /* First zero out mac. */
893 if (key)
894 memcpy(buf, key, key_len);
895 key_write(dev, index, algorithm, buf);
896 if (index >= per_sta_keys_start)
897 keymac_write(dev, index, mac_addr);
898
899 dev->key[index].algorithm = algorithm;
900}
901
902static int b43_key_write(struct b43_wldev *dev,
903 int index, u8 algorithm,
904 const u8 * key, size_t key_len,
905 const u8 * mac_addr,
906 struct ieee80211_key_conf *keyconf)
907{
908 int i;
909 int sta_keys_start;
910
911 if (key_len > B43_SEC_KEYSIZE)
912 return -EINVAL;
913 for (i = 0; i < dev->max_nr_keys; i++) {
914 /* Check that we don't already have this key. */
915 B43_WARN_ON(dev->key[i].keyconf == keyconf);
916 }
917 if (index < 0) {
918 /* Either pairwise key or address is 00:00:00:00:00:00
919 * for transmit-only keys. Search the index. */
920 if (b43_new_kidx_api(dev))
921 sta_keys_start = 4;
922 else
923 sta_keys_start = 8;
924 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
925 if (!dev->key[i].keyconf) {
926 /* found empty */
927 index = i;
928 break;
929 }
930 }
931 if (index < 0) {
932 b43err(dev->wl, "Out of hardware key memory\n");
933 return -ENOSPC;
934 }
935 } else
936 B43_WARN_ON(index > 3);
937
938 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
939 if ((index <= 3) && !b43_new_kidx_api(dev)) {
940 /* Default RX key */
941 B43_WARN_ON(mac_addr);
942 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
943 }
944 keyconf->hw_key_idx = index;
945 dev->key[index].keyconf = keyconf;
946
947 return 0;
948}
949
950static int b43_key_clear(struct b43_wldev *dev, int index)
951{
952 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
953 return -EINVAL;
954 do_key_write(dev, index, B43_SEC_ALGO_NONE,
955 NULL, B43_SEC_KEYSIZE, NULL);
956 if ((index <= 3) && !b43_new_kidx_api(dev)) {
957 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
958 NULL, B43_SEC_KEYSIZE, NULL);
959 }
960 dev->key[index].keyconf = NULL;
961
962 return 0;
963}
964
965static void b43_clear_keys(struct b43_wldev *dev)
966{
967 int i;
968
969 for (i = 0; i < dev->max_nr_keys; i++)
970 b43_key_clear(dev, i);
971}
972
973void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
974{
975 u32 macctl;
976 u16 ucstat;
977 bool hwps;
978 bool awake;
979 int i;
980
981 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
982 (ps_flags & B43_PS_DISABLED));
983 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
984
985 if (ps_flags & B43_PS_ENABLED) {
986 hwps = 1;
987 } else if (ps_flags & B43_PS_DISABLED) {
988 hwps = 0;
989 } else {
990 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
991 // and thus is not an AP and we are associated, set bit 25
992 }
993 if (ps_flags & B43_PS_AWAKE) {
994 awake = 1;
995 } else if (ps_flags & B43_PS_ASLEEP) {
996 awake = 0;
997 } else {
998 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
999 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1000 // successful, set bit26
1001 }
1002
1003/* FIXME: For now we force awake-on and hwps-off */
1004 hwps = 0;
1005 awake = 1;
1006
1007 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1008 if (hwps)
1009 macctl |= B43_MACCTL_HWPS;
1010 else
1011 macctl &= ~B43_MACCTL_HWPS;
1012 if (awake)
1013 macctl |= B43_MACCTL_AWAKE;
1014 else
1015 macctl &= ~B43_MACCTL_AWAKE;
1016 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1017 /* Commit write */
1018 b43_read32(dev, B43_MMIO_MACCTL);
1019 if (awake && dev->dev->id.revision >= 5) {
1020 /* Wait for the microcode to wake up. */
1021 for (i = 0; i < 100; i++) {
1022 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1023 B43_SHM_SH_UCODESTAT);
1024 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1025 break;
1026 udelay(10);
1027 }
1028 }
1029}
1030
1031/* Turn the Analog ON/OFF */
1032static void b43_switch_analog(struct b43_wldev *dev, int on)
1033{
7b584163
MB		 1034 switch (dev->phy.type) {
1035 case B43_PHYTYPE_A:
1036 case B43_PHYTYPE_G:
1037 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1038 break;
1039 case B43_PHYTYPE_N:
1040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1041 on ? 0 : 0x7FFF);
1042 break;
1043 default:
1044 B43_WARN_ON(1);
1045 }
e4d6b795
MB		 1046}
1047
1048void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1049{
1050 u32 tmslow;
1051 u32 macctl;
1052
1053 flags |= B43_TMSLOW_PHYCLKEN;
1054 flags |= B43_TMSLOW_PHYRESET;
1055 ssb_device_enable(dev->dev, flags);
1056 msleep(2); /* Wait for the PLL to turn on. */
1057
1058 /* Now take the PHY out of Reset again */
1059 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1060 tmslow |= SSB_TMSLOW_FGC;
1061 tmslow &= ~B43_TMSLOW_PHYRESET;
1062 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1063 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1064 msleep(1);
1065 tmslow &= ~SSB_TMSLOW_FGC;
1066 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1067 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1068 msleep(1);
1069
1070 /* Turn Analog ON */
1071 b43_switch_analog(dev, 1);
1072
1073 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1074 macctl &= ~B43_MACCTL_GMODE;
1075 if (flags & B43_TMSLOW_GMODE)
1076 macctl |= B43_MACCTL_GMODE;
1077 macctl |= B43_MACCTL_IHR_ENABLED;
1078 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1079}
1080
1081static void handle_irq_transmit_status(struct b43_wldev *dev)
1082{
1083 u32 v0, v1;
1084 u16 tmp;
1085 struct b43_txstatus stat;
1086
1087 while (1) {
1088 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1089 if (!(v0 & 0x00000001))
1090 break;
1091 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1092
1093 stat.cookie = (v0 >> 16);
1094 stat.seq = (v1 & 0x0000FFFF);
1095 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1096 tmp = (v0 & 0x0000FFFF);
1097 stat.frame_count = ((tmp & 0xF000) >> 12);
1098 stat.rts_count = ((tmp & 0x0F00) >> 8);
1099 stat.supp_reason = ((tmp & 0x001C) >> 2);
1100 stat.pm_indicated = !!(tmp & 0x0080);
1101 stat.intermediate = !!(tmp & 0x0040);
1102 stat.for_ampdu = !!(tmp & 0x0020);
1103 stat.acked = !!(tmp & 0x0002);
1104
1105 b43_handle_txstatus(dev, &stat);
1106 }
1107}
1108
1109static void drain_txstatus_queue(struct b43_wldev *dev)
1110{
1111 u32 dummy;
1112
1113 if (dev->dev->id.revision < 5)
1114 return;
1115 /* Read all entries from the microcode TXstatus FIFO
1116 * and throw them away.
1117 */
1118 while (1) {
1119 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1120 if (!(dummy & 0x00000001))
1121 break;
1122 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1123 }
1124}
1125
1126static u32 b43_jssi_read(struct b43_wldev *dev)
1127{
1128 u32 val = 0;
1129
1130 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1131 val <<= 16;
1132 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1133
1134 return val;
1135}
1136
1137static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1138{
1139 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1140 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1141}
1142
1143static void b43_generate_noise_sample(struct b43_wldev *dev)
1144{
1145 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1146 b43_write32(dev, B43_MMIO_MACCMD,
1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1148}
1149
1150static void b43_calculate_link_quality(struct b43_wldev *dev)
1151{
1152 /* Top half of Link Quality calculation. */
1153
1154 if (dev->noisecalc.calculation_running)
1155 return;
e4d6b795
MB		 1156 dev->noisecalc.calculation_running = 1;
1157 dev->noisecalc.nr_samples = 0;
1158
1159 b43_generate_noise_sample(dev);
1160}
1161
1162static void handle_irq_noise(struct b43_wldev *dev)
1163{
1164 struct b43_phy *phy = &dev->phy;
1165 u16 tmp;
1166 u8 noise[4];
1167 u8 i, j;
1168 s32 average;
1169
1170 /* Bottom half of Link Quality calculation. */
1171
98a3b2fe
MB		 1172 /* Possible race condition: It might be possible that the user
1173 * changed to a different channel in the meantime since we
1174 * started the calculation. We ignore that fact, since it's
1175 * not really that much of a problem. The background noise is
1176 * an estimation only anyway. Slightly wrong results will get damped
1177 * by the averaging of the 8 sample rounds. Additionally the
1178 * value is shortlived. So it will be replaced by the next noise
1179 * calculation round soon. */
1180
e4d6b795 1181 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1182 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1183 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1184 noise[2] == 0x7F || noise[3] == 0x7F)
1185 goto generate_new;
1186
1187 /* Get the noise samples. */
1188 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1189 i = dev->noisecalc.nr_samples;
1190 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1191 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1192 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1193 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1195 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1196 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1197 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1198 dev->noisecalc.nr_samples++;
1199 if (dev->noisecalc.nr_samples == 8) {
1200 /* Calculate the Link Quality by the noise samples. */
1201 average = 0;
1202 for (i = 0; i < 8; i++) {
1203 for (j = 0; j < 4; j++)
1204 average += dev->noisecalc.samples[i][j];
1205 }
1206 average /= (8 * 4);
1207 average *= 125;
1208 average += 64;
1209 average /= 128;
1210 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1211 tmp = (tmp / 128) & 0x1F;
1212 if (tmp >= 8)
1213 average += 2;
1214 else
1215 average -= 25;
1216 if (tmp == 8)
1217 average -= 72;
1218 else
1219 average -= 48;
1220
1221 dev->stats.link_noise = average;
e4d6b795
MB		 1222 dev->noisecalc.calculation_running = 0;
1223 return;
1224 }
98a3b2fe 1225generate_new:
e4d6b795
MB		 1226 b43_generate_noise_sample(dev);
1227}
1228
1229static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1230{
1231 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1232 ///TODO: PS TBTT
1233 } else {
1234 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1235 b43_power_saving_ctl_bits(dev, 0);
1236 }
e4d6b795 1237 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
aa6c7ae2 1238 dev->dfq_valid = 1;
e4d6b795
MB		 1239}
1240
1241static void handle_irq_atim_end(struct b43_wldev *dev)
1242{
aa6c7ae2
MB		 1243 if (dev->dfq_valid) {
1244 b43_write32(dev, B43_MMIO_MACCMD,
1245 b43_read32(dev, B43_MMIO_MACCMD)
1246 | B43_MACCMD_DFQ_VALID);
1247 dev->dfq_valid = 0;
1248 }
e4d6b795
MB		 1249}
1250
1251static void handle_irq_pmq(struct b43_wldev *dev)
1252{
1253 u32 tmp;
1254
1255 //TODO: AP mode.
1256
1257 while (1) {
1258 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1259 if (!(tmp & 0x00000008))
1260 break;
1261 }
1262 /* 16bit write is odd, but correct. */
1263 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1264}
1265
1266static void b43_write_template_common(struct b43_wldev *dev,
1267 const u8 * data, u16 size,
1268 u16 ram_offset,
1269 u16 shm_size_offset, u8 rate)
1270{
1271 u32 i, tmp;
1272 struct b43_plcp_hdr4 plcp;
1273
1274 plcp.data = 0;
1275 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1276 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1277 ram_offset += sizeof(u32);
1278 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1279 * So leave the first two bytes of the next write blank.
1280 */
1281 tmp = (u32) (data[0]) << 16;
1282 tmp |= (u32) (data[1]) << 24;
1283 b43_ram_write(dev, ram_offset, tmp);
1284 ram_offset += sizeof(u32);
1285 for (i = 2; i < size; i += sizeof(u32)) {
1286 tmp = (u32) (data[i + 0]);
1287 if (i + 1 < size)
1288 tmp |= (u32) (data[i + 1]) << 8;
1289 if (i + 2 < size)
1290 tmp |= (u32) (data[i + 2]) << 16;
1291 if (i + 3 < size)
1292 tmp |= (u32) (data[i + 3]) << 24;
1293 b43_ram_write(dev, ram_offset + i - 2, tmp);
1294 }
1295 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1296 size + sizeof(struct b43_plcp_hdr6));
1297}
1298
5042c507
MB		 1299/* Check if the use of the antenna that ieee80211 told us to
1300 * use is possible. This will fall back to DEFAULT.
1301 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1302u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1303 u8 antenna_nr)
1304{
1305 u8 antenna_mask;
1306
1307 if (antenna_nr == 0) {
1308 /* Zero means "use default antenna". That's always OK. */
1309 return 0;
1310 }
1311
1312 /* Get the mask of available antennas. */
1313 if (dev->phy.gmode)
1314 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1315 else
1316 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1317
1318 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1319 /* This antenna is not available. Fall back to default. */
1320 return 0;
1321 }
1322
1323 return antenna_nr;
1324}
1325
1326static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1327{
1328 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1329 switch (antenna) {
1330 case 0: /* default/diversity */
1331 return B43_ANTENNA_DEFAULT;
1332 case 1: /* Antenna 0 */
1333 return B43_ANTENNA0;
1334 case 2: /* Antenna 1 */
1335 return B43_ANTENNA1;
1336 case 3: /* Antenna 2 */
1337 return B43_ANTENNA2;
1338 case 4: /* Antenna 3 */
1339 return B43_ANTENNA3;
1340 default:
1341 return B43_ANTENNA_DEFAULT;
1342 }
1343}
1344
1345/* Convert a b43 antenna number value to the PHY TX control value. */
1346static u16 b43_antenna_to_phyctl(int antenna)
1347{
1348 switch (antenna) {
1349 case B43_ANTENNA0:
1350 return B43_TXH_PHY_ANT0;
1351 case B43_ANTENNA1:
1352 return B43_TXH_PHY_ANT1;
1353 case B43_ANTENNA2:
1354 return B43_TXH_PHY_ANT2;
1355 case B43_ANTENNA3:
1356 return B43_TXH_PHY_ANT3;
1357 case B43_ANTENNA_AUTO:
1358 return B43_TXH_PHY_ANT01AUTO;
1359 }
1360 B43_WARN_ON(1);
1361 return 0;
1362}
1363
e4d6b795
MB		 1364static void b43_write_beacon_template(struct b43_wldev *dev,
1365 u16 ram_offset,
5042c507 1366 u16 shm_size_offset)
e4d6b795 1367{
47f76ca3 1368 unsigned int i, len, variable_len;
e66fee6a
MB		 1369 const struct ieee80211_mgmt *bcn;
1370 const u8 *ie;
1371 bool tim_found = 0;
5042c507
MB		 1372 unsigned int rate;
1373 u16 ctl;
1374 int antenna;
e4d6b795 1375
e66fee6a
MB		 1376 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1377 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1378 0x200 - sizeof(struct b43_plcp_hdr6));
5042c507 1379 rate = dev->wl->beacon_txctl.tx_rate->hw_value;
e66fee6a
MB		 1380
1381 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1382 len, ram_offset, shm_size_offset, rate);
e66fee6a 1383
5042c507
MB		 1384 /* Write the PHY TX control parameters. */
1385 antenna = b43_antenna_from_ieee80211(dev,
1386 dev->wl->beacon_txctl.antenna_sel_tx);
1387 antenna = b43_antenna_to_phyctl(antenna);
1388 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1389 /* We can't send beacons with short preamble. Would get PHY errors. */
1390 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1391 ctl &= ~B43_TXH_PHY_ANT;
1392 ctl &= ~B43_TXH_PHY_ENC;
1393 ctl |= antenna;
1394 if (b43_is_cck_rate(rate))
1395 ctl |= B43_TXH_PHY_ENC_CCK;
1396 else
1397 ctl |= B43_TXH_PHY_ENC_OFDM;
1398 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1399
e66fee6a
MB		 1400 /* Find the position of the TIM and the DTIM_period value
1401 * and write them to SHM. */
1402 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1403 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1404 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1405 uint8_t ie_id, ie_len;
1406
1407 ie_id = ie[i];
1408 ie_len = ie[i + 1];
1409 if (ie_id == 5) {
1410 u16 tim_position;
1411 u16 dtim_period;
1412 /* This is the TIM Information Element */
1413
1414 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1415 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1416 break;
1417 /* A valid TIM is at least 4 bytes long. */
1418 if (ie_len < 4)
1419 break;
1420 tim_found = 1;
1421
1422 tim_position = sizeof(struct b43_plcp_hdr6);
1423 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1424 tim_position += i;
1425
1426 dtim_period = ie[i + 3];
1427
1428 b43_shm_write16(dev, B43_SHM_SHARED,
1429 B43_SHM_SH_TIMBPOS, tim_position);
1430 b43_shm_write16(dev, B43_SHM_SHARED,
1431 B43_SHM_SH_DTIMPER, dtim_period);
1432 break;
1433 }
1434 i += ie_len + 2;
1435 }
1436 if (!tim_found) {
1437 b43warn(dev->wl, "Did not find a valid TIM IE in "
1438 "the beacon template packet. AP or IBSS operation "
1439 "may be broken.\n");
a82d9922
MB		 1440 } else
1441 b43dbg(dev->wl, "Updated beacon template\n");
e4d6b795
MB		 1442}
1443
1444static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1445 u16 shm_offset, u16 size,
1446 struct ieee80211_rate *rate)
e4d6b795
MB		 1447{
1448 struct b43_plcp_hdr4 plcp;
1449 u32 tmp;
1450 __le16 dur;
1451
1452 plcp.data = 0;
8318d78a 1453 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1454 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1455 dev->wl->vif, size,
8318d78a 1456 rate);
e4d6b795
MB		 1457 /* Write PLCP in two parts and timing for packet transfer */
1458 tmp = le32_to_cpu(plcp.data);
1459 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1461 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1462}
1463
1464/* Instead of using custom probe response template, this function
1465 * just patches custom beacon template by:
1466 * 1) Changing packet type
1467 * 2) Patching duration field
1468 * 3) Stripping TIM
1469 */
e66fee6a 1470static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1471 u16 *dest_size,
1472 struct ieee80211_rate *rate)
e4d6b795
MB		 1473{
1474 const u8 *src_data;
1475 u8 *dest_data;
1476 u16 src_size, elem_size, src_pos, dest_pos;
1477 __le16 dur;
1478 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1479 size_t ie_start;
1480
1481 src_size = dev->wl->current_beacon->len;
1482 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1483
e66fee6a
MB		 1484 /* Get the start offset of the variable IEs in the packet. */
1485 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1486 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1487
e66fee6a 1488 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1489 return NULL;
e4d6b795
MB		 1490
1491 dest_data = kmalloc(src_size, GFP_ATOMIC);
1492 if (unlikely(!dest_data))
1493 return NULL;
1494
e66fee6a
MB		 1495 /* Copy the static data and all Information Elements, except the TIM. */
1496 memcpy(dest_data, src_data, ie_start);
1497 src_pos = ie_start;
1498 dest_pos = ie_start;
1499 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1500 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1501 if (src_data[src_pos] == 5) {
1502 /* This is the TIM. */
1503 continue;
e4d6b795 1504 }
e66fee6a
MB		 1505 memcpy(dest_data + dest_pos, src_data + src_pos,
1506 elem_size);
1507 dest_pos += elem_size;
e4d6b795
MB		 1508 }
1509 *dest_size = dest_pos;
1510 hdr = (struct ieee80211_hdr *)dest_data;
1511
1512 /* Set the frame control. */
1513 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1514 IEEE80211_STYPE_PROBE_RESP);
1515 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1516 dev->wl->vif, *dest_size,
8318d78a 1517 rate);
e4d6b795
MB		 1518 hdr->duration_id = dur;
1519
1520 return dest_data;
1521}
1522
1523static void b43_write_probe_resp_template(struct b43_wldev *dev,
1524 u16 ram_offset,
8318d78a
JB		 1525 u16 shm_size_offset,
1526 struct ieee80211_rate *rate)
e4d6b795 1527{
e66fee6a 1528 const u8 *probe_resp_data;
e4d6b795
MB		 1529 u16 size;
1530
e66fee6a 1531 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1532 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1533 if (unlikely(!probe_resp_data))
1534 return;
1535
1536 /* Looks like PLCP headers plus packet timings are stored for
1537 * all possible basic rates
1538 */
8318d78a
JB		 1539 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1540 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1541 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1542 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1543
1544 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1545 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1546 size, ram_offset, shm_size_offset,
1547 rate->hw_value);
e4d6b795
MB		 1548 kfree(probe_resp_data);
1549}
1550
6b4bec01
MB		 1551static void b43_upload_beacon0(struct b43_wldev *dev)
1552{
1553 struct b43_wl *wl = dev->wl;
1554
1555 if (wl->beacon0_uploaded)
1556 return;
1557 b43_write_beacon_template(dev, 0x68, 0x18);
1558 /* FIXME: Probe resp upload doesn't really belong here,
1559 * but we don't use that feature anyway. */
1560 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1561 &__b43_ratetable[3]);
1562 wl->beacon0_uploaded = 1;
1563}
1564
1565static void b43_upload_beacon1(struct b43_wldev *dev)
1566{
1567 struct b43_wl *wl = dev->wl;
1568
1569 if (wl->beacon1_uploaded)
1570 return;
1571 b43_write_beacon_template(dev, 0x468, 0x1A);
1572 wl->beacon1_uploaded = 1;
1573}
1574
c97a4ccc
MB		 1575static void handle_irq_beacon(struct b43_wldev *dev)
1576{
1577 struct b43_wl *wl = dev->wl;
1578 u32 cmd, beacon0_valid, beacon1_valid;
1579
1580 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1581 return;
1582
1583 /* This is the bottom half of the asynchronous beacon update. */
1584
1585 /* Ignore interrupt in the future. */
1586 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1587
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1590 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1591
1592 /* Schedule interrupt manually, if busy. */
1593 if (beacon0_valid && beacon1_valid) {
1594 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1595 dev->irq_savedstate |= B43_IRQ_BEACON;
1596 return;
1597 }
1598
6b4bec01
MB		 1599 if (unlikely(wl->beacon_templates_virgin)) {
1600 /* We never uploaded a beacon before.
1601 * Upload both templates now, but only mark one valid. */
1602 wl->beacon_templates_virgin = 0;
1603 b43_upload_beacon0(dev);
1604 b43_upload_beacon1(dev);
c97a4ccc
MB		 1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON0_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1608 } else {
1609 if (!beacon0_valid) {
1610 b43_upload_beacon0(dev);
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 cmd |= B43_MACCMD_BEACON0_VALID;
1613 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1614 } else if (!beacon1_valid) {
1615 b43_upload_beacon1(dev);
1616 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1617 cmd |= B43_MACCMD_BEACON1_VALID;
1618 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1619 }
c97a4ccc
MB		 1620 }
1621}
1622
a82d9922
MB		 1623static void b43_beacon_update_trigger_work(struct work_struct *work)
1624{
1625 struct b43_wl *wl = container_of(work, struct b43_wl,
1626 beacon_update_trigger);
1627 struct b43_wldev *dev;
1628
1629 mutex_lock(&wl->mutex);
1630 dev = wl->current_dev;
1631 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1632 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1633 /* update beacon right away or defer to irq */
1634 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1635 handle_irq_beacon(dev);
1636 /* The handler might have updated the IRQ mask. */
1637 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1638 dev->irq_savedstate);
1639 mmiowb();
a82d9922
MB		 1640 spin_unlock_irq(&wl->irq_lock);
1641 }
1642 mutex_unlock(&wl->mutex);
1643}
1644
d4df6f1a
MB		 1645/* Asynchronously update the packet templates in template RAM.
1646 * Locking: Requires wl->irq_lock to be locked. */
5042c507
MB		 1647static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon,
1648 const struct ieee80211_tx_control *txctl)
e4d6b795 1649{
e66fee6a
MB		 1650 /* This is the top half of the ansynchronous beacon update.
1651 * The bottom half is the beacon IRQ.
1652 * Beacon update must be asynchronous to avoid sending an
1653 * invalid beacon. This can happen for example, if the firmware
1654 * transmits a beacon while we are updating it. */
e4d6b795 1655
e66fee6a
MB		 1656 if (wl->current_beacon)
1657 dev_kfree_skb_any(wl->current_beacon);
1658 wl->current_beacon = beacon;
5042c507 1659 memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
e66fee6a
MB		 1660 wl->beacon0_uploaded = 0;
1661 wl->beacon1_uploaded = 0;
a82d9922 1662 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1663}
1664
1665static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1666{
1667 u32 tmp;
1668 u16 i, len;
1669
1670 len = min((u16) ssid_len, (u16) 0x100);
1671 for (i = 0; i < len; i += sizeof(u32)) {
1672 tmp = (u32) (ssid[i + 0]);
1673 if (i + 1 < len)
1674 tmp |= (u32) (ssid[i + 1]) << 8;
1675 if (i + 2 < len)
1676 tmp |= (u32) (ssid[i + 2]) << 16;
1677 if (i + 3 < len)
1678 tmp |= (u32) (ssid[i + 3]) << 24;
1679 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1680 }
1681 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1682}
1683
1684static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1685{
1686 b43_time_lock(dev);
1687 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1688 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1689 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1690 } else {
1691 b43_write16(dev, 0x606, (beacon_int >> 6));
1692 b43_write16(dev, 0x610, beacon_int);
1693 }
1694 b43_time_unlock(dev);
a82d9922 1695 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1696}
1697
e4d6b795
MB		 1698static void handle_irq_ucode_debug(struct b43_wldev *dev)
1699{
1700 //TODO
1701}
1702
1703/* Interrupt handler bottom-half */
1704static void b43_interrupt_tasklet(struct b43_wldev *dev)
1705{
1706 u32 reason;
1707 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1708 u32 merged_dma_reason = 0;
21954c36 1709 int i;
e4d6b795
MB		 1710 unsigned long flags;
1711
1712 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1713
1714 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1715
1716 reason = dev->irq_reason;
1717 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1718 dma_reason[i] = dev->dma_reason[i];
1719 merged_dma_reason |= dma_reason[i];
1720 }
1721
1722 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1723 b43err(dev->wl, "MAC transmission error\n");
1724
00e0b8cb 1725 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1726 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1727 rmb();
1728 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1729 atomic_set(&dev->phy.txerr_cnt,
1730 B43_PHY_TX_BADNESS_LIMIT);
1731 b43err(dev->wl, "Too many PHY TX errors, "
1732 "restarting the controller\n");
1733 b43_controller_restart(dev, "PHY TX errors");
1734 }
1735 }
e4d6b795
MB		 1736
1737 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1738 B43_DMAIRQ_NONFATALMASK))) {
1739 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1740 b43err(dev->wl, "Fatal DMA error: "
1741 "0x%08X, 0x%08X, 0x%08X, "
1742 "0x%08X, 0x%08X, 0x%08X\n",
1743 dma_reason[0], dma_reason[1],
1744 dma_reason[2], dma_reason[3],
1745 dma_reason[4], dma_reason[5]);
1746 b43_controller_restart(dev, "DMA error");
1747 mmiowb();
1748 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1749 return;
1750 }
1751 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1752 b43err(dev->wl, "DMA error: "
1753 "0x%08X, 0x%08X, 0x%08X, "
1754 "0x%08X, 0x%08X, 0x%08X\n",
1755 dma_reason[0], dma_reason[1],
1756 dma_reason[2], dma_reason[3],
1757 dma_reason[4], dma_reason[5]);
1758 }
1759 }
1760
1761 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1762 handle_irq_ucode_debug(dev);
1763 if (reason & B43_IRQ_TBTT_INDI)
1764 handle_irq_tbtt_indication(dev);
1765 if (reason & B43_IRQ_ATIM_END)
1766 handle_irq_atim_end(dev);
1767 if (reason & B43_IRQ_BEACON)
1768 handle_irq_beacon(dev);
1769 if (reason & B43_IRQ_PMQ)
1770 handle_irq_pmq(dev);
21954c36
MB		 1771 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1772 ;/* TODO */
1773 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1774 handle_irq_noise(dev);
1775
1776 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1777 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1778 if (b43_using_pio_transfers(dev))
1779 b43_pio_rx(dev->pio.rx_queue);
1780 else
1781 b43_dma_rx(dev->dma.rx_ring);
1782 }
e4d6b795
MB		 1783 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1784 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1785 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1786 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1787 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1788
21954c36 1789 if (reason & B43_IRQ_TX_OK)
e4d6b795 1790 handle_irq_transmit_status(dev);
e4d6b795 1791
e4d6b795
MB		 1792 b43_interrupt_enable(dev, dev->irq_savedstate);
1793 mmiowb();
1794 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1795}
1796
e4d6b795
MB		 1797static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1798{
e4d6b795
MB		 1799 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1800
1801 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1802 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1803 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1804 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1805 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1806 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1807}
1808
1809/* Interrupt handler top-half */
1810static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1811{
1812 irqreturn_t ret = IRQ_NONE;
1813 struct b43_wldev *dev = dev_id;
1814 u32 reason;
1815
1816 if (!dev)
1817 return IRQ_NONE;
1818
1819 spin_lock(&dev->wl->irq_lock);
1820
1821 if (b43_status(dev) < B43_STAT_STARTED)
1822 goto out;
1823 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1824 if (reason == 0xffffffff) /* shared IRQ */
1825 goto out;
1826 ret = IRQ_HANDLED;
1827 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1828 if (!reason)
1829 goto out;
1830
1831 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1832 & 0x0001DC00;
1833 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1834 & 0x0000DC00;
1835 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1836 & 0x0000DC00;
1837 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1838 & 0x0001DC00;
1839 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1840 & 0x0000DC00;
1841 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1842 & 0x0000DC00;
1843
1844 b43_interrupt_ack(dev, reason);
1845 /* disable all IRQs. They are enabled again in the bottom half. */
1846 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1847 /* save the reason code and call our bottom half. */
1848 dev->irq_reason = reason;
1849 tasklet_schedule(&dev->isr_tasklet);
1850 out:
1851 mmiowb();
1852 spin_unlock(&dev->wl->irq_lock);
1853
1854 return ret;
1855}
1856
61cb5dd6
MB		 1857static void do_release_fw(struct b43_firmware_file *fw)
1858{
1859 release_firmware(fw->data);
1860 fw->data = NULL;
1861 fw->filename = NULL;
1862}
1863
e4d6b795
MB		 1864static void b43_release_firmware(struct b43_wldev *dev)
1865{
61cb5dd6
MB		 1866 do_release_fw(&dev->fw.ucode);
1867 do_release_fw(&dev->fw.pcm);
1868 do_release_fw(&dev->fw.initvals);
1869 do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1870}
1871
eb189d8b 1872static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1873{
eb189d8b
MB		 1874 const char *text;
1875
1876 text = "You must go to "
354807e0 1877 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 1878 "and download the latest firmware (version 4).\n";
1879 if (error)
1880 b43err(wl, text);
1881 else
1882 b43warn(wl, text);
e4d6b795
MB		 1883}
1884
1885static int do_request_fw(struct b43_wldev *dev,
1886 const char *name,
61cb5dd6 1887 struct b43_firmware_file *fw)
e4d6b795 1888{
1a09404a 1889 char path[sizeof(modparam_fwpostfix) + 32];
61cb5dd6 1890 const struct firmware *blob;
e4d6b795
MB		 1891 struct b43_fw_header *hdr;
1892 u32 size;
1893 int err;
1894
61cb5dd6
MB		 1895 if (!name) {
1896 /* Don't fetch anything. Free possibly cached firmware. */
1897 do_release_fw(fw);
e4d6b795 1898 return 0;
61cb5dd6
MB		 1899 }
1900 if (fw->filename) {
1901 if (strcmp(fw->filename, name) == 0)
1902 return 0; /* Already have this fw. */
1903 /* Free the cached firmware first. */
1904 do_release_fw(fw);
1905 }
e4d6b795
MB		 1906
1907 snprintf(path, ARRAY_SIZE(path),
1908 "b43%s/%s.fw",
1909 modparam_fwpostfix, name);
61cb5dd6 1910 err = request_firmware(&blob, path, dev->dev->dev);
e4d6b795
MB		 1911 if (err) {
1912 b43err(dev->wl, "Firmware file \"%s\" not found "
1913 "or load failed.\n", path);
1914 return err;
1915 }
61cb5dd6 1916 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 1917 goto err_format;
61cb5dd6 1918 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 1919 switch (hdr->type) {
1920 case B43_FW_TYPE_UCODE:
1921 case B43_FW_TYPE_PCM:
1922 size = be32_to_cpu(hdr->size);
61cb5dd6 1923 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 1924 goto err_format;
1925 /* fallthrough */
1926 case B43_FW_TYPE_IV:
1927 if (hdr->ver != 1)
1928 goto err_format;
1929 break;
1930 default:
1931 goto err_format;
1932 }
1933
61cb5dd6
MB		 1934 fw->data = blob;
1935 fw->filename = name;
1936
1937 return 0;
e4d6b795
MB		 1938
1939err_format:
1940 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
61cb5dd6
MB		 1941 release_firmware(blob);
1942
e4d6b795
MB		 1943 return -EPROTO;
1944}
1945
1946static int b43_request_firmware(struct b43_wldev *dev)
1947{
1948 struct b43_firmware *fw = &dev->fw;
1949 const u8 rev = dev->dev->id.revision;
1950 const char *filename;
1951 u32 tmshigh;
1952 int err;
1953
61cb5dd6 1954 /* Get microcode */
e4d6b795 1955 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 1956 if ((rev >= 5) && (rev <= 10))
1957 filename = "ucode5";
1958 else if ((rev >= 11) && (rev <= 12))
1959 filename = "ucode11";
1960 else if (rev >= 13)
1961 filename = "ucode13";
1962 else
1963 goto err_no_ucode;
1964 err = do_request_fw(dev, filename, &fw->ucode);
1965 if (err)
1966 goto err_load;
1967
1968 /* Get PCM code */
1969 if ((rev >= 5) && (rev <= 10))
1970 filename = "pcm5";
1971 else if (rev >= 11)
1972 filename = NULL;
1973 else
1974 goto err_no_pcm;
1975 err = do_request_fw(dev, filename, &fw->pcm);
1976 if (err)
1977 goto err_load;
1978
1979 /* Get initvals */
1980 switch (dev->phy.type) {
1981 case B43_PHYTYPE_A:
1982 if ((rev >= 5) && (rev <= 10)) {
1983 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1984 filename = "a0g1initvals5";
1985 else
1986 filename = "a0g0initvals5";
1987 } else
1988 goto err_no_initvals;
1989 break;
1990 case B43_PHYTYPE_G:
e4d6b795 1991 if ((rev >= 5) && (rev <= 10))
61cb5dd6 1992 filename = "b0g0initvals5";
e4d6b795 1993 else if (rev >= 13)
61cb5dd6 1994 filename = "lp0initvals13";
e4d6b795 1995 else
61cb5dd6
MB		 1996 goto err_no_initvals;
1997 break;
1998 case B43_PHYTYPE_N:
1999 if ((rev >= 11) && (rev <= 12))
2000 filename = "n0initvals11";
2001 else
2002 goto err_no_initvals;
2003 break;
2004 default:
2005 goto err_no_initvals;
e4d6b795 2006 }
61cb5dd6
MB		 2007 err = do_request_fw(dev, filename, &fw->initvals);
2008 if (err)
2009 goto err_load;
2010
2011 /* Get bandswitch initvals */
2012 switch (dev->phy.type) {
2013 case B43_PHYTYPE_A:
2014 if ((rev >= 5) && (rev <= 10)) {
2015 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2016 filename = "a0g1bsinitvals5";
2017 else
2018 filename = "a0g0bsinitvals5";
2019 } else if (rev >= 11)
2020 filename = NULL;
2021 else
2022 goto err_no_initvals;
2023 break;
2024 case B43_PHYTYPE_G:
e4d6b795 2025 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2026 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2027 else if (rev >= 11)
2028 filename = NULL;
2029 else
e4d6b795 2030 goto err_no_initvals;
61cb5dd6
MB		 2031 break;
2032 case B43_PHYTYPE_N:
2033 if ((rev >= 11) && (rev <= 12))
2034 filename = "n0bsinitvals11";
2035 else
e4d6b795 2036 goto err_no_initvals;
61cb5dd6
MB		 2037 break;
2038 default:
2039 goto err_no_initvals;
e4d6b795 2040 }
61cb5dd6
MB		 2041 err = do_request_fw(dev, filename, &fw->initvals_band);
2042 if (err)
2043 goto err_load;
e4d6b795
MB		 2044
2045 return 0;
2046
2047err_load:
eb189d8b 2048 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2049 goto error;
2050
2051err_no_ucode:
2052 err = -ENODEV;
2053 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2054 goto error;
2055
2056err_no_pcm:
2057 err = -ENODEV;
2058 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2059 goto error;
2060
2061err_no_initvals:
2062 err = -ENODEV;
2063 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2064 "core rev %u\n", dev->phy.type, rev);
2065 goto error;
2066
2067error:
2068 b43_release_firmware(dev);
2069 return err;
2070}
2071
2072static int b43_upload_microcode(struct b43_wldev *dev)
2073{
2074 const size_t hdr_len = sizeof(struct b43_fw_header);
2075 const __be32 *data;
2076 unsigned int i, len;
2077 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2078 u32 tmp, macctl;
e4d6b795
MB		 2079 int err = 0;
2080
1f7d87b0
MB		 2081 /* Jump the microcode PSM to offset 0 */
2082 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2083 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2084 macctl |= B43_MACCTL_PSM_JMP0;
2085 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2086 /* Zero out all microcode PSM registers and shared memory. */
2087 for (i = 0; i < 64; i++)
2088 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2089 for (i = 0; i < 4096; i += 2)
2090 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2091
e4d6b795 2092 /* Upload Microcode. */
61cb5dd6
MB		 2093 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2094 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2095 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2096 for (i = 0; i < len; i++) {
2097 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2098 udelay(10);
2099 }
2100
61cb5dd6 2101 if (dev->fw.pcm.data) {
e4d6b795 2102 /* Upload PCM data. */
61cb5dd6
MB		 2103 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2104 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2105 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2106 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2107 /* No need for autoinc bit in SHM_HW */
2108 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2109 for (i = 0; i < len; i++) {
2110 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2111 udelay(10);
2112 }
2113 }
2114
2115 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2116
2117 /* Start the microcode PSM */
2118 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2119 macctl &= ~B43_MACCTL_PSM_JMP0;
2120 macctl |= B43_MACCTL_PSM_RUN;
2121 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2122
2123 /* Wait for the microcode to load and respond */
2124 i = 0;
2125 while (1) {
2126 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2127 if (tmp == B43_IRQ_MAC_SUSPENDED)
2128 break;
2129 i++;
1f7d87b0 2130 if (i >= 20) {
e4d6b795 2131 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2132 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2133 err = -ENODEV;
1f7d87b0
MB		 2134 goto error;
2135 }
2136 msleep_interruptible(50);
2137 if (signal_pending(current)) {
2138 err = -EINTR;
2139 goto error;
e4d6b795 2140 }
e4d6b795
MB		 2141 }
2142 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2143
2144 /* Get and check the revisions. */
2145 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2146 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2147 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2148 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2149
2150 if (fwrev <= 0x128) {
2151 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2152 "binary drivers older than version 4.x is unsupported. "
2153 "You must upgrade your firmware files.\n");
eb189d8b 2154 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2155 err = -EOPNOTSUPP;
1f7d87b0 2156 goto error;
e4d6b795 2157 }
588e6cdf
MB		 2158 b43info(dev->wl, "Loading firmware version %u.%u "
2159 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2160 fwrev, fwpatch,
2161 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2162 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
e4d6b795
MB		 2163
2164 dev->fw.rev = fwrev;
2165 dev->fw.patch = fwpatch;
2166
eb189d8b
MB		 2167 if (b43_is_old_txhdr_format(dev)) {
2168 b43warn(dev->wl, "You are using an old firmware image. "
2169 "Support for old firmware will be removed in July 2008.\n");
2170 b43_print_fw_helptext(dev->wl, 0);
2171 }
2172
1f7d87b0
MB		 2173 return 0;
2174
2175error:
2176 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2177 macctl &= ~B43_MACCTL_PSM_RUN;
2178 macctl |= B43_MACCTL_PSM_JMP0;
2179 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2180
e4d6b795
MB		 2181 return err;
2182}
2183
2184static int b43_write_initvals(struct b43_wldev *dev,
2185 const struct b43_iv *ivals,
2186 size_t count,
2187 size_t array_size)
2188{
2189 const struct b43_iv *iv;
2190 u16 offset;
2191 size_t i;
2192 bool bit32;
2193
2194 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2195 iv = ivals;
2196 for (i = 0; i < count; i++) {
2197 if (array_size < sizeof(iv->offset_size))
2198 goto err_format;
2199 array_size -= sizeof(iv->offset_size);
2200 offset = be16_to_cpu(iv->offset_size);
2201 bit32 = !!(offset & B43_IV_32BIT);
2202 offset &= B43_IV_OFFSET_MASK;
2203 if (offset >= 0x1000)
2204 goto err_format;
2205 if (bit32) {
2206 u32 value;
2207
2208 if (array_size < sizeof(iv->data.d32))
2209 goto err_format;
2210 array_size -= sizeof(iv->data.d32);
2211
533dd1b0 2212 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2213 b43_write32(dev, offset, value);
2214
2215 iv = (const struct b43_iv *)((const uint8_t *)iv +
2216 sizeof(__be16) +
2217 sizeof(__be32));
2218 } else {
2219 u16 value;
2220
2221 if (array_size < sizeof(iv->data.d16))
2222 goto err_format;
2223 array_size -= sizeof(iv->data.d16);
2224
2225 value = be16_to_cpu(iv->data.d16);
2226 b43_write16(dev, offset, value);
2227
2228 iv = (const struct b43_iv *)((const uint8_t *)iv +
2229 sizeof(__be16) +
2230 sizeof(__be16));
2231 }
2232 }
2233 if (array_size)
2234 goto err_format;
2235
2236 return 0;
2237
2238err_format:
2239 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2240 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2241
2242 return -EPROTO;
2243}
2244
2245static int b43_upload_initvals(struct b43_wldev *dev)
2246{
2247 const size_t hdr_len = sizeof(struct b43_fw_header);
2248 const struct b43_fw_header *hdr;
2249 struct b43_firmware *fw = &dev->fw;
2250 const struct b43_iv *ivals;
2251 size_t count;
2252 int err;
2253
61cb5dd6
MB		 2254 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2255 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2256 count = be32_to_cpu(hdr->size);
2257 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2258 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2259 if (err)
2260 goto out;
61cb5dd6
MB		 2261 if (fw->initvals_band.data) {
2262 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2263 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2264 count = be32_to_cpu(hdr->size);
2265 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2266 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2267 if (err)
2268 goto out;
2269 }
2270out:
2271
2272 return err;
2273}
2274
2275/* Initialize the GPIOs
2276 * http://bcm-specs.sipsolutions.net/GPIO
2277 */
2278static int b43_gpio_init(struct b43_wldev *dev)
2279{
2280 struct ssb_bus *bus = dev->dev->bus;
2281 struct ssb_device *gpiodev, *pcidev = NULL;
2282 u32 mask, set;
2283
2284 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2285 & ~B43_MACCTL_GPOUTSMSK);
2286
e4d6b795
MB		 2287 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2288 | 0x000F);
2289
2290 mask = 0x0000001F;
2291 set = 0x0000000F;
2292 if (dev->dev->bus->chip_id == 0x4301) {
2293 mask |= 0x0060;
2294 set |= 0x0060;
2295 }
2296 if (0 /* FIXME: conditional unknown */ ) {
2297 b43_write16(dev, B43_MMIO_GPIO_MASK,
2298 b43_read16(dev, B43_MMIO_GPIO_MASK)
2299 | 0x0100);
2300 mask |= 0x0180;
2301 set |= 0x0180;
2302 }
95de2841 2303 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2304 b43_write16(dev, B43_MMIO_GPIO_MASK,
2305 b43_read16(dev, B43_MMIO_GPIO_MASK)
2306 | 0x0200);
2307 mask |= 0x0200;
2308 set |= 0x0200;
2309 }
2310 if (dev->dev->id.revision >= 2)
2311 mask |= 0x0010; /* FIXME: This is redundant. */
2312
2313#ifdef CONFIG_SSB_DRIVER_PCICORE
2314 pcidev = bus->pcicore.dev;
2315#endif
2316 gpiodev = bus->chipco.dev ? : pcidev;
2317 if (!gpiodev)
2318 return 0;
2319 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2320 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2321 & mask) | set);
2322
2323 return 0;
2324}
2325
2326/* Turn off all GPIO stuff. Call this on module unload, for example. */
2327static void b43_gpio_cleanup(struct b43_wldev *dev)
2328{
2329 struct ssb_bus *bus = dev->dev->bus;
2330 struct ssb_device *gpiodev, *pcidev = NULL;
2331
2332#ifdef CONFIG_SSB_DRIVER_PCICORE
2333 pcidev = bus->pcicore.dev;
2334#endif
2335 gpiodev = bus->chipco.dev ? : pcidev;
2336 if (!gpiodev)
2337 return;
2338 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2339}
2340
2341/* http://bcm-specs.sipsolutions.net/EnableMac */
affe0a02 2342static void b43_mac_enable(struct b43_wldev *dev)
e4d6b795
MB		 2343{
2344 dev->mac_suspended--;
2345 B43_WARN_ON(dev->mac_suspended < 0);
2346 if (dev->mac_suspended == 0) {
2347 b43_write32(dev, B43_MMIO_MACCTL,
2348 b43_read32(dev, B43_MMIO_MACCTL)
2349 | B43_MACCTL_ENABLED);
2350 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2351 B43_IRQ_MAC_SUSPENDED);
2352 /* Commit writes */
2353 b43_read32(dev, B43_MMIO_MACCTL);
2354 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2355 b43_power_saving_ctl_bits(dev, 0);
05b64b36
MB		 2356
2357 /* Re-enable IRQs. */
2358 spin_lock_irq(&dev->wl->irq_lock);
2359 b43_interrupt_enable(dev, dev->irq_savedstate);
2360 spin_unlock_irq(&dev->wl->irq_lock);
e4d6b795
MB		 2361 }
2362}
2363
2364/* http://bcm-specs.sipsolutions.net/SuspendMAC */
affe0a02 2365static void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2366{
2367 int i;
2368 u32 tmp;
2369
05b64b36 2370 might_sleep();
e4d6b795 2371 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2372
e4d6b795 2373 if (dev->mac_suspended == 0) {
05b64b36
MB		 2374 /* Mask IRQs before suspending MAC. Otherwise
2375 * the MAC stays busy and won't suspend. */
2376 spin_lock_irq(&dev->wl->irq_lock);
2377 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2378 spin_unlock_irq(&dev->wl->irq_lock);
2379 b43_synchronize_irq(dev);
2380 dev->irq_savedstate = tmp;
2381
e4d6b795
MB		 2382 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2383 b43_write32(dev, B43_MMIO_MACCTL,
2384 b43_read32(dev, B43_MMIO_MACCTL)
2385 & ~B43_MACCTL_ENABLED);
2386 /* force pci to flush the write */
2387 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2388 for (i = 35; i; i--) {
2389 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2390 if (tmp & B43_IRQ_MAC_SUSPENDED)
2391 goto out;
2392 udelay(10);
2393 }
2394 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2395 for (i = 40; i; i--) {
e4d6b795
MB		 2396 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2397 if (tmp & B43_IRQ_MAC_SUSPENDED)
2398 goto out;
05b64b36 2399 msleep(1);
e4d6b795
MB		 2400 }
2401 b43err(dev->wl, "MAC suspend failed\n");
2402 }
05b64b36 2403out:
e4d6b795
MB		 2404 dev->mac_suspended++;
2405}
2406
2407static void b43_adjust_opmode(struct b43_wldev *dev)
2408{
2409 struct b43_wl *wl = dev->wl;
2410 u32 ctl;
2411 u16 cfp_pretbtt;
2412
2413 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2414 /* Reset status to STA infrastructure mode. */
2415 ctl &= ~B43_MACCTL_AP;
2416 ctl &= ~B43_MACCTL_KEEP_CTL;
2417 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2418 ctl &= ~B43_MACCTL_KEEP_BAD;
2419 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2420 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2421 ctl |= B43_MACCTL_INFRA;
2422
4150c572
JB		 2423 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2424 ctl |= B43_MACCTL_AP;
2425 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2426 ctl &= ~B43_MACCTL_INFRA;
2427
2428 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2429 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2430 if (wl->filter_flags & FIF_FCSFAIL)
2431 ctl |= B43_MACCTL_KEEP_BAD;
2432 if (wl->filter_flags & FIF_PLCPFAIL)
2433 ctl |= B43_MACCTL_KEEP_BADPLCP;
2434 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2435 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2436 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2437 ctl |= B43_MACCTL_BEACPROMISC;
2438
e4d6b795
MB		 2439 /* Workaround: On old hardware the HW-MAC-address-filter
2440 * doesn't work properly, so always run promisc in filter
2441 * it in software. */
2442 if (dev->dev->id.revision <= 4)
2443 ctl |= B43_MACCTL_PROMISC;
2444
2445 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2446
2447 cfp_pretbtt = 2;
2448 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2449 if (dev->dev->bus->chip_id == 0x4306 &&
2450 dev->dev->bus->chip_rev == 3)
2451 cfp_pretbtt = 100;
2452 else
2453 cfp_pretbtt = 50;
2454 }
2455 b43_write16(dev, 0x612, cfp_pretbtt);
2456}
2457
2458static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2459{
2460 u16 offset;
2461
2462 if (is_ofdm) {
2463 offset = 0x480;
2464 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2465 } else {
2466 offset = 0x4C0;
2467 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2468 }
2469 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2470 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2471}
2472
2473static void b43_rate_memory_init(struct b43_wldev *dev)
2474{
2475 switch (dev->phy.type) {
2476 case B43_PHYTYPE_A:
2477 case B43_PHYTYPE_G:
53a6e234 2478 case B43_PHYTYPE_N:
e4d6b795
MB		 2479 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2480 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2481 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2482 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2483 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2484 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2485 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2486 if (dev->phy.type == B43_PHYTYPE_A)
2487 break;
2488 /* fallthrough */
2489 case B43_PHYTYPE_B:
2490 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2491 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2492 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2493 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2494 break;
2495 default:
2496 B43_WARN_ON(1);
2497 }
2498}
2499
5042c507
MB		 2500/* Set the default values for the PHY TX Control Words. */
2501static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2502{
2503 u16 ctl = 0;
2504
2505 ctl |= B43_TXH_PHY_ENC_CCK;
2506 ctl |= B43_TXH_PHY_ANT01AUTO;
2507 ctl |= B43_TXH_PHY_TXPWR;
2508
2509 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2512}
2513
e4d6b795
MB		 2514/* Set the TX-Antenna for management frames sent by firmware. */
2515static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2516{
5042c507 2517 u16 ant;
e4d6b795
MB		 2518 u16 tmp;
2519
5042c507 2520 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2521
e4d6b795
MB		 2522 /* For ACK/CTS */
2523 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2524 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2526 /* For Probe Resposes */
2527 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2528 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2529 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2530}
2531
2532/* This is the opposite of b43_chip_init() */
2533static void b43_chip_exit(struct b43_wldev *dev)
2534{
8e9f7529 2535 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 2536 b43_gpio_cleanup(dev);
2537 /* firmware is released later */
2538}
2539
2540/* Initialize the chip
2541 * http://bcm-specs.sipsolutions.net/ChipInit
2542 */
2543static int b43_chip_init(struct b43_wldev *dev)
2544{
2545 struct b43_phy *phy = &dev->phy;
2546 int err, tmp;
1f7d87b0 2547 u32 value32, macctl;
e4d6b795
MB		 2548 u16 value16;
2549
1f7d87b0
MB		 2550 /* Initialize the MAC control */
2551 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2552 if (dev->phy.gmode)
2553 macctl |= B43_MACCTL_GMODE;
2554 macctl |= B43_MACCTL_INFRA;
2555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2556
2557 err = b43_request_firmware(dev);
2558 if (err)
2559 goto out;
2560 err = b43_upload_microcode(dev);
2561 if (err)
2562 goto out; /* firmware is released later */
2563
2564 err = b43_gpio_init(dev);
2565 if (err)
2566 goto out; /* firmware is released later */
21954c36 2567
e4d6b795
MB		 2568 err = b43_upload_initvals(dev);
2569 if (err)
1a8d1227 2570 goto err_gpio_clean;
e4d6b795 2571 b43_radio_turn_on(dev);
e4d6b795
MB		 2572
2573 b43_write16(dev, 0x03E6, 0x0000);
2574 err = b43_phy_init(dev);
2575 if (err)
2576 goto err_radio_off;
2577
2578 /* Select initial Interference Mitigation. */
2579 tmp = phy->interfmode;
2580 phy->interfmode = B43_INTERFMODE_NONE;
2581 b43_radio_set_interference_mitigation(dev, tmp);
2582
2583 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2584 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2585
2586 if (phy->type == B43_PHYTYPE_B) {
2587 value16 = b43_read16(dev, 0x005E);
2588 value16 |= 0x0004;
2589 b43_write16(dev, 0x005E, value16);
2590 }
2591 b43_write32(dev, 0x0100, 0x01000000);
2592 if (dev->dev->id.revision < 5)
2593 b43_write32(dev, 0x010C, 0x01000000);
2594
2595 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2596 & ~B43_MACCTL_INFRA);
2597 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2598 | B43_MACCTL_INFRA);
e4d6b795 2599
e4d6b795
MB		 2600 /* Probe Response Timeout value */
2601 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2602 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2603
2604 /* Initially set the wireless operation mode. */
2605 b43_adjust_opmode(dev);
2606
2607 if (dev->dev->id.revision < 3) {
2608 b43_write16(dev, 0x060E, 0x0000);
2609 b43_write16(dev, 0x0610, 0x8000);
2610 b43_write16(dev, 0x0604, 0x0000);
2611 b43_write16(dev, 0x0606, 0x0200);
2612 } else {
2613 b43_write32(dev, 0x0188, 0x80000000);
2614 b43_write32(dev, 0x018C, 0x02000000);
2615 }
2616 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2617 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2618 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2619 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2620 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2621 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2622 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2623
2624 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2625 value32 |= 0x00100000;
2626 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2627
2628 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2629 dev->dev->bus->chipco.fast_pwrup_delay);
2630
2631 err = 0;
2632 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2633out:
e4d6b795
MB		 2634 return err;
2635
21954c36 2636err_radio_off:
8e9f7529 2637 b43_radio_turn_off(dev, 1);
1a8d1227 2638err_gpio_clean:
e4d6b795 2639 b43_gpio_cleanup(dev);
21954c36 2640 return err;
e4d6b795
MB		 2641}
2642
2643static void b43_periodic_every120sec(struct b43_wldev *dev)
2644{
2645 struct b43_phy *phy = &dev->phy;
2646
2647 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2648 return;
2649
2650 b43_mac_suspend(dev);
2651 b43_lo_g_measure(dev);
2652 b43_mac_enable(dev);
2653 if (b43_has_hardware_pctl(phy))
2654 b43_lo_g_ctl_mark_all_unused(dev);
2655}
2656
2657static void b43_periodic_every60sec(struct b43_wldev *dev)
2658{
2659 struct b43_phy *phy = &dev->phy;
2660
53a6e234
MB		 2661 if (phy->type != B43_PHYTYPE_G)
2662 return;
e4d6b795
MB		 2663 if (!b43_has_hardware_pctl(phy))
2664 b43_lo_g_ctl_mark_all_unused(dev);
95de2841 2665 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
e4d6b795
MB		 2666 b43_mac_suspend(dev);
2667 b43_calc_nrssi_slope(dev);
2668 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2669 u8 old_chan = phy->channel;
2670
2671 /* VCO Calibration */
2672 if (old_chan >= 8)
2673 b43_radio_selectchannel(dev, 1, 0);
2674 else
2675 b43_radio_selectchannel(dev, 13, 0);
2676 b43_radio_selectchannel(dev, old_chan, 0);
2677 }
2678 b43_mac_enable(dev);
2679 }
2680}
2681
2682static void b43_periodic_every30sec(struct b43_wldev *dev)
2683{
2684 /* Update device statistics. */
2685 b43_calculate_link_quality(dev);
2686}
2687
2688static void b43_periodic_every15sec(struct b43_wldev *dev)
2689{
2690 struct b43_phy *phy = &dev->phy;
2691
2692 if (phy->type == B43_PHYTYPE_G) {
2693 //TODO: update_aci_moving_average
2694 if (phy->aci_enable && phy->aci_wlan_automatic) {
2695 b43_mac_suspend(dev);
2696 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2697 if (0 /*TODO: bunch of conditions */ ) {
2698 b43_radio_set_interference_mitigation
2699 (dev, B43_INTERFMODE_MANUALWLAN);
2700 }
2701 } else if (1 /*TODO*/) {
2702 /*
2703 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2704 b43_radio_set_interference_mitigation(dev,
2705 B43_INTERFMODE_NONE);
2706 }
2707 */
2708 }
2709 b43_mac_enable(dev);
2710 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2711 phy->rev == 1) {
2712 //TODO: implement rev1 workaround
2713 }
2714 }
2715 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2716 //TODO for APHY (temperature?)
00e0b8cb
SB		 2717
2718 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2719 wmb();
e4d6b795
MB		 2720}
2721
e4d6b795
MB		 2722static void do_periodic_work(struct b43_wldev *dev)
2723{
2724 unsigned int state;
2725
2726 state = dev->periodic_state;
42bb4cd5 2727 if (state % 8 == 0)
e4d6b795 2728 b43_periodic_every120sec(dev);
42bb4cd5 2729 if (state % 4 == 0)
e4d6b795 2730 b43_periodic_every60sec(dev);
42bb4cd5 2731 if (state % 2 == 0)
e4d6b795 2732 b43_periodic_every30sec(dev);
42bb4cd5 2733 b43_periodic_every15sec(dev);
e4d6b795
MB		 2734}
2735
05b64b36
MB		 2736/* Periodic work locking policy:
2737 * The whole periodic work handler is protected by
2738 * wl->mutex. If another lock is needed somewhere in the
2739 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2740 */
e4d6b795
MB		 2741static void b43_periodic_work_handler(struct work_struct *work)
2742{
05b64b36
MB		 2743 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2744 periodic_work.work);
2745 struct b43_wl *wl = dev->wl;
2746 unsigned long delay;
e4d6b795 2747
05b64b36 2748 mutex_lock(&wl->mutex);
e4d6b795
MB		 2749
2750 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2751 goto out;
2752 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2753 goto out_requeue;
2754
05b64b36 2755 do_periodic_work(dev);
e4d6b795 2756
e4d6b795 2757 dev->periodic_state++;
42bb4cd5 2758out_requeue:
e4d6b795
MB		 2759 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2760 delay = msecs_to_jiffies(50);
2761 else
82cd682d 2762 delay = round_jiffies_relative(HZ * 15);
05b64b36 2763 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2764out:
05b64b36 2765 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2766}
2767
2768static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2769{
2770 struct delayed_work *work = &dev->periodic_work;
2771
2772 dev->periodic_state = 0;
2773 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2774 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2775}
2776
f3dd3fcc 2777/* Check if communication with the device works correctly. */
e4d6b795
MB		 2778static int b43_validate_chipaccess(struct b43_wldev *dev)
2779{
f3dd3fcc 2780 u32 v, backup;
e4d6b795 2781
f3dd3fcc
MB		 2782 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2783
2784 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2785 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2786 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2787 goto error;
f3dd3fcc
MB		 2788 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2789 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2790 goto error;
2791
f3dd3fcc
MB		 2792 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2793
2794 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2795 /* The 32bit register shadows the two 16bit registers
2796 * with update sideeffects. Validate this. */
2797 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2798 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2799 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2800 goto error;
2801 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2802 goto error;
2803 }
2804 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2805
2806 v = b43_read32(dev, B43_MMIO_MACCTL);
2807 v |= B43_MACCTL_GMODE;
2808 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2809 goto error;
2810
2811 return 0;
f3dd3fcc 2812error:
e4d6b795
MB		 2813 b43err(dev->wl, "Failed to validate the chipaccess\n");
2814 return -ENODEV;
2815}
2816
2817static void b43_security_init(struct b43_wldev *dev)
2818{
2819 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2820 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2821 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2822 /* KTP is a word address, but we address SHM bytewise.
2823 * So multiply by two.
2824 */
2825 dev->ktp *= 2;
2826 if (dev->dev->id.revision >= 5) {
2827 /* Number of RCMTA address slots */
2828 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2829 }
2830 b43_clear_keys(dev);
2831}
2832
2833static int b43_rng_read(struct hwrng *rng, u32 * data)
2834{
2835 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2836 unsigned long flags;
2837
2838 /* Don't take wl->mutex here, as it could deadlock with
2839 * hwrng internal locking. It's not needed to take
2840 * wl->mutex here, anyway. */
2841
2842 spin_lock_irqsave(&wl->irq_lock, flags);
2843 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2844 spin_unlock_irqrestore(&wl->irq_lock, flags);
2845
2846 return (sizeof(u16));
2847}
2848
b844eba2 2849static void b43_rng_exit(struct b43_wl *wl)
e4d6b795
MB		 2850{
2851 if (wl->rng_initialized)
b844eba2 2852 hwrng_unregister(&wl->rng);
e4d6b795
MB		 2853}
2854
2855static int b43_rng_init(struct b43_wl *wl)
2856{
2857 int err;
2858
2859 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2860 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2861 wl->rng.name = wl->rng_name;
2862 wl->rng.data_read = b43_rng_read;
2863 wl->rng.priv = (unsigned long)wl;
2864 wl->rng_initialized = 1;
2865 err = hwrng_register(&wl->rng);
2866 if (err) {
2867 wl->rng_initialized = 0;
2868 b43err(wl, "Failed to register the random "
2869 "number generator (%d)\n", err);
2870 }
2871
2872 return err;
2873}
2874
40faacc4
MB		 2875static int b43_op_tx(struct ieee80211_hw *hw,
2876 struct sk_buff *skb,
2877 struct ieee80211_tx_control *ctl)
e4d6b795
MB		 2878{
2879 struct b43_wl *wl = hw_to_b43_wl(hw);
2880 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 2881 unsigned long flags;
2882 int err;
e4d6b795 2883
5100d5ac
MB		 2884 if (unlikely(skb->len < 2 + 2 + 6)) {
2885 /* Too short, this can't be a valid frame. */
21a75d77
MB		 2886 dev_kfree_skb_any(skb);
2887 return NETDEV_TX_OK;
5100d5ac
MB		 2888 }
2889 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 2890 if (unlikely(!dev))
21a75d77
MB		 2891 return NETDEV_TX_BUSY;
2892
2893 /* Transmissions on seperate queues can run concurrently. */
2894 read_lock_irqsave(&wl->tx_lock, flags);
2895
2896 err = -ENODEV;
2897 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2898 if (b43_using_pio_transfers(dev))
2899 err = b43_pio_tx(dev, skb, ctl);
2900 else
2901 err = b43_dma_tx(dev, skb, ctl);
2902 }
2903
2904 read_unlock_irqrestore(&wl->tx_lock, flags);
2905
e4d6b795
MB		 2906 if (unlikely(err))
2907 return NETDEV_TX_BUSY;
2908 return NETDEV_TX_OK;
2909}
2910
e6f5b934
MB		 2911/* Locking: wl->irq_lock */
2912static void b43_qos_params_upload(struct b43_wldev *dev,
2913 const struct ieee80211_tx_queue_params *p,
2914 u16 shm_offset)
2915{
2916 u16 params[B43_NR_QOSPARAMS];
2917 int cw_min, cw_max, aifs, bslots, tmp;
2918 unsigned int i;
2919
2920 const u16 aCWmin = 0x0001;
2921 const u16 aCWmax = 0x03FF;
2922
2923 /* Calculate the default values for the parameters, if needed. */
2924 switch (shm_offset) {
2925 case B43_QOS_VOICE:
2926 aifs = (p->aifs == -1) ? 2 : p->aifs;
2927 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2928 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2929 break;
2930 case B43_QOS_VIDEO:
2931 aifs = (p->aifs == -1) ? 2 : p->aifs;
2932 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2933 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2934 break;
2935 case B43_QOS_BESTEFFORT:
2936 aifs = (p->aifs == -1) ? 3 : p->aifs;
2937 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2938 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2939 break;
2940 case B43_QOS_BACKGROUND:
2941 aifs = (p->aifs == -1) ? 7 : p->aifs;
2942 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2943 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2944 break;
2945 default:
2946 B43_WARN_ON(1);
2947 return;
2948 }
2949 if (cw_min <= 0)
2950 cw_min = aCWmin;
2951 if (cw_max <= 0)
2952 cw_max = aCWmin;
2953 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2954
2955 memset(&params, 0, sizeof(params));
2956
2957 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2958 params[B43_QOSPARAM_CWMIN] = cw_min;
2959 params[B43_QOSPARAM_CWMAX] = cw_max;
2960 params[B43_QOSPARAM_CWCUR] = cw_min;
2961 params[B43_QOSPARAM_AIFS] = aifs;
2962 params[B43_QOSPARAM_BSLOTS] = bslots;
2963 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2964
2965 for (i = 0; i < ARRAY_SIZE(params); i++) {
2966 if (i == B43_QOSPARAM_STATUS) {
2967 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2968 shm_offset + (i * 2));
2969 /* Mark the parameters as updated. */
2970 tmp |= 0x100;
2971 b43_shm_write16(dev, B43_SHM_SHARED,
2972 shm_offset + (i * 2),
2973 tmp);
2974 } else {
2975 b43_shm_write16(dev, B43_SHM_SHARED,
2976 shm_offset + (i * 2),
2977 params[i]);
2978 }
2979 }
2980}
2981
2982/* Update the QOS parameters in hardware. */
2983static void b43_qos_update(struct b43_wldev *dev)
2984{
2985 struct b43_wl *wl = dev->wl;
2986 struct b43_qos_params *params;
2987 unsigned long flags;
2988 unsigned int i;
2989
2990 /* Mapping of mac80211 queues to b43 SHM offsets. */
2991 static const u16 qos_shm_offsets[] = {
2992 [0] = B43_QOS_VOICE,
2993 [1] = B43_QOS_VIDEO,
2994 [2] = B43_QOS_BESTEFFORT,
2995 [3] = B43_QOS_BACKGROUND,
2996 };
2997 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
2998
2999 b43_mac_suspend(dev);
3000 spin_lock_irqsave(&wl->irq_lock, flags);
3001
3002 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3003 params = &(wl->qos_params[i]);
3004 if (params->need_hw_update) {
3005 b43_qos_params_upload(dev, &(params->p),
3006 qos_shm_offsets[i]);
3007 params->need_hw_update = 0;
3008 }
3009 }
3010
3011 spin_unlock_irqrestore(&wl->irq_lock, flags);
3012 b43_mac_enable(dev);
3013}
3014
3015static void b43_qos_clear(struct b43_wl *wl)
3016{
3017 struct b43_qos_params *params;
3018 unsigned int i;
3019
3020 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3021 params = &(wl->qos_params[i]);
3022
3023 memset(&(params->p), 0, sizeof(params->p));
3024 params->p.aifs = -1;
3025 params->need_hw_update = 1;
3026 }
3027}
3028
3029/* Initialize the core's QOS capabilities */
3030static void b43_qos_init(struct b43_wldev *dev)
3031{
3032 struct b43_wl *wl = dev->wl;
3033 unsigned int i;
3034
3035 /* Upload the current QOS parameters. */
3036 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
3037 wl->qos_params[i].need_hw_update = 1;
3038 b43_qos_update(dev);
3039
3040 /* Enable QOS support. */
3041 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3042 b43_write16(dev, B43_MMIO_IFSCTL,
3043 b43_read16(dev, B43_MMIO_IFSCTL)
3044 | B43_MMIO_IFSCTL_USE_EDCF);
3045}
3046
3047static void b43_qos_update_work(struct work_struct *work)
3048{
3049 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
3050 struct b43_wldev *dev;
3051
3052 mutex_lock(&wl->mutex);
3053 dev = wl->current_dev;
3054 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
3055 b43_qos_update(dev);
3056 mutex_unlock(&wl->mutex);
3057}
3058
40faacc4 3059static int b43_op_conf_tx(struct ieee80211_hw *hw,
e6f5b934 3060 int _queue,
40faacc4 3061 const struct ieee80211_tx_queue_params *params)
e4d6b795 3062{
e6f5b934
MB		 3063 struct b43_wl *wl = hw_to_b43_wl(hw);
3064 unsigned long flags;
3065 unsigned int queue = (unsigned int)_queue;
3066 struct b43_qos_params *p;
3067
3068 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3069 /* Queue not available or don't support setting
3070 * params on this queue. Return success to not
3071 * confuse mac80211. */
3072 return 0;
3073 }
3074
3075 spin_lock_irqsave(&wl->irq_lock, flags);
3076 p = &(wl->qos_params[queue]);
3077 memcpy(&(p->p), params, sizeof(p->p));
3078 p->need_hw_update = 1;
3079 spin_unlock_irqrestore(&wl->irq_lock, flags);
3080
3081 queue_work(hw->workqueue, &wl->qos_update_work);
3082
e4d6b795
MB		 3083 return 0;
3084}
3085
40faacc4
MB		 3086static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3087 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3088{
3089 struct b43_wl *wl = hw_to_b43_wl(hw);
3090 struct b43_wldev *dev = wl->current_dev;
3091 unsigned long flags;
3092 int err = -ENODEV;
3093
3094 if (!dev)
3095 goto out;
3096 spin_lock_irqsave(&wl->irq_lock, flags);
3097 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3098 if (b43_using_pio_transfers(dev))
3099 b43_pio_get_tx_stats(dev, stats);
3100 else
3101 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3102 err = 0;
3103 }
3104 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3105out:
e4d6b795
MB		 3106 return err;
3107}
3108
40faacc4
MB		 3109static int b43_op_get_stats(struct ieee80211_hw *hw,
3110 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3111{
3112 struct b43_wl *wl = hw_to_b43_wl(hw);
3113 unsigned long flags;
3114
3115 spin_lock_irqsave(&wl->irq_lock, flags);
3116 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3117 spin_unlock_irqrestore(&wl->irq_lock, flags);
3118
3119 return 0;
3120}
3121
e4d6b795
MB		 3122static void b43_put_phy_into_reset(struct b43_wldev *dev)
3123{
3124 struct ssb_device *sdev = dev->dev;
3125 u32 tmslow;
3126
3127 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3128 tmslow &= ~B43_TMSLOW_GMODE;
3129 tmslow |= B43_TMSLOW_PHYRESET;
3130 tmslow |= SSB_TMSLOW_FGC;
3131 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3132 msleep(1);
3133
3134 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3135 tmslow &= ~SSB_TMSLOW_FGC;
3136 tmslow |= B43_TMSLOW_PHYRESET;
3137 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3138 msleep(1);
3139}
3140
bb1eeff1
MB		 3141static const char * band_to_string(enum ieee80211_band band)
3142{
3143 switch (band) {
3144 case IEEE80211_BAND_5GHZ:
3145 return "5";
3146 case IEEE80211_BAND_2GHZ:
3147 return "2.4";
3148 default:
3149 break;
3150 }
3151 B43_WARN_ON(1);
3152 return "";
3153}
3154
e4d6b795 3155/* Expects wl->mutex locked */
bb1eeff1 3156static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3157{
bb1eeff1 3158 struct b43_wldev *up_dev = NULL;
e4d6b795 3159 struct b43_wldev *down_dev;
bb1eeff1 3160 struct b43_wldev *d;
e4d6b795 3161 int err;
bb1eeff1 3162 bool gmode;
e4d6b795
MB		 3163 int prev_status;
3164
bb1eeff1
MB		 3165 /* Find a device and PHY which supports the band. */
3166 list_for_each_entry(d, &wl->devlist, list) {
3167 switch (chan->band) {
3168 case IEEE80211_BAND_5GHZ:
3169 if (d->phy.supports_5ghz) {
3170 up_dev = d;
3171 gmode = 0;
3172 }
3173 break;
3174 case IEEE80211_BAND_2GHZ:
3175 if (d->phy.supports_2ghz) {
3176 up_dev = d;
3177 gmode = 1;
3178 }
3179 break;
3180 default:
3181 B43_WARN_ON(1);
3182 return -EINVAL;
3183 }
3184 if (up_dev)
3185 break;
3186 }
3187 if (!up_dev) {
3188 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3189 band_to_string(chan->band));
3190 return -ENODEV;
e4d6b795
MB		 3191 }
3192 if ((up_dev == wl->current_dev) &&
3193 (!!wl->current_dev->phy.gmode == !!gmode)) {
3194 /* This device is already running. */
3195 return 0;
3196 }
bb1eeff1
MB		 3197 b43dbg(wl, "Switching to %s-GHz band\n",
3198 band_to_string(chan->band));
e4d6b795
MB		 3199 down_dev = wl->current_dev;
3200
3201 prev_status = b43_status(down_dev);
3202 /* Shutdown the currently running core. */
3203 if (prev_status >= B43_STAT_STARTED)
3204 b43_wireless_core_stop(down_dev);
3205 if (prev_status >= B43_STAT_INITIALIZED)
3206 b43_wireless_core_exit(down_dev);
3207
3208 if (down_dev != up_dev) {
3209 /* We switch to a different core, so we put PHY into
3210 * RESET on the old core. */
3211 b43_put_phy_into_reset(down_dev);
3212 }
3213
3214 /* Now start the new core. */
3215 up_dev->phy.gmode = gmode;
3216 if (prev_status >= B43_STAT_INITIALIZED) {
3217 err = b43_wireless_core_init(up_dev);
3218 if (err) {
3219 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3220 "selected %s-GHz band\n",
3221 band_to_string(chan->band));
e4d6b795
MB		 3222 goto init_failure;
3223 }
3224 }
3225 if (prev_status >= B43_STAT_STARTED) {
3226 err = b43_wireless_core_start(up_dev);
3227 if (err) {
3228 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3229 "selected %s-GHz band\n",
3230 band_to_string(chan->band));
e4d6b795
MB		 3231 b43_wireless_core_exit(up_dev);
3232 goto init_failure;
3233 }
3234 }
3235 B43_WARN_ON(b43_status(up_dev) != prev_status);
3236
3237 wl->current_dev = up_dev;
3238
3239 return 0;
bb1eeff1 3240init_failure:
e4d6b795
MB		 3241 /* Whoops, failed to init the new core. No core is operating now. */
3242 wl->current_dev = NULL;
3243 return err;
3244}
3245
40faacc4 3246static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
e4d6b795
MB		 3247{
3248 struct b43_wl *wl = hw_to_b43_wl(hw);
3249 struct b43_wldev *dev;
3250 struct b43_phy *phy;
3251 unsigned long flags;
9db1f6d7 3252 int antenna;
e4d6b795
MB		 3253 int err = 0;
3254 u32 savedirqs;
3255
e4d6b795
MB		 3256 mutex_lock(&wl->mutex);
3257
bb1eeff1
MB		 3258 /* Switch the band (if necessary). This might change the active core. */
3259 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3260 if (err)
3261 goto out_unlock_mutex;
3262 dev = wl->current_dev;
3263 phy = &dev->phy;
3264
3265 /* Disable IRQs while reconfiguring the device.
3266 * This makes it possible to drop the spinlock throughout
3267 * the reconfiguration process. */
3268 spin_lock_irqsave(&wl->irq_lock, flags);
3269 if (b43_status(dev) < B43_STAT_STARTED) {
3270 spin_unlock_irqrestore(&wl->irq_lock, flags);
3271 goto out_unlock_mutex;
3272 }
3273 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3274 spin_unlock_irqrestore(&wl->irq_lock, flags);
3275 b43_synchronize_irq(dev);
3276
3277 /* Switch to the requested channel.
3278 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 3279 if (conf->channel->hw_value != phy->channel)
3280 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
e4d6b795
MB		 3281
3282 /* Enable/Disable ShortSlot timing. */
3283 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3284 dev->short_slot) {
3285 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3286 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3287 b43_short_slot_timing_enable(dev);
3288 else
3289 b43_short_slot_timing_disable(dev);
3290 }
3291
d42ce84a
JB		 3292 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3293
e4d6b795
MB		 3294 /* Adjust the desired TX power level. */
3295 if (conf->power_level != 0) {
3296 if (conf->power_level != phy->power_level) {
3297 phy->power_level = conf->power_level;
3298 b43_phy_xmitpower(dev);
3299 }
3300 }
3301
3302 /* Antennas for RX and management frame TX. */
9db1f6d7
MB		 3303 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3304 b43_mgmtframe_txantenna(dev, antenna);
3305 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3306 b43_set_rx_antenna(dev, antenna);
e4d6b795
MB		 3307
3308 /* Update templates for AP mode. */
3309 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3310 b43_set_beacon_int(dev, conf->beacon_int);
3311
fda9abcf
MB		 3312 if (!!conf->radio_enabled != phy->radio_on) {
3313 if (conf->radio_enabled) {
3314 b43_radio_turn_on(dev);
3315 b43info(dev->wl, "Radio turned on by software\n");
3316 if (!dev->radio_hw_enable) {
3317 b43info(dev->wl, "The hardware RF-kill button "
3318 "still turns the radio physically off. "
3319 "Press the button to turn it on.\n");
3320 }
3321 } else {
8e9f7529 3322 b43_radio_turn_off(dev, 0);
fda9abcf
MB		 3323 b43info(dev->wl, "Radio turned off by software\n");
3324 }
3325 }
3326
e4d6b795
MB		 3327 spin_lock_irqsave(&wl->irq_lock, flags);
3328 b43_interrupt_enable(dev, savedirqs);
3329 mmiowb();
3330 spin_unlock_irqrestore(&wl->irq_lock, flags);
3331 out_unlock_mutex:
3332 mutex_unlock(&wl->mutex);
3333
3334 return err;
3335}
3336
40faacc4 3337static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 3338 const u8 *local_addr, const u8 *addr,
3339 struct ieee80211_key_conf *key)
e4d6b795
MB		 3340{
3341 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3342 struct b43_wldev *dev;
e4d6b795
MB		 3343 unsigned long flags;
3344 u8 algorithm;
3345 u8 index;
c6dfc9a8 3346 int err;
0795af57 3347 DECLARE_MAC_BUF(mac);
e4d6b795
MB		 3348
3349 if (modparam_nohwcrypt)
3350 return -ENOSPC; /* User disabled HW-crypto */
3351
c6dfc9a8
MB		 3352 mutex_lock(&wl->mutex);
3353 spin_lock_irqsave(&wl->irq_lock, flags);
3354
3355 dev = wl->current_dev;
3356 err = -ENODEV;
3357 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3358 goto out_unlock;
3359
3360 err = -EINVAL;
e4d6b795 3361 switch (key->alg) {
e4d6b795
MB		 3362 case ALG_WEP:
3363 if (key->keylen == 5)
3364 algorithm = B43_SEC_ALGO_WEP40;
3365 else
3366 algorithm = B43_SEC_ALGO_WEP104;
3367 break;
3368 case ALG_TKIP:
3369 algorithm = B43_SEC_ALGO_TKIP;
3370 break;
3371 case ALG_CCMP:
3372 algorithm = B43_SEC_ALGO_AES;
3373 break;
3374 default:
3375 B43_WARN_ON(1);
c6dfc9a8 3376 goto out_unlock;
e4d6b795 3377 }
e4d6b795
MB		 3378 index = (u8) (key->keyidx);
3379 if (index > 3)
e4d6b795 3380 goto out_unlock;
e4d6b795
MB		 3381
3382 switch (cmd) {
3383 case SET_KEY:
3384 if (algorithm == B43_SEC_ALGO_TKIP) {
3385 /* FIXME: No TKIP hardware encryption for now. */
3386 err = -EOPNOTSUPP;
3387 goto out_unlock;
3388 }
3389
3390 if (is_broadcast_ether_addr(addr)) {
3391 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3392 err = b43_key_write(dev, index, algorithm,
3393 key->key, key->keylen, NULL, key);
3394 } else {
3395 /*
3396 * either pairwise key or address is 00:00:00:00:00:00
3397 * for transmit-only keys
3398 */
3399 err = b43_key_write(dev, -1, algorithm,
3400 key->key, key->keylen, addr, key);
3401 }
3402 if (err)
3403 goto out_unlock;
3404
3405 if (algorithm == B43_SEC_ALGO_WEP40 ||
3406 algorithm == B43_SEC_ALGO_WEP104) {
3407 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3408 } else {
3409 b43_hf_write(dev,
3410 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3411 }
3412 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3413 break;
3414 case DISABLE_KEY: {
3415 err = b43_key_clear(dev, key->hw_key_idx);
3416 if (err)
3417 goto out_unlock;
3418 break;
3419 }
3420 default:
3421 B43_WARN_ON(1);
3422 }
3423out_unlock:
3424 spin_unlock_irqrestore(&wl->irq_lock, flags);
3425 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3426 if (!err) {
3427 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
0795af57 3428 "mac: %s\n",
e4d6b795 3429 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
0795af57 3430 print_mac(mac, addr));
e4d6b795
MB		 3431 }
3432 return err;
3433}
3434
40faacc4
MB		 3435static void b43_op_configure_filter(struct ieee80211_hw *hw,
3436 unsigned int changed, unsigned int *fflags,
3437 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3438{
3439 struct b43_wl *wl = hw_to_b43_wl(hw);
3440 struct b43_wldev *dev = wl->current_dev;
3441 unsigned long flags;
3442
4150c572
JB		 3443 if (!dev) {
3444 *fflags = 0;
e4d6b795 3445 return;
e4d6b795 3446 }
4150c572
JB		 3447
3448 spin_lock_irqsave(&wl->irq_lock, flags);
3449 *fflags &= FIF_PROMISC_IN_BSS |
3450 FIF_ALLMULTI |
3451 FIF_FCSFAIL |
3452 FIF_PLCPFAIL |
3453 FIF_CONTROL |
3454 FIF_OTHER_BSS |
3455 FIF_BCN_PRBRESP_PROMISC;
3456
3457 changed &= FIF_PROMISC_IN_BSS |
3458 FIF_ALLMULTI |
3459 FIF_FCSFAIL |
3460 FIF_PLCPFAIL |
3461 FIF_CONTROL |
3462 FIF_OTHER_BSS |
3463 FIF_BCN_PRBRESP_PROMISC;
3464
3465 wl->filter_flags = *fflags;
3466
3467 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3468 b43_adjust_opmode(dev);
e4d6b795
MB		 3469 spin_unlock_irqrestore(&wl->irq_lock, flags);
3470}
3471
40faacc4 3472static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3473 struct ieee80211_vif *vif,
40faacc4 3474 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3475{
3476 struct b43_wl *wl = hw_to_b43_wl(hw);
3477 struct b43_wldev *dev = wl->current_dev;
3478 unsigned long flags;
3479
3480 if (!dev)
3481 return -ENODEV;
3482 mutex_lock(&wl->mutex);
3483 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3484 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3485 if (conf->bssid)
3486 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3487 else
3488 memset(wl->bssid, 0, ETH_ALEN);
3489 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3490 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3491 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3492 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
5042c507
MB		 3493 if (conf->beacon) {
3494 b43_update_templates(wl, conf->beacon,
3495 conf->beacon_control);
3496 }
e4d6b795 3497 }
4150c572 3498 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3499 }
3500 spin_unlock_irqrestore(&wl->irq_lock, flags);
3501 mutex_unlock(&wl->mutex);
3502
3503 return 0;
3504}
3505
3506/* Locking: wl->mutex */
3507static void b43_wireless_core_stop(struct b43_wldev *dev)
3508{
3509 struct b43_wl *wl = dev->wl;
3510 unsigned long flags;
3511
3512 if (b43_status(dev) < B43_STAT_STARTED)
3513 return;
a19d12d7
SB		 3514
3515 /* Disable and sync interrupts. We must do this before than
3516 * setting the status to INITIALIZED, as the interrupt handler
3517 * won't care about IRQs then. */
3518 spin_lock_irqsave(&wl->irq_lock, flags);
3519 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3520 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3521 spin_unlock_irqrestore(&wl->irq_lock, flags);
3522 b43_synchronize_irq(dev);
3523
21a75d77 3524 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3525 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3526 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3527
5100d5ac 3528 b43_pio_stop(dev);
e4d6b795
MB		 3529 mutex_unlock(&wl->mutex);
3530 /* Must unlock as it would otherwise deadlock. No races here.
3531 * Cancel the possibly running self-rearming periodic work. */
3532 cancel_delayed_work_sync(&dev->periodic_work);
3533 mutex_lock(&wl->mutex);
3534
e4d6b795
MB		 3535 b43_mac_suspend(dev);
3536 free_irq(dev->dev->irq, dev);
3537 b43dbg(wl, "Wireless interface stopped\n");
3538}
3539
3540/* Locking: wl->mutex */
3541static int b43_wireless_core_start(struct b43_wldev *dev)
3542{
3543 int err;
3544
3545 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3546
3547 drain_txstatus_queue(dev);
3548 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3549 IRQF_SHARED, KBUILD_MODNAME, dev);
3550 if (err) {
3551 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3552 goto out;
3553 }
3554
3555 /* We are ready to run. */
3556 b43_set_status(dev, B43_STAT_STARTED);
3557
3558 /* Start data flow (TX/RX). */
3559 b43_mac_enable(dev);
3560 b43_interrupt_enable(dev, dev->irq_savedstate);
3561 ieee80211_start_queues(dev->wl->hw);
3562
3563 /* Start maintainance work */
3564 b43_periodic_tasks_setup(dev);
3565
3566 b43dbg(dev->wl, "Wireless interface started\n");
3567 out:
3568 return err;
3569}
3570
3571/* Get PHY and RADIO versioning numbers */
3572static int b43_phy_versioning(struct b43_wldev *dev)
3573{
3574 struct b43_phy *phy = &dev->phy;
3575 u32 tmp;
3576 u8 analog_type;
3577 u8 phy_type;
3578 u8 phy_rev;
3579 u16 radio_manuf;
3580 u16 radio_ver;
3581 u16 radio_rev;
3582 int unsupported = 0;
3583
3584 /* Get PHY versioning */
3585 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3586 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3587 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3588 phy_rev = (tmp & B43_PHYVER_VERSION);
3589 switch (phy_type) {
3590 case B43_PHYTYPE_A:
3591 if (phy_rev >= 4)
3592 unsupported = 1;
3593 break;
3594 case B43_PHYTYPE_B:
3595 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3596 && phy_rev != 7)
3597 unsupported = 1;
3598 break;
3599 case B43_PHYTYPE_G:
013978b6 3600 if (phy_rev > 9)
e4d6b795
MB		 3601 unsupported = 1;
3602 break;
d5c71e46
MB		 3603#ifdef CONFIG_B43_NPHY
3604 case B43_PHYTYPE_N:
3605 if (phy_rev > 1)
3606 unsupported = 1;
3607 break;
3608#endif
e4d6b795
MB		 3609 default:
3610 unsupported = 1;
3611 };
3612 if (unsupported) {
3613 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3614 "(Analog %u, Type %u, Revision %u)\n",
3615 analog_type, phy_type, phy_rev);
3616 return -EOPNOTSUPP;
3617 }
3618 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3619 analog_type, phy_type, phy_rev);
3620
3621 /* Get RADIO versioning */
3622 if (dev->dev->bus->chip_id == 0x4317) {
3623 if (dev->dev->bus->chip_rev == 0)
3624 tmp = 0x3205017F;
3625 else if (dev->dev->bus->chip_rev == 1)
3626 tmp = 0x4205017F;
3627 else
3628 tmp = 0x5205017F;
3629 } else {
3630 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3631 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3632 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3633 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3634 }
3635 radio_manuf = (tmp & 0x00000FFF);
3636 radio_ver = (tmp & 0x0FFFF000) >> 12;
3637 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3638 if (radio_manuf != 0x17F /* Broadcom */)
3639 unsupported = 1;
e4d6b795
MB		 3640 switch (phy_type) {
3641 case B43_PHYTYPE_A:
3642 if (radio_ver != 0x2060)
3643 unsupported = 1;
3644 if (radio_rev != 1)
3645 unsupported = 1;
3646 if (radio_manuf != 0x17F)
3647 unsupported = 1;
3648 break;
3649 case B43_PHYTYPE_B:
3650 if ((radio_ver & 0xFFF0) != 0x2050)
3651 unsupported = 1;
3652 break;
3653 case B43_PHYTYPE_G:
3654 if (radio_ver != 0x2050)
3655 unsupported = 1;
3656 break;
96c755a3 3657 case B43_PHYTYPE_N:
243dcfcc 3658 if (radio_ver != 0x2055)
96c755a3
MB		 3659 unsupported = 1;
3660 break;
e4d6b795
MB		 3661 default:
3662 B43_WARN_ON(1);
3663 }
3664 if (unsupported) {
3665 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3666 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3667 radio_manuf, radio_ver, radio_rev);
3668 return -EOPNOTSUPP;
3669 }
3670 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3671 radio_manuf, radio_ver, radio_rev);
3672
3673 phy->radio_manuf = radio_manuf;
3674 phy->radio_ver = radio_ver;
3675 phy->radio_rev = radio_rev;
3676
3677 phy->analog = analog_type;
3678 phy->type = phy_type;
3679 phy->rev = phy_rev;
3680
3681 return 0;
3682}
3683
3684static void setup_struct_phy_for_init(struct b43_wldev *dev,
3685 struct b43_phy *phy)
3686{
3687 struct b43_txpower_lo_control *lo;
3688 int i;
3689
3690 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3691 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3692
e4d6b795
MB		 3693 phy->aci_enable = 0;
3694 phy->aci_wlan_automatic = 0;
3695 phy->aci_hw_rssi = 0;
3696
fda9abcf
MB		 3697 phy->radio_off_context.valid = 0;
3698
e4d6b795
MB		 3699 lo = phy->lo_control;
3700 if (lo) {
3701 memset(lo, 0, sizeof(*(phy->lo_control)));
3702 lo->rebuild = 1;
3703 lo->tx_bias = 0xFF;
3704 }
3705 phy->max_lb_gain = 0;
3706 phy->trsw_rx_gain = 0;
3707 phy->txpwr_offset = 0;
3708
3709 /* NRSSI */
3710 phy->nrssislope = 0;
3711 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3712 phy->nrssi[i] = -1000;
3713 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3714 phy->nrssi_lt[i] = i;
3715
3716 phy->lofcal = 0xFFFF;
3717 phy->initval = 0xFFFF;
3718
e4d6b795
MB		 3719 phy->interfmode = B43_INTERFMODE_NONE;
3720 phy->channel = 0xFF;
3721
3722 phy->hardware_power_control = !!modparam_hwpctl;
8ed7fc48
MB		 3723
3724 /* PHY TX errors counter. */
3725 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3726
3727 /* OFDM-table address caching. */
3728 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
e4d6b795
MB		 3729}
3730
3731static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3732{
aa6c7ae2
MB		 3733 dev->dfq_valid = 0;
3734
6a724d68
MB		 3735 /* Assume the radio is enabled. If it's not enabled, the state will
3736 * immediately get fixed on the first periodic work run. */
3737 dev->radio_hw_enable = 1;
e4d6b795
MB		 3738
3739 /* Stats */
3740 memset(&dev->stats, 0, sizeof(dev->stats));
3741
3742 setup_struct_phy_for_init(dev, &dev->phy);
3743
3744 /* IRQ related flags */
3745 dev->irq_reason = 0;
3746 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3747 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3748
3749 dev->mac_suspended = 1;
3750
3751 /* Noise calculation context */
3752 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3753}
3754
3755static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3756{
3757 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 3758 u64 hf;
e4d6b795 3759
1855ba78
MB		 3760 if (!modparam_btcoex)
3761 return;
95de2841 3762 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3763 return;
3764 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3765 return;
3766
3767 hf = b43_hf_read(dev);
95de2841 3768 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3769 hf |= B43_HF_BTCOEXALT;
3770 else
3771 hf |= B43_HF_BTCOEX;
3772 b43_hf_write(dev, hf);
e4d6b795
MB		 3773}
3774
3775static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 3776{
3777 if (!modparam_btcoex)
3778 return;
3779 //TODO
e4d6b795
MB		 3780}
3781
3782static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3783{
3784#ifdef CONFIG_SSB_DRIVER_PCICORE
3785 struct ssb_bus *bus = dev->dev->bus;
3786 u32 tmp;
3787
3788 if (bus->pcicore.dev &&
3789 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3790 bus->pcicore.dev->id.revision <= 5) {
3791 /* IMCFGLO timeouts workaround. */
3792 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3793 tmp &= ~SSB_IMCFGLO_REQTO;
3794 tmp &= ~SSB_IMCFGLO_SERTO;
3795 switch (bus->bustype) {
3796 case SSB_BUSTYPE_PCI:
3797 case SSB_BUSTYPE_PCMCIA:
3798 tmp |= 0x32;
3799 break;
3800 case SSB_BUSTYPE_SSB:
3801 tmp |= 0x53;
3802 break;
3803 }
3804 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3805 }
3806#endif /* CONFIG_SSB_DRIVER_PCICORE */
3807}
3808
74cfdba7
MB		 3809/* Write the short and long frame retry limit values. */
3810static void b43_set_retry_limits(struct b43_wldev *dev,
3811 unsigned int short_retry,
3812 unsigned int long_retry)
3813{
3814 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3815 * the chip-internal counter. */
3816 short_retry = min(short_retry, (unsigned int)0xF);
3817 long_retry = min(long_retry, (unsigned int)0xF);
3818
3819 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3820 short_retry);
3821 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3822 long_retry);
3823}
3824
d59f720d
MB		 3825static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3826{
3827 u16 pu_delay;
3828
3829 /* The time value is in microseconds. */
3830 if (dev->phy.type == B43_PHYTYPE_A)
3831 pu_delay = 3700;
3832 else
3833 pu_delay = 1050;
8cf6a31e 3834 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
d59f720d
MB		 3835 pu_delay = 500;
3836 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3837 pu_delay = max(pu_delay, (u16)2400);
3838
3839 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3840}
3841
3842/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3843static void b43_set_pretbtt(struct b43_wldev *dev)
3844{
3845 u16 pretbtt;
3846
3847 /* The time value is in microseconds. */
8cf6a31e 3848 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
d59f720d
MB		 3849 pretbtt = 2;
3850 } else {
3851 if (dev->phy.type == B43_PHYTYPE_A)
3852 pretbtt = 120;
3853 else
3854 pretbtt = 250;
3855 }
3856 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3857 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3858}
3859
e4d6b795
MB		 3860/* Shutdown a wireless core */
3861/* Locking: wl->mutex */
3862static void b43_wireless_core_exit(struct b43_wldev *dev)
3863{
3864 struct b43_phy *phy = &dev->phy;
1f7d87b0 3865 u32 macctl;
e4d6b795
MB		 3866
3867 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3868 if (b43_status(dev) != B43_STAT_INITIALIZED)
3869 return;
3870 b43_set_status(dev, B43_STAT_UNINIT);
3871
1f7d87b0
MB		 3872 /* Stop the microcode PSM. */
3873 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3874 macctl &= ~B43_MACCTL_PSM_RUN;
3875 macctl |= B43_MACCTL_PSM_JMP0;
3876 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3877
3506e0c4
RW		 3878 if (!dev->suspend_in_progress) {
3879 b43_leds_exit(dev);
b844eba2 3880 b43_rng_exit(dev->wl);
3506e0c4 3881 }
e4d6b795 3882 b43_dma_free(dev);
5100d5ac 3883 b43_pio_free(dev);
e4d6b795 3884 b43_chip_exit(dev);
8e9f7529 3885 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 3886 b43_switch_analog(dev, 0);
3887 if (phy->dyn_tssi_tbl)
3888 kfree(phy->tssi2dbm);
3889 kfree(phy->lo_control);
3890 phy->lo_control = NULL;
e66fee6a
MB		 3891 if (dev->wl->current_beacon) {
3892 dev_kfree_skb_any(dev->wl->current_beacon);
3893 dev->wl->current_beacon = NULL;
3894 }
3895
e4d6b795
MB		 3896 ssb_device_disable(dev->dev, 0);
3897 ssb_bus_may_powerdown(dev->dev->bus);
3898}
3899
3900/* Initialize a wireless core */
3901static int b43_wireless_core_init(struct b43_wldev *dev)
3902{
3903 struct b43_wl *wl = dev->wl;
3904 struct ssb_bus *bus = dev->dev->bus;
3905 struct ssb_sprom *sprom = &bus->sprom;
3906 struct b43_phy *phy = &dev->phy;
3907 int err;
a259d6a4
MB		 3908 u64 hf;
3909 u32 tmp;
e4d6b795
MB		 3910
3911 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3912
3913 err = ssb_bus_powerup(bus, 0);
3914 if (err)
3915 goto out;
3916 if (!ssb_device_is_enabled(dev->dev)) {
3917 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3918 b43_wireless_core_reset(dev, tmp);
3919 }
3920
3921 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3922 phy->lo_control =
3923 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3924 if (!phy->lo_control) {
3925 err = -ENOMEM;
3926 goto err_busdown;
3927 }
3928 }
3929 setup_struct_wldev_for_init(dev);
3930
3931 err = b43_phy_init_tssi2dbm_table(dev);
3932 if (err)
3933 goto err_kfree_lo_control;
3934
3935 /* Enable IRQ routing to this device. */
3936 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3937
3938 b43_imcfglo_timeouts_workaround(dev);
3939 b43_bluetooth_coext_disable(dev);
3940 b43_phy_early_init(dev);
3941 err = b43_chip_init(dev);
3942 if (err)
3943 goto err_kfree_tssitbl;
3944 b43_shm_write16(dev, B43_SHM_SHARED,
3945 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3946 hf = b43_hf_read(dev);
3947 if (phy->type == B43_PHYTYPE_G) {
3948 hf |= B43_HF_SYMW;
3949 if (phy->rev == 1)
3950 hf |= B43_HF_GDCW;
95de2841 3951 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 3952 hf |= B43_HF_OFDMPABOOST;
3953 } else if (phy->type == B43_PHYTYPE_B) {
3954 hf |= B43_HF_SYMW;
3955 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3956 hf &= ~B43_HF_GDCW;
3957 }
3958 b43_hf_write(dev, hf);
3959
74cfdba7
MB		 3960 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3961 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 3962 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3963 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3964
3965 /* Disable sending probe responses from firmware.
3966 * Setting the MaxTime to one usec will always trigger
3967 * a timeout, so we never send any probe resp.
3968 * A timeout of zero is infinite. */
3969 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3970
3971 b43_rate_memory_init(dev);
5042c507 3972 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 3973
3974 /* Minimum Contention Window */
3975 if (phy->type == B43_PHYTYPE_B) {
3976 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3977 } else {
3978 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3979 }
3980 /* Maximum Contention Window */
3981 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3982
5100d5ac
MB		 3983 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3984 dev->__using_pio_transfers = 1;
3985 err = b43_pio_init(dev);
3986 } else {
3987 dev->__using_pio_transfers = 0;
3988 err = b43_dma_init(dev);
3989 }
e4d6b795
MB		 3990 if (err)
3991 goto err_chip_exit;
03b29773 3992 b43_qos_init(dev);
d59f720d 3993 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 3994 b43_bluetooth_coext_enable(dev);
3995
3996 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3997 b43_upload_card_macaddress(dev);
e4d6b795 3998 b43_security_init(dev);
3506e0c4
RW		 3999 if (!dev->suspend_in_progress)
4000 b43_rng_init(wl);
e4d6b795
MB		 4001
4002 b43_set_status(dev, B43_STAT_INITIALIZED);
4003
3506e0c4
RW		 4004 if (!dev->suspend_in_progress)
4005 b43_leds_init(dev);
1a8d1227 4006out:
e4d6b795
MB		 4007 return err;
4008
4009 err_chip_exit:
4010 b43_chip_exit(dev);
4011 err_kfree_tssitbl:
4012 if (phy->dyn_tssi_tbl)
4013 kfree(phy->tssi2dbm);
4014 err_kfree_lo_control:
4015 kfree(phy->lo_control);
4016 phy->lo_control = NULL;
4017 err_busdown:
4018 ssb_bus_may_powerdown(bus);
4019 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4020 return err;
4021}
4022
40faacc4
MB		 4023static int b43_op_add_interface(struct ieee80211_hw *hw,
4024 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4025{
4026 struct b43_wl *wl = hw_to_b43_wl(hw);
4027 struct b43_wldev *dev;
4028 unsigned long flags;
4029 int err = -EOPNOTSUPP;
4150c572
JB		 4030
4031 /* TODO: allow WDS/AP devices to coexist */
4032
4033 if (conf->type != IEEE80211_IF_TYPE_AP &&
4034 conf->type != IEEE80211_IF_TYPE_STA &&
4035 conf->type != IEEE80211_IF_TYPE_WDS &&
4036 conf->type != IEEE80211_IF_TYPE_IBSS)
4037 return -EOPNOTSUPP;
e4d6b795
MB		 4038
4039 mutex_lock(&wl->mutex);
4150c572 4040 if (wl->operating)
e4d6b795
MB		 4041 goto out_mutex_unlock;
4042
4043 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4044
4045 dev = wl->current_dev;
4150c572 4046 wl->operating = 1;
32bfd35d 4047 wl->vif = conf->vif;
4150c572
JB		 4048 wl->if_type = conf->type;
4049 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4050
4051 spin_lock_irqsave(&wl->irq_lock, flags);
4052 b43_adjust_opmode(dev);
d59f720d
MB		 4053 b43_set_pretbtt(dev);
4054 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4055 b43_upload_card_macaddress(dev);
4056 spin_unlock_irqrestore(&wl->irq_lock, flags);
4057
4058 err = 0;
4059 out_mutex_unlock:
4060 mutex_unlock(&wl->mutex);
4061
4062 return err;
4063}
4064
40faacc4
MB		 4065static void b43_op_remove_interface(struct ieee80211_hw *hw,
4066 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4067{
4068 struct b43_wl *wl = hw_to_b43_wl(hw);
4069 struct b43_wldev *dev = wl->current_dev;
4070 unsigned long flags;
4071
4072 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4073
4074 mutex_lock(&wl->mutex);
4075
4076 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4077 B43_WARN_ON(wl->vif != conf->vif);
4078 wl->vif = NULL;
4150c572
JB		 4079
4080 wl->operating = 0;
4081
4082 spin_lock_irqsave(&wl->irq_lock, flags);
4083 b43_adjust_opmode(dev);
4084 memset(wl->mac_addr, 0, ETH_ALEN);
4085 b43_upload_card_macaddress(dev);
4086 spin_unlock_irqrestore(&wl->irq_lock, flags);
4087
4088 mutex_unlock(&wl->mutex);
4089}
4090
40faacc4 4091static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4092{
4093 struct b43_wl *wl = hw_to_b43_wl(hw);
4094 struct b43_wldev *dev = wl->current_dev;
4095 int did_init = 0;
923403b8 4096 int err = 0;
1946a2c3 4097 bool do_rfkill_exit = 0;
4150c572 4098
7be1bb6b
MB		 4099 /* Kill all old instance specific information to make sure
4100 * the card won't use it in the short timeframe between start
4101 * and mac80211 reconfiguring it. */
4102 memset(wl->bssid, 0, ETH_ALEN);
4103 memset(wl->mac_addr, 0, ETH_ALEN);
4104 wl->filter_flags = 0;
4105 wl->radiotap_enabled = 0;
e6f5b934 4106 b43_qos_clear(wl);
6b4bec01
MB		 4107 wl->beacon0_uploaded = 0;
4108 wl->beacon1_uploaded = 0;
4109 wl->beacon_templates_virgin = 1;
7be1bb6b 4110
1a8d1227
LF		 4111 /* First register RFkill.
4112 * LEDs that are registered later depend on it. */
4113 b43_rfkill_init(dev);
4114
4150c572
JB		 4115 mutex_lock(&wl->mutex);
4116
e4d6b795
MB		 4117 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4118 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4119 if (err) {
4120 do_rfkill_exit = 1;
e4d6b795 4121 goto out_mutex_unlock;
1946a2c3 4122 }
e4d6b795
MB		 4123 did_init = 1;
4124 }
4150c572 4125
e4d6b795
MB		 4126 if (b43_status(dev) < B43_STAT_STARTED) {
4127 err = b43_wireless_core_start(dev);
4128 if (err) {
4129 if (did_init)
4130 b43_wireless_core_exit(dev);
1946a2c3 4131 do_rfkill_exit = 1;
e4d6b795
MB		 4132 goto out_mutex_unlock;
4133 }
4134 }
4135
4150c572 4136 out_mutex_unlock:
e4d6b795
MB		 4137 mutex_unlock(&wl->mutex);
4138
1946a2c3
MB		 4139 if (do_rfkill_exit)
4140 b43_rfkill_exit(dev);
4141
e4d6b795
MB		 4142 return err;
4143}
4144
40faacc4 4145static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4146{
4147 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4148 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4149
1a8d1227 4150 b43_rfkill_exit(dev);
e6f5b934 4151 cancel_work_sync(&(wl->qos_update_work));
a82d9922 4152 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4153
e4d6b795 4154 mutex_lock(&wl->mutex);
4150c572
JB		 4155 if (b43_status(dev) >= B43_STAT_STARTED)
4156 b43_wireless_core_stop(dev);
4157 b43_wireless_core_exit(dev);
e4d6b795
MB		 4158 mutex_unlock(&wl->mutex);
4159}
4160
74cfdba7
MB		 4161static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4162 u32 short_retry_limit, u32 long_retry_limit)
4163{
4164 struct b43_wl *wl = hw_to_b43_wl(hw);
4165 struct b43_wldev *dev;
4166 int err = 0;
4167
4168 mutex_lock(&wl->mutex);
4169 dev = wl->current_dev;
4170 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4171 err = -ENODEV;
4172 goto out_unlock;
4173 }
4174 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4175out_unlock:
4176 mutex_unlock(&wl->mutex);
4177
4178 return err;
4179}
4180
e66fee6a
MB		 4181static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4182{
4183 struct b43_wl *wl = hw_to_b43_wl(hw);
4184 struct sk_buff *beacon;
d4df6f1a 4185 unsigned long flags;
5042c507 4186 struct ieee80211_tx_control txctl;
e66fee6a
MB		 4187
4188 /* We could modify the existing beacon and set the aid bit in
4189 * the TIM field, but that would probably require resizing and
4190 * moving of data within the beacon template.
4191 * Simply request a new beacon and let mac80211 do the hard work. */
5042c507 4192 beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
e66fee6a
MB		 4193 if (unlikely(!beacon))
4194 return -ENOMEM;
d4df6f1a 4195 spin_lock_irqsave(&wl->irq_lock, flags);
5042c507 4196 b43_update_templates(wl, beacon, &txctl);
d4df6f1a 4197 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4198
4199 return 0;
4200}
4201
4202static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4203 struct sk_buff *beacon,
4204 struct ieee80211_tx_control *ctl)
4205{
4206 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4207 unsigned long flags;
e66fee6a 4208
d4df6f1a 4209 spin_lock_irqsave(&wl->irq_lock, flags);
5042c507 4210 b43_update_templates(wl, beacon, ctl);
d4df6f1a 4211 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4212
4213 return 0;
4214}
4215
38968d09
JB		 4216static void b43_op_sta_notify(struct ieee80211_hw *hw,
4217 struct ieee80211_vif *vif,
4218 enum sta_notify_cmd notify_cmd,
4219 const u8 *addr)
4220{
4221 struct b43_wl *wl = hw_to_b43_wl(hw);
4222
4223 B43_WARN_ON(!vif || wl->vif != vif);
4224}
4225
e4d6b795 4226static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4227 .tx = b43_op_tx,
4228 .conf_tx = b43_op_conf_tx,
4229 .add_interface = b43_op_add_interface,
4230 .remove_interface = b43_op_remove_interface,
4231 .config = b43_op_config,
4232 .config_interface = b43_op_config_interface,
4233 .configure_filter = b43_op_configure_filter,
4234 .set_key = b43_op_set_key,
4235 .get_stats = b43_op_get_stats,
4236 .get_tx_stats = b43_op_get_tx_stats,
4237 .start = b43_op_start,
4238 .stop = b43_op_stop,
74cfdba7 4239 .set_retry_limit = b43_op_set_retry_limit,
e66fee6a
MB		 4240 .set_tim = b43_op_beacon_set_tim,
4241 .beacon_update = b43_op_ibss_beacon_update,
38968d09 4242 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4243};
4244
4245/* Hard-reset the chip. Do not call this directly.
4246 * Use b43_controller_restart()
4247 */
4248static void b43_chip_reset(struct work_struct *work)
4249{
4250 struct b43_wldev *dev =
4251 container_of(work, struct b43_wldev, restart_work);
4252 struct b43_wl *wl = dev->wl;
4253 int err = 0;
4254 int prev_status;
4255
4256 mutex_lock(&wl->mutex);
4257
4258 prev_status = b43_status(dev);
4259 /* Bring the device down... */
4260 if (prev_status >= B43_STAT_STARTED)
4261 b43_wireless_core_stop(dev);
4262 if (prev_status >= B43_STAT_INITIALIZED)
4263 b43_wireless_core_exit(dev);
4264
4265 /* ...and up again. */
4266 if (prev_status >= B43_STAT_INITIALIZED) {
4267 err = b43_wireless_core_init(dev);
4268 if (err)
4269 goto out;
4270 }
4271 if (prev_status >= B43_STAT_STARTED) {
4272 err = b43_wireless_core_start(dev);
4273 if (err) {
4274 b43_wireless_core_exit(dev);
4275 goto out;
4276 }
4277 }
3bf0a32e
MB		 4278out:
4279 if (err)
4280 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4281 mutex_unlock(&wl->mutex);
4282 if (err)
4283 b43err(wl, "Controller restart FAILED\n");
4284 else
4285 b43info(wl, "Controller restarted\n");
4286}
4287
bb1eeff1 4288static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4289 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4290{
4291 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4292
bb1eeff1
MB		 4293 if (have_2ghz_phy)
4294 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4295 if (dev->phy.type == B43_PHYTYPE_N) {
4296 if (have_5ghz_phy)
4297 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4298 } else {
4299 if (have_5ghz_phy)
4300 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4301 }
96c755a3 4302
bb1eeff1
MB		 4303 dev->phy.supports_2ghz = have_2ghz_phy;
4304 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4305
4306 return 0;
4307}
4308
4309static void b43_wireless_core_detach(struct b43_wldev *dev)
4310{
4311 /* We release firmware that late to not be required to re-request
4312 * is all the time when we reinit the core. */
4313 b43_release_firmware(dev);
4314}
4315
4316static int b43_wireless_core_attach(struct b43_wldev *dev)
4317{
4318 struct b43_wl *wl = dev->wl;
4319 struct ssb_bus *bus = dev->dev->bus;
4320 struct pci_dev *pdev = bus->host_pci;
4321 int err;
96c755a3 4322 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4323 u32 tmp;
4324
4325 /* Do NOT do any device initialization here.
4326 * Do it in wireless_core_init() instead.
4327 * This function is for gathering basic information about the HW, only.
4328 * Also some structs may be set up here. But most likely you want to have
4329 * that in core_init(), too.
4330 */
4331
4332 err = ssb_bus_powerup(bus, 0);
4333 if (err) {
4334 b43err(wl, "Bus powerup failed\n");
4335 goto out;
4336 }
4337 /* Get the PHY type. */
4338 if (dev->dev->id.revision >= 5) {
4339 u32 tmshigh;
4340
4341 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4342 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4343 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4344 } else
96c755a3 4345 B43_WARN_ON(1);
e4d6b795 4346
96c755a3 4347 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4348 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4349 b43_wireless_core_reset(dev, tmp);
4350
4351 err = b43_phy_versioning(dev);
4352 if (err)
21954c36 4353 goto err_powerdown;
e4d6b795
MB		 4354 /* Check if this device supports multiband. */
4355 if (!pdev ||
4356 (pdev->device != 0x4312 &&
4357 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4358 /* No multiband support. */
96c755a3
MB		 4359 have_2ghz_phy = 0;
4360 have_5ghz_phy = 0;
e4d6b795
MB		 4361 switch (dev->phy.type) {
4362 case B43_PHYTYPE_A:
96c755a3 4363 have_5ghz_phy = 1;
e4d6b795
MB		 4364 break;
4365 case B43_PHYTYPE_G:
96c755a3
MB		 4366 case B43_PHYTYPE_N:
4367 have_2ghz_phy = 1;
e4d6b795
MB		 4368 break;
4369 default:
4370 B43_WARN_ON(1);
4371 }
4372 }
96c755a3
MB		 4373 if (dev->phy.type == B43_PHYTYPE_A) {
4374 /* FIXME */
4375 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4376 err = -EOPNOTSUPP;
4377 goto err_powerdown;
4378 }
2e35af14
MB		 4379 if (1 /* disable A-PHY */) {
4380 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4381 if (dev->phy.type != B43_PHYTYPE_N) {
4382 have_2ghz_phy = 1;
4383 have_5ghz_phy = 0;
4384 }
4385 }
4386
96c755a3 4387 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4388 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4389 b43_wireless_core_reset(dev, tmp);
4390
4391 err = b43_validate_chipaccess(dev);
4392 if (err)
21954c36 4393 goto err_powerdown;
bb1eeff1 4394 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4395 if (err)
21954c36 4396 goto err_powerdown;
e4d6b795
MB		 4397
4398 /* Now set some default "current_dev" */
4399 if (!wl->current_dev)
4400 wl->current_dev = dev;
4401 INIT_WORK(&dev->restart_work, b43_chip_reset);
4402
8e9f7529 4403 b43_radio_turn_off(dev, 1);
e4d6b795
MB		 4404 b43_switch_analog(dev, 0);
4405 ssb_device_disable(dev->dev, 0);
4406 ssb_bus_may_powerdown(bus);
4407
4408out:
4409 return err;
4410
e4d6b795
MB		 4411err_powerdown:
4412 ssb_bus_may_powerdown(bus);
4413 return err;
4414}
4415
4416static void b43_one_core_detach(struct ssb_device *dev)
4417{
4418 struct b43_wldev *wldev;
4419 struct b43_wl *wl;
4420
3bf0a32e
MB		 4421 /* Do not cancel ieee80211-workqueue based work here.
4422 * See comment in b43_remove(). */
4423
e4d6b795
MB		 4424 wldev = ssb_get_drvdata(dev);
4425 wl = wldev->wl;
e4d6b795
MB		 4426 b43_debugfs_remove_device(wldev);
4427 b43_wireless_core_detach(wldev);
4428 list_del(&wldev->list);
4429 wl->nr_devs--;
4430 ssb_set_drvdata(dev, NULL);
4431 kfree(wldev);
4432}
4433
4434static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4435{
4436 struct b43_wldev *wldev;
4437 struct pci_dev *pdev;
4438 int err = -ENOMEM;
4439
4440 if (!list_empty(&wl->devlist)) {
4441 /* We are not the first core on this chip. */
4442 pdev = dev->bus->host_pci;
4443 /* Only special chips support more than one wireless
4444 * core, although some of the other chips have more than
4445 * one wireless core as well. Check for this and
4446 * bail out early.
4447 */
4448 if (!pdev ||
4449 ((pdev->device != 0x4321) &&
4450 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4451 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4452 return -ENODEV;
4453 }
4454 }
4455
4456 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4457 if (!wldev)
4458 goto out;
4459
4460 wldev->dev = dev;
4461 wldev->wl = wl;
4462 b43_set_status(wldev, B43_STAT_UNINIT);
4463 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4464 tasklet_init(&wldev->isr_tasklet,
4465 (void (*)(unsigned long))b43_interrupt_tasklet,
4466 (unsigned long)wldev);
e4d6b795
MB		 4467 INIT_LIST_HEAD(&wldev->list);
4468
4469 err = b43_wireless_core_attach(wldev);
4470 if (err)
4471 goto err_kfree_wldev;
4472
4473 list_add(&wldev->list, &wl->devlist);
4474 wl->nr_devs++;
4475 ssb_set_drvdata(dev, wldev);
4476 b43_debugfs_add_device(wldev);
4477
4478 out:
4479 return err;
4480
4481 err_kfree_wldev:
4482 kfree(wldev);
4483 return err;
4484}
4485
9fc38458
MB		 4486#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4487 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4488 (pdev->device == _device) && \
4489 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4490 (pdev->subsystem_device == _subdevice) )
4491
e4d6b795
MB		 4492static void b43_sprom_fixup(struct ssb_bus *bus)
4493{
1855ba78
MB		 4494 struct pci_dev *pdev;
4495
e4d6b795
MB		 4496 /* boardflags workarounds */
4497 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4498 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4499 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4500 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4501 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4502 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4503 if (bus->bustype == SSB_BUSTYPE_PCI) {
4504 pdev = bus->host_pci;
9fc38458
MB		 4505 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4506 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4507 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
1855ba78
MB		 4508 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4509 }
e4d6b795
MB		 4510}
4511
4512static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4513{
4514 struct ieee80211_hw *hw = wl->hw;
4515
4516 ssb_set_devtypedata(dev, NULL);
4517 ieee80211_free_hw(hw);
4518}
4519
4520static int b43_wireless_init(struct ssb_device *dev)
4521{
4522 struct ssb_sprom *sprom = &dev->bus->sprom;
4523 struct ieee80211_hw *hw;
4524 struct b43_wl *wl;
4525 int err = -ENOMEM;
4526
4527 b43_sprom_fixup(dev->bus);
4528
4529 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4530 if (!hw) {
4531 b43err(NULL, "Could not allocate ieee80211 device\n");
4532 goto out;
4533 }
4534
4535 /* fill hw info */
d8be11ee
JB		 4536 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4537 IEEE80211_HW_RX_INCLUDES_FCS;
e4d6b795
MB		 4538 hw->max_signal = 100;
4539 hw->max_rssi = -110;
4540 hw->max_noise = -110;
e6f5b934 4541 hw->queues = b43_modparam_qos ? 4 : 1;
e4d6b795 4542 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4543 if (is_valid_ether_addr(sprom->et1mac))
4544 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4545 else
95de2841 4546 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4547
4548 /* Get and initialize struct b43_wl */
4549 wl = hw_to_b43_wl(hw);
4550 memset(wl, 0, sizeof(*wl));
4551 wl->hw = hw;
4552 spin_lock_init(&wl->irq_lock);
21a75d77 4553 rwlock_init(&wl->tx_lock);
e4d6b795 4554 spin_lock_init(&wl->leds_lock);
280d0e16 4555 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4556 mutex_init(&wl->mutex);
4557 INIT_LIST_HEAD(&wl->devlist);
e6f5b934 4558 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
a82d9922 4559 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
e4d6b795
MB		 4560
4561 ssb_set_devtypedata(dev, wl);
4562 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4563 err = 0;
4564 out:
4565 return err;
4566}
4567
4568static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4569{
4570 struct b43_wl *wl;
4571 int err;
4572 int first = 0;
4573
4574 wl = ssb_get_devtypedata(dev);
4575 if (!wl) {
4576 /* Probing the first core. Must setup common struct b43_wl */
4577 first = 1;
4578 err = b43_wireless_init(dev);
4579 if (err)
4580 goto out;
4581 wl = ssb_get_devtypedata(dev);
4582 B43_WARN_ON(!wl);
4583 }
4584 err = b43_one_core_attach(dev, wl);
4585 if (err)
4586 goto err_wireless_exit;
4587
4588 if (first) {
4589 err = ieee80211_register_hw(wl->hw);
4590 if (err)
4591 goto err_one_core_detach;
4592 }
4593
4594 out:
4595 return err;
4596
4597 err_one_core_detach:
4598 b43_one_core_detach(dev);
4599 err_wireless_exit:
4600 if (first)
4601 b43_wireless_exit(dev, wl);
4602 return err;
4603}
4604
4605static void b43_remove(struct ssb_device *dev)
4606{
4607 struct b43_wl *wl = ssb_get_devtypedata(dev);
4608 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4609
3bf0a32e
MB		 4610 /* We must cancel any work here before unregistering from ieee80211,
4611 * as the ieee80211 unreg will destroy the workqueue. */
4612 cancel_work_sync(&wldev->restart_work);
4613
e4d6b795
MB		 4614 B43_WARN_ON(!wl);
4615 if (wl->current_dev == wldev)
4616 ieee80211_unregister_hw(wl->hw);
4617
4618 b43_one_core_detach(dev);
4619
4620 if (list_empty(&wl->devlist)) {
4621 /* Last core on the chip unregistered.
4622 * We can destroy common struct b43_wl.
4623 */
4624 b43_wireless_exit(dev, wl);
4625 }
4626}
4627
4628/* Perform a hardware reset. This can be called from any context. */
4629void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4630{
4631 /* Must avoid requeueing, if we are in shutdown. */
4632 if (b43_status(dev) < B43_STAT_INITIALIZED)
4633 return;
4634 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4635 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4636}
4637
4638#ifdef CONFIG_PM
4639
4640static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4641{
4642 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4643 struct b43_wl *wl = wldev->wl;
4644
4645 b43dbg(wl, "Suspending...\n");
4646
4647 mutex_lock(&wl->mutex);
3506e0c4 4648 wldev->suspend_in_progress = true;
e4d6b795
MB		 4649 wldev->suspend_init_status = b43_status(wldev);
4650 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4651 b43_wireless_core_stop(wldev);
4652 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4653 b43_wireless_core_exit(wldev);
4654 mutex_unlock(&wl->mutex);
4655
4656 b43dbg(wl, "Device suspended.\n");
4657
4658 return 0;
4659}
4660
4661static int b43_resume(struct ssb_device *dev)
4662{
4663 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4664 struct b43_wl *wl = wldev->wl;
4665 int err = 0;
4666
4667 b43dbg(wl, "Resuming...\n");
4668
4669 mutex_lock(&wl->mutex);
4670 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4671 err = b43_wireless_core_init(wldev);
4672 if (err) {
4673 b43err(wl, "Resume failed at core init\n");
4674 goto out;
4675 }
4676 }
4677 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4678 err = b43_wireless_core_start(wldev);
4679 if (err) {
3506e0c4 4680 b43_leds_exit(wldev);
b844eba2 4681 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4682 b43_wireless_core_exit(wldev);
4683 b43err(wl, "Resume failed at core start\n");
4684 goto out;
4685 }
4686 }
e4d6b795 4687 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4688 out:
4689 wldev->suspend_in_progress = false;
4690 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4691 return err;
4692}
4693
4694#else /* CONFIG_PM */
4695# define b43_suspend NULL
4696# define b43_resume NULL
4697#endif /* CONFIG_PM */
4698
4699static struct ssb_driver b43_ssb_driver = {
4700 .name = KBUILD_MODNAME,
4701 .id_table = b43_ssb_tbl,
4702 .probe = b43_probe,
4703 .remove = b43_remove,
4704 .suspend = b43_suspend,
4705 .resume = b43_resume,
4706};
4707
26bc783f
MB		 4708static void b43_print_driverinfo(void)
4709{
4710 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4711 *feat_leds = "", *feat_rfkill = "";
4712
4713#ifdef CONFIG_B43_PCI_AUTOSELECT
4714 feat_pci = "P";
4715#endif
4716#ifdef CONFIG_B43_PCMCIA
4717 feat_pcmcia = "M";
4718#endif
4719#ifdef CONFIG_B43_NPHY
4720 feat_nphy = "N";
4721#endif
4722#ifdef CONFIG_B43_LEDS
4723 feat_leds = "L";
4724#endif
4725#ifdef CONFIG_B43_RFKILL
4726 feat_rfkill = "R";
4727#endif
4728 printk(KERN_INFO "Broadcom 43xx driver loaded "
4729 "[ Features: %s%s%s%s%s, Firmware-ID: "
4730 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4731 feat_pci, feat_pcmcia, feat_nphy,
4732 feat_leds, feat_rfkill);
4733}
4734
e4d6b795
MB		 4735static int __init b43_init(void)
4736{
4737 int err;
4738
4739 b43_debugfs_init();
4740 err = b43_pcmcia_init();
4741 if (err)
4742 goto err_dfs_exit;
4743 err = ssb_driver_register(&b43_ssb_driver);
4744 if (err)
4745 goto err_pcmcia_exit;
26bc783f 4746 b43_print_driverinfo();
e4d6b795
MB		 4747
4748 return err;
4749
4750err_pcmcia_exit:
4751 b43_pcmcia_exit();
4752err_dfs_exit:
4753 b43_debugfs_exit();
4754 return err;
4755}
4756
4757static void __exit b43_exit(void)
4758{
4759 ssb_driver_unregister(&b43_ssb_driver);
4760 b43_pcmcia_exit();
4761 b43_debugfs_exit();
4762}
4763
4764module_init(b43_init)
4765module_exit(b43_exit)
Linux kernel - Deliverables
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