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libertas: fix warning about %zd:
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
060210f9
MB		 91int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
92module_param_named(verbose, b43_modparam_verbose, int, 0644);
93MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
94
e6f5b934 95
e4d6b795
MB		 96static const struct ssb_device_id b43_ssb_tbl[] = {
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 106 SSB_DEVTABLE_END
107};
108
109MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
110
111/* Channel and ratetables are shared for all devices.
112 * They can't be const, because ieee80211 puts some precalculated
113 * data in there. This data is the same for all devices, so we don't
114 * get concurrency issues */
115#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 116 { \
117 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
118 .hw_value = (_rateid), \
119 .flags = (_flags), \
e4d6b795 120 }
8318d78a
JB		 121
122/*
123 * NOTE: When changing this, sync with xmit.c's
124 * b43_plcp_get_bitrate_idx_* functions!
125 */
e4d6b795 126static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 127 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
128 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
129 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
130 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
131 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
135 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
136 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 139};
140
141#define b43_a_ratetable (__b43_ratetable + 4)
142#define b43_a_ratetable_size 8
143#define b43_b_ratetable (__b43_ratetable + 0)
144#define b43_b_ratetable_size 4
145#define b43_g_ratetable (__b43_ratetable + 0)
146#define b43_g_ratetable_size 12
147
bb1eeff1
MB		 148#define CHAN4G(_channel, _freq, _flags) { \
149 .band = IEEE80211_BAND_2GHZ, \
150 .center_freq = (_freq), \
151 .hw_value = (_channel), \
152 .flags = (_flags), \
153 .max_antenna_gain = 0, \
154 .max_power = 30, \
155}
96c755a3 156static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 157 CHAN4G(1, 2412, 0),
158 CHAN4G(2, 2417, 0),
159 CHAN4G(3, 2422, 0),
160 CHAN4G(4, 2427, 0),
161 CHAN4G(5, 2432, 0),
162 CHAN4G(6, 2437, 0),
163 CHAN4G(7, 2442, 0),
164 CHAN4G(8, 2447, 0),
165 CHAN4G(9, 2452, 0),
166 CHAN4G(10, 2457, 0),
167 CHAN4G(11, 2462, 0),
168 CHAN4G(12, 2467, 0),
169 CHAN4G(13, 2472, 0),
170 CHAN4G(14, 2484, 0),
171};
172#undef CHAN4G
173
174#define CHAN5G(_channel, _flags) { \
175 .band = IEEE80211_BAND_5GHZ, \
176 .center_freq = 5000 + (5 * (_channel)), \
177 .hw_value = (_channel), \
178 .flags = (_flags), \
179 .max_antenna_gain = 0, \
180 .max_power = 30, \
181}
182static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
183 CHAN5G(32, 0), CHAN5G(34, 0),
184 CHAN5G(36, 0), CHAN5G(38, 0),
185 CHAN5G(40, 0), CHAN5G(42, 0),
186 CHAN5G(44, 0), CHAN5G(46, 0),
187 CHAN5G(48, 0), CHAN5G(50, 0),
188 CHAN5G(52, 0), CHAN5G(54, 0),
189 CHAN5G(56, 0), CHAN5G(58, 0),
190 CHAN5G(60, 0), CHAN5G(62, 0),
191 CHAN5G(64, 0), CHAN5G(66, 0),
192 CHAN5G(68, 0), CHAN5G(70, 0),
193 CHAN5G(72, 0), CHAN5G(74, 0),
194 CHAN5G(76, 0), CHAN5G(78, 0),
195 CHAN5G(80, 0), CHAN5G(82, 0),
196 CHAN5G(84, 0), CHAN5G(86, 0),
197 CHAN5G(88, 0), CHAN5G(90, 0),
198 CHAN5G(92, 0), CHAN5G(94, 0),
199 CHAN5G(96, 0), CHAN5G(98, 0),
200 CHAN5G(100, 0), CHAN5G(102, 0),
201 CHAN5G(104, 0), CHAN5G(106, 0),
202 CHAN5G(108, 0), CHAN5G(110, 0),
203 CHAN5G(112, 0), CHAN5G(114, 0),
204 CHAN5G(116, 0), CHAN5G(118, 0),
205 CHAN5G(120, 0), CHAN5G(122, 0),
206 CHAN5G(124, 0), CHAN5G(126, 0),
207 CHAN5G(128, 0), CHAN5G(130, 0),
208 CHAN5G(132, 0), CHAN5G(134, 0),
209 CHAN5G(136, 0), CHAN5G(138, 0),
210 CHAN5G(140, 0), CHAN5G(142, 0),
211 CHAN5G(144, 0), CHAN5G(145, 0),
212 CHAN5G(146, 0), CHAN5G(147, 0),
213 CHAN5G(148, 0), CHAN5G(149, 0),
214 CHAN5G(150, 0), CHAN5G(151, 0),
215 CHAN5G(152, 0), CHAN5G(153, 0),
216 CHAN5G(154, 0), CHAN5G(155, 0),
217 CHAN5G(156, 0), CHAN5G(157, 0),
218 CHAN5G(158, 0), CHAN5G(159, 0),
219 CHAN5G(160, 0), CHAN5G(161, 0),
220 CHAN5G(162, 0), CHAN5G(163, 0),
221 CHAN5G(164, 0), CHAN5G(165, 0),
222 CHAN5G(166, 0), CHAN5G(168, 0),
223 CHAN5G(170, 0), CHAN5G(172, 0),
224 CHAN5G(174, 0), CHAN5G(176, 0),
225 CHAN5G(178, 0), CHAN5G(180, 0),
226 CHAN5G(182, 0), CHAN5G(184, 0),
227 CHAN5G(186, 0), CHAN5G(188, 0),
228 CHAN5G(190, 0), CHAN5G(192, 0),
229 CHAN5G(194, 0), CHAN5G(196, 0),
230 CHAN5G(198, 0), CHAN5G(200, 0),
231 CHAN5G(202, 0), CHAN5G(204, 0),
232 CHAN5G(206, 0), CHAN5G(208, 0),
233 CHAN5G(210, 0), CHAN5G(212, 0),
234 CHAN5G(214, 0), CHAN5G(216, 0),
235 CHAN5G(218, 0), CHAN5G(220, 0),
236 CHAN5G(222, 0), CHAN5G(224, 0),
237 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 238};
239
bb1eeff1
MB		 240static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
241 CHAN5G(34, 0), CHAN5G(36, 0),
242 CHAN5G(38, 0), CHAN5G(40, 0),
243 CHAN5G(42, 0), CHAN5G(44, 0),
244 CHAN5G(46, 0), CHAN5G(48, 0),
245 CHAN5G(52, 0), CHAN5G(56, 0),
246 CHAN5G(60, 0), CHAN5G(64, 0),
247 CHAN5G(100, 0), CHAN5G(104, 0),
248 CHAN5G(108, 0), CHAN5G(112, 0),
249 CHAN5G(116, 0), CHAN5G(120, 0),
250 CHAN5G(124, 0), CHAN5G(128, 0),
251 CHAN5G(132, 0), CHAN5G(136, 0),
252 CHAN5G(140, 0), CHAN5G(149, 0),
253 CHAN5G(153, 0), CHAN5G(157, 0),
254 CHAN5G(161, 0), CHAN5G(165, 0),
255 CHAN5G(184, 0), CHAN5G(188, 0),
256 CHAN5G(192, 0), CHAN5G(196, 0),
257 CHAN5G(200, 0), CHAN5G(204, 0),
258 CHAN5G(208, 0), CHAN5G(212, 0),
259 CHAN5G(216, 0),
260};
261#undef CHAN5G
262
263static struct ieee80211_supported_band b43_band_5GHz_nphy = {
264 .band = IEEE80211_BAND_5GHZ,
265 .channels = b43_5ghz_nphy_chantable,
266 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
267 .bitrates = b43_a_ratetable,
268 .n_bitrates = b43_a_ratetable_size,
e4d6b795 269};
8318d78a 270
bb1eeff1
MB		 271static struct ieee80211_supported_band b43_band_5GHz_aphy = {
272 .band = IEEE80211_BAND_5GHZ,
273 .channels = b43_5ghz_aphy_chantable,
274 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
275 .bitrates = b43_a_ratetable,
276 .n_bitrates = b43_a_ratetable_size,
8318d78a 277};
e4d6b795 278
8318d78a 279static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 280 .band = IEEE80211_BAND_2GHZ,
281 .channels = b43_2ghz_chantable,
282 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
283 .bitrates = b43_g_ratetable,
284 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 285};
286
e4d6b795
MB		 287static void b43_wireless_core_exit(struct b43_wldev *dev);
288static int b43_wireless_core_init(struct b43_wldev *dev);
289static void b43_wireless_core_stop(struct b43_wldev *dev);
290static int b43_wireless_core_start(struct b43_wldev *dev);
291
292static int b43_ratelimit(struct b43_wl *wl)
293{
294 if (!wl || !wl->current_dev)
295 return 1;
296 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
297 return 1;
298 /* We are up and running.
299 * Ratelimit the messages to avoid DoS over the net. */
300 return net_ratelimit();
301}
302
303void b43info(struct b43_wl *wl, const char *fmt, ...)
304{
305 va_list args;
306
060210f9
MB		 307 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
308 return;
e4d6b795
MB		 309 if (!b43_ratelimit(wl))
310 return;
311 va_start(args, fmt);
312 printk(KERN_INFO "b43-%s: ",
313 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
314 vprintk(fmt, args);
315 va_end(args);
316}
317
318void b43err(struct b43_wl *wl, const char *fmt, ...)
319{
320 va_list args;
321
060210f9
MB		 322 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
323 return;
e4d6b795
MB		 324 if (!b43_ratelimit(wl))
325 return;
326 va_start(args, fmt);
327 printk(KERN_ERR "b43-%s ERROR: ",
328 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
329 vprintk(fmt, args);
330 va_end(args);
331}
332
333void b43warn(struct b43_wl *wl, const char *fmt, ...)
334{
335 va_list args;
336
060210f9
MB		 337 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
338 return;
e4d6b795
MB		 339 if (!b43_ratelimit(wl))
340 return;
341 va_start(args, fmt);
342 printk(KERN_WARNING "b43-%s warning: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347
e4d6b795
MB		 348void b43dbg(struct b43_wl *wl, const char *fmt, ...)
349{
350 va_list args;
351
060210f9
MB		 352 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
353 return;
e4d6b795
MB		 354 va_start(args, fmt);
355 printk(KERN_DEBUG "b43-%s debug: ",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
357 vprintk(fmt, args);
358 va_end(args);
359}
e4d6b795
MB		 360
361static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
362{
363 u32 macctl;
364
365 B43_WARN_ON(offset % 4 != 0);
366
367 macctl = b43_read32(dev, B43_MMIO_MACCTL);
368 if (macctl & B43_MACCTL_BE)
369 val = swab32(val);
370
371 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
372 mmiowb();
373 b43_write32(dev, B43_MMIO_RAM_DATA, val);
374}
375
280d0e16
MB		 376static inline void b43_shm_control_word(struct b43_wldev *dev,
377 u16 routing, u16 offset)
e4d6b795
MB		 378{
379 u32 control;
380
381 /* "offset" is the WORD offset. */
e4d6b795
MB		 382 control = routing;
383 control <<= 16;
384 control |= offset;
385 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
386}
387
6bbc321a 388u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 389{
390 u32 ret;
391
392 if (routing == B43_SHM_SHARED) {
393 B43_WARN_ON(offset & 0x0001);
394 if (offset & 0x0003) {
395 /* Unaligned access */
396 b43_shm_control_word(dev, routing, offset >> 2);
397 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
398 ret <<= 16;
399 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
400 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
401
280d0e16 402 goto out;
e4d6b795
MB		 403 }
404 offset >>= 2;
405 }
406 b43_shm_control_word(dev, routing, offset);
407 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 408out:
e4d6b795
MB		 409 return ret;
410}
411
6bbc321a 412u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 413{
280d0e16
MB		 414 struct b43_wl *wl = dev->wl;
415 unsigned long flags;
6bbc321a 416 u32 ret;
e4d6b795 417
280d0e16 418 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 419 ret = __b43_shm_read32(dev, routing, offset);
420 spin_unlock_irqrestore(&wl->shm_lock, flags);
421
422 return ret;
423}
424
425u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
426{
427 u16 ret;
428
e4d6b795
MB		 429 if (routing == B43_SHM_SHARED) {
430 B43_WARN_ON(offset & 0x0001);
431 if (offset & 0x0003) {
432 /* Unaligned access */
433 b43_shm_control_word(dev, routing, offset >> 2);
434 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
435
280d0e16 436 goto out;
e4d6b795
MB		 437 }
438 offset >>= 2;
439 }
440 b43_shm_control_word(dev, routing, offset);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 442out:
e4d6b795
MB		 443 return ret;
444}
445
6bbc321a 446u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 447{
280d0e16
MB		 448 struct b43_wl *wl = dev->wl;
449 unsigned long flags;
6bbc321a 450 u16 ret;
280d0e16
MB		 451
452 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 453 ret = __b43_shm_read16(dev, routing, offset);
454 spin_unlock_irqrestore(&wl->shm_lock, flags);
455
456 return ret;
457}
458
459void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
460{
e4d6b795
MB		 461 if (routing == B43_SHM_SHARED) {
462 B43_WARN_ON(offset & 0x0001);
463 if (offset & 0x0003) {
464 /* Unaligned access */
465 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 466 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
467 (value >> 16) & 0xffff);
e4d6b795 468 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 469 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 470 return;
e4d6b795
MB		 471 }
472 offset >>= 2;
473 }
474 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 475 b43_write32(dev, B43_MMIO_SHM_DATA, value);
476}
477
6bbc321a 478void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 479{
280d0e16
MB		 480 struct b43_wl *wl = dev->wl;
481 unsigned long flags;
482
483 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 484 __b43_shm_write32(dev, routing, offset, value);
485 spin_unlock_irqrestore(&wl->shm_lock, flags);
486}
487
488void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
489{
e4d6b795
MB		 490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 495 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 496 return;
e4d6b795
MB		 497 }
498 offset >>= 2;
499 }
500 b43_shm_control_word(dev, routing, offset);
e4d6b795 501 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 502}
503
504void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
505{
506 struct b43_wl *wl = dev->wl;
507 unsigned long flags;
508
509 spin_lock_irqsave(&wl->shm_lock, flags);
510 __b43_shm_write16(dev, routing, offset, value);
280d0e16 511 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 512}
513
514/* Read HostFlags */
99da185a 515u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 516{
35f0d354 517 u64 ret;
e4d6b795
MB		 518
519 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
520 ret <<= 16;
35f0d354
MB		 521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
522 ret <<= 16;
e4d6b795
MB		 523 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
524
525 return ret;
526}
527
528/* Write HostFlags */
35f0d354 529void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 530{
35f0d354
MB		 531 u16 lo, mi, hi;
532
533 lo = (value & 0x00000000FFFFULL);
534 mi = (value & 0x0000FFFF0000ULL) >> 16;
535 hi = (value & 0xFFFF00000000ULL) >> 32;
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
538 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 539}
540
3ebbbb56 541void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 542{
3ebbbb56
MB		 543 u32 low, high;
544
545 B43_WARN_ON(dev->dev->id.revision < 3);
546
547 /* The hardware guarantees us an atomic read, if we
548 * read the low register first. */
549 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
550 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
551
552 *tsf = high;
553 *tsf <<= 32;
554 *tsf |= low;
e4d6b795
MB		 555}
556
557static void b43_time_lock(struct b43_wldev *dev)
558{
559 u32 macctl;
560
561 macctl = b43_read32(dev, B43_MMIO_MACCTL);
562 macctl |= B43_MACCTL_TBTTHOLD;
563 b43_write32(dev, B43_MMIO_MACCTL, macctl);
564 /* Commit the write */
565 b43_read32(dev, B43_MMIO_MACCTL);
566}
567
568static void b43_time_unlock(struct b43_wldev *dev)
569{
570 u32 macctl;
571
572 macctl = b43_read32(dev, B43_MMIO_MACCTL);
573 macctl &= ~B43_MACCTL_TBTTHOLD;
574 b43_write32(dev, B43_MMIO_MACCTL, macctl);
575 /* Commit the write */
576 b43_read32(dev, B43_MMIO_MACCTL);
577}
578
579static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
580{
3ebbbb56
MB		 581 u32 low, high;
582
583 B43_WARN_ON(dev->dev->id.revision < 3);
584
585 low = tsf;
586 high = (tsf >> 32);
587 /* The hardware guarantees us an atomic write, if we
588 * write the low register first. */
589 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
590 mmiowb();
591 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
592 mmiowb();
e4d6b795
MB		 593}
594
595void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
596{
597 b43_time_lock(dev);
598 b43_tsf_write_locked(dev, tsf);
599 b43_time_unlock(dev);
600}
601
602static
99da185a 603void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 604{
605 static const u8 zero_addr[ETH_ALEN] = { 0 };
606 u16 data;
607
608 if (!mac)
609 mac = zero_addr;
610
611 offset |= 0x0020;
612 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
613
614 data = mac[0];
615 data |= mac[1] << 8;
616 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
617 data = mac[2];
618 data |= mac[3] << 8;
619 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
620 data = mac[4];
621 data |= mac[5] << 8;
622 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
623}
624
625static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
626{
627 const u8 *mac;
628 const u8 *bssid;
629 u8 mac_bssid[ETH_ALEN * 2];
630 int i;
631 u32 tmp;
632
633 bssid = dev->wl->bssid;
634 mac = dev->wl->mac_addr;
635
636 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
637
638 memcpy(mac_bssid, mac, ETH_ALEN);
639 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
640
641 /* Write our MAC address and BSSID to template ram */
642 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
643 tmp = (u32) (mac_bssid[i + 0]);
644 tmp |= (u32) (mac_bssid[i + 1]) << 8;
645 tmp |= (u32) (mac_bssid[i + 2]) << 16;
646 tmp |= (u32) (mac_bssid[i + 3]) << 24;
647 b43_ram_write(dev, 0x20 + i, tmp);
648 }
649}
650
4150c572 651static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 652{
e4d6b795 653 b43_write_mac_bssid_templates(dev);
4150c572 654 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 655}
656
657static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
658{
659 /* slot_time is in usec. */
660 if (dev->phy.type != B43_PHYTYPE_G)
661 return;
662 b43_write16(dev, 0x684, 510 + slot_time);
663 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
664}
665
666static void b43_short_slot_timing_enable(struct b43_wldev *dev)
667{
668 b43_set_slot_time(dev, 9);
e4d6b795
MB		 669}
670
671static void b43_short_slot_timing_disable(struct b43_wldev *dev)
672{
673 b43_set_slot_time(dev, 20);
e4d6b795
MB		 674}
675
676/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
677 * Returns the _previously_ enabled IRQ mask.
678 */
679static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
680{
681 u32 old_mask;
682
683 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
684 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
685
686 return old_mask;
687}
688
689/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
690 * Returns the _previously_ enabled IRQ mask.
691 */
692static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
693{
694 u32 old_mask;
695
696 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
697 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
698
699 return old_mask;
700}
701
702/* Synchronize IRQ top- and bottom-half.
703 * IRQs must be masked before calling this.
704 * This must not be called with the irq_lock held.
705 */
706static void b43_synchronize_irq(struct b43_wldev *dev)
707{
708 synchronize_irq(dev->dev->irq);
709 tasklet_kill(&dev->isr_tasklet);
710}
711
712/* DummyTransmission function, as documented on
713 * http://bcm-specs.sipsolutions.net/DummyTransmission
714 */
715void b43_dummy_transmission(struct b43_wldev *dev)
716{
21a75d77 717 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 718 struct b43_phy *phy = &dev->phy;
719 unsigned int i, max_loop;
720 u16 value;
721 u32 buffer[5] = {
722 0x00000000,
723 0x00D40000,
724 0x00000000,
725 0x01000000,
726 0x00000000,
727 };
728
729 switch (phy->type) {
730 case B43_PHYTYPE_A:
731 max_loop = 0x1E;
732 buffer[0] = 0x000201CC;
733 break;
734 case B43_PHYTYPE_B:
735 case B43_PHYTYPE_G:
736 max_loop = 0xFA;
737 buffer[0] = 0x000B846E;
738 break;
739 default:
740 B43_WARN_ON(1);
741 return;
742 }
743
21a75d77
MB		 744 spin_lock_irq(&wl->irq_lock);
745 write_lock(&wl->tx_lock);
746
e4d6b795
MB		 747 for (i = 0; i < 5; i++)
748 b43_ram_write(dev, i * 4, buffer[i]);
749
750 /* Commit writes */
751 b43_read32(dev, B43_MMIO_MACCTL);
752
753 b43_write16(dev, 0x0568, 0x0000);
754 b43_write16(dev, 0x07C0, 0x0000);
755 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
756 b43_write16(dev, 0x050C, value);
757 b43_write16(dev, 0x0508, 0x0000);
758 b43_write16(dev, 0x050A, 0x0000);
759 b43_write16(dev, 0x054C, 0x0000);
760 b43_write16(dev, 0x056A, 0x0014);
761 b43_write16(dev, 0x0568, 0x0826);
762 b43_write16(dev, 0x0500, 0x0000);
763 b43_write16(dev, 0x0502, 0x0030);
764
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0017);
767 for (i = 0x00; i < max_loop; i++) {
768 value = b43_read16(dev, 0x050E);
769 if (value & 0x0080)
770 break;
771 udelay(10);
772 }
773 for (i = 0x00; i < 0x0A; i++) {
774 value = b43_read16(dev, 0x050E);
775 if (value & 0x0400)
776 break;
777 udelay(10);
778 }
1d280ddc 779 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 780 value = b43_read16(dev, 0x0690);
781 if (!(value & 0x0100))
782 break;
783 udelay(10);
784 }
785 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
786 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 787
788 write_unlock(&wl->tx_lock);
789 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 790}
791
792static void key_write(struct b43_wldev *dev,
99da185a 793 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 794{
795 unsigned int i;
796 u32 offset;
797 u16 value;
798 u16 kidx;
799
800 /* Key index/algo block */
801 kidx = b43_kidx_to_fw(dev, index);
802 value = ((kidx << 4) | algorithm);
803 b43_shm_write16(dev, B43_SHM_SHARED,
804 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
805
806 /* Write the key to the Key Table Pointer offset */
807 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
808 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
809 value = key[i];
810 value |= (u16) (key[i + 1]) << 8;
811 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
812 }
813}
814
99da185a 815static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 816{
817 u32 addrtmp[2] = { 0, 0, };
818 u8 per_sta_keys_start = 8;
819
820 if (b43_new_kidx_api(dev))
821 per_sta_keys_start = 4;
822
823 B43_WARN_ON(index < per_sta_keys_start);
824 /* We have two default TX keys and possibly two default RX keys.
825 * Physical mac 0 is mapped to physical key 4 or 8, depending
826 * on the firmware version.
827 * So we must adjust the index here.
828 */
829 index -= per_sta_keys_start;
830
831 if (addr) {
832 addrtmp[0] = addr[0];
833 addrtmp[0] |= ((u32) (addr[1]) << 8);
834 addrtmp[0] |= ((u32) (addr[2]) << 16);
835 addrtmp[0] |= ((u32) (addr[3]) << 24);
836 addrtmp[1] = addr[4];
837 addrtmp[1] |= ((u32) (addr[5]) << 8);
838 }
839
840 if (dev->dev->id.revision >= 5) {
841 /* Receive match transmitter address mechanism */
842 b43_shm_write32(dev, B43_SHM_RCMTA,
843 (index * 2) + 0, addrtmp[0]);
844 b43_shm_write16(dev, B43_SHM_RCMTA,
845 (index * 2) + 1, addrtmp[1]);
846 } else {
847 /* RXE (Receive Engine) and
848 * PSM (Programmable State Machine) mechanism
849 */
850 if (index < 8) {
851 /* TODO write to RCM 16, 19, 22 and 25 */
852 } else {
853 b43_shm_write32(dev, B43_SHM_SHARED,
854 B43_SHM_SH_PSM + (index * 6) + 0,
855 addrtmp[0]);
856 b43_shm_write16(dev, B43_SHM_SHARED,
857 B43_SHM_SH_PSM + (index * 6) + 4,
858 addrtmp[1]);
859 }
860 }
861}
862
863static void do_key_write(struct b43_wldev *dev,
864 u8 index, u8 algorithm,
99da185a 865 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 866{
867 u8 buf[B43_SEC_KEYSIZE] = { 0, };
868 u8 per_sta_keys_start = 8;
869
870 if (b43_new_kidx_api(dev))
871 per_sta_keys_start = 4;
872
873 B43_WARN_ON(index >= dev->max_nr_keys);
874 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
875
876 if (index >= per_sta_keys_start)
877 keymac_write(dev, index, NULL); /* First zero out mac. */
878 if (key)
879 memcpy(buf, key, key_len);
880 key_write(dev, index, algorithm, buf);
881 if (index >= per_sta_keys_start)
882 keymac_write(dev, index, mac_addr);
883
884 dev->key[index].algorithm = algorithm;
885}
886
887static int b43_key_write(struct b43_wldev *dev,
888 int index, u8 algorithm,
99da185a
JD		 889 const u8 *key, size_t key_len,
890 const u8 *mac_addr,
e4d6b795
MB		 891 struct ieee80211_key_conf *keyconf)
892{
893 int i;
894 int sta_keys_start;
895
896 if (key_len > B43_SEC_KEYSIZE)
897 return -EINVAL;
898 for (i = 0; i < dev->max_nr_keys; i++) {
899 /* Check that we don't already have this key. */
900 B43_WARN_ON(dev->key[i].keyconf == keyconf);
901 }
902 if (index < 0) {
e808e586 903 /* Pairwise key. Get an empty slot for the key. */
e4d6b795
MB		 904 if (b43_new_kidx_api(dev))
905 sta_keys_start = 4;
906 else
907 sta_keys_start = 8;
908 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
909 if (!dev->key[i].keyconf) {
910 /* found empty */
911 index = i;
912 break;
913 }
914 }
915 if (index < 0) {
e808e586 916 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 917 return -ENOSPC;
918 }
919 } else
920 B43_WARN_ON(index > 3);
921
922 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
923 if ((index <= 3) && !b43_new_kidx_api(dev)) {
924 /* Default RX key */
925 B43_WARN_ON(mac_addr);
926 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
927 }
928 keyconf->hw_key_idx = index;
929 dev->key[index].keyconf = keyconf;
930
931 return 0;
932}
933
934static int b43_key_clear(struct b43_wldev *dev, int index)
935{
936 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
937 return -EINVAL;
938 do_key_write(dev, index, B43_SEC_ALGO_NONE,
939 NULL, B43_SEC_KEYSIZE, NULL);
940 if ((index <= 3) && !b43_new_kidx_api(dev)) {
941 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
942 NULL, B43_SEC_KEYSIZE, NULL);
943 }
944 dev->key[index].keyconf = NULL;
945
946 return 0;
947}
948
949static void b43_clear_keys(struct b43_wldev *dev)
950{
951 int i;
952
953 for (i = 0; i < dev->max_nr_keys; i++)
954 b43_key_clear(dev, i);
955}
956
9cf7f247
MB		 957static void b43_dump_keymemory(struct b43_wldev *dev)
958{
959 unsigned int i, index, offset;
960 DECLARE_MAC_BUF(macbuf);
961 u8 mac[ETH_ALEN];
962 u16 algo;
963 u32 rcmta0;
964 u16 rcmta1;
965 u64 hf;
966 struct b43_key *key;
967
968 if (!b43_debug(dev, B43_DBG_KEYS))
969 return;
970
971 hf = b43_hf_read(dev);
972 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
973 !!(hf & B43_HF_USEDEFKEYS));
974 for (index = 0; index < dev->max_nr_keys; index++) {
975 key = &(dev->key[index]);
976 printk(KERN_DEBUG "Key slot %02u: %s",
977 index, (key->keyconf == NULL) ? " " : "*");
978 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
979 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
980 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
981 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
982 }
983
984 algo = b43_shm_read16(dev, B43_SHM_SHARED,
985 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
986 printk(" Algo: %04X/%02X", algo, key->algorithm);
987
988 if (index >= 4) {
989 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
990 ((index - 4) * 2) + 0);
991 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
992 ((index - 4) * 2) + 1);
993 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
994 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
995 printk(" MAC: %s",
996 print_mac(macbuf, mac));
997 } else
998 printk(" DEFAULT KEY");
999 printk("\n");
1000 }
1001}
1002
e4d6b795
MB		 1003void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1004{
1005 u32 macctl;
1006 u16 ucstat;
1007 bool hwps;
1008 bool awake;
1009 int i;
1010
1011 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1012 (ps_flags & B43_PS_DISABLED));
1013 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1014
1015 if (ps_flags & B43_PS_ENABLED) {
1016 hwps = 1;
1017 } else if (ps_flags & B43_PS_DISABLED) {
1018 hwps = 0;
1019 } else {
1020 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1021 // and thus is not an AP and we are associated, set bit 25
1022 }
1023 if (ps_flags & B43_PS_AWAKE) {
1024 awake = 1;
1025 } else if (ps_flags & B43_PS_ASLEEP) {
1026 awake = 0;
1027 } else {
1028 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1029 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1030 // successful, set bit26
1031 }
1032
1033/* FIXME: For now we force awake-on and hwps-off */
1034 hwps = 0;
1035 awake = 1;
1036
1037 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1038 if (hwps)
1039 macctl |= B43_MACCTL_HWPS;
1040 else
1041 macctl &= ~B43_MACCTL_HWPS;
1042 if (awake)
1043 macctl |= B43_MACCTL_AWAKE;
1044 else
1045 macctl &= ~B43_MACCTL_AWAKE;
1046 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1047 /* Commit write */
1048 b43_read32(dev, B43_MMIO_MACCTL);
1049 if (awake && dev->dev->id.revision >= 5) {
1050 /* Wait for the microcode to wake up. */
1051 for (i = 0; i < 100; i++) {
1052 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1053 B43_SHM_SH_UCODESTAT);
1054 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1055 break;
1056 udelay(10);
1057 }
1058 }
1059}
1060
e4d6b795
MB		 1061void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1062{
1063 u32 tmslow;
1064 u32 macctl;
1065
1066 flags |= B43_TMSLOW_PHYCLKEN;
1067 flags |= B43_TMSLOW_PHYRESET;
1068 ssb_device_enable(dev->dev, flags);
1069 msleep(2); /* Wait for the PLL to turn on. */
1070
1071 /* Now take the PHY out of Reset again */
1072 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1073 tmslow |= SSB_TMSLOW_FGC;
1074 tmslow &= ~B43_TMSLOW_PHYRESET;
1075 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1076 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1077 msleep(1);
1078 tmslow &= ~SSB_TMSLOW_FGC;
1079 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1080 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1081 msleep(1);
1082
fb11137a
MB		 1083 /* Turn Analog ON, but only if we already know the PHY-type.
1084 * This protects against very early setup where we don't know the
1085 * PHY-type, yet. wireless_core_reset will be called once again later,
1086 * when we know the PHY-type. */
1087 if (dev->phy.ops)
cb24f57f 1088 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1089
1090 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1091 macctl &= ~B43_MACCTL_GMODE;
1092 if (flags & B43_TMSLOW_GMODE)
1093 macctl |= B43_MACCTL_GMODE;
1094 macctl |= B43_MACCTL_IHR_ENABLED;
1095 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1096}
1097
1098static void handle_irq_transmit_status(struct b43_wldev *dev)
1099{
1100 u32 v0, v1;
1101 u16 tmp;
1102 struct b43_txstatus stat;
1103
1104 while (1) {
1105 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1106 if (!(v0 & 0x00000001))
1107 break;
1108 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1109
1110 stat.cookie = (v0 >> 16);
1111 stat.seq = (v1 & 0x0000FFFF);
1112 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1113 tmp = (v0 & 0x0000FFFF);
1114 stat.frame_count = ((tmp & 0xF000) >> 12);
1115 stat.rts_count = ((tmp & 0x0F00) >> 8);
1116 stat.supp_reason = ((tmp & 0x001C) >> 2);
1117 stat.pm_indicated = !!(tmp & 0x0080);
1118 stat.intermediate = !!(tmp & 0x0040);
1119 stat.for_ampdu = !!(tmp & 0x0020);
1120 stat.acked = !!(tmp & 0x0002);
1121
1122 b43_handle_txstatus(dev, &stat);
1123 }
1124}
1125
1126static void drain_txstatus_queue(struct b43_wldev *dev)
1127{
1128 u32 dummy;
1129
1130 if (dev->dev->id.revision < 5)
1131 return;
1132 /* Read all entries from the microcode TXstatus FIFO
1133 * and throw them away.
1134 */
1135 while (1) {
1136 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1137 if (!(dummy & 0x00000001))
1138 break;
1139 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1140 }
1141}
1142
1143static u32 b43_jssi_read(struct b43_wldev *dev)
1144{
1145 u32 val = 0;
1146
1147 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1148 val <<= 16;
1149 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1150
1151 return val;
1152}
1153
1154static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1155{
1156 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1157 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1158}
1159
1160static void b43_generate_noise_sample(struct b43_wldev *dev)
1161{
1162 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1163 b43_write32(dev, B43_MMIO_MACCMD,
1164 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1165}
1166
1167static void b43_calculate_link_quality(struct b43_wldev *dev)
1168{
1169 /* Top half of Link Quality calculation. */
1170
ef1a628d
MB		 1171 if (dev->phy.type != B43_PHYTYPE_G)
1172 return;
e4d6b795
MB		 1173 if (dev->noisecalc.calculation_running)
1174 return;
e4d6b795
MB		 1175 dev->noisecalc.calculation_running = 1;
1176 dev->noisecalc.nr_samples = 0;
1177
1178 b43_generate_noise_sample(dev);
1179}
1180
1181static void handle_irq_noise(struct b43_wldev *dev)
1182{
ef1a628d 1183 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1184 u16 tmp;
1185 u8 noise[4];
1186 u8 i, j;
1187 s32 average;
1188
1189 /* Bottom half of Link Quality calculation. */
1190
ef1a628d
MB		 1191 if (dev->phy.type != B43_PHYTYPE_G)
1192 return;
1193
98a3b2fe
MB		 1194 /* Possible race condition: It might be possible that the user
1195 * changed to a different channel in the meantime since we
1196 * started the calculation. We ignore that fact, since it's
1197 * not really that much of a problem. The background noise is
1198 * an estimation only anyway. Slightly wrong results will get damped
1199 * by the averaging of the 8 sample rounds. Additionally the
1200 * value is shortlived. So it will be replaced by the next noise
1201 * calculation round soon. */
1202
e4d6b795 1203 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1204 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1205 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1206 noise[2] == 0x7F || noise[3] == 0x7F)
1207 goto generate_new;
1208
1209 /* Get the noise samples. */
1210 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1211 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1212 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1213 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1214 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1215 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1216 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1217 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1218 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1219 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1220 dev->noisecalc.nr_samples++;
1221 if (dev->noisecalc.nr_samples == 8) {
1222 /* Calculate the Link Quality by the noise samples. */
1223 average = 0;
1224 for (i = 0; i < 8; i++) {
1225 for (j = 0; j < 4; j++)
1226 average += dev->noisecalc.samples[i][j];
1227 }
1228 average /= (8 * 4);
1229 average *= 125;
1230 average += 64;
1231 average /= 128;
1232 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1233 tmp = (tmp / 128) & 0x1F;
1234 if (tmp >= 8)
1235 average += 2;
1236 else
1237 average -= 25;
1238 if (tmp == 8)
1239 average -= 72;
1240 else
1241 average -= 48;
1242
1243 dev->stats.link_noise = average;
e4d6b795
MB		 1244 dev->noisecalc.calculation_running = 0;
1245 return;
1246 }
98a3b2fe 1247generate_new:
e4d6b795
MB		 1248 b43_generate_noise_sample(dev);
1249}
1250
1251static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1252{
05c914fe 1253 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1254 ///TODO: PS TBTT
1255 } else {
1256 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1257 b43_power_saving_ctl_bits(dev, 0);
1258 }
05c914fe 1259 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1260 dev->dfq_valid = 1;
e4d6b795
MB		 1261}
1262
1263static void handle_irq_atim_end(struct b43_wldev *dev)
1264{
aa6c7ae2
MB		 1265 if (dev->dfq_valid) {
1266 b43_write32(dev, B43_MMIO_MACCMD,
1267 b43_read32(dev, B43_MMIO_MACCMD)
1268 | B43_MACCMD_DFQ_VALID);
1269 dev->dfq_valid = 0;
1270 }
e4d6b795
MB		 1271}
1272
1273static void handle_irq_pmq(struct b43_wldev *dev)
1274{
1275 u32 tmp;
1276
1277 //TODO: AP mode.
1278
1279 while (1) {
1280 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1281 if (!(tmp & 0x00000008))
1282 break;
1283 }
1284 /* 16bit write is odd, but correct. */
1285 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1286}
1287
1288static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1289 const u8 *data, u16 size,
e4d6b795
MB		 1290 u16 ram_offset,
1291 u16 shm_size_offset, u8 rate)
1292{
1293 u32 i, tmp;
1294 struct b43_plcp_hdr4 plcp;
1295
1296 plcp.data = 0;
1297 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1298 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1299 ram_offset += sizeof(u32);
1300 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1301 * So leave the first two bytes of the next write blank.
1302 */
1303 tmp = (u32) (data[0]) << 16;
1304 tmp |= (u32) (data[1]) << 24;
1305 b43_ram_write(dev, ram_offset, tmp);
1306 ram_offset += sizeof(u32);
1307 for (i = 2; i < size; i += sizeof(u32)) {
1308 tmp = (u32) (data[i + 0]);
1309 if (i + 1 < size)
1310 tmp |= (u32) (data[i + 1]) << 8;
1311 if (i + 2 < size)
1312 tmp |= (u32) (data[i + 2]) << 16;
1313 if (i + 3 < size)
1314 tmp |= (u32) (data[i + 3]) << 24;
1315 b43_ram_write(dev, ram_offset + i - 2, tmp);
1316 }
1317 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1318 size + sizeof(struct b43_plcp_hdr6));
1319}
1320
5042c507
MB		 1321/* Check if the use of the antenna that ieee80211 told us to
1322 * use is possible. This will fall back to DEFAULT.
1323 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1324u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1325 u8 antenna_nr)
1326{
1327 u8 antenna_mask;
1328
1329 if (antenna_nr == 0) {
1330 /* Zero means "use default antenna". That's always OK. */
1331 return 0;
1332 }
1333
1334 /* Get the mask of available antennas. */
1335 if (dev->phy.gmode)
1336 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1337 else
1338 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1339
1340 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1341 /* This antenna is not available. Fall back to default. */
1342 return 0;
1343 }
1344
1345 return antenna_nr;
1346}
1347
5042c507
MB		 1348/* Convert a b43 antenna number value to the PHY TX control value. */
1349static u16 b43_antenna_to_phyctl(int antenna)
1350{
1351 switch (antenna) {
1352 case B43_ANTENNA0:
1353 return B43_TXH_PHY_ANT0;
1354 case B43_ANTENNA1:
1355 return B43_TXH_PHY_ANT1;
1356 case B43_ANTENNA2:
1357 return B43_TXH_PHY_ANT2;
1358 case B43_ANTENNA3:
1359 return B43_TXH_PHY_ANT3;
1360 case B43_ANTENNA_AUTO:
1361 return B43_TXH_PHY_ANT01AUTO;
1362 }
1363 B43_WARN_ON(1);
1364 return 0;
1365}
1366
e4d6b795
MB		 1367static void b43_write_beacon_template(struct b43_wldev *dev,
1368 u16 ram_offset,
5042c507 1369 u16 shm_size_offset)
e4d6b795 1370{
47f76ca3 1371 unsigned int i, len, variable_len;
e66fee6a
MB		 1372 const struct ieee80211_mgmt *bcn;
1373 const u8 *ie;
1374 bool tim_found = 0;
5042c507
MB		 1375 unsigned int rate;
1376 u16 ctl;
1377 int antenna;
e039fa4a 1378 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1379
e66fee6a
MB		 1380 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1381 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1382 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1383 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1384
1385 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1386 len, ram_offset, shm_size_offset, rate);
e66fee6a 1387
5042c507 1388 /* Write the PHY TX control parameters. */
0f4ac38b 1389 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1390 antenna = b43_antenna_to_phyctl(antenna);
1391 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1392 /* We can't send beacons with short preamble. Would get PHY errors. */
1393 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1394 ctl &= ~B43_TXH_PHY_ANT;
1395 ctl &= ~B43_TXH_PHY_ENC;
1396 ctl |= antenna;
1397 if (b43_is_cck_rate(rate))
1398 ctl |= B43_TXH_PHY_ENC_CCK;
1399 else
1400 ctl |= B43_TXH_PHY_ENC_OFDM;
1401 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1402
e66fee6a
MB		 1403 /* Find the position of the TIM and the DTIM_period value
1404 * and write them to SHM. */
1405 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1406 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1407 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1408 uint8_t ie_id, ie_len;
1409
1410 ie_id = ie[i];
1411 ie_len = ie[i + 1];
1412 if (ie_id == 5) {
1413 u16 tim_position;
1414 u16 dtim_period;
1415 /* This is the TIM Information Element */
1416
1417 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1418 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1419 break;
1420 /* A valid TIM is at least 4 bytes long. */
1421 if (ie_len < 4)
1422 break;
1423 tim_found = 1;
1424
1425 tim_position = sizeof(struct b43_plcp_hdr6);
1426 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1427 tim_position += i;
1428
1429 dtim_period = ie[i + 3];
1430
1431 b43_shm_write16(dev, B43_SHM_SHARED,
1432 B43_SHM_SH_TIMBPOS, tim_position);
1433 b43_shm_write16(dev, B43_SHM_SHARED,
1434 B43_SHM_SH_DTIMPER, dtim_period);
1435 break;
1436 }
1437 i += ie_len + 2;
1438 }
1439 if (!tim_found) {
04dea136
JB		 1440 /*
1441 * If ucode wants to modify TIM do it behind the beacon, this
1442 * will happen, for example, when doing mesh networking.
1443 */
1444 b43_shm_write16(dev, B43_SHM_SHARED,
1445 B43_SHM_SH_TIMBPOS,
1446 len + sizeof(struct b43_plcp_hdr6));
1447 b43_shm_write16(dev, B43_SHM_SHARED,
1448 B43_SHM_SH_DTIMPER, 0);
1449 }
1450 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1451}
1452
1453static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1454 u16 shm_offset, u16 size,
1455 struct ieee80211_rate *rate)
e4d6b795
MB		 1456{
1457 struct b43_plcp_hdr4 plcp;
1458 u32 tmp;
1459 __le16 dur;
1460
1461 plcp.data = 0;
8318d78a 1462 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1463 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1464 dev->wl->vif, size,
8318d78a 1465 rate);
e4d6b795
MB		 1466 /* Write PLCP in two parts and timing for packet transfer */
1467 tmp = le32_to_cpu(plcp.data);
1468 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1469 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1470 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1471}
1472
1473/* Instead of using custom probe response template, this function
1474 * just patches custom beacon template by:
1475 * 1) Changing packet type
1476 * 2) Patching duration field
1477 * 3) Stripping TIM
1478 */
99da185a
JD		 1479static const u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1480 u16 *dest_size,
1481 struct ieee80211_rate *rate)
e4d6b795
MB		 1482{
1483 const u8 *src_data;
1484 u8 *dest_data;
1485 u16 src_size, elem_size, src_pos, dest_pos;
1486 __le16 dur;
1487 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1488 size_t ie_start;
1489
1490 src_size = dev->wl->current_beacon->len;
1491 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1492
e66fee6a
MB		 1493 /* Get the start offset of the variable IEs in the packet. */
1494 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1495 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1496
e66fee6a 1497 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1498 return NULL;
e4d6b795
MB		 1499
1500 dest_data = kmalloc(src_size, GFP_ATOMIC);
1501 if (unlikely(!dest_data))
1502 return NULL;
1503
e66fee6a
MB		 1504 /* Copy the static data and all Information Elements, except the TIM. */
1505 memcpy(dest_data, src_data, ie_start);
1506 src_pos = ie_start;
1507 dest_pos = ie_start;
1508 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1509 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1510 if (src_data[src_pos] == 5) {
1511 /* This is the TIM. */
1512 continue;
e4d6b795 1513 }
e66fee6a
MB		 1514 memcpy(dest_data + dest_pos, src_data + src_pos,
1515 elem_size);
1516 dest_pos += elem_size;
e4d6b795
MB		 1517 }
1518 *dest_size = dest_pos;
1519 hdr = (struct ieee80211_hdr *)dest_data;
1520
1521 /* Set the frame control. */
1522 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1523 IEEE80211_STYPE_PROBE_RESP);
1524 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1525 dev->wl->vif, *dest_size,
8318d78a 1526 rate);
e4d6b795
MB		 1527 hdr->duration_id = dur;
1528
1529 return dest_data;
1530}
1531
1532static void b43_write_probe_resp_template(struct b43_wldev *dev,
1533 u16 ram_offset,
8318d78a
JB		 1534 u16 shm_size_offset,
1535 struct ieee80211_rate *rate)
e4d6b795 1536{
e66fee6a 1537 const u8 *probe_resp_data;
e4d6b795
MB		 1538 u16 size;
1539
e66fee6a 1540 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1541 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1542 if (unlikely(!probe_resp_data))
1543 return;
1544
1545 /* Looks like PLCP headers plus packet timings are stored for
1546 * all possible basic rates
1547 */
8318d78a
JB		 1548 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1549 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1550 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1551 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1552
1553 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1554 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1555 size, ram_offset, shm_size_offset,
1556 rate->hw_value);
e4d6b795
MB		 1557 kfree(probe_resp_data);
1558}
1559
6b4bec01
MB		 1560static void b43_upload_beacon0(struct b43_wldev *dev)
1561{
1562 struct b43_wl *wl = dev->wl;
1563
1564 if (wl->beacon0_uploaded)
1565 return;
1566 b43_write_beacon_template(dev, 0x68, 0x18);
1567 /* FIXME: Probe resp upload doesn't really belong here,
1568 * but we don't use that feature anyway. */
1569 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1570 &__b43_ratetable[3]);
1571 wl->beacon0_uploaded = 1;
1572}
1573
1574static void b43_upload_beacon1(struct b43_wldev *dev)
1575{
1576 struct b43_wl *wl = dev->wl;
1577
1578 if (wl->beacon1_uploaded)
1579 return;
1580 b43_write_beacon_template(dev, 0x468, 0x1A);
1581 wl->beacon1_uploaded = 1;
1582}
1583
c97a4ccc
MB		 1584static void handle_irq_beacon(struct b43_wldev *dev)
1585{
1586 struct b43_wl *wl = dev->wl;
1587 u32 cmd, beacon0_valid, beacon1_valid;
1588
05c914fe
JB		 1589 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1590 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1591 return;
1592
1593 /* This is the bottom half of the asynchronous beacon update. */
1594
1595 /* Ignore interrupt in the future. */
1596 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1597
1598 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1599 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1600 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1601
1602 /* Schedule interrupt manually, if busy. */
1603 if (beacon0_valid && beacon1_valid) {
1604 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1605 dev->irq_savedstate |= B43_IRQ_BEACON;
1606 return;
1607 }
1608
6b4bec01
MB		 1609 if (unlikely(wl->beacon_templates_virgin)) {
1610 /* We never uploaded a beacon before.
1611 * Upload both templates now, but only mark one valid. */
1612 wl->beacon_templates_virgin = 0;
1613 b43_upload_beacon0(dev);
1614 b43_upload_beacon1(dev);
c97a4ccc
MB		 1615 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1616 cmd |= B43_MACCMD_BEACON0_VALID;
1617 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1618 } else {
1619 if (!beacon0_valid) {
1620 b43_upload_beacon0(dev);
1621 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1622 cmd |= B43_MACCMD_BEACON0_VALID;
1623 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1624 } else if (!beacon1_valid) {
1625 b43_upload_beacon1(dev);
1626 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1627 cmd |= B43_MACCMD_BEACON1_VALID;
1628 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1629 }
c97a4ccc
MB		 1630 }
1631}
1632
a82d9922
MB		 1633static void b43_beacon_update_trigger_work(struct work_struct *work)
1634{
1635 struct b43_wl *wl = container_of(work, struct b43_wl,
1636 beacon_update_trigger);
1637 struct b43_wldev *dev;
1638
1639 mutex_lock(&wl->mutex);
1640 dev = wl->current_dev;
1641 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1642 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1643 /* update beacon right away or defer to irq */
1644 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1645 handle_irq_beacon(dev);
1646 /* The handler might have updated the IRQ mask. */
1647 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1648 dev->irq_savedstate);
1649 mmiowb();
a82d9922
MB		 1650 spin_unlock_irq(&wl->irq_lock);
1651 }
1652 mutex_unlock(&wl->mutex);
1653}
1654
d4df6f1a
MB		 1655/* Asynchronously update the packet templates in template RAM.
1656 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1657static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1658{
9d139c81
JB		 1659 struct sk_buff *beacon;
1660
e66fee6a
MB		 1661 /* This is the top half of the ansynchronous beacon update.
1662 * The bottom half is the beacon IRQ.
1663 * Beacon update must be asynchronous to avoid sending an
1664 * invalid beacon. This can happen for example, if the firmware
1665 * transmits a beacon while we are updating it. */
e4d6b795 1666
9d139c81
JB		 1667 /* We could modify the existing beacon and set the aid bit in
1668 * the TIM field, but that would probably require resizing and
1669 * moving of data within the beacon template.
1670 * Simply request a new beacon and let mac80211 do the hard work. */
1671 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1672 if (unlikely(!beacon))
1673 return;
1674
e66fee6a
MB		 1675 if (wl->current_beacon)
1676 dev_kfree_skb_any(wl->current_beacon);
1677 wl->current_beacon = beacon;
1678 wl->beacon0_uploaded = 0;
1679 wl->beacon1_uploaded = 0;
a82d9922 1680 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1681}
1682
e4d6b795
MB		 1683static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1684{
1685 b43_time_lock(dev);
1686 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1687 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1688 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1689 } else {
1690 b43_write16(dev, 0x606, (beacon_int >> 6));
1691 b43_write16(dev, 0x610, beacon_int);
1692 }
1693 b43_time_unlock(dev);
a82d9922 1694 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1695}
1696
afa83e23
MB		 1697static void b43_handle_firmware_panic(struct b43_wldev *dev)
1698{
1699 u16 reason;
1700
1701 /* Read the register that contains the reason code for the panic. */
1702 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1703 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1704
1705 switch (reason) {
1706 default:
1707 b43dbg(dev->wl, "The panic reason is unknown.\n");
1708 /* fallthrough */
1709 case B43_FWPANIC_DIE:
1710 /* Do not restart the controller or firmware.
1711 * The device is nonfunctional from now on.
1712 * Restarting would result in this panic to trigger again,
1713 * so we avoid that recursion. */
1714 break;
1715 case B43_FWPANIC_RESTART:
1716 b43_controller_restart(dev, "Microcode panic");
1717 break;
1718 }
1719}
1720
e4d6b795
MB		 1721static void handle_irq_ucode_debug(struct b43_wldev *dev)
1722{
e48b0eeb 1723 unsigned int i, cnt;
53c06856 1724 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1725 __le16 *buf;
1726
1727 /* The proprietary firmware doesn't have this IRQ. */
1728 if (!dev->fw.opensource)
1729 return;
1730
afa83e23
MB		 1731 /* Read the register that contains the reason code for this IRQ. */
1732 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1733
e48b0eeb
MB		 1734 switch (reason) {
1735 case B43_DEBUGIRQ_PANIC:
afa83e23 1736 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1737 break;
1738 case B43_DEBUGIRQ_DUMP_SHM:
1739 if (!B43_DEBUG)
1740 break; /* Only with driver debugging enabled. */
1741 buf = kmalloc(4096, GFP_ATOMIC);
1742 if (!buf) {
1743 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1744 goto out;
1745 }
1746 for (i = 0; i < 4096; i += 2) {
1747 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1748 buf[i / 2] = cpu_to_le16(tmp);
1749 }
1750 b43info(dev->wl, "Shared memory dump:\n");
1751 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1752 16, 2, buf, 4096, 1);
1753 kfree(buf);
1754 break;
1755 case B43_DEBUGIRQ_DUMP_REGS:
1756 if (!B43_DEBUG)
1757 break; /* Only with driver debugging enabled. */
1758 b43info(dev->wl, "Microcode register dump:\n");
1759 for (i = 0, cnt = 0; i < 64; i++) {
1760 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1761 if (cnt == 0)
1762 printk(KERN_INFO);
1763 printk("r%02u: 0x%04X ", i, tmp);
1764 cnt++;
1765 if (cnt == 6) {
1766 printk("\n");
1767 cnt = 0;
1768 }
1769 }
1770 printk("\n");
1771 break;
53c06856
MB		 1772 case B43_DEBUGIRQ_MARKER:
1773 if (!B43_DEBUG)
1774 break; /* Only with driver debugging enabled. */
1775 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1776 B43_MARKER_ID_REG);
1777 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1778 B43_MARKER_LINE_REG);
1779 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1780 "at line number %u\n",
1781 marker_id, marker_line);
1782 break;
e48b0eeb
MB		 1783 default:
1784 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1785 reason);
1786 }
1787out:
afa83e23
MB		 1788 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1789 b43_shm_write16(dev, B43_SHM_SCRATCH,
1790 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1791}
1792
1793/* Interrupt handler bottom-half */
1794static void b43_interrupt_tasklet(struct b43_wldev *dev)
1795{
1796 u32 reason;
1797 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1798 u32 merged_dma_reason = 0;
21954c36 1799 int i;
e4d6b795
MB		 1800 unsigned long flags;
1801
1802 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1803
1804 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1805
1806 reason = dev->irq_reason;
1807 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1808 dma_reason[i] = dev->dma_reason[i];
1809 merged_dma_reason |= dma_reason[i];
1810 }
1811
1812 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1813 b43err(dev->wl, "MAC transmission error\n");
1814
00e0b8cb 1815 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1816 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1817 rmb();
1818 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1819 atomic_set(&dev->phy.txerr_cnt,
1820 B43_PHY_TX_BADNESS_LIMIT);
1821 b43err(dev->wl, "Too many PHY TX errors, "
1822 "restarting the controller\n");
1823 b43_controller_restart(dev, "PHY TX errors");
1824 }
1825 }
e4d6b795
MB		 1826
1827 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1828 B43_DMAIRQ_NONFATALMASK))) {
1829 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1830 b43err(dev->wl, "Fatal DMA error: "
1831 "0x%08X, 0x%08X, 0x%08X, "
1832 "0x%08X, 0x%08X, 0x%08X\n",
1833 dma_reason[0], dma_reason[1],
1834 dma_reason[2], dma_reason[3],
1835 dma_reason[4], dma_reason[5]);
1836 b43_controller_restart(dev, "DMA error");
1837 mmiowb();
1838 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1839 return;
1840 }
1841 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1842 b43err(dev->wl, "DMA error: "
1843 "0x%08X, 0x%08X, 0x%08X, "
1844 "0x%08X, 0x%08X, 0x%08X\n",
1845 dma_reason[0], dma_reason[1],
1846 dma_reason[2], dma_reason[3],
1847 dma_reason[4], dma_reason[5]);
1848 }
1849 }
1850
1851 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1852 handle_irq_ucode_debug(dev);
1853 if (reason & B43_IRQ_TBTT_INDI)
1854 handle_irq_tbtt_indication(dev);
1855 if (reason & B43_IRQ_ATIM_END)
1856 handle_irq_atim_end(dev);
1857 if (reason & B43_IRQ_BEACON)
1858 handle_irq_beacon(dev);
1859 if (reason & B43_IRQ_PMQ)
1860 handle_irq_pmq(dev);
21954c36
MB		 1861 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1862 ;/* TODO */
1863 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1864 handle_irq_noise(dev);
1865
1866 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1867 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1868 if (b43_using_pio_transfers(dev))
1869 b43_pio_rx(dev->pio.rx_queue);
1870 else
1871 b43_dma_rx(dev->dma.rx_ring);
1872 }
e4d6b795
MB		 1873 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1874 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1875 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1876 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1877 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1878
21954c36 1879 if (reason & B43_IRQ_TX_OK)
e4d6b795 1880 handle_irq_transmit_status(dev);
e4d6b795 1881
e4d6b795
MB		 1882 b43_interrupt_enable(dev, dev->irq_savedstate);
1883 mmiowb();
1884 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1885}
1886
e4d6b795
MB		 1887static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1888{
e4d6b795
MB		 1889 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1890
1891 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1892 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1893 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1894 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1895 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1896 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1897}
1898
1899/* Interrupt handler top-half */
1900static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1901{
1902 irqreturn_t ret = IRQ_NONE;
1903 struct b43_wldev *dev = dev_id;
1904 u32 reason;
1905
1906 if (!dev)
1907 return IRQ_NONE;
1908
1909 spin_lock(&dev->wl->irq_lock);
1910
1911 if (b43_status(dev) < B43_STAT_STARTED)
1912 goto out;
1913 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1914 if (reason == 0xffffffff) /* shared IRQ */
1915 goto out;
1916 ret = IRQ_HANDLED;
1917 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1918 if (!reason)
1919 goto out;
1920
1921 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1922 & 0x0001DC00;
1923 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1924 & 0x0000DC00;
1925 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1926 & 0x0000DC00;
1927 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1928 & 0x0001DC00;
1929 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1930 & 0x0000DC00;
1931 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1932 & 0x0000DC00;
1933
1934 b43_interrupt_ack(dev, reason);
1935 /* disable all IRQs. They are enabled again in the bottom half. */
1936 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1937 /* save the reason code and call our bottom half. */
1938 dev->irq_reason = reason;
1939 tasklet_schedule(&dev->isr_tasklet);
1940 out:
1941 mmiowb();
1942 spin_unlock(&dev->wl->irq_lock);
1943
1944 return ret;
1945}
1946
1a9f5093 1947void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1948{
1949 release_firmware(fw->data);
1950 fw->data = NULL;
1951 fw->filename = NULL;
1952}
1953
e4d6b795
MB		 1954static void b43_release_firmware(struct b43_wldev *dev)
1955{
1a9f5093
MB		 1956 b43_do_release_fw(&dev->fw.ucode);
1957 b43_do_release_fw(&dev->fw.pcm);
1958 b43_do_release_fw(&dev->fw.initvals);
1959 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1960}
1961
eb189d8b 1962static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1963{
fc68ed4f
HE		 1964 const char text[] =
1965 "You must go to " \
1966 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1967 "and download the correct firmware for this driver version. " \
1968 "Please carefully read all instructions on this website.\n";
eb189d8b 1969
eb189d8b
MB		 1970 if (error)
1971 b43err(wl, text);
1972 else
1973 b43warn(wl, text);
e4d6b795
MB		 1974}
1975
1a9f5093
MB		 1976int b43_do_request_fw(struct b43_request_fw_context *ctx,
1977 const char *name,
1978 struct b43_firmware_file *fw)
e4d6b795 1979{
61cb5dd6 1980 const struct firmware *blob;
e4d6b795
MB		 1981 struct b43_fw_header *hdr;
1982 u32 size;
1983 int err;
1984
61cb5dd6
MB		 1985 if (!name) {
1986 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1987 /* FIXME: We should probably keep it anyway, to save some headache
1988 * on suspend/resume with multiband devices. */
1989 b43_do_release_fw(fw);
e4d6b795 1990 return 0;
61cb5dd6
MB		 1991 }
1992 if (fw->filename) {
1a9f5093
MB		 1993 if ((fw->type == ctx->req_type) &&
1994 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1995 return 0; /* Already have this fw. */
1996 /* Free the cached firmware first. */
1a9f5093
MB		 1997 /* FIXME: We should probably do this later after we successfully
1998 * got the new fw. This could reduce headache with multiband devices.
1999 * We could also redesign this to cache the firmware for all possible
2000 * bands all the time. */
2001 b43_do_release_fw(fw);
61cb5dd6 2002 }
e4d6b795 2003
1a9f5093
MB		 2004 switch (ctx->req_type) {
2005 case B43_FWTYPE_PROPRIETARY:
2006 snprintf(ctx->fwname, sizeof(ctx->fwname),
2007 "b43%s/%s.fw",
2008 modparam_fwpostfix, name);
2009 break;
2010 case B43_FWTYPE_OPENSOURCE:
2011 snprintf(ctx->fwname, sizeof(ctx->fwname),
2012 "b43-open%s/%s.fw",
2013 modparam_fwpostfix, name);
2014 break;
2015 default:
2016 B43_WARN_ON(1);
2017 return -ENOSYS;
2018 }
2019 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2020 if (err == -ENOENT) {
1a9f5093
MB		 2021 snprintf(ctx->errors[ctx->req_type],
2022 sizeof(ctx->errors[ctx->req_type]),
2023 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2024 return err;
2025 } else if (err) {
1a9f5093
MB		 2026 snprintf(ctx->errors[ctx->req_type],
2027 sizeof(ctx->errors[ctx->req_type]),
2028 "Firmware file \"%s\" request failed (err=%d)\n",
2029 ctx->fwname, err);
e4d6b795
MB		 2030 return err;
2031 }
61cb5dd6 2032 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2033 goto err_format;
61cb5dd6 2034 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2035 switch (hdr->type) {
2036 case B43_FW_TYPE_UCODE:
2037 case B43_FW_TYPE_PCM:
2038 size = be32_to_cpu(hdr->size);
61cb5dd6 2039 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2040 goto err_format;
2041 /* fallthrough */
2042 case B43_FW_TYPE_IV:
2043 if (hdr->ver != 1)
2044 goto err_format;
2045 break;
2046 default:
2047 goto err_format;
2048 }
2049
61cb5dd6
MB		 2050 fw->data = blob;
2051 fw->filename = name;
1a9f5093 2052 fw->type = ctx->req_type;
61cb5dd6
MB		 2053
2054 return 0;
e4d6b795
MB		 2055
2056err_format:
1a9f5093
MB		 2057 snprintf(ctx->errors[ctx->req_type],
2058 sizeof(ctx->errors[ctx->req_type]),
2059 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2060 release_firmware(blob);
2061
e4d6b795
MB		 2062 return -EPROTO;
2063}
2064
1a9f5093 2065static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2066{
1a9f5093
MB		 2067 struct b43_wldev *dev = ctx->dev;
2068 struct b43_firmware *fw = &ctx->dev->fw;
2069 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2070 const char *filename;
2071 u32 tmshigh;
2072 int err;
2073
61cb5dd6 2074 /* Get microcode */
e4d6b795 2075 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2076 if ((rev >= 5) && (rev <= 10))
2077 filename = "ucode5";
2078 else if ((rev >= 11) && (rev <= 12))
2079 filename = "ucode11";
2080 else if (rev >= 13)
2081 filename = "ucode13";
2082 else
2083 goto err_no_ucode;
1a9f5093 2084 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2085 if (err)
2086 goto err_load;
2087
2088 /* Get PCM code */
2089 if ((rev >= 5) && (rev <= 10))
2090 filename = "pcm5";
2091 else if (rev >= 11)
2092 filename = NULL;
2093 else
2094 goto err_no_pcm;
68217832 2095 fw->pcm_request_failed = 0;
1a9f5093 2096 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2097 if (err == -ENOENT) {
2098 /* We did not find a PCM file? Not fatal, but
2099 * core rev <= 10 must do without hwcrypto then. */
2100 fw->pcm_request_failed = 1;
2101 } else if (err)
61cb5dd6
MB		 2102 goto err_load;
2103
2104 /* Get initvals */
2105 switch (dev->phy.type) {
2106 case B43_PHYTYPE_A:
2107 if ((rev >= 5) && (rev <= 10)) {
2108 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2109 filename = "a0g1initvals5";
2110 else
2111 filename = "a0g0initvals5";
2112 } else
2113 goto err_no_initvals;
2114 break;
2115 case B43_PHYTYPE_G:
e4d6b795 2116 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2117 filename = "b0g0initvals5";
e4d6b795 2118 else if (rev >= 13)
e9304882 2119 filename = "b0g0initvals13";
e4d6b795 2120 else
61cb5dd6
MB		 2121 goto err_no_initvals;
2122 break;
2123 case B43_PHYTYPE_N:
2124 if ((rev >= 11) && (rev <= 12))
2125 filename = "n0initvals11";
2126 else
2127 goto err_no_initvals;
2128 break;
2129 default:
2130 goto err_no_initvals;
e4d6b795 2131 }
1a9f5093 2132 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2133 if (err)
2134 goto err_load;
2135
2136 /* Get bandswitch initvals */
2137 switch (dev->phy.type) {
2138 case B43_PHYTYPE_A:
2139 if ((rev >= 5) && (rev <= 10)) {
2140 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2141 filename = "a0g1bsinitvals5";
2142 else
2143 filename = "a0g0bsinitvals5";
2144 } else if (rev >= 11)
2145 filename = NULL;
2146 else
2147 goto err_no_initvals;
2148 break;
2149 case B43_PHYTYPE_G:
e4d6b795 2150 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2151 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2152 else if (rev >= 11)
2153 filename = NULL;
2154 else
e4d6b795 2155 goto err_no_initvals;
61cb5dd6
MB		 2156 break;
2157 case B43_PHYTYPE_N:
2158 if ((rev >= 11) && (rev <= 12))
2159 filename = "n0bsinitvals11";
2160 else
e4d6b795 2161 goto err_no_initvals;
61cb5dd6
MB		 2162 break;
2163 default:
2164 goto err_no_initvals;
e4d6b795 2165 }
1a9f5093 2166 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2167 if (err)
2168 goto err_load;
e4d6b795
MB		 2169
2170 return 0;
2171
e4d6b795 2172err_no_ucode:
1a9f5093
MB		 2173 err = ctx->fatal_failure = -EOPNOTSUPP;
2174 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2175 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2176 goto error;
2177
2178err_no_pcm:
1a9f5093
MB		 2179 err = ctx->fatal_failure = -EOPNOTSUPP;
2180 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2181 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2182 goto error;
2183
2184err_no_initvals:
1a9f5093
MB		 2185 err = ctx->fatal_failure = -EOPNOTSUPP;
2186 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2187 "is required for your device (wl-core rev %u)\n", rev);
2188 goto error;
2189
2190err_load:
2191 /* We failed to load this firmware image. The error message
2192 * already is in ctx->errors. Return and let our caller decide
2193 * what to do. */
e4d6b795
MB		 2194 goto error;
2195
2196error:
2197 b43_release_firmware(dev);
2198 return err;
2199}
2200
1a9f5093
MB		 2201static int b43_request_firmware(struct b43_wldev *dev)
2202{
2203 struct b43_request_fw_context *ctx;
2204 unsigned int i;
2205 int err;
2206 const char *errmsg;
2207
2208 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2209 if (!ctx)
2210 return -ENOMEM;
2211 ctx->dev = dev;
2212
2213 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2214 err = b43_try_request_fw(ctx);
2215 if (!err)
2216 goto out; /* Successfully loaded it. */
2217 err = ctx->fatal_failure;
2218 if (err)
2219 goto out;
2220
2221 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2222 err = b43_try_request_fw(ctx);
2223 if (!err)
2224 goto out; /* Successfully loaded it. */
2225 err = ctx->fatal_failure;
2226 if (err)
2227 goto out;
2228
2229 /* Could not find a usable firmware. Print the errors. */
2230 for (i = 0; i < B43_NR_FWTYPES; i++) {
2231 errmsg = ctx->errors[i];
2232 if (strlen(errmsg))
2233 b43err(dev->wl, errmsg);
2234 }
2235 b43_print_fw_helptext(dev->wl, 1);
2236 err = -ENOENT;
2237
2238out:
2239 kfree(ctx);
2240 return err;
2241}
2242
e4d6b795
MB		 2243static int b43_upload_microcode(struct b43_wldev *dev)
2244{
2245 const size_t hdr_len = sizeof(struct b43_fw_header);
2246 const __be32 *data;
2247 unsigned int i, len;
2248 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2249 u32 tmp, macctl;
e4d6b795
MB		 2250 int err = 0;
2251
1f7d87b0
MB		 2252 /* Jump the microcode PSM to offset 0 */
2253 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2254 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2255 macctl |= B43_MACCTL_PSM_JMP0;
2256 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2257 /* Zero out all microcode PSM registers and shared memory. */
2258 for (i = 0; i < 64; i++)
2259 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2260 for (i = 0; i < 4096; i += 2)
2261 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2262
e4d6b795 2263 /* Upload Microcode. */
61cb5dd6
MB		 2264 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2265 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2266 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2267 for (i = 0; i < len; i++) {
2268 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2269 udelay(10);
2270 }
2271
61cb5dd6 2272 if (dev->fw.pcm.data) {
e4d6b795 2273 /* Upload PCM data. */
61cb5dd6
MB		 2274 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2275 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2276 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2277 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2278 /* No need for autoinc bit in SHM_HW */
2279 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2280 for (i = 0; i < len; i++) {
2281 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2282 udelay(10);
2283 }
2284 }
2285
2286 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2287
2288 /* Start the microcode PSM */
2289 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2290 macctl &= ~B43_MACCTL_PSM_JMP0;
2291 macctl |= B43_MACCTL_PSM_RUN;
2292 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2293
2294 /* Wait for the microcode to load and respond */
2295 i = 0;
2296 while (1) {
2297 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2298 if (tmp == B43_IRQ_MAC_SUSPENDED)
2299 break;
2300 i++;
1f7d87b0 2301 if (i >= 20) {
e4d6b795 2302 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2303 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2304 err = -ENODEV;
1f7d87b0
MB		 2305 goto error;
2306 }
2307 msleep_interruptible(50);
2308 if (signal_pending(current)) {
2309 err = -EINTR;
2310 goto error;
e4d6b795 2311 }
e4d6b795
MB		 2312 }
2313 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2314
2315 /* Get and check the revisions. */
2316 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2317 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2318 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2319 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2320
2321 if (fwrev <= 0x128) {
2322 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2323 "binary drivers older than version 4.x is unsupported. "
2324 "You must upgrade your firmware files.\n");
eb189d8b 2325 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2326 err = -EOPNOTSUPP;
1f7d87b0 2327 goto error;
e4d6b795 2328 }
e4d6b795
MB		 2329 dev->fw.rev = fwrev;
2330 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2331 dev->fw.opensource = (fwdate == 0xFFFF);
2332
2333 if (dev->fw.opensource) {
2334 /* Patchlevel info is encoded in the "time" field. */
2335 dev->fw.patch = fwtime;
68217832
MB		 2336 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2337 dev->fw.rev, dev->fw.patch,
2338 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
e48b0eeb
MB		 2339 } else {
2340 b43info(dev->wl, "Loading firmware version %u.%u "
2341 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2342 fwrev, fwpatch,
2343 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2344 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2345 if (dev->fw.pcm_request_failed) {
2346 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2347 "Hardware accelerated cryptography is disabled.\n");
2348 b43_print_fw_helptext(dev->wl, 0);
2349 }
e48b0eeb 2350 }
e4d6b795 2351
eb189d8b 2352 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2353 /* We're over the deadline, but we keep support for old fw
2354 * until it turns out to be in major conflict with something new. */
eb189d8b 2355 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2356 "Support for old firmware will be removed soon "
2357 "(official deadline was July 2008).\n");
eb189d8b
MB		 2358 b43_print_fw_helptext(dev->wl, 0);
2359 }
2360
1f7d87b0
MB		 2361 return 0;
2362
2363error:
2364 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2365 macctl &= ~B43_MACCTL_PSM_RUN;
2366 macctl |= B43_MACCTL_PSM_JMP0;
2367 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2368
e4d6b795
MB		 2369 return err;
2370}
2371
2372static int b43_write_initvals(struct b43_wldev *dev,
2373 const struct b43_iv *ivals,
2374 size_t count,
2375 size_t array_size)
2376{
2377 const struct b43_iv *iv;
2378 u16 offset;
2379 size_t i;
2380 bool bit32;
2381
2382 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2383 iv = ivals;
2384 for (i = 0; i < count; i++) {
2385 if (array_size < sizeof(iv->offset_size))
2386 goto err_format;
2387 array_size -= sizeof(iv->offset_size);
2388 offset = be16_to_cpu(iv->offset_size);
2389 bit32 = !!(offset & B43_IV_32BIT);
2390 offset &= B43_IV_OFFSET_MASK;
2391 if (offset >= 0x1000)
2392 goto err_format;
2393 if (bit32) {
2394 u32 value;
2395
2396 if (array_size < sizeof(iv->data.d32))
2397 goto err_format;
2398 array_size -= sizeof(iv->data.d32);
2399
533dd1b0 2400 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2401 b43_write32(dev, offset, value);
2402
2403 iv = (const struct b43_iv *)((const uint8_t *)iv +
2404 sizeof(__be16) +
2405 sizeof(__be32));
2406 } else {
2407 u16 value;
2408
2409 if (array_size < sizeof(iv->data.d16))
2410 goto err_format;
2411 array_size -= sizeof(iv->data.d16);
2412
2413 value = be16_to_cpu(iv->data.d16);
2414 b43_write16(dev, offset, value);
2415
2416 iv = (const struct b43_iv *)((const uint8_t *)iv +
2417 sizeof(__be16) +
2418 sizeof(__be16));
2419 }
2420 }
2421 if (array_size)
2422 goto err_format;
2423
2424 return 0;
2425
2426err_format:
2427 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2428 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2429
2430 return -EPROTO;
2431}
2432
2433static int b43_upload_initvals(struct b43_wldev *dev)
2434{
2435 const size_t hdr_len = sizeof(struct b43_fw_header);
2436 const struct b43_fw_header *hdr;
2437 struct b43_firmware *fw = &dev->fw;
2438 const struct b43_iv *ivals;
2439 size_t count;
2440 int err;
2441
61cb5dd6
MB		 2442 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2443 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2444 count = be32_to_cpu(hdr->size);
2445 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2446 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2447 if (err)
2448 goto out;
61cb5dd6
MB		 2449 if (fw->initvals_band.data) {
2450 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2451 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2452 count = be32_to_cpu(hdr->size);
2453 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2454 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2455 if (err)
2456 goto out;
2457 }
2458out:
2459
2460 return err;
2461}
2462
2463/* Initialize the GPIOs
2464 * http://bcm-specs.sipsolutions.net/GPIO
2465 */
2466static int b43_gpio_init(struct b43_wldev *dev)
2467{
2468 struct ssb_bus *bus = dev->dev->bus;
2469 struct ssb_device *gpiodev, *pcidev = NULL;
2470 u32 mask, set;
2471
2472 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2473 & ~B43_MACCTL_GPOUTSMSK);
2474
e4d6b795
MB		 2475 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2476 | 0x000F);
2477
2478 mask = 0x0000001F;
2479 set = 0x0000000F;
2480 if (dev->dev->bus->chip_id == 0x4301) {
2481 mask |= 0x0060;
2482 set |= 0x0060;
2483 }
2484 if (0 /* FIXME: conditional unknown */ ) {
2485 b43_write16(dev, B43_MMIO_GPIO_MASK,
2486 b43_read16(dev, B43_MMIO_GPIO_MASK)
2487 | 0x0100);
2488 mask |= 0x0180;
2489 set |= 0x0180;
2490 }
95de2841 2491 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2492 b43_write16(dev, B43_MMIO_GPIO_MASK,
2493 b43_read16(dev, B43_MMIO_GPIO_MASK)
2494 | 0x0200);
2495 mask |= 0x0200;
2496 set |= 0x0200;
2497 }
2498 if (dev->dev->id.revision >= 2)
2499 mask |= 0x0010; /* FIXME: This is redundant. */
2500
2501#ifdef CONFIG_SSB_DRIVER_PCICORE
2502 pcidev = bus->pcicore.dev;
2503#endif
2504 gpiodev = bus->chipco.dev ? : pcidev;
2505 if (!gpiodev)
2506 return 0;
2507 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2508 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2509 & mask) | set);
2510
2511 return 0;
2512}
2513
2514/* Turn off all GPIO stuff. Call this on module unload, for example. */
2515static void b43_gpio_cleanup(struct b43_wldev *dev)
2516{
2517 struct ssb_bus *bus = dev->dev->bus;
2518 struct ssb_device *gpiodev, *pcidev = NULL;
2519
2520#ifdef CONFIG_SSB_DRIVER_PCICORE
2521 pcidev = bus->pcicore.dev;
2522#endif
2523 gpiodev = bus->chipco.dev ? : pcidev;
2524 if (!gpiodev)
2525 return;
2526 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2527}
2528
2529/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2530void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2531{
923fd703
MB		 2532 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2533 u16 fwstate;
2534
2535 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2536 B43_SHM_SH_UCODESTAT);
2537 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2538 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2539 b43err(dev->wl, "b43_mac_enable(): The firmware "
2540 "should be suspended, but current state is %u\n",
2541 fwstate);
2542 }
2543 }
2544
e4d6b795
MB		 2545 dev->mac_suspended--;
2546 B43_WARN_ON(dev->mac_suspended < 0);
2547 if (dev->mac_suspended == 0) {
2548 b43_write32(dev, B43_MMIO_MACCTL,
2549 b43_read32(dev, B43_MMIO_MACCTL)
2550 | B43_MACCTL_ENABLED);
2551 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2552 B43_IRQ_MAC_SUSPENDED);
2553 /* Commit writes */
2554 b43_read32(dev, B43_MMIO_MACCTL);
2555 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2556 b43_power_saving_ctl_bits(dev, 0);
2557 }
2558}
2559
2560/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2561void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2562{
2563 int i;
2564 u32 tmp;
2565
05b64b36 2566 might_sleep();
e4d6b795 2567 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2568
e4d6b795
MB		 2569 if (dev->mac_suspended == 0) {
2570 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2571 b43_write32(dev, B43_MMIO_MACCTL,
2572 b43_read32(dev, B43_MMIO_MACCTL)
2573 & ~B43_MACCTL_ENABLED);
2574 /* force pci to flush the write */
2575 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2576 for (i = 35; i; i--) {
2577 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2578 if (tmp & B43_IRQ_MAC_SUSPENDED)
2579 goto out;
2580 udelay(10);
2581 }
2582 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2583 for (i = 40; i; i--) {
e4d6b795
MB		 2584 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2585 if (tmp & B43_IRQ_MAC_SUSPENDED)
2586 goto out;
05b64b36 2587 msleep(1);
e4d6b795
MB		 2588 }
2589 b43err(dev->wl, "MAC suspend failed\n");
2590 }
05b64b36 2591out:
e4d6b795
MB		 2592 dev->mac_suspended++;
2593}
2594
2595static void b43_adjust_opmode(struct b43_wldev *dev)
2596{
2597 struct b43_wl *wl = dev->wl;
2598 u32 ctl;
2599 u16 cfp_pretbtt;
2600
2601 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2602 /* Reset status to STA infrastructure mode. */
2603 ctl &= ~B43_MACCTL_AP;
2604 ctl &= ~B43_MACCTL_KEEP_CTL;
2605 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2606 ctl &= ~B43_MACCTL_KEEP_BAD;
2607 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2608 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2609 ctl |= B43_MACCTL_INFRA;
2610
05c914fe
JB		 2611 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2612 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2613 ctl |= B43_MACCTL_AP;
05c914fe 2614 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2615 ctl &= ~B43_MACCTL_INFRA;
2616
2617 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2618 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2619 if (wl->filter_flags & FIF_FCSFAIL)
2620 ctl |= B43_MACCTL_KEEP_BAD;
2621 if (wl->filter_flags & FIF_PLCPFAIL)
2622 ctl |= B43_MACCTL_KEEP_BADPLCP;
2623 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2624 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2625 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2626 ctl |= B43_MACCTL_BEACPROMISC;
2627
e4d6b795
MB		 2628 /* Workaround: On old hardware the HW-MAC-address-filter
2629 * doesn't work properly, so always run promisc in filter
2630 * it in software. */
2631 if (dev->dev->id.revision <= 4)
2632 ctl |= B43_MACCTL_PROMISC;
2633
2634 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2635
2636 cfp_pretbtt = 2;
2637 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2638 if (dev->dev->bus->chip_id == 0x4306 &&
2639 dev->dev->bus->chip_rev == 3)
2640 cfp_pretbtt = 100;
2641 else
2642 cfp_pretbtt = 50;
2643 }
2644 b43_write16(dev, 0x612, cfp_pretbtt);
2645}
2646
2647static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2648{
2649 u16 offset;
2650
2651 if (is_ofdm) {
2652 offset = 0x480;
2653 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2654 } else {
2655 offset = 0x4C0;
2656 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2657 }
2658 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2659 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2660}
2661
2662static void b43_rate_memory_init(struct b43_wldev *dev)
2663{
2664 switch (dev->phy.type) {
2665 case B43_PHYTYPE_A:
2666 case B43_PHYTYPE_G:
53a6e234 2667 case B43_PHYTYPE_N:
e4d6b795
MB		 2668 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2669 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2670 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2671 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2672 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2673 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2674 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2675 if (dev->phy.type == B43_PHYTYPE_A)
2676 break;
2677 /* fallthrough */
2678 case B43_PHYTYPE_B:
2679 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2680 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2681 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2682 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2683 break;
2684 default:
2685 B43_WARN_ON(1);
2686 }
2687}
2688
5042c507
MB		 2689/* Set the default values for the PHY TX Control Words. */
2690static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2691{
2692 u16 ctl = 0;
2693
2694 ctl |= B43_TXH_PHY_ENC_CCK;
2695 ctl |= B43_TXH_PHY_ANT01AUTO;
2696 ctl |= B43_TXH_PHY_TXPWR;
2697
2698 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2699 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2700 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2701}
2702
e4d6b795
MB		 2703/* Set the TX-Antenna for management frames sent by firmware. */
2704static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2705{
5042c507 2706 u16 ant;
e4d6b795
MB		 2707 u16 tmp;
2708
5042c507 2709 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2710
e4d6b795
MB		 2711 /* For ACK/CTS */
2712 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2713 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2714 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2715 /* For Probe Resposes */
2716 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2717 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2718 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2719}
2720
2721/* This is the opposite of b43_chip_init() */
2722static void b43_chip_exit(struct b43_wldev *dev)
2723{
fb11137a 2724 b43_phy_exit(dev);
e4d6b795
MB		 2725 b43_gpio_cleanup(dev);
2726 /* firmware is released later */
2727}
2728
2729/* Initialize the chip
2730 * http://bcm-specs.sipsolutions.net/ChipInit
2731 */
2732static int b43_chip_init(struct b43_wldev *dev)
2733{
2734 struct b43_phy *phy = &dev->phy;
ef1a628d 2735 int err;
1f7d87b0 2736 u32 value32, macctl;
e4d6b795
MB		 2737 u16 value16;
2738
1f7d87b0
MB		 2739 /* Initialize the MAC control */
2740 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2741 if (dev->phy.gmode)
2742 macctl |= B43_MACCTL_GMODE;
2743 macctl |= B43_MACCTL_INFRA;
2744 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2745
2746 err = b43_request_firmware(dev);
2747 if (err)
2748 goto out;
2749 err = b43_upload_microcode(dev);
2750 if (err)
2751 goto out; /* firmware is released later */
2752
2753 err = b43_gpio_init(dev);
2754 if (err)
2755 goto out; /* firmware is released later */
21954c36 2756
e4d6b795
MB		 2757 err = b43_upload_initvals(dev);
2758 if (err)
1a8d1227 2759 goto err_gpio_clean;
e4d6b795 2760
0b7dcd96
MB		 2761 /* Turn the Analog on and initialize the PHY. */
2762 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2763 err = b43_phy_init(dev);
2764 if (err)
ef1a628d 2765 goto err_gpio_clean;
e4d6b795 2766
ef1a628d
MB		 2767 /* Disable Interference Mitigation. */
2768 if (phy->ops->interf_mitigation)
2769 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2770
ef1a628d
MB		 2771 /* Select the antennae */
2772 if (phy->ops->set_rx_antenna)
2773 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2774 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2775
2776 if (phy->type == B43_PHYTYPE_B) {
2777 value16 = b43_read16(dev, 0x005E);
2778 value16 |= 0x0004;
2779 b43_write16(dev, 0x005E, value16);
2780 }
2781 b43_write32(dev, 0x0100, 0x01000000);
2782 if (dev->dev->id.revision < 5)
2783 b43_write32(dev, 0x010C, 0x01000000);
2784
2785 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2786 & ~B43_MACCTL_INFRA);
2787 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2788 | B43_MACCTL_INFRA);
e4d6b795 2789
e4d6b795
MB		 2790 /* Probe Response Timeout value */
2791 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2792 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2793
2794 /* Initially set the wireless operation mode. */
2795 b43_adjust_opmode(dev);
2796
2797 if (dev->dev->id.revision < 3) {
2798 b43_write16(dev, 0x060E, 0x0000);
2799 b43_write16(dev, 0x0610, 0x8000);
2800 b43_write16(dev, 0x0604, 0x0000);
2801 b43_write16(dev, 0x0606, 0x0200);
2802 } else {
2803 b43_write32(dev, 0x0188, 0x80000000);
2804 b43_write32(dev, 0x018C, 0x02000000);
2805 }
2806 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2807 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2808 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2809 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2810 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2811 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2812 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2813
2814 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2815 value32 |= 0x00100000;
2816 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2817
2818 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2819 dev->dev->bus->chipco.fast_pwrup_delay);
2820
2821 err = 0;
2822 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2823out:
e4d6b795
MB		 2824 return err;
2825
1a8d1227 2826err_gpio_clean:
e4d6b795 2827 b43_gpio_cleanup(dev);
21954c36 2828 return err;
e4d6b795
MB		 2829}
2830
e4d6b795
MB		 2831static void b43_periodic_every60sec(struct b43_wldev *dev)
2832{
ef1a628d 2833 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2834
ef1a628d
MB		 2835 if (ops->pwork_60sec)
2836 ops->pwork_60sec(dev);
18c8adeb
MB		 2837
2838 /* Force check the TX power emission now. */
2839 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2840}
2841
2842static void b43_periodic_every30sec(struct b43_wldev *dev)
2843{
2844 /* Update device statistics. */
2845 b43_calculate_link_quality(dev);
2846}
2847
2848static void b43_periodic_every15sec(struct b43_wldev *dev)
2849{
2850 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2851 u16 wdr;
2852
2853 if (dev->fw.opensource) {
2854 /* Check if the firmware is still alive.
2855 * It will reset the watchdog counter to 0 in its idle loop. */
2856 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2857 if (unlikely(wdr)) {
2858 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2859 b43_controller_restart(dev, "Firmware watchdog");
2860 return;
2861 } else {
2862 b43_shm_write16(dev, B43_SHM_SCRATCH,
2863 B43_WATCHDOG_REG, 1);
2864 }
2865 }
e4d6b795 2866
ef1a628d
MB		 2867 if (phy->ops->pwork_15sec)
2868 phy->ops->pwork_15sec(dev);
2869
00e0b8cb
SB		 2870 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2871 wmb();
e4d6b795
MB		 2872}
2873
e4d6b795
MB		 2874static void do_periodic_work(struct b43_wldev *dev)
2875{
2876 unsigned int state;
2877
2878 state = dev->periodic_state;
42bb4cd5 2879 if (state % 4 == 0)
e4d6b795 2880 b43_periodic_every60sec(dev);
42bb4cd5 2881 if (state % 2 == 0)
e4d6b795 2882 b43_periodic_every30sec(dev);
42bb4cd5 2883 b43_periodic_every15sec(dev);
e4d6b795
MB		 2884}
2885
05b64b36
MB		 2886/* Periodic work locking policy:
2887 * The whole periodic work handler is protected by
2888 * wl->mutex. If another lock is needed somewhere in the
2889 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2890 */
e4d6b795
MB		 2891static void b43_periodic_work_handler(struct work_struct *work)
2892{
05b64b36
MB		 2893 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2894 periodic_work.work);
2895 struct b43_wl *wl = dev->wl;
2896 unsigned long delay;
e4d6b795 2897
05b64b36 2898 mutex_lock(&wl->mutex);
e4d6b795
MB		 2899
2900 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2901 goto out;
2902 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2903 goto out_requeue;
2904
05b64b36 2905 do_periodic_work(dev);
e4d6b795 2906
e4d6b795 2907 dev->periodic_state++;
42bb4cd5 2908out_requeue:
e4d6b795
MB		 2909 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2910 delay = msecs_to_jiffies(50);
2911 else
82cd682d 2912 delay = round_jiffies_relative(HZ * 15);
05b64b36 2913 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2914out:
05b64b36 2915 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2916}
2917
2918static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2919{
2920 struct delayed_work *work = &dev->periodic_work;
2921
2922 dev->periodic_state = 0;
2923 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2924 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2925}
2926
f3dd3fcc 2927/* Check if communication with the device works correctly. */
e4d6b795
MB		 2928static int b43_validate_chipaccess(struct b43_wldev *dev)
2929{
f3dd3fcc 2930 u32 v, backup;
e4d6b795 2931
f3dd3fcc
MB		 2932 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2933
2934 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2935 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2936 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2937 goto error;
f3dd3fcc
MB		 2938 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2939 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2940 goto error;
2941
f3dd3fcc
MB		 2942 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2943
2944 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2945 /* The 32bit register shadows the two 16bit registers
2946 * with update sideeffects. Validate this. */
2947 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2948 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2949 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2950 goto error;
2951 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2952 goto error;
2953 }
2954 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2955
2956 v = b43_read32(dev, B43_MMIO_MACCTL);
2957 v |= B43_MACCTL_GMODE;
2958 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2959 goto error;
2960
2961 return 0;
f3dd3fcc 2962error:
e4d6b795
MB		 2963 b43err(dev->wl, "Failed to validate the chipaccess\n");
2964 return -ENODEV;
2965}
2966
2967static void b43_security_init(struct b43_wldev *dev)
2968{
2969 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2970 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2971 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2972 /* KTP is a word address, but we address SHM bytewise.
2973 * So multiply by two.
2974 */
2975 dev->ktp *= 2;
2976 if (dev->dev->id.revision >= 5) {
2977 /* Number of RCMTA address slots */
2978 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2979 }
2980 b43_clear_keys(dev);
2981}
2982
616de35d 2983#ifdef CONFIG_B43_HWRNG
99da185a 2984static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 2985{
2986 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2987 unsigned long flags;
2988
2989 /* Don't take wl->mutex here, as it could deadlock with
2990 * hwrng internal locking. It's not needed to take
2991 * wl->mutex here, anyway. */
2992
2993 spin_lock_irqsave(&wl->irq_lock, flags);
2994 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2995 spin_unlock_irqrestore(&wl->irq_lock, flags);
2996
2997 return (sizeof(u16));
2998}
616de35d 2999#endif /* CONFIG_B43_HWRNG */
e4d6b795 3000
b844eba2 3001static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3002{
616de35d 3003#ifdef CONFIG_B43_HWRNG
e4d6b795 3004 if (wl->rng_initialized)
b844eba2 3005 hwrng_unregister(&wl->rng);
616de35d 3006#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3007}
3008
3009static int b43_rng_init(struct b43_wl *wl)
3010{
616de35d 3011 int err = 0;
e4d6b795 3012
616de35d 3013#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3014 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3015 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3016 wl->rng.name = wl->rng_name;
3017 wl->rng.data_read = b43_rng_read;
3018 wl->rng.priv = (unsigned long)wl;
3019 wl->rng_initialized = 1;
3020 err = hwrng_register(&wl->rng);
3021 if (err) {
3022 wl->rng_initialized = 0;
3023 b43err(wl, "Failed to register the random "
3024 "number generator (%d)\n", err);
3025 }
616de35d 3026#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3027
3028 return err;
3029}
3030
40faacc4 3031static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 3032 struct sk_buff *skb)
e4d6b795
MB		 3033{
3034 struct b43_wl *wl = hw_to_b43_wl(hw);
3035 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 3036 unsigned long flags;
3037 int err;
e4d6b795 3038
5100d5ac
MB		 3039 if (unlikely(skb->len < 2 + 2 + 6)) {
3040 /* Too short, this can't be a valid frame. */
c9e8eae0 3041 goto drop_packet;
5100d5ac
MB		 3042 }
3043 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 3044 if (unlikely(!dev))
c9e8eae0 3045 goto drop_packet;
21a75d77
MB		 3046
3047 /* Transmissions on seperate queues can run concurrently. */
3048 read_lock_irqsave(&wl->tx_lock, flags);
3049
3050 err = -ENODEV;
3051 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3052 if (b43_using_pio_transfers(dev))
e039fa4a 3053 err = b43_pio_tx(dev, skb);
21a75d77 3054 else
e039fa4a 3055 err = b43_dma_tx(dev, skb);
21a75d77
MB		 3056 }
3057
3058 read_unlock_irqrestore(&wl->tx_lock, flags);
3059
e4d6b795 3060 if (unlikely(err))
c9e8eae0
MB		 3061 goto drop_packet;
3062 return NETDEV_TX_OK;
3063
3064drop_packet:
3065 /* We can not transmit this packet. Drop it. */
3066 dev_kfree_skb_any(skb);
e4d6b795
MB		 3067 return NETDEV_TX_OK;
3068}
3069
e6f5b934
MB		 3070/* Locking: wl->irq_lock */
3071static void b43_qos_params_upload(struct b43_wldev *dev,
3072 const struct ieee80211_tx_queue_params *p,
3073 u16 shm_offset)
3074{
3075 u16 params[B43_NR_QOSPARAMS];
0b57664c 3076 int bslots, tmp;
e6f5b934
MB		 3077 unsigned int i;
3078
0b57664c 3079 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3080
3081 memset(&params, 0, sizeof(params));
3082
3083 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3084 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3085 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3086 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3087 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3088 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3089 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3090
3091 for (i = 0; i < ARRAY_SIZE(params); i++) {
3092 if (i == B43_QOSPARAM_STATUS) {
3093 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3094 shm_offset + (i * 2));
3095 /* Mark the parameters as updated. */
3096 tmp |= 0x100;
3097 b43_shm_write16(dev, B43_SHM_SHARED,
3098 shm_offset + (i * 2),
3099 tmp);
3100 } else {
3101 b43_shm_write16(dev, B43_SHM_SHARED,
3102 shm_offset + (i * 2),
3103 params[i]);
3104 }
3105 }
3106}
3107
c40c1129
MB		 3108/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3109static const u16 b43_qos_shm_offsets[] = {
3110 /* [mac80211-queue-nr] = SHM_OFFSET, */
3111 [0] = B43_QOS_VOICE,
3112 [1] = B43_QOS_VIDEO,
3113 [2] = B43_QOS_BESTEFFORT,
3114 [3] = B43_QOS_BACKGROUND,
3115};
3116
5a5f3b40
MB		 3117/* Update all QOS parameters in hardware. */
3118static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3119{
3120 struct b43_wl *wl = dev->wl;
3121 struct b43_qos_params *params;
e6f5b934
MB		 3122 unsigned int i;
3123
c40c1129
MB		 3124 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3125 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3126
3127 b43_mac_suspend(dev);
e6f5b934
MB		 3128 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3129 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3130 b43_qos_params_upload(dev, &(params->p),
3131 b43_qos_shm_offsets[i]);
e6f5b934 3132 }
e6f5b934
MB		 3133 b43_mac_enable(dev);
3134}
3135
3136static void b43_qos_clear(struct b43_wl *wl)
3137{
3138 struct b43_qos_params *params;
3139 unsigned int i;
3140
c40c1129
MB		 3141 /* Initialize QoS parameters to sane defaults. */
3142
3143 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3144 ARRAY_SIZE(wl->qos_params));
3145
e6f5b934
MB		 3146 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3147 params = &(wl->qos_params[i]);
3148
c40c1129
MB		 3149 switch (b43_qos_shm_offsets[i]) {
3150 case B43_QOS_VOICE:
3151 params->p.txop = 0;
3152 params->p.aifs = 2;
3153 params->p.cw_min = 0x0001;
3154 params->p.cw_max = 0x0001;
3155 break;
3156 case B43_QOS_VIDEO:
3157 params->p.txop = 0;
3158 params->p.aifs = 2;
3159 params->p.cw_min = 0x0001;
3160 params->p.cw_max = 0x0001;
3161 break;
3162 case B43_QOS_BESTEFFORT:
3163 params->p.txop = 0;
3164 params->p.aifs = 3;
3165 params->p.cw_min = 0x0001;
3166 params->p.cw_max = 0x03FF;
3167 break;
3168 case B43_QOS_BACKGROUND:
3169 params->p.txop = 0;
3170 params->p.aifs = 7;
3171 params->p.cw_min = 0x0001;
3172 params->p.cw_max = 0x03FF;
3173 break;
3174 default:
3175 B43_WARN_ON(1);
3176 }
e6f5b934
MB		 3177 }
3178}
3179
3180/* Initialize the core's QOS capabilities */
3181static void b43_qos_init(struct b43_wldev *dev)
3182{
e6f5b934 3183 /* Upload the current QOS parameters. */
5a5f3b40 3184 b43_qos_upload_all(dev);
e6f5b934
MB		 3185
3186 /* Enable QOS support. */
3187 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3188 b43_write16(dev, B43_MMIO_IFSCTL,
3189 b43_read16(dev, B43_MMIO_IFSCTL)
3190 | B43_MMIO_IFSCTL_USE_EDCF);
3191}
3192
e100bb64 3193static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3194 const struct ieee80211_tx_queue_params *params)
e4d6b795 3195{
e6f5b934 3196 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3197 struct b43_wldev *dev;
e6f5b934 3198 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3199 int err = -ENODEV;
e6f5b934
MB		 3200
3201 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3202 /* Queue not available or don't support setting
3203 * params on this queue. Return success to not
3204 * confuse mac80211. */
3205 return 0;
3206 }
5a5f3b40
MB		 3207 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3208 ARRAY_SIZE(wl->qos_params));
e6f5b934 3209
5a5f3b40
MB		 3210 mutex_lock(&wl->mutex);
3211 dev = wl->current_dev;
3212 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3213 goto out_unlock;
e6f5b934 3214
5a5f3b40
MB		 3215 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3216 b43_mac_suspend(dev);
3217 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3218 b43_qos_shm_offsets[queue]);
3219 b43_mac_enable(dev);
3220 err = 0;
e6f5b934 3221
5a5f3b40
MB		 3222out_unlock:
3223 mutex_unlock(&wl->mutex);
3224
3225 return err;
e4d6b795
MB		 3226}
3227
40faacc4
MB		 3228static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3229 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3230{
3231 struct b43_wl *wl = hw_to_b43_wl(hw);
3232 struct b43_wldev *dev = wl->current_dev;
3233 unsigned long flags;
3234 int err = -ENODEV;
3235
3236 if (!dev)
3237 goto out;
3238 spin_lock_irqsave(&wl->irq_lock, flags);
3239 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3240 if (b43_using_pio_transfers(dev))
3241 b43_pio_get_tx_stats(dev, stats);
3242 else
3243 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3244 err = 0;
3245 }
3246 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3247out:
e4d6b795
MB		 3248 return err;
3249}
3250
40faacc4
MB		 3251static int b43_op_get_stats(struct ieee80211_hw *hw,
3252 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3253{
3254 struct b43_wl *wl = hw_to_b43_wl(hw);
3255 unsigned long flags;
3256
3257 spin_lock_irqsave(&wl->irq_lock, flags);
3258 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3259 spin_unlock_irqrestore(&wl->irq_lock, flags);
3260
3261 return 0;
3262}
3263
08e87a83
AF		 3264static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3265{
3266 struct b43_wl *wl = hw_to_b43_wl(hw);
3267 struct b43_wldev *dev;
3268 u64 tsf;
3269
3270 mutex_lock(&wl->mutex);
3271 spin_lock_irq(&wl->irq_lock);
3272 dev = wl->current_dev;
3273
3274 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3275 b43_tsf_read(dev, &tsf);
3276 else
3277 tsf = 0;
3278
3279 spin_unlock_irq(&wl->irq_lock);
3280 mutex_unlock(&wl->mutex);
3281
3282 return tsf;
3283}
3284
3285static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3286{
3287 struct b43_wl *wl = hw_to_b43_wl(hw);
3288 struct b43_wldev *dev;
3289
3290 mutex_lock(&wl->mutex);
3291 spin_lock_irq(&wl->irq_lock);
3292 dev = wl->current_dev;
3293
3294 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3295 b43_tsf_write(dev, tsf);
3296
3297 spin_unlock_irq(&wl->irq_lock);
3298 mutex_unlock(&wl->mutex);
3299}
3300
e4d6b795
MB		 3301static void b43_put_phy_into_reset(struct b43_wldev *dev)
3302{
3303 struct ssb_device *sdev = dev->dev;
3304 u32 tmslow;
3305
3306 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3307 tmslow &= ~B43_TMSLOW_GMODE;
3308 tmslow |= B43_TMSLOW_PHYRESET;
3309 tmslow |= SSB_TMSLOW_FGC;
3310 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3311 msleep(1);
3312
3313 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3314 tmslow &= ~SSB_TMSLOW_FGC;
3315 tmslow |= B43_TMSLOW_PHYRESET;
3316 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3317 msleep(1);
3318}
3319
99da185a 3320static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3321{
3322 switch (band) {
3323 case IEEE80211_BAND_5GHZ:
3324 return "5";
3325 case IEEE80211_BAND_2GHZ:
3326 return "2.4";
3327 default:
3328 break;
3329 }
3330 B43_WARN_ON(1);
3331 return "";
3332}
3333
e4d6b795 3334/* Expects wl->mutex locked */
bb1eeff1 3335static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3336{
bb1eeff1 3337 struct b43_wldev *up_dev = NULL;
e4d6b795 3338 struct b43_wldev *down_dev;
bb1eeff1 3339 struct b43_wldev *d;
e4d6b795 3340 int err;
922d8a0b 3341 bool uninitialized_var(gmode);
e4d6b795
MB		 3342 int prev_status;
3343
bb1eeff1
MB		 3344 /* Find a device and PHY which supports the band. */
3345 list_for_each_entry(d, &wl->devlist, list) {
3346 switch (chan->band) {
3347 case IEEE80211_BAND_5GHZ:
3348 if (d->phy.supports_5ghz) {
3349 up_dev = d;
3350 gmode = 0;
3351 }
3352 break;
3353 case IEEE80211_BAND_2GHZ:
3354 if (d->phy.supports_2ghz) {
3355 up_dev = d;
3356 gmode = 1;
3357 }
3358 break;
3359 default:
3360 B43_WARN_ON(1);
3361 return -EINVAL;
3362 }
3363 if (up_dev)
3364 break;
3365 }
3366 if (!up_dev) {
3367 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3368 band_to_string(chan->band));
3369 return -ENODEV;
e4d6b795
MB		 3370 }
3371 if ((up_dev == wl->current_dev) &&
3372 (!!wl->current_dev->phy.gmode == !!gmode)) {
3373 /* This device is already running. */
3374 return 0;
3375 }
bb1eeff1
MB		 3376 b43dbg(wl, "Switching to %s-GHz band\n",
3377 band_to_string(chan->band));
e4d6b795
MB		 3378 down_dev = wl->current_dev;
3379
3380 prev_status = b43_status(down_dev);
3381 /* Shutdown the currently running core. */
3382 if (prev_status >= B43_STAT_STARTED)
3383 b43_wireless_core_stop(down_dev);
3384 if (prev_status >= B43_STAT_INITIALIZED)
3385 b43_wireless_core_exit(down_dev);
3386
3387 if (down_dev != up_dev) {
3388 /* We switch to a different core, so we put PHY into
3389 * RESET on the old core. */
3390 b43_put_phy_into_reset(down_dev);
3391 }
3392
3393 /* Now start the new core. */
3394 up_dev->phy.gmode = gmode;
3395 if (prev_status >= B43_STAT_INITIALIZED) {
3396 err = b43_wireless_core_init(up_dev);
3397 if (err) {
3398 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3399 "selected %s-GHz band\n",
3400 band_to_string(chan->band));
e4d6b795
MB		 3401 goto init_failure;
3402 }
3403 }
3404 if (prev_status >= B43_STAT_STARTED) {
3405 err = b43_wireless_core_start(up_dev);
3406 if (err) {
3407 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3408 "selected %s-GHz band\n",
3409 band_to_string(chan->band));
e4d6b795
MB		 3410 b43_wireless_core_exit(up_dev);
3411 goto init_failure;
3412 }
3413 }
3414 B43_WARN_ON(b43_status(up_dev) != prev_status);
3415
3416 wl->current_dev = up_dev;
3417
3418 return 0;
bb1eeff1 3419init_failure:
e4d6b795
MB		 3420 /* Whoops, failed to init the new core. No core is operating now. */
3421 wl->current_dev = NULL;
3422 return err;
3423}
3424
9124b077
JB		 3425/* Write the short and long frame retry limit values. */
3426static void b43_set_retry_limits(struct b43_wldev *dev,
3427 unsigned int short_retry,
3428 unsigned int long_retry)
3429{
3430 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3431 * the chip-internal counter. */
3432 short_retry = min(short_retry, (unsigned int)0xF);
3433 long_retry = min(long_retry, (unsigned int)0xF);
3434
3435 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3436 short_retry);
3437 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3438 long_retry);
3439}
3440
e8975581 3441static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3442{
3443 struct b43_wl *wl = hw_to_b43_wl(hw);
3444 struct b43_wldev *dev;
3445 struct b43_phy *phy;
e8975581 3446 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3447 unsigned long flags;
9db1f6d7 3448 int antenna;
e4d6b795 3449 int err = 0;
e4d6b795 3450
e4d6b795
MB		 3451 mutex_lock(&wl->mutex);
3452
bb1eeff1
MB		 3453 /* Switch the band (if necessary). This might change the active core. */
3454 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3455 if (err)
3456 goto out_unlock_mutex;
3457 dev = wl->current_dev;
3458 phy = &dev->phy;
3459
d10d0e57
MB		 3460 b43_mac_suspend(dev);
3461
9124b077
JB		 3462 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3463 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3464 conf->long_frame_max_tx_count);
3465 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3466 if (!changed)
d10d0e57 3467 goto out_mac_enable;
e4d6b795
MB		 3468
3469 /* Switch to the requested channel.
3470 * The firmware takes care of races with the TX handler. */
8318d78a 3471 if (conf->channel->hw_value != phy->channel)
ef1a628d 3472 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3473
d42ce84a
JB		 3474 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3475
e4d6b795
MB		 3476 /* Adjust the desired TX power level. */
3477 if (conf->power_level != 0) {
18c8adeb
MB		 3478 spin_lock_irqsave(&wl->irq_lock, flags);
3479 if (conf->power_level != phy->desired_txpower) {
3480 phy->desired_txpower = conf->power_level;
3481 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3482 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3483 }
18c8adeb 3484 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3485 }
3486
3487 /* Antennas for RX and management frame TX. */
0f4ac38b 3488 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3489 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3490 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3491 if (phy->ops->set_rx_antenna)
3492 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3493
04dea136 3494 /* Update templates for AP/mesh mode. */
05c914fe
JB		 3495 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3496 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
e4d6b795
MB		 3497 b43_set_beacon_int(dev, conf->beacon_int);
3498
fda9abcf
MB		 3499 if (!!conf->radio_enabled != phy->radio_on) {
3500 if (conf->radio_enabled) {
ef1a628d 3501 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
fda9abcf
MB		 3502 b43info(dev->wl, "Radio turned on by software\n");
3503 if (!dev->radio_hw_enable) {
3504 b43info(dev->wl, "The hardware RF-kill button "
3505 "still turns the radio physically off. "
3506 "Press the button to turn it on.\n");
3507 }
3508 } else {
ef1a628d 3509 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
fda9abcf
MB		 3510 b43info(dev->wl, "Radio turned off by software\n");
3511 }
3512 }
3513
d10d0e57
MB		 3514out_mac_enable:
3515 b43_mac_enable(dev);
3516out_unlock_mutex:
e4d6b795
MB		 3517 mutex_unlock(&wl->mutex);
3518
3519 return err;
3520}
3521
881d948c 3522static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3523{
3524 struct ieee80211_supported_band *sband =
3525 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3526 struct ieee80211_rate *rate;
3527 int i;
3528 u16 basic, direct, offset, basic_offset, rateptr;
3529
3530 for (i = 0; i < sband->n_bitrates; i++) {
3531 rate = &sband->bitrates[i];
3532
3533 if (b43_is_cck_rate(rate->hw_value)) {
3534 direct = B43_SHM_SH_CCKDIRECT;
3535 basic = B43_SHM_SH_CCKBASIC;
3536 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3537 offset &= 0xF;
3538 } else {
3539 direct = B43_SHM_SH_OFDMDIRECT;
3540 basic = B43_SHM_SH_OFDMBASIC;
3541 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3542 offset &= 0xF;
3543 }
3544
3545 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3546
3547 if (b43_is_cck_rate(rate->hw_value)) {
3548 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3549 basic_offset &= 0xF;
3550 } else {
3551 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3552 basic_offset &= 0xF;
3553 }
3554
3555 /*
3556 * Get the pointer that we need to point to
3557 * from the direct map
3558 */
3559 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3560 direct + 2 * basic_offset);
3561 /* and write it to the basic map */
3562 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3563 rateptr);
3564 }
3565}
3566
3567static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3568 struct ieee80211_vif *vif,
3569 struct ieee80211_bss_conf *conf,
3570 u32 changed)
3571{
3572 struct b43_wl *wl = hw_to_b43_wl(hw);
3573 struct b43_wldev *dev;
c7ab5ef9
JB		 3574
3575 mutex_lock(&wl->mutex);
3576
3577 dev = wl->current_dev;
d10d0e57 3578 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3579 goto out_unlock_mutex;
c7ab5ef9
JB		 3580 b43_mac_suspend(dev);
3581
3582 if (changed & BSS_CHANGED_BASIC_RATES)
3583 b43_update_basic_rates(dev, conf->basic_rates);
3584
3585 if (changed & BSS_CHANGED_ERP_SLOT) {
3586 if (conf->use_short_slot)
3587 b43_short_slot_timing_enable(dev);
3588 else
3589 b43_short_slot_timing_disable(dev);
3590 }
3591
3592 b43_mac_enable(dev);
d10d0e57 3593out_unlock_mutex:
c7ab5ef9
JB		 3594 mutex_unlock(&wl->mutex);
3595
3596 return;
3597}
3598
40faacc4 3599static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3600 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3601 struct ieee80211_key_conf *key)
e4d6b795
MB		 3602{
3603 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3604 struct b43_wldev *dev;
e4d6b795
MB		 3605 u8 algorithm;
3606 u8 index;
c6dfc9a8 3607 int err;
060210f9 3608 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3609
3610 if (modparam_nohwcrypt)
3611 return -ENOSPC; /* User disabled HW-crypto */
3612
c6dfc9a8 3613 mutex_lock(&wl->mutex);
e808e586
MB		 3614 spin_lock_irq(&wl->irq_lock);
3615 write_lock(&wl->tx_lock);
3616 /* Why do we need all this locking here?
3617 * mutex -> Every config operation must take it.
3618 * irq_lock -> We modify the dev->key array, which is accessed
3619 * in the IRQ handlers.
3620 * tx_lock -> We modify the dev->key array, which is accessed
3621 * in the TX handler.
3622 */
c6dfc9a8
MB		 3623
3624 dev = wl->current_dev;
3625 err = -ENODEV;
3626 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3627 goto out_unlock;
3628
68217832
MB		 3629 if (dev->fw.pcm_request_failed) {
3630 /* We don't have firmware for the crypto engine.
3631 * Must use software-crypto. */
3632 err = -EOPNOTSUPP;
3633 goto out_unlock;
3634 }
3635
c6dfc9a8 3636 err = -EINVAL;
e4d6b795 3637 switch (key->alg) {
e4d6b795 3638 case ALG_WEP:
e808e586 3639 if (key->keylen == LEN_WEP40)
e4d6b795
MB		 3640 algorithm = B43_SEC_ALGO_WEP40;
3641 else
3642 algorithm = B43_SEC_ALGO_WEP104;
3643 break;
3644 case ALG_TKIP:
3645 algorithm = B43_SEC_ALGO_TKIP;
3646 break;
3647 case ALG_CCMP:
3648 algorithm = B43_SEC_ALGO_AES;
3649 break;
3650 default:
3651 B43_WARN_ON(1);
c6dfc9a8 3652 goto out_unlock;
e4d6b795 3653 }
e4d6b795
MB		 3654 index = (u8) (key->keyidx);
3655 if (index > 3)
e4d6b795 3656 goto out_unlock;
e4d6b795
MB		 3657
3658 switch (cmd) {
3659 case SET_KEY:
3660 if (algorithm == B43_SEC_ALGO_TKIP) {
3661 /* FIXME: No TKIP hardware encryption for now. */
3662 err = -EOPNOTSUPP;
3663 goto out_unlock;
3664 }
3665
e808e586 3666 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3667 if (WARN_ON(!sta)) {
3668 err = -EOPNOTSUPP;
3669 goto out_unlock;
3670 }
e808e586 3671 /* Pairwise key with an assigned MAC address. */
e4d6b795 3672 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3673 key->key, key->keylen,
3674 sta->addr, key);
e808e586
MB		 3675 } else {
3676 /* Group key */
3677 err = b43_key_write(dev, index, algorithm,
3678 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3679 }
3680 if (err)
3681 goto out_unlock;
3682
3683 if (algorithm == B43_SEC_ALGO_WEP40 ||
3684 algorithm == B43_SEC_ALGO_WEP104) {
3685 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3686 } else {
3687 b43_hf_write(dev,
3688 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3689 }
3690 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3691 break;
3692 case DISABLE_KEY: {
3693 err = b43_key_clear(dev, key->hw_key_idx);
3694 if (err)
3695 goto out_unlock;
3696 break;
3697 }
3698 default:
3699 B43_WARN_ON(1);
3700 }
9cf7f247 3701
e4d6b795 3702out_unlock:
e4d6b795
MB		 3703 if (!err) {
3704 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3705 "mac: %pM\n",
e4d6b795 3706 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3707 sta ? sta->addr : bcast_addr);
9cf7f247 3708 b43_dump_keymemory(dev);
e4d6b795 3709 }
e808e586
MB		 3710 write_unlock(&wl->tx_lock);
3711 spin_unlock_irq(&wl->irq_lock);
9cf7f247
MB		 3712 mutex_unlock(&wl->mutex);
3713
e4d6b795
MB		 3714 return err;
3715}
3716
40faacc4
MB		 3717static void b43_op_configure_filter(struct ieee80211_hw *hw,
3718 unsigned int changed, unsigned int *fflags,
3719 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3720{
3721 struct b43_wl *wl = hw_to_b43_wl(hw);
3722 struct b43_wldev *dev = wl->current_dev;
3723 unsigned long flags;
3724
4150c572
JB		 3725 if (!dev) {
3726 *fflags = 0;
e4d6b795 3727 return;
e4d6b795 3728 }
4150c572
JB		 3729
3730 spin_lock_irqsave(&wl->irq_lock, flags);
3731 *fflags &= FIF_PROMISC_IN_BSS |
3732 FIF_ALLMULTI |
3733 FIF_FCSFAIL |
3734 FIF_PLCPFAIL |
3735 FIF_CONTROL |
3736 FIF_OTHER_BSS |
3737 FIF_BCN_PRBRESP_PROMISC;
3738
3739 changed &= FIF_PROMISC_IN_BSS |
3740 FIF_ALLMULTI |
3741 FIF_FCSFAIL |
3742 FIF_PLCPFAIL |
3743 FIF_CONTROL |
3744 FIF_OTHER_BSS |
3745 FIF_BCN_PRBRESP_PROMISC;
3746
3747 wl->filter_flags = *fflags;
3748
3749 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3750 b43_adjust_opmode(dev);
e4d6b795
MB		 3751 spin_unlock_irqrestore(&wl->irq_lock, flags);
3752}
3753
40faacc4 3754static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3755 struct ieee80211_vif *vif,
40faacc4 3756 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3757{
3758 struct b43_wl *wl = hw_to_b43_wl(hw);
3759 struct b43_wldev *dev = wl->current_dev;
3760 unsigned long flags;
3761
3762 if (!dev)
3763 return -ENODEV;
3764 mutex_lock(&wl->mutex);
3765 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3766 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3767 if (conf->bssid)
3768 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3769 else
3770 memset(wl->bssid, 0, ETH_ALEN);
3771 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
05c914fe
JB		 3772 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3773 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
9d139c81 3774 B43_WARN_ON(vif->type != wl->if_type);
9d139c81
JB		 3775 if (conf->changed & IEEE80211_IFCC_BEACON)
3776 b43_update_templates(wl);
05c914fe 3777 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 3778 if (conf->changed & IEEE80211_IFCC_BEACON)
3779 b43_update_templates(wl);
e4d6b795 3780 }
4150c572 3781 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3782 }
3783 spin_unlock_irqrestore(&wl->irq_lock, flags);
3784 mutex_unlock(&wl->mutex);
3785
3786 return 0;
3787}
3788
3789/* Locking: wl->mutex */
3790static void b43_wireless_core_stop(struct b43_wldev *dev)
3791{
3792 struct b43_wl *wl = dev->wl;
3793 unsigned long flags;
3794
3795 if (b43_status(dev) < B43_STAT_STARTED)
3796 return;
a19d12d7
SB		 3797
3798 /* Disable and sync interrupts. We must do this before than
3799 * setting the status to INITIALIZED, as the interrupt handler
3800 * won't care about IRQs then. */
3801 spin_lock_irqsave(&wl->irq_lock, flags);
3802 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3803 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3804 spin_unlock_irqrestore(&wl->irq_lock, flags);
3805 b43_synchronize_irq(dev);
3806
21a75d77 3807 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3808 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3809 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3810
5100d5ac 3811 b43_pio_stop(dev);
e4d6b795
MB		 3812 mutex_unlock(&wl->mutex);
3813 /* Must unlock as it would otherwise deadlock. No races here.
3814 * Cancel the possibly running self-rearming periodic work. */
3815 cancel_delayed_work_sync(&dev->periodic_work);
3816 mutex_lock(&wl->mutex);
3817
e4d6b795
MB		 3818 b43_mac_suspend(dev);
3819 free_irq(dev->dev->irq, dev);
3820 b43dbg(wl, "Wireless interface stopped\n");
3821}
3822
3823/* Locking: wl->mutex */
3824static int b43_wireless_core_start(struct b43_wldev *dev)
3825{
3826 int err;
3827
3828 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3829
3830 drain_txstatus_queue(dev);
3831 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3832 IRQF_SHARED, KBUILD_MODNAME, dev);
3833 if (err) {
3834 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3835 goto out;
3836 }
3837
3838 /* We are ready to run. */
3839 b43_set_status(dev, B43_STAT_STARTED);
3840
3841 /* Start data flow (TX/RX). */
3842 b43_mac_enable(dev);
3843 b43_interrupt_enable(dev, dev->irq_savedstate);
e4d6b795
MB		 3844
3845 /* Start maintainance work */
3846 b43_periodic_tasks_setup(dev);
3847
3848 b43dbg(dev->wl, "Wireless interface started\n");
3849 out:
3850 return err;
3851}
3852
3853/* Get PHY and RADIO versioning numbers */
3854static int b43_phy_versioning(struct b43_wldev *dev)
3855{
3856 struct b43_phy *phy = &dev->phy;
3857 u32 tmp;
3858 u8 analog_type;
3859 u8 phy_type;
3860 u8 phy_rev;
3861 u16 radio_manuf;
3862 u16 radio_ver;
3863 u16 radio_rev;
3864 int unsupported = 0;
3865
3866 /* Get PHY versioning */
3867 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3868 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3869 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3870 phy_rev = (tmp & B43_PHYVER_VERSION);
3871 switch (phy_type) {
3872 case B43_PHYTYPE_A:
3873 if (phy_rev >= 4)
3874 unsupported = 1;
3875 break;
3876 case B43_PHYTYPE_B:
3877 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3878 && phy_rev != 7)
3879 unsupported = 1;
3880 break;
3881 case B43_PHYTYPE_G:
013978b6 3882 if (phy_rev > 9)
e4d6b795
MB		 3883 unsupported = 1;
3884 break;
d5c71e46
MB		 3885#ifdef CONFIG_B43_NPHY
3886 case B43_PHYTYPE_N:
bb519bee 3887 if (phy_rev > 4)
d5c71e46
MB		 3888 unsupported = 1;
3889 break;
6b1c7c67
MB		 3890#endif
3891#ifdef CONFIG_B43_PHY_LP
3892 case B43_PHYTYPE_LP:
3893 if (phy_rev > 1)
3894 unsupported = 1;
3895 break;
d5c71e46 3896#endif
e4d6b795
MB		 3897 default:
3898 unsupported = 1;
3899 };
3900 if (unsupported) {
3901 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3902 "(Analog %u, Type %u, Revision %u)\n",
3903 analog_type, phy_type, phy_rev);
3904 return -EOPNOTSUPP;
3905 }
3906 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3907 analog_type, phy_type, phy_rev);
3908
3909 /* Get RADIO versioning */
3910 if (dev->dev->bus->chip_id == 0x4317) {
3911 if (dev->dev->bus->chip_rev == 0)
3912 tmp = 0x3205017F;
3913 else if (dev->dev->bus->chip_rev == 1)
3914 tmp = 0x4205017F;
3915 else
3916 tmp = 0x5205017F;
3917 } else {
3918 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3919 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3920 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3921 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3922 }
3923 radio_manuf = (tmp & 0x00000FFF);
3924 radio_ver = (tmp & 0x0FFFF000) >> 12;
3925 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3926 if (radio_manuf != 0x17F /* Broadcom */)
3927 unsupported = 1;
e4d6b795
MB		 3928 switch (phy_type) {
3929 case B43_PHYTYPE_A:
3930 if (radio_ver != 0x2060)
3931 unsupported = 1;
3932 if (radio_rev != 1)
3933 unsupported = 1;
3934 if (radio_manuf != 0x17F)
3935 unsupported = 1;
3936 break;
3937 case B43_PHYTYPE_B:
3938 if ((radio_ver & 0xFFF0) != 0x2050)
3939 unsupported = 1;
3940 break;
3941 case B43_PHYTYPE_G:
3942 if (radio_ver != 0x2050)
3943 unsupported = 1;
3944 break;
96c755a3 3945 case B43_PHYTYPE_N:
bb519bee 3946 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3947 unsupported = 1;
3948 break;
6b1c7c67
MB		 3949 case B43_PHYTYPE_LP:
3950 if (radio_ver != 0x2062)
3951 unsupported = 1;
3952 break;
e4d6b795
MB		 3953 default:
3954 B43_WARN_ON(1);
3955 }
3956 if (unsupported) {
3957 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3958 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3959 radio_manuf, radio_ver, radio_rev);
3960 return -EOPNOTSUPP;
3961 }
3962 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3963 radio_manuf, radio_ver, radio_rev);
3964
3965 phy->radio_manuf = radio_manuf;
3966 phy->radio_ver = radio_ver;
3967 phy->radio_rev = radio_rev;
3968
3969 phy->analog = analog_type;
3970 phy->type = phy_type;
3971 phy->rev = phy_rev;
3972
3973 return 0;
3974}
3975
3976static void setup_struct_phy_for_init(struct b43_wldev *dev,
3977 struct b43_phy *phy)
3978{
e4d6b795 3979 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3980 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3981 /* PHY TX errors counter. */
3982 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 3983
3984#if B43_DEBUG
3985 phy->phy_locked = 0;
3986 phy->radio_locked = 0;
3987#endif
e4d6b795
MB		 3988}
3989
3990static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3991{
aa6c7ae2
MB		 3992 dev->dfq_valid = 0;
3993
6a724d68
MB		 3994 /* Assume the radio is enabled. If it's not enabled, the state will
3995 * immediately get fixed on the first periodic work run. */
3996 dev->radio_hw_enable = 1;
e4d6b795
MB		 3997
3998 /* Stats */
3999 memset(&dev->stats, 0, sizeof(dev->stats));
4000
4001 setup_struct_phy_for_init(dev, &dev->phy);
4002
4003 /* IRQ related flags */
4004 dev->irq_reason = 0;
4005 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4006 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3e3ccb3d
MB		 4007 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4008 dev->irq_savedstate &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4009
4010 dev->mac_suspended = 1;
4011
4012 /* Noise calculation context */
4013 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4014}
4015
4016static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4017{
4018 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4019 u64 hf;
e4d6b795 4020
1855ba78
MB		 4021 if (!modparam_btcoex)
4022 return;
95de2841 4023 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4024 return;
4025 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4026 return;
4027
4028 hf = b43_hf_read(dev);
95de2841 4029 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4030 hf |= B43_HF_BTCOEXALT;
4031 else
4032 hf |= B43_HF_BTCOEX;
4033 b43_hf_write(dev, hf);
e4d6b795
MB		 4034}
4035
4036static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4037{
4038 if (!modparam_btcoex)
4039 return;
4040 //TODO
e4d6b795
MB		 4041}
4042
4043static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4044{
4045#ifdef CONFIG_SSB_DRIVER_PCICORE
4046 struct ssb_bus *bus = dev->dev->bus;
4047 u32 tmp;
4048
4049 if (bus->pcicore.dev &&
4050 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4051 bus->pcicore.dev->id.revision <= 5) {
4052 /* IMCFGLO timeouts workaround. */
4053 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4054 tmp &= ~SSB_IMCFGLO_REQTO;
4055 tmp &= ~SSB_IMCFGLO_SERTO;
4056 switch (bus->bustype) {
4057 case SSB_BUSTYPE_PCI:
4058 case SSB_BUSTYPE_PCMCIA:
4059 tmp |= 0x32;
4060 break;
4061 case SSB_BUSTYPE_SSB:
4062 tmp |= 0x53;
4063 break;
4064 }
4065 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4066 }
4067#endif /* CONFIG_SSB_DRIVER_PCICORE */
4068}
4069
d59f720d
MB		 4070static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4071{
4072 u16 pu_delay;
4073
4074 /* The time value is in microseconds. */
4075 if (dev->phy.type == B43_PHYTYPE_A)
4076 pu_delay = 3700;
4077 else
4078 pu_delay = 1050;
05c914fe 4079 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4080 pu_delay = 500;
4081 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4082 pu_delay = max(pu_delay, (u16)2400);
4083
4084 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4085}
4086
4087/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4088static void b43_set_pretbtt(struct b43_wldev *dev)
4089{
4090 u16 pretbtt;
4091
4092 /* The time value is in microseconds. */
05c914fe 4093 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4094 pretbtt = 2;
4095 } else {
4096 if (dev->phy.type == B43_PHYTYPE_A)
4097 pretbtt = 120;
4098 else
4099 pretbtt = 250;
4100 }
4101 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4102 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4103}
4104
e4d6b795
MB		 4105/* Shutdown a wireless core */
4106/* Locking: wl->mutex */
4107static void b43_wireless_core_exit(struct b43_wldev *dev)
4108{
1f7d87b0 4109 u32 macctl;
e4d6b795
MB		 4110
4111 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4112 if (b43_status(dev) != B43_STAT_INITIALIZED)
4113 return;
4114 b43_set_status(dev, B43_STAT_UNINIT);
4115
1f7d87b0
MB		 4116 /* Stop the microcode PSM. */
4117 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4118 macctl &= ~B43_MACCTL_PSM_RUN;
4119 macctl |= B43_MACCTL_PSM_JMP0;
4120 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4121
3506e0c4
RW		 4122 if (!dev->suspend_in_progress) {
4123 b43_leds_exit(dev);
b844eba2 4124 b43_rng_exit(dev->wl);
3506e0c4 4125 }
e4d6b795 4126 b43_dma_free(dev);
5100d5ac 4127 b43_pio_free(dev);
e4d6b795 4128 b43_chip_exit(dev);
cb24f57f 4129 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4130 if (dev->wl->current_beacon) {
4131 dev_kfree_skb_any(dev->wl->current_beacon);
4132 dev->wl->current_beacon = NULL;
4133 }
4134
e4d6b795
MB		 4135 ssb_device_disable(dev->dev, 0);
4136 ssb_bus_may_powerdown(dev->dev->bus);
4137}
4138
4139/* Initialize a wireless core */
4140static int b43_wireless_core_init(struct b43_wldev *dev)
4141{
4142 struct b43_wl *wl = dev->wl;
4143 struct ssb_bus *bus = dev->dev->bus;
4144 struct ssb_sprom *sprom = &bus->sprom;
4145 struct b43_phy *phy = &dev->phy;
4146 int err;
a259d6a4
MB		 4147 u64 hf;
4148 u32 tmp;
e4d6b795
MB		 4149
4150 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4151
4152 err = ssb_bus_powerup(bus, 0);
4153 if (err)
4154 goto out;
4155 if (!ssb_device_is_enabled(dev->dev)) {
4156 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4157 b43_wireless_core_reset(dev, tmp);
4158 }
4159
fb11137a 4160 /* Reset all data structures. */
e4d6b795 4161 setup_struct_wldev_for_init(dev);
fb11137a 4162 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4163
4164 /* Enable IRQ routing to this device. */
4165 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4166
4167 b43_imcfglo_timeouts_workaround(dev);
4168 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4169 if (phy->ops->prepare_hardware) {
4170 err = phy->ops->prepare_hardware(dev);
ef1a628d 4171 if (err)
fb11137a 4172 goto err_busdown;
ef1a628d 4173 }
e4d6b795
MB		 4174 err = b43_chip_init(dev);
4175 if (err)
fb11137a 4176 goto err_busdown;
e4d6b795
MB		 4177 b43_shm_write16(dev, B43_SHM_SHARED,
4178 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4179 hf = b43_hf_read(dev);
4180 if (phy->type == B43_PHYTYPE_G) {
4181 hf |= B43_HF_SYMW;
4182 if (phy->rev == 1)
4183 hf |= B43_HF_GDCW;
95de2841 4184 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4185 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4186 }
4187 if (phy->radio_ver == 0x2050) {
4188 if (phy->radio_rev == 6)
4189 hf |= B43_HF_4318TSSI;
4190 if (phy->radio_rev < 6)
4191 hf |= B43_HF_VCORECALC;
e4d6b795 4192 }
1cc8f476
MB		 4193 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4194 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4195#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4196 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4197 (bus->pcicore.dev->id.revision <= 10))
4198 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4199#endif
25d3ef59 4200 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4201 b43_hf_write(dev, hf);
4202
74cfdba7
MB		 4203 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4204 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4206 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4207
4208 /* Disable sending probe responses from firmware.
4209 * Setting the MaxTime to one usec will always trigger
4210 * a timeout, so we never send any probe resp.
4211 * A timeout of zero is infinite. */
4212 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4213
4214 b43_rate_memory_init(dev);
5042c507 4215 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4216
4217 /* Minimum Contention Window */
4218 if (phy->type == B43_PHYTYPE_B) {
4219 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4220 } else {
4221 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4222 }
4223 /* Maximum Contention Window */
4224 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4225
5100d5ac
MB		 4226 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4227 dev->__using_pio_transfers = 1;
4228 err = b43_pio_init(dev);
4229 } else {
4230 dev->__using_pio_transfers = 0;
4231 err = b43_dma_init(dev);
4232 }
e4d6b795
MB		 4233 if (err)
4234 goto err_chip_exit;
03b29773 4235 b43_qos_init(dev);
d59f720d 4236 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4237 b43_bluetooth_coext_enable(dev);
4238
1cc8f476 4239 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4240 b43_upload_card_macaddress(dev);
e4d6b795 4241 b43_security_init(dev);
3506e0c4
RW		 4242 if (!dev->suspend_in_progress)
4243 b43_rng_init(wl);
e4d6b795
MB		 4244
4245 b43_set_status(dev, B43_STAT_INITIALIZED);
4246
3506e0c4
RW		 4247 if (!dev->suspend_in_progress)
4248 b43_leds_init(dev);
1a8d1227 4249out:
e4d6b795
MB		 4250 return err;
4251
ef1a628d 4252err_chip_exit:
e4d6b795 4253 b43_chip_exit(dev);
ef1a628d 4254err_busdown:
e4d6b795
MB		 4255 ssb_bus_may_powerdown(bus);
4256 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4257 return err;
4258}
4259
40faacc4
MB		 4260static int b43_op_add_interface(struct ieee80211_hw *hw,
4261 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4262{
4263 struct b43_wl *wl = hw_to_b43_wl(hw);
4264 struct b43_wldev *dev;
4265 unsigned long flags;
4266 int err = -EOPNOTSUPP;
4150c572
JB		 4267
4268 /* TODO: allow WDS/AP devices to coexist */
4269
05c914fe
JB		 4270 if (conf->type != NL80211_IFTYPE_AP &&
4271 conf->type != NL80211_IFTYPE_MESH_POINT &&
4272 conf->type != NL80211_IFTYPE_STATION &&
4273 conf->type != NL80211_IFTYPE_WDS &&
4274 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4275 return -EOPNOTSUPP;
e4d6b795
MB		 4276
4277 mutex_lock(&wl->mutex);
4150c572 4278 if (wl->operating)
e4d6b795
MB		 4279 goto out_mutex_unlock;
4280
4281 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4282
4283 dev = wl->current_dev;
4150c572 4284 wl->operating = 1;
32bfd35d 4285 wl->vif = conf->vif;
4150c572
JB		 4286 wl->if_type = conf->type;
4287 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4288
4289 spin_lock_irqsave(&wl->irq_lock, flags);
4290 b43_adjust_opmode(dev);
d59f720d
MB		 4291 b43_set_pretbtt(dev);
4292 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4293 b43_upload_card_macaddress(dev);
4294 spin_unlock_irqrestore(&wl->irq_lock, flags);
4295
4296 err = 0;
4297 out_mutex_unlock:
4298 mutex_unlock(&wl->mutex);
4299
4300 return err;
4301}
4302
40faacc4
MB		 4303static void b43_op_remove_interface(struct ieee80211_hw *hw,
4304 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4305{
4306 struct b43_wl *wl = hw_to_b43_wl(hw);
4307 struct b43_wldev *dev = wl->current_dev;
4308 unsigned long flags;
4309
4310 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4311
4312 mutex_lock(&wl->mutex);
4313
4314 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4315 B43_WARN_ON(wl->vif != conf->vif);
4316 wl->vif = NULL;
4150c572
JB		 4317
4318 wl->operating = 0;
4319
4320 spin_lock_irqsave(&wl->irq_lock, flags);
4321 b43_adjust_opmode(dev);
4322 memset(wl->mac_addr, 0, ETH_ALEN);
4323 b43_upload_card_macaddress(dev);
4324 spin_unlock_irqrestore(&wl->irq_lock, flags);
4325
4326 mutex_unlock(&wl->mutex);
4327}
4328
40faacc4 4329static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4330{
4331 struct b43_wl *wl = hw_to_b43_wl(hw);
4332 struct b43_wldev *dev = wl->current_dev;
4333 int did_init = 0;
923403b8 4334 int err = 0;
1946a2c3 4335 bool do_rfkill_exit = 0;
4150c572 4336
7be1bb6b
MB		 4337 /* Kill all old instance specific information to make sure
4338 * the card won't use it in the short timeframe between start
4339 * and mac80211 reconfiguring it. */
4340 memset(wl->bssid, 0, ETH_ALEN);
4341 memset(wl->mac_addr, 0, ETH_ALEN);
4342 wl->filter_flags = 0;
4343 wl->radiotap_enabled = 0;
e6f5b934 4344 b43_qos_clear(wl);
6b4bec01
MB		 4345 wl->beacon0_uploaded = 0;
4346 wl->beacon1_uploaded = 0;
4347 wl->beacon_templates_virgin = 1;
7be1bb6b 4348
1a8d1227
LF		 4349 /* First register RFkill.
4350 * LEDs that are registered later depend on it. */
4351 b43_rfkill_init(dev);
4352
4150c572
JB		 4353 mutex_lock(&wl->mutex);
4354
e4d6b795
MB		 4355 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4356 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4357 if (err) {
4358 do_rfkill_exit = 1;
e4d6b795 4359 goto out_mutex_unlock;
1946a2c3 4360 }
e4d6b795
MB		 4361 did_init = 1;
4362 }
4150c572 4363
e4d6b795
MB		 4364 if (b43_status(dev) < B43_STAT_STARTED) {
4365 err = b43_wireless_core_start(dev);
4366 if (err) {
4367 if (did_init)
4368 b43_wireless_core_exit(dev);
1946a2c3 4369 do_rfkill_exit = 1;
e4d6b795
MB		 4370 goto out_mutex_unlock;
4371 }
4372 }
4373
4150c572 4374 out_mutex_unlock:
e4d6b795
MB		 4375 mutex_unlock(&wl->mutex);
4376
1946a2c3
MB		 4377 if (do_rfkill_exit)
4378 b43_rfkill_exit(dev);
4379
e4d6b795
MB		 4380 return err;
4381}
4382
40faacc4 4383static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4384{
4385 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4386 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4387
1a8d1227 4388 b43_rfkill_exit(dev);
a82d9922 4389 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4390
e4d6b795 4391 mutex_lock(&wl->mutex);
4150c572
JB		 4392 if (b43_status(dev) >= B43_STAT_STARTED)
4393 b43_wireless_core_stop(dev);
4394 b43_wireless_core_exit(dev);
e4d6b795 4395 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4396
4397 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4398}
4399
17741cdc
JB		 4400static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4401 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4402{
4403 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4404 unsigned long flags;
e66fee6a 4405
d4df6f1a 4406 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4407 b43_update_templates(wl);
d4df6f1a 4408 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4409
4410 return 0;
4411}
4412
38968d09
JB		 4413static void b43_op_sta_notify(struct ieee80211_hw *hw,
4414 struct ieee80211_vif *vif,
4415 enum sta_notify_cmd notify_cmd,
17741cdc 4416 struct ieee80211_sta *sta)
38968d09
JB		 4417{
4418 struct b43_wl *wl = hw_to_b43_wl(hw);
4419
4420 B43_WARN_ON(!vif || wl->vif != vif);
4421}
4422
25d3ef59
MB		 4423static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4424{
4425 struct b43_wl *wl = hw_to_b43_wl(hw);
4426 struct b43_wldev *dev;
4427
4428 mutex_lock(&wl->mutex);
4429 dev = wl->current_dev;
4430 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4431 /* Disable CFP update during scan on other channels. */
4432 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4433 }
4434 mutex_unlock(&wl->mutex);
4435}
4436
4437static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4438{
4439 struct b43_wl *wl = hw_to_b43_wl(hw);
4440 struct b43_wldev *dev;
4441
4442 mutex_lock(&wl->mutex);
4443 dev = wl->current_dev;
4444 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4445 /* Re-enable CFP update. */
4446 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4447 }
4448 mutex_unlock(&wl->mutex);
4449}
4450
e4d6b795 4451static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4452 .tx = b43_op_tx,
4453 .conf_tx = b43_op_conf_tx,
4454 .add_interface = b43_op_add_interface,
4455 .remove_interface = b43_op_remove_interface,
4456 .config = b43_op_config,
c7ab5ef9 4457 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4458 .config_interface = b43_op_config_interface,
4459 .configure_filter = b43_op_configure_filter,
4460 .set_key = b43_op_set_key,
4461 .get_stats = b43_op_get_stats,
4462 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4463 .get_tsf = b43_op_get_tsf,
4464 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4465 .start = b43_op_start,
4466 .stop = b43_op_stop,
e66fee6a 4467 .set_tim = b43_op_beacon_set_tim,
38968d09 4468 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4469 .sw_scan_start = b43_op_sw_scan_start_notifier,
4470 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
e4d6b795
MB		 4471};
4472
4473/* Hard-reset the chip. Do not call this directly.
4474 * Use b43_controller_restart()
4475 */
4476static void b43_chip_reset(struct work_struct *work)
4477{
4478 struct b43_wldev *dev =
4479 container_of(work, struct b43_wldev, restart_work);
4480 struct b43_wl *wl = dev->wl;
4481 int err = 0;
4482 int prev_status;
4483
4484 mutex_lock(&wl->mutex);
4485
4486 prev_status = b43_status(dev);
4487 /* Bring the device down... */
4488 if (prev_status >= B43_STAT_STARTED)
4489 b43_wireless_core_stop(dev);
4490 if (prev_status >= B43_STAT_INITIALIZED)
4491 b43_wireless_core_exit(dev);
4492
4493 /* ...and up again. */
4494 if (prev_status >= B43_STAT_INITIALIZED) {
4495 err = b43_wireless_core_init(dev);
4496 if (err)
4497 goto out;
4498 }
4499 if (prev_status >= B43_STAT_STARTED) {
4500 err = b43_wireless_core_start(dev);
4501 if (err) {
4502 b43_wireless_core_exit(dev);
4503 goto out;
4504 }
4505 }
3bf0a32e
MB		 4506out:
4507 if (err)
4508 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4509 mutex_unlock(&wl->mutex);
4510 if (err)
4511 b43err(wl, "Controller restart FAILED\n");
4512 else
4513 b43info(wl, "Controller restarted\n");
4514}
4515
bb1eeff1 4516static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4517 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4518{
4519 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4520
bb1eeff1
MB		 4521 if (have_2ghz_phy)
4522 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4523 if (dev->phy.type == B43_PHYTYPE_N) {
4524 if (have_5ghz_phy)
4525 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4526 } else {
4527 if (have_5ghz_phy)
4528 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4529 }
96c755a3 4530
bb1eeff1
MB		 4531 dev->phy.supports_2ghz = have_2ghz_phy;
4532 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4533
4534 return 0;
4535}
4536
4537static void b43_wireless_core_detach(struct b43_wldev *dev)
4538{
4539 /* We release firmware that late to not be required to re-request
4540 * is all the time when we reinit the core. */
4541 b43_release_firmware(dev);
fb11137a 4542 b43_phy_free(dev);
e4d6b795
MB		 4543}
4544
4545static int b43_wireless_core_attach(struct b43_wldev *dev)
4546{
4547 struct b43_wl *wl = dev->wl;
4548 struct ssb_bus *bus = dev->dev->bus;
4549 struct pci_dev *pdev = bus->host_pci;
4550 int err;
96c755a3 4551 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4552 u32 tmp;
4553
4554 /* Do NOT do any device initialization here.
4555 * Do it in wireless_core_init() instead.
4556 * This function is for gathering basic information about the HW, only.
4557 * Also some structs may be set up here. But most likely you want to have
4558 * that in core_init(), too.
4559 */
4560
4561 err = ssb_bus_powerup(bus, 0);
4562 if (err) {
4563 b43err(wl, "Bus powerup failed\n");
4564 goto out;
4565 }
4566 /* Get the PHY type. */
4567 if (dev->dev->id.revision >= 5) {
4568 u32 tmshigh;
4569
4570 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4571 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4572 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4573 } else
96c755a3 4574 B43_WARN_ON(1);
e4d6b795 4575
96c755a3 4576 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4577 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4578 b43_wireless_core_reset(dev, tmp);
4579
4580 err = b43_phy_versioning(dev);
4581 if (err)
21954c36 4582 goto err_powerdown;
e4d6b795
MB		 4583 /* Check if this device supports multiband. */
4584 if (!pdev ||
4585 (pdev->device != 0x4312 &&
4586 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4587 /* No multiband support. */
96c755a3
MB		 4588 have_2ghz_phy = 0;
4589 have_5ghz_phy = 0;
e4d6b795
MB		 4590 switch (dev->phy.type) {
4591 case B43_PHYTYPE_A:
96c755a3 4592 have_5ghz_phy = 1;
e4d6b795
MB		 4593 break;
4594 case B43_PHYTYPE_G:
96c755a3 4595 case B43_PHYTYPE_N:
6b1c7c67 4596 case B43_PHYTYPE_LP:
96c755a3 4597 have_2ghz_phy = 1;
e4d6b795
MB		 4598 break;
4599 default:
4600 B43_WARN_ON(1);
4601 }
4602 }
96c755a3
MB		 4603 if (dev->phy.type == B43_PHYTYPE_A) {
4604 /* FIXME */
4605 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4606 err = -EOPNOTSUPP;
4607 goto err_powerdown;
4608 }
2e35af14
MB		 4609 if (1 /* disable A-PHY */) {
4610 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4611 if (dev->phy.type != B43_PHYTYPE_N) {
4612 have_2ghz_phy = 1;
4613 have_5ghz_phy = 0;
4614 }
4615 }
4616
fb11137a
MB		 4617 err = b43_phy_allocate(dev);
4618 if (err)
4619 goto err_powerdown;
4620
96c755a3 4621 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4622 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4623 b43_wireless_core_reset(dev, tmp);
4624
4625 err = b43_validate_chipaccess(dev);
4626 if (err)
fb11137a 4627 goto err_phy_free;
bb1eeff1 4628 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4629 if (err)
fb11137a 4630 goto err_phy_free;
e4d6b795
MB		 4631
4632 /* Now set some default "current_dev" */
4633 if (!wl->current_dev)
4634 wl->current_dev = dev;
4635 INIT_WORK(&dev->restart_work, b43_chip_reset);
4636
cb24f57f 4637 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4638 ssb_device_disable(dev->dev, 0);
4639 ssb_bus_may_powerdown(bus);
4640
4641out:
4642 return err;
4643
fb11137a
MB		 4644err_phy_free:
4645 b43_phy_free(dev);
e4d6b795
MB		 4646err_powerdown:
4647 ssb_bus_may_powerdown(bus);
4648 return err;
4649}
4650
4651static void b43_one_core_detach(struct ssb_device *dev)
4652{
4653 struct b43_wldev *wldev;
4654 struct b43_wl *wl;
4655
3bf0a32e
MB		 4656 /* Do not cancel ieee80211-workqueue based work here.
4657 * See comment in b43_remove(). */
4658
e4d6b795
MB		 4659 wldev = ssb_get_drvdata(dev);
4660 wl = wldev->wl;
e4d6b795
MB		 4661 b43_debugfs_remove_device(wldev);
4662 b43_wireless_core_detach(wldev);
4663 list_del(&wldev->list);
4664 wl->nr_devs--;
4665 ssb_set_drvdata(dev, NULL);
4666 kfree(wldev);
4667}
4668
4669static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4670{
4671 struct b43_wldev *wldev;
4672 struct pci_dev *pdev;
4673 int err = -ENOMEM;
4674
4675 if (!list_empty(&wl->devlist)) {
4676 /* We are not the first core on this chip. */
4677 pdev = dev->bus->host_pci;
4678 /* Only special chips support more than one wireless
4679 * core, although some of the other chips have more than
4680 * one wireless core as well. Check for this and
4681 * bail out early.
4682 */
4683 if (!pdev ||
4684 ((pdev->device != 0x4321) &&
4685 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4686 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4687 return -ENODEV;
4688 }
4689 }
4690
4691 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4692 if (!wldev)
4693 goto out;
4694
4695 wldev->dev = dev;
4696 wldev->wl = wl;
4697 b43_set_status(wldev, B43_STAT_UNINIT);
4698 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4699 tasklet_init(&wldev->isr_tasklet,
4700 (void (*)(unsigned long))b43_interrupt_tasklet,
4701 (unsigned long)wldev);
e4d6b795
MB		 4702 INIT_LIST_HEAD(&wldev->list);
4703
4704 err = b43_wireless_core_attach(wldev);
4705 if (err)
4706 goto err_kfree_wldev;
4707
4708 list_add(&wldev->list, &wl->devlist);
4709 wl->nr_devs++;
4710 ssb_set_drvdata(dev, wldev);
4711 b43_debugfs_add_device(wldev);
4712
4713 out:
4714 return err;
4715
4716 err_kfree_wldev:
4717 kfree(wldev);
4718 return err;
4719}
4720
9fc38458
MB		 4721#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4722 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4723 (pdev->device == _device) && \
4724 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4725 (pdev->subsystem_device == _subdevice) )
4726
e4d6b795
MB		 4727static void b43_sprom_fixup(struct ssb_bus *bus)
4728{
1855ba78
MB		 4729 struct pci_dev *pdev;
4730
e4d6b795
MB		 4731 /* boardflags workarounds */
4732 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4733 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4734 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4735 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4736 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4737 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4738 if (bus->bustype == SSB_BUSTYPE_PCI) {
4739 pdev = bus->host_pci;
9fc38458 4740 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4741 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4742 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4743 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4744 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4745 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4746 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4747 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4748 }
e4d6b795
MB		 4749}
4750
4751static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4752{
4753 struct ieee80211_hw *hw = wl->hw;
4754
4755 ssb_set_devtypedata(dev, NULL);
4756 ieee80211_free_hw(hw);
4757}
4758
4759static int b43_wireless_init(struct ssb_device *dev)
4760{
4761 struct ssb_sprom *sprom = &dev->bus->sprom;
4762 struct ieee80211_hw *hw;
4763 struct b43_wl *wl;
4764 int err = -ENOMEM;
4765
4766 b43_sprom_fixup(dev->bus);
4767
4768 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4769 if (!hw) {
4770 b43err(NULL, "Could not allocate ieee80211 device\n");
4771 goto out;
4772 }
4773
4774 /* fill hw info */
605a0bd6 4775 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4776 IEEE80211_HW_SIGNAL_DBM |
4777 IEEE80211_HW_NOISE_DBM;
4778
f59ac048
LR		 4779 hw->wiphy->interface_modes =
4780 BIT(NL80211_IFTYPE_AP) |
4781 BIT(NL80211_IFTYPE_MESH_POINT) |
4782 BIT(NL80211_IFTYPE_STATION) |
4783 BIT(NL80211_IFTYPE_WDS) |
4784 BIT(NL80211_IFTYPE_ADHOC);
4785
e6f5b934 4786 hw->queues = b43_modparam_qos ? 4 : 1;
e6a9854b 4787 hw->max_rates = 2;
e4d6b795 4788 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4789 if (is_valid_ether_addr(sprom->et1mac))
4790 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4791 else
95de2841 4792 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4793
4794 /* Get and initialize struct b43_wl */
4795 wl = hw_to_b43_wl(hw);
4796 memset(wl, 0, sizeof(*wl));
4797 wl->hw = hw;
4798 spin_lock_init(&wl->irq_lock);
21a75d77 4799 rwlock_init(&wl->tx_lock);
e4d6b795 4800 spin_lock_init(&wl->leds_lock);
280d0e16 4801 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4802 mutex_init(&wl->mutex);
4803 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4804 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4805 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4806
4807 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4808 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4809 dev->bus->chip_id, dev->id.revision);
e4d6b795 4810 err = 0;
060210f9 4811out:
e4d6b795
MB		 4812 return err;
4813}
4814
4815static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4816{
4817 struct b43_wl *wl;
4818 int err;
4819 int first = 0;
4820
4821 wl = ssb_get_devtypedata(dev);
4822 if (!wl) {
4823 /* Probing the first core. Must setup common struct b43_wl */
4824 first = 1;
4825 err = b43_wireless_init(dev);
4826 if (err)
4827 goto out;
4828 wl = ssb_get_devtypedata(dev);
4829 B43_WARN_ON(!wl);
4830 }
4831 err = b43_one_core_attach(dev, wl);
4832 if (err)
4833 goto err_wireless_exit;
4834
4835 if (first) {
4836 err = ieee80211_register_hw(wl->hw);
4837 if (err)
4838 goto err_one_core_detach;
4839 }
4840
4841 out:
4842 return err;
4843
4844 err_one_core_detach:
4845 b43_one_core_detach(dev);
4846 err_wireless_exit:
4847 if (first)
4848 b43_wireless_exit(dev, wl);
4849 return err;
4850}
4851
4852static void b43_remove(struct ssb_device *dev)
4853{
4854 struct b43_wl *wl = ssb_get_devtypedata(dev);
4855 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4856
3bf0a32e
MB		 4857 /* We must cancel any work here before unregistering from ieee80211,
4858 * as the ieee80211 unreg will destroy the workqueue. */
4859 cancel_work_sync(&wldev->restart_work);
4860
e4d6b795
MB		 4861 B43_WARN_ON(!wl);
4862 if (wl->current_dev == wldev)
4863 ieee80211_unregister_hw(wl->hw);
4864
4865 b43_one_core_detach(dev);
4866
4867 if (list_empty(&wl->devlist)) {
4868 /* Last core on the chip unregistered.
4869 * We can destroy common struct b43_wl.
4870 */
4871 b43_wireless_exit(dev, wl);
4872 }
4873}
4874
4875/* Perform a hardware reset. This can be called from any context. */
4876void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4877{
4878 /* Must avoid requeueing, if we are in shutdown. */
4879 if (b43_status(dev) < B43_STAT_INITIALIZED)
4880 return;
4881 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4882 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4883}
4884
4885#ifdef CONFIG_PM
4886
4887static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4888{
4889 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4890 struct b43_wl *wl = wldev->wl;
4891
4892 b43dbg(wl, "Suspending...\n");
4893
4894 mutex_lock(&wl->mutex);
3506e0c4 4895 wldev->suspend_in_progress = true;
e4d6b795
MB		 4896 wldev->suspend_init_status = b43_status(wldev);
4897 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4898 b43_wireless_core_stop(wldev);
4899 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4900 b43_wireless_core_exit(wldev);
4901 mutex_unlock(&wl->mutex);
4902
4903 b43dbg(wl, "Device suspended.\n");
4904
4905 return 0;
4906}
4907
4908static int b43_resume(struct ssb_device *dev)
4909{
4910 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4911 struct b43_wl *wl = wldev->wl;
4912 int err = 0;
4913
4914 b43dbg(wl, "Resuming...\n");
4915
4916 mutex_lock(&wl->mutex);
4917 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4918 err = b43_wireless_core_init(wldev);
4919 if (err) {
4920 b43err(wl, "Resume failed at core init\n");
4921 goto out;
4922 }
4923 }
4924 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4925 err = b43_wireless_core_start(wldev);
4926 if (err) {
3506e0c4 4927 b43_leds_exit(wldev);
b844eba2 4928 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4929 b43_wireless_core_exit(wldev);
4930 b43err(wl, "Resume failed at core start\n");
4931 goto out;
4932 }
4933 }
e4d6b795 4934 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4935 out:
4936 wldev->suspend_in_progress = false;
4937 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4938 return err;
4939}
4940
4941#else /* CONFIG_PM */
4942# define b43_suspend NULL
4943# define b43_resume NULL
4944#endif /* CONFIG_PM */
4945
4946static struct ssb_driver b43_ssb_driver = {
4947 .name = KBUILD_MODNAME,
4948 .id_table = b43_ssb_tbl,
4949 .probe = b43_probe,
4950 .remove = b43_remove,
4951 .suspend = b43_suspend,
4952 .resume = b43_resume,
4953};
4954
26bc783f
MB		 4955static void b43_print_driverinfo(void)
4956{
4957 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4958 *feat_leds = "", *feat_rfkill = "";
4959
4960#ifdef CONFIG_B43_PCI_AUTOSELECT
4961 feat_pci = "P";
4962#endif
4963#ifdef CONFIG_B43_PCMCIA
4964 feat_pcmcia = "M";
4965#endif
4966#ifdef CONFIG_B43_NPHY
4967 feat_nphy = "N";
4968#endif
4969#ifdef CONFIG_B43_LEDS
4970 feat_leds = "L";
4971#endif
4972#ifdef CONFIG_B43_RFKILL
4973 feat_rfkill = "R";
4974#endif
4975 printk(KERN_INFO "Broadcom 43xx driver loaded "
4976 "[ Features: %s%s%s%s%s, Firmware-ID: "
4977 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4978 feat_pci, feat_pcmcia, feat_nphy,
4979 feat_leds, feat_rfkill);
4980}
4981
e4d6b795
MB		 4982static int __init b43_init(void)
4983{
4984 int err;
4985
4986 b43_debugfs_init();
4987 err = b43_pcmcia_init();
4988 if (err)
4989 goto err_dfs_exit;
4990 err = ssb_driver_register(&b43_ssb_driver);
4991 if (err)
4992 goto err_pcmcia_exit;
26bc783f 4993 b43_print_driverinfo();
e4d6b795
MB		 4994
4995 return err;
4996
4997err_pcmcia_exit:
4998 b43_pcmcia_exit();
4999err_dfs_exit:
5000 b43_debugfs_exit();
5001 return err;
5002}
5003
5004static void __exit b43_exit(void)
5005{
5006 ssb_driver_unregister(&b43_ssb_driver);
5007 b43_pcmcia_exit();
5008 b43_debugfs_exit();
5009}
5010
5011module_init(b43_init)
5012module_exit(b43_exit)
Linux kernel - Deliverables
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