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b43: Suspend MAC while killing the radio
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
e6f5b934 91
e4d6b795
MB		 92static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
e4d6b795
MB		 100 SSB_DEVTABLE_END
101};
102
103MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105/* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
e4d6b795 114 }
8318d78a
JB		 115
116/*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
e4d6b795 120static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 133};
134
135#define b43_a_ratetable (__b43_ratetable + 4)
136#define b43_a_ratetable_size 8
137#define b43_b_ratetable (__b43_ratetable + 0)
138#define b43_b_ratetable_size 4
139#define b43_g_ratetable (__b43_ratetable + 0)
140#define b43_g_ratetable_size 12
141
bb1eeff1
MB		 142#define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149}
96c755a3 150static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165};
166#undef CHAN4G
167
168#define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175}
176static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 232};
233
bb1eeff1
MB		 234static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254};
255#undef CHAN5G
256
257static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
e4d6b795 263};
8318d78a 264
bb1eeff1
MB		 265static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
8318d78a 271};
e4d6b795 272
8318d78a 273static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 279};
280
e4d6b795
MB		 281static void b43_wireless_core_exit(struct b43_wldev *dev);
282static int b43_wireless_core_init(struct b43_wldev *dev);
283static void b43_wireless_core_stop(struct b43_wldev *dev);
284static int b43_wireless_core_start(struct b43_wldev *dev);
285
286static int b43_ratelimit(struct b43_wl *wl)
287{
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295}
296
297void b43info(struct b43_wl *wl, const char *fmt, ...)
298{
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308}
309
310void b43err(struct b43_wl *wl, const char *fmt, ...)
311{
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321}
322
323void b43warn(struct b43_wl *wl, const char *fmt, ...)
324{
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334}
335
336#if B43_DEBUG
337void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338{
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346}
347#endif /* DEBUG */
348
349static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350{
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362}
363
280d0e16
MB		 364static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
e4d6b795
MB		 366{
367 u32 control;
368
369 /* "offset" is the WORD offset. */
e4d6b795
MB		 370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374}
375
6bbc321a 376u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 377{
378 u32 ret;
379
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 ret <<= 16;
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
389
280d0e16 390 goto out;
e4d6b795
MB		 391 }
392 offset >>= 2;
393 }
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 396out:
e4d6b795
MB		 397 return ret;
398}
399
6bbc321a 400u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 401{
280d0e16
MB		 402 struct b43_wl *wl = dev->wl;
403 unsigned long flags;
6bbc321a 404 u32 ret;
e4d6b795 405
280d0e16 406 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
409
410 return ret;
411}
412
413u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
414{
415 u16 ret;
416
e4d6b795
MB		 417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423
280d0e16 424 goto out;
e4d6b795
MB		 425 }
426 offset >>= 2;
427 }
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 430out:
e4d6b795
MB		 431 return ret;
432}
433
6bbc321a 434u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 435{
280d0e16
MB		 436 struct b43_wl *wl = dev->wl;
437 unsigned long flags;
6bbc321a 438 u16 ret;
280d0e16
MB		 439
440 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
443
444 return ret;
445}
446
447void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
448{
e4d6b795
MB		 449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
e4d6b795 456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 458 return;
e4d6b795
MB		 459 }
460 offset >>= 2;
461 }
462 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
464}
465
6bbc321a 466void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 467{
280d0e16
MB		 468 struct b43_wl *wl = dev->wl;
469 unsigned long flags;
470
471 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
474}
475
476void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
477{
e4d6b795
MB		 478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 484 return;
e4d6b795
MB		 485 }
486 offset >>= 2;
487 }
488 b43_shm_control_word(dev, routing, offset);
e4d6b795 489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 490}
491
492void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493{
494 struct b43_wl *wl = dev->wl;
495 unsigned long flags;
496
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
280d0e16 499 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 500}
501
502/* Read HostFlags */
35f0d354 503u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 504{
35f0d354 505 u64 ret;
e4d6b795
MB		 506
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
508 ret <<= 16;
35f0d354
MB		 509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
510 ret <<= 16;
e4d6b795
MB		 511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
512
513 return ret;
514}
515
516/* Write HostFlags */
35f0d354 517void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 518{
35f0d354
MB		 519 u16 lo, mi, hi;
520
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 527}
528
529void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
530{
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
536 */
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
539
540 do {
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
545
546 *tsf = high;
547 *tsf <<= 32;
548 *tsf |= low;
549 } else {
550 u64 tmp;
551 u16 v0, v1, v2, v3;
552 u16 test1, test2, test3;
553
554 do {
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
559
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
564
565 *tsf = v3;
566 *tsf <<= 48;
567 tmp = v2;
568 tmp <<= 32;
569 *tsf |= tmp;
570 tmp = v1;
571 tmp <<= 16;
572 *tsf |= tmp;
573 *tsf |= v0;
574 }
575}
576
577static void b43_time_lock(struct b43_wldev *dev)
578{
579 u32 macctl;
580
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586}
587
588static void b43_time_unlock(struct b43_wldev *dev)
589{
590 u32 macctl;
591
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
597}
598
599static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
600{
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
604 */
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
608
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
610 mmiowb();
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
614 } else {
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
619
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
621 mmiowb();
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
623 mmiowb();
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
625 mmiowb();
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
627 mmiowb();
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
629 }
630}
631
632void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
633{
634 b43_time_lock(dev);
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
637}
638
639static
640void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
641{
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
643 u16 data;
644
645 if (!mac)
646 mac = zero_addr;
647
648 offset |= 0x0020;
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
650
651 data = mac[0];
652 data |= mac[1] << 8;
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
654 data = mac[2];
655 data |= mac[3] << 8;
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
657 data = mac[4];
658 data |= mac[5] << 8;
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
660}
661
662static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
663{
664 const u8 *mac;
665 const u8 *bssid;
666 u8 mac_bssid[ETH_ALEN * 2];
667 int i;
668 u32 tmp;
669
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
672
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
674
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
677
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
685 }
686}
687
4150c572 688static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 689{
e4d6b795 690 b43_write_mac_bssid_templates(dev);
4150c572 691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 692}
693
694static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
695{
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
698 return;
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
701}
702
703static void b43_short_slot_timing_enable(struct b43_wldev *dev)
704{
705 b43_set_slot_time(dev, 9);
e4d6b795
MB		 706}
707
708static void b43_short_slot_timing_disable(struct b43_wldev *dev)
709{
710 b43_set_slot_time(dev, 20);
e4d6b795
MB		 711}
712
713/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
714 * Returns the _previously_ enabled IRQ mask.
715 */
716static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
717{
718 u32 old_mask;
719
720 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
721 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
722
723 return old_mask;
724}
725
726/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
727 * Returns the _previously_ enabled IRQ mask.
728 */
729static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
730{
731 u32 old_mask;
732
733 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
734 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
735
736 return old_mask;
737}
738
739/* Synchronize IRQ top- and bottom-half.
740 * IRQs must be masked before calling this.
741 * This must not be called with the irq_lock held.
742 */
743static void b43_synchronize_irq(struct b43_wldev *dev)
744{
745 synchronize_irq(dev->dev->irq);
746 tasklet_kill(&dev->isr_tasklet);
747}
748
749/* DummyTransmission function, as documented on
750 * http://bcm-specs.sipsolutions.net/DummyTransmission
751 */
752void b43_dummy_transmission(struct b43_wldev *dev)
753{
21a75d77 754 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 755 struct b43_phy *phy = &dev->phy;
756 unsigned int i, max_loop;
757 u16 value;
758 u32 buffer[5] = {
759 0x00000000,
760 0x00D40000,
761 0x00000000,
762 0x01000000,
763 0x00000000,
764 };
765
766 switch (phy->type) {
767 case B43_PHYTYPE_A:
768 max_loop = 0x1E;
769 buffer[0] = 0x000201CC;
770 break;
771 case B43_PHYTYPE_B:
772 case B43_PHYTYPE_G:
773 max_loop = 0xFA;
774 buffer[0] = 0x000B846E;
775 break;
776 default:
777 B43_WARN_ON(1);
778 return;
779 }
780
21a75d77
MB		 781 spin_lock_irq(&wl->irq_lock);
782 write_lock(&wl->tx_lock);
783
e4d6b795
MB		 784 for (i = 0; i < 5; i++)
785 b43_ram_write(dev, i * 4, buffer[i]);
786
787 /* Commit writes */
788 b43_read32(dev, B43_MMIO_MACCTL);
789
790 b43_write16(dev, 0x0568, 0x0000);
791 b43_write16(dev, 0x07C0, 0x0000);
792 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
793 b43_write16(dev, 0x050C, value);
794 b43_write16(dev, 0x0508, 0x0000);
795 b43_write16(dev, 0x050A, 0x0000);
796 b43_write16(dev, 0x054C, 0x0000);
797 b43_write16(dev, 0x056A, 0x0014);
798 b43_write16(dev, 0x0568, 0x0826);
799 b43_write16(dev, 0x0500, 0x0000);
800 b43_write16(dev, 0x0502, 0x0030);
801
802 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
803 b43_radio_write16(dev, 0x0051, 0x0017);
804 for (i = 0x00; i < max_loop; i++) {
805 value = b43_read16(dev, 0x050E);
806 if (value & 0x0080)
807 break;
808 udelay(10);
809 }
810 for (i = 0x00; i < 0x0A; i++) {
811 value = b43_read16(dev, 0x050E);
812 if (value & 0x0400)
813 break;
814 udelay(10);
815 }
1d280ddc 816 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 817 value = b43_read16(dev, 0x0690);
818 if (!(value & 0x0100))
819 break;
820 udelay(10);
821 }
822 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
823 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 824
825 write_unlock(&wl->tx_lock);
826 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 827}
828
829static void key_write(struct b43_wldev *dev,
830 u8 index, u8 algorithm, const u8 * key)
831{
832 unsigned int i;
833 u32 offset;
834 u16 value;
835 u16 kidx;
836
837 /* Key index/algo block */
838 kidx = b43_kidx_to_fw(dev, index);
839 value = ((kidx << 4) | algorithm);
840 b43_shm_write16(dev, B43_SHM_SHARED,
841 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
842
843 /* Write the key to the Key Table Pointer offset */
844 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
845 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
846 value = key[i];
847 value |= (u16) (key[i + 1]) << 8;
848 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
849 }
850}
851
852static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
853{
854 u32 addrtmp[2] = { 0, 0, };
855 u8 per_sta_keys_start = 8;
856
857 if (b43_new_kidx_api(dev))
858 per_sta_keys_start = 4;
859
860 B43_WARN_ON(index < per_sta_keys_start);
861 /* We have two default TX keys and possibly two default RX keys.
862 * Physical mac 0 is mapped to physical key 4 or 8, depending
863 * on the firmware version.
864 * So we must adjust the index here.
865 */
866 index -= per_sta_keys_start;
867
868 if (addr) {
869 addrtmp[0] = addr[0];
870 addrtmp[0] |= ((u32) (addr[1]) << 8);
871 addrtmp[0] |= ((u32) (addr[2]) << 16);
872 addrtmp[0] |= ((u32) (addr[3]) << 24);
873 addrtmp[1] = addr[4];
874 addrtmp[1] |= ((u32) (addr[5]) << 8);
875 }
876
877 if (dev->dev->id.revision >= 5) {
878 /* Receive match transmitter address mechanism */
879 b43_shm_write32(dev, B43_SHM_RCMTA,
880 (index * 2) + 0, addrtmp[0]);
881 b43_shm_write16(dev, B43_SHM_RCMTA,
882 (index * 2) + 1, addrtmp[1]);
883 } else {
884 /* RXE (Receive Engine) and
885 * PSM (Programmable State Machine) mechanism
886 */
887 if (index < 8) {
888 /* TODO write to RCM 16, 19, 22 and 25 */
889 } else {
890 b43_shm_write32(dev, B43_SHM_SHARED,
891 B43_SHM_SH_PSM + (index * 6) + 0,
892 addrtmp[0]);
893 b43_shm_write16(dev, B43_SHM_SHARED,
894 B43_SHM_SH_PSM + (index * 6) + 4,
895 addrtmp[1]);
896 }
897 }
898}
899
900static void do_key_write(struct b43_wldev *dev,
901 u8 index, u8 algorithm,
902 const u8 * key, size_t key_len, const u8 * mac_addr)
903{
904 u8 buf[B43_SEC_KEYSIZE] = { 0, };
905 u8 per_sta_keys_start = 8;
906
907 if (b43_new_kidx_api(dev))
908 per_sta_keys_start = 4;
909
910 B43_WARN_ON(index >= dev->max_nr_keys);
911 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
912
913 if (index >= per_sta_keys_start)
914 keymac_write(dev, index, NULL); /* First zero out mac. */
915 if (key)
916 memcpy(buf, key, key_len);
917 key_write(dev, index, algorithm, buf);
918 if (index >= per_sta_keys_start)
919 keymac_write(dev, index, mac_addr);
920
921 dev->key[index].algorithm = algorithm;
922}
923
924static int b43_key_write(struct b43_wldev *dev,
925 int index, u8 algorithm,
926 const u8 * key, size_t key_len,
927 const u8 * mac_addr,
928 struct ieee80211_key_conf *keyconf)
929{
930 int i;
931 int sta_keys_start;
932
933 if (key_len > B43_SEC_KEYSIZE)
934 return -EINVAL;
935 for (i = 0; i < dev->max_nr_keys; i++) {
936 /* Check that we don't already have this key. */
937 B43_WARN_ON(dev->key[i].keyconf == keyconf);
938 }
939 if (index < 0) {
940 /* Either pairwise key or address is 00:00:00:00:00:00
941 * for transmit-only keys. Search the index. */
942 if (b43_new_kidx_api(dev))
943 sta_keys_start = 4;
944 else
945 sta_keys_start = 8;
946 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
947 if (!dev->key[i].keyconf) {
948 /* found empty */
949 index = i;
950 break;
951 }
952 }
953 if (index < 0) {
954 b43err(dev->wl, "Out of hardware key memory\n");
955 return -ENOSPC;
956 }
957 } else
958 B43_WARN_ON(index > 3);
959
960 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
961 if ((index <= 3) && !b43_new_kidx_api(dev)) {
962 /* Default RX key */
963 B43_WARN_ON(mac_addr);
964 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
965 }
966 keyconf->hw_key_idx = index;
967 dev->key[index].keyconf = keyconf;
968
969 return 0;
970}
971
972static int b43_key_clear(struct b43_wldev *dev, int index)
973{
974 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
975 return -EINVAL;
976 do_key_write(dev, index, B43_SEC_ALGO_NONE,
977 NULL, B43_SEC_KEYSIZE, NULL);
978 if ((index <= 3) && !b43_new_kidx_api(dev)) {
979 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
980 NULL, B43_SEC_KEYSIZE, NULL);
981 }
982 dev->key[index].keyconf = NULL;
983
984 return 0;
985}
986
987static void b43_clear_keys(struct b43_wldev *dev)
988{
989 int i;
990
991 for (i = 0; i < dev->max_nr_keys; i++)
992 b43_key_clear(dev, i);
993}
994
995void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
996{
997 u32 macctl;
998 u16 ucstat;
999 bool hwps;
1000 bool awake;
1001 int i;
1002
1003 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1004 (ps_flags & B43_PS_DISABLED));
1005 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1006
1007 if (ps_flags & B43_PS_ENABLED) {
1008 hwps = 1;
1009 } else if (ps_flags & B43_PS_DISABLED) {
1010 hwps = 0;
1011 } else {
1012 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1013 // and thus is not an AP and we are associated, set bit 25
1014 }
1015 if (ps_flags & B43_PS_AWAKE) {
1016 awake = 1;
1017 } else if (ps_flags & B43_PS_ASLEEP) {
1018 awake = 0;
1019 } else {
1020 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1021 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1022 // successful, set bit26
1023 }
1024
1025/* FIXME: For now we force awake-on and hwps-off */
1026 hwps = 0;
1027 awake = 1;
1028
1029 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1030 if (hwps)
1031 macctl |= B43_MACCTL_HWPS;
1032 else
1033 macctl &= ~B43_MACCTL_HWPS;
1034 if (awake)
1035 macctl |= B43_MACCTL_AWAKE;
1036 else
1037 macctl &= ~B43_MACCTL_AWAKE;
1038 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1039 /* Commit write */
1040 b43_read32(dev, B43_MMIO_MACCTL);
1041 if (awake && dev->dev->id.revision >= 5) {
1042 /* Wait for the microcode to wake up. */
1043 for (i = 0; i < 100; i++) {
1044 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1045 B43_SHM_SH_UCODESTAT);
1046 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1047 break;
1048 udelay(10);
1049 }
1050 }
1051}
1052
e4d6b795
MB		 1053void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1054{
1055 u32 tmslow;
1056 u32 macctl;
1057
1058 flags |= B43_TMSLOW_PHYCLKEN;
1059 flags |= B43_TMSLOW_PHYRESET;
1060 ssb_device_enable(dev->dev, flags);
1061 msleep(2); /* Wait for the PLL to turn on. */
1062
1063 /* Now take the PHY out of Reset again */
1064 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1065 tmslow |= SSB_TMSLOW_FGC;
1066 tmslow &= ~B43_TMSLOW_PHYRESET;
1067 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1068 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1069 msleep(1);
1070 tmslow &= ~SSB_TMSLOW_FGC;
1071 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1072 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1073 msleep(1);
1074
fb11137a
MB		 1075 /* Turn Analog ON, but only if we already know the PHY-type.
1076 * This protects against very early setup where we don't know the
1077 * PHY-type, yet. wireless_core_reset will be called once again later,
1078 * when we know the PHY-type. */
1079 if (dev->phy.ops)
cb24f57f 1080 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1081
1082 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1083 macctl &= ~B43_MACCTL_GMODE;
1084 if (flags & B43_TMSLOW_GMODE)
1085 macctl |= B43_MACCTL_GMODE;
1086 macctl |= B43_MACCTL_IHR_ENABLED;
1087 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1088}
1089
1090static void handle_irq_transmit_status(struct b43_wldev *dev)
1091{
1092 u32 v0, v1;
1093 u16 tmp;
1094 struct b43_txstatus stat;
1095
1096 while (1) {
1097 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1098 if (!(v0 & 0x00000001))
1099 break;
1100 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1101
1102 stat.cookie = (v0 >> 16);
1103 stat.seq = (v1 & 0x0000FFFF);
1104 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1105 tmp = (v0 & 0x0000FFFF);
1106 stat.frame_count = ((tmp & 0xF000) >> 12);
1107 stat.rts_count = ((tmp & 0x0F00) >> 8);
1108 stat.supp_reason = ((tmp & 0x001C) >> 2);
1109 stat.pm_indicated = !!(tmp & 0x0080);
1110 stat.intermediate = !!(tmp & 0x0040);
1111 stat.for_ampdu = !!(tmp & 0x0020);
1112 stat.acked = !!(tmp & 0x0002);
1113
1114 b43_handle_txstatus(dev, &stat);
1115 }
1116}
1117
1118static void drain_txstatus_queue(struct b43_wldev *dev)
1119{
1120 u32 dummy;
1121
1122 if (dev->dev->id.revision < 5)
1123 return;
1124 /* Read all entries from the microcode TXstatus FIFO
1125 * and throw them away.
1126 */
1127 while (1) {
1128 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1129 if (!(dummy & 0x00000001))
1130 break;
1131 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1132 }
1133}
1134
1135static u32 b43_jssi_read(struct b43_wldev *dev)
1136{
1137 u32 val = 0;
1138
1139 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1140 val <<= 16;
1141 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1142
1143 return val;
1144}
1145
1146static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1147{
1148 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1149 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1150}
1151
1152static void b43_generate_noise_sample(struct b43_wldev *dev)
1153{
1154 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1155 b43_write32(dev, B43_MMIO_MACCMD,
1156 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1157}
1158
1159static void b43_calculate_link_quality(struct b43_wldev *dev)
1160{
1161 /* Top half of Link Quality calculation. */
1162
ef1a628d
MB		 1163 if (dev->phy.type != B43_PHYTYPE_G)
1164 return;
e4d6b795
MB		 1165 if (dev->noisecalc.calculation_running)
1166 return;
e4d6b795
MB		 1167 dev->noisecalc.calculation_running = 1;
1168 dev->noisecalc.nr_samples = 0;
1169
1170 b43_generate_noise_sample(dev);
1171}
1172
1173static void handle_irq_noise(struct b43_wldev *dev)
1174{
ef1a628d 1175 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1176 u16 tmp;
1177 u8 noise[4];
1178 u8 i, j;
1179 s32 average;
1180
1181 /* Bottom half of Link Quality calculation. */
1182
ef1a628d
MB		 1183 if (dev->phy.type != B43_PHYTYPE_G)
1184 return;
1185
98a3b2fe
MB		 1186 /* Possible race condition: It might be possible that the user
1187 * changed to a different channel in the meantime since we
1188 * started the calculation. We ignore that fact, since it's
1189 * not really that much of a problem. The background noise is
1190 * an estimation only anyway. Slightly wrong results will get damped
1191 * by the averaging of the 8 sample rounds. Additionally the
1192 * value is shortlived. So it will be replaced by the next noise
1193 * calculation round soon. */
1194
e4d6b795 1195 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1196 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1197 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1198 noise[2] == 0x7F || noise[3] == 0x7F)
1199 goto generate_new;
1200
1201 /* Get the noise samples. */
1202 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1203 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1204 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1205 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1206 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1207 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1208 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1209 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1210 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1211 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1212 dev->noisecalc.nr_samples++;
1213 if (dev->noisecalc.nr_samples == 8) {
1214 /* Calculate the Link Quality by the noise samples. */
1215 average = 0;
1216 for (i = 0; i < 8; i++) {
1217 for (j = 0; j < 4; j++)
1218 average += dev->noisecalc.samples[i][j];
1219 }
1220 average /= (8 * 4);
1221 average *= 125;
1222 average += 64;
1223 average /= 128;
1224 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1225 tmp = (tmp / 128) & 0x1F;
1226 if (tmp >= 8)
1227 average += 2;
1228 else
1229 average -= 25;
1230 if (tmp == 8)
1231 average -= 72;
1232 else
1233 average -= 48;
1234
1235 dev->stats.link_noise = average;
e4d6b795
MB		 1236 dev->noisecalc.calculation_running = 0;
1237 return;
1238 }
98a3b2fe 1239generate_new:
e4d6b795
MB		 1240 b43_generate_noise_sample(dev);
1241}
1242
1243static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1244{
05c914fe 1245 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1246 ///TODO: PS TBTT
1247 } else {
1248 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1249 b43_power_saving_ctl_bits(dev, 0);
1250 }
05c914fe 1251 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1252 dev->dfq_valid = 1;
e4d6b795
MB		 1253}
1254
1255static void handle_irq_atim_end(struct b43_wldev *dev)
1256{
aa6c7ae2
MB		 1257 if (dev->dfq_valid) {
1258 b43_write32(dev, B43_MMIO_MACCMD,
1259 b43_read32(dev, B43_MMIO_MACCMD)
1260 | B43_MACCMD_DFQ_VALID);
1261 dev->dfq_valid = 0;
1262 }
e4d6b795
MB		 1263}
1264
1265static void handle_irq_pmq(struct b43_wldev *dev)
1266{
1267 u32 tmp;
1268
1269 //TODO: AP mode.
1270
1271 while (1) {
1272 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1273 if (!(tmp & 0x00000008))
1274 break;
1275 }
1276 /* 16bit write is odd, but correct. */
1277 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1278}
1279
1280static void b43_write_template_common(struct b43_wldev *dev,
1281 const u8 * data, u16 size,
1282 u16 ram_offset,
1283 u16 shm_size_offset, u8 rate)
1284{
1285 u32 i, tmp;
1286 struct b43_plcp_hdr4 plcp;
1287
1288 plcp.data = 0;
1289 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1290 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1291 ram_offset += sizeof(u32);
1292 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1293 * So leave the first two bytes of the next write blank.
1294 */
1295 tmp = (u32) (data[0]) << 16;
1296 tmp |= (u32) (data[1]) << 24;
1297 b43_ram_write(dev, ram_offset, tmp);
1298 ram_offset += sizeof(u32);
1299 for (i = 2; i < size; i += sizeof(u32)) {
1300 tmp = (u32) (data[i + 0]);
1301 if (i + 1 < size)
1302 tmp |= (u32) (data[i + 1]) << 8;
1303 if (i + 2 < size)
1304 tmp |= (u32) (data[i + 2]) << 16;
1305 if (i + 3 < size)
1306 tmp |= (u32) (data[i + 3]) << 24;
1307 b43_ram_write(dev, ram_offset + i - 2, tmp);
1308 }
1309 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1310 size + sizeof(struct b43_plcp_hdr6));
1311}
1312
5042c507
MB		 1313/* Check if the use of the antenna that ieee80211 told us to
1314 * use is possible. This will fall back to DEFAULT.
1315 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1316u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1317 u8 antenna_nr)
1318{
1319 u8 antenna_mask;
1320
1321 if (antenna_nr == 0) {
1322 /* Zero means "use default antenna". That's always OK. */
1323 return 0;
1324 }
1325
1326 /* Get the mask of available antennas. */
1327 if (dev->phy.gmode)
1328 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1329 else
1330 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1331
1332 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1333 /* This antenna is not available. Fall back to default. */
1334 return 0;
1335 }
1336
1337 return antenna_nr;
1338}
1339
5042c507
MB		 1340/* Convert a b43 antenna number value to the PHY TX control value. */
1341static u16 b43_antenna_to_phyctl(int antenna)
1342{
1343 switch (antenna) {
1344 case B43_ANTENNA0:
1345 return B43_TXH_PHY_ANT0;
1346 case B43_ANTENNA1:
1347 return B43_TXH_PHY_ANT1;
1348 case B43_ANTENNA2:
1349 return B43_TXH_PHY_ANT2;
1350 case B43_ANTENNA3:
1351 return B43_TXH_PHY_ANT3;
1352 case B43_ANTENNA_AUTO:
1353 return B43_TXH_PHY_ANT01AUTO;
1354 }
1355 B43_WARN_ON(1);
1356 return 0;
1357}
1358
e4d6b795
MB		 1359static void b43_write_beacon_template(struct b43_wldev *dev,
1360 u16 ram_offset,
5042c507 1361 u16 shm_size_offset)
e4d6b795 1362{
47f76ca3 1363 unsigned int i, len, variable_len;
e66fee6a
MB		 1364 const struct ieee80211_mgmt *bcn;
1365 const u8 *ie;
1366 bool tim_found = 0;
5042c507
MB		 1367 unsigned int rate;
1368 u16 ctl;
1369 int antenna;
e039fa4a 1370 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1371
e66fee6a
MB		 1372 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1373 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1374 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1375 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1376
1377 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1378 len, ram_offset, shm_size_offset, rate);
e66fee6a 1379
5042c507 1380 /* Write the PHY TX control parameters. */
0f4ac38b 1381 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1382 antenna = b43_antenna_to_phyctl(antenna);
1383 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1384 /* We can't send beacons with short preamble. Would get PHY errors. */
1385 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1386 ctl &= ~B43_TXH_PHY_ANT;
1387 ctl &= ~B43_TXH_PHY_ENC;
1388 ctl |= antenna;
1389 if (b43_is_cck_rate(rate))
1390 ctl |= B43_TXH_PHY_ENC_CCK;
1391 else
1392 ctl |= B43_TXH_PHY_ENC_OFDM;
1393 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1394
e66fee6a
MB		 1395 /* Find the position of the TIM and the DTIM_period value
1396 * and write them to SHM. */
1397 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1398 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1399 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1400 uint8_t ie_id, ie_len;
1401
1402 ie_id = ie[i];
1403 ie_len = ie[i + 1];
1404 if (ie_id == 5) {
1405 u16 tim_position;
1406 u16 dtim_period;
1407 /* This is the TIM Information Element */
1408
1409 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1410 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1411 break;
1412 /* A valid TIM is at least 4 bytes long. */
1413 if (ie_len < 4)
1414 break;
1415 tim_found = 1;
1416
1417 tim_position = sizeof(struct b43_plcp_hdr6);
1418 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1419 tim_position += i;
1420
1421 dtim_period = ie[i + 3];
1422
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1424 B43_SHM_SH_TIMBPOS, tim_position);
1425 b43_shm_write16(dev, B43_SHM_SHARED,
1426 B43_SHM_SH_DTIMPER, dtim_period);
1427 break;
1428 }
1429 i += ie_len + 2;
1430 }
1431 if (!tim_found) {
04dea136
JB		 1432 /*
1433 * If ucode wants to modify TIM do it behind the beacon, this
1434 * will happen, for example, when doing mesh networking.
1435 */
1436 b43_shm_write16(dev, B43_SHM_SHARED,
1437 B43_SHM_SH_TIMBPOS,
1438 len + sizeof(struct b43_plcp_hdr6));
1439 b43_shm_write16(dev, B43_SHM_SHARED,
1440 B43_SHM_SH_DTIMPER, 0);
1441 }
1442 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1443}
1444
1445static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1446 u16 shm_offset, u16 size,
1447 struct ieee80211_rate *rate)
e4d6b795
MB		 1448{
1449 struct b43_plcp_hdr4 plcp;
1450 u32 tmp;
1451 __le16 dur;
1452
1453 plcp.data = 0;
8318d78a 1454 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1455 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1456 dev->wl->vif, size,
8318d78a 1457 rate);
e4d6b795
MB		 1458 /* Write PLCP in two parts and timing for packet transfer */
1459 tmp = le32_to_cpu(plcp.data);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1461 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1462 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1463}
1464
1465/* Instead of using custom probe response template, this function
1466 * just patches custom beacon template by:
1467 * 1) Changing packet type
1468 * 2) Patching duration field
1469 * 3) Stripping TIM
1470 */
e66fee6a 1471static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1472 u16 *dest_size,
1473 struct ieee80211_rate *rate)
e4d6b795
MB		 1474{
1475 const u8 *src_data;
1476 u8 *dest_data;
1477 u16 src_size, elem_size, src_pos, dest_pos;
1478 __le16 dur;
1479 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1480 size_t ie_start;
1481
1482 src_size = dev->wl->current_beacon->len;
1483 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1484
e66fee6a
MB		 1485 /* Get the start offset of the variable IEs in the packet. */
1486 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1487 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1488
e66fee6a 1489 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1490 return NULL;
e4d6b795
MB		 1491
1492 dest_data = kmalloc(src_size, GFP_ATOMIC);
1493 if (unlikely(!dest_data))
1494 return NULL;
1495
e66fee6a
MB		 1496 /* Copy the static data and all Information Elements, except the TIM. */
1497 memcpy(dest_data, src_data, ie_start);
1498 src_pos = ie_start;
1499 dest_pos = ie_start;
1500 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1501 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1502 if (src_data[src_pos] == 5) {
1503 /* This is the TIM. */
1504 continue;
e4d6b795 1505 }
e66fee6a
MB		 1506 memcpy(dest_data + dest_pos, src_data + src_pos,
1507 elem_size);
1508 dest_pos += elem_size;
e4d6b795
MB		 1509 }
1510 *dest_size = dest_pos;
1511 hdr = (struct ieee80211_hdr *)dest_data;
1512
1513 /* Set the frame control. */
1514 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1515 IEEE80211_STYPE_PROBE_RESP);
1516 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1517 dev->wl->vif, *dest_size,
8318d78a 1518 rate);
e4d6b795
MB		 1519 hdr->duration_id = dur;
1520
1521 return dest_data;
1522}
1523
1524static void b43_write_probe_resp_template(struct b43_wldev *dev,
1525 u16 ram_offset,
8318d78a
JB		 1526 u16 shm_size_offset,
1527 struct ieee80211_rate *rate)
e4d6b795 1528{
e66fee6a 1529 const u8 *probe_resp_data;
e4d6b795
MB		 1530 u16 size;
1531
e66fee6a 1532 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1533 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1534 if (unlikely(!probe_resp_data))
1535 return;
1536
1537 /* Looks like PLCP headers plus packet timings are stored for
1538 * all possible basic rates
1539 */
8318d78a
JB		 1540 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1541 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1542 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1543 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1544
1545 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1546 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1547 size, ram_offset, shm_size_offset,
1548 rate->hw_value);
e4d6b795
MB		 1549 kfree(probe_resp_data);
1550}
1551
6b4bec01
MB		 1552static void b43_upload_beacon0(struct b43_wldev *dev)
1553{
1554 struct b43_wl *wl = dev->wl;
1555
1556 if (wl->beacon0_uploaded)
1557 return;
1558 b43_write_beacon_template(dev, 0x68, 0x18);
1559 /* FIXME: Probe resp upload doesn't really belong here,
1560 * but we don't use that feature anyway. */
1561 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1562 &__b43_ratetable[3]);
1563 wl->beacon0_uploaded = 1;
1564}
1565
1566static void b43_upload_beacon1(struct b43_wldev *dev)
1567{
1568 struct b43_wl *wl = dev->wl;
1569
1570 if (wl->beacon1_uploaded)
1571 return;
1572 b43_write_beacon_template(dev, 0x468, 0x1A);
1573 wl->beacon1_uploaded = 1;
1574}
1575
c97a4ccc
MB		 1576static void handle_irq_beacon(struct b43_wldev *dev)
1577{
1578 struct b43_wl *wl = dev->wl;
1579 u32 cmd, beacon0_valid, beacon1_valid;
1580
05c914fe
JB		 1581 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1582 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1583 return;
1584
1585 /* This is the bottom half of the asynchronous beacon update. */
1586
1587 /* Ignore interrupt in the future. */
1588 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1589
1590 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1591 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1592 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1593
1594 /* Schedule interrupt manually, if busy. */
1595 if (beacon0_valid && beacon1_valid) {
1596 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1597 dev->irq_savedstate |= B43_IRQ_BEACON;
1598 return;
1599 }
1600
6b4bec01
MB		 1601 if (unlikely(wl->beacon_templates_virgin)) {
1602 /* We never uploaded a beacon before.
1603 * Upload both templates now, but only mark one valid. */
1604 wl->beacon_templates_virgin = 0;
1605 b43_upload_beacon0(dev);
1606 b43_upload_beacon1(dev);
c97a4ccc
MB		 1607 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1608 cmd |= B43_MACCMD_BEACON0_VALID;
1609 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1610 } else {
1611 if (!beacon0_valid) {
1612 b43_upload_beacon0(dev);
1613 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1614 cmd |= B43_MACCMD_BEACON0_VALID;
1615 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1616 } else if (!beacon1_valid) {
1617 b43_upload_beacon1(dev);
1618 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1619 cmd |= B43_MACCMD_BEACON1_VALID;
1620 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1621 }
c97a4ccc
MB		 1622 }
1623}
1624
a82d9922
MB		 1625static void b43_beacon_update_trigger_work(struct work_struct *work)
1626{
1627 struct b43_wl *wl = container_of(work, struct b43_wl,
1628 beacon_update_trigger);
1629 struct b43_wldev *dev;
1630
1631 mutex_lock(&wl->mutex);
1632 dev = wl->current_dev;
1633 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1634 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1635 /* update beacon right away or defer to irq */
1636 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1637 handle_irq_beacon(dev);
1638 /* The handler might have updated the IRQ mask. */
1639 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1640 dev->irq_savedstate);
1641 mmiowb();
a82d9922
MB		 1642 spin_unlock_irq(&wl->irq_lock);
1643 }
1644 mutex_unlock(&wl->mutex);
1645}
1646
d4df6f1a
MB		 1647/* Asynchronously update the packet templates in template RAM.
1648 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1649static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1650{
9d139c81
JB		 1651 struct sk_buff *beacon;
1652
e66fee6a
MB		 1653 /* This is the top half of the ansynchronous beacon update.
1654 * The bottom half is the beacon IRQ.
1655 * Beacon update must be asynchronous to avoid sending an
1656 * invalid beacon. This can happen for example, if the firmware
1657 * transmits a beacon while we are updating it. */
e4d6b795 1658
9d139c81
JB		 1659 /* We could modify the existing beacon and set the aid bit in
1660 * the TIM field, but that would probably require resizing and
1661 * moving of data within the beacon template.
1662 * Simply request a new beacon and let mac80211 do the hard work. */
1663 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1664 if (unlikely(!beacon))
1665 return;
1666
e66fee6a
MB		 1667 if (wl->current_beacon)
1668 dev_kfree_skb_any(wl->current_beacon);
1669 wl->current_beacon = beacon;
1670 wl->beacon0_uploaded = 0;
1671 wl->beacon1_uploaded = 0;
a82d9922 1672 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1673}
1674
e4d6b795
MB		 1675static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1676{
1677 b43_time_lock(dev);
1678 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1679 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1680 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1681 } else {
1682 b43_write16(dev, 0x606, (beacon_int >> 6));
1683 b43_write16(dev, 0x610, beacon_int);
1684 }
1685 b43_time_unlock(dev);
a82d9922 1686 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1687}
1688
afa83e23
MB		 1689static void b43_handle_firmware_panic(struct b43_wldev *dev)
1690{
1691 u16 reason;
1692
1693 /* Read the register that contains the reason code for the panic. */
1694 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1695 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1696
1697 switch (reason) {
1698 default:
1699 b43dbg(dev->wl, "The panic reason is unknown.\n");
1700 /* fallthrough */
1701 case B43_FWPANIC_DIE:
1702 /* Do not restart the controller or firmware.
1703 * The device is nonfunctional from now on.
1704 * Restarting would result in this panic to trigger again,
1705 * so we avoid that recursion. */
1706 break;
1707 case B43_FWPANIC_RESTART:
1708 b43_controller_restart(dev, "Microcode panic");
1709 break;
1710 }
1711}
1712
e4d6b795
MB		 1713static void handle_irq_ucode_debug(struct b43_wldev *dev)
1714{
e48b0eeb 1715 unsigned int i, cnt;
53c06856 1716 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1717 __le16 *buf;
1718
1719 /* The proprietary firmware doesn't have this IRQ. */
1720 if (!dev->fw.opensource)
1721 return;
1722
afa83e23
MB		 1723 /* Read the register that contains the reason code for this IRQ. */
1724 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1725
e48b0eeb
MB		 1726 switch (reason) {
1727 case B43_DEBUGIRQ_PANIC:
afa83e23 1728 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1729 break;
1730 case B43_DEBUGIRQ_DUMP_SHM:
1731 if (!B43_DEBUG)
1732 break; /* Only with driver debugging enabled. */
1733 buf = kmalloc(4096, GFP_ATOMIC);
1734 if (!buf) {
1735 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1736 goto out;
1737 }
1738 for (i = 0; i < 4096; i += 2) {
1739 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1740 buf[i / 2] = cpu_to_le16(tmp);
1741 }
1742 b43info(dev->wl, "Shared memory dump:\n");
1743 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1744 16, 2, buf, 4096, 1);
1745 kfree(buf);
1746 break;
1747 case B43_DEBUGIRQ_DUMP_REGS:
1748 if (!B43_DEBUG)
1749 break; /* Only with driver debugging enabled. */
1750 b43info(dev->wl, "Microcode register dump:\n");
1751 for (i = 0, cnt = 0; i < 64; i++) {
1752 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1753 if (cnt == 0)
1754 printk(KERN_INFO);
1755 printk("r%02u: 0x%04X ", i, tmp);
1756 cnt++;
1757 if (cnt == 6) {
1758 printk("\n");
1759 cnt = 0;
1760 }
1761 }
1762 printk("\n");
1763 break;
53c06856
MB		 1764 case B43_DEBUGIRQ_MARKER:
1765 if (!B43_DEBUG)
1766 break; /* Only with driver debugging enabled. */
1767 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1768 B43_MARKER_ID_REG);
1769 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1770 B43_MARKER_LINE_REG);
1771 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1772 "at line number %u\n",
1773 marker_id, marker_line);
1774 break;
e48b0eeb
MB		 1775 default:
1776 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1777 reason);
1778 }
1779out:
afa83e23
MB		 1780 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1781 b43_shm_write16(dev, B43_SHM_SCRATCH,
1782 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1783}
1784
1785/* Interrupt handler bottom-half */
1786static void b43_interrupt_tasklet(struct b43_wldev *dev)
1787{
1788 u32 reason;
1789 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1790 u32 merged_dma_reason = 0;
21954c36 1791 int i;
e4d6b795
MB		 1792 unsigned long flags;
1793
1794 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1795
1796 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1797
1798 reason = dev->irq_reason;
1799 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1800 dma_reason[i] = dev->dma_reason[i];
1801 merged_dma_reason |= dma_reason[i];
1802 }
1803
1804 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1805 b43err(dev->wl, "MAC transmission error\n");
1806
00e0b8cb 1807 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1808 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1809 rmb();
1810 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1811 atomic_set(&dev->phy.txerr_cnt,
1812 B43_PHY_TX_BADNESS_LIMIT);
1813 b43err(dev->wl, "Too many PHY TX errors, "
1814 "restarting the controller\n");
1815 b43_controller_restart(dev, "PHY TX errors");
1816 }
1817 }
e4d6b795
MB		 1818
1819 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1820 B43_DMAIRQ_NONFATALMASK))) {
1821 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1822 b43err(dev->wl, "Fatal DMA error: "
1823 "0x%08X, 0x%08X, 0x%08X, "
1824 "0x%08X, 0x%08X, 0x%08X\n",
1825 dma_reason[0], dma_reason[1],
1826 dma_reason[2], dma_reason[3],
1827 dma_reason[4], dma_reason[5]);
1828 b43_controller_restart(dev, "DMA error");
1829 mmiowb();
1830 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1831 return;
1832 }
1833 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1834 b43err(dev->wl, "DMA error: "
1835 "0x%08X, 0x%08X, 0x%08X, "
1836 "0x%08X, 0x%08X, 0x%08X\n",
1837 dma_reason[0], dma_reason[1],
1838 dma_reason[2], dma_reason[3],
1839 dma_reason[4], dma_reason[5]);
1840 }
1841 }
1842
1843 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1844 handle_irq_ucode_debug(dev);
1845 if (reason & B43_IRQ_TBTT_INDI)
1846 handle_irq_tbtt_indication(dev);
1847 if (reason & B43_IRQ_ATIM_END)
1848 handle_irq_atim_end(dev);
1849 if (reason & B43_IRQ_BEACON)
1850 handle_irq_beacon(dev);
1851 if (reason & B43_IRQ_PMQ)
1852 handle_irq_pmq(dev);
21954c36
MB		 1853 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1854 ;/* TODO */
1855 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1856 handle_irq_noise(dev);
1857
1858 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1859 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1860 if (b43_using_pio_transfers(dev))
1861 b43_pio_rx(dev->pio.rx_queue);
1862 else
1863 b43_dma_rx(dev->dma.rx_ring);
1864 }
e4d6b795
MB		 1865 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1866 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1867 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1868 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1869 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1870
21954c36 1871 if (reason & B43_IRQ_TX_OK)
e4d6b795 1872 handle_irq_transmit_status(dev);
e4d6b795 1873
e4d6b795
MB		 1874 b43_interrupt_enable(dev, dev->irq_savedstate);
1875 mmiowb();
1876 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1877}
1878
e4d6b795
MB		 1879static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1880{
e4d6b795
MB		 1881 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1882
1883 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1884 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1885 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1886 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1887 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1888 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1889}
1890
1891/* Interrupt handler top-half */
1892static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1893{
1894 irqreturn_t ret = IRQ_NONE;
1895 struct b43_wldev *dev = dev_id;
1896 u32 reason;
1897
1898 if (!dev)
1899 return IRQ_NONE;
1900
1901 spin_lock(&dev->wl->irq_lock);
1902
1903 if (b43_status(dev) < B43_STAT_STARTED)
1904 goto out;
1905 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1906 if (reason == 0xffffffff) /* shared IRQ */
1907 goto out;
1908 ret = IRQ_HANDLED;
1909 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1910 if (!reason)
1911 goto out;
1912
1913 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1914 & 0x0001DC00;
1915 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1916 & 0x0000DC00;
1917 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1918 & 0x0000DC00;
1919 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1920 & 0x0001DC00;
1921 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1922 & 0x0000DC00;
1923 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1924 & 0x0000DC00;
1925
1926 b43_interrupt_ack(dev, reason);
1927 /* disable all IRQs. They are enabled again in the bottom half. */
1928 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1929 /* save the reason code and call our bottom half. */
1930 dev->irq_reason = reason;
1931 tasklet_schedule(&dev->isr_tasklet);
1932 out:
1933 mmiowb();
1934 spin_unlock(&dev->wl->irq_lock);
1935
1936 return ret;
1937}
1938
61cb5dd6
MB		 1939static void do_release_fw(struct b43_firmware_file *fw)
1940{
1941 release_firmware(fw->data);
1942 fw->data = NULL;
1943 fw->filename = NULL;
1944}
1945
e4d6b795
MB		 1946static void b43_release_firmware(struct b43_wldev *dev)
1947{
61cb5dd6
MB		 1948 do_release_fw(&dev->fw.ucode);
1949 do_release_fw(&dev->fw.pcm);
1950 do_release_fw(&dev->fw.initvals);
1951 do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1952}
1953
eb189d8b 1954static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1955{
eb189d8b
MB		 1956 const char *text;
1957
1958 text = "You must go to "
354807e0 1959 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
eb189d8b
MB		 1960 "and download the latest firmware (version 4).\n";
1961 if (error)
1962 b43err(wl, text);
1963 else
1964 b43warn(wl, text);
e4d6b795
MB		 1965}
1966
1967static int do_request_fw(struct b43_wldev *dev,
1968 const char *name,
68217832
MB		 1969 struct b43_firmware_file *fw,
1970 bool silent)
e4d6b795 1971{
1a09404a 1972 char path[sizeof(modparam_fwpostfix) + 32];
61cb5dd6 1973 const struct firmware *blob;
e4d6b795
MB		 1974 struct b43_fw_header *hdr;
1975 u32 size;
1976 int err;
1977
61cb5dd6
MB		 1978 if (!name) {
1979 /* Don't fetch anything. Free possibly cached firmware. */
1980 do_release_fw(fw);
e4d6b795 1981 return 0;
61cb5dd6
MB		 1982 }
1983 if (fw->filename) {
1984 if (strcmp(fw->filename, name) == 0)
1985 return 0; /* Already have this fw. */
1986 /* Free the cached firmware first. */
1987 do_release_fw(fw);
1988 }
e4d6b795
MB		 1989
1990 snprintf(path, ARRAY_SIZE(path),
1991 "b43%s/%s.fw",
1992 modparam_fwpostfix, name);
61cb5dd6 1993 err = request_firmware(&blob, path, dev->dev->dev);
68217832
MB		 1994 if (err == -ENOENT) {
1995 if (!silent) {
1996 b43err(dev->wl, "Firmware file \"%s\" not found\n",
1997 path);
1998 }
1999 return err;
2000 } else if (err) {
2001 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2002 path, err);
e4d6b795
MB		 2003 return err;
2004 }
61cb5dd6 2005 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2006 goto err_format;
61cb5dd6 2007 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2008 switch (hdr->type) {
2009 case B43_FW_TYPE_UCODE:
2010 case B43_FW_TYPE_PCM:
2011 size = be32_to_cpu(hdr->size);
61cb5dd6 2012 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2013 goto err_format;
2014 /* fallthrough */
2015 case B43_FW_TYPE_IV:
2016 if (hdr->ver != 1)
2017 goto err_format;
2018 break;
2019 default:
2020 goto err_format;
2021 }
2022
61cb5dd6
MB		 2023 fw->data = blob;
2024 fw->filename = name;
2025
2026 return 0;
e4d6b795
MB		 2027
2028err_format:
2029 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
61cb5dd6
MB		 2030 release_firmware(blob);
2031
e4d6b795
MB		 2032 return -EPROTO;
2033}
2034
2035static int b43_request_firmware(struct b43_wldev *dev)
2036{
2037 struct b43_firmware *fw = &dev->fw;
2038 const u8 rev = dev->dev->id.revision;
2039 const char *filename;
2040 u32 tmshigh;
2041 int err;
2042
61cb5dd6 2043 /* Get microcode */
e4d6b795 2044 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2045 if ((rev >= 5) && (rev <= 10))
2046 filename = "ucode5";
2047 else if ((rev >= 11) && (rev <= 12))
2048 filename = "ucode11";
2049 else if (rev >= 13)
2050 filename = "ucode13";
2051 else
2052 goto err_no_ucode;
68217832 2053 err = do_request_fw(dev, filename, &fw->ucode, 0);
61cb5dd6
MB		 2054 if (err)
2055 goto err_load;
2056
2057 /* Get PCM code */
2058 if ((rev >= 5) && (rev <= 10))
2059 filename = "pcm5";
2060 else if (rev >= 11)
2061 filename = NULL;
2062 else
2063 goto err_no_pcm;
68217832
MB		 2064 fw->pcm_request_failed = 0;
2065 err = do_request_fw(dev, filename, &fw->pcm, 1);
2066 if (err == -ENOENT) {
2067 /* We did not find a PCM file? Not fatal, but
2068 * core rev <= 10 must do without hwcrypto then. */
2069 fw->pcm_request_failed = 1;
2070 } else if (err)
61cb5dd6
MB		 2071 goto err_load;
2072
2073 /* Get initvals */
2074 switch (dev->phy.type) {
2075 case B43_PHYTYPE_A:
2076 if ((rev >= 5) && (rev <= 10)) {
2077 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2078 filename = "a0g1initvals5";
2079 else
2080 filename = "a0g0initvals5";
2081 } else
2082 goto err_no_initvals;
2083 break;
2084 case B43_PHYTYPE_G:
e4d6b795 2085 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2086 filename = "b0g0initvals5";
e4d6b795 2087 else if (rev >= 13)
e9304882 2088 filename = "b0g0initvals13";
e4d6b795 2089 else
61cb5dd6
MB		 2090 goto err_no_initvals;
2091 break;
2092 case B43_PHYTYPE_N:
2093 if ((rev >= 11) && (rev <= 12))
2094 filename = "n0initvals11";
2095 else
2096 goto err_no_initvals;
2097 break;
2098 default:
2099 goto err_no_initvals;
e4d6b795 2100 }
68217832 2101 err = do_request_fw(dev, filename, &fw->initvals, 0);
61cb5dd6
MB		 2102 if (err)
2103 goto err_load;
2104
2105 /* Get bandswitch initvals */
2106 switch (dev->phy.type) {
2107 case B43_PHYTYPE_A:
2108 if ((rev >= 5) && (rev <= 10)) {
2109 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2110 filename = "a0g1bsinitvals5";
2111 else
2112 filename = "a0g0bsinitvals5";
2113 } else if (rev >= 11)
2114 filename = NULL;
2115 else
2116 goto err_no_initvals;
2117 break;
2118 case B43_PHYTYPE_G:
e4d6b795 2119 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2120 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2121 else if (rev >= 11)
2122 filename = NULL;
2123 else
e4d6b795 2124 goto err_no_initvals;
61cb5dd6
MB		 2125 break;
2126 case B43_PHYTYPE_N:
2127 if ((rev >= 11) && (rev <= 12))
2128 filename = "n0bsinitvals11";
2129 else
e4d6b795 2130 goto err_no_initvals;
61cb5dd6
MB		 2131 break;
2132 default:
2133 goto err_no_initvals;
e4d6b795 2134 }
68217832 2135 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
61cb5dd6
MB		 2136 if (err)
2137 goto err_load;
e4d6b795
MB		 2138
2139 return 0;
2140
2141err_load:
eb189d8b 2142 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2143 goto error;
2144
2145err_no_ucode:
2146 err = -ENODEV;
2147 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2148 goto error;
2149
2150err_no_pcm:
2151 err = -ENODEV;
2152 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2153 goto error;
2154
2155err_no_initvals:
2156 err = -ENODEV;
2157 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2158 "core rev %u\n", dev->phy.type, rev);
2159 goto error;
2160
2161error:
2162 b43_release_firmware(dev);
2163 return err;
2164}
2165
2166static int b43_upload_microcode(struct b43_wldev *dev)
2167{
2168 const size_t hdr_len = sizeof(struct b43_fw_header);
2169 const __be32 *data;
2170 unsigned int i, len;
2171 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2172 u32 tmp, macctl;
e4d6b795
MB		 2173 int err = 0;
2174
1f7d87b0
MB		 2175 /* Jump the microcode PSM to offset 0 */
2176 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2177 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2178 macctl |= B43_MACCTL_PSM_JMP0;
2179 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2180 /* Zero out all microcode PSM registers and shared memory. */
2181 for (i = 0; i < 64; i++)
2182 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2183 for (i = 0; i < 4096; i += 2)
2184 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2185
e4d6b795 2186 /* Upload Microcode. */
61cb5dd6
MB		 2187 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2188 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2189 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2190 for (i = 0; i < len; i++) {
2191 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2192 udelay(10);
2193 }
2194
61cb5dd6 2195 if (dev->fw.pcm.data) {
e4d6b795 2196 /* Upload PCM data. */
61cb5dd6
MB		 2197 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2198 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2199 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2200 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2201 /* No need for autoinc bit in SHM_HW */
2202 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2203 for (i = 0; i < len; i++) {
2204 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2205 udelay(10);
2206 }
2207 }
2208
2209 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2210
2211 /* Start the microcode PSM */
2212 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2213 macctl &= ~B43_MACCTL_PSM_JMP0;
2214 macctl |= B43_MACCTL_PSM_RUN;
2215 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2216
2217 /* Wait for the microcode to load and respond */
2218 i = 0;
2219 while (1) {
2220 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2221 if (tmp == B43_IRQ_MAC_SUSPENDED)
2222 break;
2223 i++;
1f7d87b0 2224 if (i >= 20) {
e4d6b795 2225 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2226 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2227 err = -ENODEV;
1f7d87b0
MB		 2228 goto error;
2229 }
2230 msleep_interruptible(50);
2231 if (signal_pending(current)) {
2232 err = -EINTR;
2233 goto error;
e4d6b795 2234 }
e4d6b795
MB		 2235 }
2236 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2237
2238 /* Get and check the revisions. */
2239 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2240 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2241 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2242 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2243
2244 if (fwrev <= 0x128) {
2245 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2246 "binary drivers older than version 4.x is unsupported. "
2247 "You must upgrade your firmware files.\n");
eb189d8b 2248 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2249 err = -EOPNOTSUPP;
1f7d87b0 2250 goto error;
e4d6b795 2251 }
e4d6b795
MB		 2252 dev->fw.rev = fwrev;
2253 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2254 dev->fw.opensource = (fwdate == 0xFFFF);
2255
2256 if (dev->fw.opensource) {
2257 /* Patchlevel info is encoded in the "time" field. */
2258 dev->fw.patch = fwtime;
68217832
MB		 2259 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2260 dev->fw.rev, dev->fw.patch,
2261 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
e48b0eeb
MB		 2262 } else {
2263 b43info(dev->wl, "Loading firmware version %u.%u "
2264 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2265 fwrev, fwpatch,
2266 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2267 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2268 if (dev->fw.pcm_request_failed) {
2269 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2270 "Hardware accelerated cryptography is disabled.\n");
2271 b43_print_fw_helptext(dev->wl, 0);
2272 }
e48b0eeb 2273 }
e4d6b795 2274
eb189d8b
MB		 2275 if (b43_is_old_txhdr_format(dev)) {
2276 b43warn(dev->wl, "You are using an old firmware image. "
2277 "Support for old firmware will be removed in July 2008.\n");
2278 b43_print_fw_helptext(dev->wl, 0);
2279 }
2280
1f7d87b0
MB		 2281 return 0;
2282
2283error:
2284 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2285 macctl &= ~B43_MACCTL_PSM_RUN;
2286 macctl |= B43_MACCTL_PSM_JMP0;
2287 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2288
e4d6b795
MB		 2289 return err;
2290}
2291
2292static int b43_write_initvals(struct b43_wldev *dev,
2293 const struct b43_iv *ivals,
2294 size_t count,
2295 size_t array_size)
2296{
2297 const struct b43_iv *iv;
2298 u16 offset;
2299 size_t i;
2300 bool bit32;
2301
2302 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2303 iv = ivals;
2304 for (i = 0; i < count; i++) {
2305 if (array_size < sizeof(iv->offset_size))
2306 goto err_format;
2307 array_size -= sizeof(iv->offset_size);
2308 offset = be16_to_cpu(iv->offset_size);
2309 bit32 = !!(offset & B43_IV_32BIT);
2310 offset &= B43_IV_OFFSET_MASK;
2311 if (offset >= 0x1000)
2312 goto err_format;
2313 if (bit32) {
2314 u32 value;
2315
2316 if (array_size < sizeof(iv->data.d32))
2317 goto err_format;
2318 array_size -= sizeof(iv->data.d32);
2319
533dd1b0 2320 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2321 b43_write32(dev, offset, value);
2322
2323 iv = (const struct b43_iv *)((const uint8_t *)iv +
2324 sizeof(__be16) +
2325 sizeof(__be32));
2326 } else {
2327 u16 value;
2328
2329 if (array_size < sizeof(iv->data.d16))
2330 goto err_format;
2331 array_size -= sizeof(iv->data.d16);
2332
2333 value = be16_to_cpu(iv->data.d16);
2334 b43_write16(dev, offset, value);
2335
2336 iv = (const struct b43_iv *)((const uint8_t *)iv +
2337 sizeof(__be16) +
2338 sizeof(__be16));
2339 }
2340 }
2341 if (array_size)
2342 goto err_format;
2343
2344 return 0;
2345
2346err_format:
2347 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2348 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2349
2350 return -EPROTO;
2351}
2352
2353static int b43_upload_initvals(struct b43_wldev *dev)
2354{
2355 const size_t hdr_len = sizeof(struct b43_fw_header);
2356 const struct b43_fw_header *hdr;
2357 struct b43_firmware *fw = &dev->fw;
2358 const struct b43_iv *ivals;
2359 size_t count;
2360 int err;
2361
61cb5dd6
MB		 2362 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2363 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2364 count = be32_to_cpu(hdr->size);
2365 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2366 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2367 if (err)
2368 goto out;
61cb5dd6
MB		 2369 if (fw->initvals_band.data) {
2370 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2371 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2372 count = be32_to_cpu(hdr->size);
2373 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2374 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2375 if (err)
2376 goto out;
2377 }
2378out:
2379
2380 return err;
2381}
2382
2383/* Initialize the GPIOs
2384 * http://bcm-specs.sipsolutions.net/GPIO
2385 */
2386static int b43_gpio_init(struct b43_wldev *dev)
2387{
2388 struct ssb_bus *bus = dev->dev->bus;
2389 struct ssb_device *gpiodev, *pcidev = NULL;
2390 u32 mask, set;
2391
2392 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2393 & ~B43_MACCTL_GPOUTSMSK);
2394
e4d6b795
MB		 2395 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2396 | 0x000F);
2397
2398 mask = 0x0000001F;
2399 set = 0x0000000F;
2400 if (dev->dev->bus->chip_id == 0x4301) {
2401 mask |= 0x0060;
2402 set |= 0x0060;
2403 }
2404 if (0 /* FIXME: conditional unknown */ ) {
2405 b43_write16(dev, B43_MMIO_GPIO_MASK,
2406 b43_read16(dev, B43_MMIO_GPIO_MASK)
2407 | 0x0100);
2408 mask |= 0x0180;
2409 set |= 0x0180;
2410 }
95de2841 2411 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2412 b43_write16(dev, B43_MMIO_GPIO_MASK,
2413 b43_read16(dev, B43_MMIO_GPIO_MASK)
2414 | 0x0200);
2415 mask |= 0x0200;
2416 set |= 0x0200;
2417 }
2418 if (dev->dev->id.revision >= 2)
2419 mask |= 0x0010; /* FIXME: This is redundant. */
2420
2421#ifdef CONFIG_SSB_DRIVER_PCICORE
2422 pcidev = bus->pcicore.dev;
2423#endif
2424 gpiodev = bus->chipco.dev ? : pcidev;
2425 if (!gpiodev)
2426 return 0;
2427 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2428 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2429 & mask) | set);
2430
2431 return 0;
2432}
2433
2434/* Turn off all GPIO stuff. Call this on module unload, for example. */
2435static void b43_gpio_cleanup(struct b43_wldev *dev)
2436{
2437 struct ssb_bus *bus = dev->dev->bus;
2438 struct ssb_device *gpiodev, *pcidev = NULL;
2439
2440#ifdef CONFIG_SSB_DRIVER_PCICORE
2441 pcidev = bus->pcicore.dev;
2442#endif
2443 gpiodev = bus->chipco.dev ? : pcidev;
2444 if (!gpiodev)
2445 return;
2446 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2447}
2448
2449/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2450void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2451{
923fd703
MB		 2452 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2453 u16 fwstate;
2454
2455 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2456 B43_SHM_SH_UCODESTAT);
2457 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2458 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2459 b43err(dev->wl, "b43_mac_enable(): The firmware "
2460 "should be suspended, but current state is %u\n",
2461 fwstate);
2462 }
2463 }
2464
e4d6b795
MB		 2465 dev->mac_suspended--;
2466 B43_WARN_ON(dev->mac_suspended < 0);
2467 if (dev->mac_suspended == 0) {
2468 b43_write32(dev, B43_MMIO_MACCTL,
2469 b43_read32(dev, B43_MMIO_MACCTL)
2470 | B43_MACCTL_ENABLED);
2471 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2472 B43_IRQ_MAC_SUSPENDED);
2473 /* Commit writes */
2474 b43_read32(dev, B43_MMIO_MACCTL);
2475 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2476 b43_power_saving_ctl_bits(dev, 0);
2477 }
2478}
2479
2480/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2481void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2482{
2483 int i;
2484 u32 tmp;
2485
05b64b36 2486 might_sleep();
e4d6b795 2487 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2488
e4d6b795
MB		 2489 if (dev->mac_suspended == 0) {
2490 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2491 b43_write32(dev, B43_MMIO_MACCTL,
2492 b43_read32(dev, B43_MMIO_MACCTL)
2493 & ~B43_MACCTL_ENABLED);
2494 /* force pci to flush the write */
2495 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2496 for (i = 35; i; i--) {
2497 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2498 if (tmp & B43_IRQ_MAC_SUSPENDED)
2499 goto out;
2500 udelay(10);
2501 }
2502 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2503 for (i = 40; i; i--) {
e4d6b795
MB		 2504 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2505 if (tmp & B43_IRQ_MAC_SUSPENDED)
2506 goto out;
05b64b36 2507 msleep(1);
e4d6b795
MB		 2508 }
2509 b43err(dev->wl, "MAC suspend failed\n");
2510 }
05b64b36 2511out:
e4d6b795
MB		 2512 dev->mac_suspended++;
2513}
2514
2515static void b43_adjust_opmode(struct b43_wldev *dev)
2516{
2517 struct b43_wl *wl = dev->wl;
2518 u32 ctl;
2519 u16 cfp_pretbtt;
2520
2521 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2522 /* Reset status to STA infrastructure mode. */
2523 ctl &= ~B43_MACCTL_AP;
2524 ctl &= ~B43_MACCTL_KEEP_CTL;
2525 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2526 ctl &= ~B43_MACCTL_KEEP_BAD;
2527 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2528 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2529 ctl |= B43_MACCTL_INFRA;
2530
05c914fe
JB		 2531 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2532 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2533 ctl |= B43_MACCTL_AP;
05c914fe 2534 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2535 ctl &= ~B43_MACCTL_INFRA;
2536
2537 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2538 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2539 if (wl->filter_flags & FIF_FCSFAIL)
2540 ctl |= B43_MACCTL_KEEP_BAD;
2541 if (wl->filter_flags & FIF_PLCPFAIL)
2542 ctl |= B43_MACCTL_KEEP_BADPLCP;
2543 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2544 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2545 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2546 ctl |= B43_MACCTL_BEACPROMISC;
2547
e4d6b795
MB		 2548 /* Workaround: On old hardware the HW-MAC-address-filter
2549 * doesn't work properly, so always run promisc in filter
2550 * it in software. */
2551 if (dev->dev->id.revision <= 4)
2552 ctl |= B43_MACCTL_PROMISC;
2553
2554 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2555
2556 cfp_pretbtt = 2;
2557 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2558 if (dev->dev->bus->chip_id == 0x4306 &&
2559 dev->dev->bus->chip_rev == 3)
2560 cfp_pretbtt = 100;
2561 else
2562 cfp_pretbtt = 50;
2563 }
2564 b43_write16(dev, 0x612, cfp_pretbtt);
2565}
2566
2567static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2568{
2569 u16 offset;
2570
2571 if (is_ofdm) {
2572 offset = 0x480;
2573 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2574 } else {
2575 offset = 0x4C0;
2576 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2577 }
2578 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2579 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2580}
2581
2582static void b43_rate_memory_init(struct b43_wldev *dev)
2583{
2584 switch (dev->phy.type) {
2585 case B43_PHYTYPE_A:
2586 case B43_PHYTYPE_G:
53a6e234 2587 case B43_PHYTYPE_N:
e4d6b795
MB		 2588 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2589 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2590 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2591 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2592 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2593 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2594 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2595 if (dev->phy.type == B43_PHYTYPE_A)
2596 break;
2597 /* fallthrough */
2598 case B43_PHYTYPE_B:
2599 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2600 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2601 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2602 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2603 break;
2604 default:
2605 B43_WARN_ON(1);
2606 }
2607}
2608
5042c507
MB		 2609/* Set the default values for the PHY TX Control Words. */
2610static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2611{
2612 u16 ctl = 0;
2613
2614 ctl |= B43_TXH_PHY_ENC_CCK;
2615 ctl |= B43_TXH_PHY_ANT01AUTO;
2616 ctl |= B43_TXH_PHY_TXPWR;
2617
2618 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2619 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2620 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2621}
2622
e4d6b795
MB		 2623/* Set the TX-Antenna for management frames sent by firmware. */
2624static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2625{
5042c507 2626 u16 ant;
e4d6b795
MB		 2627 u16 tmp;
2628
5042c507 2629 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2630
e4d6b795
MB		 2631 /* For ACK/CTS */
2632 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2633 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2634 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2635 /* For Probe Resposes */
2636 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2637 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2638 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2639}
2640
2641/* This is the opposite of b43_chip_init() */
2642static void b43_chip_exit(struct b43_wldev *dev)
2643{
fb11137a 2644 b43_phy_exit(dev);
e4d6b795
MB		 2645 b43_gpio_cleanup(dev);
2646 /* firmware is released later */
2647}
2648
2649/* Initialize the chip
2650 * http://bcm-specs.sipsolutions.net/ChipInit
2651 */
2652static int b43_chip_init(struct b43_wldev *dev)
2653{
2654 struct b43_phy *phy = &dev->phy;
ef1a628d 2655 int err;
1f7d87b0 2656 u32 value32, macctl;
e4d6b795
MB		 2657 u16 value16;
2658
1f7d87b0
MB		 2659 /* Initialize the MAC control */
2660 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2661 if (dev->phy.gmode)
2662 macctl |= B43_MACCTL_GMODE;
2663 macctl |= B43_MACCTL_INFRA;
2664 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2665
2666 err = b43_request_firmware(dev);
2667 if (err)
2668 goto out;
2669 err = b43_upload_microcode(dev);
2670 if (err)
2671 goto out; /* firmware is released later */
2672
2673 err = b43_gpio_init(dev);
2674 if (err)
2675 goto out; /* firmware is released later */
21954c36 2676
e4d6b795
MB		 2677 err = b43_upload_initvals(dev);
2678 if (err)
1a8d1227 2679 goto err_gpio_clean;
e4d6b795 2680
0b7dcd96
MB		 2681 /* Turn the Analog on and initialize the PHY. */
2682 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2683 err = b43_phy_init(dev);
2684 if (err)
ef1a628d 2685 goto err_gpio_clean;
e4d6b795 2686
ef1a628d
MB		 2687 /* Disable Interference Mitigation. */
2688 if (phy->ops->interf_mitigation)
2689 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2690
ef1a628d
MB		 2691 /* Select the antennae */
2692 if (phy->ops->set_rx_antenna)
2693 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2694 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2695
2696 if (phy->type == B43_PHYTYPE_B) {
2697 value16 = b43_read16(dev, 0x005E);
2698 value16 |= 0x0004;
2699 b43_write16(dev, 0x005E, value16);
2700 }
2701 b43_write32(dev, 0x0100, 0x01000000);
2702 if (dev->dev->id.revision < 5)
2703 b43_write32(dev, 0x010C, 0x01000000);
2704
2705 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2706 & ~B43_MACCTL_INFRA);
2707 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2708 | B43_MACCTL_INFRA);
e4d6b795 2709
e4d6b795
MB		 2710 /* Probe Response Timeout value */
2711 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2712 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2713
2714 /* Initially set the wireless operation mode. */
2715 b43_adjust_opmode(dev);
2716
2717 if (dev->dev->id.revision < 3) {
2718 b43_write16(dev, 0x060E, 0x0000);
2719 b43_write16(dev, 0x0610, 0x8000);
2720 b43_write16(dev, 0x0604, 0x0000);
2721 b43_write16(dev, 0x0606, 0x0200);
2722 } else {
2723 b43_write32(dev, 0x0188, 0x80000000);
2724 b43_write32(dev, 0x018C, 0x02000000);
2725 }
2726 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2727 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2728 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2729 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2730 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2731 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2732 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2733
2734 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2735 value32 |= 0x00100000;
2736 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2737
2738 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2739 dev->dev->bus->chipco.fast_pwrup_delay);
2740
2741 err = 0;
2742 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2743out:
e4d6b795
MB		 2744 return err;
2745
1a8d1227 2746err_gpio_clean:
e4d6b795 2747 b43_gpio_cleanup(dev);
21954c36 2748 return err;
e4d6b795
MB		 2749}
2750
e4d6b795
MB		 2751static void b43_periodic_every60sec(struct b43_wldev *dev)
2752{
ef1a628d 2753 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2754
ef1a628d
MB		 2755 if (ops->pwork_60sec)
2756 ops->pwork_60sec(dev);
18c8adeb
MB		 2757
2758 /* Force check the TX power emission now. */
2759 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2760}
2761
2762static void b43_periodic_every30sec(struct b43_wldev *dev)
2763{
2764 /* Update device statistics. */
2765 b43_calculate_link_quality(dev);
2766}
2767
2768static void b43_periodic_every15sec(struct b43_wldev *dev)
2769{
2770 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2771 u16 wdr;
2772
2773 if (dev->fw.opensource) {
2774 /* Check if the firmware is still alive.
2775 * It will reset the watchdog counter to 0 in its idle loop. */
2776 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2777 if (unlikely(wdr)) {
2778 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2779 b43_controller_restart(dev, "Firmware watchdog");
2780 return;
2781 } else {
2782 b43_shm_write16(dev, B43_SHM_SCRATCH,
2783 B43_WATCHDOG_REG, 1);
2784 }
2785 }
e4d6b795 2786
ef1a628d
MB		 2787 if (phy->ops->pwork_15sec)
2788 phy->ops->pwork_15sec(dev);
2789
00e0b8cb
SB		 2790 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2791 wmb();
e4d6b795
MB		 2792}
2793
e4d6b795
MB		 2794static void do_periodic_work(struct b43_wldev *dev)
2795{
2796 unsigned int state;
2797
2798 state = dev->periodic_state;
42bb4cd5 2799 if (state % 4 == 0)
e4d6b795 2800 b43_periodic_every60sec(dev);
42bb4cd5 2801 if (state % 2 == 0)
e4d6b795 2802 b43_periodic_every30sec(dev);
42bb4cd5 2803 b43_periodic_every15sec(dev);
e4d6b795
MB		 2804}
2805
05b64b36
MB		 2806/* Periodic work locking policy:
2807 * The whole periodic work handler is protected by
2808 * wl->mutex. If another lock is needed somewhere in the
2809 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2810 */
e4d6b795
MB		 2811static void b43_periodic_work_handler(struct work_struct *work)
2812{
05b64b36
MB		 2813 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2814 periodic_work.work);
2815 struct b43_wl *wl = dev->wl;
2816 unsigned long delay;
e4d6b795 2817
05b64b36 2818 mutex_lock(&wl->mutex);
e4d6b795
MB		 2819
2820 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2821 goto out;
2822 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2823 goto out_requeue;
2824
05b64b36 2825 do_periodic_work(dev);
e4d6b795 2826
e4d6b795 2827 dev->periodic_state++;
42bb4cd5 2828out_requeue:
e4d6b795
MB		 2829 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2830 delay = msecs_to_jiffies(50);
2831 else
82cd682d 2832 delay = round_jiffies_relative(HZ * 15);
05b64b36 2833 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2834out:
05b64b36 2835 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2836}
2837
2838static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2839{
2840 struct delayed_work *work = &dev->periodic_work;
2841
2842 dev->periodic_state = 0;
2843 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2844 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2845}
2846
f3dd3fcc 2847/* Check if communication with the device works correctly. */
e4d6b795
MB		 2848static int b43_validate_chipaccess(struct b43_wldev *dev)
2849{
f3dd3fcc 2850 u32 v, backup;
e4d6b795 2851
f3dd3fcc
MB		 2852 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2853
2854 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2855 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2856 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2857 goto error;
f3dd3fcc
MB		 2858 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2859 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2860 goto error;
2861
f3dd3fcc
MB		 2862 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2863
2864 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2865 /* The 32bit register shadows the two 16bit registers
2866 * with update sideeffects. Validate this. */
2867 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2868 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2869 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2870 goto error;
2871 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2872 goto error;
2873 }
2874 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2875
2876 v = b43_read32(dev, B43_MMIO_MACCTL);
2877 v |= B43_MACCTL_GMODE;
2878 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2879 goto error;
2880
2881 return 0;
f3dd3fcc 2882error:
e4d6b795
MB		 2883 b43err(dev->wl, "Failed to validate the chipaccess\n");
2884 return -ENODEV;
2885}
2886
2887static void b43_security_init(struct b43_wldev *dev)
2888{
2889 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2890 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2891 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2892 /* KTP is a word address, but we address SHM bytewise.
2893 * So multiply by two.
2894 */
2895 dev->ktp *= 2;
2896 if (dev->dev->id.revision >= 5) {
2897 /* Number of RCMTA address slots */
2898 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2899 }
2900 b43_clear_keys(dev);
2901}
2902
2903static int b43_rng_read(struct hwrng *rng, u32 * data)
2904{
2905 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2906 unsigned long flags;
2907
2908 /* Don't take wl->mutex here, as it could deadlock with
2909 * hwrng internal locking. It's not needed to take
2910 * wl->mutex here, anyway. */
2911
2912 spin_lock_irqsave(&wl->irq_lock, flags);
2913 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2914 spin_unlock_irqrestore(&wl->irq_lock, flags);
2915
2916 return (sizeof(u16));
2917}
2918
b844eba2 2919static void b43_rng_exit(struct b43_wl *wl)
e4d6b795
MB		 2920{
2921 if (wl->rng_initialized)
b844eba2 2922 hwrng_unregister(&wl->rng);
e4d6b795
MB		 2923}
2924
2925static int b43_rng_init(struct b43_wl *wl)
2926{
2927 int err;
2928
2929 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2930 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2931 wl->rng.name = wl->rng_name;
2932 wl->rng.data_read = b43_rng_read;
2933 wl->rng.priv = (unsigned long)wl;
2934 wl->rng_initialized = 1;
2935 err = hwrng_register(&wl->rng);
2936 if (err) {
2937 wl->rng_initialized = 0;
2938 b43err(wl, "Failed to register the random "
2939 "number generator (%d)\n", err);
2940 }
2941
2942 return err;
2943}
2944
40faacc4 2945static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 2946 struct sk_buff *skb)
e4d6b795
MB		 2947{
2948 struct b43_wl *wl = hw_to_b43_wl(hw);
2949 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 2950 unsigned long flags;
2951 int err;
e4d6b795 2952
5100d5ac
MB		 2953 if (unlikely(skb->len < 2 + 2 + 6)) {
2954 /* Too short, this can't be a valid frame. */
c9e8eae0 2955 goto drop_packet;
5100d5ac
MB		 2956 }
2957 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 2958 if (unlikely(!dev))
c9e8eae0 2959 goto drop_packet;
21a75d77
MB		 2960
2961 /* Transmissions on seperate queues can run concurrently. */
2962 read_lock_irqsave(&wl->tx_lock, flags);
2963
2964 err = -ENODEV;
2965 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2966 if (b43_using_pio_transfers(dev))
e039fa4a 2967 err = b43_pio_tx(dev, skb);
21a75d77 2968 else
e039fa4a 2969 err = b43_dma_tx(dev, skb);
21a75d77
MB		 2970 }
2971
2972 read_unlock_irqrestore(&wl->tx_lock, flags);
2973
e4d6b795 2974 if (unlikely(err))
c9e8eae0
MB		 2975 goto drop_packet;
2976 return NETDEV_TX_OK;
2977
2978drop_packet:
2979 /* We can not transmit this packet. Drop it. */
2980 dev_kfree_skb_any(skb);
e4d6b795
MB		 2981 return NETDEV_TX_OK;
2982}
2983
e6f5b934
MB		 2984/* Locking: wl->irq_lock */
2985static void b43_qos_params_upload(struct b43_wldev *dev,
2986 const struct ieee80211_tx_queue_params *p,
2987 u16 shm_offset)
2988{
2989 u16 params[B43_NR_QOSPARAMS];
0b57664c 2990 int bslots, tmp;
e6f5b934
MB		 2991 unsigned int i;
2992
0b57664c 2993 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 2994
2995 memset(&params, 0, sizeof(params));
2996
2997 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 2998 params[B43_QOSPARAM_CWMIN] = p->cw_min;
2999 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3000 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3001 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3002 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3003 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3004
3005 for (i = 0; i < ARRAY_SIZE(params); i++) {
3006 if (i == B43_QOSPARAM_STATUS) {
3007 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3008 shm_offset + (i * 2));
3009 /* Mark the parameters as updated. */
3010 tmp |= 0x100;
3011 b43_shm_write16(dev, B43_SHM_SHARED,
3012 shm_offset + (i * 2),
3013 tmp);
3014 } else {
3015 b43_shm_write16(dev, B43_SHM_SHARED,
3016 shm_offset + (i * 2),
3017 params[i]);
3018 }
3019 }
3020}
3021
c40c1129
MB		 3022/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3023static const u16 b43_qos_shm_offsets[] = {
3024 /* [mac80211-queue-nr] = SHM_OFFSET, */
3025 [0] = B43_QOS_VOICE,
3026 [1] = B43_QOS_VIDEO,
3027 [2] = B43_QOS_BESTEFFORT,
3028 [3] = B43_QOS_BACKGROUND,
3029};
3030
5a5f3b40
MB		 3031/* Update all QOS parameters in hardware. */
3032static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3033{
3034 struct b43_wl *wl = dev->wl;
3035 struct b43_qos_params *params;
e6f5b934
MB		 3036 unsigned int i;
3037
c40c1129
MB		 3038 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3039 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3040
3041 b43_mac_suspend(dev);
e6f5b934
MB		 3042 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3043 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3044 b43_qos_params_upload(dev, &(params->p),
3045 b43_qos_shm_offsets[i]);
e6f5b934 3046 }
e6f5b934
MB		 3047 b43_mac_enable(dev);
3048}
3049
3050static void b43_qos_clear(struct b43_wl *wl)
3051{
3052 struct b43_qos_params *params;
3053 unsigned int i;
3054
c40c1129
MB		 3055 /* Initialize QoS parameters to sane defaults. */
3056
3057 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3058 ARRAY_SIZE(wl->qos_params));
3059
e6f5b934
MB		 3060 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3061 params = &(wl->qos_params[i]);
3062
c40c1129
MB		 3063 switch (b43_qos_shm_offsets[i]) {
3064 case B43_QOS_VOICE:
3065 params->p.txop = 0;
3066 params->p.aifs = 2;
3067 params->p.cw_min = 0x0001;
3068 params->p.cw_max = 0x0001;
3069 break;
3070 case B43_QOS_VIDEO:
3071 params->p.txop = 0;
3072 params->p.aifs = 2;
3073 params->p.cw_min = 0x0001;
3074 params->p.cw_max = 0x0001;
3075 break;
3076 case B43_QOS_BESTEFFORT:
3077 params->p.txop = 0;
3078 params->p.aifs = 3;
3079 params->p.cw_min = 0x0001;
3080 params->p.cw_max = 0x03FF;
3081 break;
3082 case B43_QOS_BACKGROUND:
3083 params->p.txop = 0;
3084 params->p.aifs = 7;
3085 params->p.cw_min = 0x0001;
3086 params->p.cw_max = 0x03FF;
3087 break;
3088 default:
3089 B43_WARN_ON(1);
3090 }
e6f5b934
MB		 3091 }
3092}
3093
3094/* Initialize the core's QOS capabilities */
3095static void b43_qos_init(struct b43_wldev *dev)
3096{
e6f5b934 3097 /* Upload the current QOS parameters. */
5a5f3b40 3098 b43_qos_upload_all(dev);
e6f5b934
MB		 3099
3100 /* Enable QOS support. */
3101 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3102 b43_write16(dev, B43_MMIO_IFSCTL,
3103 b43_read16(dev, B43_MMIO_IFSCTL)
3104 | B43_MMIO_IFSCTL_USE_EDCF);
3105}
3106
e100bb64 3107static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3108 const struct ieee80211_tx_queue_params *params)
e4d6b795 3109{
e6f5b934 3110 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3111 struct b43_wldev *dev;
e6f5b934 3112 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3113 int err = -ENODEV;
e6f5b934
MB		 3114
3115 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3116 /* Queue not available or don't support setting
3117 * params on this queue. Return success to not
3118 * confuse mac80211. */
3119 return 0;
3120 }
5a5f3b40
MB		 3121 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3122 ARRAY_SIZE(wl->qos_params));
e6f5b934 3123
5a5f3b40
MB		 3124 mutex_lock(&wl->mutex);
3125 dev = wl->current_dev;
3126 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3127 goto out_unlock;
e6f5b934 3128
5a5f3b40
MB		 3129 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3130 b43_mac_suspend(dev);
3131 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3132 b43_qos_shm_offsets[queue]);
3133 b43_mac_enable(dev);
3134 err = 0;
e6f5b934 3135
5a5f3b40
MB		 3136out_unlock:
3137 mutex_unlock(&wl->mutex);
3138
3139 return err;
e4d6b795
MB		 3140}
3141
40faacc4
MB		 3142static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3143 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3144{
3145 struct b43_wl *wl = hw_to_b43_wl(hw);
3146 struct b43_wldev *dev = wl->current_dev;
3147 unsigned long flags;
3148 int err = -ENODEV;
3149
3150 if (!dev)
3151 goto out;
3152 spin_lock_irqsave(&wl->irq_lock, flags);
3153 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3154 if (b43_using_pio_transfers(dev))
3155 b43_pio_get_tx_stats(dev, stats);
3156 else
3157 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3158 err = 0;
3159 }
3160 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3161out:
e4d6b795
MB		 3162 return err;
3163}
3164
40faacc4
MB		 3165static int b43_op_get_stats(struct ieee80211_hw *hw,
3166 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3167{
3168 struct b43_wl *wl = hw_to_b43_wl(hw);
3169 unsigned long flags;
3170
3171 spin_lock_irqsave(&wl->irq_lock, flags);
3172 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3173 spin_unlock_irqrestore(&wl->irq_lock, flags);
3174
3175 return 0;
3176}
3177
e4d6b795
MB		 3178static void b43_put_phy_into_reset(struct b43_wldev *dev)
3179{
3180 struct ssb_device *sdev = dev->dev;
3181 u32 tmslow;
3182
3183 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3184 tmslow &= ~B43_TMSLOW_GMODE;
3185 tmslow |= B43_TMSLOW_PHYRESET;
3186 tmslow |= SSB_TMSLOW_FGC;
3187 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3188 msleep(1);
3189
3190 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3191 tmslow &= ~SSB_TMSLOW_FGC;
3192 tmslow |= B43_TMSLOW_PHYRESET;
3193 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3194 msleep(1);
3195}
3196
bb1eeff1
MB		 3197static const char * band_to_string(enum ieee80211_band band)
3198{
3199 switch (band) {
3200 case IEEE80211_BAND_5GHZ:
3201 return "5";
3202 case IEEE80211_BAND_2GHZ:
3203 return "2.4";
3204 default:
3205 break;
3206 }
3207 B43_WARN_ON(1);
3208 return "";
3209}
3210
e4d6b795 3211/* Expects wl->mutex locked */
bb1eeff1 3212static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3213{
bb1eeff1 3214 struct b43_wldev *up_dev = NULL;
e4d6b795 3215 struct b43_wldev *down_dev;
bb1eeff1 3216 struct b43_wldev *d;
e4d6b795 3217 int err;
bb1eeff1 3218 bool gmode;
e4d6b795
MB		 3219 int prev_status;
3220
bb1eeff1
MB		 3221 /* Find a device and PHY which supports the band. */
3222 list_for_each_entry(d, &wl->devlist, list) {
3223 switch (chan->band) {
3224 case IEEE80211_BAND_5GHZ:
3225 if (d->phy.supports_5ghz) {
3226 up_dev = d;
3227 gmode = 0;
3228 }
3229 break;
3230 case IEEE80211_BAND_2GHZ:
3231 if (d->phy.supports_2ghz) {
3232 up_dev = d;
3233 gmode = 1;
3234 }
3235 break;
3236 default:
3237 B43_WARN_ON(1);
3238 return -EINVAL;
3239 }
3240 if (up_dev)
3241 break;
3242 }
3243 if (!up_dev) {
3244 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3245 band_to_string(chan->band));
3246 return -ENODEV;
e4d6b795
MB		 3247 }
3248 if ((up_dev == wl->current_dev) &&
3249 (!!wl->current_dev->phy.gmode == !!gmode)) {
3250 /* This device is already running. */
3251 return 0;
3252 }
bb1eeff1
MB		 3253 b43dbg(wl, "Switching to %s-GHz band\n",
3254 band_to_string(chan->band));
e4d6b795
MB		 3255 down_dev = wl->current_dev;
3256
3257 prev_status = b43_status(down_dev);
3258 /* Shutdown the currently running core. */
3259 if (prev_status >= B43_STAT_STARTED)
3260 b43_wireless_core_stop(down_dev);
3261 if (prev_status >= B43_STAT_INITIALIZED)
3262 b43_wireless_core_exit(down_dev);
3263
3264 if (down_dev != up_dev) {
3265 /* We switch to a different core, so we put PHY into
3266 * RESET on the old core. */
3267 b43_put_phy_into_reset(down_dev);
3268 }
3269
3270 /* Now start the new core. */
3271 up_dev->phy.gmode = gmode;
3272 if (prev_status >= B43_STAT_INITIALIZED) {
3273 err = b43_wireless_core_init(up_dev);
3274 if (err) {
3275 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3276 "selected %s-GHz band\n",
3277 band_to_string(chan->band));
e4d6b795
MB		 3278 goto init_failure;
3279 }
3280 }
3281 if (prev_status >= B43_STAT_STARTED) {
3282 err = b43_wireless_core_start(up_dev);
3283 if (err) {
3284 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3285 "selected %s-GHz band\n",
3286 band_to_string(chan->band));
e4d6b795
MB		 3287 b43_wireless_core_exit(up_dev);
3288 goto init_failure;
3289 }
3290 }
3291 B43_WARN_ON(b43_status(up_dev) != prev_status);
3292
3293 wl->current_dev = up_dev;
3294
3295 return 0;
bb1eeff1 3296init_failure:
e4d6b795
MB		 3297 /* Whoops, failed to init the new core. No core is operating now. */
3298 wl->current_dev = NULL;
3299 return err;
3300}
3301
9124b077
JB		 3302/* Write the short and long frame retry limit values. */
3303static void b43_set_retry_limits(struct b43_wldev *dev,
3304 unsigned int short_retry,
3305 unsigned int long_retry)
3306{
3307 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3308 * the chip-internal counter. */
3309 short_retry = min(short_retry, (unsigned int)0xF);
3310 long_retry = min(long_retry, (unsigned int)0xF);
3311
3312 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3313 short_retry);
3314 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3315 long_retry);
3316}
3317
e8975581 3318static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3319{
3320 struct b43_wl *wl = hw_to_b43_wl(hw);
3321 struct b43_wldev *dev;
3322 struct b43_phy *phy;
e8975581 3323 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3324 unsigned long flags;
9db1f6d7 3325 int antenna;
e4d6b795 3326 int err = 0;
e4d6b795 3327
e4d6b795
MB		 3328 mutex_lock(&wl->mutex);
3329
bb1eeff1
MB		 3330 /* Switch the band (if necessary). This might change the active core. */
3331 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3332 if (err)
3333 goto out_unlock_mutex;
3334 dev = wl->current_dev;
3335 phy = &dev->phy;
3336
d10d0e57
MB		 3337 b43_mac_suspend(dev);
3338
9124b077
JB		 3339 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3340 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3341 conf->long_frame_max_tx_count);
3342 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3343 if (!changed)
d10d0e57 3344 goto out_mac_enable;
e4d6b795
MB		 3345
3346 /* Switch to the requested channel.
3347 * The firmware takes care of races with the TX handler. */
8318d78a 3348 if (conf->channel->hw_value != phy->channel)
ef1a628d 3349 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3350
d42ce84a
JB		 3351 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3352
e4d6b795
MB		 3353 /* Adjust the desired TX power level. */
3354 if (conf->power_level != 0) {
18c8adeb
MB		 3355 spin_lock_irqsave(&wl->irq_lock, flags);
3356 if (conf->power_level != phy->desired_txpower) {
3357 phy->desired_txpower = conf->power_level;
3358 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3359 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3360 }
18c8adeb 3361 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3362 }
3363
3364 /* Antennas for RX and management frame TX. */
0f4ac38b 3365 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3366 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3367 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3368 if (phy->ops->set_rx_antenna)
3369 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3370
04dea136 3371 /* Update templates for AP/mesh mode. */
05c914fe
JB		 3372 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3373 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
e4d6b795
MB		 3374 b43_set_beacon_int(dev, conf->beacon_int);
3375
fda9abcf
MB		 3376 if (!!conf->radio_enabled != phy->radio_on) {
3377 if (conf->radio_enabled) {
ef1a628d 3378 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
fda9abcf
MB		 3379 b43info(dev->wl, "Radio turned on by software\n");
3380 if (!dev->radio_hw_enable) {
3381 b43info(dev->wl, "The hardware RF-kill button "
3382 "still turns the radio physically off. "
3383 "Press the button to turn it on.\n");
3384 }
3385 } else {
ef1a628d 3386 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
fda9abcf
MB		 3387 b43info(dev->wl, "Radio turned off by software\n");
3388 }
3389 }
3390
d10d0e57
MB		 3391out_mac_enable:
3392 b43_mac_enable(dev);
3393out_unlock_mutex:
e4d6b795
MB		 3394 mutex_unlock(&wl->mutex);
3395
3396 return err;
3397}
3398
c7ab5ef9
JB		 3399static void b43_update_basic_rates(struct b43_wldev *dev, u64 brates)
3400{
3401 struct ieee80211_supported_band *sband =
3402 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3403 struct ieee80211_rate *rate;
3404 int i;
3405 u16 basic, direct, offset, basic_offset, rateptr;
3406
3407 for (i = 0; i < sband->n_bitrates; i++) {
3408 rate = &sband->bitrates[i];
3409
3410 if (b43_is_cck_rate(rate->hw_value)) {
3411 direct = B43_SHM_SH_CCKDIRECT;
3412 basic = B43_SHM_SH_CCKBASIC;
3413 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3414 offset &= 0xF;
3415 } else {
3416 direct = B43_SHM_SH_OFDMDIRECT;
3417 basic = B43_SHM_SH_OFDMBASIC;
3418 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3419 offset &= 0xF;
3420 }
3421
3422 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3423
3424 if (b43_is_cck_rate(rate->hw_value)) {
3425 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3426 basic_offset &= 0xF;
3427 } else {
3428 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3429 basic_offset &= 0xF;
3430 }
3431
3432 /*
3433 * Get the pointer that we need to point to
3434 * from the direct map
3435 */
3436 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3437 direct + 2 * basic_offset);
3438 /* and write it to the basic map */
3439 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3440 rateptr);
3441 }
3442}
3443
3444static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3445 struct ieee80211_vif *vif,
3446 struct ieee80211_bss_conf *conf,
3447 u32 changed)
3448{
3449 struct b43_wl *wl = hw_to_b43_wl(hw);
3450 struct b43_wldev *dev;
c7ab5ef9
JB		 3451
3452 mutex_lock(&wl->mutex);
3453
3454 dev = wl->current_dev;
d10d0e57 3455 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3456 goto out_unlock_mutex;
c7ab5ef9
JB		 3457 b43_mac_suspend(dev);
3458
3459 if (changed & BSS_CHANGED_BASIC_RATES)
3460 b43_update_basic_rates(dev, conf->basic_rates);
3461
3462 if (changed & BSS_CHANGED_ERP_SLOT) {
3463 if (conf->use_short_slot)
3464 b43_short_slot_timing_enable(dev);
3465 else
3466 b43_short_slot_timing_disable(dev);
3467 }
3468
3469 b43_mac_enable(dev);
d10d0e57 3470out_unlock_mutex:
c7ab5ef9
JB		 3471 mutex_unlock(&wl->mutex);
3472
3473 return;
3474}
3475
40faacc4 3476static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4150c572
JB		 3477 const u8 *local_addr, const u8 *addr,
3478 struct ieee80211_key_conf *key)
e4d6b795
MB		 3479{
3480 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3481 struct b43_wldev *dev;
e4d6b795
MB		 3482 unsigned long flags;
3483 u8 algorithm;
3484 u8 index;
c6dfc9a8 3485 int err;
e4d6b795
MB		 3486
3487 if (modparam_nohwcrypt)
3488 return -ENOSPC; /* User disabled HW-crypto */
3489
c6dfc9a8
MB		 3490 mutex_lock(&wl->mutex);
3491 spin_lock_irqsave(&wl->irq_lock, flags);
3492
3493 dev = wl->current_dev;
3494 err = -ENODEV;
3495 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3496 goto out_unlock;
3497
68217832
MB		 3498 if (dev->fw.pcm_request_failed) {
3499 /* We don't have firmware for the crypto engine.
3500 * Must use software-crypto. */
3501 err = -EOPNOTSUPP;
3502 goto out_unlock;
3503 }
3504
c6dfc9a8 3505 err = -EINVAL;
e4d6b795 3506 switch (key->alg) {
e4d6b795
MB		 3507 case ALG_WEP:
3508 if (key->keylen == 5)
3509 algorithm = B43_SEC_ALGO_WEP40;
3510 else
3511 algorithm = B43_SEC_ALGO_WEP104;
3512 break;
3513 case ALG_TKIP:
3514 algorithm = B43_SEC_ALGO_TKIP;
3515 break;
3516 case ALG_CCMP:
3517 algorithm = B43_SEC_ALGO_AES;
3518 break;
3519 default:
3520 B43_WARN_ON(1);
c6dfc9a8 3521 goto out_unlock;
e4d6b795 3522 }
e4d6b795
MB		 3523 index = (u8) (key->keyidx);
3524 if (index > 3)
e4d6b795 3525 goto out_unlock;
e4d6b795
MB		 3526
3527 switch (cmd) {
3528 case SET_KEY:
3529 if (algorithm == B43_SEC_ALGO_TKIP) {
3530 /* FIXME: No TKIP hardware encryption for now. */
3531 err = -EOPNOTSUPP;
3532 goto out_unlock;
3533 }
3534
3535 if (is_broadcast_ether_addr(addr)) {
3536 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3537 err = b43_key_write(dev, index, algorithm,
3538 key->key, key->keylen, NULL, key);
3539 } else {
3540 /*
3541 * either pairwise key or address is 00:00:00:00:00:00
3542 * for transmit-only keys
3543 */
3544 err = b43_key_write(dev, -1, algorithm,
3545 key->key, key->keylen, addr, key);
3546 }
3547 if (err)
3548 goto out_unlock;
3549
3550 if (algorithm == B43_SEC_ALGO_WEP40 ||
3551 algorithm == B43_SEC_ALGO_WEP104) {
3552 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3553 } else {
3554 b43_hf_write(dev,
3555 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3556 }
3557 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3558 break;
3559 case DISABLE_KEY: {
3560 err = b43_key_clear(dev, key->hw_key_idx);
3561 if (err)
3562 goto out_unlock;
3563 break;
3564 }
3565 default:
3566 B43_WARN_ON(1);
3567 }
3568out_unlock:
3569 spin_unlock_irqrestore(&wl->irq_lock, flags);
3570 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3571 if (!err) {
3572 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3573 "mac: %pM\n",
e4d6b795 3574 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
e174961c 3575 addr);
e4d6b795
MB		 3576 }
3577 return err;
3578}
3579
40faacc4
MB		 3580static void b43_op_configure_filter(struct ieee80211_hw *hw,
3581 unsigned int changed, unsigned int *fflags,
3582 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3583{
3584 struct b43_wl *wl = hw_to_b43_wl(hw);
3585 struct b43_wldev *dev = wl->current_dev;
3586 unsigned long flags;
3587
4150c572
JB		 3588 if (!dev) {
3589 *fflags = 0;
e4d6b795 3590 return;
e4d6b795 3591 }
4150c572
JB		 3592
3593 spin_lock_irqsave(&wl->irq_lock, flags);
3594 *fflags &= FIF_PROMISC_IN_BSS |
3595 FIF_ALLMULTI |
3596 FIF_FCSFAIL |
3597 FIF_PLCPFAIL |
3598 FIF_CONTROL |
3599 FIF_OTHER_BSS |
3600 FIF_BCN_PRBRESP_PROMISC;
3601
3602 changed &= FIF_PROMISC_IN_BSS |
3603 FIF_ALLMULTI |
3604 FIF_FCSFAIL |
3605 FIF_PLCPFAIL |
3606 FIF_CONTROL |
3607 FIF_OTHER_BSS |
3608 FIF_BCN_PRBRESP_PROMISC;
3609
3610 wl->filter_flags = *fflags;
3611
3612 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3613 b43_adjust_opmode(dev);
e4d6b795
MB		 3614 spin_unlock_irqrestore(&wl->irq_lock, flags);
3615}
3616
40faacc4 3617static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3618 struct ieee80211_vif *vif,
40faacc4 3619 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3620{
3621 struct b43_wl *wl = hw_to_b43_wl(hw);
3622 struct b43_wldev *dev = wl->current_dev;
3623 unsigned long flags;
3624
3625 if (!dev)
3626 return -ENODEV;
3627 mutex_lock(&wl->mutex);
3628 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3629 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3630 if (conf->bssid)
3631 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3632 else
3633 memset(wl->bssid, 0, ETH_ALEN);
3634 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
05c914fe
JB		 3635 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3636 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
9d139c81 3637 B43_WARN_ON(vif->type != wl->if_type);
9d139c81
JB		 3638 if (conf->changed & IEEE80211_IFCC_BEACON)
3639 b43_update_templates(wl);
05c914fe 3640 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 3641 if (conf->changed & IEEE80211_IFCC_BEACON)
3642 b43_update_templates(wl);
e4d6b795 3643 }
4150c572 3644 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3645 }
3646 spin_unlock_irqrestore(&wl->irq_lock, flags);
3647 mutex_unlock(&wl->mutex);
3648
3649 return 0;
3650}
3651
3652/* Locking: wl->mutex */
3653static void b43_wireless_core_stop(struct b43_wldev *dev)
3654{
3655 struct b43_wl *wl = dev->wl;
3656 unsigned long flags;
3657
3658 if (b43_status(dev) < B43_STAT_STARTED)
3659 return;
a19d12d7
SB		 3660
3661 /* Disable and sync interrupts. We must do this before than
3662 * setting the status to INITIALIZED, as the interrupt handler
3663 * won't care about IRQs then. */
3664 spin_lock_irqsave(&wl->irq_lock, flags);
3665 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3666 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3667 spin_unlock_irqrestore(&wl->irq_lock, flags);
3668 b43_synchronize_irq(dev);
3669
21a75d77 3670 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3671 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3672 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3673
5100d5ac 3674 b43_pio_stop(dev);
e4d6b795
MB		 3675 mutex_unlock(&wl->mutex);
3676 /* Must unlock as it would otherwise deadlock. No races here.
3677 * Cancel the possibly running self-rearming periodic work. */
3678 cancel_delayed_work_sync(&dev->periodic_work);
3679 mutex_lock(&wl->mutex);
3680
e4d6b795
MB		 3681 b43_mac_suspend(dev);
3682 free_irq(dev->dev->irq, dev);
3683 b43dbg(wl, "Wireless interface stopped\n");
3684}
3685
3686/* Locking: wl->mutex */
3687static int b43_wireless_core_start(struct b43_wldev *dev)
3688{
3689 int err;
3690
3691 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3692
3693 drain_txstatus_queue(dev);
3694 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3695 IRQF_SHARED, KBUILD_MODNAME, dev);
3696 if (err) {
3697 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3698 goto out;
3699 }
3700
3701 /* We are ready to run. */
3702 b43_set_status(dev, B43_STAT_STARTED);
3703
3704 /* Start data flow (TX/RX). */
3705 b43_mac_enable(dev);
3706 b43_interrupt_enable(dev, dev->irq_savedstate);
e4d6b795
MB		 3707
3708 /* Start maintainance work */
3709 b43_periodic_tasks_setup(dev);
3710
3711 b43dbg(dev->wl, "Wireless interface started\n");
3712 out:
3713 return err;
3714}
3715
3716/* Get PHY and RADIO versioning numbers */
3717static int b43_phy_versioning(struct b43_wldev *dev)
3718{
3719 struct b43_phy *phy = &dev->phy;
3720 u32 tmp;
3721 u8 analog_type;
3722 u8 phy_type;
3723 u8 phy_rev;
3724 u16 radio_manuf;
3725 u16 radio_ver;
3726 u16 radio_rev;
3727 int unsupported = 0;
3728
3729 /* Get PHY versioning */
3730 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3731 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3732 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3733 phy_rev = (tmp & B43_PHYVER_VERSION);
3734 switch (phy_type) {
3735 case B43_PHYTYPE_A:
3736 if (phy_rev >= 4)
3737 unsupported = 1;
3738 break;
3739 case B43_PHYTYPE_B:
3740 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3741 && phy_rev != 7)
3742 unsupported = 1;
3743 break;
3744 case B43_PHYTYPE_G:
013978b6 3745 if (phy_rev > 9)
e4d6b795
MB		 3746 unsupported = 1;
3747 break;
d5c71e46
MB		 3748#ifdef CONFIG_B43_NPHY
3749 case B43_PHYTYPE_N:
3750 if (phy_rev > 1)
3751 unsupported = 1;
3752 break;
3753#endif
e4d6b795
MB		 3754 default:
3755 unsupported = 1;
3756 };
3757 if (unsupported) {
3758 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3759 "(Analog %u, Type %u, Revision %u)\n",
3760 analog_type, phy_type, phy_rev);
3761 return -EOPNOTSUPP;
3762 }
3763 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3764 analog_type, phy_type, phy_rev);
3765
3766 /* Get RADIO versioning */
3767 if (dev->dev->bus->chip_id == 0x4317) {
3768 if (dev->dev->bus->chip_rev == 0)
3769 tmp = 0x3205017F;
3770 else if (dev->dev->bus->chip_rev == 1)
3771 tmp = 0x4205017F;
3772 else
3773 tmp = 0x5205017F;
3774 } else {
3775 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3776 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3777 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3778 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3779 }
3780 radio_manuf = (tmp & 0x00000FFF);
3781 radio_ver = (tmp & 0x0FFFF000) >> 12;
3782 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3783 if (radio_manuf != 0x17F /* Broadcom */)
3784 unsupported = 1;
e4d6b795
MB		 3785 switch (phy_type) {
3786 case B43_PHYTYPE_A:
3787 if (radio_ver != 0x2060)
3788 unsupported = 1;
3789 if (radio_rev != 1)
3790 unsupported = 1;
3791 if (radio_manuf != 0x17F)
3792 unsupported = 1;
3793 break;
3794 case B43_PHYTYPE_B:
3795 if ((radio_ver & 0xFFF0) != 0x2050)
3796 unsupported = 1;
3797 break;
3798 case B43_PHYTYPE_G:
3799 if (radio_ver != 0x2050)
3800 unsupported = 1;
3801 break;
96c755a3 3802 case B43_PHYTYPE_N:
243dcfcc 3803 if (radio_ver != 0x2055)
96c755a3
MB		 3804 unsupported = 1;
3805 break;
e4d6b795
MB		 3806 default:
3807 B43_WARN_ON(1);
3808 }
3809 if (unsupported) {
3810 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3811 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3812 radio_manuf, radio_ver, radio_rev);
3813 return -EOPNOTSUPP;
3814 }
3815 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3816 radio_manuf, radio_ver, radio_rev);
3817
3818 phy->radio_manuf = radio_manuf;
3819 phy->radio_ver = radio_ver;
3820 phy->radio_rev = radio_rev;
3821
3822 phy->analog = analog_type;
3823 phy->type = phy_type;
3824 phy->rev = phy_rev;
3825
3826 return 0;
3827}
3828
3829static void setup_struct_phy_for_init(struct b43_wldev *dev,
3830 struct b43_phy *phy)
3831{
e4d6b795 3832 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3833 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3834 /* PHY TX errors counter. */
3835 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
e4d6b795
MB		 3836}
3837
3838static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3839{
aa6c7ae2
MB		 3840 dev->dfq_valid = 0;
3841
6a724d68
MB		 3842 /* Assume the radio is enabled. If it's not enabled, the state will
3843 * immediately get fixed on the first periodic work run. */
3844 dev->radio_hw_enable = 1;
e4d6b795
MB		 3845
3846 /* Stats */
3847 memset(&dev->stats, 0, sizeof(dev->stats));
3848
3849 setup_struct_phy_for_init(dev, &dev->phy);
3850
3851 /* IRQ related flags */
3852 dev->irq_reason = 0;
3853 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3854 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3855
3856 dev->mac_suspended = 1;
3857
3858 /* Noise calculation context */
3859 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3860}
3861
3862static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3863{
3864 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 3865 u64 hf;
e4d6b795 3866
1855ba78
MB		 3867 if (!modparam_btcoex)
3868 return;
95de2841 3869 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 3870 return;
3871 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3872 return;
3873
3874 hf = b43_hf_read(dev);
95de2841 3875 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 3876 hf |= B43_HF_BTCOEXALT;
3877 else
3878 hf |= B43_HF_BTCOEX;
3879 b43_hf_write(dev, hf);
e4d6b795
MB		 3880}
3881
3882static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 3883{
3884 if (!modparam_btcoex)
3885 return;
3886 //TODO
e4d6b795
MB		 3887}
3888
3889static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3890{
3891#ifdef CONFIG_SSB_DRIVER_PCICORE
3892 struct ssb_bus *bus = dev->dev->bus;
3893 u32 tmp;
3894
3895 if (bus->pcicore.dev &&
3896 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3897 bus->pcicore.dev->id.revision <= 5) {
3898 /* IMCFGLO timeouts workaround. */
3899 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3900 tmp &= ~SSB_IMCFGLO_REQTO;
3901 tmp &= ~SSB_IMCFGLO_SERTO;
3902 switch (bus->bustype) {
3903 case SSB_BUSTYPE_PCI:
3904 case SSB_BUSTYPE_PCMCIA:
3905 tmp |= 0x32;
3906 break;
3907 case SSB_BUSTYPE_SSB:
3908 tmp |= 0x53;
3909 break;
3910 }
3911 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3912 }
3913#endif /* CONFIG_SSB_DRIVER_PCICORE */
3914}
3915
d59f720d
MB		 3916static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3917{
3918 u16 pu_delay;
3919
3920 /* The time value is in microseconds. */
3921 if (dev->phy.type == B43_PHYTYPE_A)
3922 pu_delay = 3700;
3923 else
3924 pu_delay = 1050;
05c914fe 3925 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 3926 pu_delay = 500;
3927 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3928 pu_delay = max(pu_delay, (u16)2400);
3929
3930 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3931}
3932
3933/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3934static void b43_set_pretbtt(struct b43_wldev *dev)
3935{
3936 u16 pretbtt;
3937
3938 /* The time value is in microseconds. */
05c914fe 3939 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 3940 pretbtt = 2;
3941 } else {
3942 if (dev->phy.type == B43_PHYTYPE_A)
3943 pretbtt = 120;
3944 else
3945 pretbtt = 250;
3946 }
3947 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3948 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3949}
3950
e4d6b795
MB		 3951/* Shutdown a wireless core */
3952/* Locking: wl->mutex */
3953static void b43_wireless_core_exit(struct b43_wldev *dev)
3954{
1f7d87b0 3955 u32 macctl;
e4d6b795
MB		 3956
3957 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3958 if (b43_status(dev) != B43_STAT_INITIALIZED)
3959 return;
3960 b43_set_status(dev, B43_STAT_UNINIT);
3961
1f7d87b0
MB		 3962 /* Stop the microcode PSM. */
3963 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3964 macctl &= ~B43_MACCTL_PSM_RUN;
3965 macctl |= B43_MACCTL_PSM_JMP0;
3966 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3967
3506e0c4
RW		 3968 if (!dev->suspend_in_progress) {
3969 b43_leds_exit(dev);
b844eba2 3970 b43_rng_exit(dev->wl);
3506e0c4 3971 }
e4d6b795 3972 b43_dma_free(dev);
5100d5ac 3973 b43_pio_free(dev);
e4d6b795 3974 b43_chip_exit(dev);
cb24f57f 3975 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 3976 if (dev->wl->current_beacon) {
3977 dev_kfree_skb_any(dev->wl->current_beacon);
3978 dev->wl->current_beacon = NULL;
3979 }
3980
e4d6b795
MB		 3981 ssb_device_disable(dev->dev, 0);
3982 ssb_bus_may_powerdown(dev->dev->bus);
3983}
3984
3985/* Initialize a wireless core */
3986static int b43_wireless_core_init(struct b43_wldev *dev)
3987{
3988 struct b43_wl *wl = dev->wl;
3989 struct ssb_bus *bus = dev->dev->bus;
3990 struct ssb_sprom *sprom = &bus->sprom;
3991 struct b43_phy *phy = &dev->phy;
3992 int err;
a259d6a4
MB		 3993 u64 hf;
3994 u32 tmp;
e4d6b795
MB		 3995
3996 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3997
3998 err = ssb_bus_powerup(bus, 0);
3999 if (err)
4000 goto out;
4001 if (!ssb_device_is_enabled(dev->dev)) {
4002 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4003 b43_wireless_core_reset(dev, tmp);
4004 }
4005
fb11137a 4006 /* Reset all data structures. */
e4d6b795 4007 setup_struct_wldev_for_init(dev);
fb11137a 4008 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4009
4010 /* Enable IRQ routing to this device. */
4011 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4012
4013 b43_imcfglo_timeouts_workaround(dev);
4014 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4015 if (phy->ops->prepare_hardware) {
4016 err = phy->ops->prepare_hardware(dev);
ef1a628d 4017 if (err)
fb11137a 4018 goto err_busdown;
ef1a628d 4019 }
e4d6b795
MB		 4020 err = b43_chip_init(dev);
4021 if (err)
fb11137a 4022 goto err_busdown;
e4d6b795
MB		 4023 b43_shm_write16(dev, B43_SHM_SHARED,
4024 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4025 hf = b43_hf_read(dev);
4026 if (phy->type == B43_PHYTYPE_G) {
4027 hf |= B43_HF_SYMW;
4028 if (phy->rev == 1)
4029 hf |= B43_HF_GDCW;
95de2841 4030 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 4031 hf |= B43_HF_OFDMPABOOST;
4032 } else if (phy->type == B43_PHYTYPE_B) {
4033 hf |= B43_HF_SYMW;
4034 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4035 hf &= ~B43_HF_GDCW;
4036 }
4037 b43_hf_write(dev, hf);
4038
74cfdba7
MB		 4039 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4040 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4041 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4042 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4043
4044 /* Disable sending probe responses from firmware.
4045 * Setting the MaxTime to one usec will always trigger
4046 * a timeout, so we never send any probe resp.
4047 * A timeout of zero is infinite. */
4048 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4049
4050 b43_rate_memory_init(dev);
5042c507 4051 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4052
4053 /* Minimum Contention Window */
4054 if (phy->type == B43_PHYTYPE_B) {
4055 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4056 } else {
4057 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4058 }
4059 /* Maximum Contention Window */
4060 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4061
5100d5ac
MB		 4062 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4063 dev->__using_pio_transfers = 1;
4064 err = b43_pio_init(dev);
4065 } else {
4066 dev->__using_pio_transfers = 0;
4067 err = b43_dma_init(dev);
4068 }
e4d6b795
MB		 4069 if (err)
4070 goto err_chip_exit;
03b29773 4071 b43_qos_init(dev);
d59f720d 4072 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4073 b43_bluetooth_coext_enable(dev);
4074
4075 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 4076 b43_upload_card_macaddress(dev);
e4d6b795 4077 b43_security_init(dev);
3506e0c4
RW		 4078 if (!dev->suspend_in_progress)
4079 b43_rng_init(wl);
e4d6b795
MB		 4080
4081 b43_set_status(dev, B43_STAT_INITIALIZED);
4082
3506e0c4
RW		 4083 if (!dev->suspend_in_progress)
4084 b43_leds_init(dev);
1a8d1227 4085out:
e4d6b795
MB		 4086 return err;
4087
ef1a628d 4088err_chip_exit:
e4d6b795 4089 b43_chip_exit(dev);
ef1a628d 4090err_busdown:
e4d6b795
MB		 4091 ssb_bus_may_powerdown(bus);
4092 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4093 return err;
4094}
4095
40faacc4
MB		 4096static int b43_op_add_interface(struct ieee80211_hw *hw,
4097 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4098{
4099 struct b43_wl *wl = hw_to_b43_wl(hw);
4100 struct b43_wldev *dev;
4101 unsigned long flags;
4102 int err = -EOPNOTSUPP;
4150c572
JB		 4103
4104 /* TODO: allow WDS/AP devices to coexist */
4105
05c914fe
JB		 4106 if (conf->type != NL80211_IFTYPE_AP &&
4107 conf->type != NL80211_IFTYPE_MESH_POINT &&
4108 conf->type != NL80211_IFTYPE_STATION &&
4109 conf->type != NL80211_IFTYPE_WDS &&
4110 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4111 return -EOPNOTSUPP;
e4d6b795
MB		 4112
4113 mutex_lock(&wl->mutex);
4150c572 4114 if (wl->operating)
e4d6b795
MB		 4115 goto out_mutex_unlock;
4116
4117 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4118
4119 dev = wl->current_dev;
4150c572 4120 wl->operating = 1;
32bfd35d 4121 wl->vif = conf->vif;
4150c572
JB		 4122 wl->if_type = conf->type;
4123 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4124
4125 spin_lock_irqsave(&wl->irq_lock, flags);
4126 b43_adjust_opmode(dev);
d59f720d
MB		 4127 b43_set_pretbtt(dev);
4128 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4129 b43_upload_card_macaddress(dev);
4130 spin_unlock_irqrestore(&wl->irq_lock, flags);
4131
4132 err = 0;
4133 out_mutex_unlock:
4134 mutex_unlock(&wl->mutex);
4135
4136 return err;
4137}
4138
40faacc4
MB		 4139static void b43_op_remove_interface(struct ieee80211_hw *hw,
4140 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4141{
4142 struct b43_wl *wl = hw_to_b43_wl(hw);
4143 struct b43_wldev *dev = wl->current_dev;
4144 unsigned long flags;
4145
4146 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4147
4148 mutex_lock(&wl->mutex);
4149
4150 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4151 B43_WARN_ON(wl->vif != conf->vif);
4152 wl->vif = NULL;
4150c572
JB		 4153
4154 wl->operating = 0;
4155
4156 spin_lock_irqsave(&wl->irq_lock, flags);
4157 b43_adjust_opmode(dev);
4158 memset(wl->mac_addr, 0, ETH_ALEN);
4159 b43_upload_card_macaddress(dev);
4160 spin_unlock_irqrestore(&wl->irq_lock, flags);
4161
4162 mutex_unlock(&wl->mutex);
4163}
4164
40faacc4 4165static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4166{
4167 struct b43_wl *wl = hw_to_b43_wl(hw);
4168 struct b43_wldev *dev = wl->current_dev;
4169 int did_init = 0;
923403b8 4170 int err = 0;
1946a2c3 4171 bool do_rfkill_exit = 0;
4150c572 4172
7be1bb6b
MB		 4173 /* Kill all old instance specific information to make sure
4174 * the card won't use it in the short timeframe between start
4175 * and mac80211 reconfiguring it. */
4176 memset(wl->bssid, 0, ETH_ALEN);
4177 memset(wl->mac_addr, 0, ETH_ALEN);
4178 wl->filter_flags = 0;
4179 wl->radiotap_enabled = 0;
e6f5b934 4180 b43_qos_clear(wl);
6b4bec01
MB		 4181 wl->beacon0_uploaded = 0;
4182 wl->beacon1_uploaded = 0;
4183 wl->beacon_templates_virgin = 1;
7be1bb6b 4184
1a8d1227
LF		 4185 /* First register RFkill.
4186 * LEDs that are registered later depend on it. */
4187 b43_rfkill_init(dev);
4188
4150c572
JB		 4189 mutex_lock(&wl->mutex);
4190
e4d6b795
MB		 4191 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4192 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4193 if (err) {
4194 do_rfkill_exit = 1;
e4d6b795 4195 goto out_mutex_unlock;
1946a2c3 4196 }
e4d6b795
MB		 4197 did_init = 1;
4198 }
4150c572 4199
e4d6b795
MB		 4200 if (b43_status(dev) < B43_STAT_STARTED) {
4201 err = b43_wireless_core_start(dev);
4202 if (err) {
4203 if (did_init)
4204 b43_wireless_core_exit(dev);
1946a2c3 4205 do_rfkill_exit = 1;
e4d6b795
MB		 4206 goto out_mutex_unlock;
4207 }
4208 }
4209
4150c572 4210 out_mutex_unlock:
e4d6b795
MB		 4211 mutex_unlock(&wl->mutex);
4212
1946a2c3
MB		 4213 if (do_rfkill_exit)
4214 b43_rfkill_exit(dev);
4215
e4d6b795
MB		 4216 return err;
4217}
4218
40faacc4 4219static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4220{
4221 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4222 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4223
1a8d1227 4224 b43_rfkill_exit(dev);
a82d9922 4225 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4226
e4d6b795 4227 mutex_lock(&wl->mutex);
4150c572
JB		 4228 if (b43_status(dev) >= B43_STAT_STARTED)
4229 b43_wireless_core_stop(dev);
4230 b43_wireless_core_exit(dev);
e4d6b795 4231 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4232
4233 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4234}
4235
17741cdc
JB		 4236static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4237 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4238{
4239 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4240 unsigned long flags;
e66fee6a 4241
d4df6f1a 4242 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4243 b43_update_templates(wl);
d4df6f1a 4244 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4245
4246 return 0;
4247}
4248
38968d09
JB		 4249static void b43_op_sta_notify(struct ieee80211_hw *hw,
4250 struct ieee80211_vif *vif,
4251 enum sta_notify_cmd notify_cmd,
17741cdc 4252 struct ieee80211_sta *sta)
38968d09
JB		 4253{
4254 struct b43_wl *wl = hw_to_b43_wl(hw);
4255
4256 B43_WARN_ON(!vif || wl->vif != vif);
4257}
4258
e4d6b795 4259static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4260 .tx = b43_op_tx,
4261 .conf_tx = b43_op_conf_tx,
4262 .add_interface = b43_op_add_interface,
4263 .remove_interface = b43_op_remove_interface,
4264 .config = b43_op_config,
c7ab5ef9 4265 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4266 .config_interface = b43_op_config_interface,
4267 .configure_filter = b43_op_configure_filter,
4268 .set_key = b43_op_set_key,
4269 .get_stats = b43_op_get_stats,
4270 .get_tx_stats = b43_op_get_tx_stats,
4271 .start = b43_op_start,
4272 .stop = b43_op_stop,
e66fee6a 4273 .set_tim = b43_op_beacon_set_tim,
38968d09 4274 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4275};
4276
4277/* Hard-reset the chip. Do not call this directly.
4278 * Use b43_controller_restart()
4279 */
4280static void b43_chip_reset(struct work_struct *work)
4281{
4282 struct b43_wldev *dev =
4283 container_of(work, struct b43_wldev, restart_work);
4284 struct b43_wl *wl = dev->wl;
4285 int err = 0;
4286 int prev_status;
4287
4288 mutex_lock(&wl->mutex);
4289
4290 prev_status = b43_status(dev);
4291 /* Bring the device down... */
4292 if (prev_status >= B43_STAT_STARTED)
4293 b43_wireless_core_stop(dev);
4294 if (prev_status >= B43_STAT_INITIALIZED)
4295 b43_wireless_core_exit(dev);
4296
4297 /* ...and up again. */
4298 if (prev_status >= B43_STAT_INITIALIZED) {
4299 err = b43_wireless_core_init(dev);
4300 if (err)
4301 goto out;
4302 }
4303 if (prev_status >= B43_STAT_STARTED) {
4304 err = b43_wireless_core_start(dev);
4305 if (err) {
4306 b43_wireless_core_exit(dev);
4307 goto out;
4308 }
4309 }
3bf0a32e
MB		 4310out:
4311 if (err)
4312 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4313 mutex_unlock(&wl->mutex);
4314 if (err)
4315 b43err(wl, "Controller restart FAILED\n");
4316 else
4317 b43info(wl, "Controller restarted\n");
4318}
4319
bb1eeff1 4320static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4321 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4322{
4323 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4324
bb1eeff1
MB		 4325 if (have_2ghz_phy)
4326 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4327 if (dev->phy.type == B43_PHYTYPE_N) {
4328 if (have_5ghz_phy)
4329 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4330 } else {
4331 if (have_5ghz_phy)
4332 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4333 }
96c755a3 4334
bb1eeff1
MB		 4335 dev->phy.supports_2ghz = have_2ghz_phy;
4336 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4337
4338 return 0;
4339}
4340
4341static void b43_wireless_core_detach(struct b43_wldev *dev)
4342{
4343 /* We release firmware that late to not be required to re-request
4344 * is all the time when we reinit the core. */
4345 b43_release_firmware(dev);
fb11137a 4346 b43_phy_free(dev);
e4d6b795
MB		 4347}
4348
4349static int b43_wireless_core_attach(struct b43_wldev *dev)
4350{
4351 struct b43_wl *wl = dev->wl;
4352 struct ssb_bus *bus = dev->dev->bus;
4353 struct pci_dev *pdev = bus->host_pci;
4354 int err;
96c755a3 4355 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4356 u32 tmp;
4357
4358 /* Do NOT do any device initialization here.
4359 * Do it in wireless_core_init() instead.
4360 * This function is for gathering basic information about the HW, only.
4361 * Also some structs may be set up here. But most likely you want to have
4362 * that in core_init(), too.
4363 */
4364
4365 err = ssb_bus_powerup(bus, 0);
4366 if (err) {
4367 b43err(wl, "Bus powerup failed\n");
4368 goto out;
4369 }
4370 /* Get the PHY type. */
4371 if (dev->dev->id.revision >= 5) {
4372 u32 tmshigh;
4373
4374 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4375 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4376 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4377 } else
96c755a3 4378 B43_WARN_ON(1);
e4d6b795 4379
96c755a3 4380 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4381 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4382 b43_wireless_core_reset(dev, tmp);
4383
4384 err = b43_phy_versioning(dev);
4385 if (err)
21954c36 4386 goto err_powerdown;
e4d6b795
MB		 4387 /* Check if this device supports multiband. */
4388 if (!pdev ||
4389 (pdev->device != 0x4312 &&
4390 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4391 /* No multiband support. */
96c755a3
MB		 4392 have_2ghz_phy = 0;
4393 have_5ghz_phy = 0;
e4d6b795
MB		 4394 switch (dev->phy.type) {
4395 case B43_PHYTYPE_A:
96c755a3 4396 have_5ghz_phy = 1;
e4d6b795
MB		 4397 break;
4398 case B43_PHYTYPE_G:
96c755a3
MB		 4399 case B43_PHYTYPE_N:
4400 have_2ghz_phy = 1;
e4d6b795
MB		 4401 break;
4402 default:
4403 B43_WARN_ON(1);
4404 }
4405 }
96c755a3
MB		 4406 if (dev->phy.type == B43_PHYTYPE_A) {
4407 /* FIXME */
4408 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4409 err = -EOPNOTSUPP;
4410 goto err_powerdown;
4411 }
2e35af14
MB		 4412 if (1 /* disable A-PHY */) {
4413 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4414 if (dev->phy.type != B43_PHYTYPE_N) {
4415 have_2ghz_phy = 1;
4416 have_5ghz_phy = 0;
4417 }
4418 }
4419
fb11137a
MB		 4420 err = b43_phy_allocate(dev);
4421 if (err)
4422 goto err_powerdown;
4423
96c755a3 4424 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4425 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4426 b43_wireless_core_reset(dev, tmp);
4427
4428 err = b43_validate_chipaccess(dev);
4429 if (err)
fb11137a 4430 goto err_phy_free;
bb1eeff1 4431 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4432 if (err)
fb11137a 4433 goto err_phy_free;
e4d6b795
MB		 4434
4435 /* Now set some default "current_dev" */
4436 if (!wl->current_dev)
4437 wl->current_dev = dev;
4438 INIT_WORK(&dev->restart_work, b43_chip_reset);
4439
cb24f57f 4440 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4441 ssb_device_disable(dev->dev, 0);
4442 ssb_bus_may_powerdown(bus);
4443
4444out:
4445 return err;
4446
fb11137a
MB		 4447err_phy_free:
4448 b43_phy_free(dev);
e4d6b795
MB		 4449err_powerdown:
4450 ssb_bus_may_powerdown(bus);
4451 return err;
4452}
4453
4454static void b43_one_core_detach(struct ssb_device *dev)
4455{
4456 struct b43_wldev *wldev;
4457 struct b43_wl *wl;
4458
3bf0a32e
MB		 4459 /* Do not cancel ieee80211-workqueue based work here.
4460 * See comment in b43_remove(). */
4461
e4d6b795
MB		 4462 wldev = ssb_get_drvdata(dev);
4463 wl = wldev->wl;
e4d6b795
MB		 4464 b43_debugfs_remove_device(wldev);
4465 b43_wireless_core_detach(wldev);
4466 list_del(&wldev->list);
4467 wl->nr_devs--;
4468 ssb_set_drvdata(dev, NULL);
4469 kfree(wldev);
4470}
4471
4472static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4473{
4474 struct b43_wldev *wldev;
4475 struct pci_dev *pdev;
4476 int err = -ENOMEM;
4477
4478 if (!list_empty(&wl->devlist)) {
4479 /* We are not the first core on this chip. */
4480 pdev = dev->bus->host_pci;
4481 /* Only special chips support more than one wireless
4482 * core, although some of the other chips have more than
4483 * one wireless core as well. Check for this and
4484 * bail out early.
4485 */
4486 if (!pdev ||
4487 ((pdev->device != 0x4321) &&
4488 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4489 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4490 return -ENODEV;
4491 }
4492 }
4493
4494 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4495 if (!wldev)
4496 goto out;
4497
4498 wldev->dev = dev;
4499 wldev->wl = wl;
4500 b43_set_status(wldev, B43_STAT_UNINIT);
4501 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4502 tasklet_init(&wldev->isr_tasklet,
4503 (void (*)(unsigned long))b43_interrupt_tasklet,
4504 (unsigned long)wldev);
e4d6b795
MB		 4505 INIT_LIST_HEAD(&wldev->list);
4506
4507 err = b43_wireless_core_attach(wldev);
4508 if (err)
4509 goto err_kfree_wldev;
4510
4511 list_add(&wldev->list, &wl->devlist);
4512 wl->nr_devs++;
4513 ssb_set_drvdata(dev, wldev);
4514 b43_debugfs_add_device(wldev);
4515
4516 out:
4517 return err;
4518
4519 err_kfree_wldev:
4520 kfree(wldev);
4521 return err;
4522}
4523
9fc38458
MB		 4524#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4525 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4526 (pdev->device == _device) && \
4527 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4528 (pdev->subsystem_device == _subdevice) )
4529
e4d6b795
MB		 4530static void b43_sprom_fixup(struct ssb_bus *bus)
4531{
1855ba78
MB		 4532 struct pci_dev *pdev;
4533
e4d6b795
MB		 4534 /* boardflags workarounds */
4535 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4536 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4537 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4538 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4539 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4540 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4541 if (bus->bustype == SSB_BUSTYPE_PCI) {
4542 pdev = bus->host_pci;
9fc38458 4543 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4544 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4545 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4546 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4547 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4548 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4549 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4550 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4551 }
e4d6b795
MB		 4552}
4553
4554static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4555{
4556 struct ieee80211_hw *hw = wl->hw;
4557
4558 ssb_set_devtypedata(dev, NULL);
4559 ieee80211_free_hw(hw);
4560}
4561
4562static int b43_wireless_init(struct ssb_device *dev)
4563{
4564 struct ssb_sprom *sprom = &dev->bus->sprom;
4565 struct ieee80211_hw *hw;
4566 struct b43_wl *wl;
4567 int err = -ENOMEM;
4568
4569 b43_sprom_fixup(dev->bus);
4570
4571 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4572 if (!hw) {
4573 b43err(NULL, "Could not allocate ieee80211 device\n");
4574 goto out;
4575 }
4576
4577 /* fill hw info */
605a0bd6 4578 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4579 IEEE80211_HW_SIGNAL_DBM |
4580 IEEE80211_HW_NOISE_DBM;
4581
f59ac048
LR		 4582 hw->wiphy->interface_modes =
4583 BIT(NL80211_IFTYPE_AP) |
4584 BIT(NL80211_IFTYPE_MESH_POINT) |
4585 BIT(NL80211_IFTYPE_STATION) |
4586 BIT(NL80211_IFTYPE_WDS) |
4587 BIT(NL80211_IFTYPE_ADHOC);
4588
e6f5b934 4589 hw->queues = b43_modparam_qos ? 4 : 1;
e6a9854b 4590 hw->max_rates = 2;
e4d6b795 4591 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4592 if (is_valid_ether_addr(sprom->et1mac))
4593 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4594 else
95de2841 4595 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4596
4597 /* Get and initialize struct b43_wl */
4598 wl = hw_to_b43_wl(hw);
4599 memset(wl, 0, sizeof(*wl));
4600 wl->hw = hw;
4601 spin_lock_init(&wl->irq_lock);
21a75d77 4602 rwlock_init(&wl->tx_lock);
e4d6b795 4603 spin_lock_init(&wl->leds_lock);
280d0e16 4604 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4605 mutex_init(&wl->mutex);
4606 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4607 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4608 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4609
4610 ssb_set_devtypedata(dev, wl);
4611 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4612 err = 0;
4613 out:
4614 return err;
4615}
4616
4617static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4618{
4619 struct b43_wl *wl;
4620 int err;
4621 int first = 0;
4622
4623 wl = ssb_get_devtypedata(dev);
4624 if (!wl) {
4625 /* Probing the first core. Must setup common struct b43_wl */
4626 first = 1;
4627 err = b43_wireless_init(dev);
4628 if (err)
4629 goto out;
4630 wl = ssb_get_devtypedata(dev);
4631 B43_WARN_ON(!wl);
4632 }
4633 err = b43_one_core_attach(dev, wl);
4634 if (err)
4635 goto err_wireless_exit;
4636
4637 if (first) {
4638 err = ieee80211_register_hw(wl->hw);
4639 if (err)
4640 goto err_one_core_detach;
4641 }
4642
4643 out:
4644 return err;
4645
4646 err_one_core_detach:
4647 b43_one_core_detach(dev);
4648 err_wireless_exit:
4649 if (first)
4650 b43_wireless_exit(dev, wl);
4651 return err;
4652}
4653
4654static void b43_remove(struct ssb_device *dev)
4655{
4656 struct b43_wl *wl = ssb_get_devtypedata(dev);
4657 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4658
3bf0a32e
MB		 4659 /* We must cancel any work here before unregistering from ieee80211,
4660 * as the ieee80211 unreg will destroy the workqueue. */
4661 cancel_work_sync(&wldev->restart_work);
4662
e4d6b795
MB		 4663 B43_WARN_ON(!wl);
4664 if (wl->current_dev == wldev)
4665 ieee80211_unregister_hw(wl->hw);
4666
4667 b43_one_core_detach(dev);
4668
4669 if (list_empty(&wl->devlist)) {
4670 /* Last core on the chip unregistered.
4671 * We can destroy common struct b43_wl.
4672 */
4673 b43_wireless_exit(dev, wl);
4674 }
4675}
4676
4677/* Perform a hardware reset. This can be called from any context. */
4678void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4679{
4680 /* Must avoid requeueing, if we are in shutdown. */
4681 if (b43_status(dev) < B43_STAT_INITIALIZED)
4682 return;
4683 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4684 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4685}
4686
4687#ifdef CONFIG_PM
4688
4689static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4690{
4691 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4692 struct b43_wl *wl = wldev->wl;
4693
4694 b43dbg(wl, "Suspending...\n");
4695
4696 mutex_lock(&wl->mutex);
3506e0c4 4697 wldev->suspend_in_progress = true;
e4d6b795
MB		 4698 wldev->suspend_init_status = b43_status(wldev);
4699 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4700 b43_wireless_core_stop(wldev);
4701 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4702 b43_wireless_core_exit(wldev);
4703 mutex_unlock(&wl->mutex);
4704
4705 b43dbg(wl, "Device suspended.\n");
4706
4707 return 0;
4708}
4709
4710static int b43_resume(struct ssb_device *dev)
4711{
4712 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4713 struct b43_wl *wl = wldev->wl;
4714 int err = 0;
4715
4716 b43dbg(wl, "Resuming...\n");
4717
4718 mutex_lock(&wl->mutex);
4719 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4720 err = b43_wireless_core_init(wldev);
4721 if (err) {
4722 b43err(wl, "Resume failed at core init\n");
4723 goto out;
4724 }
4725 }
4726 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4727 err = b43_wireless_core_start(wldev);
4728 if (err) {
3506e0c4 4729 b43_leds_exit(wldev);
b844eba2 4730 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4731 b43_wireless_core_exit(wldev);
4732 b43err(wl, "Resume failed at core start\n");
4733 goto out;
4734 }
4735 }
e4d6b795 4736 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4737 out:
4738 wldev->suspend_in_progress = false;
4739 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4740 return err;
4741}
4742
4743#else /* CONFIG_PM */
4744# define b43_suspend NULL
4745# define b43_resume NULL
4746#endif /* CONFIG_PM */
4747
4748static struct ssb_driver b43_ssb_driver = {
4749 .name = KBUILD_MODNAME,
4750 .id_table = b43_ssb_tbl,
4751 .probe = b43_probe,
4752 .remove = b43_remove,
4753 .suspend = b43_suspend,
4754 .resume = b43_resume,
4755};
4756
26bc783f
MB		 4757static void b43_print_driverinfo(void)
4758{
4759 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4760 *feat_leds = "", *feat_rfkill = "";
4761
4762#ifdef CONFIG_B43_PCI_AUTOSELECT
4763 feat_pci = "P";
4764#endif
4765#ifdef CONFIG_B43_PCMCIA
4766 feat_pcmcia = "M";
4767#endif
4768#ifdef CONFIG_B43_NPHY
4769 feat_nphy = "N";
4770#endif
4771#ifdef CONFIG_B43_LEDS
4772 feat_leds = "L";
4773#endif
4774#ifdef CONFIG_B43_RFKILL
4775 feat_rfkill = "R";
4776#endif
4777 printk(KERN_INFO "Broadcom 43xx driver loaded "
4778 "[ Features: %s%s%s%s%s, Firmware-ID: "
4779 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4780 feat_pci, feat_pcmcia, feat_nphy,
4781 feat_leds, feat_rfkill);
4782}
4783
e4d6b795
MB		 4784static int __init b43_init(void)
4785{
4786 int err;
4787
4788 b43_debugfs_init();
4789 err = b43_pcmcia_init();
4790 if (err)
4791 goto err_dfs_exit;
4792 err = ssb_driver_register(&b43_ssb_driver);
4793 if (err)
4794 goto err_pcmcia_exit;
26bc783f 4795 b43_print_driverinfo();
e4d6b795
MB		 4796
4797 return err;
4798
4799err_pcmcia_exit:
4800 b43_pcmcia_exit();
4801err_dfs_exit:
4802 b43_debugfs_exit();
4803 return err;
4804}
4805
4806static void __exit b43_exit(void)
4807{
4808 ssb_driver_unregister(&b43_ssb_driver);
4809 b43_pcmcia_exit();
4810 b43_debugfs_exit();
4811}
4812
4813module_init(b43_init)
4814module_exit(b43_exit)
Linux kernel - Deliverables
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