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drivers/net/wireless/ipw2x00/libipw_module.c: remove unnecessary null test before...
[deliverable/linux.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
108f4f3c 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
e4d6b795 11
3dbba8e2
AH		 12 SDIO support
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
e4d6b795
MB		 15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
17
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
32
33*/
34
35#include <linux/delay.h>
36#include <linux/init.h>
ac5c24e9 37#include <linux/module.h>
e4d6b795
MB		 38#include <linux/if_arp.h>
39#include <linux/etherdevice.h>
e4d6b795 40#include <linux/firmware.h>
e4d6b795
MB		 41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795 44#include <linux/dma-mapping.h>
5a0e3ad6 45#include <linux/slab.h>
e4d6b795
MB		 46#include <asm/unaligned.h>
47
48#include "b43.h"
49#include "main.h"
50#include "debugfs.h"
ef1a628d
MB		 51#include "phy_common.h"
52#include "phy_g.h"
3d0da751 53#include "phy_n.h"
e4d6b795 54#include "dma.h"
5100d5ac 55#include "pio.h"
e4d6b795
MB		 56#include "sysfs.h"
57#include "xmit.h"
e4d6b795
MB		 58#include "lo.h"
59#include "pcmcia.h"
3dbba8e2
AH		 60#include "sdio.h"
61#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 62
63MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64MODULE_AUTHOR("Martin Langer");
65MODULE_AUTHOR("Stefano Brivio");
66MODULE_AUTHOR("Michael Buesch");
0136e51e 67MODULE_AUTHOR("Gábor Stefanik");
108f4f3c 68MODULE_AUTHOR("Rafał Miłecki");
e4d6b795
MB		 69MODULE_LICENSE("GPL");
70
6021e08d
TG		 71MODULE_FIRMWARE("b43/ucode11.fw");
72MODULE_FIRMWARE("b43/ucode13.fw");
73MODULE_FIRMWARE("b43/ucode14.fw");
74MODULE_FIRMWARE("b43/ucode15.fw");
f6158394 75MODULE_FIRMWARE("b43/ucode16_mimo.fw");
6021e08d
TG		 76MODULE_FIRMWARE("b43/ucode5.fw");
77MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 78
79static int modparam_bad_frames_preempt;
80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
83
e4d6b795
MB		 84static char modparam_fwpostfix[16];
85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
e4d6b795
MB		 88static int modparam_hwpctl;
89module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92static int modparam_nohwcrypt;
93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
035d0243 96static int modparam_hwtkip;
97module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
403a3a13
MB		 100static int modparam_qos = 1;
101module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
1855ba78
MB		 104static int modparam_btcoex = 1;
105module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 107
060210f9
MB		 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109module_param_named(verbose, b43_modparam_verbose, int, 0644);
110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
df766267 112static int b43_modparam_pio = 0;
9e3bd919
LT		 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
e6f5b934 115
8960400e
RM		 116static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
117module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
118MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119
3c65ab62
RM		 120#ifdef CONFIG_B43_BCMA
121static const struct bcma_device_id b43_bcma_tbl[] = {
c027ed4c 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
3c65ab62
RM		 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
126 BCMA_CORETABLE_END
127};
128MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
129#endif
130
aec7ffdf 131#ifdef CONFIG_B43_SSB
e4d6b795
MB		 132static const struct ssb_device_id b43_ssb_tbl[] = {
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 143 SSB_DEVTABLE_END
144};
e4d6b795 145MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
aec7ffdf 146#endif
e4d6b795
MB		 147
148/* Channel and ratetables are shared for all devices.
149 * They can't be const, because ieee80211 puts some precalculated
150 * data in there. This data is the same for all devices, so we don't
151 * get concurrency issues */
152#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 153 { \
154 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
155 .hw_value = (_rateid), \
156 .flags = (_flags), \
e4d6b795 157 }
8318d78a
JB		 158
159/*
160 * NOTE: When changing this, sync with xmit.c's
161 * b43_plcp_get_bitrate_idx_* functions!
162 */
e4d6b795 163static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 164 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
165 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
167 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
168 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 176};
177
178#define b43_a_ratetable (__b43_ratetable + 4)
179#define b43_a_ratetable_size 8
180#define b43_b_ratetable (__b43_ratetable + 0)
181#define b43_b_ratetable_size 4
182#define b43_g_ratetable (__b43_ratetable + 0)
183#define b43_g_ratetable_size 12
184
e9cdcb74 185#define CHAN2G(_channel, _freq, _flags) { \
bb1eeff1
MB		 186 .band = IEEE80211_BAND_2GHZ, \
187 .center_freq = (_freq), \
188 .hw_value = (_channel), \
189 .flags = (_flags), \
190 .max_antenna_gain = 0, \
191 .max_power = 30, \
192}
96c755a3 193static struct ieee80211_channel b43_2ghz_chantable[] = {
e9cdcb74
RM		 194 CHAN2G(1, 2412, 0),
195 CHAN2G(2, 2417, 0),
196 CHAN2G(3, 2422, 0),
197 CHAN2G(4, 2427, 0),
198 CHAN2G(5, 2432, 0),
199 CHAN2G(6, 2437, 0),
200 CHAN2G(7, 2442, 0),
201 CHAN2G(8, 2447, 0),
202 CHAN2G(9, 2452, 0),
203 CHAN2G(10, 2457, 0),
204 CHAN2G(11, 2462, 0),
205 CHAN2G(12, 2467, 0),
206 CHAN2G(13, 2472, 0),
207 CHAN2G(14, 2484, 0),
bb1eeff1 208};
e9cdcb74 209#undef CHAN2G
bb1eeff1 210
91211739
RM		 211#define CHAN4G(_channel, _flags) { \
212 .band = IEEE80211_BAND_5GHZ, \
213 .center_freq = 4000 + (5 * (_channel)), \
214 .hw_value = (_channel), \
215 .flags = (_flags), \
216 .max_antenna_gain = 0, \
217 .max_power = 30, \
218}
bb1eeff1
MB		 219#define CHAN5G(_channel, _flags) { \
220 .band = IEEE80211_BAND_5GHZ, \
221 .center_freq = 5000 + (5 * (_channel)), \
222 .hw_value = (_channel), \
223 .flags = (_flags), \
224 .max_antenna_gain = 0, \
225 .max_power = 30, \
226}
227static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
91211739
RM		 228 CHAN4G(184, 0), CHAN4G(186, 0),
229 CHAN4G(188, 0), CHAN4G(190, 0),
230 CHAN4G(192, 0), CHAN4G(194, 0),
231 CHAN4G(196, 0), CHAN4G(198, 0),
232 CHAN4G(200, 0), CHAN4G(202, 0),
233 CHAN4G(204, 0), CHAN4G(206, 0),
234 CHAN4G(208, 0), CHAN4G(210, 0),
235 CHAN4G(212, 0), CHAN4G(214, 0),
236 CHAN4G(216, 0), CHAN4G(218, 0),
237 CHAN4G(220, 0), CHAN4G(222, 0),
238 CHAN4G(224, 0), CHAN4G(226, 0),
239 CHAN4G(228, 0),
bb1eeff1
MB		 240 CHAN5G(32, 0), CHAN5G(34, 0),
241 CHAN5G(36, 0), CHAN5G(38, 0),
242 CHAN5G(40, 0), CHAN5G(42, 0),
243 CHAN5G(44, 0), CHAN5G(46, 0),
244 CHAN5G(48, 0), CHAN5G(50, 0),
245 CHAN5G(52, 0), CHAN5G(54, 0),
246 CHAN5G(56, 0), CHAN5G(58, 0),
247 CHAN5G(60, 0), CHAN5G(62, 0),
248 CHAN5G(64, 0), CHAN5G(66, 0),
249 CHAN5G(68, 0), CHAN5G(70, 0),
250 CHAN5G(72, 0), CHAN5G(74, 0),
251 CHAN5G(76, 0), CHAN5G(78, 0),
252 CHAN5G(80, 0), CHAN5G(82, 0),
253 CHAN5G(84, 0), CHAN5G(86, 0),
254 CHAN5G(88, 0), CHAN5G(90, 0),
255 CHAN5G(92, 0), CHAN5G(94, 0),
256 CHAN5G(96, 0), CHAN5G(98, 0),
257 CHAN5G(100, 0), CHAN5G(102, 0),
258 CHAN5G(104, 0), CHAN5G(106, 0),
259 CHAN5G(108, 0), CHAN5G(110, 0),
260 CHAN5G(112, 0), CHAN5G(114, 0),
261 CHAN5G(116, 0), CHAN5G(118, 0),
262 CHAN5G(120, 0), CHAN5G(122, 0),
263 CHAN5G(124, 0), CHAN5G(126, 0),
264 CHAN5G(128, 0), CHAN5G(130, 0),
265 CHAN5G(132, 0), CHAN5G(134, 0),
266 CHAN5G(136, 0), CHAN5G(138, 0),
267 CHAN5G(140, 0), CHAN5G(142, 0),
268 CHAN5G(144, 0), CHAN5G(145, 0),
269 CHAN5G(146, 0), CHAN5G(147, 0),
270 CHAN5G(148, 0), CHAN5G(149, 0),
271 CHAN5G(150, 0), CHAN5G(151, 0),
272 CHAN5G(152, 0), CHAN5G(153, 0),
273 CHAN5G(154, 0), CHAN5G(155, 0),
274 CHAN5G(156, 0), CHAN5G(157, 0),
275 CHAN5G(158, 0), CHAN5G(159, 0),
276 CHAN5G(160, 0), CHAN5G(161, 0),
277 CHAN5G(162, 0), CHAN5G(163, 0),
278 CHAN5G(164, 0), CHAN5G(165, 0),
279 CHAN5G(166, 0), CHAN5G(168, 0),
280 CHAN5G(170, 0), CHAN5G(172, 0),
281 CHAN5G(174, 0), CHAN5G(176, 0),
282 CHAN5G(178, 0), CHAN5G(180, 0),
91211739 283 CHAN5G(182, 0),
e4d6b795
MB		 284};
285
bb1eeff1
MB		 286static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
287 CHAN5G(34, 0), CHAN5G(36, 0),
288 CHAN5G(38, 0), CHAN5G(40, 0),
289 CHAN5G(42, 0), CHAN5G(44, 0),
290 CHAN5G(46, 0), CHAN5G(48, 0),
291 CHAN5G(52, 0), CHAN5G(56, 0),
292 CHAN5G(60, 0), CHAN5G(64, 0),
293 CHAN5G(100, 0), CHAN5G(104, 0),
294 CHAN5G(108, 0), CHAN5G(112, 0),
295 CHAN5G(116, 0), CHAN5G(120, 0),
296 CHAN5G(124, 0), CHAN5G(128, 0),
297 CHAN5G(132, 0), CHAN5G(136, 0),
298 CHAN5G(140, 0), CHAN5G(149, 0),
299 CHAN5G(153, 0), CHAN5G(157, 0),
300 CHAN5G(161, 0), CHAN5G(165, 0),
301 CHAN5G(184, 0), CHAN5G(188, 0),
302 CHAN5G(192, 0), CHAN5G(196, 0),
303 CHAN5G(200, 0), CHAN5G(204, 0),
304 CHAN5G(208, 0), CHAN5G(212, 0),
305 CHAN5G(216, 0),
306};
91211739 307#undef CHAN4G
bb1eeff1
MB		 308#undef CHAN5G
309
310static struct ieee80211_supported_band b43_band_5GHz_nphy = {
311 .band = IEEE80211_BAND_5GHZ,
312 .channels = b43_5ghz_nphy_chantable,
313 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
314 .bitrates = b43_a_ratetable,
315 .n_bitrates = b43_a_ratetable_size,
e4d6b795 316};
8318d78a 317
bb1eeff1
MB		 318static struct ieee80211_supported_band b43_band_5GHz_aphy = {
319 .band = IEEE80211_BAND_5GHZ,
320 .channels = b43_5ghz_aphy_chantable,
321 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
322 .bitrates = b43_a_ratetable,
323 .n_bitrates = b43_a_ratetable_size,
8318d78a 324};
e4d6b795 325
8318d78a 326static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 327 .band = IEEE80211_BAND_2GHZ,
328 .channels = b43_2ghz_chantable,
329 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
330 .bitrates = b43_g_ratetable,
331 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 332};
333
e4d6b795
MB		 334static void b43_wireless_core_exit(struct b43_wldev *dev);
335static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 336static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795 337static int b43_wireless_core_start(struct b43_wldev *dev);
2a190322
FF		 338static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
339 struct ieee80211_vif *vif,
340 struct ieee80211_bss_conf *conf,
341 u32 changed);
e4d6b795
MB		 342
343static int b43_ratelimit(struct b43_wl *wl)
344{
345 if (!wl || !wl->current_dev)
346 return 1;
347 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
348 return 1;
349 /* We are up and running.
350 * Ratelimit the messages to avoid DoS over the net. */
351 return net_ratelimit();
352}
353
354void b43info(struct b43_wl *wl, const char *fmt, ...)
355{
5b736d42 356 struct va_format vaf;
e4d6b795
MB		 357 va_list args;
358
060210f9
MB		 359 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
360 return;
e4d6b795
MB		 361 if (!b43_ratelimit(wl))
362 return;
5b736d42 363
e4d6b795 364 va_start(args, fmt);
5b736d42
JP		 365
366 vaf.fmt = fmt;
367 vaf.va = &args;
368
369 printk(KERN_INFO "b43-%s: %pV",
370 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
371
e4d6b795
MB		 372 va_end(args);
373}
374
375void b43err(struct b43_wl *wl, const char *fmt, ...)
376{
5b736d42 377 struct va_format vaf;
e4d6b795
MB		 378 va_list args;
379
060210f9
MB		 380 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
381 return;
e4d6b795
MB		 382 if (!b43_ratelimit(wl))
383 return;
5b736d42 384
e4d6b795 385 va_start(args, fmt);
5b736d42
JP		 386
387 vaf.fmt = fmt;
388 vaf.va = &args;
389
390 printk(KERN_ERR "b43-%s ERROR: %pV",
391 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
392
e4d6b795
MB		 393 va_end(args);
394}
395
396void b43warn(struct b43_wl *wl, const char *fmt, ...)
397{
5b736d42 398 struct va_format vaf;
e4d6b795
MB		 399 va_list args;
400
060210f9
MB		 401 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
402 return;
e4d6b795
MB		 403 if (!b43_ratelimit(wl))
404 return;
5b736d42 405
e4d6b795 406 va_start(args, fmt);
5b736d42
JP		 407
408 vaf.fmt = fmt;
409 vaf.va = &args;
410
411 printk(KERN_WARNING "b43-%s warning: %pV",
412 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
413
e4d6b795
MB		 414 va_end(args);
415}
416
e4d6b795
MB		 417void b43dbg(struct b43_wl *wl, const char *fmt, ...)
418{
5b736d42 419 struct va_format vaf;
e4d6b795
MB		 420 va_list args;
421
060210f9
MB		 422 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
423 return;
5b736d42 424
e4d6b795 425 va_start(args, fmt);
5b736d42
JP		 426
427 vaf.fmt = fmt;
428 vaf.va = &args;
429
430 printk(KERN_DEBUG "b43-%s debug: %pV",
431 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
432
e4d6b795
MB		 433 va_end(args);
434}
e4d6b795
MB		 435
436static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
437{
438 u32 macctl;
439
440 B43_WARN_ON(offset % 4 != 0);
441
442 macctl = b43_read32(dev, B43_MMIO_MACCTL);
443 if (macctl & B43_MACCTL_BE)
444 val = swab32(val);
445
446 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
447 mmiowb();
448 b43_write32(dev, B43_MMIO_RAM_DATA, val);
449}
450
280d0e16
MB		 451static inline void b43_shm_control_word(struct b43_wldev *dev,
452 u16 routing, u16 offset)
e4d6b795
MB		 453{
454 u32 control;
455
456 /* "offset" is the WORD offset. */
e4d6b795
MB		 457 control = routing;
458 control <<= 16;
459 control |= offset;
460 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
461}
462
69eddc8a 463u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 464{
465 u32 ret;
466
467 if (routing == B43_SHM_SHARED) {
468 B43_WARN_ON(offset & 0x0001);
469 if (offset & 0x0003) {
470 /* Unaligned access */
471 b43_shm_control_word(dev, routing, offset >> 2);
472 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 473 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 474 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 475
280d0e16 476 goto out;
e4d6b795
MB		 477 }
478 offset >>= 2;
479 }
480 b43_shm_control_word(dev, routing, offset);
481 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 482out:
e4d6b795
MB		 483 return ret;
484}
485
69eddc8a 486u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 487{
488 u16 ret;
489
e4d6b795
MB		 490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
495 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
496
280d0e16 497 goto out;
e4d6b795
MB		 498 }
499 offset >>= 2;
500 }
501 b43_shm_control_word(dev, routing, offset);
502 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 503out:
e4d6b795
MB		 504 return ret;
505}
506
69eddc8a 507void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 508{
e4d6b795
MB		 509 if (routing == B43_SHM_SHARED) {
510 B43_WARN_ON(offset & 0x0001);
511 if (offset & 0x0003) {
512 /* Unaligned access */
513 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 514 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 515 value & 0xFFFF);
e4d6b795 516 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 517 b43_write16(dev, B43_MMIO_SHM_DATA,
518 (value >> 16) & 0xFFFF);
6bbc321a 519 return;
e4d6b795
MB		 520 }
521 offset >>= 2;
522 }
523 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 524 b43_write32(dev, B43_MMIO_SHM_DATA, value);
525}
526
69eddc8a 527void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 528{
e4d6b795
MB		 529 if (routing == B43_SHM_SHARED) {
530 B43_WARN_ON(offset & 0x0001);
531 if (offset & 0x0003) {
532 /* Unaligned access */
533 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 534 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 535 return;
e4d6b795
MB		 536 }
537 offset >>= 2;
538 }
539 b43_shm_control_word(dev, routing, offset);
e4d6b795 540 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 541}
542
e4d6b795 543/* Read HostFlags */
99da185a 544u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 545{
35f0d354 546 u64 ret;
e4d6b795 547
6e6a2cd5 548 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
e4d6b795 549 ret <<= 16;
6e6a2cd5 550 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
35f0d354 551 ret <<= 16;
6e6a2cd5 552 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
e4d6b795
MB		 553
554 return ret;
555}
556
557/* Write HostFlags */
35f0d354 558void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 559{
35f0d354
MB		 560 u16 lo, mi, hi;
561
562 lo = (value & 0x00000000FFFFULL);
563 mi = (value & 0x0000FFFF0000ULL) >> 16;
564 hi = (value & 0xFFFF00000000ULL) >> 32;
6e6a2cd5
RM		 565 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
566 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
567 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
e4d6b795
MB		 568}
569
403a3a13
MB		 570/* Read the firmware capabilities bitmask (Opensource firmware only) */
571static u16 b43_fwcapa_read(struct b43_wldev *dev)
572{
573 B43_WARN_ON(!dev->fw.opensource);
574 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
575}
576
3ebbbb56 577void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 578{
3ebbbb56
MB		 579 u32 low, high;
580
21d889d4 581 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 582
583 /* The hardware guarantees us an atomic read, if we
584 * read the low register first. */
585 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
586 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
587
588 *tsf = high;
589 *tsf <<= 32;
590 *tsf |= low;
e4d6b795
MB		 591}
592
593static void b43_time_lock(struct b43_wldev *dev)
594{
5056635c 595 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
e4d6b795
MB		 596 /* Commit the write */
597 b43_read32(dev, B43_MMIO_MACCTL);
598}
599
600static void b43_time_unlock(struct b43_wldev *dev)
601{
5056635c 602 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
e4d6b795
MB		 603 /* Commit the write */
604 b43_read32(dev, B43_MMIO_MACCTL);
605}
606
607static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
608{
3ebbbb56
MB		 609 u32 low, high;
610
21d889d4 611 B43_WARN_ON(dev->dev->core_rev < 3);
3ebbbb56
MB		 612
613 low = tsf;
614 high = (tsf >> 32);
615 /* The hardware guarantees us an atomic write, if we
616 * write the low register first. */
617 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
618 mmiowb();
619 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
620 mmiowb();
e4d6b795
MB		 621}
622
623void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
624{
625 b43_time_lock(dev);
626 b43_tsf_write_locked(dev, tsf);
627 b43_time_unlock(dev);
628}
629
630static
99da185a 631void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 632{
633 static const u8 zero_addr[ETH_ALEN] = { 0 };
634 u16 data;
635
636 if (!mac)
637 mac = zero_addr;
638
639 offset |= 0x0020;
640 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
641
642 data = mac[0];
643 data |= mac[1] << 8;
644 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
645 data = mac[2];
646 data |= mac[3] << 8;
647 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
648 data = mac[4];
649 data |= mac[5] << 8;
650 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
651}
652
653static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
654{
655 const u8 *mac;
656 const u8 *bssid;
657 u8 mac_bssid[ETH_ALEN * 2];
658 int i;
659 u32 tmp;
660
661 bssid = dev->wl->bssid;
662 mac = dev->wl->mac_addr;
663
664 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
665
666 memcpy(mac_bssid, mac, ETH_ALEN);
667 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
668
669 /* Write our MAC address and BSSID to template ram */
670 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
671 tmp = (u32) (mac_bssid[i + 0]);
672 tmp |= (u32) (mac_bssid[i + 1]) << 8;
673 tmp |= (u32) (mac_bssid[i + 2]) << 16;
674 tmp |= (u32) (mac_bssid[i + 3]) << 24;
675 b43_ram_write(dev, 0x20 + i, tmp);
676 }
677}
678
4150c572 679static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 680{
e4d6b795 681 b43_write_mac_bssid_templates(dev);
4150c572 682 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 683}
684
685static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
686{
687 /* slot_time is in usec. */
b6c3f5be
LF		 688 /* This test used to exit for all but a G PHY. */
689 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 690 return;
b6c3f5be
LF		 691 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
692 /* Shared memory location 0x0010 is the slot time and should be
693 * set to slot_time; however, this register is initially 0 and changing
694 * the value adversely affects the transmit rate for BCM4311
695 * devices. Until this behavior is unterstood, delete this step
696 *
697 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
698 */
e4d6b795
MB		 699}
700
701static void b43_short_slot_timing_enable(struct b43_wldev *dev)
702{
703 b43_set_slot_time(dev, 9);
e4d6b795
MB		 704}
705
706static void b43_short_slot_timing_disable(struct b43_wldev *dev)
707{
708 b43_set_slot_time(dev, 20);
e4d6b795
MB		 709}
710
e4d6b795 711/* DummyTransmission function, as documented on
2f19c287 712 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 713 */
2f19c287 714void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 715{
716 struct b43_phy *phy = &dev->phy;
717 unsigned int i, max_loop;
718 u16 value;
719 u32 buffer[5] = {
720 0x00000000,
721 0x00D40000,
722 0x00000000,
723 0x01000000,
724 0x00000000,
725 };
726
2f19c287 727 if (ofdm) {
e4d6b795
MB		 728 max_loop = 0x1E;
729 buffer[0] = 0x000201CC;
2f19c287 730 } else {
e4d6b795
MB		 731 max_loop = 0xFA;
732 buffer[0] = 0x000B846E;
e4d6b795
MB		 733 }
734
735 for (i = 0; i < 5; i++)
736 b43_ram_write(dev, i * 4, buffer[i]);
737
7955d87f
RM		 738 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
739
21d889d4 740 if (dev->dev->core_rev < 11)
7955d87f 741 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
2f19c287 742 else
7955d87f
RM		 743 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
744
2f19c287 745 value = (ofdm ? 0x41 : 0x40);
7955d87f 746 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
93dbd828
RM		 747 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
748 phy->type == B43_PHYTYPE_LCN)
7955d87f
RM		 749 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
750
751 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
752 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
753
754 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
755 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
756 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
757 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
93dbd828
RM		 758
759 if (!pa_on && phy->type == B43_PHYTYPE_N)
760 ; /*b43_nphy_pa_override(dev, false) */
2f19c287
GS		 761
762 switch (phy->type) {
763 case B43_PHYTYPE_N:
93dbd828 764 case B43_PHYTYPE_LCN:
7955d87f 765 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
2f19c287
GS		 766 break;
767 case B43_PHYTYPE_LP:
7955d87f 768 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
2f19c287
GS		 769 break;
770 default:
7955d87f 771 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
2f19c287 772 }
93dbd828 773 b43_read16(dev, B43_MMIO_TXE0_AUX);
e4d6b795
MB		 774
775 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
776 b43_radio_write16(dev, 0x0051, 0x0017);
777 for (i = 0x00; i < max_loop; i++) {
7955d87f 778 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 779 if (value & 0x0080)
780 break;
781 udelay(10);
782 }
783 for (i = 0x00; i < 0x0A; i++) {
7955d87f 784 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
e4d6b795
MB		 785 if (value & 0x0400)
786 break;
787 udelay(10);
788 }
1d280ddc 789 for (i = 0x00; i < 0x19; i++) {
7955d87f 790 value = b43_read16(dev, B43_MMIO_IFSSTAT);
e4d6b795
MB		 791 if (!(value & 0x0100))
792 break;
793 udelay(10);
794 }
795 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
796 b43_radio_write16(dev, 0x0051, 0x0037);
797}
798
799static void key_write(struct b43_wldev *dev,
99da185a 800 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 801{
802 unsigned int i;
803 u32 offset;
804 u16 value;
805 u16 kidx;
806
807 /* Key index/algo block */
808 kidx = b43_kidx_to_fw(dev, index);
809 value = ((kidx << 4) | algorithm);
810 b43_shm_write16(dev, B43_SHM_SHARED,
811 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
812
813 /* Write the key to the Key Table Pointer offset */
814 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
815 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
816 value = key[i];
817 value |= (u16) (key[i + 1]) << 8;
818 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
819 }
820}
821
99da185a 822static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 823{
824 u32 addrtmp[2] = { 0, 0, };
66d2d089 825 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 826
827 if (b43_new_kidx_api(dev))
66d2d089 828 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 829
66d2d089
MB		 830 B43_WARN_ON(index < pairwise_keys_start);
831 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 832 * Physical mac 0 is mapped to physical key 4 or 8, depending
833 * on the firmware version.
834 * So we must adjust the index here.
835 */
66d2d089
MB		 836 index -= pairwise_keys_start;
837 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 838
839 if (addr) {
840 addrtmp[0] = addr[0];
841 addrtmp[0] |= ((u32) (addr[1]) << 8);
842 addrtmp[0] |= ((u32) (addr[2]) << 16);
843 addrtmp[0] |= ((u32) (addr[3]) << 24);
844 addrtmp[1] = addr[4];
845 addrtmp[1] |= ((u32) (addr[5]) << 8);
846 }
847
66d2d089
MB		 848 /* Receive match transmitter address (RCMTA) mechanism */
849 b43_shm_write32(dev, B43_SHM_RCMTA,
850 (index * 2) + 0, addrtmp[0]);
851 b43_shm_write16(dev, B43_SHM_RCMTA,
852 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 853}
854
035d0243 855/* The ucode will use phase1 key with TEK key to decrypt rx packets.
856 * When a packet is received, the iv32 is checked.
857 * - if it doesn't the packet is returned without modification (and software
858 * decryption can be done). That's what happen when iv16 wrap.
859 * - if it does, the rc4 key is computed, and decryption is tried.
860 * Either it will success and B43_RX_MAC_DEC is returned,
861 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
862 * and the packet is not usable (it got modified by the ucode).
863 * So in order to never have B43_RX_MAC_DECERR, we should provide
864 * a iv32 and phase1key that match. Because we drop packets in case of
865 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
866 * packets will be lost without higher layer knowing (ie no resync possible
867 * until next wrap).
868 *
869 * NOTE : this should support 50 key like RCMTA because
870 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
871 */
872static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
873 u16 *phase1key)
874{
875 unsigned int i;
876 u32 offset;
877 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
878
879 if (!modparam_hwtkip)
880 return;
881
882 if (b43_new_kidx_api(dev))
883 pairwise_keys_start = B43_NR_GROUP_KEYS;
884
885 B43_WARN_ON(index < pairwise_keys_start);
886 /* We have four default TX keys and possibly four default RX keys.
887 * Physical mac 0 is mapped to physical key 4 or 8, depending
888 * on the firmware version.
889 * So we must adjust the index here.
890 */
891 index -= pairwise_keys_start;
892 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
893
894 if (b43_debug(dev, B43_DBG_KEYS)) {
895 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
896 index, iv32);
897 }
898 /* Write the key to the RX tkip shared mem */
899 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
900 for (i = 0; i < 10; i += 2) {
901 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
902 phase1key ? phase1key[i / 2] : 0);
903 }
904 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
905 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
906}
907
908static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 909 struct ieee80211_vif *vif,
910 struct ieee80211_key_conf *keyconf,
911 struct ieee80211_sta *sta,
912 u32 iv32, u16 *phase1key)
035d0243 913{
914 struct b43_wl *wl = hw_to_b43_wl(hw);
915 struct b43_wldev *dev;
916 int index = keyconf->hw_key_idx;
917
918 if (B43_WARN_ON(!modparam_hwtkip))
919 return;
920
96869a39
MB		 921 /* This is only called from the RX path through mac80211, where
922 * our mutex is already locked. */
923 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 924 dev = wl->current_dev;
96869a39 925 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 926
927 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
928
929 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 930 /* only pairwise TKIP keys are supported right now */
931 if (WARN_ON(!sta))
96869a39 932 return;
b3fbdcf4 933 keymac_write(dev, index, sta->addr);
035d0243 934}
935
e4d6b795
MB		 936static void do_key_write(struct b43_wldev *dev,
937 u8 index, u8 algorithm,
99da185a 938 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 939{
940 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 941 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 942
943 if (b43_new_kidx_api(dev))
66d2d089 944 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 945
66d2d089 946 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 947 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
948
66d2d089 949 if (index >= pairwise_keys_start)
e4d6b795 950 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 951 if (algorithm == B43_SEC_ALGO_TKIP) {
952 /*
953 * We should provide an initial iv32, phase1key pair.
954 * We could start with iv32=0 and compute the corresponding
955 * phase1key, but this means calling ieee80211_get_tkip_key
956 * with a fake skb (or export other tkip function).
957 * Because we are lazy we hope iv32 won't start with
958 * 0xffffffff and let's b43_op_update_tkip_key provide a
959 * correct pair.
960 */
961 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
962 } else if (index >= pairwise_keys_start) /* clear it */
963 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 964 if (key)
965 memcpy(buf, key, key_len);
966 key_write(dev, index, algorithm, buf);
66d2d089 967 if (index >= pairwise_keys_start)
e4d6b795
MB		 968 keymac_write(dev, index, mac_addr);
969
970 dev->key[index].algorithm = algorithm;
971}
972
973static int b43_key_write(struct b43_wldev *dev,
974 int index, u8 algorithm,
99da185a
JD		 975 const u8 *key, size_t key_len,
976 const u8 *mac_addr,
e4d6b795
MB		 977 struct ieee80211_key_conf *keyconf)
978{
979 int i;
66d2d089 980 int pairwise_keys_start;
e4d6b795 981
035d0243 982 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
983 * - Temporal Encryption Key (128 bits)
984 * - Temporal Authenticator Tx MIC Key (64 bits)
985 * - Temporal Authenticator Rx MIC Key (64 bits)
986 *
987 * Hardware only store TEK
988 */
989 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
990 key_len = 16;
e4d6b795
MB		 991 if (key_len > B43_SEC_KEYSIZE)
992 return -EINVAL;
66d2d089 993 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 994 /* Check that we don't already have this key. */
995 B43_WARN_ON(dev->key[i].keyconf == keyconf);
996 }
997 if (index < 0) {
e808e586 998 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 999 if (b43_new_kidx_api(dev))
66d2d089 1000 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 1001 else
66d2d089
MB		 1002 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1003 for (i = pairwise_keys_start;
1004 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1005 i++) {
1006 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 1007 if (!dev->key[i].keyconf) {
1008 /* found empty */
1009 index = i;
1010 break;
1011 }
1012 }
1013 if (index < 0) {
e808e586 1014 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 1015 return -ENOSPC;
1016 }
1017 } else
1018 B43_WARN_ON(index > 3);
1019
1020 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1021 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1022 /* Default RX key */
1023 B43_WARN_ON(mac_addr);
1024 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1025 }
1026 keyconf->hw_key_idx = index;
1027 dev->key[index].keyconf = keyconf;
1028
1029 return 0;
1030}
1031
1032static int b43_key_clear(struct b43_wldev *dev, int index)
1033{
66d2d089 1034 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 1035 return -EINVAL;
1036 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1037 NULL, B43_SEC_KEYSIZE, NULL);
1038 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1039 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1040 NULL, B43_SEC_KEYSIZE, NULL);
1041 }
1042 dev->key[index].keyconf = NULL;
1043
1044 return 0;
1045}
1046
1047static void b43_clear_keys(struct b43_wldev *dev)
1048{
66d2d089 1049 int i, count;
e4d6b795 1050
66d2d089
MB		 1051 if (b43_new_kidx_api(dev))
1052 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1053 else
1054 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1055 for (i = 0; i < count; i++)
e4d6b795
MB		 1056 b43_key_clear(dev, i);
1057}
1058
9cf7f247
MB		 1059static void b43_dump_keymemory(struct b43_wldev *dev)
1060{
66d2d089 1061 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1062 u8 mac[ETH_ALEN];
1063 u16 algo;
1064 u32 rcmta0;
1065 u16 rcmta1;
1066 u64 hf;
1067 struct b43_key *key;
1068
1069 if (!b43_debug(dev, B43_DBG_KEYS))
1070 return;
1071
1072 hf = b43_hf_read(dev);
1073 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1074 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1075 if (b43_new_kidx_api(dev)) {
1076 pairwise_keys_start = B43_NR_GROUP_KEYS;
1077 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1078 } else {
1079 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1080 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1081 }
1082 for (index = 0; index < count; index++) {
9cf7f247
MB		 1083 key = &(dev->key[index]);
1084 printk(KERN_DEBUG "Key slot %02u: %s",
1085 index, (key->keyconf == NULL) ? " " : "*");
1086 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1087 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1088 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1089 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1090 }
1091
1092 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1093 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1094 printk(" Algo: %04X/%02X", algo, key->algorithm);
1095
66d2d089 1096 if (index >= pairwise_keys_start) {
035d0243 1097 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1098 printk(" TKIP: ");
1099 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1100 for (i = 0; i < 14; i += 2) {
1101 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1102 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1103 }
1104 }
9cf7f247 1105 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1106 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1107 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1108 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1109 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1110 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1111 printk(" MAC: %pM", mac);
9cf7f247
MB		 1112 } else
1113 printk(" DEFAULT KEY");
1114 printk("\n");
1115 }
1116}
1117
e4d6b795
MB		 1118void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1119{
1120 u32 macctl;
1121 u16 ucstat;
1122 bool hwps;
1123 bool awake;
1124 int i;
1125
1126 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1127 (ps_flags & B43_PS_DISABLED));
1128 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1129
1130 if (ps_flags & B43_PS_ENABLED) {
3db1cd5c 1131 hwps = true;
e4d6b795 1132 } else if (ps_flags & B43_PS_DISABLED) {
3db1cd5c 1133 hwps = false;
e4d6b795
MB		 1134 } else {
1135 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1136 // and thus is not an AP and we are associated, set bit 25
1137 }
1138 if (ps_flags & B43_PS_AWAKE) {
3db1cd5c 1139 awake = true;
e4d6b795 1140 } else if (ps_flags & B43_PS_ASLEEP) {
3db1cd5c 1141 awake = false;
e4d6b795
MB		 1142 } else {
1143 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1144 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1145 // successful, set bit26
1146 }
1147
1148/* FIXME: For now we force awake-on and hwps-off */
3db1cd5c
RR		 1149 hwps = false;
1150 awake = true;
e4d6b795
MB		 1151
1152 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1153 if (hwps)
1154 macctl |= B43_MACCTL_HWPS;
1155 else
1156 macctl &= ~B43_MACCTL_HWPS;
1157 if (awake)
1158 macctl |= B43_MACCTL_AWAKE;
1159 else
1160 macctl &= ~B43_MACCTL_AWAKE;
1161 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1162 /* Commit write */
1163 b43_read32(dev, B43_MMIO_MACCTL);
21d889d4 1164 if (awake && dev->dev->core_rev >= 5) {
e4d6b795
MB		 1165 /* Wait for the microcode to wake up. */
1166 for (i = 0; i < 100; i++) {
1167 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1168 B43_SHM_SH_UCODESTAT);
1169 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1170 break;
1171 udelay(10);
1172 }
1173 }
1174}
1175
42c9a458 1176#ifdef CONFIG_B43_BCMA
49173592 1177static void b43_bcma_phy_reset(struct b43_wldev *dev)
42c9a458 1178{
49173592 1179 u32 flags;
42c9a458 1180
49173592
RM		 1181 /* Put PHY into reset */
1182 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1183 flags |= B43_BCMA_IOCTL_PHY_RESET;
42c9a458 1184 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
49173592
RM		 1185 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1186 udelay(2);
1187
50c1b59e 1188 b43_phy_take_out_of_reset(dev);
49173592 1189}
42c9a458 1190
49173592
RM		 1191static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1192{
88cceab5
RM		 1193 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1194 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1195 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1196 B43_BCMA_CLKCTLST_PHY_PLL_ST;
6b9e03e6
RM		 1197 u32 flags;
1198
1199 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1200 if (gmode)
1201 flags |= B43_BCMA_IOCTL_GMODE;
1202 b43_device_enable(dev, flags);
88cceab5 1203
49173592
RM		 1204 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1205 b43_bcma_phy_reset(dev);
88cceab5 1206 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
42c9a458
RM		 1207}
1208#endif
1209
bd7c8a59 1210#ifdef CONFIG_B43_SSB
4da909e7 1211static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
e4d6b795 1212{
4da909e7 1213 u32 flags = 0;
e4d6b795 1214
4da909e7
RM		 1215 if (gmode)
1216 flags |= B43_TMSLOW_GMODE;
e4d6b795
MB		 1217 flags |= B43_TMSLOW_PHYCLKEN;
1218 flags |= B43_TMSLOW_PHYRESET;
42ab135f
RM		 1219 if (dev->phy.type == B43_PHYTYPE_N)
1220 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
24ca39d6 1221 b43_device_enable(dev, flags);
e4d6b795
MB		 1222 msleep(2); /* Wait for the PLL to turn on. */
1223
50c1b59e 1224 b43_phy_take_out_of_reset(dev);
1495298d 1225}
bd7c8a59 1226#endif
1495298d 1227
4da909e7 1228void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1495298d
RM		 1229{
1230 u32 macctl;
1231
6cbab0d9 1232 switch (dev->dev->bus_type) {
42c9a458
RM		 1233#ifdef CONFIG_B43_BCMA
1234 case B43_BUS_BCMA:
1235 b43_bcma_wireless_core_reset(dev, gmode);
1236 break;
1237#endif
6cbab0d9
RM		 1238#ifdef CONFIG_B43_SSB
1239 case B43_BUS_SSB:
1240 b43_ssb_wireless_core_reset(dev, gmode);
1241 break;
1242#endif
1243 }
e4d6b795 1244
fb11137a
MB		 1245 /* Turn Analog ON, but only if we already know the PHY-type.
1246 * This protects against very early setup where we don't know the
1247 * PHY-type, yet. wireless_core_reset will be called once again later,
1248 * when we know the PHY-type. */
1249 if (dev->phy.ops)
cb24f57f 1250 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1251
1252 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1253 macctl &= ~B43_MACCTL_GMODE;
4da909e7 1254 if (gmode)
e4d6b795
MB		 1255 macctl |= B43_MACCTL_GMODE;
1256 macctl |= B43_MACCTL_IHR_ENABLED;
1257 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1258}
1259
1260static void handle_irq_transmit_status(struct b43_wldev *dev)
1261{
1262 u32 v0, v1;
1263 u16 tmp;
1264 struct b43_txstatus stat;
1265
1266 while (1) {
1267 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1268 if (!(v0 & 0x00000001))
1269 break;
1270 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1271
1272 stat.cookie = (v0 >> 16);
1273 stat.seq = (v1 & 0x0000FFFF);
1274 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1275 tmp = (v0 & 0x0000FFFF);
1276 stat.frame_count = ((tmp & 0xF000) >> 12);
1277 stat.rts_count = ((tmp & 0x0F00) >> 8);
1278 stat.supp_reason = ((tmp & 0x001C) >> 2);
1279 stat.pm_indicated = !!(tmp & 0x0080);
1280 stat.intermediate = !!(tmp & 0x0040);
1281 stat.for_ampdu = !!(tmp & 0x0020);
1282 stat.acked = !!(tmp & 0x0002);
1283
1284 b43_handle_txstatus(dev, &stat);
1285 }
1286}
1287
1288static void drain_txstatus_queue(struct b43_wldev *dev)
1289{
1290 u32 dummy;
1291
21d889d4 1292 if (dev->dev->core_rev < 5)
e4d6b795
MB		 1293 return;
1294 /* Read all entries from the microcode TXstatus FIFO
1295 * and throw them away.
1296 */
1297 while (1) {
1298 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1299 if (!(dummy & 0x00000001))
1300 break;
1301 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1302 }
1303}
1304
1305static u32 b43_jssi_read(struct b43_wldev *dev)
1306{
1307 u32 val = 0;
1308
5c1da23b 1309 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
e4d6b795 1310 val <<= 16;
5c1da23b 1311 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
e4d6b795
MB		 1312
1313 return val;
1314}
1315
1316static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1317{
5c1da23b
HM		 1318 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1319 (jssi & 0x0000FFFF));
1320 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1321 (jssi & 0xFFFF0000) >> 16);
e4d6b795
MB		 1322}
1323
1324static void b43_generate_noise_sample(struct b43_wldev *dev)
1325{
1326 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1327 b43_write32(dev, B43_MMIO_MACCMD,
1328 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1329}
1330
1331static void b43_calculate_link_quality(struct b43_wldev *dev)
1332{
1333 /* Top half of Link Quality calculation. */
1334
ef1a628d
MB		 1335 if (dev->phy.type != B43_PHYTYPE_G)
1336 return;
e4d6b795
MB		 1337 if (dev->noisecalc.calculation_running)
1338 return;
3db1cd5c 1339 dev->noisecalc.calculation_running = true;
e4d6b795
MB		 1340 dev->noisecalc.nr_samples = 0;
1341
1342 b43_generate_noise_sample(dev);
1343}
1344
1345static void handle_irq_noise(struct b43_wldev *dev)
1346{
ef1a628d 1347 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1348 u16 tmp;
1349 u8 noise[4];
1350 u8 i, j;
1351 s32 average;
1352
1353 /* Bottom half of Link Quality calculation. */
1354
ef1a628d
MB		 1355 if (dev->phy.type != B43_PHYTYPE_G)
1356 return;
1357
98a3b2fe
MB		 1358 /* Possible race condition: It might be possible that the user
1359 * changed to a different channel in the meantime since we
1360 * started the calculation. We ignore that fact, since it's
1361 * not really that much of a problem. The background noise is
1362 * an estimation only anyway. Slightly wrong results will get damped
1363 * by the averaging of the 8 sample rounds. Additionally the
1364 * value is shortlived. So it will be replaced by the next noise
1365 * calculation round soon. */
1366
e4d6b795 1367 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1368 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1369 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1370 noise[2] == 0x7F || noise[3] == 0x7F)
1371 goto generate_new;
1372
1373 /* Get the noise samples. */
1374 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1375 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1376 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1378 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1379 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1380 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1381 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1382 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1383 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1384 dev->noisecalc.nr_samples++;
1385 if (dev->noisecalc.nr_samples == 8) {
1386 /* Calculate the Link Quality by the noise samples. */
1387 average = 0;
1388 for (i = 0; i < 8; i++) {
1389 for (j = 0; j < 4; j++)
1390 average += dev->noisecalc.samples[i][j];
1391 }
1392 average /= (8 * 4);
1393 average *= 125;
1394 average += 64;
1395 average /= 128;
1396 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1397 tmp = (tmp / 128) & 0x1F;
1398 if (tmp >= 8)
1399 average += 2;
1400 else
1401 average -= 25;
1402 if (tmp == 8)
1403 average -= 72;
1404 else
1405 average -= 48;
1406
1407 dev->stats.link_noise = average;
3db1cd5c 1408 dev->noisecalc.calculation_running = false;
e4d6b795
MB		 1409 return;
1410 }
98a3b2fe 1411generate_new:
e4d6b795
MB		 1412 b43_generate_noise_sample(dev);
1413}
1414
1415static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1416{
05c914fe 1417 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1418 ///TODO: PS TBTT
1419 } else {
1420 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1421 b43_power_saving_ctl_bits(dev, 0);
1422 }
05c914fe 1423 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3db1cd5c 1424 dev->dfq_valid = true;
e4d6b795
MB		 1425}
1426
1427static void handle_irq_atim_end(struct b43_wldev *dev)
1428{
aa6c7ae2
MB		 1429 if (dev->dfq_valid) {
1430 b43_write32(dev, B43_MMIO_MACCMD,
1431 b43_read32(dev, B43_MMIO_MACCMD)
1432 | B43_MACCMD_DFQ_VALID);
3db1cd5c 1433 dev->dfq_valid = false;
aa6c7ae2 1434 }
e4d6b795
MB		 1435}
1436
1437static void handle_irq_pmq(struct b43_wldev *dev)
1438{
1439 u32 tmp;
1440
1441 //TODO: AP mode.
1442
1443 while (1) {
1444 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1445 if (!(tmp & 0x00000008))
1446 break;
1447 }
1448 /* 16bit write is odd, but correct. */
1449 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1450}
1451
1452static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1453 const u8 *data, u16 size,
e4d6b795
MB		 1454 u16 ram_offset,
1455 u16 shm_size_offset, u8 rate)
1456{
1457 u32 i, tmp;
1458 struct b43_plcp_hdr4 plcp;
1459
1460 plcp.data = 0;
1461 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1462 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1463 ram_offset += sizeof(u32);
1464 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1465 * So leave the first two bytes of the next write blank.
1466 */
1467 tmp = (u32) (data[0]) << 16;
1468 tmp |= (u32) (data[1]) << 24;
1469 b43_ram_write(dev, ram_offset, tmp);
1470 ram_offset += sizeof(u32);
1471 for (i = 2; i < size; i += sizeof(u32)) {
1472 tmp = (u32) (data[i + 0]);
1473 if (i + 1 < size)
1474 tmp |= (u32) (data[i + 1]) << 8;
1475 if (i + 2 < size)
1476 tmp |= (u32) (data[i + 2]) << 16;
1477 if (i + 3 < size)
1478 tmp |= (u32) (data[i + 3]) << 24;
1479 b43_ram_write(dev, ram_offset + i - 2, tmp);
1480 }
1481 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1482 size + sizeof(struct b43_plcp_hdr6));
1483}
1484
5042c507
MB		 1485/* Check if the use of the antenna that ieee80211 told us to
1486 * use is possible. This will fall back to DEFAULT.
1487 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1488u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1489 u8 antenna_nr)
1490{
1491 u8 antenna_mask;
1492
1493 if (antenna_nr == 0) {
1494 /* Zero means "use default antenna". That's always OK. */
1495 return 0;
1496 }
1497
1498 /* Get the mask of available antennas. */
1499 if (dev->phy.gmode)
0581483a 1500 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
5042c507 1501 else
0581483a 1502 antenna_mask = dev->dev->bus_sprom->ant_available_a;
5042c507
MB		 1503
1504 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1505 /* This antenna is not available. Fall back to default. */
1506 return 0;
1507 }
1508
1509 return antenna_nr;
1510}
1511
5042c507
MB		 1512/* Convert a b43 antenna number value to the PHY TX control value. */
1513static u16 b43_antenna_to_phyctl(int antenna)
1514{
1515 switch (antenna) {
1516 case B43_ANTENNA0:
1517 return B43_TXH_PHY_ANT0;
1518 case B43_ANTENNA1:
1519 return B43_TXH_PHY_ANT1;
1520 case B43_ANTENNA2:
1521 return B43_TXH_PHY_ANT2;
1522 case B43_ANTENNA3:
1523 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1524 case B43_ANTENNA_AUTO0:
1525 case B43_ANTENNA_AUTO1:
5042c507
MB		 1526 return B43_TXH_PHY_ANT01AUTO;
1527 }
1528 B43_WARN_ON(1);
1529 return 0;
1530}
1531
e4d6b795
MB		 1532static void b43_write_beacon_template(struct b43_wldev *dev,
1533 u16 ram_offset,
5042c507 1534 u16 shm_size_offset)
e4d6b795 1535{
47f76ca3 1536 unsigned int i, len, variable_len;
e66fee6a
MB		 1537 const struct ieee80211_mgmt *bcn;
1538 const u8 *ie;
3db1cd5c 1539 bool tim_found = false;
5042c507
MB		 1540 unsigned int rate;
1541 u16 ctl;
1542 int antenna;
e039fa4a 1543 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1544
e66fee6a 1545 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
c8e49556 1546 len = min_t(size_t, dev->wl->current_beacon->len,
e4d6b795 1547 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1548 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1549
1550 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1551 len, ram_offset, shm_size_offset, rate);
e66fee6a 1552
5042c507 1553 /* Write the PHY TX control parameters. */
0f4ac38b 1554 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1555 antenna = b43_antenna_to_phyctl(antenna);
1556 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1557 /* We can't send beacons with short preamble. Would get PHY errors. */
1558 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1559 ctl &= ~B43_TXH_PHY_ANT;
1560 ctl &= ~B43_TXH_PHY_ENC;
1561 ctl |= antenna;
1562 if (b43_is_cck_rate(rate))
1563 ctl |= B43_TXH_PHY_ENC_CCK;
1564 else
1565 ctl |= B43_TXH_PHY_ENC_OFDM;
1566 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1567
e66fee6a
MB		 1568 /* Find the position of the TIM and the DTIM_period value
1569 * and write them to SHM. */
1570 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1571 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1572 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1573 uint8_t ie_id, ie_len;
1574
1575 ie_id = ie[i];
1576 ie_len = ie[i + 1];
1577 if (ie_id == 5) {
1578 u16 tim_position;
1579 u16 dtim_period;
1580 /* This is the TIM Information Element */
1581
1582 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1583 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1584 break;
1585 /* A valid TIM is at least 4 bytes long. */
1586 if (ie_len < 4)
1587 break;
3db1cd5c 1588 tim_found = true;
e66fee6a
MB		 1589
1590 tim_position = sizeof(struct b43_plcp_hdr6);
1591 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1592 tim_position += i;
1593
1594 dtim_period = ie[i + 3];
1595
1596 b43_shm_write16(dev, B43_SHM_SHARED,
1597 B43_SHM_SH_TIMBPOS, tim_position);
1598 b43_shm_write16(dev, B43_SHM_SHARED,
1599 B43_SHM_SH_DTIMPER, dtim_period);
1600 break;
1601 }
1602 i += ie_len + 2;
1603 }
1604 if (!tim_found) {
04dea136
JB		 1605 /*
1606 * If ucode wants to modify TIM do it behind the beacon, this
1607 * will happen, for example, when doing mesh networking.
1608 */
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_TIMBPOS,
1611 len + sizeof(struct b43_plcp_hdr6));
1612 b43_shm_write16(dev, B43_SHM_SHARED,
1613 B43_SHM_SH_DTIMPER, 0);
1614 }
1615 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1616}
1617
6b4bec01
MB		 1618static void b43_upload_beacon0(struct b43_wldev *dev)
1619{
1620 struct b43_wl *wl = dev->wl;
1621
1622 if (wl->beacon0_uploaded)
1623 return;
5c1da23b 1624 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
3db1cd5c 1625 wl->beacon0_uploaded = true;
6b4bec01
MB		 1626}
1627
1628static void b43_upload_beacon1(struct b43_wldev *dev)
1629{
1630 struct b43_wl *wl = dev->wl;
1631
1632 if (wl->beacon1_uploaded)
1633 return;
5c1da23b 1634 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
3db1cd5c 1635 wl->beacon1_uploaded = true;
6b4bec01
MB		 1636}
1637
c97a4ccc
MB		 1638static void handle_irq_beacon(struct b43_wldev *dev)
1639{
1640 struct b43_wl *wl = dev->wl;
1641 u32 cmd, beacon0_valid, beacon1_valid;
1642
05c914fe 1643 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
8c23516f
MM		 1644 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1645 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
c97a4ccc
MB		 1646 return;
1647
1648 /* This is the bottom half of the asynchronous beacon update. */
1649
1650 /* Ignore interrupt in the future. */
13790728 1651 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1652
1653 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1654 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1655 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1656
1657 /* Schedule interrupt manually, if busy. */
1658 if (beacon0_valid && beacon1_valid) {
1659 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1660 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1661 return;
1662 }
1663
6b4bec01
MB		 1664 if (unlikely(wl->beacon_templates_virgin)) {
1665 /* We never uploaded a beacon before.
1666 * Upload both templates now, but only mark one valid. */
3db1cd5c 1667 wl->beacon_templates_virgin = false;
6b4bec01
MB		 1668 b43_upload_beacon0(dev);
1669 b43_upload_beacon1(dev);
c97a4ccc
MB		 1670 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1671 cmd |= B43_MACCMD_BEACON0_VALID;
1672 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1673 } else {
1674 if (!beacon0_valid) {
1675 b43_upload_beacon0(dev);
1676 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1677 cmd |= B43_MACCMD_BEACON0_VALID;
1678 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1679 } else if (!beacon1_valid) {
1680 b43_upload_beacon1(dev);
1681 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1682 cmd |= B43_MACCMD_BEACON1_VALID;
1683 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1684 }
c97a4ccc
MB		 1685 }
1686}
1687
36dbd954
MB		 1688static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1689{
1690 u32 old_irq_mask = dev->irq_mask;
1691
1692 /* update beacon right away or defer to irq */
1693 handle_irq_beacon(dev);
1694 if (old_irq_mask != dev->irq_mask) {
1695 /* The handler updated the IRQ mask. */
1696 B43_WARN_ON(!dev->irq_mask);
1697 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1698 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1699 } else {
1700 /* Device interrupts are currently disabled. That means
1701 * we just ran the hardirq handler and scheduled the
1702 * IRQ thread. The thread will write the IRQ mask when
1703 * it finished, so there's nothing to do here. Writing
1704 * the mask _here_ would incorrectly re-enable IRQs. */
1705 }
1706 }
1707}
1708
a82d9922
MB		 1709static void b43_beacon_update_trigger_work(struct work_struct *work)
1710{
1711 struct b43_wl *wl = container_of(work, struct b43_wl,
1712 beacon_update_trigger);
1713 struct b43_wldev *dev;
1714
1715 mutex_lock(&wl->mutex);
1716 dev = wl->current_dev;
1717 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
505fb019 1718 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 1719 /* wl->mutex is enough. */
1720 b43_do_beacon_update_trigger_work(dev);
1721 mmiowb();
1722 } else {
1723 spin_lock_irq(&wl->hardirq_lock);
1724 b43_do_beacon_update_trigger_work(dev);
1725 mmiowb();
1726 spin_unlock_irq(&wl->hardirq_lock);
1727 }
a82d9922
MB		 1728 }
1729 mutex_unlock(&wl->mutex);
1730}
1731
d4df6f1a 1732/* Asynchronously update the packet templates in template RAM.
36dbd954 1733 * Locking: Requires wl->mutex to be locked. */
9d139c81 1734static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1735{
9d139c81
JB		 1736 struct sk_buff *beacon;
1737
e66fee6a
MB		 1738 /* This is the top half of the ansynchronous beacon update.
1739 * The bottom half is the beacon IRQ.
1740 * Beacon update must be asynchronous to avoid sending an
1741 * invalid beacon. This can happen for example, if the firmware
1742 * transmits a beacon while we are updating it. */
e4d6b795 1743
9d139c81
JB		 1744 /* We could modify the existing beacon and set the aid bit in
1745 * the TIM field, but that would probably require resizing and
1746 * moving of data within the beacon template.
1747 * Simply request a new beacon and let mac80211 do the hard work. */
1748 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1749 if (unlikely(!beacon))
1750 return;
1751
e66fee6a
MB		 1752 if (wl->current_beacon)
1753 dev_kfree_skb_any(wl->current_beacon);
1754 wl->current_beacon = beacon;
3db1cd5c
RR		 1755 wl->beacon0_uploaded = false;
1756 wl->beacon1_uploaded = false;
42935eca 1757 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1758}
1759
e4d6b795
MB		 1760static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1761{
1762 b43_time_lock(dev);
21d889d4 1763 if (dev->dev->core_rev >= 3) {
a82d9922
MB		 1764 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1765 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1766 } else {
1767 b43_write16(dev, 0x606, (beacon_int >> 6));
1768 b43_write16(dev, 0x610, beacon_int);
1769 }
1770 b43_time_unlock(dev);
a82d9922 1771 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1772}
1773
afa83e23
MB		 1774static void b43_handle_firmware_panic(struct b43_wldev *dev)
1775{
1776 u16 reason;
1777
1778 /* Read the register that contains the reason code for the panic. */
1779 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1780 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1781
1782 switch (reason) {
1783 default:
1784 b43dbg(dev->wl, "The panic reason is unknown.\n");
1785 /* fallthrough */
1786 case B43_FWPANIC_DIE:
1787 /* Do not restart the controller or firmware.
1788 * The device is nonfunctional from now on.
1789 * Restarting would result in this panic to trigger again,
1790 * so we avoid that recursion. */
1791 break;
1792 case B43_FWPANIC_RESTART:
1793 b43_controller_restart(dev, "Microcode panic");
1794 break;
1795 }
1796}
1797
e4d6b795
MB		 1798static void handle_irq_ucode_debug(struct b43_wldev *dev)
1799{
e48b0eeb 1800 unsigned int i, cnt;
53c06856 1801 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1802 __le16 *buf;
1803
1804 /* The proprietary firmware doesn't have this IRQ. */
1805 if (!dev->fw.opensource)
1806 return;
1807
afa83e23
MB		 1808 /* Read the register that contains the reason code for this IRQ. */
1809 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1810
e48b0eeb
MB		 1811 switch (reason) {
1812 case B43_DEBUGIRQ_PANIC:
afa83e23 1813 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1814 break;
1815 case B43_DEBUGIRQ_DUMP_SHM:
1816 if (!B43_DEBUG)
1817 break; /* Only with driver debugging enabled. */
1818 buf = kmalloc(4096, GFP_ATOMIC);
1819 if (!buf) {
1820 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1821 goto out;
1822 }
1823 for (i = 0; i < 4096; i += 2) {
1824 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1825 buf[i / 2] = cpu_to_le16(tmp);
1826 }
1827 b43info(dev->wl, "Shared memory dump:\n");
1828 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1829 16, 2, buf, 4096, 1);
1830 kfree(buf);
1831 break;
1832 case B43_DEBUGIRQ_DUMP_REGS:
1833 if (!B43_DEBUG)
1834 break; /* Only with driver debugging enabled. */
1835 b43info(dev->wl, "Microcode register dump:\n");
1836 for (i = 0, cnt = 0; i < 64; i++) {
1837 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1838 if (cnt == 0)
1839 printk(KERN_INFO);
1840 printk("r%02u: 0x%04X ", i, tmp);
1841 cnt++;
1842 if (cnt == 6) {
1843 printk("\n");
1844 cnt = 0;
1845 }
1846 }
1847 printk("\n");
1848 break;
53c06856
MB		 1849 case B43_DEBUGIRQ_MARKER:
1850 if (!B43_DEBUG)
1851 break; /* Only with driver debugging enabled. */
1852 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1853 B43_MARKER_ID_REG);
1854 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1855 B43_MARKER_LINE_REG);
1856 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1857 "at line number %u\n",
1858 marker_id, marker_line);
1859 break;
e48b0eeb
MB		 1860 default:
1861 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1862 reason);
1863 }
1864out:
afa83e23
MB		 1865 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1866 b43_shm_write16(dev, B43_SHM_SCRATCH,
1867 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1868}
1869
36dbd954 1870static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1871{
1872 u32 reason;
1873 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1874 u32 merged_dma_reason = 0;
21954c36 1875 int i;
e4d6b795 1876
36dbd954
MB		 1877 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1878 return;
e4d6b795
MB		 1879
1880 reason = dev->irq_reason;
1881 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1882 dma_reason[i] = dev->dma_reason[i];
1883 merged_dma_reason |= dma_reason[i];
1884 }
1885
1886 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1887 b43err(dev->wl, "MAC transmission error\n");
1888
00e0b8cb 1889 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1890 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1891 rmb();
1892 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1893 atomic_set(&dev->phy.txerr_cnt,
1894 B43_PHY_TX_BADNESS_LIMIT);
1895 b43err(dev->wl, "Too many PHY TX errors, "
1896 "restarting the controller\n");
1897 b43_controller_restart(dev, "PHY TX errors");
1898 }
1899 }
e4d6b795 1900
73b82bf0
TJ		 1901 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
1902 b43err(dev->wl,
1903 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1904 dma_reason[0], dma_reason[1],
1905 dma_reason[2], dma_reason[3],
1906 dma_reason[4], dma_reason[5]);
1907 b43err(dev->wl, "This device does not support DMA "
bb64d95e 1908 "on your system. It will now be switched to PIO.\n");
73b82bf0
TJ		 1909 /* Fall back to PIO transfers if we get fatal DMA errors! */
1910 dev->use_pio = true;
1911 b43_controller_restart(dev, "DMA error");
1912 return;
e4d6b795
MB		 1913 }
1914
1915 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1916 handle_irq_ucode_debug(dev);
1917 if (reason & B43_IRQ_TBTT_INDI)
1918 handle_irq_tbtt_indication(dev);
1919 if (reason & B43_IRQ_ATIM_END)
1920 handle_irq_atim_end(dev);
1921 if (reason & B43_IRQ_BEACON)
1922 handle_irq_beacon(dev);
1923 if (reason & B43_IRQ_PMQ)
1924 handle_irq_pmq(dev);
21954c36
MB		 1925 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1926 ;/* TODO */
1927 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1928 handle_irq_noise(dev);
1929
1930 /* Check the DMA reason registers for received data. */
73b82bf0
TJ		 1931 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
1932 if (B43_DEBUG)
1933 b43warn(dev->wl, "RX descriptor underrun\n");
1934 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
1935 }
5100d5ac
MB		 1936 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1937 if (b43_using_pio_transfers(dev))
1938 b43_pio_rx(dev->pio.rx_queue);
1939 else
1940 b43_dma_rx(dev->dma.rx_ring);
1941 }
e4d6b795
MB		 1942 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1943 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1944 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1945 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1946 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1947
21954c36 1948 if (reason & B43_IRQ_TX_OK)
e4d6b795 1949 handle_irq_transmit_status(dev);
e4d6b795 1950
36dbd954 1951 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1952 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1953
1954#if B43_DEBUG
1955 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1956 dev->irq_count++;
1957 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1958 if (reason & (1 << i))
1959 dev->irq_bit_count[i]++;
1960 }
1961 }
1962#endif
e4d6b795
MB		 1963}
1964
36dbd954
MB		 1965/* Interrupt thread handler. Handles device interrupts in thread context. */
1966static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1967{
36dbd954 1968 struct b43_wldev *dev = dev_id;
e4d6b795 1969
36dbd954
MB		 1970 mutex_lock(&dev->wl->mutex);
1971 b43_do_interrupt_thread(dev);
1972 mmiowb();
1973 mutex_unlock(&dev->wl->mutex);
1974
1975 return IRQ_HANDLED;
e4d6b795
MB		 1976}
1977
36dbd954 1978static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1979{
e4d6b795
MB		 1980 u32 reason;
1981
36dbd954
MB		 1982 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1983 * On SDIO, this runs under wl->mutex. */
e4d6b795 1984
e4d6b795
MB		 1985 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1986 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1987 return IRQ_NONE;
13790728 1988 reason &= dev->irq_mask;
e4d6b795 1989 if (!reason)
cae56147 1990 return IRQ_NONE;
e4d6b795
MB		 1991
1992 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
73b82bf0 1993 & 0x0001FC00;
e4d6b795
MB		 1994 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1995 & 0x0000DC00;
1996 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1997 & 0x0000DC00;
1998 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1999 & 0x0001DC00;
2000 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2001 & 0x0000DC00;
13790728 2002/* Unused ring
e4d6b795
MB		 2003 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2004 & 0x0000DC00;
13790728 2005*/
e4d6b795 2006
36dbd954
MB		 2007 /* ACK the interrupt. */
2008 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2009 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2010 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2011 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2012 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2013 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2014/* Unused ring
2015 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2016*/
2017
2018 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 2019 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 2020 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 2021 dev->irq_reason = reason;
36dbd954
MB		 2022
2023 return IRQ_WAKE_THREAD;
2024}
2025
2026/* Interrupt handler top-half. This runs with interrupts disabled. */
2027static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2028{
2029 struct b43_wldev *dev = dev_id;
2030 irqreturn_t ret;
2031
2032 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2033 return IRQ_NONE;
2034
2035 spin_lock(&dev->wl->hardirq_lock);
2036 ret = b43_do_interrupt(dev);
e4d6b795 2037 mmiowb();
36dbd954 2038 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 2039
2040 return ret;
2041}
2042
3dbba8e2
AH		 2043/* SDIO interrupt handler. This runs in process context. */
2044static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2045{
2046 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 2047 irqreturn_t ret;
2048
3dbba8e2 2049 mutex_lock(&wl->mutex);
3dbba8e2
AH		 2050
2051 ret = b43_do_interrupt(dev);
2052 if (ret == IRQ_WAKE_THREAD)
2053 b43_do_interrupt_thread(dev);
2054
3dbba8e2
AH		 2055 mutex_unlock(&wl->mutex);
2056}
2057
1a9f5093 2058void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 2059{
2060 release_firmware(fw->data);
2061 fw->data = NULL;
2062 fw->filename = NULL;
2063}
2064
e4d6b795
MB		 2065static void b43_release_firmware(struct b43_wldev *dev)
2066{
0673effd 2067 complete(&dev->fw_load_complete);
1a9f5093
MB		 2068 b43_do_release_fw(&dev->fw.ucode);
2069 b43_do_release_fw(&dev->fw.pcm);
2070 b43_do_release_fw(&dev->fw.initvals);
2071 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 2072}
2073
eb189d8b 2074static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 2075{
fc68ed4f
HE		 2076 const char text[] =
2077 "You must go to " \
2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2079 "and download the correct firmware for this driver version. " \
2080 "Please carefully read all instructions on this website.\n";
eb189d8b 2081
eb189d8b
MB		 2082 if (error)
2083 b43err(wl, text);
2084 else
2085 b43warn(wl, text);
e4d6b795
MB		 2086}
2087
5e20a4b5
LF		 2088static void b43_fw_cb(const struct firmware *firmware, void *context)
2089{
2090 struct b43_request_fw_context *ctx = context;
2091
2092 ctx->blob = firmware;
0673effd 2093 complete(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2094}
2095
1a9f5093
MB		 2096int b43_do_request_fw(struct b43_request_fw_context *ctx,
2097 const char *name,
5e20a4b5 2098 struct b43_firmware_file *fw, bool async)
e4d6b795 2099{
e4d6b795
MB		 2100 struct b43_fw_header *hdr;
2101 u32 size;
2102 int err;
2103
61cb5dd6
MB		 2104 if (!name) {
2105 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 2106 /* FIXME: We should probably keep it anyway, to save some headache
2107 * on suspend/resume with multiband devices. */
2108 b43_do_release_fw(fw);
e4d6b795 2109 return 0;
61cb5dd6
MB		 2110 }
2111 if (fw->filename) {
1a9f5093
MB		 2112 if ((fw->type == ctx->req_type) &&
2113 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2114 return 0; /* Already have this fw. */
2115 /* Free the cached firmware first. */
1a9f5093
MB		 2116 /* FIXME: We should probably do this later after we successfully
2117 * got the new fw. This could reduce headache with multiband devices.
2118 * We could also redesign this to cache the firmware for all possible
2119 * bands all the time. */
2120 b43_do_release_fw(fw);
61cb5dd6 2121 }
e4d6b795 2122
1a9f5093
MB		 2123 switch (ctx->req_type) {
2124 case B43_FWTYPE_PROPRIETARY:
2125 snprintf(ctx->fwname, sizeof(ctx->fwname),
2126 "b43%s/%s.fw",
2127 modparam_fwpostfix, name);
2128 break;
2129 case B43_FWTYPE_OPENSOURCE:
2130 snprintf(ctx->fwname, sizeof(ctx->fwname),
2131 "b43-open%s/%s.fw",
2132 modparam_fwpostfix, name);
2133 break;
2134 default:
2135 B43_WARN_ON(1);
2136 return -ENOSYS;
2137 }
5e20a4b5
LF		 2138 if (async) {
2139 /* do this part asynchronously */
0673effd 2140 init_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2141 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2142 ctx->dev->dev->dev, GFP_KERNEL,
2143 ctx, b43_fw_cb);
2144 if (err < 0) {
2145 pr_err("Unable to load firmware\n");
2146 return err;
2147 }
0673effd 2148 wait_for_completion(&ctx->dev->fw_load_complete);
5e20a4b5
LF		 2149 if (ctx->blob)
2150 goto fw_ready;
2151 /* On some ARM systems, the async request will fail, but the next sync
0673effd 2152 * request works. For this reason, we fall through here
5e20a4b5
LF		 2153 */
2154 }
2155 err = request_firmware(&ctx->blob, ctx->fwname,
2156 ctx->dev->dev->dev);
68217832 2157 if (err == -ENOENT) {
1a9f5093
MB		 2158 snprintf(ctx->errors[ctx->req_type],
2159 sizeof(ctx->errors[ctx->req_type]),
5e20a4b5
LF		 2160 "Firmware file \"%s\" not found\n",
2161 ctx->fwname);
68217832
MB		 2162 return err;
2163 } else if (err) {
1a9f5093
MB		 2164 snprintf(ctx->errors[ctx->req_type],
2165 sizeof(ctx->errors[ctx->req_type]),
2166 "Firmware file \"%s\" request failed (err=%d)\n",
2167 ctx->fwname, err);
e4d6b795
MB		 2168 return err;
2169 }
5e20a4b5
LF		 2170fw_ready:
2171 if (ctx->blob->size < sizeof(struct b43_fw_header))
e4d6b795 2172 goto err_format;
5e20a4b5 2173 hdr = (struct b43_fw_header *)(ctx->blob->data);
e4d6b795
MB		 2174 switch (hdr->type) {
2175 case B43_FW_TYPE_UCODE:
2176 case B43_FW_TYPE_PCM:
2177 size = be32_to_cpu(hdr->size);
5e20a4b5 2178 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2179 goto err_format;
2180 /* fallthrough */
2181 case B43_FW_TYPE_IV:
2182 if (hdr->ver != 1)
2183 goto err_format;
2184 break;
2185 default:
2186 goto err_format;
2187 }
2188
5e20a4b5 2189 fw->data = ctx->blob;
61cb5dd6 2190 fw->filename = name;
1a9f5093 2191 fw->type = ctx->req_type;
61cb5dd6
MB		 2192
2193 return 0;
e4d6b795
MB		 2194
2195err_format:
1a9f5093
MB		 2196 snprintf(ctx->errors[ctx->req_type],
2197 sizeof(ctx->errors[ctx->req_type]),
2198 "Firmware file \"%s\" format error.\n", ctx->fwname);
5e20a4b5 2199 release_firmware(ctx->blob);
61cb5dd6 2200
e4d6b795
MB		 2201 return -EPROTO;
2202}
2203
a60f99f7 2204/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
1a9f5093 2205static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2206{
1a9f5093
MB		 2207 struct b43_wldev *dev = ctx->dev;
2208 struct b43_firmware *fw = &ctx->dev->fw;
a60f99f7 2209 struct b43_phy *phy = &dev->phy;
21d889d4 2210 const u8 rev = ctx->dev->dev->core_rev;
e4d6b795 2211 const char *filename;
e4d6b795
MB		 2212 int err;
2213
61cb5dd6 2214 /* Get microcode */
a60f99f7
RM		 2215 filename = NULL;
2216 switch (rev) {
2217 case 42:
2218 if (phy->type == B43_PHYTYPE_AC)
2219 filename = "ucode42";
2220 break;
2221 case 33:
2222 if (phy->type == B43_PHYTYPE_LCN40)
2223 filename = "ucode33_lcn40";
2224 break;
2225 case 30:
2226 if (phy->type == B43_PHYTYPE_N)
2227 filename = "ucode30_mimo";
2228 break;
2229 case 29:
2230 if (phy->type == B43_PHYTYPE_HT)
2231 filename = "ucode29_mimo";
2232 break;
2233 case 26:
2234 if (phy->type == B43_PHYTYPE_HT)
2235 filename = "ucode26_mimo";
2236 break;
2237 case 28:
2238 case 25:
2239 if (phy->type == B43_PHYTYPE_N)
2240 filename = "ucode25_mimo";
2241 else if (phy->type == B43_PHYTYPE_LCN)
2242 filename = "ucode25_lcn";
2243 break;
2244 case 24:
2245 if (phy->type == B43_PHYTYPE_LCN)
2246 filename = "ucode24_lcn";
2247 break;
2248 case 23:
2249 if (phy->type == B43_PHYTYPE_N)
2250 filename = "ucode16_mimo";
2251 break;
2252 case 16 ... 19:
2253 if (phy->type == B43_PHYTYPE_N)
2254 filename = "ucode16_mimo";
2255 else if (phy->type == B43_PHYTYPE_LP)
2256 filename = "ucode16_lp";
2257 break;
2258 case 15:
759b973b 2259 filename = "ucode15";
a60f99f7
RM		 2260 break;
2261 case 14:
2262 filename = "ucode14";
2263 break;
2264 case 13:
2265 filename = "ucode13";
2266 break;
2267 case 11 ... 12:
2268 filename = "ucode11";
2269 break;
2270 case 5 ... 10:
2271 filename = "ucode5";
2272 break;
6ff1e5cf 2273 }
a60f99f7
RM		 2274 if (!filename)
2275 goto err_no_ucode;
5e20a4b5 2276 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
61cb5dd6
MB		 2277 if (err)
2278 goto err_load;
2279
2280 /* Get PCM code */
2281 if ((rev >= 5) && (rev <= 10))
2282 filename = "pcm5";
2283 else if (rev >= 11)
2284 filename = NULL;
2285 else
2286 goto err_no_pcm;
3db1cd5c 2287 fw->pcm_request_failed = false;
5e20a4b5 2288 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
68217832
MB		 2289 if (err == -ENOENT) {
2290 /* We did not find a PCM file? Not fatal, but
2291 * core rev <= 10 must do without hwcrypto then. */
3db1cd5c 2292 fw->pcm_request_failed = true;
68217832 2293 } else if (err)
61cb5dd6
MB		 2294 goto err_load;
2295
2296 /* Get initvals */
a60f99f7 2297 filename = NULL;
61cb5dd6 2298 switch (dev->phy.type) {
61cb5dd6 2299 case B43_PHYTYPE_G:
a60f99f7 2300 if (rev == 13)
e9304882 2301 filename = "b0g0initvals13";
a60f99f7
RM		 2302 else if (rev >= 5 && rev <= 10)
2303 filename = "b0g0initvals5";
61cb5dd6
MB		 2304 break;
2305 case B43_PHYTYPE_N:
a60f99f7
RM		 2306 if (rev == 30)
2307 filename = "n16initvals30";
2308 else if (rev == 28 || rev == 25)
2309 filename = "n0initvals25";
2310 else if (rev == 24)
2311 filename = "n0initvals24";
2312 else if (rev == 23)
2313 filename = "n0initvals16"; /* What about n0initvals22? */
2314 else if (rev >= 16 && rev <= 18)
e41596a1 2315 filename = "n0initvals16";
a60f99f7 2316 else if (rev >= 11 && rev <= 12)
61cb5dd6 2317 filename = "n0initvals11";
61cb5dd6 2318 break;
759b973b 2319 case B43_PHYTYPE_LP:
a60f99f7
RM		 2320 if (rev >= 16 && rev <= 18)
2321 filename = "lp0initvals16";
2322 else if (rev == 15)
2323 filename = "lp0initvals15";
759b973b
GS		 2324 else if (rev == 14)
2325 filename = "lp0initvals14";
a60f99f7
RM		 2326 else if (rev == 13)
2327 filename = "lp0initvals13";
759b973b 2328 break;
8b9bda75
RM		 2329 case B43_PHYTYPE_HT:
2330 if (rev == 29)
2331 filename = "ht0initvals29";
a60f99f7
RM		 2332 else if (rev == 26)
2333 filename = "ht0initvals26";
8b9bda75
RM		 2334 break;
2335 case B43_PHYTYPE_LCN:
2336 if (rev == 24)
2337 filename = "lcn0initvals24";
8b9bda75 2338 break;
a60f99f7
RM		 2339 case B43_PHYTYPE_LCN40:
2340 if (rev == 33)
2341 filename = "lcn400initvals33";
2342 break;
2343 case B43_PHYTYPE_AC:
2344 if (rev == 42)
2345 filename = "ac1initvals42";
2346 break;
e4d6b795 2347 }
a60f99f7
RM		 2348 if (!filename)
2349 goto err_no_initvals;
5e20a4b5 2350 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
61cb5dd6
MB		 2351 if (err)
2352 goto err_load;
2353
2354 /* Get bandswitch initvals */
a60f99f7 2355 filename = NULL;
61cb5dd6 2356 switch (dev->phy.type) {
61cb5dd6 2357 case B43_PHYTYPE_G:
a60f99f7
RM		 2358 if (rev == 13)
2359 filename = "b0g0bsinitvals13";
2360 else if (rev >= 5 && rev <= 10)
61cb5dd6 2361 filename = "b0g0bsinitvals5";
61cb5dd6
MB		 2362 break;
2363 case B43_PHYTYPE_N:
a60f99f7
RM		 2364 if (rev == 30)
2365 filename = "n16bsinitvals30";
2366 else if (rev == 28 || rev == 25)
2367 filename = "n0bsinitvals25";
2368 else if (rev == 24)
2369 filename = "n0bsinitvals24";
2370 else if (rev == 23)
2371 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2372 else if (rev >= 16 && rev <= 18)
e41596a1 2373 filename = "n0bsinitvals16";
a60f99f7 2374 else if (rev >= 11 && rev <= 12)
61cb5dd6 2375 filename = "n0bsinitvals11";
61cb5dd6 2376 break;
759b973b 2377 case B43_PHYTYPE_LP:
a60f99f7
RM		 2378 if (rev >= 16 && rev <= 18)
2379 filename = "lp0bsinitvals16";
2380 else if (rev == 15)
2381 filename = "lp0bsinitvals15";
759b973b
GS		 2382 else if (rev == 14)
2383 filename = "lp0bsinitvals14";
a60f99f7
RM		 2384 else if (rev == 13)
2385 filename = "lp0bsinitvals13";
759b973b 2386 break;
8b9bda75
RM		 2387 case B43_PHYTYPE_HT:
2388 if (rev == 29)
2389 filename = "ht0bsinitvals29";
a60f99f7
RM		 2390 else if (rev == 26)
2391 filename = "ht0bsinitvals26";
8b9bda75
RM		 2392 break;
2393 case B43_PHYTYPE_LCN:
2394 if (rev == 24)
2395 filename = "lcn0bsinitvals24";
8b9bda75 2396 break;
a60f99f7
RM		 2397 case B43_PHYTYPE_LCN40:
2398 if (rev == 33)
2399 filename = "lcn400bsinitvals33";
2400 break;
2401 case B43_PHYTYPE_AC:
2402 if (rev == 42)
2403 filename = "ac1bsinitvals42";
2404 break;
e4d6b795 2405 }
a60f99f7
RM		 2406 if (!filename)
2407 goto err_no_initvals;
5e20a4b5 2408 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
61cb5dd6
MB		 2409 if (err)
2410 goto err_load;
e4d6b795 2411
097b0e1b
JB		 2412 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2413
e4d6b795
MB		 2414 return 0;
2415
e4d6b795 2416err_no_ucode:
1a9f5093
MB		 2417 err = ctx->fatal_failure = -EOPNOTSUPP;
2418 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2419 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2420 goto error;
2421
2422err_no_pcm:
1a9f5093
MB		 2423 err = ctx->fatal_failure = -EOPNOTSUPP;
2424 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2425 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2426 goto error;
2427
2428err_no_initvals:
1a9f5093
MB		 2429 err = ctx->fatal_failure = -EOPNOTSUPP;
2430 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2431 "is required for your device (wl-core rev %u)\n", rev);
2432 goto error;
2433
2434err_load:
2435 /* We failed to load this firmware image. The error message
2436 * already is in ctx->errors. Return and let our caller decide
2437 * what to do. */
e4d6b795
MB		 2438 goto error;
2439
2440error:
2441 b43_release_firmware(dev);
2442 return err;
2443}
2444
6b6fa586
LF		 2445static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2446static void b43_one_core_detach(struct b43_bus_dev *dev);
09164043 2447static int b43_rng_init(struct b43_wl *wl);
6b6fa586
LF		 2448
2449static void b43_request_firmware(struct work_struct *work)
1a9f5093 2450{
6b6fa586
LF		 2451 struct b43_wl *wl = container_of(work,
2452 struct b43_wl, firmware_load);
2453 struct b43_wldev *dev = wl->current_dev;
1a9f5093
MB		 2454 struct b43_request_fw_context *ctx;
2455 unsigned int i;
2456 int err;
2457 const char *errmsg;
2458
2459 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2460 if (!ctx)
6b6fa586 2461 return;
1a9f5093
MB		 2462 ctx->dev = dev;
2463
2464 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2465 err = b43_try_request_fw(ctx);
2466 if (!err)
6b6fa586
LF		 2467 goto start_ieee80211; /* Successfully loaded it. */
2468 /* Was fw version known? */
2469 if (ctx->fatal_failure)
1a9f5093
MB		 2470 goto out;
2471
6b6fa586 2472 /* proprietary fw not found, try open source */
1a9f5093
MB		 2473 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2474 err = b43_try_request_fw(ctx);
2475 if (!err)
6b6fa586
LF		 2476 goto start_ieee80211; /* Successfully loaded it. */
2477 if(ctx->fatal_failure)
1a9f5093
MB		 2478 goto out;
2479
2480 /* Could not find a usable firmware. Print the errors. */
2481 for (i = 0; i < B43_NR_FWTYPES; i++) {
2482 errmsg = ctx->errors[i];
2483 if (strlen(errmsg))
e0e29b68 2484 b43err(dev->wl, "%s", errmsg);
1a9f5093
MB		 2485 }
2486 b43_print_fw_helptext(dev->wl, 1);
6b6fa586
LF		 2487 goto out;
2488
2489start_ieee80211:
097b0e1b
JB		 2490 wl->hw->queues = B43_QOS_QUEUE_NUM;
2491 if (!modparam_qos || dev->fw.opensource)
2492 wl->hw->queues = 1;
2493
6b6fa586
LF		 2494 err = ieee80211_register_hw(wl->hw);
2495 if (err)
2496 goto err_one_core_detach;
e64add27 2497 wl->hw_registred = true;
6b6fa586 2498 b43_leds_register(wl->current_dev);
09164043
LF		 2499
2500 /* Register HW RNG driver */
2501 b43_rng_init(wl);
2502
6b6fa586
LF		 2503 goto out;
2504
2505err_one_core_detach:
2506 b43_one_core_detach(dev->dev);
1a9f5093
MB		 2507
2508out:
2509 kfree(ctx);
1a9f5093
MB		 2510}
2511
e4d6b795
MB		 2512static int b43_upload_microcode(struct b43_wldev *dev)
2513{
652caa5b 2514 struct wiphy *wiphy = dev->wl->hw->wiphy;
e4d6b795
MB		 2515 const size_t hdr_len = sizeof(struct b43_fw_header);
2516 const __be32 *data;
2517 unsigned int i, len;
2518 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2519 u32 tmp, macctl;
e4d6b795
MB		 2520 int err = 0;
2521
1f7d87b0
MB		 2522 /* Jump the microcode PSM to offset 0 */
2523 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2524 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2525 macctl |= B43_MACCTL_PSM_JMP0;
2526 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2527 /* Zero out all microcode PSM registers and shared memory. */
2528 for (i = 0; i < 64; i++)
2529 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2530 for (i = 0; i < 4096; i += 2)
2531 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2532
e4d6b795 2533 /* Upload Microcode. */
61cb5dd6
MB		 2534 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2535 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2536 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2537 for (i = 0; i < len; i++) {
2538 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2539 udelay(10);
2540 }
2541
61cb5dd6 2542 if (dev->fw.pcm.data) {
e4d6b795 2543 /* Upload PCM data. */
61cb5dd6
MB		 2544 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2545 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2546 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2547 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2548 /* No need for autoinc bit in SHM_HW */
2549 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2550 for (i = 0; i < len; i++) {
2551 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2552 udelay(10);
2553 }
2554 }
2555
2556 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2557
2558 /* Start the microcode PSM */
5056635c
RM		 2559 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2560 B43_MACCTL_PSM_RUN);
e4d6b795
MB		 2561
2562 /* Wait for the microcode to load and respond */
2563 i = 0;
2564 while (1) {
2565 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2566 if (tmp == B43_IRQ_MAC_SUSPENDED)
2567 break;
2568 i++;
1f7d87b0 2569 if (i >= 20) {
e4d6b795 2570 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2571 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2572 err = -ENODEV;
1f7d87b0
MB		 2573 goto error;
2574 }
e175e996 2575 msleep(50);
e4d6b795
MB		 2576 }
2577 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2578
2579 /* Get and check the revisions. */
2580 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2581 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2582 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2583 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2584
2585 if (fwrev <= 0x128) {
2586 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2587 "binary drivers older than version 4.x is unsupported. "
2588 "You must upgrade your firmware files.\n");
eb189d8b 2589 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2590 err = -EOPNOTSUPP;
1f7d87b0 2591 goto error;
e4d6b795 2592 }
e4d6b795
MB		 2593 dev->fw.rev = fwrev;
2594 dev->fw.patch = fwpatch;
5d852905
RM		 2595 if (dev->fw.rev >= 598)
2596 dev->fw.hdr_format = B43_FW_HDR_598;
2597 else if (dev->fw.rev >= 410)
efe0249b
RM		 2598 dev->fw.hdr_format = B43_FW_HDR_410;
2599 else
2600 dev->fw.hdr_format = B43_FW_HDR_351;
097b0e1b 2601 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
e48b0eeb 2602
097b0e1b 2603 dev->qos_enabled = dev->wl->hw->queues > 1;
403a3a13 2604 /* Default to firmware/hardware crypto acceleration. */
3db1cd5c 2605 dev->hwcrypto_enabled = true;
403a3a13 2606
e48b0eeb 2607 if (dev->fw.opensource) {
403a3a13
MB		 2608 u16 fwcapa;
2609
e48b0eeb
MB		 2610 /* Patchlevel info is encoded in the "time" field. */
2611 dev->fw.patch = fwtime;
403a3a13
MB		 2612 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2613 dev->fw.rev, dev->fw.patch);
2614
2615 fwcapa = b43_fwcapa_read(dev);
2616 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2617 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2618 /* Disable hardware crypto and fall back to software crypto. */
3db1cd5c 2619 dev->hwcrypto_enabled = false;
403a3a13 2620 }
097b0e1b
JB		 2621 /* adding QoS support should use an offline discovery mechanism */
2622 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
e48b0eeb
MB		 2623 } else {
2624 b43info(dev->wl, "Loading firmware version %u.%u "
2625 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2626 fwrev, fwpatch,
2627 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2628 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2629 if (dev->fw.pcm_request_failed) {
2630 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2631 "Hardware accelerated cryptography is disabled.\n");
2632 b43_print_fw_helptext(dev->wl, 0);
2633 }
e48b0eeb 2634 }
e4d6b795 2635
652caa5b
JL		 2636 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2637 dev->fw.rev, dev->fw.patch);
21d889d4 2638 wiphy->hw_version = dev->dev->core_id;
652caa5b 2639
efe0249b 2640 if (dev->fw.hdr_format == B43_FW_HDR_351) {
c557289c
MB		 2641 /* We're over the deadline, but we keep support for old fw
2642 * until it turns out to be in major conflict with something new. */
eb189d8b 2643 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2644 "Support for old firmware will be removed soon "
2645 "(official deadline was July 2008).\n");
eb189d8b
MB		 2646 b43_print_fw_helptext(dev->wl, 0);
2647 }
2648
1f7d87b0
MB		 2649 return 0;
2650
2651error:
5056635c
RM		 2652 /* Stop the microcode PSM. */
2653 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2654 B43_MACCTL_PSM_JMP0);
1f7d87b0 2655
e4d6b795
MB		 2656 return err;
2657}
2658
2659static int b43_write_initvals(struct b43_wldev *dev,
2660 const struct b43_iv *ivals,
2661 size_t count,
2662 size_t array_size)
2663{
2664 const struct b43_iv *iv;
2665 u16 offset;
2666 size_t i;
2667 bool bit32;
2668
2669 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2670 iv = ivals;
2671 for (i = 0; i < count; i++) {
2672 if (array_size < sizeof(iv->offset_size))
2673 goto err_format;
2674 array_size -= sizeof(iv->offset_size);
2675 offset = be16_to_cpu(iv->offset_size);
2676 bit32 = !!(offset & B43_IV_32BIT);
2677 offset &= B43_IV_OFFSET_MASK;
2678 if (offset >= 0x1000)
2679 goto err_format;
2680 if (bit32) {
2681 u32 value;
2682
2683 if (array_size < sizeof(iv->data.d32))
2684 goto err_format;
2685 array_size -= sizeof(iv->data.d32);
2686
533dd1b0 2687 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2688 b43_write32(dev, offset, value);
2689
2690 iv = (const struct b43_iv *)((const uint8_t *)iv +
2691 sizeof(__be16) +
2692 sizeof(__be32));
2693 } else {
2694 u16 value;
2695
2696 if (array_size < sizeof(iv->data.d16))
2697 goto err_format;
2698 array_size -= sizeof(iv->data.d16);
2699
2700 value = be16_to_cpu(iv->data.d16);
2701 b43_write16(dev, offset, value);
2702
2703 iv = (const struct b43_iv *)((const uint8_t *)iv +
2704 sizeof(__be16) +
2705 sizeof(__be16));
2706 }
2707 }
2708 if (array_size)
2709 goto err_format;
2710
2711 return 0;
2712
2713err_format:
2714 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2715 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2716
2717 return -EPROTO;
2718}
2719
2720static int b43_upload_initvals(struct b43_wldev *dev)
2721{
2722 const size_t hdr_len = sizeof(struct b43_fw_header);
2723 const struct b43_fw_header *hdr;
2724 struct b43_firmware *fw = &dev->fw;
2725 const struct b43_iv *ivals;
2726 size_t count;
e4d6b795 2727
61cb5dd6
MB		 2728 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2729 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795 2730 count = be32_to_cpu(hdr->size);
0f68423f 2731 return b43_write_initvals(dev, ivals, count,
61cb5dd6 2732 fw->initvals.data->size - hdr_len);
0f68423f 2733}
e4d6b795 2734
0f68423f
RM		 2735static int b43_upload_initvals_band(struct b43_wldev *dev)
2736{
2737 const size_t hdr_len = sizeof(struct b43_fw_header);
2738 const struct b43_fw_header *hdr;
2739 struct b43_firmware *fw = &dev->fw;
2740 const struct b43_iv *ivals;
2741 size_t count;
2742
2743 if (!fw->initvals_band.data)
2744 return 0;
2745
2746 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2747 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2748 count = be32_to_cpu(hdr->size);
2749 return b43_write_initvals(dev, ivals, count,
2750 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2751}
2752
2753/* Initialize the GPIOs
2754 * http://bcm-specs.sipsolutions.net/GPIO
2755 */
bd7c8a59
RM		 2756
2757#ifdef CONFIG_B43_SSB
c4a2a081 2758static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
e4d6b795 2759{
d48ae5c8 2760 struct ssb_bus *bus = dev->dev->sdev->bus;
c4a2a081
RM		 2761
2762#ifdef CONFIG_SSB_DRIVER_PCICORE
2763 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2764#else
2765 return bus->chipco.dev;
2766#endif
2767}
bd7c8a59 2768#endif
c4a2a081 2769
e4d6b795
MB		 2770static int b43_gpio_init(struct b43_wldev *dev)
2771{
bd7c8a59 2772#ifdef CONFIG_B43_SSB
c4a2a081 2773 struct ssb_device *gpiodev;
bd7c8a59 2774#endif
e4d6b795
MB		 2775 u32 mask, set;
2776
5056635c
RM		 2777 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2778 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
e4d6b795
MB		 2779
2780 mask = 0x0000001F;
2781 set = 0x0000000F;
c244e08c 2782 if (dev->dev->chip_id == 0x4301) {
e4d6b795
MB		 2783 mask |= 0x0060;
2784 set |= 0x0060;
828afd26
RM		 2785 } else if (dev->dev->chip_id == 0x5354) {
2786 /* Don't allow overtaking buttons GPIOs */
2787 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
e4d6b795 2788 }
828afd26 2789
e4d6b795
MB		 2790 if (0 /* FIXME: conditional unknown */ ) {
2791 b43_write16(dev, B43_MMIO_GPIO_MASK,
2792 b43_read16(dev, B43_MMIO_GPIO_MASK)
2793 | 0x0100);
828afd26
RM		 2794 /* BT Coexistance Input */
2795 mask |= 0x0080;
2796 set |= 0x0080;
2797 /* BT Coexistance Out */
2798 mask |= 0x0100;
2799 set |= 0x0100;
e4d6b795 2800 }
0581483a 2801 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
828afd26 2802 /* PA is controlled by gpio 9, let ucode handle it */
e4d6b795
MB		 2803 b43_write16(dev, B43_MMIO_GPIO_MASK,
2804 b43_read16(dev, B43_MMIO_GPIO_MASK)
2805 | 0x0200);
2806 mask |= 0x0200;
2807 set |= 0x0200;
2808 }
e4d6b795 2809
6cbab0d9 2810 switch (dev->dev->bus_type) {
42c9a458
RM		 2811#ifdef CONFIG_B43_BCMA
2812 case B43_BUS_BCMA:
0a64baea 2813 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
42c9a458
RM		 2814 break;
2815#endif
6cbab0d9
RM		 2816#ifdef CONFIG_B43_SSB
2817 case B43_BUS_SSB:
2818 gpiodev = b43_ssb_gpio_dev(dev);
2819 if (gpiodev)
2820 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2821 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
828afd26 2822 & ~mask) | set);
6cbab0d9
RM		 2823 break;
2824#endif
2825 }
e4d6b795
MB		 2826
2827 return 0;
2828}
2829
2830/* Turn off all GPIO stuff. Call this on module unload, for example. */
2831static void b43_gpio_cleanup(struct b43_wldev *dev)
2832{
bd7c8a59 2833#ifdef CONFIG_B43_SSB
c4a2a081 2834 struct ssb_device *gpiodev;
bd7c8a59 2835#endif
e4d6b795 2836
6cbab0d9 2837 switch (dev->dev->bus_type) {
42c9a458
RM		 2838#ifdef CONFIG_B43_BCMA
2839 case B43_BUS_BCMA:
0a64baea 2840 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
42c9a458
RM		 2841 break;
2842#endif
6cbab0d9
RM		 2843#ifdef CONFIG_B43_SSB
2844 case B43_BUS_SSB:
2845 gpiodev = b43_ssb_gpio_dev(dev);
2846 if (gpiodev)
2847 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2848 break;
2849#endif
2850 }
e4d6b795
MB		 2851}
2852
2853/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2854void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2855{
923fd703
MB		 2856 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2857 u16 fwstate;
2858
2859 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2860 B43_SHM_SH_UCODESTAT);
2861 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2862 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2863 b43err(dev->wl, "b43_mac_enable(): The firmware "
2864 "should be suspended, but current state is %u\n",
2865 fwstate);
2866 }
2867 }
2868
e4d6b795
MB		 2869 dev->mac_suspended--;
2870 B43_WARN_ON(dev->mac_suspended < 0);
2871 if (dev->mac_suspended == 0) {
5056635c 2872 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
e4d6b795
MB		 2873 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2874 B43_IRQ_MAC_SUSPENDED);
2875 /* Commit writes */
2876 b43_read32(dev, B43_MMIO_MACCTL);
2877 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2878 b43_power_saving_ctl_bits(dev, 0);
2879 }
2880}
2881
2882/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2883void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2884{
2885 int i;
2886 u32 tmp;
2887
05b64b36 2888 might_sleep();
e4d6b795 2889 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2890
e4d6b795
MB		 2891 if (dev->mac_suspended == 0) {
2892 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
5056635c 2893 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
e4d6b795
MB		 2894 /* force pci to flush the write */
2895 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2896 for (i = 35; i; i--) {
2897 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2898 if (tmp & B43_IRQ_MAC_SUSPENDED)
2899 goto out;
2900 udelay(10);
2901 }
2902 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2903 for (i = 40; i; i--) {
e4d6b795
MB		 2904 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2905 if (tmp & B43_IRQ_MAC_SUSPENDED)
2906 goto out;
05b64b36 2907 msleep(1);
e4d6b795
MB		 2908 }
2909 b43err(dev->wl, "MAC suspend failed\n");
2910 }
05b64b36 2911out:
e4d6b795
MB		 2912 dev->mac_suspended++;
2913}
2914
858a1652
RM		 2915/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2916void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2917{
6cbab0d9
RM		 2918 u32 tmp;
2919
2920 switch (dev->dev->bus_type) {
42c9a458
RM		 2921#ifdef CONFIG_B43_BCMA
2922 case B43_BUS_BCMA:
36677874 2923 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
42c9a458
RM		 2924 if (on)
2925 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2926 else
2927 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
36677874 2928 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
42c9a458
RM		 2929 break;
2930#endif
6cbab0d9
RM		 2931#ifdef CONFIG_B43_SSB
2932 case B43_BUS_SSB:
2933 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2934 if (on)
2935 tmp |= B43_TMSLOW_MACPHYCLKEN;
2936 else
2937 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2938 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2939 break;
2940#endif
2941 }
858a1652
RM		 2942}
2943
e4d6b795
MB		 2944static void b43_adjust_opmode(struct b43_wldev *dev)
2945{
2946 struct b43_wl *wl = dev->wl;
2947 u32 ctl;
2948 u16 cfp_pretbtt;
2949
2950 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2951 /* Reset status to STA infrastructure mode. */
2952 ctl &= ~B43_MACCTL_AP;
2953 ctl &= ~B43_MACCTL_KEEP_CTL;
2954 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2955 ctl &= ~B43_MACCTL_KEEP_BAD;
2956 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2957 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2958 ctl |= B43_MACCTL_INFRA;
2959
05c914fe
JB		 2960 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2961 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2962 ctl |= B43_MACCTL_AP;
05c914fe 2963 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2964 ctl &= ~B43_MACCTL_INFRA;
2965
2966 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2967 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2968 if (wl->filter_flags & FIF_FCSFAIL)
2969 ctl |= B43_MACCTL_KEEP_BAD;
2970 if (wl->filter_flags & FIF_PLCPFAIL)
2971 ctl |= B43_MACCTL_KEEP_BADPLCP;
2972 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2973 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2974 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2975 ctl |= B43_MACCTL_BEACPROMISC;
2976
e4d6b795
MB		 2977 /* Workaround: On old hardware the HW-MAC-address-filter
2978 * doesn't work properly, so always run promisc in filter
2979 * it in software. */
21d889d4 2980 if (dev->dev->core_rev <= 4)
e4d6b795
MB		 2981 ctl |= B43_MACCTL_PROMISC;
2982
2983 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2984
2985 cfp_pretbtt = 2;
2986 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
c244e08c
RM		 2987 if (dev->dev->chip_id == 0x4306 &&
2988 dev->dev->chip_rev == 3)
e4d6b795
MB		 2989 cfp_pretbtt = 100;
2990 else
2991 cfp_pretbtt = 50;
2992 }
2993 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2994
2995 /* FIXME: We don't currently implement the PMQ mechanism,
2996 * so always disable it. If we want to implement PMQ,
2997 * we need to enable it here (clear DISCPMQ) in AP mode.
2998 */
5056635c
RM		 2999 if (0 /* ctl & B43_MACCTL_AP */)
3000 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3001 else
3002 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
e4d6b795
MB		 3003}
3004
3005static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3006{
3007 u16 offset;
3008
3009 if (is_ofdm) {
3010 offset = 0x480;
3011 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3012 } else {
3013 offset = 0x4C0;
3014 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3015 }
3016 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3017 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3018}
3019
3020static void b43_rate_memory_init(struct b43_wldev *dev)
3021{
3022 switch (dev->phy.type) {
3023 case B43_PHYTYPE_A:
3024 case B43_PHYTYPE_G:
53a6e234 3025 case B43_PHYTYPE_N:
9d86a2d5 3026 case B43_PHYTYPE_LP:
6a461c23 3027 case B43_PHYTYPE_HT:
0b4ff45d 3028 case B43_PHYTYPE_LCN:
e4d6b795
MB		 3029 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3030 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3031 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3032 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3033 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3034 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3035 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3036 if (dev->phy.type == B43_PHYTYPE_A)
3037 break;
3038 /* fallthrough */
3039 case B43_PHYTYPE_B:
3040 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3041 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3042 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3043 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3044 break;
3045 default:
3046 B43_WARN_ON(1);
3047 }
3048}
3049
5042c507
MB		 3050/* Set the default values for the PHY TX Control Words. */
3051static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3052{
3053 u16 ctl = 0;
3054
3055 ctl |= B43_TXH_PHY_ENC_CCK;
3056 ctl |= B43_TXH_PHY_ANT01AUTO;
3057 ctl |= B43_TXH_PHY_TXPWR;
3058
3059 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3060 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3061 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3062}
3063
e4d6b795
MB		 3064/* Set the TX-Antenna for management frames sent by firmware. */
3065static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3066{
5042c507 3067 u16 ant;
e4d6b795
MB		 3068 u16 tmp;
3069
5042c507 3070 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 3071
e4d6b795
MB		 3072 /* For ACK/CTS */
3073 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 3074 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3075 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3076 /* For Probe Resposes */
3077 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 3078 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 3079 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3080}
3081
3082/* This is the opposite of b43_chip_init() */
3083static void b43_chip_exit(struct b43_wldev *dev)
3084{
fb11137a 3085 b43_phy_exit(dev);
e4d6b795
MB		 3086 b43_gpio_cleanup(dev);
3087 /* firmware is released later */
3088}
3089
3090/* Initialize the chip
3091 * http://bcm-specs.sipsolutions.net/ChipInit
3092 */
3093static int b43_chip_init(struct b43_wldev *dev)
3094{
3095 struct b43_phy *phy = &dev->phy;
ef1a628d 3096 int err;
858a1652 3097 u32 macctl;
e4d6b795
MB		 3098 u16 value16;
3099
1f7d87b0
MB		 3100 /* Initialize the MAC control */
3101 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3102 if (dev->phy.gmode)
3103 macctl |= B43_MACCTL_GMODE;
3104 macctl |= B43_MACCTL_INFRA;
3105 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795 3106
e4d6b795
MB		 3107 err = b43_upload_microcode(dev);
3108 if (err)
3109 goto out; /* firmware is released later */
3110
3111 err = b43_gpio_init(dev);
3112 if (err)
3113 goto out; /* firmware is released later */
21954c36 3114
e4d6b795
MB		 3115 err = b43_upload_initvals(dev);
3116 if (err)
1a8d1227 3117 goto err_gpio_clean;
e4d6b795 3118
0f68423f
RM		 3119 err = b43_upload_initvals_band(dev);
3120 if (err)
3121 goto err_gpio_clean;
3122
0b7dcd96
MB		 3123 /* Turn the Analog on and initialize the PHY. */
3124 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 3125 err = b43_phy_init(dev);
3126 if (err)
ef1a628d 3127 goto err_gpio_clean;
e4d6b795 3128
ef1a628d
MB		 3129 /* Disable Interference Mitigation. */
3130 if (phy->ops->interf_mitigation)
3131 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 3132
ef1a628d
MB		 3133 /* Select the antennae */
3134 if (phy->ops->set_rx_antenna)
3135 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 3136 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3137
3138 if (phy->type == B43_PHYTYPE_B) {
3139 value16 = b43_read16(dev, 0x005E);
3140 value16 |= 0x0004;
3141 b43_write16(dev, 0x005E, value16);
3142 }
3143 b43_write32(dev, 0x0100, 0x01000000);
21d889d4 3144 if (dev->dev->core_rev < 5)
e4d6b795
MB		 3145 b43_write32(dev, 0x010C, 0x01000000);
3146
5056635c
RM		 3147 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3148 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
e4d6b795 3149
e4d6b795
MB		 3150 /* Probe Response Timeout value */
3151 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
5c1da23b 3152 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
e4d6b795
MB		 3153
3154 /* Initially set the wireless operation mode. */
3155 b43_adjust_opmode(dev);
3156
21d889d4 3157 if (dev->dev->core_rev < 3) {
e4d6b795
MB		 3158 b43_write16(dev, 0x060E, 0x0000);
3159 b43_write16(dev, 0x0610, 0x8000);
3160 b43_write16(dev, 0x0604, 0x0000);
3161 b43_write16(dev, 0x0606, 0x0200);
3162 } else {
3163 b43_write32(dev, 0x0188, 0x80000000);
3164 b43_write32(dev, 0x018C, 0x02000000);
3165 }
3166 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
73b82bf0 3167 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
e4d6b795
MB		 3168 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3169 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3170 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3171 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3172 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3173
858a1652 3174 b43_mac_phy_clock_set(dev, true);
e4d6b795 3175
6cbab0d9 3176 switch (dev->dev->bus_type) {
42c9a458
RM		 3177#ifdef CONFIG_B43_BCMA
3178 case B43_BUS_BCMA:
3179 /* FIXME: 0xE74 is quite common, but should be read from CC */
3180 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3181 break;
3182#endif
6cbab0d9
RM		 3183#ifdef CONFIG_B43_SSB
3184 case B43_BUS_SSB:
3185 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3186 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3187 break;
3188#endif
3189 }
e4d6b795
MB		 3190
3191 err = 0;
3192 b43dbg(dev->wl, "Chip initialized\n");
21954c36 3193out:
e4d6b795
MB		 3194 return err;
3195
1a8d1227 3196err_gpio_clean:
e4d6b795 3197 b43_gpio_cleanup(dev);
21954c36 3198 return err;
e4d6b795
MB		 3199}
3200
e4d6b795
MB		 3201static void b43_periodic_every60sec(struct b43_wldev *dev)
3202{
ef1a628d 3203 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 3204
ef1a628d
MB		 3205 if (ops->pwork_60sec)
3206 ops->pwork_60sec(dev);
18c8adeb
MB		 3207
3208 /* Force check the TX power emission now. */
3209 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 3210}
3211
3212static void b43_periodic_every30sec(struct b43_wldev *dev)
3213{
3214 /* Update device statistics. */
3215 b43_calculate_link_quality(dev);
3216}
3217
3218static void b43_periodic_every15sec(struct b43_wldev *dev)
3219{
3220 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 3221 u16 wdr;
3222
3223 if (dev->fw.opensource) {
3224 /* Check if the firmware is still alive.
3225 * It will reset the watchdog counter to 0 in its idle loop. */
3226 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3227 if (unlikely(wdr)) {
3228 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3229 b43_controller_restart(dev, "Firmware watchdog");
3230 return;
3231 } else {
3232 b43_shm_write16(dev, B43_SHM_SCRATCH,
3233 B43_WATCHDOG_REG, 1);
3234 }
3235 }
e4d6b795 3236
ef1a628d
MB		 3237 if (phy->ops->pwork_15sec)
3238 phy->ops->pwork_15sec(dev);
3239
00e0b8cb
SB		 3240 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3241 wmb();
990b86f4
MB		 3242
3243#if B43_DEBUG
3244 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3245 unsigned int i;
3246
3247 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3248 dev->irq_count / 15,
3249 dev->tx_count / 15,
3250 dev->rx_count / 15);
3251 dev->irq_count = 0;
3252 dev->tx_count = 0;
3253 dev->rx_count = 0;
3254 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3255 if (dev->irq_bit_count[i]) {
3256 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3257 dev->irq_bit_count[i] / 15, i, (1 << i));
3258 dev->irq_bit_count[i] = 0;
3259 }
3260 }
3261 }
3262#endif
e4d6b795
MB		 3263}
3264
e4d6b795
MB		 3265static void do_periodic_work(struct b43_wldev *dev)
3266{
3267 unsigned int state;
3268
3269 state = dev->periodic_state;
42bb4cd5 3270 if (state % 4 == 0)
e4d6b795 3271 b43_periodic_every60sec(dev);
42bb4cd5 3272 if (state % 2 == 0)
e4d6b795 3273 b43_periodic_every30sec(dev);
42bb4cd5 3274 b43_periodic_every15sec(dev);
e4d6b795
MB		 3275}
3276
05b64b36
MB		 3277/* Periodic work locking policy:
3278 * The whole periodic work handler is protected by
3279 * wl->mutex. If another lock is needed somewhere in the
21ae2956 3280 * pwork callchain, it's acquired in-place, where it's needed.
e4d6b795 3281 */
e4d6b795
MB		 3282static void b43_periodic_work_handler(struct work_struct *work)
3283{
05b64b36
MB		 3284 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3285 periodic_work.work);
3286 struct b43_wl *wl = dev->wl;
3287 unsigned long delay;
e4d6b795 3288
05b64b36 3289 mutex_lock(&wl->mutex);
e4d6b795
MB		 3290
3291 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3292 goto out;
3293 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3294 goto out_requeue;
3295
05b64b36 3296 do_periodic_work(dev);
e4d6b795 3297
e4d6b795 3298 dev->periodic_state++;
42bb4cd5 3299out_requeue:
e4d6b795
MB		 3300 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3301 delay = msecs_to_jiffies(50);
3302 else
82cd682d 3303 delay = round_jiffies_relative(HZ * 15);
42935eca 3304 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3305out:
05b64b36 3306 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3307}
3308
3309static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3310{
3311 struct delayed_work *work = &dev->periodic_work;
3312
3313 dev->periodic_state = 0;
3314 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3315 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3316}
3317
f3dd3fcc 3318/* Check if communication with the device works correctly. */
e4d6b795
MB		 3319static int b43_validate_chipaccess(struct b43_wldev *dev)
3320{
f62ae6cd 3321 u32 v, backup0, backup4;
e4d6b795 3322
f62ae6cd
MB		 3323 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3324 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3325
3326 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3327 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3328 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3329 goto error;
f3dd3fcc
MB		 3330 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3331 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3332 goto error;
3333
f62ae6cd
MB		 3334 /* Check if unaligned 32bit SHM_SHARED access works properly.
3335 * However, don't bail out on failure, because it's noncritical. */
3336 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3337 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3338 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3339 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3340 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3341 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3342 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3343 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3344 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3345 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3346 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3347 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3348
3349 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3350 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc 3351
21d889d4 3352 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
f3dd3fcc
MB		 3353 /* The 32bit register shadows the two 16bit registers
3354 * with update sideeffects. Validate this. */
3355 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3356 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3357 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3358 goto error;
3359 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3360 goto error;
3361 }
3362 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3363
3364 v = b43_read32(dev, B43_MMIO_MACCTL);
3365 v |= B43_MACCTL_GMODE;
3366 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3367 goto error;
3368
3369 return 0;
f3dd3fcc 3370error:
e4d6b795
MB		 3371 b43err(dev->wl, "Failed to validate the chipaccess\n");
3372 return -ENODEV;
3373}
3374
3375static void b43_security_init(struct b43_wldev *dev)
3376{
e4d6b795
MB		 3377 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3378 /* KTP is a word address, but we address SHM bytewise.
3379 * So multiply by two.
3380 */
3381 dev->ktp *= 2;
66d2d089
MB		 3382 /* Number of RCMTA address slots */
3383 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3384 /* Clear the key memory. */
e4d6b795
MB		 3385 b43_clear_keys(dev);
3386}
3387
616de35d 3388#ifdef CONFIG_B43_HWRNG
99da185a 3389static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3390{
3391 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3392 struct b43_wldev *dev;
3393 int count = -ENODEV;
e4d6b795 3394
a78b3bb2
MB		 3395 mutex_lock(&wl->mutex);
3396 dev = wl->current_dev;
3397 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3398 *data = b43_read16(dev, B43_MMIO_RNG);
3399 count = sizeof(u16);
3400 }
3401 mutex_unlock(&wl->mutex);
e4d6b795 3402
a78b3bb2 3403 return count;
e4d6b795 3404}
616de35d 3405#endif /* CONFIG_B43_HWRNG */
e4d6b795 3406
b844eba2 3407static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3408{
616de35d 3409#ifdef CONFIG_B43_HWRNG
e4d6b795 3410 if (wl->rng_initialized)
b844eba2 3411 hwrng_unregister(&wl->rng);
616de35d 3412#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3413}
3414
3415static int b43_rng_init(struct b43_wl *wl)
3416{
616de35d 3417 int err = 0;
e4d6b795 3418
616de35d 3419#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3420 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3421 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3422 wl->rng.name = wl->rng_name;
3423 wl->rng.data_read = b43_rng_read;
3424 wl->rng.priv = (unsigned long)wl;
3db1cd5c 3425 wl->rng_initialized = true;
e4d6b795
MB		 3426 err = hwrng_register(&wl->rng);
3427 if (err) {
3db1cd5c 3428 wl->rng_initialized = false;
e4d6b795
MB		 3429 b43err(wl, "Failed to register the random "
3430 "number generator (%d)\n", err);
3431 }
616de35d 3432#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3433
3434 return err;
3435}
3436
f5d40eed 3437static void b43_tx_work(struct work_struct *work)
e4d6b795 3438{
f5d40eed
MB		 3439 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3440 struct b43_wldev *dev;
3441 struct sk_buff *skb;
bad69194 3442 int queue_num;
f5d40eed 3443 int err = 0;
e4d6b795 3444
f5d40eed
MB		 3445 mutex_lock(&wl->mutex);
3446 dev = wl->current_dev;
3447 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3448 mutex_unlock(&wl->mutex);
3449 return;
5100d5ac 3450 }
21a75d77 3451
bad69194 3452 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3453 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3454 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3455 if (b43_using_pio_transfers(dev))
3456 err = b43_pio_tx(dev, skb);
3457 else
3458 err = b43_dma_tx(dev, skb);
3459 if (err == -ENOSPC) {
3460 wl->tx_queue_stopped[queue_num] = 1;
3461 ieee80211_stop_queue(wl->hw, queue_num);
3462 skb_queue_head(&wl->tx_queue[queue_num], skb);
3463 break;
3464 }
3465 if (unlikely(err))
78f18df4 3466 ieee80211_free_txskb(wl->hw, skb);
bad69194 3467 err = 0;
3468 }
21a75d77 3469
bad69194 3470 if (!err)
3471 wl->tx_queue_stopped[queue_num] = 0;
21a75d77
MB		 3472 }
3473
990b86f4
MB		 3474#if B43_DEBUG
3475 dev->tx_count++;
3476#endif
f5d40eed
MB		 3477 mutex_unlock(&wl->mutex);
3478}
21a75d77 3479
7bb45683 3480static void b43_op_tx(struct ieee80211_hw *hw,
36323f81
TH		 3481 struct ieee80211_tx_control *control,
3482 struct sk_buff *skb)
f5d40eed
MB		 3483{
3484 struct b43_wl *wl = hw_to_b43_wl(hw);
3485
3486 if (unlikely(skb->len < 2 + 2 + 6)) {
3487 /* Too short, this can't be a valid frame. */
78f18df4 3488 ieee80211_free_txskb(hw, skb);
7bb45683 3489 return;
f5d40eed
MB		 3490 }
3491 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3492
bad69194 3493 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3494 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3495 ieee80211_queue_work(wl->hw, &wl->tx_work);
3496 } else {
3497 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3498 }
e4d6b795
MB		 3499}
3500
e6f5b934
MB		 3501static void b43_qos_params_upload(struct b43_wldev *dev,
3502 const struct ieee80211_tx_queue_params *p,
3503 u16 shm_offset)
3504{
3505 u16 params[B43_NR_QOSPARAMS];
0b57664c 3506 int bslots, tmp;
e6f5b934
MB		 3507 unsigned int i;
3508
b0544eb6
MB		 3509 if (!dev->qos_enabled)
3510 return;
3511
0b57664c 3512 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3513
3514 memset(&params, 0, sizeof(params));
3515
3516 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3517 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3518 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3519 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3520 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3521 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3522 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3523
3524 for (i = 0; i < ARRAY_SIZE(params); i++) {
3525 if (i == B43_QOSPARAM_STATUS) {
3526 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3527 shm_offset + (i * 2));
3528 /* Mark the parameters as updated. */
3529 tmp |= 0x100;
3530 b43_shm_write16(dev, B43_SHM_SHARED,
3531 shm_offset + (i * 2),
3532 tmp);
3533 } else {
3534 b43_shm_write16(dev, B43_SHM_SHARED,
3535 shm_offset + (i * 2),
3536 params[i]);
3537 }
3538 }
3539}
3540
c40c1129
MB		 3541/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3542static const u16 b43_qos_shm_offsets[] = {
3543 /* [mac80211-queue-nr] = SHM_OFFSET, */
3544 [0] = B43_QOS_VOICE,
3545 [1] = B43_QOS_VIDEO,
3546 [2] = B43_QOS_BESTEFFORT,
3547 [3] = B43_QOS_BACKGROUND,
3548};
3549
5a5f3b40
MB		 3550/* Update all QOS parameters in hardware. */
3551static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3552{
3553 struct b43_wl *wl = dev->wl;
3554 struct b43_qos_params *params;
e6f5b934
MB		 3555 unsigned int i;
3556
b0544eb6
MB		 3557 if (!dev->qos_enabled)
3558 return;
3559
c40c1129
MB		 3560 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3561 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3562
3563 b43_mac_suspend(dev);
e6f5b934
MB		 3564 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3565 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3566 b43_qos_params_upload(dev, &(params->p),
3567 b43_qos_shm_offsets[i]);
e6f5b934 3568 }
e6f5b934
MB		 3569 b43_mac_enable(dev);
3570}
3571
3572static void b43_qos_clear(struct b43_wl *wl)
3573{
3574 struct b43_qos_params *params;
3575 unsigned int i;
3576
c40c1129
MB		 3577 /* Initialize QoS parameters to sane defaults. */
3578
3579 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3580 ARRAY_SIZE(wl->qos_params));
3581
e6f5b934
MB		 3582 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3583 params = &(wl->qos_params[i]);
3584
c40c1129
MB		 3585 switch (b43_qos_shm_offsets[i]) {
3586 case B43_QOS_VOICE:
3587 params->p.txop = 0;
3588 params->p.aifs = 2;
3589 params->p.cw_min = 0x0001;
3590 params->p.cw_max = 0x0001;
3591 break;
3592 case B43_QOS_VIDEO:
3593 params->p.txop = 0;
3594 params->p.aifs = 2;
3595 params->p.cw_min = 0x0001;
3596 params->p.cw_max = 0x0001;
3597 break;
3598 case B43_QOS_BESTEFFORT:
3599 params->p.txop = 0;
3600 params->p.aifs = 3;
3601 params->p.cw_min = 0x0001;
3602 params->p.cw_max = 0x03FF;
3603 break;
3604 case B43_QOS_BACKGROUND:
3605 params->p.txop = 0;
3606 params->p.aifs = 7;
3607 params->p.cw_min = 0x0001;
3608 params->p.cw_max = 0x03FF;
3609 break;
3610 default:
3611 B43_WARN_ON(1);
3612 }
e6f5b934
MB		 3613 }
3614}
3615
3616/* Initialize the core's QOS capabilities */
3617static void b43_qos_init(struct b43_wldev *dev)
3618{
b0544eb6
MB		 3619 if (!dev->qos_enabled) {
3620 /* Disable QOS support. */
3621 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3622 b43_write16(dev, B43_MMIO_IFSCTL,
3623 b43_read16(dev, B43_MMIO_IFSCTL)
3624 & ~B43_MMIO_IFSCTL_USE_EDCF);
3625 b43dbg(dev->wl, "QoS disabled\n");
3626 return;
3627 }
3628
e6f5b934 3629 /* Upload the current QOS parameters. */
5a5f3b40 3630 b43_qos_upload_all(dev);
e6f5b934
MB		 3631
3632 /* Enable QOS support. */
3633 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3634 b43_write16(dev, B43_MMIO_IFSCTL,
3635 b43_read16(dev, B43_MMIO_IFSCTL)
3636 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3637 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3638}
3639
8a3a3c85
EP		 3640static int b43_op_conf_tx(struct ieee80211_hw *hw,
3641 struct ieee80211_vif *vif, u16 _queue,
40faacc4 3642 const struct ieee80211_tx_queue_params *params)
e4d6b795 3643{
e6f5b934 3644 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3645 struct b43_wldev *dev;
e6f5b934 3646 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3647 int err = -ENODEV;
e6f5b934
MB		 3648
3649 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3650 /* Queue not available or don't support setting
3651 * params on this queue. Return success to not
3652 * confuse mac80211. */
3653 return 0;
3654 }
5a5f3b40
MB		 3655 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3656 ARRAY_SIZE(wl->qos_params));
e6f5b934 3657
5a5f3b40
MB		 3658 mutex_lock(&wl->mutex);
3659 dev = wl->current_dev;
3660 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3661 goto out_unlock;
e6f5b934 3662
5a5f3b40
MB		 3663 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3664 b43_mac_suspend(dev);
3665 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3666 b43_qos_shm_offsets[queue]);
3667 b43_mac_enable(dev);
3668 err = 0;
e6f5b934 3669
5a5f3b40
MB		 3670out_unlock:
3671 mutex_unlock(&wl->mutex);
3672
3673 return err;
e4d6b795
MB		 3674}
3675
40faacc4
MB		 3676static int b43_op_get_stats(struct ieee80211_hw *hw,
3677 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3678{
3679 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3680
36dbd954 3681 mutex_lock(&wl->mutex);
e4d6b795 3682 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3683 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3684
3685 return 0;
3686}
3687
37a41b4a 3688static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
08e87a83
AF		 3689{
3690 struct b43_wl *wl = hw_to_b43_wl(hw);
3691 struct b43_wldev *dev;
3692 u64 tsf;
3693
3694 mutex_lock(&wl->mutex);
08e87a83
AF		 3695 dev = wl->current_dev;
3696
3697 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3698 b43_tsf_read(dev, &tsf);
3699 else
3700 tsf = 0;
3701
08e87a83
AF		 3702 mutex_unlock(&wl->mutex);
3703
3704 return tsf;
3705}
3706
37a41b4a
EP		 3707static void b43_op_set_tsf(struct ieee80211_hw *hw,
3708 struct ieee80211_vif *vif, u64 tsf)
08e87a83
AF		 3709{
3710 struct b43_wl *wl = hw_to_b43_wl(hw);
3711 struct b43_wldev *dev;
3712
3713 mutex_lock(&wl->mutex);
08e87a83
AF		 3714 dev = wl->current_dev;
3715
3716 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3717 b43_tsf_write(dev, tsf);
3718
08e87a83
AF		 3719 mutex_unlock(&wl->mutex);
3720}
3721
99da185a 3722static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3723{
3724 switch (band) {
3725 case IEEE80211_BAND_5GHZ:
3726 return "5";
3727 case IEEE80211_BAND_2GHZ:
3728 return "2.4";
3729 default:
3730 break;
3731 }
3732 B43_WARN_ON(1);
3733 return "";
3734}
3735
e4d6b795 3736/* Expects wl->mutex locked */
7a8af8cf
RM		 3737static int b43_switch_band(struct b43_wldev *dev,
3738 struct ieee80211_channel *chan)
e4d6b795 3739{
7a8af8cf
RM		 3740 struct b43_phy *phy = &dev->phy;
3741 bool gmode;
3742 u32 tmp;
e4d6b795 3743
644aa4d6
RM		 3744 switch (chan->band) {
3745 case IEEE80211_BAND_5GHZ:
7a8af8cf 3746 gmode = false;
644aa4d6
RM		 3747 break;
3748 case IEEE80211_BAND_2GHZ:
7a8af8cf 3749 gmode = true;
644aa4d6
RM		 3750 break;
3751 default:
3752 B43_WARN_ON(1);
3753 return -EINVAL;
bb1eeff1 3754 }
644aa4d6 3755
7a8af8cf
RM		 3756 if (!((gmode && phy->supports_2ghz) ||
3757 (!gmode && phy->supports_5ghz))) {
3758 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
bb1eeff1
MB		 3759 band_to_string(chan->band));
3760 return -ENODEV;
e4d6b795 3761 }
7a8af8cf
RM		 3762
3763 if (!!phy->gmode == !!gmode) {
e4d6b795
MB		 3764 /* This device is already running. */
3765 return 0;
3766 }
7a8af8cf
RM		 3767
3768 b43dbg(dev->wl, "Switching to %s GHz band\n",
bb1eeff1 3769 band_to_string(chan->band));
7a8af8cf 3770
6fe55143
RM		 3771 /* Some new devices don't need disabling radio for band switching */
3772 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3773 b43_software_rfkill(dev, true);
7a8af8cf
RM		 3774
3775 phy->gmode = gmode;
3776 b43_phy_put_into_reset(dev);
3777 switch (dev->dev->bus_type) {
3778#ifdef CONFIG_B43_BCMA
3779 case B43_BUS_BCMA:
3780 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3781 if (gmode)
3782 tmp |= B43_BCMA_IOCTL_GMODE;
3783 else
3784 tmp &= ~B43_BCMA_IOCTL_GMODE;
3785 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3786 break;
3787#endif
3788#ifdef CONFIG_B43_SSB
3789 case B43_BUS_SSB:
3790 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3791 if (gmode)
3792 tmp |= B43_TMSLOW_GMODE;
3793 else
3794 tmp &= ~B43_TMSLOW_GMODE;
3795 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3796 break;
3797#endif
e4d6b795 3798 }
7a8af8cf 3799 b43_phy_take_out_of_reset(dev);
e4d6b795 3800
7a8af8cf
RM		 3801 b43_upload_initvals_band(dev);
3802
3803 b43_phy_init(dev);
e4d6b795
MB		 3804
3805 return 0;
e4d6b795
MB		 3806}
3807
9124b077
JB		 3808/* Write the short and long frame retry limit values. */
3809static void b43_set_retry_limits(struct b43_wldev *dev,
3810 unsigned int short_retry,
3811 unsigned int long_retry)
3812{
3813 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3814 * the chip-internal counter. */
3815 short_retry = min(short_retry, (unsigned int)0xF);
3816 long_retry = min(long_retry, (unsigned int)0xF);
3817
3818 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3819 short_retry);
3820 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3821 long_retry);
3822}
3823
e8975581 3824static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3825{
3826 struct b43_wl *wl = hw_to_b43_wl(hw);
53256511
RM		 3827 struct b43_wldev *dev = wl->current_dev;
3828 struct b43_phy *phy = &dev->phy;
e8975581 3829 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3830 int antenna;
e4d6b795 3831 int err = 0;
e4d6b795 3832
e4d6b795 3833 mutex_lock(&wl->mutex);
7a8af8cf
RM		 3834 b43_mac_suspend(dev);
3835
8c79e5ee 3836 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ea42e71c 3837 phy->chandef = &conf->chandef;
f9471e99 3838 phy->channel = conf->chandef.chan->hw_value;
2a190322 3839
8c79e5ee
RM		 3840 /* Switch the band (if necessary). */
3841 err = b43_switch_band(dev, conf->chandef.chan);
3842 if (err)
3843 goto out_mac_enable;
3844
3845 /* Switch to the requested channel.
3846 * The firmware takes care of races with the TX handler.
3847 */
f9471e99 3848 b43_switch_channel(dev, phy->channel);
8c79e5ee 3849 }
aa4c7b2a 3850
9124b077
JB		 3851 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3852 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3853 conf->long_frame_max_tx_count);
3854 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3855 if (!changed)
d10d0e57 3856 goto out_mac_enable;
e4d6b795 3857
0869aea0 3858 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3859
e4d6b795
MB		 3860 /* Adjust the desired TX power level. */
3861 if (conf->power_level != 0) {
18c8adeb
MB		 3862 if (conf->power_level != phy->desired_txpower) {
3863 phy->desired_txpower = conf->power_level;
3864 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3865 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3866 }
3867 }
3868
3869 /* Antennas for RX and management frame TX. */
0f4ac38b 3870 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3871 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3872 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3873 if (phy->ops->set_rx_antenna)
3874 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3875
fd4973c5
LF		 3876 if (wl->radio_enabled != phy->radio_on) {
3877 if (wl->radio_enabled) {
19d337df 3878 b43_software_rfkill(dev, false);
fda9abcf
MB		 3879 b43info(dev->wl, "Radio turned on by software\n");
3880 if (!dev->radio_hw_enable) {
3881 b43info(dev->wl, "The hardware RF-kill button "
3882 "still turns the radio physically off. "
3883 "Press the button to turn it on.\n");
3884 }
3885 } else {
19d337df 3886 b43_software_rfkill(dev, true);
fda9abcf
MB		 3887 b43info(dev->wl, "Radio turned off by software\n");
3888 }
3889 }
3890
d10d0e57
MB		 3891out_mac_enable:
3892 b43_mac_enable(dev);
e4d6b795
MB		 3893 mutex_unlock(&wl->mutex);
3894
3895 return err;
3896}
3897
881d948c 3898static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3899{
3900 struct ieee80211_supported_band *sband =
3901 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3902 struct ieee80211_rate *rate;
3903 int i;
3904 u16 basic, direct, offset, basic_offset, rateptr;
3905
3906 for (i = 0; i < sband->n_bitrates; i++) {
3907 rate = &sband->bitrates[i];
3908
3909 if (b43_is_cck_rate(rate->hw_value)) {
3910 direct = B43_SHM_SH_CCKDIRECT;
3911 basic = B43_SHM_SH_CCKBASIC;
3912 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3913 offset &= 0xF;
3914 } else {
3915 direct = B43_SHM_SH_OFDMDIRECT;
3916 basic = B43_SHM_SH_OFDMBASIC;
3917 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3918 offset &= 0xF;
3919 }
3920
3921 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3922
3923 if (b43_is_cck_rate(rate->hw_value)) {
3924 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3925 basic_offset &= 0xF;
3926 } else {
3927 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3928 basic_offset &= 0xF;
3929 }
3930
3931 /*
3932 * Get the pointer that we need to point to
3933 * from the direct map
3934 */
3935 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3936 direct + 2 * basic_offset);
3937 /* and write it to the basic map */
3938 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3939 rateptr);
3940 }
3941}
3942
3943static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3944 struct ieee80211_vif *vif,
3945 struct ieee80211_bss_conf *conf,
3946 u32 changed)
3947{
3948 struct b43_wl *wl = hw_to_b43_wl(hw);
3949 struct b43_wldev *dev;
c7ab5ef9
JB		 3950
3951 mutex_lock(&wl->mutex);
3952
3953 dev = wl->current_dev;
d10d0e57 3954 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3955 goto out_unlock_mutex;
2d0ddec5
JB		 3956
3957 B43_WARN_ON(wl->vif != vif);
3958
3959 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3960 if (conf->bssid)
3961 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3962 else
3963 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3964 }
2d0ddec5 3965
3f0d843b
JB		 3966 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3967 if (changed & BSS_CHANGED_BEACON &&
3968 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3969 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3970 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3971 b43_update_templates(wl);
3972
3973 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3974 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3975 }
3976
c7ab5ef9
JB		 3977 b43_mac_suspend(dev);
3978
57c4d7b4
JB		 3979 /* Update templates for AP/mesh mode. */
3980 if (changed & BSS_CHANGED_BEACON_INT &&
3981 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3982 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
2a190322
FF		 3983 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3984 conf->beacon_int)
57c4d7b4
JB		 3985 b43_set_beacon_int(dev, conf->beacon_int);
3986
c7ab5ef9
JB		 3987 if (changed & BSS_CHANGED_BASIC_RATES)
3988 b43_update_basic_rates(dev, conf->basic_rates);
3989
3990 if (changed & BSS_CHANGED_ERP_SLOT) {
3991 if (conf->use_short_slot)
3992 b43_short_slot_timing_enable(dev);
3993 else
3994 b43_short_slot_timing_disable(dev);
3995 }
3996
3997 b43_mac_enable(dev);
d10d0e57 3998out_unlock_mutex:
c7ab5ef9 3999 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 4000}
4001
40faacc4 4002static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 4003 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4004 struct ieee80211_key_conf *key)
e4d6b795
MB		 4005{
4006 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 4007 struct b43_wldev *dev;
e4d6b795
MB		 4008 u8 algorithm;
4009 u8 index;
c6dfc9a8 4010 int err;
060210f9 4011 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 4012
4013 if (modparam_nohwcrypt)
4014 return -ENOSPC; /* User disabled HW-crypto */
4015
78f9c850
AQ		 4016 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4017 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4018 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4019 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4020 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4021 /*
4022 * For now, disable hw crypto for the RSN IBSS group keys. This
4023 * could be optimized in the future, but until that gets
4024 * implemented, use of software crypto for group addressed
4025 * frames is a acceptable to allow RSN IBSS to be used.
4026 */
4027 return -EOPNOTSUPP;
4028 }
4029
c6dfc9a8 4030 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 4031
4032 dev = wl->current_dev;
4033 err = -ENODEV;
4034 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4035 goto out_unlock;
4036
403a3a13 4037 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 4038 /* We don't have firmware for the crypto engine.
4039 * Must use software-crypto. */
4040 err = -EOPNOTSUPP;
4041 goto out_unlock;
4042 }
4043
c6dfc9a8 4044 err = -EINVAL;
97359d12
JB		 4045 switch (key->cipher) {
4046 case WLAN_CIPHER_SUITE_WEP40:
4047 algorithm = B43_SEC_ALGO_WEP40;
4048 break;
4049 case WLAN_CIPHER_SUITE_WEP104:
4050 algorithm = B43_SEC_ALGO_WEP104;
e4d6b795 4051 break;
97359d12 4052 case WLAN_CIPHER_SUITE_TKIP:
e4d6b795
MB		 4053 algorithm = B43_SEC_ALGO_TKIP;
4054 break;
97359d12 4055 case WLAN_CIPHER_SUITE_CCMP:
e4d6b795
MB		 4056 algorithm = B43_SEC_ALGO_AES;
4057 break;
4058 default:
4059 B43_WARN_ON(1);
c6dfc9a8 4060 goto out_unlock;
e4d6b795 4061 }
e4d6b795
MB		 4062 index = (u8) (key->keyidx);
4063 if (index > 3)
e4d6b795 4064 goto out_unlock;
e4d6b795
MB		 4065
4066 switch (cmd) {
4067 case SET_KEY:
035d0243 4068 if (algorithm == B43_SEC_ALGO_TKIP &&
4069 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4070 !modparam_hwtkip)) {
4071 /* We support only pairwise key */
e4d6b795
MB		 4072 err = -EOPNOTSUPP;
4073 goto out_unlock;
4074 }
4075
e808e586 4076 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 4077 if (WARN_ON(!sta)) {
4078 err = -EOPNOTSUPP;
4079 goto out_unlock;
4080 }
e808e586 4081 /* Pairwise key with an assigned MAC address. */
e4d6b795 4082 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 4083 key->key, key->keylen,
4084 sta->addr, key);
e808e586
MB		 4085 } else {
4086 /* Group key */
4087 err = b43_key_write(dev, index, algorithm,
4088 key->key, key->keylen, NULL, key);
e4d6b795
MB		 4089 }
4090 if (err)
4091 goto out_unlock;
4092
4093 if (algorithm == B43_SEC_ALGO_WEP40 ||
4094 algorithm == B43_SEC_ALGO_WEP104) {
4095 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4096 } else {
4097 b43_hf_write(dev,
4098 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4099 }
4100 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 4101 if (algorithm == B43_SEC_ALGO_TKIP)
4102 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 4103 break;
4104 case DISABLE_KEY: {
4105 err = b43_key_clear(dev, key->hw_key_idx);
4106 if (err)
4107 goto out_unlock;
4108 break;
4109 }
4110 default:
4111 B43_WARN_ON(1);
4112 }
9cf7f247 4113
e4d6b795 4114out_unlock:
e4d6b795
MB		 4115 if (!err) {
4116 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 4117 "mac: %pM\n",
e4d6b795 4118 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 4119 sta ? sta->addr : bcast_addr);
9cf7f247 4120 b43_dump_keymemory(dev);
e4d6b795 4121 }
9cf7f247
MB		 4122 mutex_unlock(&wl->mutex);
4123
e4d6b795
MB		 4124 return err;
4125}
4126
40faacc4
MB		 4127static void b43_op_configure_filter(struct ieee80211_hw *hw,
4128 unsigned int changed, unsigned int *fflags,
3ac64bee 4129 u64 multicast)
e4d6b795
MB		 4130{
4131 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 4132 struct b43_wldev *dev;
e4d6b795 4133
36dbd954
MB		 4134 mutex_lock(&wl->mutex);
4135 dev = wl->current_dev;
4150c572
JB		 4136 if (!dev) {
4137 *fflags = 0;
36dbd954 4138 goto out_unlock;
e4d6b795 4139 }
4150c572 4140
4150c572
JB		 4141 *fflags &= FIF_PROMISC_IN_BSS |
4142 FIF_ALLMULTI |
4143 FIF_FCSFAIL |
4144 FIF_PLCPFAIL |
4145 FIF_CONTROL |
4146 FIF_OTHER_BSS |
4147 FIF_BCN_PRBRESP_PROMISC;
4148
4149 changed &= FIF_PROMISC_IN_BSS |
4150 FIF_ALLMULTI |
4151 FIF_FCSFAIL |
4152 FIF_PLCPFAIL |
4153 FIF_CONTROL |
4154 FIF_OTHER_BSS |
4155 FIF_BCN_PRBRESP_PROMISC;
4156
4157 wl->filter_flags = *fflags;
4158
4159 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4160 b43_adjust_opmode(dev);
36dbd954
MB		 4161
4162out_unlock:
4163 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4164}
4165
36dbd954
MB		 4166/* Locking: wl->mutex
4167 * Returns the current dev. This might be different from the passed in dev,
4168 * because the core might be gone away while we unlocked the mutex. */
4169static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795 4170{
9a53bf54 4171 struct b43_wl *wl;
36dbd954 4172 struct b43_wldev *orig_dev;
49d965c8 4173 u32 mask;
bad69194 4174 int queue_num;
e4d6b795 4175
9a53bf54
LF		 4176 if (!dev)
4177 return NULL;
4178 wl = dev->wl;
36dbd954
MB		 4179redo:
4180 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4181 return dev;
a19d12d7 4182
f5d40eed 4183 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 4184 mutex_unlock(&wl->mutex);
4185 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 4186 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 4187 mutex_lock(&wl->mutex);
4188 dev = wl->current_dev;
4189 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4190 /* Whoops, aliens ate up the device while we were unlocked. */
4191 return dev;
4192 }
a19d12d7 4193
36dbd954 4194 /* Disable interrupts on the device. */
e4d6b795 4195 b43_set_status(dev, B43_STAT_INITIALIZED);
505fb019 4196 if (b43_bus_host_is_sdio(dev->dev)) {
36dbd954
MB		 4197 /* wl->mutex is locked. That is enough. */
4198 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4199 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4200 } else {
4201 spin_lock_irq(&wl->hardirq_lock);
4202 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4203 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4204 spin_unlock_irq(&wl->hardirq_lock);
4205 }
176e9f6a 4206 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 4207 orig_dev = dev;
e4d6b795 4208 mutex_unlock(&wl->mutex);
505fb019 4209 if (b43_bus_host_is_sdio(dev->dev)) {
176e9f6a
MB		 4210 b43_sdio_free_irq(dev);
4211 } else {
a18c715e
RM		 4212 synchronize_irq(dev->dev->irq);
4213 free_irq(dev->dev->irq, dev);
176e9f6a 4214 }
e4d6b795 4215 mutex_lock(&wl->mutex);
36dbd954
MB		 4216 dev = wl->current_dev;
4217 if (!dev)
4218 return dev;
4219 if (dev != orig_dev) {
4220 if (b43_status(dev) >= B43_STAT_STARTED)
4221 goto redo;
4222 return dev;
4223 }
49d965c8
MB		 4224 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4225 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 4226
bad69194 4227 /* Drain all TX queues. */
4228 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
78f18df4
FF		 4229 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4230 struct sk_buff *skb;
4231
4232 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4233 ieee80211_free_txskb(wl->hw, skb);
4234 }
bad69194 4235 }
f5d40eed 4236
e4d6b795 4237 b43_mac_suspend(dev);
a78b3bb2 4238 b43_leds_exit(dev);
e4d6b795 4239 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 4240
4241 return dev;
e4d6b795
MB		 4242}
4243
4244/* Locking: wl->mutex */
4245static int b43_wireless_core_start(struct b43_wldev *dev)
4246{
4247 int err;
4248
4249 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4250
4251 drain_txstatus_queue(dev);
505fb019 4252 if (b43_bus_host_is_sdio(dev->dev)) {
3dbba8e2
AH		 4253 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4254 if (err) {
4255 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4256 goto out;
4257 }
4258 } else {
a18c715e 4259 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3dbba8e2
AH		 4260 b43_interrupt_thread_handler,
4261 IRQF_SHARED, KBUILD_MODNAME, dev);
4262 if (err) {
dedb1eb9 4263 b43err(dev->wl, "Cannot request IRQ-%d\n",
a18c715e 4264 dev->dev->irq);
3dbba8e2
AH		 4265 goto out;
4266 }
e4d6b795
MB		 4267 }
4268
4269 /* We are ready to run. */
0866b03c 4270 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4271 b43_set_status(dev, B43_STAT_STARTED);
4272
4273 /* Start data flow (TX/RX). */
4274 b43_mac_enable(dev);
13790728 4275 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795 4276
25985edc 4277 /* Start maintenance work */
e4d6b795
MB		 4278 b43_periodic_tasks_setup(dev);
4279
a78b3bb2
MB		 4280 b43_leds_init(dev);
4281
e4d6b795 4282 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4283out:
e4d6b795
MB		 4284 return err;
4285}
4286
2fdf8c54
RM		 4287static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4288{
4289 switch (phy_type) {
4290 case B43_PHYTYPE_A:
4291 return "A";
4292 case B43_PHYTYPE_B:
4293 return "B";
4294 case B43_PHYTYPE_G:
4295 return "G";
4296 case B43_PHYTYPE_N:
4297 return "N";
4298 case B43_PHYTYPE_LP:
4299 return "LP";
4300 case B43_PHYTYPE_SSLPN:
4301 return "SSLPN";
4302 case B43_PHYTYPE_HT:
4303 return "HT";
4304 case B43_PHYTYPE_LCN:
4305 return "LCN";
4306 case B43_PHYTYPE_LCNXN:
4307 return "LCNXN";
4308 case B43_PHYTYPE_LCN40:
4309 return "LCN40";
4310 case B43_PHYTYPE_AC:
4311 return "AC";
4312 }
4313 return "UNKNOWN";
4314}
4315
e4d6b795
MB		 4316/* Get PHY and RADIO versioning numbers */
4317static int b43_phy_versioning(struct b43_wldev *dev)
4318{
4319 struct b43_phy *phy = &dev->phy;
4320 u32 tmp;
4321 u8 analog_type;
4322 u8 phy_type;
4323 u8 phy_rev;
4324 u16 radio_manuf;
4325 u16 radio_ver;
4326 u16 radio_rev;
4327 int unsupported = 0;
4328
4329 /* Get PHY versioning */
4330 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4331 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4332 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4333 phy_rev = (tmp & B43_PHYVER_VERSION);
4334 switch (phy_type) {
418378fe 4335#ifdef CONFIG_B43_PHY_G
e4d6b795 4336 case B43_PHYTYPE_G:
013978b6 4337 if (phy_rev > 9)
e4d6b795
MB		 4338 unsupported = 1;
4339 break;
418378fe 4340#endif
692d2c0f 4341#ifdef CONFIG_B43_PHY_N
d5c71e46 4342 case B43_PHYTYPE_N:
ab72efdf 4343 if (phy_rev > 9)
d5c71e46
MB		 4344 unsupported = 1;
4345 break;
6b1c7c67
MB		 4346#endif
4347#ifdef CONFIG_B43_PHY_LP
4348 case B43_PHYTYPE_LP:
9d86a2d5 4349 if (phy_rev > 2)
6b1c7c67
MB		 4350 unsupported = 1;
4351 break;
d7520b1d
RM		 4352#endif
4353#ifdef CONFIG_B43_PHY_HT
4354 case B43_PHYTYPE_HT:
4355 if (phy_rev > 1)
4356 unsupported = 1;
4357 break;
1d738e64
RM		 4358#endif
4359#ifdef CONFIG_B43_PHY_LCN
4360 case B43_PHYTYPE_LCN:
4361 if (phy_rev > 1)
4362 unsupported = 1;
4363 break;
d5c71e46 4364#endif
e4d6b795
MB		 4365 default:
4366 unsupported = 1;
6403eab1 4367 }
e4d6b795 4368 if (unsupported) {
2fdf8c54
RM		 4369 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4370 analog_type, phy_type, b43_phy_name(dev, phy_type),
4371 phy_rev);
e4d6b795
MB		 4372 return -EOPNOTSUPP;
4373 }
2fdf8c54
RM		 4374 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4375 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
e4d6b795
MB		 4376
4377 /* Get RADIO versioning */
3fd48508 4378 if (dev->dev->core_rev >= 24) {
544e5d8b
RM		 4379 u16 radio24[3];
4380
4381 for (tmp = 0; tmp < 3; tmp++) {
4382 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4383 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4384 }
4385
4386 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4387 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4388
4389 radio_manuf = 0x17F;
4390 radio_ver = (radio24[2] << 8) | radio24[1];
4391 radio_rev = (radio24[0] & 0xF);
e4d6b795 4392 } else {
3fd48508
RM		 4393 if (dev->dev->chip_id == 0x4317) {
4394 if (dev->dev->chip_rev == 0)
4395 tmp = 0x3205017F;
4396 else if (dev->dev->chip_rev == 1)
4397 tmp = 0x4205017F;
4398 else
4399 tmp = 0x5205017F;
4400 } else {
4401 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4402 B43_RADIOCTL_ID);
4403 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4404 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4405 B43_RADIOCTL_ID);
4406 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4407 << 16;
4408 }
4409 radio_manuf = (tmp & 0x00000FFF);
4410 radio_ver = (tmp & 0x0FFFF000) >> 12;
4411 radio_rev = (tmp & 0xF0000000) >> 28;
e4d6b795 4412 }
3fd48508 4413
96c755a3
MB		 4414 if (radio_manuf != 0x17F /* Broadcom */)
4415 unsupported = 1;
e4d6b795
MB		 4416 switch (phy_type) {
4417 case B43_PHYTYPE_A:
4418 if (radio_ver != 0x2060)
4419 unsupported = 1;
4420 if (radio_rev != 1)
4421 unsupported = 1;
4422 if (radio_manuf != 0x17F)
4423 unsupported = 1;
4424 break;
4425 case B43_PHYTYPE_B:
4426 if ((radio_ver & 0xFFF0) != 0x2050)
4427 unsupported = 1;
4428 break;
4429 case B43_PHYTYPE_G:
4430 if (radio_ver != 0x2050)
4431 unsupported = 1;
4432 break;
96c755a3 4433 case B43_PHYTYPE_N:
bb519bee 4434 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4435 unsupported = 1;
4436 break;
6b1c7c67 4437 case B43_PHYTYPE_LP:
9d86a2d5 4438 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4439 unsupported = 1;
4440 break;
d7520b1d
RM		 4441 case B43_PHYTYPE_HT:
4442 if (radio_ver != 0x2059)
4443 unsupported = 1;
4444 break;
1d738e64
RM		 4445 case B43_PHYTYPE_LCN:
4446 if (radio_ver != 0x2064)
4447 unsupported = 1;
4448 break;
e4d6b795
MB		 4449 default:
4450 B43_WARN_ON(1);
4451 }
4452 if (unsupported) {
4453 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4454 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4455 radio_manuf, radio_ver, radio_rev);
4456 return -EOPNOTSUPP;
4457 }
4458 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4459 radio_manuf, radio_ver, radio_rev);
4460
4461 phy->radio_manuf = radio_manuf;
4462 phy->radio_ver = radio_ver;
4463 phy->radio_rev = radio_rev;
4464
4465 phy->analog = analog_type;
4466 phy->type = phy_type;
4467 phy->rev = phy_rev;
4468
4469 return 0;
4470}
4471
4472static void setup_struct_phy_for_init(struct b43_wldev *dev,
4473 struct b43_phy *phy)
4474{
e4d6b795 4475 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4476 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4477 /* PHY TX errors counter. */
4478 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4479
4480#if B43_DEBUG
3db1cd5c
RR		 4481 phy->phy_locked = false;
4482 phy->radio_locked = false;
591f3dc2 4483#endif
e4d6b795
MB		 4484}
4485
4486static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4487{
3db1cd5c 4488 dev->dfq_valid = false;
aa6c7ae2 4489
6a724d68
MB		 4490 /* Assume the radio is enabled. If it's not enabled, the state will
4491 * immediately get fixed on the first periodic work run. */
3db1cd5c 4492 dev->radio_hw_enable = true;
e4d6b795
MB		 4493
4494 /* Stats */
4495 memset(&dev->stats, 0, sizeof(dev->stats));
4496
4497 setup_struct_phy_for_init(dev, &dev->phy);
4498
4499 /* IRQ related flags */
4500 dev->irq_reason = 0;
4501 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4502 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4503 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4504 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4505
4506 dev->mac_suspended = 1;
4507
4508 /* Noise calculation context */
4509 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4510}
4511
4512static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4513{
0581483a 4514 struct ssb_sprom *sprom = dev->dev->bus_sprom;
a259d6a4 4515 u64 hf;
e4d6b795 4516
1855ba78
MB		 4517 if (!modparam_btcoex)
4518 return;
95de2841 4519 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4520 return;
4521 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4522 return;
4523
4524 hf = b43_hf_read(dev);
95de2841 4525 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4526 hf |= B43_HF_BTCOEXALT;
4527 else
4528 hf |= B43_HF_BTCOEX;
4529 b43_hf_write(dev, hf);
e4d6b795
MB		 4530}
4531
4532static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4533{
4534 if (!modparam_btcoex)
4535 return;
4536 //TODO
e4d6b795
MB		 4537}
4538
4539static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4540{
d48ae5c8 4541 struct ssb_bus *bus;
e4d6b795
MB		 4542 u32 tmp;
4543
bd7c8a59 4544#ifdef CONFIG_B43_SSB
d48ae5c8
RM		 4545 if (dev->dev->bus_type != B43_BUS_SSB)
4546 return;
bd7c8a59
RM		 4547#else
4548 return;
4549#endif
d48ae5c8
RM		 4550
4551 bus = dev->dev->sdev->bus;
4552
0fd82eaf
RM		 4553 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4554 (bus->chip_id == 0x4312)) {
d48ae5c8 4555 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
0fd82eaf
RM		 4556 tmp &= ~SSB_IMCFGLO_REQTO;
4557 tmp &= ~SSB_IMCFGLO_SERTO;
4558 tmp |= 0x3;
d48ae5c8 4559 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
0fd82eaf 4560 ssb_commit_settings(bus);
e4d6b795 4561 }
e4d6b795
MB		 4562}
4563
d59f720d
MB		 4564static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4565{
4566 u16 pu_delay;
4567
4568 /* The time value is in microseconds. */
4569 if (dev->phy.type == B43_PHYTYPE_A)
4570 pu_delay = 3700;
4571 else
4572 pu_delay = 1050;
05c914fe 4573 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4574 pu_delay = 500;
4575 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4576 pu_delay = max(pu_delay, (u16)2400);
4577
4578 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4579}
4580
4581/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4582static void b43_set_pretbtt(struct b43_wldev *dev)
4583{
4584 u16 pretbtt;
4585
4586 /* The time value is in microseconds. */
05c914fe 4587 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4588 pretbtt = 2;
4589 } else {
4590 if (dev->phy.type == B43_PHYTYPE_A)
4591 pretbtt = 120;
4592 else
4593 pretbtt = 250;
4594 }
4595 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4596 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4597}
4598
e4d6b795
MB		 4599/* Shutdown a wireless core */
4600/* Locking: wl->mutex */
4601static void b43_wireless_core_exit(struct b43_wldev *dev)
4602{
36dbd954
MB		 4603 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4604 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795 4605 return;
84c164a3 4606
e4d6b795
MB		 4607 b43_set_status(dev, B43_STAT_UNINIT);
4608
1f7d87b0 4609 /* Stop the microcode PSM. */
5056635c
RM		 4610 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4611 B43_MACCTL_PSM_JMP0);
1f7d87b0 4612
50023008
HM		 4613 switch (dev->dev->bus_type) {
4614#ifdef CONFIG_B43_BCMA
4615 case B43_BUS_BCMA:
4616 bcma_core_pci_down(dev->dev->bdev->bus);
4617 break;
4618#endif
4619#ifdef CONFIG_B43_SSB
4620 case B43_BUS_SSB:
4621 /* TODO */
4622 break;
4623#endif
4624 }
4625
e4d6b795 4626 b43_dma_free(dev);
5100d5ac 4627 b43_pio_free(dev);
e4d6b795 4628 b43_chip_exit(dev);
cb24f57f 4629 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4630 if (dev->wl->current_beacon) {
4631 dev_kfree_skb_any(dev->wl->current_beacon);
4632 dev->wl->current_beacon = NULL;
4633 }
4634
24ca39d6
RM		 4635 b43_device_disable(dev, 0);
4636 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4637}
4638
4639/* Initialize a wireless core */
4640static int b43_wireless_core_init(struct b43_wldev *dev)
4641{
0581483a 4642 struct ssb_sprom *sprom = dev->dev->bus_sprom;
e4d6b795
MB		 4643 struct b43_phy *phy = &dev->phy;
4644 int err;
a259d6a4 4645 u64 hf;
e4d6b795
MB		 4646
4647 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4648
24ca39d6 4649 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 4650 if (err)
4651 goto out;
4da909e7
RM		 4652 if (!b43_device_is_enabled(dev))
4653 b43_wireless_core_reset(dev, phy->gmode);
e4d6b795 4654
fb11137a 4655 /* Reset all data structures. */
e4d6b795 4656 setup_struct_wldev_for_init(dev);
fb11137a 4657 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4658
4659 /* Enable IRQ routing to this device. */
6cbab0d9 4660 switch (dev->dev->bus_type) {
42c9a458
RM		 4661#ifdef CONFIG_B43_BCMA
4662 case B43_BUS_BCMA:
dfae7143 4663 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
42c9a458 4664 dev->dev->bdev, true);
50023008 4665 bcma_core_pci_up(dev->dev->bdev->bus);
42c9a458
RM		 4666 break;
4667#endif
6cbab0d9
RM		 4668#ifdef CONFIG_B43_SSB
4669 case B43_BUS_SSB:
4670 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4671 dev->dev->sdev);
4672 break;
4673#endif
4674 }
e4d6b795
MB		 4675
4676 b43_imcfglo_timeouts_workaround(dev);
4677 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4678 if (phy->ops->prepare_hardware) {
4679 err = phy->ops->prepare_hardware(dev);
ef1a628d 4680 if (err)
fb11137a 4681 goto err_busdown;
ef1a628d 4682 }
e4d6b795
MB		 4683 err = b43_chip_init(dev);
4684 if (err)
fb11137a 4685 goto err_busdown;
e4d6b795 4686 b43_shm_write16(dev, B43_SHM_SHARED,
21d889d4 4687 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
e4d6b795
MB		 4688 hf = b43_hf_read(dev);
4689 if (phy->type == B43_PHYTYPE_G) {
4690 hf |= B43_HF_SYMW;
4691 if (phy->rev == 1)
4692 hf |= B43_HF_GDCW;
95de2841 4693 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4694 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4695 }
4696 if (phy->radio_ver == 0x2050) {
4697 if (phy->radio_rev == 6)
4698 hf |= B43_HF_4318TSSI;
4699 if (phy->radio_rev < 6)
4700 hf |= B43_HF_VCORECALC;
e4d6b795 4701 }
1cc8f476
MB		 4702 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4703 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
bd7c8a59 4704#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
6cbab0d9
RM		 4705 if (dev->dev->bus_type == B43_BUS_SSB &&
4706 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4707 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
8821905c 4708 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4709#endif
25d3ef59 4710 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4711 b43_hf_write(dev, hf);
4712
74cfdba7
MB		 4713 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4714 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4715 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4716 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4717
4718 /* Disable sending probe responses from firmware.
4719 * Setting the MaxTime to one usec will always trigger
4720 * a timeout, so we never send any probe resp.
4721 * A timeout of zero is infinite. */
4722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4723
4724 b43_rate_memory_init(dev);
5042c507 4725 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4726
4727 /* Minimum Contention Window */
c5a079f4 4728 if (phy->type == B43_PHYTYPE_B)
e4d6b795 4729 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
c5a079f4 4730 else
e4d6b795 4731 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
e4d6b795
MB		 4732 /* Maximum Contention Window */
4733 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4734
505fb019 4735 if (b43_bus_host_is_pcmcia(dev->dev) ||
cbe1e82a 4736 b43_bus_host_is_sdio(dev->dev)) {
3db1cd5c 4737 dev->__using_pio_transfers = true;
cbe1e82a
RM		 4738 err = b43_pio_init(dev);
4739 } else if (dev->use_pio) {
4740 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4741 "This should not be needed and will result in lower "
4742 "performance.\n");
3db1cd5c 4743 dev->__using_pio_transfers = true;
5100d5ac
MB		 4744 err = b43_pio_init(dev);
4745 } else {
3db1cd5c 4746 dev->__using_pio_transfers = false;
5100d5ac
MB		 4747 err = b43_dma_init(dev);
4748 }
e4d6b795
MB		 4749 if (err)
4750 goto err_chip_exit;
03b29773 4751 b43_qos_init(dev);
d59f720d 4752 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4753 b43_bluetooth_coext_enable(dev);
4754
24ca39d6 4755 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4756 b43_upload_card_macaddress(dev);
e4d6b795 4757 b43_security_init(dev);
e4d6b795 4758
5ab9549a 4759 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4760
4761 b43_set_status(dev, B43_STAT_INITIALIZED);
4762
1a8d1227 4763out:
e4d6b795
MB		 4764 return err;
4765
ef1a628d 4766err_chip_exit:
e4d6b795 4767 b43_chip_exit(dev);
ef1a628d 4768err_busdown:
24ca39d6 4769 b43_bus_may_powerdown(dev);
e4d6b795
MB		 4770 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4771 return err;
4772}
4773
40faacc4 4774static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4775 struct ieee80211_vif *vif)
e4d6b795
MB		 4776{
4777 struct b43_wl *wl = hw_to_b43_wl(hw);
4778 struct b43_wldev *dev;
e4d6b795 4779 int err = -EOPNOTSUPP;
4150c572
JB		 4780
4781 /* TODO: allow WDS/AP devices to coexist */
4782
1ed32e4f
JB		 4783 if (vif->type != NL80211_IFTYPE_AP &&
4784 vif->type != NL80211_IFTYPE_MESH_POINT &&
4785 vif->type != NL80211_IFTYPE_STATION &&
4786 vif->type != NL80211_IFTYPE_WDS &&
4787 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4788 return -EOPNOTSUPP;
e4d6b795
MB		 4789
4790 mutex_lock(&wl->mutex);
4150c572 4791 if (wl->operating)
e4d6b795
MB		 4792 goto out_mutex_unlock;
4793
1ed32e4f 4794 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4795
4796 dev = wl->current_dev;
3db1cd5c 4797 wl->operating = true;
1ed32e4f
JB		 4798 wl->vif = vif;
4799 wl->if_type = vif->type;
4800 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4801
4150c572 4802 b43_adjust_opmode(dev);
d59f720d
MB		 4803 b43_set_pretbtt(dev);
4804 b43_set_synth_pu_delay(dev, 0);
4150c572 4805 b43_upload_card_macaddress(dev);
4150c572
JB		 4806
4807 err = 0;
4808 out_mutex_unlock:
4809 mutex_unlock(&wl->mutex);
4810
2a190322
FF		 4811 if (err == 0)
4812 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4813
4150c572
JB		 4814 return err;
4815}
4816
40faacc4 4817static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4818 struct ieee80211_vif *vif)
4150c572
JB		 4819{
4820 struct b43_wl *wl = hw_to_b43_wl(hw);
4821 struct b43_wldev *dev = wl->current_dev;
4150c572 4822
1ed32e4f 4823 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4824
4825 mutex_lock(&wl->mutex);
4826
4827 B43_WARN_ON(!wl->operating);
1ed32e4f 4828 B43_WARN_ON(wl->vif != vif);
32bfd35d 4829 wl->vif = NULL;
4150c572 4830
3db1cd5c 4831 wl->operating = false;
4150c572 4832
4150c572
JB		 4833 b43_adjust_opmode(dev);
4834 memset(wl->mac_addr, 0, ETH_ALEN);
4835 b43_upload_card_macaddress(dev);
4150c572
JB		 4836
4837 mutex_unlock(&wl->mutex);
4838}
4839
40faacc4 4840static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4841{
4842 struct b43_wl *wl = hw_to_b43_wl(hw);
4843 struct b43_wldev *dev = wl->current_dev;
4844 int did_init = 0;
923403b8 4845 int err = 0;
4150c572 4846
7be1bb6b
MB		 4847 /* Kill all old instance specific information to make sure
4848 * the card won't use it in the short timeframe between start
4849 * and mac80211 reconfiguring it. */
4850 memset(wl->bssid, 0, ETH_ALEN);
4851 memset(wl->mac_addr, 0, ETH_ALEN);
4852 wl->filter_flags = 0;
3db1cd5c 4853 wl->radiotap_enabled = false;
e6f5b934 4854 b43_qos_clear(wl);
3db1cd5c
RR		 4855 wl->beacon0_uploaded = false;
4856 wl->beacon1_uploaded = false;
4857 wl->beacon_templates_virgin = true;
4858 wl->radio_enabled = true;
7be1bb6b 4859
4150c572
JB		 4860 mutex_lock(&wl->mutex);
4861
e4d6b795
MB		 4862 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4863 err = b43_wireless_core_init(dev);
f41f3f37 4864 if (err)
e4d6b795
MB		 4865 goto out_mutex_unlock;
4866 did_init = 1;
4867 }
4150c572 4868
e4d6b795
MB		 4869 if (b43_status(dev) < B43_STAT_STARTED) {
4870 err = b43_wireless_core_start(dev);
4871 if (err) {
4872 if (did_init)
4873 b43_wireless_core_exit(dev);
4874 goto out_mutex_unlock;
4875 }
4876 }
4877
f41f3f37
JB		 4878 /* XXX: only do if device doesn't support rfkill irq */
4879 wiphy_rfkill_start_polling(hw->wiphy);
4880
4150c572 4881 out_mutex_unlock:
e4d6b795
MB		 4882 mutex_unlock(&wl->mutex);
4883
dbdedbdf
SF		 4884 /*
4885 * Configuration may have been overwritten during initialization.
4886 * Reload the configuration, but only if initialization was
4887 * successful. Reloading the configuration after a failed init
4888 * may hang the system.
4889 */
4890 if (!err)
4891 b43_op_config(hw, ~0);
2a190322 4892
e4d6b795
MB		 4893 return err;
4894}
4895
40faacc4 4896static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4897{
4898 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4899 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4900
a82d9922 4901 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4902
ccde8a45
GL		 4903 if (!dev)
4904 goto out;
4905
e4d6b795 4906 mutex_lock(&wl->mutex);
36dbd954
MB		 4907 if (b43_status(dev) >= B43_STAT_STARTED) {
4908 dev = b43_wireless_core_stop(dev);
4909 if (!dev)
4910 goto out_unlock;
4911 }
4150c572 4912 b43_wireless_core_exit(dev);
3db1cd5c 4913 wl->radio_enabled = false;
36dbd954
MB		 4914
4915out_unlock:
e4d6b795 4916 mutex_unlock(&wl->mutex);
ccde8a45 4917out:
18c8adeb 4918 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4919}
4920
17741cdc
JB		 4921static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4922 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4923{
4924 struct b43_wl *wl = hw_to_b43_wl(hw);
4925
8f611288 4926 /* FIXME: add locking */
9d139c81 4927 b43_update_templates(wl);
e66fee6a
MB		 4928
4929 return 0;
4930}
4931
38968d09
JB		 4932static void b43_op_sta_notify(struct ieee80211_hw *hw,
4933 struct ieee80211_vif *vif,
4934 enum sta_notify_cmd notify_cmd,
17741cdc 4935 struct ieee80211_sta *sta)
38968d09
JB		 4936{
4937 struct b43_wl *wl = hw_to_b43_wl(hw);
4938
4939 B43_WARN_ON(!vif || wl->vif != vif);
4940}
4941
25d3ef59
MB		 4942static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4943{
4944 struct b43_wl *wl = hw_to_b43_wl(hw);
4945 struct b43_wldev *dev;
4946
4947 mutex_lock(&wl->mutex);
4948 dev = wl->current_dev;
4949 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4950 /* Disable CFP update during scan on other channels. */
4951 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4952 }
4953 mutex_unlock(&wl->mutex);
4954}
4955
4956static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4957{
4958 struct b43_wl *wl = hw_to_b43_wl(hw);
4959 struct b43_wldev *dev;
4960
4961 mutex_lock(&wl->mutex);
4962 dev = wl->current_dev;
4963 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4964 /* Re-enable CFP update. */
4965 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4966 }
4967 mutex_unlock(&wl->mutex);
4968}
4969
354b4f04
JL		 4970static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4971 struct survey_info *survey)
4972{
4973 struct b43_wl *wl = hw_to_b43_wl(hw);
4974 struct b43_wldev *dev = wl->current_dev;
4975 struct ieee80211_conf *conf = &hw->conf;
4976
4977 if (idx != 0)
4978 return -ENOENT;
4979
675a0b04 4980 survey->channel = conf->chandef.chan;
354b4f04
JL		 4981 survey->filled = SURVEY_INFO_NOISE_DBM;
4982 survey->noise = dev->stats.link_noise;
4983
4984 return 0;
4985}
4986
e4d6b795 4987static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4988 .tx = b43_op_tx,
4989 .conf_tx = b43_op_conf_tx,
4990 .add_interface = b43_op_add_interface,
4991 .remove_interface = b43_op_remove_interface,
4992 .config = b43_op_config,
c7ab5ef9 4993 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4994 .configure_filter = b43_op_configure_filter,
4995 .set_key = b43_op_set_key,
035d0243 4996 .update_tkip_key = b43_op_update_tkip_key,
40faacc4 4997 .get_stats = b43_op_get_stats,
08e87a83
AF		 4998 .get_tsf = b43_op_get_tsf,
4999 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 5000 .start = b43_op_start,
5001 .stop = b43_op_stop,
e66fee6a 5002 .set_tim = b43_op_beacon_set_tim,
38968d09 5003 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 5004 .sw_scan_start = b43_op_sw_scan_start_notifier,
5005 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
354b4f04 5006 .get_survey = b43_op_get_survey,
f41f3f37 5007 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 5008};
5009
5010/* Hard-reset the chip. Do not call this directly.
5011 * Use b43_controller_restart()
5012 */
5013static void b43_chip_reset(struct work_struct *work)
5014{
5015 struct b43_wldev *dev =
5016 container_of(work, struct b43_wldev, restart_work);
5017 struct b43_wl *wl = dev->wl;
5018 int err = 0;
5019 int prev_status;
5020
5021 mutex_lock(&wl->mutex);
5022
5023 prev_status = b43_status(dev);
5024 /* Bring the device down... */
36dbd954
MB		 5025 if (prev_status >= B43_STAT_STARTED) {
5026 dev = b43_wireless_core_stop(dev);
5027 if (!dev) {
5028 err = -ENODEV;
5029 goto out;
5030 }
5031 }
e4d6b795
MB		 5032 if (prev_status >= B43_STAT_INITIALIZED)
5033 b43_wireless_core_exit(dev);
5034
5035 /* ...and up again. */
5036 if (prev_status >= B43_STAT_INITIALIZED) {
5037 err = b43_wireless_core_init(dev);
5038 if (err)
5039 goto out;
5040 }
5041 if (prev_status >= B43_STAT_STARTED) {
5042 err = b43_wireless_core_start(dev);
5043 if (err) {
5044 b43_wireless_core_exit(dev);
5045 goto out;
5046 }
5047 }
3bf0a32e
MB		 5048out:
5049 if (err)
5050 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795 5051 mutex_unlock(&wl->mutex);
2a190322
FF		 5052
5053 if (err) {
e4d6b795 5054 b43err(wl, "Controller restart FAILED\n");
2a190322
FF		 5055 return;
5056 }
5057
5058 /* reload configuration */
5059 b43_op_config(wl->hw, ~0);
5060 if (wl->vif)
5061 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5062
5063 b43info(wl, "Controller restarted\n");
e4d6b795
MB		 5064}
5065
bb1eeff1 5066static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 5067 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 5068{
5069 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 5070
bb1eeff1
MB		 5071 if (have_2ghz_phy)
5072 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5073 if (dev->phy.type == B43_PHYTYPE_N) {
5074 if (have_5ghz_phy)
5075 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5076 } else {
5077 if (have_5ghz_phy)
5078 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5079 }
96c755a3 5080
bb1eeff1
MB		 5081 dev->phy.supports_2ghz = have_2ghz_phy;
5082 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 5083
5084 return 0;
5085}
5086
5087static void b43_wireless_core_detach(struct b43_wldev *dev)
5088{
5089 /* We release firmware that late to not be required to re-request
5090 * is all the time when we reinit the core. */
5091 b43_release_firmware(dev);
fb11137a 5092 b43_phy_free(dev);
e4d6b795
MB		 5093}
5094
075ca604
RM		 5095static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5096 bool *have_5ghz_phy)
5097{
5098 u16 dev_id = 0;
5099
773cfc50
RM		 5100#ifdef CONFIG_B43_BCMA
5101 if (dev->dev->bus_type == B43_BUS_BCMA &&
5102 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5103 dev_id = dev->dev->bdev->bus->host_pci->device;
5104#endif
075ca604
RM		 5105#ifdef CONFIG_B43_SSB
5106 if (dev->dev->bus_type == B43_BUS_SSB &&
5107 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5108 dev_id = dev->dev->sdev->bus->host_pci->device;
5109#endif
773cfc50
RM		 5110 /* Override with SPROM value if available */
5111 if (dev->dev->bus_sprom->dev_id)
5112 dev_id = dev->dev->bus_sprom->dev_id;
075ca604
RM		 5113
5114 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5115 switch (dev_id) {
5116 case 0x4324: /* BCM4306 */
5117 case 0x4312: /* BCM4311 */
5118 case 0x4319: /* BCM4318 */
773cfc50
RM		 5119 case 0x4328: /* BCM4321 */
5120 case 0x432b: /* BCM4322 */
5121 case 0x4350: /* BCM43222 */
5122 case 0x4353: /* BCM43224 */
5123 case 0x0576: /* BCM43224 */
5124 case 0x435f: /* BCM6362 */
5125 case 0x4331: /* BCM4331 */
5126 case 0x4359: /* BCM43228 */
5127 case 0x43a0: /* BCM4360 */
5128 case 0x43b1: /* BCM4352 */
075ca604
RM		 5129 /* Dual band devices */
5130 *have_2ghz_phy = true;
5131 *have_5ghz_phy = true;
5132 return;
773cfc50
RM		 5133 case 0x4321: /* BCM4306 */
5134 case 0x4313: /* BCM4311 */
5135 case 0x431a: /* BCM4318 */
5136 case 0x432a: /* BCM4321 */
5137 case 0x432d: /* BCM4322 */
5138 case 0x4352: /* BCM43222 */
5139 case 0x4333: /* BCM4331 */
5140 case 0x43a2: /* BCM4360 */
5141 case 0x43b3: /* BCM4352 */
5142 /* 5 GHz only devices */
5143 *have_2ghz_phy = false;
5144 *have_5ghz_phy = true;
5145 return;
075ca604
RM		 5146 }
5147
5148 /* As a fallback, try to guess using PHY type */
5149 switch (dev->phy.type) {
5150 case B43_PHYTYPE_A:
5151 *have_2ghz_phy = false;
5152 *have_5ghz_phy = true;
5153 return;
5154 case B43_PHYTYPE_G:
5155 case B43_PHYTYPE_N:
5156 case B43_PHYTYPE_LP:
5157 case B43_PHYTYPE_HT:
5158 case B43_PHYTYPE_LCN:
5159 *have_2ghz_phy = true;
5160 *have_5ghz_phy = false;
5161 return;
5162 }
5163
5164 B43_WARN_ON(1);
5165}
5166
e4d6b795
MB		 5167static int b43_wireless_core_attach(struct b43_wldev *dev)
5168{
5169 struct b43_wl *wl = dev->wl;
09951ad4 5170 struct b43_phy *phy = &dev->phy;
e4d6b795 5171 int err;
40c62269 5172 u32 tmp;
3db1cd5c 5173 bool have_2ghz_phy = false, have_5ghz_phy = false;
e4d6b795
MB		 5174
5175 /* Do NOT do any device initialization here.
5176 * Do it in wireless_core_init() instead.
5177 * This function is for gathering basic information about the HW, only.
5178 * Also some structs may be set up here. But most likely you want to have
5179 * that in core_init(), too.
5180 */
5181
24ca39d6 5182 err = b43_bus_powerup(dev, 0);
e4d6b795
MB		 5183 if (err) {
5184 b43err(wl, "Bus powerup failed\n");
5185 goto out;
5186 }
e4d6b795 5187
09951ad4
RM		 5188 phy->do_full_init = true;
5189
075ca604 5190 /* Try to guess supported bands for the first init needs */
6cbab0d9 5191 switch (dev->dev->bus_type) {
42c9a458
RM		 5192#ifdef CONFIG_B43_BCMA
5193 case B43_BUS_BCMA:
40c62269
RM		 5194 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5195 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5196 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
42c9a458
RM		 5197 break;
5198#endif
6cbab0d9
RM		 5199#ifdef CONFIG_B43_SSB
5200 case B43_BUS_SSB:
5201 if (dev->dev->core_rev >= 5) {
40c62269
RM		 5202 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5203 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5204 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
6cbab0d9
RM		 5205 } else
5206 B43_WARN_ON(1);
5207 break;
5208#endif
5209 }
e4d6b795 5210
96c755a3 5211 dev->phy.gmode = have_2ghz_phy;
4da909e7 5212 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795 5213
075ca604 5214 /* Get the PHY type. */
e4d6b795
MB		 5215 err = b43_phy_versioning(dev);
5216 if (err)
21954c36 5217 goto err_powerdown;
075ca604
RM		 5218
5219 /* Get real info about supported bands */
5220 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5221
5222 /* We don't support 5 GHz on some PHYs yet */
5223 switch (dev->phy.type) {
5224 case B43_PHYTYPE_A:
5225 case B43_PHYTYPE_N:
5226 case B43_PHYTYPE_LP:
773cfc50 5227 case B43_PHYTYPE_HT:
075ca604 5228 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
3db1cd5c 5229 have_5ghz_phy = false;
e4d6b795 5230 }
075ca604
RM		 5231
5232 if (!have_2ghz_phy && !have_5ghz_phy) {
5233 b43err(wl, "b43 can't support any band on this device\n");
96c755a3
MB		 5234 err = -EOPNOTSUPP;
5235 goto err_powerdown;
5236 }
2e35af14 5237
fb11137a
MB		 5238 err = b43_phy_allocate(dev);
5239 if (err)
5240 goto err_powerdown;
5241
96c755a3 5242 dev->phy.gmode = have_2ghz_phy;
4da909e7 5243 b43_wireless_core_reset(dev, dev->phy.gmode);
e4d6b795
MB		 5244
5245 err = b43_validate_chipaccess(dev);
5246 if (err)
fb11137a 5247 goto err_phy_free;
bb1eeff1 5248 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 5249 if (err)
fb11137a 5250 goto err_phy_free;
e4d6b795
MB		 5251
5252 /* Now set some default "current_dev" */
5253 if (!wl->current_dev)
5254 wl->current_dev = dev;
5255 INIT_WORK(&dev->restart_work, b43_chip_reset);
5256
cb24f57f 5257 dev->phy.ops->switch_analog(dev, 0);
24ca39d6
RM		 5258 b43_device_disable(dev, 0);
5259 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5260
5261out:
5262 return err;
5263
fb11137a
MB		 5264err_phy_free:
5265 b43_phy_free(dev);
e4d6b795 5266err_powerdown:
24ca39d6 5267 b43_bus_may_powerdown(dev);
e4d6b795
MB		 5268 return err;
5269}
5270
482f0538 5271static void b43_one_core_detach(struct b43_bus_dev *dev)
e4d6b795
MB		 5272{
5273 struct b43_wldev *wldev;
5274 struct b43_wl *wl;
5275
3bf0a32e
MB		 5276 /* Do not cancel ieee80211-workqueue based work here.
5277 * See comment in b43_remove(). */
5278
74abacb6 5279 wldev = b43_bus_get_wldev(dev);
e4d6b795 5280 wl = wldev->wl;
e4d6b795
MB		 5281 b43_debugfs_remove_device(wldev);
5282 b43_wireless_core_detach(wldev);
5283 list_del(&wldev->list);
74abacb6 5284 b43_bus_set_wldev(dev, NULL);
e4d6b795
MB		 5285 kfree(wldev);
5286}
5287
482f0538 5288static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5289{
5290 struct b43_wldev *wldev;
e4d6b795
MB		 5291 int err = -ENOMEM;
5292
e4d6b795
MB		 5293 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5294 if (!wldev)
5295 goto out;
5296
9e3bd919 5297 wldev->use_pio = b43_modparam_pio;
482f0538 5298 wldev->dev = dev;
e4d6b795
MB		 5299 wldev->wl = wl;
5300 b43_set_status(wldev, B43_STAT_UNINIT);
5301 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 5302 INIT_LIST_HEAD(&wldev->list);
5303
5304 err = b43_wireless_core_attach(wldev);
5305 if (err)
5306 goto err_kfree_wldev;
5307
74abacb6 5308 b43_bus_set_wldev(dev, wldev);
e4d6b795
MB		 5309 b43_debugfs_add_device(wldev);
5310
5311 out:
5312 return err;
5313
5314 err_kfree_wldev:
5315 kfree(wldev);
5316 return err;
5317}
5318
9fc38458
MB		 5319#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5320 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5321 (pdev->device == _device) && \
5322 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5323 (pdev->subsystem_device == _subdevice) )
5324
bd7c8a59 5325#ifdef CONFIG_B43_SSB
e4d6b795
MB		 5326static void b43_sprom_fixup(struct ssb_bus *bus)
5327{
1855ba78
MB		 5328 struct pci_dev *pdev;
5329
e4d6b795
MB		 5330 /* boardflags workarounds */
5331 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5a20ef3d 5332 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
95de2841 5333 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795 5334 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5a20ef3d 5335 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
95de2841 5336 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 5337 if (bus->bustype == SSB_BUSTYPE_PCI) {
5338 pdev = bus->host_pci;
9fc38458 5339 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 5340 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 5341 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 5342 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 5343 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 5344 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5345 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 5346 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5347 }
e4d6b795
MB		 5348}
5349
482f0538 5350static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
e4d6b795
MB		 5351{
5352 struct ieee80211_hw *hw = wl->hw;
5353
482f0538 5354 ssb_set_devtypedata(dev->sdev, NULL);
e4d6b795
MB		 5355 ieee80211_free_hw(hw);
5356}
bd7c8a59 5357#endif
e4d6b795 5358
d1507051 5359static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
e4d6b795 5360{
d1507051 5361 struct ssb_sprom *sprom = dev->bus_sprom;
e4d6b795
MB		 5362 struct ieee80211_hw *hw;
5363 struct b43_wl *wl;
2729df25 5364 char chip_name[6];
bad69194 5365 int queue_num;
e4d6b795
MB		 5366
5367 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5368 if (!hw) {
5369 b43err(NULL, "Could not allocate ieee80211 device\n");
0355a345 5370 return ERR_PTR(-ENOMEM);
e4d6b795 5371 }
403a3a13 5372 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 5373
5374 /* fill hw info */
605a0bd6 5375 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
f5c044e5 5376 IEEE80211_HW_SIGNAL_DBM;
566bfe5a 5377
f59ac048
LR		 5378 hw->wiphy->interface_modes =
5379 BIT(NL80211_IFTYPE_AP) |
5380 BIT(NL80211_IFTYPE_MESH_POINT) |
5381 BIT(NL80211_IFTYPE_STATION) |
5382 BIT(NL80211_IFTYPE_WDS) |
5383 BIT(NL80211_IFTYPE_ADHOC);
5384
78f9c850
AQ		 5385 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5386
e64add27 5387 wl->hw_registred = false;
e6a9854b 5388 hw->max_rates = 2;
e4d6b795 5389 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 5390 if (is_valid_ether_addr(sprom->et1mac))
5391 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 5392 else
95de2841 5393 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 5394
403a3a13 5395 /* Initialize struct b43_wl */
e4d6b795 5396 wl->hw = hw;
e4d6b795 5397 mutex_init(&wl->mutex);
36dbd954 5398 spin_lock_init(&wl->hardirq_lock);
a82d9922 5399 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 5400 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed 5401 INIT_WORK(&wl->tx_work, b43_tx_work);
bad69194 5402
5403 /* Initialize queues and flags. */
5404 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5405 skb_queue_head_init(&wl->tx_queue[queue_num]);
5406 wl->tx_queue_stopped[queue_num] = 0;
5407 }
e4d6b795 5408
2729df25
RM		 5409 snprintf(chip_name, ARRAY_SIZE(chip_name),
5410 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5411 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5412 dev->core_rev);
0355a345 5413 return wl;
e4d6b795
MB		 5414}
5415
3c65ab62
RM		 5416#ifdef CONFIG_B43_BCMA
5417static int b43_bcma_probe(struct bcma_device *core)
5418{
397915c3 5419 struct b43_bus_dev *dev;
24aad3f4
RM		 5420 struct b43_wl *wl;
5421 int err;
397915c3 5422
8960400e
RM		 5423 if (!modparam_allhwsupport &&
5424 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5425 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5426 return -ENOTSUPP;
5427 }
5428
397915c3
RM		 5429 dev = b43_bus_dev_bcma_init(core);
5430 if (!dev)
5431 return -ENODEV;
5432
24aad3f4
RM		 5433 wl = b43_wireless_init(dev);
5434 if (IS_ERR(wl)) {
5435 err = PTR_ERR(wl);
5436 goto bcma_out;
5437 }
5438
5439 err = b43_one_core_attach(dev, wl);
5440 if (err)
5441 goto bcma_err_wireless_exit;
5442
6b6fa586
LF		 5443 /* setup and start work to load firmware */
5444 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5445 schedule_work(&wl->firmware_load);
24aad3f4
RM		 5446
5447bcma_out:
5448 return err;
5449
24aad3f4
RM		 5450bcma_err_wireless_exit:
5451 ieee80211_free_hw(wl->hw);
5452 return err;
3c65ab62
RM		 5453}
5454
5455static void b43_bcma_remove(struct bcma_device *core)
5456{
24aad3f4
RM		 5457 struct b43_wldev *wldev = bcma_get_drvdata(core);
5458 struct b43_wl *wl = wldev->wl;
5459
5460 /* We must cancel any work here before unregistering from ieee80211,
5461 * as the ieee80211 unreg will destroy the workqueue. */
5462 cancel_work_sync(&wldev->restart_work);
63a02ce1 5463 cancel_work_sync(&wl->firmware_load);
24aad3f4 5464
e64add27 5465 B43_WARN_ON(!wl);
f89ff644
LF		 5466 if (!wldev->fw.ucode.data)
5467 return; /* NULL if firmware never loaded */
e64add27 5468 if (wl->current_dev == wldev && wl->hw_registred) {
e64add27
OR		 5469 b43_leds_stop(wldev);
5470 ieee80211_unregister_hw(wl->hw);
5471 }
24aad3f4
RM		 5472
5473 b43_one_core_detach(wldev->dev);
5474
09164043
LF		 5475 /* Unregister HW RNG driver */
5476 b43_rng_exit(wl);
5477
24aad3f4
RM		 5478 b43_leds_unregister(wl);
5479
5480 ieee80211_free_hw(wl->hw);
3c65ab62
RM		 5481}
5482
5483static struct bcma_driver b43_bcma_driver = {
5484 .name = KBUILD_MODNAME,
5485 .id_table = b43_bcma_tbl,
5486 .probe = b43_bcma_probe,
5487 .remove = b43_bcma_remove,
5488};
5489#endif
5490
aec7ffdf 5491#ifdef CONFIG_B43_SSB
aa63418a
RM		 5492static
5493int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
e4d6b795 5494{
482f0538 5495 struct b43_bus_dev *dev;
e4d6b795
MB		 5496 struct b43_wl *wl;
5497 int err;
e4d6b795 5498
482f0538 5499 dev = b43_bus_dev_ssb_init(sdev);
5b49b35a
DC		 5500 if (!dev)
5501 return -ENOMEM;
482f0538 5502
aa63418a 5503 wl = ssb_get_devtypedata(sdev);
8f15e287
RM		 5504 if (wl) {
5505 b43err(NULL, "Dual-core devices are not supported\n");
5506 err = -ENOTSUPP;
5507 goto err_ssb_kfree_dev;
e4d6b795 5508 }
8f15e287
RM		 5509
5510 b43_sprom_fixup(sdev->bus);
5511
5512 wl = b43_wireless_init(dev);
5513 if (IS_ERR(wl)) {
5514 err = PTR_ERR(wl);
5515 goto err_ssb_kfree_dev;
5516 }
5517 ssb_set_devtypedata(sdev, wl);
5518 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5519
e4d6b795
MB		 5520 err = b43_one_core_attach(dev, wl);
5521 if (err)
8f15e287 5522 goto err_ssb_wireless_exit;
e4d6b795 5523
6b6fa586
LF		 5524 /* setup and start work to load firmware */
5525 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5526 schedule_work(&wl->firmware_load);
e4d6b795 5527
e4d6b795
MB		 5528 return err;
5529
8f15e287
RM		 5530err_ssb_wireless_exit:
5531 b43_wireless_exit(dev, wl);
5532err_ssb_kfree_dev:
5533 kfree(dev);
e4d6b795
MB		 5534 return err;
5535}
5536
aa63418a 5537static void b43_ssb_remove(struct ssb_device *sdev)
e4d6b795 5538{
aa63418a
RM		 5539 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5540 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
e61b52d1 5541 struct b43_bus_dev *dev = wldev->dev;
e4d6b795 5542
3bf0a32e
MB		 5543 /* We must cancel any work here before unregistering from ieee80211,
5544 * as the ieee80211 unreg will destroy the workqueue. */
5545 cancel_work_sync(&wldev->restart_work);
63a02ce1 5546 cancel_work_sync(&wl->firmware_load);
3bf0a32e 5547
e4d6b795 5548 B43_WARN_ON(!wl);
f89ff644
LF		 5549 if (!wldev->fw.ucode.data)
5550 return; /* NULL if firmware never loaded */
e64add27 5551 if (wl->current_dev == wldev && wl->hw_registred) {
82905ace 5552 b43_leds_stop(wldev);
e4d6b795 5553 ieee80211_unregister_hw(wl->hw);
403a3a13 5554 }
e4d6b795 5555
e61b52d1 5556 b43_one_core_detach(dev);
e4d6b795 5557
09164043
LF		 5558 /* Unregister HW RNG driver */
5559 b43_rng_exit(wl);
5560
644aa4d6
RM		 5561 b43_leds_unregister(wl);
5562 b43_wireless_exit(dev, wl);
e4d6b795
MB		 5563}
5564
aec7ffdf
RM		 5565static struct ssb_driver b43_ssb_driver = {
5566 .name = KBUILD_MODNAME,
5567 .id_table = b43_ssb_tbl,
5568 .probe = b43_ssb_probe,
5569 .remove = b43_ssb_remove,
5570};
5571#endif /* CONFIG_B43_SSB */
5572
e4d6b795
MB		 5573/* Perform a hardware reset. This can be called from any context. */
5574void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5575{
5576 /* Must avoid requeueing, if we are in shutdown. */
5577 if (b43_status(dev) < B43_STAT_INITIALIZED)
5578 return;
5579 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5580 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5581}
5582
26bc783f
MB		 5583static void b43_print_driverinfo(void)
5584{
5585 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5586 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5587
5588#ifdef CONFIG_B43_PCI_AUTOSELECT
5589 feat_pci = "P";
5590#endif
5591#ifdef CONFIG_B43_PCMCIA
5592 feat_pcmcia = "M";
5593#endif
692d2c0f 5594#ifdef CONFIG_B43_PHY_N
26bc783f
MB		 5595 feat_nphy = "N";
5596#endif
5597#ifdef CONFIG_B43_LEDS
5598 feat_leds = "L";
3dbba8e2
AH		 5599#endif
5600#ifdef CONFIG_B43_SDIO
5601 feat_sdio = "S";
26bc783f
MB		 5602#endif
5603 printk(KERN_INFO "Broadcom 43xx driver loaded "
8b0be90c 5604 "[ Features: %s%s%s%s%s ]\n",
26bc783f 5605 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5606 feat_leds, feat_sdio);
26bc783f
MB		 5607}
5608
e4d6b795
MB		 5609static int __init b43_init(void)
5610{
5611 int err;
5612
5613 b43_debugfs_init();
5614 err = b43_pcmcia_init();
5615 if (err)
5616 goto err_dfs_exit;
3dbba8e2 5617 err = b43_sdio_init();
e4d6b795
MB		 5618 if (err)
5619 goto err_pcmcia_exit;
3c65ab62
RM		 5620#ifdef CONFIG_B43_BCMA
5621 err = bcma_driver_register(&b43_bcma_driver);
3dbba8e2
AH		 5622 if (err)
5623 goto err_sdio_exit;
3c65ab62 5624#endif
aec7ffdf 5625#ifdef CONFIG_B43_SSB
3c65ab62
RM		 5626 err = ssb_driver_register(&b43_ssb_driver);
5627 if (err)
5628 goto err_bcma_driver_exit;
aec7ffdf 5629#endif
26bc783f 5630 b43_print_driverinfo();
e4d6b795
MB		 5631
5632 return err;
5633
aec7ffdf 5634#ifdef CONFIG_B43_SSB
3c65ab62 5635err_bcma_driver_exit:
aec7ffdf 5636#endif
3c65ab62
RM		 5637#ifdef CONFIG_B43_BCMA
5638 bcma_driver_unregister(&b43_bcma_driver);
3dbba8e2 5639err_sdio_exit:
3c65ab62 5640#endif
3dbba8e2 5641 b43_sdio_exit();
e4d6b795
MB		 5642err_pcmcia_exit:
5643 b43_pcmcia_exit();
5644err_dfs_exit:
5645 b43_debugfs_exit();
5646 return err;
5647}
5648
5649static void __exit b43_exit(void)
5650{
aec7ffdf 5651#ifdef CONFIG_B43_SSB
e4d6b795 5652 ssb_driver_unregister(&b43_ssb_driver);
aec7ffdf 5653#endif
3c65ab62
RM		 5654#ifdef CONFIG_B43_BCMA
5655 bcma_driver_unregister(&b43_bcma_driver);
5656#endif
3dbba8e2 5657 b43_sdio_exit();
e4d6b795
MB		 5658 b43_pcmcia_exit();
5659 b43_debugfs_exit();
5660}
5661
5662module_init(b43_init)
5663module_exit(b43_exit)
Linux kernel - Deliverables
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