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ef1a628d MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | Common PHY routines | |
5 | ||
6 | Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, | |
7 | Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> | |
8 | Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de> | |
9 | Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> | |
10 | Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> | |
11 | ||
12 | This program is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
16 | ||
17 | This program is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with this program; see the file COPYING. If not, write to | |
24 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
25 | Boston, MA 02110-1301, USA. | |
26 | ||
27 | */ | |
28 | ||
29 | #include "phy_common.h" | |
30 | #include "phy_g.h" | |
31 | #include "phy_a.h" | |
3d0da751 | 32 | #include "phy_n.h" |
e63e4363 | 33 | #include "phy_lp.h" |
ef1a628d MB |
34 | #include "b43.h" |
35 | #include "main.h" | |
36 | ||
37 | ||
fb11137a | 38 | int b43_phy_allocate(struct b43_wldev *dev) |
ef1a628d MB |
39 | { |
40 | struct b43_phy *phy = &(dev->phy); | |
41 | int err; | |
42 | ||
43 | phy->ops = NULL; | |
44 | ||
45 | switch (phy->type) { | |
46 | case B43_PHYTYPE_A: | |
47 | phy->ops = &b43_phyops_a; | |
48 | break; | |
49 | case B43_PHYTYPE_G: | |
50 | phy->ops = &b43_phyops_g; | |
51 | break; | |
52 | case B43_PHYTYPE_N: | |
53 | #ifdef CONFIG_B43_NPHY | |
54 | phy->ops = &b43_phyops_n; | |
55 | #endif | |
56 | break; | |
57 | case B43_PHYTYPE_LP: | |
e63e4363 MB |
58 | #ifdef CONFIG_B43_PHY_LP |
59 | phy->ops = &b43_phyops_lp; | |
60 | #endif | |
ef1a628d MB |
61 | break; |
62 | } | |
63 | if (B43_WARN_ON(!phy->ops)) | |
64 | return -ENODEV; | |
65 | ||
66 | err = phy->ops->allocate(dev); | |
67 | if (err) | |
68 | phy->ops = NULL; | |
69 | ||
70 | return err; | |
71 | } | |
72 | ||
fb11137a MB |
73 | void b43_phy_free(struct b43_wldev *dev) |
74 | { | |
75 | dev->phy.ops->free(dev); | |
76 | dev->phy.ops = NULL; | |
77 | } | |
78 | ||
ef1a628d MB |
79 | int b43_phy_init(struct b43_wldev *dev) |
80 | { | |
81 | struct b43_phy *phy = &dev->phy; | |
82 | const struct b43_phy_operations *ops = phy->ops; | |
83 | int err; | |
84 | ||
85 | phy->channel = ops->get_default_chan(dev); | |
86 | ||
19d337df | 87 | ops->software_rfkill(dev, false); |
ef1a628d MB |
88 | err = ops->init(dev); |
89 | if (err) { | |
90 | b43err(dev->wl, "PHY init failed\n"); | |
91 | goto err_block_rf; | |
92 | } | |
93 | /* Make sure to switch hardware and firmware (SHM) to | |
94 | * the default channel. */ | |
95 | err = b43_switch_channel(dev, ops->get_default_chan(dev)); | |
96 | if (err) { | |
97 | b43err(dev->wl, "PHY init: Channel switch to default failed\n"); | |
98 | goto err_phy_exit; | |
99 | } | |
100 | ||
101 | return 0; | |
102 | ||
103 | err_phy_exit: | |
104 | if (ops->exit) | |
105 | ops->exit(dev); | |
106 | err_block_rf: | |
19d337df | 107 | ops->software_rfkill(dev, true); |
ef1a628d MB |
108 | |
109 | return err; | |
110 | } | |
111 | ||
112 | void b43_phy_exit(struct b43_wldev *dev) | |
113 | { | |
114 | const struct b43_phy_operations *ops = dev->phy.ops; | |
115 | ||
19d337df | 116 | ops->software_rfkill(dev, true); |
ef1a628d MB |
117 | if (ops->exit) |
118 | ops->exit(dev); | |
119 | } | |
120 | ||
121 | bool b43_has_hardware_pctl(struct b43_wldev *dev) | |
122 | { | |
123 | if (!dev->phy.hardware_power_control) | |
124 | return 0; | |
125 | if (!dev->phy.ops->supports_hwpctl) | |
126 | return 0; | |
127 | return dev->phy.ops->supports_hwpctl(dev); | |
128 | } | |
129 | ||
130 | void b43_radio_lock(struct b43_wldev *dev) | |
131 | { | |
132 | u32 macctl; | |
133 | ||
591f3dc2 MB |
134 | #if B43_DEBUG |
135 | B43_WARN_ON(dev->phy.radio_locked); | |
136 | dev->phy.radio_locked = 1; | |
137 | #endif | |
138 | ||
ef1a628d | 139 | macctl = b43_read32(dev, B43_MMIO_MACCTL); |
ef1a628d MB |
140 | macctl |= B43_MACCTL_RADIOLOCK; |
141 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
591f3dc2 MB |
142 | /* Commit the write and wait for the firmware |
143 | * to finish any radio register access. */ | |
ef1a628d MB |
144 | b43_read32(dev, B43_MMIO_MACCTL); |
145 | udelay(10); | |
146 | } | |
147 | ||
148 | void b43_radio_unlock(struct b43_wldev *dev) | |
149 | { | |
150 | u32 macctl; | |
151 | ||
591f3dc2 MB |
152 | #if B43_DEBUG |
153 | B43_WARN_ON(!dev->phy.radio_locked); | |
154 | dev->phy.radio_locked = 0; | |
155 | #endif | |
156 | ||
ef1a628d MB |
157 | /* Commit any write */ |
158 | b43_read16(dev, B43_MMIO_PHY_VER); | |
159 | /* unlock */ | |
160 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
ef1a628d MB |
161 | macctl &= ~B43_MACCTL_RADIOLOCK; |
162 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
163 | } | |
164 | ||
165 | void b43_phy_lock(struct b43_wldev *dev) | |
166 | { | |
167 | #if B43_DEBUG | |
168 | B43_WARN_ON(dev->phy.phy_locked); | |
169 | dev->phy.phy_locked = 1; | |
170 | #endif | |
171 | B43_WARN_ON(dev->dev->id.revision < 3); | |
172 | ||
05c914fe | 173 | if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) |
ef1a628d MB |
174 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); |
175 | } | |
176 | ||
177 | void b43_phy_unlock(struct b43_wldev *dev) | |
178 | { | |
179 | #if B43_DEBUG | |
180 | B43_WARN_ON(!dev->phy.phy_locked); | |
181 | dev->phy.phy_locked = 0; | |
182 | #endif | |
183 | B43_WARN_ON(dev->dev->id.revision < 3); | |
184 | ||
05c914fe | 185 | if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) |
ef1a628d MB |
186 | b43_power_saving_ctl_bits(dev, 0); |
187 | } | |
188 | ||
d10d0e57 MB |
189 | static inline void assert_mac_suspended(struct b43_wldev *dev) |
190 | { | |
191 | if (!B43_DEBUG) | |
192 | return; | |
193 | if ((b43_status(dev) >= B43_STAT_INITIALIZED) && | |
194 | (dev->mac_suspended <= 0)) { | |
195 | b43dbg(dev->wl, "PHY/RADIO register access with " | |
196 | "enabled MAC.\n"); | |
197 | dump_stack(); | |
198 | } | |
199 | } | |
200 | ||
ef1a628d MB |
201 | u16 b43_radio_read(struct b43_wldev *dev, u16 reg) |
202 | { | |
d10d0e57 | 203 | assert_mac_suspended(dev); |
ef1a628d MB |
204 | return dev->phy.ops->radio_read(dev, reg); |
205 | } | |
206 | ||
207 | void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value) | |
208 | { | |
d10d0e57 | 209 | assert_mac_suspended(dev); |
ef1a628d MB |
210 | dev->phy.ops->radio_write(dev, reg, value); |
211 | } | |
212 | ||
213 | void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask) | |
214 | { | |
215 | b43_radio_write16(dev, offset, | |
216 | b43_radio_read16(dev, offset) & mask); | |
217 | } | |
218 | ||
219 | void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set) | |
220 | { | |
221 | b43_radio_write16(dev, offset, | |
222 | b43_radio_read16(dev, offset) | set); | |
223 | } | |
224 | ||
225 | void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) | |
226 | { | |
227 | b43_radio_write16(dev, offset, | |
228 | (b43_radio_read16(dev, offset) & mask) | set); | |
229 | } | |
230 | ||
231 | u16 b43_phy_read(struct b43_wldev *dev, u16 reg) | |
232 | { | |
d10d0e57 | 233 | assert_mac_suspended(dev); |
ef1a628d MB |
234 | return dev->phy.ops->phy_read(dev, reg); |
235 | } | |
236 | ||
237 | void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value) | |
238 | { | |
d10d0e57 | 239 | assert_mac_suspended(dev); |
ef1a628d MB |
240 | dev->phy.ops->phy_write(dev, reg, value); |
241 | } | |
242 | ||
243 | void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask) | |
244 | { | |
245 | b43_phy_write(dev, offset, | |
246 | b43_phy_read(dev, offset) & mask); | |
247 | } | |
248 | ||
249 | void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set) | |
250 | { | |
251 | b43_phy_write(dev, offset, | |
252 | b43_phy_read(dev, offset) | set); | |
253 | } | |
254 | ||
255 | void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) | |
256 | { | |
257 | b43_phy_write(dev, offset, | |
258 | (b43_phy_read(dev, offset) & mask) | set); | |
259 | } | |
260 | ||
261 | int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel) | |
262 | { | |
263 | struct b43_phy *phy = &(dev->phy); | |
264 | u16 channelcookie, savedcookie; | |
265 | int err; | |
266 | ||
267 | if (new_channel == B43_DEFAULT_CHANNEL) | |
268 | new_channel = phy->ops->get_default_chan(dev); | |
269 | ||
270 | /* First we set the channel radio code to prevent the | |
271 | * firmware from sending ghost packets. | |
272 | */ | |
273 | channelcookie = new_channel; | |
274 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
275 | channelcookie |= 0x100; | |
276 | //FIXME set 40Mhz flag if required | |
277 | savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN); | |
278 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie); | |
279 | ||
280 | /* Now try to switch the PHY hardware channel. */ | |
281 | err = phy->ops->switch_channel(dev, new_channel); | |
282 | if (err) | |
283 | goto err_restore_cookie; | |
284 | ||
285 | dev->phy.channel = new_channel; | |
286 | /* Wait for the radio to tune to the channel and stabilize. */ | |
287 | msleep(8); | |
288 | ||
289 | return 0; | |
290 | ||
291 | err_restore_cookie: | |
292 | b43_shm_write16(dev, B43_SHM_SHARED, | |
293 | B43_SHM_SH_CHAN, savedcookie); | |
294 | ||
295 | return err; | |
296 | } | |
297 | ||
19d337df | 298 | void b43_software_rfkill(struct b43_wldev *dev, bool blocked) |
ef1a628d MB |
299 | { |
300 | struct b43_phy *phy = &dev->phy; | |
301 | ||
b929ecf7 | 302 | b43_mac_suspend(dev); |
19d337df JB |
303 | phy->ops->software_rfkill(dev, blocked); |
304 | phy->radio_on = !blocked; | |
b929ecf7 | 305 | b43_mac_enable(dev); |
ef1a628d | 306 | } |
18c8adeb MB |
307 | |
308 | /** | |
309 | * b43_phy_txpower_adjust_work - TX power workqueue. | |
310 | * | |
311 | * Workqueue for updating the TX power parameters in hardware. | |
312 | */ | |
313 | void b43_phy_txpower_adjust_work(struct work_struct *work) | |
314 | { | |
315 | struct b43_wl *wl = container_of(work, struct b43_wl, | |
316 | txpower_adjust_work); | |
317 | struct b43_wldev *dev; | |
318 | ||
319 | mutex_lock(&wl->mutex); | |
320 | dev = wl->current_dev; | |
321 | ||
322 | if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED))) | |
323 | dev->phy.ops->adjust_txpower(dev); | |
324 | ||
325 | mutex_unlock(&wl->mutex); | |
326 | } | |
327 | ||
328 | /* Called with wl->irq_lock locked */ | |
329 | void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags) | |
330 | { | |
331 | struct b43_phy *phy = &dev->phy; | |
332 | unsigned long now = jiffies; | |
333 | enum b43_txpwr_result result; | |
334 | ||
335 | if (!(flags & B43_TXPWR_IGNORE_TIME)) { | |
336 | /* Check if it's time for a TXpower check. */ | |
337 | if (time_before(now, phy->next_txpwr_check_time)) | |
338 | return; /* Not yet */ | |
339 | } | |
340 | /* The next check will be needed in two seconds, or later. */ | |
341 | phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2)); | |
342 | ||
343 | if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) && | |
344 | (dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306)) | |
345 | return; /* No software txpower adjustment needed */ | |
346 | ||
347 | result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI)); | |
348 | if (result == B43_TXPWR_RES_DONE) | |
349 | return; /* We are done. */ | |
350 | B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST); | |
351 | B43_WARN_ON(phy->ops->adjust_txpower == NULL); | |
352 | ||
353 | /* We must adjust the transmission power in hardware. | |
354 | * Schedule b43_phy_txpower_adjust_work(). */ | |
355 | queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work); | |
356 | } | |
357 | ||
358 | int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset) | |
359 | { | |
360 | const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK); | |
361 | unsigned int a, b, c, d; | |
362 | unsigned int average; | |
363 | u32 tmp; | |
364 | ||
365 | tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset); | |
366 | a = tmp & 0xFF; | |
367 | b = (tmp >> 8) & 0xFF; | |
368 | c = (tmp >> 16) & 0xFF; | |
369 | d = (tmp >> 24) & 0xFF; | |
370 | if (a == 0 || a == B43_TSSI_MAX || | |
371 | b == 0 || b == B43_TSSI_MAX || | |
372 | c == 0 || c == B43_TSSI_MAX || | |
373 | d == 0 || d == B43_TSSI_MAX) | |
374 | return -ENOENT; | |
375 | /* The values are OK. Clear them. */ | |
376 | tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) | | |
377 | (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24); | |
378 | b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp); | |
379 | ||
380 | if (is_ofdm) { | |
381 | a = (a + 32) & 0x3F; | |
382 | b = (b + 32) & 0x3F; | |
383 | c = (c + 32) & 0x3F; | |
384 | d = (d + 32) & 0x3F; | |
385 | } | |
386 | ||
387 | /* Get the average of the values with 0.5 added to each value. */ | |
388 | average = (a + b + c + d + 2) / 4; | |
389 | if (is_ofdm) { | |
390 | /* Adjust for CCK-boost */ | |
391 | if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO) | |
392 | & B43_HF_CCKBOOST) | |
393 | average = (average >= 13) ? (average - 13) : 0; | |
394 | } | |
395 | ||
396 | return average; | |
397 | } | |
cb24f57f MB |
398 | |
399 | void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on) | |
400 | { | |
401 | b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); | |
402 | } |