[deliverable/linux.git] / drivers / net / wireless / b43 / phy_common.c

/*

  Broadcom B43 wireless driver
  Common PHY routines

  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include "phy_common.h"
#include "phy_g.h"
#include "phy_a.h"
#include "phy_n.h"
#include "phy_lp.h"
#include "phy_ht.h"
#include "b43.h"
#include "main.h"


int b43_phy_allocate(struct b43_wldev *dev)
{
	struct b43_phy *phy = &(dev->phy);
	int err;

	phy->ops = NULL;

	switch (phy->type) {
	case B43_PHYTYPE_A:
		phy->ops = &b43_phyops_a;
		break;
	case B43_PHYTYPE_G:
		phy->ops = &b43_phyops_g;
		break;
	case B43_PHYTYPE_N:
#ifdef CONFIG_B43_PHY_N
		phy->ops = &b43_phyops_n;
#endif
		break;
	case B43_PHYTYPE_LP:
#ifdef CONFIG_B43_PHY_LP
		phy->ops = &b43_phyops_lp;
#endif
		break;
	case B43_PHYTYPE_HT:
#ifdef CONFIG_B43_PHY_HT
		phy->ops = &b43_phyops_ht;
#endif
		break;
	}
	if (B43_WARN_ON(!phy->ops))
		return -ENODEV;

	err = phy->ops->allocate(dev);
	if (err)
		phy->ops = NULL;

	return err;
}

void b43_phy_free(struct b43_wldev *dev)
{
	dev->phy.ops->free(dev);
	dev->phy.ops = NULL;
}

int b43_phy_init(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	const struct b43_phy_operations *ops = phy->ops;
	int err;

	phy->channel = ops->get_default_chan(dev);

	ops->software_rfkill(dev, false);
	err = ops->init(dev);
	if (err) {
		b43err(dev->wl, "PHY init failed\n");
		goto err_block_rf;
	}
	/* Make sure to switch hardware and firmware (SHM) to
	 * the default channel. */
	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	if (err) {
		b43err(dev->wl, "PHY init: Channel switch to default failed\n");
		goto err_phy_exit;
	}

	return 0;

err_phy_exit:
	if (ops->exit)
		ops->exit(dev);
err_block_rf:
	ops->software_rfkill(dev, true);

	return err;
}

void b43_phy_exit(struct b43_wldev *dev)
{
	const struct b43_phy_operations *ops = dev->phy.ops;

	ops->software_rfkill(dev, true);
	if (ops->exit)
		ops->exit(dev);
}

bool b43_has_hardware_pctl(struct b43_wldev *dev)
{
	if (!dev->phy.hardware_power_control)
		return 0;
	if (!dev->phy.ops->supports_hwpctl)
		return 0;
	return dev->phy.ops->supports_hwpctl(dev);
}

void b43_radio_lock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(dev->phy.radio_locked);
	dev->phy.radio_locked = 1;
#endif

	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl |= B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Commit the write and wait for the firmware
	 * to finish any radio register access. */
	b43_read32(dev, B43_MMIO_MACCTL);
	udelay(10);
}

void b43_radio_unlock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(!dev->phy.radio_locked);
	dev->phy.radio_locked = 0;
#endif

	/* Commit any write */
	b43_read16(dev, B43_MMIO_PHY_VER);
	/* unlock */
	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl &= ~B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
}

void b43_phy_lock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(dev->phy.phy_locked);
	dev->phy.phy_locked = 1;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
}

void b43_phy_unlock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(!dev->phy.phy_locked);
	dev->phy.phy_locked = 0;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, 0);
}

static inline void assert_mac_suspended(struct b43_wldev *dev)
{
	if (!B43_DEBUG)
		return;
	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	    (dev->mac_suspended <= 0)) {
		b43dbg(dev->wl, "PHY/RADIO register access with "
		       "enabled MAC.\n");
		dump_stack();
	}
}

u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	return dev->phy.ops->radio_read(dev, reg);
}

void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->radio_write(dev, reg, value);
}

void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) & mask);
}

void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) | set);
}

void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	b43_radio_write16(dev, offset,
			  (b43_radio_read16(dev, offset) & mask) | set);
}

u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	dev->phy.writes_counter = 0;
	return dev->phy.ops->phy_read(dev, reg);
}

void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, reg, value);
	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
		b43_read16(dev, B43_MMIO_PHY_VER);
		dev->phy.writes_counter = 0;
	}
}

void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, destreg,
		dev->phy.ops->phy_read(dev, srcreg));
}

void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) & mask);
	}
}

void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) | set);
	}
}

void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, set);
	} else {
		b43_phy_write(dev, offset,
			      (b43_phy_read(dev, offset) & mask) | set);
	}
}

int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
{
	struct b43_phy *phy = &(dev->phy);
	u16 channelcookie, savedcookie;
	int err;

	if (new_channel == B43_DEFAULT_CHANNEL)
		new_channel = phy->ops->get_default_chan(dev);

	/* First we set the channel radio code to prevent the
	 * firmware from sending ghost packets.
	 */
	channelcookie = new_channel;
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		channelcookie |= B43_SHM_SH_CHAN_5GHZ;
	/* FIXME: set 40Mhz flag if required */
	if (0)
		channelcookie |= B43_SHM_SH_CHAN_40MHZ;
	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);

	/* Now try to switch the PHY hardware channel. */
	err = phy->ops->switch_channel(dev, new_channel);
	if (err)
		goto err_restore_cookie;

	dev->phy.channel = new_channel;
	/* Wait for the radio to tune to the channel and stabilize. */
	msleep(8);

	return 0;

err_restore_cookie:
	b43_shm_write16(dev, B43_SHM_SHARED,
			B43_SHM_SH_CHAN, savedcookie);

	return err;
}

void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
{
	struct b43_phy *phy = &dev->phy;

	b43_mac_suspend(dev);
	phy->ops->software_rfkill(dev, blocked);
	phy->radio_on = !blocked;
	b43_mac_enable(dev);
}

/**
 * b43_phy_txpower_adjust_work - TX power workqueue.
 *
 * Workqueue for updating the TX power parameters in hardware.
 */
void b43_phy_txpower_adjust_work(struct work_struct *work)
{
	struct b43_wl *wl = container_of(work, struct b43_wl,
					 txpower_adjust_work);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
		dev->phy.ops->adjust_txpower(dev);

	mutex_unlock(&wl->mutex);
}

void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
{
	struct b43_phy *phy = &dev->phy;
	unsigned long now = jiffies;
	enum b43_txpwr_result result;

	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
		/* Check if it's time for a TXpower check. */
		if (time_before(now, phy->next_txpwr_check_time))
			return; /* Not yet */
	}
	/* The next check will be needed in two seconds, or later. */
	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));

	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
	    (dev->dev->board_type == SSB_BOARD_BU4306))
		return; /* No software txpower adjustment needed */

	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	if (result == B43_TXPWR_RES_DONE)
		return; /* We are done. */
	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	B43_WARN_ON(phy->ops->adjust_txpower == NULL);

	/* We must adjust the transmission power in hardware.
	 * Schedule b43_phy_txpower_adjust_work(). */
	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
}

int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
{
	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	unsigned int a, b, c, d;
	unsigned int average;
	u32 tmp;

	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	a = tmp & 0xFF;
	b = (tmp >> 8) & 0xFF;
	c = (tmp >> 16) & 0xFF;
	d = (tmp >> 24) & 0xFF;
	if (a == 0 || a == B43_TSSI_MAX ||
	    b == 0 || b == B43_TSSI_MAX ||
	    c == 0 || c == B43_TSSI_MAX ||
	    d == 0 || d == B43_TSSI_MAX)
		return -ENOENT;
	/* The values are OK. Clear them. */
	tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
	      (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);

	if (is_ofdm) {
		a = (a + 32) & 0x3F;
		b = (b + 32) & 0x3F;
		c = (c + 32) & 0x3F;
		d = (d + 32) & 0x3F;
	}

	/* Get the average of the values with 0.5 added to each value. */
	average = (a + b + c + d + 2) / 4;
	if (is_ofdm) {
		/* Adjust for CCK-boost */
		if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
		    & B43_HF_CCKBOOST)
			average = (average >= 13) ? (average - 13) : 0;
	}

	return average;
}

void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
{
	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
}


bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
{
	return (channel_type == NL80211_CHAN_HT40MINUS ||
		channel_type == NL80211_CHAN_HT40PLUS);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
struct b43_c32 b43_cordic(int theta)
{
	static const u32 arctg[] = {
		2949120, 1740967, 919879, 466945, 234379, 117304,
		  58666,   29335,  14668,   7334,   3667,   1833,
		    917,     458,    229,    115,     57,     29,
	};
	u8 i;
	s32 tmp;
	s8 signx = 1;
	u32 angle = 0;
	struct b43_c32 ret = { .i = 39797, .q = 0, };

	while (theta > (180 << 16))
		theta -= (360 << 16);
	while (theta < -(180 << 16))
		theta += (360 << 16);

	if (theta > (90 << 16)) {
		theta -= (180 << 16);
		signx = -1;
	} else if (theta < -(90 << 16)) {
		theta += (180 << 16);
		signx = -1;
	}

	for (i = 0; i <= 17; i++) {
		if (theta > angle) {
			tmp = ret.i - (ret.q >> i);
			ret.q += ret.i >> i;
			ret.i = tmp;
			angle += arctg[i];
		} else {
			tmp = ret.i + (ret.q >> i);
			ret.q -= ret.i >> i;
			ret.i = tmp;
			angle -= arctg[i];
		}
	}

	ret.i *= signx;
	ret.q *= signx;

	return ret;
}
Commit	Line	Data
ef1a628d MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	Common PHY routines
	5
	6	Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
	7	Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
	8	Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
	9	Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
	10	Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; see the file COPYING. If not, write to
	24	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	25	Boston, MA 02110-1301, USA.
	26
	27	*/
	28
	29	#include "phy_common.h"
	30	#include "phy_g.h"
	31	#include "phy_a.h"
3d0da751	32	#include "phy_n.h"
e63e4363	33	#include "phy_lp.h"
d7520b1d	34	#include "phy_ht.h"
ef1a628d MB	35	#include "b43.h"
	36	#include "main.h"
	37
	38
fb11137a	39	int b43_phy_allocate(struct b43_wldev *dev)
ef1a628d MB	40	{
	41	struct b43_phy *phy = &(dev->phy);
	42	int err;
	43
	44	phy->ops = NULL;
	45
	46	switch (phy->type) {
	47	case B43_PHYTYPE_A:
	48	phy->ops = &b43_phyops_a;
	49	break;
	50	case B43_PHYTYPE_G:
	51	phy->ops = &b43_phyops_g;
	52	break;
	53	case B43_PHYTYPE_N:
692d2c0f	54	#ifdef CONFIG_B43_PHY_N
ef1a628d MB	55	phy->ops = &b43_phyops_n;
	56	#endif
	57	break;
	58	case B43_PHYTYPE_LP:
e63e4363 MB	59	#ifdef CONFIG_B43_PHY_LP
e63e4363 MB	60	phy->ops = &b43_phyops_lp;
d7520b1d RM	61	#endif
	62	break;
	63	case B43_PHYTYPE_HT:
	64	#ifdef CONFIG_B43_PHY_HT
	65	phy->ops = &b43_phyops_ht;
e63e4363	66	#endif
ef1a628d MB	67	break;
	68	}
	69	if (B43_WARN_ON(!phy->ops))
	70	return -ENODEV;
	71
	72	err = phy->ops->allocate(dev);
	73	if (err)
	74	phy->ops = NULL;
	75
	76	return err;
	77	}
	78
fb11137a MB	79	void b43_phy_free(struct b43_wldev *dev)
	80	{
	81	dev->phy.ops->free(dev);
	82	dev->phy.ops = NULL;
	83	}
	84
ef1a628d MB	85	int b43_phy_init(struct b43_wldev *dev)
	86	{
	87	struct b43_phy *phy = &dev->phy;
	88	const struct b43_phy_operations *ops = phy->ops;
	89	int err;
	90
	91	phy->channel = ops->get_default_chan(dev);
	92
19d337df	93	ops->software_rfkill(dev, false);
ef1a628d MB	94	err = ops->init(dev);
	95	if (err) {
	96	b43err(dev->wl, "PHY init failed\n");
	97	goto err_block_rf;
	98	}
	99	/* Make sure to switch hardware and firmware (SHM) to
	100	* the default channel. */
	101	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	102	if (err) {
	103	b43err(dev->wl, "PHY init: Channel switch to default failed\n");
	104	goto err_phy_exit;
	105	}
	106
	107	return 0;
	108
	109	err_phy_exit:
	110	if (ops->exit)
	111	ops->exit(dev);
	112	err_block_rf:
19d337df	113	ops->software_rfkill(dev, true);
ef1a628d MB	114
	115	return err;
	116	}
	117
	118	void b43_phy_exit(struct b43_wldev *dev)
	119	{
	120	const struct b43_phy_operations *ops = dev->phy.ops;
	121
19d337df	122	ops->software_rfkill(dev, true);
ef1a628d MB	123	if (ops->exit)
	124	ops->exit(dev);
	125	}
	126
	127	bool b43_has_hardware_pctl(struct b43_wldev *dev)
	128	{
	129	if (!dev->phy.hardware_power_control)
	130	return 0;
	131	if (!dev->phy.ops->supports_hwpctl)
	132	return 0;
	133	return dev->phy.ops->supports_hwpctl(dev);
	134	}
	135
	136	void b43_radio_lock(struct b43_wldev *dev)
	137	{
	138	u32 macctl;
	139
591f3dc2 MB	140	#if B43_DEBUG
	141	B43_WARN_ON(dev->phy.radio_locked);
	142	dev->phy.radio_locked = 1;
	143	#endif
	144
ef1a628d	145	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	146	macctl \|= B43_MACCTL_RADIOLOCK;
ef1a628d MB	147	b43_write32(dev, B43_MMIO_MACCTL, macctl);
591f3dc2 MB	148	/* Commit the write and wait for the firmware
591f3dc2 MB	149	* to finish any radio register access. */
ef1a628d MB	150	b43_read32(dev, B43_MMIO_MACCTL);
	151	udelay(10);
	152	}
	153
	154	void b43_radio_unlock(struct b43_wldev *dev)
	155	{
	156	u32 macctl;
	157
591f3dc2 MB	158	#if B43_DEBUG
	159	B43_WARN_ON(!dev->phy.radio_locked);
	160	dev->phy.radio_locked = 0;
	161	#endif
	162
ef1a628d MB	163	/* Commit any write */
	164	b43_read16(dev, B43_MMIO_PHY_VER);
	165	/* unlock */
	166	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	167	macctl &= ~B43_MACCTL_RADIOLOCK;
	168	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	169	}
	170
	171	void b43_phy_lock(struct b43_wldev *dev)
	172	{
	173	#if B43_DEBUG
	174	B43_WARN_ON(dev->phy.phy_locked);
	175	dev->phy.phy_locked = 1;
	176	#endif
21d889d4	177	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	178
05c914fe	179	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	180	b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
	181	}
	182
	183	void b43_phy_unlock(struct b43_wldev *dev)
	184	{
	185	#if B43_DEBUG
	186	B43_WARN_ON(!dev->phy.phy_locked);
	187	dev->phy.phy_locked = 0;
	188	#endif
21d889d4	189	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	190
05c914fe	191	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	192	b43_power_saving_ctl_bits(dev, 0);
	193	}
	194
d10d0e57 MB	195	static inline void assert_mac_suspended(struct b43_wldev *dev)
	196	{
	197	if (!B43_DEBUG)
	198	return;
	199	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	200	(dev->mac_suspended <= 0)) {
	201	b43dbg(dev->wl, "PHY/RADIO register access with "
	202	"enabled MAC.\n");
	203	dump_stack();
	204	}
	205	}
	206
ef1a628d MB	207	u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	208	{
d10d0e57	209	assert_mac_suspended(dev);
ef1a628d MB	210	return dev->phy.ops->radio_read(dev, reg);
	211	}
	212
	213	void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
	214	{
d10d0e57	215	assert_mac_suspended(dev);
ef1a628d MB	216	dev->phy.ops->radio_write(dev, reg, value);
	217	}
	218
	219	void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
	220	{
	221	b43_radio_write16(dev, offset,
	222	b43_radio_read16(dev, offset) & mask);
	223	}
	224
	225	void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
	226	{
	227	b43_radio_write16(dev, offset,
	228	b43_radio_read16(dev, offset) \| set);
	229	}
	230
	231	void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	232	{
	233	b43_radio_write16(dev, offset,
	234	(b43_radio_read16(dev, offset) & mask) \| set);
	235	}
	236
	237	u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
	238	{
d10d0e57	239	assert_mac_suspended(dev);
15518080	240	dev->phy.writes_counter = 0;
ef1a628d MB	241	return dev->phy.ops->phy_read(dev, reg);
	242	}
	243
	244	void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
	245	{
d10d0e57	246	assert_mac_suspended(dev);
ef1a628d	247	dev->phy.ops->phy_write(dev, reg, value);
15518080 RM	248	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
	249	b43_read16(dev, B43_MMIO_PHY_VER);
	250	dev->phy.writes_counter = 0;
	251	}
ef1a628d MB	252	}
ef1a628d MB	253
738f0f43 GS	254	void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
	255	{
	256	assert_mac_suspended(dev);
	257	dev->phy.ops->phy_write(dev, destreg,
	258	dev->phy.ops->phy_read(dev, srcreg));
	259	}
	260
ef1a628d MB	261	void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
ef1a628d MB	262	{
68ec5329 GS	263	if (dev->phy.ops->phy_maskset) {
	264	assert_mac_suspended(dev);
	265	dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	266	} else {
	267	b43_phy_write(dev, offset,
	268	b43_phy_read(dev, offset) & mask);
	269	}
ef1a628d MB	270	}
	271
	272	void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
	273	{
68ec5329 GS	274	if (dev->phy.ops->phy_maskset) {
	275	assert_mac_suspended(dev);
	276	dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	277	} else {
	278	b43_phy_write(dev, offset,
	279	b43_phy_read(dev, offset) \| set);
	280	}
ef1a628d MB	281	}
	282
	283	void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	284	{
68ec5329 GS	285	if (dev->phy.ops->phy_maskset) {
	286	assert_mac_suspended(dev);
	287	dev->phy.ops->phy_maskset(dev, offset, mask, set);
	288	} else {
	289	b43_phy_write(dev, offset,
	290	(b43_phy_read(dev, offset) & mask) \| set);
	291	}
ef1a628d MB	292	}
	293
	294	int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
	295	{
	296	struct b43_phy *phy = &(dev->phy);
	297	u16 channelcookie, savedcookie;
	298	int err;
	299
	300	if (new_channel == B43_DEFAULT_CHANNEL)
	301	new_channel = phy->ops->get_default_chan(dev);
	302
	303	/* First we set the channel radio code to prevent the
	304	* firmware from sending ghost packets.
	305	*/
	306	channelcookie = new_channel;
	307	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
106cb09a RM	308	channelcookie \|= B43_SHM_SH_CHAN_5GHZ;
	309	/* FIXME: set 40Mhz flag if required */
	310	if (0)
	311	channelcookie \|= B43_SHM_SH_CHAN_40MHZ;
ef1a628d MB	312	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	313	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
	314
	315	/* Now try to switch the PHY hardware channel. */
	316	err = phy->ops->switch_channel(dev, new_channel);
	317	if (err)
	318	goto err_restore_cookie;
	319
	320	dev->phy.channel = new_channel;
	321	/* Wait for the radio to tune to the channel and stabilize. */
	322	msleep(8);
	323
	324	return 0;
	325
	326	err_restore_cookie:
	327	b43_shm_write16(dev, B43_SHM_SHARED,
	328	B43_SHM_SH_CHAN, savedcookie);
	329
	330	return err;
	331	}
	332
19d337df	333	void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
ef1a628d MB	334	{
	335	struct b43_phy *phy = &dev->phy;
	336
b929ecf7	337	b43_mac_suspend(dev);
19d337df JB	338	phy->ops->software_rfkill(dev, blocked);
19d337df JB	339	phy->radio_on = !blocked;
b929ecf7	340	b43_mac_enable(dev);
ef1a628d	341	}
18c8adeb MB	342
	343	/**
	344	* b43_phy_txpower_adjust_work - TX power workqueue.
	345	*
	346	* Workqueue for updating the TX power parameters in hardware.
	347	*/
	348	void b43_phy_txpower_adjust_work(struct work_struct *work)
	349	{
	350	struct b43_wl *wl = container_of(work, struct b43_wl,
	351	txpower_adjust_work);
	352	struct b43_wldev *dev;
	353
	354	mutex_lock(&wl->mutex);
	355	dev = wl->current_dev;
	356
	357	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
	358	dev->phy.ops->adjust_txpower(dev);
	359
	360	mutex_unlock(&wl->mutex);
	361	}
	362
18c8adeb MB	363	void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
	364	{
	365	struct b43_phy *phy = &dev->phy;
	366	unsigned long now = jiffies;
	367	enum b43_txpwr_result result;
	368
	369	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
	370	/* Check if it's time for a TXpower check. */
	371	if (time_before(now, phy->next_txpwr_check_time))
	372	return; /* Not yet */
	373	}
	374	/* The next check will be needed in two seconds, or later. */
	375	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
	376
79d2232f RM	377	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
79d2232f RM	378	(dev->dev->board_type == SSB_BOARD_BU4306))
18c8adeb MB	379	return; /* No software txpower adjustment needed */
	380
	381	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	382	if (result == B43_TXPWR_RES_DONE)
	383	return; /* We are done. */
	384	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	385	B43_WARN_ON(phy->ops->adjust_txpower == NULL);
	386
	387	/* We must adjust the transmission power in hardware.
	388	* Schedule b43_phy_txpower_adjust_work(). */
42935eca	389	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
18c8adeb MB	390	}
	391
	392	int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
	393	{
	394	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	395	unsigned int a, b, c, d;
	396	unsigned int average;
	397	u32 tmp;
	398
	399	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	400	a = tmp & 0xFF;
	401	b = (tmp >> 8) & 0xFF;
	402	c = (tmp >> 16) & 0xFF;
	403	d = (tmp >> 24) & 0xFF;
	404	if (a == 0 \|\| a == B43_TSSI_MAX \|\|
	405	b == 0 \|\| b == B43_TSSI_MAX \|\|
	406	c == 0 \|\| c == B43_TSSI_MAX \|\|
	407	d == 0 \|\| d == B43_TSSI_MAX)
	408	return -ENOENT;
	409	/* The values are OK. Clear them. */
	410	tmp = B43_TSSI_MAX \| (B43_TSSI_MAX << 8) \|
	411	(B43_TSSI_MAX << 16) \| (B43_TSSI_MAX << 24);
	412	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
	413
	414	if (is_ofdm) {
	415	a = (a + 32) & 0x3F;
	416	b = (b + 32) & 0x3F;
	417	c = (c + 32) & 0x3F;
	418	d = (d + 32) & 0x3F;
	419	}
	420
	421	/* Get the average of the values with 0.5 added to each value. */
	422	average = (a + b + c + d + 2) / 4;
	423	if (is_ofdm) {
	424	/* Adjust for CCK-boost */
	425	if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
	426	& B43_HF_CCKBOOST)
	427	average = (average >= 13) ? (average - 13) : 0;
	428	}
	429
	430	return average;
	431	}
cb24f57f MB	432
	433	void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
	434	{
	435	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
	436	}
98650454	437
abc1f7cd RM	438
	439	bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
	440	{
	441	return (channel_type == NL80211_CHAN_HT40MINUS \|\|
	442	channel_type == NL80211_CHAN_HT40PLUS);
	443	}
	444
6f98e62a	445	/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
98650454 RM	446	struct b43_c32 b43_cordic(int theta)
98650454 RM	447	{
5b4bc649 JP	448	static const u32 arctg[] = {
	449	2949120, 1740967, 919879, 466945, 234379, 117304,
	450	58666, 29335, 14668, 7334, 3667, 1833,
	451	917, 458, 229, 115, 57, 29,
	452	};
6f98e62a RM	453	u8 i;
	454	s32 tmp;
	455	s8 signx = 1;
	456	u32 angle = 0;
98650454 RM	457	struct b43_c32 ret = { .i = 39797, .q = 0, };
98650454 RM	458
6f98e62a RM	459	while (theta > (180 << 16))
	460	theta -= (360 << 16);
	461	while (theta < -(180 << 16))
	462	theta += (360 << 16);
98650454	463
6f98e62a RM	464	if (theta > (90 << 16)) {
6f98e62a RM	465	theta -= (180 << 16);
98650454	466	signx = -1;
6f98e62a RM	467	} else if (theta < -(90 << 16)) {
6f98e62a RM	468	theta += (180 << 16);
98650454 RM	469	signx = -1;
	470	}
	471
	472	for (i = 0; i <= 17; i++) {
	473	if (theta > angle) {
	474	tmp = ret.i - (ret.q >> i);
	475	ret.q += ret.i >> i;
	476	ret.i = tmp;
	477	angle += arctg[i];
	478	} else {
	479	tmp = ret.i + (ret.q >> i);
	480	ret.q -= ret.i >> i;
	481	ret.i = tmp;
	482	angle -= arctg[i];
	483	}
	484	}
	485
	486	ret.i *= signx;
	487	ret.q *= signx;
	488
	489	return ret;
	490	}