[deliverable/linux.git] / drivers / net / wireless / b43 / phy_common.c

/*

  Broadcom B43 wireless driver
  Common PHY routines

  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include "phy_common.h"
#include "phy_g.h"
#include "phy_a.h"
#include "phy_n.h"
#include "phy_lp.h"
#include "phy_ht.h"
#include "phy_lcn.h"
#include "b43.h"
#include "main.h"


int b43_phy_allocate(struct b43_wldev *dev)
{
	struct b43_phy *phy = &(dev->phy);
	int err;

	phy->ops = NULL;

	switch (phy->type) {
	case B43_PHYTYPE_A:
		phy->ops = &b43_phyops_a;
		break;
	case B43_PHYTYPE_G:
		phy->ops = &b43_phyops_g;
		break;
	case B43_PHYTYPE_N:
#ifdef CONFIG_B43_PHY_N
		phy->ops = &b43_phyops_n;
#endif
		break;
	case B43_PHYTYPE_LP:
#ifdef CONFIG_B43_PHY_LP
		phy->ops = &b43_phyops_lp;
#endif
		break;
	case B43_PHYTYPE_HT:
#ifdef CONFIG_B43_PHY_HT
		phy->ops = &b43_phyops_ht;
#endif
		break;
	case B43_PHYTYPE_LCN:
#ifdef CONFIG_B43_PHY_LCN
		phy->ops = &b43_phyops_lcn;
#endif
		break;
	}
	if (B43_WARN_ON(!phy->ops))
		return -ENODEV;

	err = phy->ops->allocate(dev);
	if (err)
		phy->ops = NULL;

	return err;
}

void b43_phy_free(struct b43_wldev *dev)
{
	dev->phy.ops->free(dev);
	dev->phy.ops = NULL;
}

int b43_phy_init(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	const struct b43_phy_operations *ops = phy->ops;
	int err;

	phy->channel = ops->get_default_chan(dev);

	phy->ops->switch_analog(dev, true);
	b43_software_rfkill(dev, false);

	err = ops->init(dev);
	if (err) {
		b43err(dev->wl, "PHY init failed\n");
		goto err_block_rf;
	}
	phy->do_full_init = false;

	/* Make sure to switch hardware and firmware (SHM) to
	 * the default channel. */
	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	if (err) {
		b43err(dev->wl, "PHY init: Channel switch to default failed\n");
		goto err_phy_exit;
	}

	return 0;

err_phy_exit:
	phy->do_full_init = true;
	if (ops->exit)
		ops->exit(dev);
err_block_rf:
	b43_software_rfkill(dev, true);

	return err;
}

void b43_phy_exit(struct b43_wldev *dev)
{
	const struct b43_phy_operations *ops = dev->phy.ops;

	b43_software_rfkill(dev, true);
	dev->phy.do_full_init = true;
	if (ops->exit)
		ops->exit(dev);
}

bool b43_has_hardware_pctl(struct b43_wldev *dev)
{
	if (!dev->phy.hardware_power_control)
		return false;
	if (!dev->phy.ops->supports_hwpctl)
		return false;
	return dev->phy.ops->supports_hwpctl(dev);
}

void b43_radio_lock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(dev->phy.radio_locked);
	dev->phy.radio_locked = true;
#endif

	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl |= B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Commit the write and wait for the firmware
	 * to finish any radio register access. */
	b43_read32(dev, B43_MMIO_MACCTL);
	udelay(10);
}

void b43_radio_unlock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(!dev->phy.radio_locked);
	dev->phy.radio_locked = false;
#endif

	/* Commit any write */
	b43_read16(dev, B43_MMIO_PHY_VER);
	/* unlock */
	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl &= ~B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
}

void b43_phy_lock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(dev->phy.phy_locked);
	dev->phy.phy_locked = true;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
}

void b43_phy_unlock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(!dev->phy.phy_locked);
	dev->phy.phy_locked = false;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, 0);
}

static inline void assert_mac_suspended(struct b43_wldev *dev)
{
	if (!B43_DEBUG)
		return;
	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	    (dev->mac_suspended <= 0)) {
		b43dbg(dev->wl, "PHY/RADIO register access with "
		       "enabled MAC.\n");
		dump_stack();
	}
}

u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	return dev->phy.ops->radio_read(dev, reg);
}

void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->radio_write(dev, reg, value);
}

void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) & mask);
}

void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) | set);
}

void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	b43_radio_write16(dev, offset,
			  (b43_radio_read16(dev, offset) & mask) | set);
}

bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
			  u16 value, int delay, int timeout)
{
	u16 val;
	int i;

	for (i = 0; i < timeout; i += delay) {
		val = b43_radio_read(dev, offset);
		if ((val & mask) == value)
			return true;
		udelay(delay);
	}
	return false;
}

u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	dev->phy.writes_counter = 0;
	return dev->phy.ops->phy_read(dev, reg);
}

void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, reg, value);
	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
		b43_read16(dev, B43_MMIO_PHY_VER);
		dev->phy.writes_counter = 0;
	}
}

void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, destreg,
		dev->phy.ops->phy_read(dev, srcreg));
}

void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) & mask);
	}
}

void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) | set);
	}
}

void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, set);
	} else {
		b43_phy_write(dev, offset,
			      (b43_phy_read(dev, offset) & mask) | set);
	}
}

void b43_phy_put_into_reset(struct b43_wldev *dev)
{
	u32 tmp;

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~B43_BCMA_IOCTL_GMODE;
		tmp |= B43_BCMA_IOCTL_PHY_RESET;
		tmp |= BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);

		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~B43_TMSLOW_GMODE;
		tmp |= B43_TMSLOW_PHYRESET;
		tmp |= SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		usleep_range(1000, 2000);

		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		usleep_range(1000, 2000);

		break;
#endif
	}
}

void b43_phy_take_out_of_reset(struct b43_wldev *dev)
{
	u32 tmp;

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		/* Unset reset bit (with forcing clock) */
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
		tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
		tmp |= BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);

		/* Do not force clock anymore */
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~BCMA_IOCTL_FGC;
		tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		/* Unset reset bit (with forcing clock) */
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~B43_TMSLOW_PHYRESET;
		tmp &= ~B43_TMSLOW_PHYCLKEN;
		tmp |= SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
		usleep_range(1000, 2000);

		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~SSB_TMSLOW_FGC;
		tmp |= B43_TMSLOW_PHYCLKEN;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
		usleep_range(1000, 2000);
		break;
#endif
	}
}

int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
{
	struct b43_phy *phy = &(dev->phy);
	u16 channelcookie, savedcookie;
	int err;

	/* First we set the channel radio code to prevent the
	 * firmware from sending ghost packets.
	 */
	channelcookie = new_channel;
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		channelcookie |= B43_SHM_SH_CHAN_5GHZ;
	/* FIXME: set 40Mhz flag if required */
	if (0)
		channelcookie |= B43_SHM_SH_CHAN_40MHZ;
	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);

	/* Now try to switch the PHY hardware channel. */
	err = phy->ops->switch_channel(dev, new_channel);
	if (err)
		goto err_restore_cookie;

	dev->phy.channel = new_channel;
	/* Wait for the radio to tune to the channel and stabilize. */
	msleep(8);

	return 0;

err_restore_cookie:
	b43_shm_write16(dev, B43_SHM_SHARED,
			B43_SHM_SH_CHAN, savedcookie);

	return err;
}

void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
{
	struct b43_phy *phy = &dev->phy;

	b43_mac_suspend(dev);
	phy->ops->software_rfkill(dev, blocked);
	phy->radio_on = !blocked;
	b43_mac_enable(dev);
}

/**
 * b43_phy_txpower_adjust_work - TX power workqueue.
 *
 * Workqueue for updating the TX power parameters in hardware.
 */
void b43_phy_txpower_adjust_work(struct work_struct *work)
{
	struct b43_wl *wl = container_of(work, struct b43_wl,
					 txpower_adjust_work);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
		dev->phy.ops->adjust_txpower(dev);

	mutex_unlock(&wl->mutex);
}

void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
{
	struct b43_phy *phy = &dev->phy;
	unsigned long now = jiffies;
	enum b43_txpwr_result result;

	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
		/* Check if it's time for a TXpower check. */
		if (time_before(now, phy->next_txpwr_check_time))
			return; /* Not yet */
	}
	/* The next check will be needed in two seconds, or later. */
	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));

	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
	    (dev->dev->board_type == SSB_BOARD_BU4306))
		return; /* No software txpower adjustment needed */

	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	if (result == B43_TXPWR_RES_DONE)
		return; /* We are done. */
	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	B43_WARN_ON(phy->ops->adjust_txpower == NULL);

	/* We must adjust the transmission power in hardware.
	 * Schedule b43_phy_txpower_adjust_work(). */
	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
}

int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
{
	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	unsigned int a, b, c, d;
	unsigned int average;
	u32 tmp;

	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	a = tmp & 0xFF;
	b = (tmp >> 8) & 0xFF;
	c = (tmp >> 16) & 0xFF;
	d = (tmp >> 24) & 0xFF;
	if (a == 0 || a == B43_TSSI_MAX ||
	    b == 0 || b == B43_TSSI_MAX ||
	    c == 0 || c == B43_TSSI_MAX ||
	    d == 0 || d == B43_TSSI_MAX)
		return -ENOENT;
	/* The values are OK. Clear them. */
	tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
	      (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);

	if (is_ofdm) {
		a = (a + 32) & 0x3F;
		b = (b + 32) & 0x3F;
		c = (c + 32) & 0x3F;
		d = (d + 32) & 0x3F;
	}

	/* Get the average of the values with 0.5 added to each value. */
	average = (a + b + c + d + 2) / 4;
	if (is_ofdm) {
		/* Adjust for CCK-boost */
		if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
		    & B43_HF_CCKBOOST)
			average = (average >= 13) ? (average - 13) : 0;
	}

	return average;
}

void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
{
	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
}


bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
{
	return (channel_type == NL80211_CHAN_HT40MINUS ||
		channel_type == NL80211_CHAN_HT40PLUS);
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
void b43_phy_force_clock(struct b43_wldev *dev, bool force)
{
	u32 tmp;

	WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
		dev->phy.type != B43_PHYTYPE_HT);

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		if (force)
			tmp |= BCMA_IOCTL_FGC;
		else
			tmp &= ~BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		if (force)
			tmp |= SSB_TMSLOW_FGC;
		else
			tmp &= ~SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		break;
#endif
	}
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
struct b43_c32 b43_cordic(int theta)
{
	static const u32 arctg[] = {
		2949120, 1740967, 919879, 466945, 234379, 117304,
		  58666,   29335,  14668,   7334,   3667,   1833,
		    917,     458,    229,    115,     57,     29,
	};
	u8 i;
	s32 tmp;
	s8 signx = 1;
	u32 angle = 0;
	struct b43_c32 ret = { .i = 39797, .q = 0, };

	while (theta > (180 << 16))
		theta -= (360 << 16);
	while (theta < -(180 << 16))
		theta += (360 << 16);

	if (theta > (90 << 16)) {
		theta -= (180 << 16);
		signx = -1;
	} else if (theta < -(90 << 16)) {
		theta += (180 << 16);
		signx = -1;
	}

	for (i = 0; i <= 17; i++) {
		if (theta > angle) {
			tmp = ret.i - (ret.q >> i);
			ret.q += ret.i >> i;
			ret.i = tmp;
			angle += arctg[i];
		} else {
			tmp = ret.i + (ret.q >> i);
			ret.q -= ret.i >> i;
			ret.i = tmp;
			angle -= arctg[i];
		}
	}

	ret.i *= signx;
	ret.q *= signx;

	return ret;
}
Commit	Line	Data
ef1a628d MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	Common PHY routines
	5
	6	Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
	7	Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98	8	Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
ef1a628d MB	9	Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
	10	Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; see the file COPYING. If not, write to
	24	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	25	Boston, MA 02110-1301, USA.
	26
	27	*/
	28
	29	#include "phy_common.h"
	30	#include "phy_g.h"
	31	#include "phy_a.h"
3d0da751	32	#include "phy_n.h"
e63e4363	33	#include "phy_lp.h"
d7520b1d	34	#include "phy_ht.h"
58eb7ff3	35	#include "phy_lcn.h"
ef1a628d MB	36	#include "b43.h"
	37	#include "main.h"
	38
	39
fb11137a	40	int b43_phy_allocate(struct b43_wldev *dev)
ef1a628d MB	41	{
	42	struct b43_phy *phy = &(dev->phy);
	43	int err;
	44
	45	phy->ops = NULL;
	46
	47	switch (phy->type) {
	48	case B43_PHYTYPE_A:
	49	phy->ops = &b43_phyops_a;
	50	break;
	51	case B43_PHYTYPE_G:
	52	phy->ops = &b43_phyops_g;
	53	break;
	54	case B43_PHYTYPE_N:
692d2c0f	55	#ifdef CONFIG_B43_PHY_N
ef1a628d MB	56	phy->ops = &b43_phyops_n;
	57	#endif
	58	break;
	59	case B43_PHYTYPE_LP:
e63e4363 MB	60	#ifdef CONFIG_B43_PHY_LP
e63e4363 MB	61	phy->ops = &b43_phyops_lp;
d7520b1d RM	62	#endif
	63	break;
	64	case B43_PHYTYPE_HT:
	65	#ifdef CONFIG_B43_PHY_HT
	66	phy->ops = &b43_phyops_ht;
58eb7ff3 RM	67	#endif
	68	break;
	69	case B43_PHYTYPE_LCN:
	70	#ifdef CONFIG_B43_PHY_LCN
	71	phy->ops = &b43_phyops_lcn;
e63e4363	72	#endif
ef1a628d MB	73	break;
	74	}
	75	if (B43_WARN_ON(!phy->ops))
	76	return -ENODEV;
	77
	78	err = phy->ops->allocate(dev);
	79	if (err)
	80	phy->ops = NULL;
	81
	82	return err;
	83	}
	84
fb11137a MB	85	void b43_phy_free(struct b43_wldev *dev)
	86	{
	87	dev->phy.ops->free(dev);
	88	dev->phy.ops = NULL;
	89	}
	90
ef1a628d MB	91	int b43_phy_init(struct b43_wldev *dev)
	92	{
	93	struct b43_phy *phy = &dev->phy;
	94	const struct b43_phy_operations *ops = phy->ops;
	95	int err;
	96
	97	phy->channel = ops->get_default_chan(dev);
	98
7a8af8cf	99	phy->ops->switch_analog(dev, true);
a6316e28	100	b43_software_rfkill(dev, false);
09951ad4	101
ef1a628d MB	102	err = ops->init(dev);
	103	if (err) {
	104	b43err(dev->wl, "PHY init failed\n");
	105	goto err_block_rf;
	106	}
09951ad4 RM	107	phy->do_full_init = false;
09951ad4 RM	108
ef1a628d MB	109	/* Make sure to switch hardware and firmware (SHM) to
	110	* the default channel. */
	111	err = b43_switch_channel(dev, ops->get_default_chan(dev));
	112	if (err) {
	113	b43err(dev->wl, "PHY init: Channel switch to default failed\n");
	114	goto err_phy_exit;
	115	}
	116
	117	return 0;
	118
	119	err_phy_exit:
09951ad4	120	phy->do_full_init = true;
ef1a628d MB	121	if (ops->exit)
	122	ops->exit(dev);
	123	err_block_rf:
a6316e28	124	b43_software_rfkill(dev, true);
ef1a628d MB	125
	126	return err;
	127	}
	128
	129	void b43_phy_exit(struct b43_wldev *dev)
	130	{
	131	const struct b43_phy_operations *ops = dev->phy.ops;
	132
a6316e28	133	b43_software_rfkill(dev, true);
09951ad4	134	dev->phy.do_full_init = true;
ef1a628d MB	135	if (ops->exit)
	136	ops->exit(dev);
	137	}
	138
	139	bool b43_has_hardware_pctl(struct b43_wldev *dev)
	140	{
	141	if (!dev->phy.hardware_power_control)
1a2b250b	142	return false;
ef1a628d	143	if (!dev->phy.ops->supports_hwpctl)
1a2b250b	144	return false;
ef1a628d MB	145	return dev->phy.ops->supports_hwpctl(dev);
	146	}
	147
	148	void b43_radio_lock(struct b43_wldev *dev)
	149	{
	150	u32 macctl;
	151
591f3dc2 MB	152	#if B43_DEBUG
591f3dc2 MB	153	B43_WARN_ON(dev->phy.radio_locked);
3db1cd5c	154	dev->phy.radio_locked = true;
591f3dc2 MB	155	#endif
591f3dc2 MB	156
ef1a628d	157	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	158	macctl \|= B43_MACCTL_RADIOLOCK;
ef1a628d MB	159	b43_write32(dev, B43_MMIO_MACCTL, macctl);
591f3dc2 MB	160	/* Commit the write and wait for the firmware
591f3dc2 MB	161	* to finish any radio register access. */
ef1a628d MB	162	b43_read32(dev, B43_MMIO_MACCTL);
	163	udelay(10);
	164	}
	165
	166	void b43_radio_unlock(struct b43_wldev *dev)
	167	{
	168	u32 macctl;
	169
591f3dc2 MB	170	#if B43_DEBUG
591f3dc2 MB	171	B43_WARN_ON(!dev->phy.radio_locked);
3db1cd5c	172	dev->phy.radio_locked = false;
591f3dc2 MB	173	#endif
591f3dc2 MB	174
ef1a628d MB	175	/* Commit any write */
	176	b43_read16(dev, B43_MMIO_PHY_VER);
	177	/* unlock */
	178	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	179	macctl &= ~B43_MACCTL_RADIOLOCK;
	180	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	181	}
	182
	183	void b43_phy_lock(struct b43_wldev *dev)
	184	{
	185	#if B43_DEBUG
	186	B43_WARN_ON(dev->phy.phy_locked);
3db1cd5c	187	dev->phy.phy_locked = true;
ef1a628d	188	#endif
21d889d4	189	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	190
05c914fe	191	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	192	b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
	193	}
	194
	195	void b43_phy_unlock(struct b43_wldev *dev)
	196	{
	197	#if B43_DEBUG
	198	B43_WARN_ON(!dev->phy.phy_locked);
3db1cd5c	199	dev->phy.phy_locked = false;
ef1a628d	200	#endif
21d889d4	201	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	202
05c914fe	203	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	204	b43_power_saving_ctl_bits(dev, 0);
	205	}
	206
d10d0e57 MB	207	static inline void assert_mac_suspended(struct b43_wldev *dev)
	208	{
	209	if (!B43_DEBUG)
	210	return;
	211	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	212	(dev->mac_suspended <= 0)) {
	213	b43dbg(dev->wl, "PHY/RADIO register access with "
	214	"enabled MAC.\n");
	215	dump_stack();
	216	}
	217	}
	218
ef1a628d MB	219	u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	220	{
d10d0e57	221	assert_mac_suspended(dev);
ef1a628d MB	222	return dev->phy.ops->radio_read(dev, reg);
	223	}
	224
	225	void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
	226	{
d10d0e57	227	assert_mac_suspended(dev);
ef1a628d MB	228	dev->phy.ops->radio_write(dev, reg, value);
	229	}
	230
	231	void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
	232	{
	233	b43_radio_write16(dev, offset,
	234	b43_radio_read16(dev, offset) & mask);
	235	}
	236
	237	void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
	238	{
	239	b43_radio_write16(dev, offset,
	240	b43_radio_read16(dev, offset) \| set);
	241	}
	242
	243	void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	244	{
	245	b43_radio_write16(dev, offset,
	246	(b43_radio_read16(dev, offset) & mask) \| set);
	247	}
	248
0f941777 RM	249	bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
	250	u16 value, int delay, int timeout)
	251	{
	252	u16 val;
	253	int i;
	254
	255	for (i = 0; i < timeout; i += delay) {
	256	val = b43_radio_read(dev, offset);
	257	if ((val & mask) == value)
	258	return true;
	259	udelay(delay);
	260	}
	261	return false;
	262	}
	263
ef1a628d MB	264	u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	265	{
d10d0e57	266	assert_mac_suspended(dev);
15518080	267	dev->phy.writes_counter = 0;
ef1a628d MB	268	return dev->phy.ops->phy_read(dev, reg);
	269	}
	270
	271	void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
	272	{
d10d0e57	273	assert_mac_suspended(dev);
ef1a628d	274	dev->phy.ops->phy_write(dev, reg, value);
15518080 RM	275	if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
	276	b43_read16(dev, B43_MMIO_PHY_VER);
	277	dev->phy.writes_counter = 0;
	278	}
ef1a628d MB	279	}
ef1a628d MB	280
738f0f43 GS	281	void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
	282	{
	283	assert_mac_suspended(dev);
	284	dev->phy.ops->phy_write(dev, destreg,
	285	dev->phy.ops->phy_read(dev, srcreg));
	286	}
	287
ef1a628d MB	288	void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
ef1a628d MB	289	{
68ec5329 GS	290	if (dev->phy.ops->phy_maskset) {
	291	assert_mac_suspended(dev);
	292	dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	293	} else {
	294	b43_phy_write(dev, offset,
	295	b43_phy_read(dev, offset) & mask);
	296	}
ef1a628d MB	297	}
	298
	299	void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
	300	{
68ec5329 GS	301	if (dev->phy.ops->phy_maskset) {
	302	assert_mac_suspended(dev);
	303	dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	304	} else {
	305	b43_phy_write(dev, offset,
	306	b43_phy_read(dev, offset) \| set);
	307	}
ef1a628d MB	308	}
	309
	310	void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	311	{
68ec5329 GS	312	if (dev->phy.ops->phy_maskset) {
	313	assert_mac_suspended(dev);
	314	dev->phy.ops->phy_maskset(dev, offset, mask, set);
	315	} else {
	316	b43_phy_write(dev, offset,
	317	(b43_phy_read(dev, offset) & mask) \| set);
	318	}
ef1a628d MB	319	}
ef1a628d MB	320
b60c3c2f RM	321	void b43_phy_put_into_reset(struct b43_wldev *dev)
b60c3c2f RM	322	{
b60c3c2f	323	u32 tmp;
b60c3c2f RM	324
	325	switch (dev->dev->bus_type) {
	326	#ifdef CONFIG_B43_BCMA
	327	case B43_BUS_BCMA:
50c1b59e RM	328	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	329	tmp &= ~B43_BCMA_IOCTL_GMODE;
	330	tmp \|= B43_BCMA_IOCTL_PHY_RESET;
	331	tmp \|= BCMA_IOCTL_FGC;
	332	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	333	udelay(1);
	334
	335	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	336	tmp &= ~BCMA_IOCTL_FGC;
	337	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	338	udelay(1);
b60c3c2f RM	339	break;
	340	#endif
	341	#ifdef CONFIG_B43_SSB
	342	case B43_BUS_SSB:
	343	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	344	tmp &= ~B43_TMSLOW_GMODE;
	345	tmp \|= B43_TMSLOW_PHYRESET;
	346	tmp \|= SSB_TMSLOW_FGC;
	347	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
50c1b59e	348	usleep_range(1000, 2000);
b60c3c2f RM	349
	350	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	351	tmp &= ~SSB_TMSLOW_FGC;
b60c3c2f	352	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
50c1b59e	353	usleep_range(1000, 2000);
b60c3c2f RM	354
	355	break;
	356	#endif
	357	}
	358	}
	359
50c1b59e RM	360	void b43_phy_take_out_of_reset(struct b43_wldev *dev)
	361	{
	362	u32 tmp;
	363
	364	switch (dev->dev->bus_type) {
	365	#ifdef CONFIG_B43_BCMA
	366	case B43_BUS_BCMA:
	367	/* Unset reset bit (with forcing clock) */
	368	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	369	tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
	370	tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
	371	tmp \|= BCMA_IOCTL_FGC;
	372	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	373	udelay(1);
	374
	375	/* Do not force clock anymore */
	376	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	377	tmp &= ~BCMA_IOCTL_FGC;
	378	tmp \|= B43_BCMA_IOCTL_PHY_CLKEN;
	379	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	380	udelay(1);
	381	break;
	382	#endif
	383	#ifdef CONFIG_B43_SSB
	384	case B43_BUS_SSB:
	385	/* Unset reset bit (with forcing clock) */
	386	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	387	tmp &= ~B43_TMSLOW_PHYRESET;
	388	tmp &= ~B43_TMSLOW_PHYCLKEN;
	389	tmp \|= SSB_TMSLOW_FGC;
	390	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	391	ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
	392	usleep_range(1000, 2000);
	393
	394	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	395	tmp &= ~SSB_TMSLOW_FGC;
	396	tmp \|= B43_TMSLOW_PHYCLKEN;
	397	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	398	ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
	399	usleep_range(1000, 2000);
	400	break;
	401	#endif
	402	}
	403	}
	404
ef1a628d MB	405	int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
	406	{
	407	struct b43_phy *phy = &(dev->phy);
	408	u16 channelcookie, savedcookie;
	409	int err;
	410
ef1a628d MB	411	/* First we set the channel radio code to prevent the
	412	* firmware from sending ghost packets.
	413	*/
	414	channelcookie = new_channel;
	415	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
106cb09a RM	416	channelcookie \|= B43_SHM_SH_CHAN_5GHZ;
	417	/* FIXME: set 40Mhz flag if required */
	418	if (0)
	419	channelcookie \|= B43_SHM_SH_CHAN_40MHZ;
ef1a628d MB	420	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	421	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
	422
	423	/* Now try to switch the PHY hardware channel. */
	424	err = phy->ops->switch_channel(dev, new_channel);
	425	if (err)
	426	goto err_restore_cookie;
	427
	428	dev->phy.channel = new_channel;
	429	/* Wait for the radio to tune to the channel and stabilize. */
	430	msleep(8);
	431
	432	return 0;
	433
	434	err_restore_cookie:
	435	b43_shm_write16(dev, B43_SHM_SHARED,
	436	B43_SHM_SH_CHAN, savedcookie);
	437
	438	return err;
	439	}
	440
19d337df	441	void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
ef1a628d MB	442	{
	443	struct b43_phy *phy = &dev->phy;
	444
b929ecf7	445	b43_mac_suspend(dev);
19d337df JB	446	phy->ops->software_rfkill(dev, blocked);
19d337df JB	447	phy->radio_on = !blocked;
b929ecf7	448	b43_mac_enable(dev);
ef1a628d	449	}
18c8adeb MB	450
	451	/**
	452	* b43_phy_txpower_adjust_work - TX power workqueue.
	453	*
	454	* Workqueue for updating the TX power parameters in hardware.
	455	*/
	456	void b43_phy_txpower_adjust_work(struct work_struct *work)
	457	{
	458	struct b43_wl *wl = container_of(work, struct b43_wl,
	459	txpower_adjust_work);
	460	struct b43_wldev *dev;
	461
	462	mutex_lock(&wl->mutex);
	463	dev = wl->current_dev;
	464
	465	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
	466	dev->phy.ops->adjust_txpower(dev);
	467
	468	mutex_unlock(&wl->mutex);
	469	}
	470
18c8adeb MB	471	void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
	472	{
	473	struct b43_phy *phy = &dev->phy;
	474	unsigned long now = jiffies;
	475	enum b43_txpwr_result result;
	476
	477	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
	478	/* Check if it's time for a TXpower check. */
	479	if (time_before(now, phy->next_txpwr_check_time))
	480	return; /* Not yet */
	481	}
	482	/* The next check will be needed in two seconds, or later. */
	483	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
	484
79d2232f RM	485	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
79d2232f RM	486	(dev->dev->board_type == SSB_BOARD_BU4306))
18c8adeb MB	487	return; /* No software txpower adjustment needed */
	488
	489	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	490	if (result == B43_TXPWR_RES_DONE)
	491	return; /* We are done. */
	492	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	493	B43_WARN_ON(phy->ops->adjust_txpower == NULL);
	494
	495	/* We must adjust the transmission power in hardware.
	496	* Schedule b43_phy_txpower_adjust_work(). */
42935eca	497	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
18c8adeb MB	498	}
	499
	500	int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
	501	{
	502	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	503	unsigned int a, b, c, d;
	504	unsigned int average;
	505	u32 tmp;
	506
	507	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	508	a = tmp & 0xFF;
	509	b = (tmp >> 8) & 0xFF;
	510	c = (tmp >> 16) & 0xFF;
	511	d = (tmp >> 24) & 0xFF;
	512	if (a == 0 \|\| a == B43_TSSI_MAX \|\|
	513	b == 0 \|\| b == B43_TSSI_MAX \|\|
	514	c == 0 \|\| c == B43_TSSI_MAX \|\|
	515	d == 0 \|\| d == B43_TSSI_MAX)
	516	return -ENOENT;
	517	/* The values are OK. Clear them. */
	518	tmp = B43_TSSI_MAX \| (B43_TSSI_MAX << 8) \|
	519	(B43_TSSI_MAX << 16) \| (B43_TSSI_MAX << 24);
	520	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
	521
	522	if (is_ofdm) {
	523	a = (a + 32) & 0x3F;
	524	b = (b + 32) & 0x3F;
	525	c = (c + 32) & 0x3F;
	526	d = (d + 32) & 0x3F;
	527	}
	528
	529	/* Get the average of the values with 0.5 added to each value. */
	530	average = (a + b + c + d + 2) / 4;
	531	if (is_ofdm) {
	532	/* Adjust for CCK-boost */
6e6a2cd5	533	if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
18c8adeb MB	534	& B43_HF_CCKBOOST)
	535	average = (average >= 13) ? (average - 13) : 0;
	536	}
	537
	538	return average;
	539	}
cb24f57f MB	540
	541	void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
	542	{
	543	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
	544	}
98650454	545
abc1f7cd RM	546
	547	bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
	548	{
	549	return (channel_type == NL80211_CHAN_HT40MINUS \|\|
	550	channel_type == NL80211_CHAN_HT40PLUS);
	551	}
	552
f6a3e99d RM	553	/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
	554	void b43_phy_force_clock(struct b43_wldev *dev, bool force)
	555	{
	556	u32 tmp;
	557
	558	WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
	559	dev->phy.type != B43_PHYTYPE_HT);
	560
	561	switch (dev->dev->bus_type) {
	562	#ifdef CONFIG_B43_BCMA
	563	case B43_BUS_BCMA:
	564	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	565	if (force)
	566	tmp \|= BCMA_IOCTL_FGC;
	567	else
	568	tmp &= ~BCMA_IOCTL_FGC;
	569	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	570	break;
	571	#endif
	572	#ifdef CONFIG_B43_SSB
	573	case B43_BUS_SSB:
	574	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	575	if (force)
	576	tmp \|= SSB_TMSLOW_FGC;
	577	else
	578	tmp &= ~SSB_TMSLOW_FGC;
	579	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	580	break;
	581	#endif
	582	}
	583	}
	584
6f98e62a	585	/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
98650454 RM	586	struct b43_c32 b43_cordic(int theta)
98650454 RM	587	{
5b4bc649 JP	588	static const u32 arctg[] = {
	589	2949120, 1740967, 919879, 466945, 234379, 117304,
	590	58666, 29335, 14668, 7334, 3667, 1833,
	591	917, 458, 229, 115, 57, 29,
	592	};
6f98e62a RM	593	u8 i;
	594	s32 tmp;
	595	s8 signx = 1;
	596	u32 angle = 0;
98650454 RM	597	struct b43_c32 ret = { .i = 39797, .q = 0, };
98650454 RM	598
6f98e62a RM	599	while (theta > (180 << 16))
	600	theta -= (360 << 16);
	601	while (theta < -(180 << 16))
	602	theta += (360 << 16);
98650454	603
6f98e62a RM	604	if (theta > (90 << 16)) {
6f98e62a RM	605	theta -= (180 << 16);
98650454	606	signx = -1;
6f98e62a RM	607	} else if (theta < -(90 << 16)) {
6f98e62a RM	608	theta += (180 << 16);
98650454 RM	609	signx = -1;
	610	}
	611
	612	for (i = 0; i <= 17; i++) {
	613	if (theta > angle) {
	614	tmp = ret.i - (ret.q >> i);
	615	ret.q += ret.i >> i;
	616	ret.i = tmp;
	617	angle += arctg[i];
	618	} else {
	619	tmp = ret.i + (ret.q >> i);
	620	ret.q -= ret.i >> i;
	621	ret.i = tmp;
	622	angle -= arctg[i];
	623	}
	624	}
	625
	626	ret.i *= signx;
	627	ret.q *= signx;
	628
	629	return ret;
	630	}