[deliverable/linux.git] / drivers / net / wireless / b43 / phy_common.c

/*

  Broadcom B43 wireless driver
  Common PHY routines

  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include "phy_common.h"
#include "phy_g.h"
#include "phy_a.h"
#include "phy_n.h"
#include "phy_lp.h"
#include "phy_ht.h"
#include "phy_lcn.h"
#include "b43.h"
#include "main.h"


int b43_phy_allocate(struct b43_wldev *dev)
{
	struct b43_phy *phy = &(dev->phy);
	int err;

	phy->ops = NULL;

	switch (phy->type) {
	case B43_PHYTYPE_G:
#ifdef CONFIG_B43_PHY_G
		phy->ops = &b43_phyops_g;
#endif
		break;
	case B43_PHYTYPE_N:
#ifdef CONFIG_B43_PHY_N
		phy->ops = &b43_phyops_n;
#endif
		break;
	case B43_PHYTYPE_LP:
#ifdef CONFIG_B43_PHY_LP
		phy->ops = &b43_phyops_lp;
#endif
		break;
	case B43_PHYTYPE_HT:
#ifdef CONFIG_B43_PHY_HT
		phy->ops = &b43_phyops_ht;
#endif
		break;
	case B43_PHYTYPE_LCN:
#ifdef CONFIG_B43_PHY_LCN
		phy->ops = &b43_phyops_lcn;
#endif
		break;
	}
	if (B43_WARN_ON(!phy->ops))
		return -ENODEV;

	err = phy->ops->allocate(dev);
	if (err)
		phy->ops = NULL;

	return err;
}

void b43_phy_free(struct b43_wldev *dev)
{
	dev->phy.ops->free(dev);
	dev->phy.ops = NULL;
}

int b43_phy_init(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	const struct b43_phy_operations *ops = phy->ops;
	int err;

	/* During PHY init we need to use some channel. On the first init this
	 * function is called *before* b43_op_config, so our pointer is NULL.
	 */
	if (!phy->chandef) {
		phy->chandef = &dev->wl->hw->conf.chandef;
		phy->channel = phy->chandef->chan->hw_value;
	}

	phy->ops->switch_analog(dev, true);
	b43_software_rfkill(dev, false);

	err = ops->init(dev);
	if (err) {
		b43err(dev->wl, "PHY init failed\n");
		goto err_block_rf;
	}
	phy->do_full_init = false;

	err = b43_switch_channel(dev, phy->channel);
	if (err) {
		b43err(dev->wl, "PHY init: Channel switch to default failed\n");
		goto err_phy_exit;
	}

	return 0;

err_phy_exit:
	phy->do_full_init = true;
	if (ops->exit)
		ops->exit(dev);
err_block_rf:
	b43_software_rfkill(dev, true);

	return err;
}

void b43_phy_exit(struct b43_wldev *dev)
{
	const struct b43_phy_operations *ops = dev->phy.ops;

	b43_software_rfkill(dev, true);
	dev->phy.do_full_init = true;
	if (ops->exit)
		ops->exit(dev);
}

bool b43_has_hardware_pctl(struct b43_wldev *dev)
{
	if (!dev->phy.hardware_power_control)
		return false;
	if (!dev->phy.ops->supports_hwpctl)
		return false;
	return dev->phy.ops->supports_hwpctl(dev);
}

void b43_radio_lock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(dev->phy.radio_locked);
	dev->phy.radio_locked = true;
#endif

	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl |= B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	/* Commit the write and wait for the firmware
	 * to finish any radio register access. */
	b43_read32(dev, B43_MMIO_MACCTL);
	udelay(10);
}

void b43_radio_unlock(struct b43_wldev *dev)
{
	u32 macctl;

#if B43_DEBUG
	B43_WARN_ON(!dev->phy.radio_locked);
	dev->phy.radio_locked = false;
#endif

	/* Commit any write */
	b43_read16(dev, B43_MMIO_PHY_VER);
	/* unlock */
	macctl = b43_read32(dev, B43_MMIO_MACCTL);
	macctl &= ~B43_MACCTL_RADIOLOCK;
	b43_write32(dev, B43_MMIO_MACCTL, macctl);
}

void b43_phy_lock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(dev->phy.phy_locked);
	dev->phy.phy_locked = true;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
}

void b43_phy_unlock(struct b43_wldev *dev)
{
#if B43_DEBUG
	B43_WARN_ON(!dev->phy.phy_locked);
	dev->phy.phy_locked = false;
#endif
	B43_WARN_ON(dev->dev->core_rev < 3);

	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
		b43_power_saving_ctl_bits(dev, 0);
}

static inline void assert_mac_suspended(struct b43_wldev *dev)
{
	if (!B43_DEBUG)
		return;
	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	    (dev->mac_suspended <= 0)) {
		b43dbg(dev->wl, "PHY/RADIO register access with "
		       "enabled MAC.\n");
		dump_stack();
	}
}

u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	dev->phy.writes_counter = 0;
	return dev->phy.ops->radio_read(dev, reg);
}

void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	if (b43_bus_host_is_pci(dev->dev) &&
	    ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
		b43_read32(dev, B43_MMIO_MACCTL);
		dev->phy.writes_counter = 1;
	}
	dev->phy.ops->radio_write(dev, reg, value);
}

void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) & mask);
}

void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	b43_radio_write16(dev, offset,
			  b43_radio_read16(dev, offset) | set);
}

void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	b43_radio_write16(dev, offset,
			  (b43_radio_read16(dev, offset) & mask) | set);
}

bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
			  u16 value, int delay, int timeout)
{
	u16 val;
	int i;

	for (i = 0; i < timeout; i += delay) {
		val = b43_radio_read(dev, offset);
		if ((val & mask) == value)
			return true;
		udelay(delay);
	}
	return false;
}

u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
{
	assert_mac_suspended(dev);
	dev->phy.writes_counter = 0;

	if (dev->phy.ops->phy_read)
		return dev->phy.ops->phy_read(dev, reg);

	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	assert_mac_suspended(dev);
	if (b43_bus_host_is_pci(dev->dev) &&
	    ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
		b43_read16(dev, B43_MMIO_PHY_VER);
		dev->phy.writes_counter = 1;
	}

	if (dev->phy.ops->phy_write)
		return dev->phy.ops->phy_write(dev, reg, value);

	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
{
	assert_mac_suspended(dev);
	dev->phy.ops->phy_write(dev, destreg,
		dev->phy.ops->phy_read(dev, srcreg));
}

void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) & mask);
	}
}

void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	} else {
		b43_phy_write(dev, offset,
			      b43_phy_read(dev, offset) | set);
	}
}

void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
{
	if (dev->phy.ops->phy_maskset) {
		assert_mac_suspended(dev);
		dev->phy.ops->phy_maskset(dev, offset, mask, set);
	} else {
		b43_phy_write(dev, offset,
			      (b43_phy_read(dev, offset) & mask) | set);
	}
}

void b43_phy_put_into_reset(struct b43_wldev *dev)
{
	u32 tmp;

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~B43_BCMA_IOCTL_GMODE;
		tmp |= B43_BCMA_IOCTL_PHY_RESET;
		tmp |= BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);

		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~B43_TMSLOW_GMODE;
		tmp |= B43_TMSLOW_PHYRESET;
		tmp |= SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		usleep_range(1000, 2000);

		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		usleep_range(1000, 2000);

		break;
#endif
	}
}

void b43_phy_take_out_of_reset(struct b43_wldev *dev)
{
	u32 tmp;

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		/* Unset reset bit (with forcing clock) */
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
		tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
		tmp |= BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);

		/* Do not force clock anymore */
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		tmp &= ~BCMA_IOCTL_FGC;
		tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		udelay(1);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		/* Unset reset bit (with forcing clock) */
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~B43_TMSLOW_PHYRESET;
		tmp &= ~B43_TMSLOW_PHYCLKEN;
		tmp |= SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
		usleep_range(1000, 2000);

		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		tmp &= ~SSB_TMSLOW_FGC;
		tmp |= B43_TMSLOW_PHYCLKEN;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
		usleep_range(1000, 2000);
		break;
#endif
	}
}

int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
{
	struct b43_phy *phy = &(dev->phy);
	u16 channelcookie, savedcookie;
	int err;

	/* First we set the channel radio code to prevent the
	 * firmware from sending ghost packets.
	 */
	channelcookie = new_channel;
	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
		channelcookie |= B43_SHM_SH_CHAN_5GHZ;
	/* FIXME: set 40Mhz flag if required */
	if (0)
		channelcookie |= B43_SHM_SH_CHAN_40MHZ;
	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);

	/* Now try to switch the PHY hardware channel. */
	err = phy->ops->switch_channel(dev, new_channel);
	if (err)
		goto err_restore_cookie;

	/* Wait for the radio to tune to the channel and stabilize. */
	msleep(8);

	return 0;

err_restore_cookie:
	b43_shm_write16(dev, B43_SHM_SHARED,
			B43_SHM_SH_CHAN, savedcookie);

	return err;
}

void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
{
	struct b43_phy *phy = &dev->phy;

	b43_mac_suspend(dev);
	phy->ops->software_rfkill(dev, blocked);
	phy->radio_on = !blocked;
	b43_mac_enable(dev);
}

/**
 * b43_phy_txpower_adjust_work - TX power workqueue.
 *
 * Workqueue for updating the TX power parameters in hardware.
 */
void b43_phy_txpower_adjust_work(struct work_struct *work)
{
	struct b43_wl *wl = container_of(work, struct b43_wl,
					 txpower_adjust_work);
	struct b43_wldev *dev;

	mutex_lock(&wl->mutex);
	dev = wl->current_dev;

	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
		dev->phy.ops->adjust_txpower(dev);

	mutex_unlock(&wl->mutex);
}

void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
{
	struct b43_phy *phy = &dev->phy;
	unsigned long now = jiffies;
	enum b43_txpwr_result result;

	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
		/* Check if it's time for a TXpower check. */
		if (time_before(now, phy->next_txpwr_check_time))
			return; /* Not yet */
	}
	/* The next check will be needed in two seconds, or later. */
	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));

	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
	    (dev->dev->board_type == SSB_BOARD_BU4306))
		return; /* No software txpower adjustment needed */

	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	if (result == B43_TXPWR_RES_DONE)
		return; /* We are done. */
	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	B43_WARN_ON(phy->ops->adjust_txpower == NULL);

	/* We must adjust the transmission power in hardware.
	 * Schedule b43_phy_txpower_adjust_work(). */
	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
}

int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
{
	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	unsigned int a, b, c, d;
	unsigned int average;
	u32 tmp;

	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	a = tmp & 0xFF;
	b = (tmp >> 8) & 0xFF;
	c = (tmp >> 16) & 0xFF;
	d = (tmp >> 24) & 0xFF;
	if (a == 0 || a == B43_TSSI_MAX ||
	    b == 0 || b == B43_TSSI_MAX ||
	    c == 0 || c == B43_TSSI_MAX ||
	    d == 0 || d == B43_TSSI_MAX)
		return -ENOENT;
	/* The values are OK. Clear them. */
	tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
	      (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);

	if (is_ofdm) {
		a = (a + 32) & 0x3F;
		b = (b + 32) & 0x3F;
		c = (c + 32) & 0x3F;
		d = (d + 32) & 0x3F;
	}

	/* Get the average of the values with 0.5 added to each value. */
	average = (a + b + c + d + 2) / 4;
	if (is_ofdm) {
		/* Adjust for CCK-boost */
		if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
		    & B43_HF_CCKBOOST)
			average = (average >= 13) ? (average - 13) : 0;
	}

	return average;
}

void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
{
	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
}


bool b43_is_40mhz(struct b43_wldev *dev)
{
	return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
void b43_phy_force_clock(struct b43_wldev *dev, bool force)
{
	u32 tmp;

	WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
		dev->phy.type != B43_PHYTYPE_HT);

	switch (dev->dev->bus_type) {
#ifdef CONFIG_B43_BCMA
	case B43_BUS_BCMA:
		tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
		if (force)
			tmp |= BCMA_IOCTL_FGC;
		else
			tmp &= ~BCMA_IOCTL_FGC;
		bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
		break;
#endif
#ifdef CONFIG_B43_SSB
	case B43_BUS_SSB:
		tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
		if (force)
			tmp |= SSB_TMSLOW_FGC;
		else
			tmp &= ~SSB_TMSLOW_FGC;
		ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
		break;
#endif
	}
}

/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
struct b43_c32 b43_cordic(int theta)
{
	static const u32 arctg[] = {
		2949120, 1740967, 919879, 466945, 234379, 117304,
		  58666,   29335,  14668,   7334,   3667,   1833,
		    917,     458,    229,    115,     57,     29,
	};
	u8 i;
	s32 tmp;
	s8 signx = 1;
	u32 angle = 0;
	struct b43_c32 ret = { .i = 39797, .q = 0, };

	while (theta > (180 << 16))
		theta -= (360 << 16);
	while (theta < -(180 << 16))
		theta += (360 << 16);

	if (theta > (90 << 16)) {
		theta -= (180 << 16);
		signx = -1;
	} else if (theta < -(90 << 16)) {
		theta += (180 << 16);
		signx = -1;
	}

	for (i = 0; i <= 17; i++) {
		if (theta > angle) {
			tmp = ret.i - (ret.q >> i);
			ret.q += ret.i >> i;
			ret.i = tmp;
			angle += arctg[i];
		} else {
			tmp = ret.i + (ret.q >> i);
			ret.q -= ret.i >> i;
			ret.i = tmp;
			angle -= arctg[i];
		}
	}

	ret.i *= signx;
	ret.q *= signx;

	return ret;
}
Commit	Line	Data
ef1a628d MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	Common PHY routines
	5
	6	Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
	7	Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
eb032b98	8	Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
ef1a628d MB	9	Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
	10	Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; see the file COPYING. If not, write to
	24	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	25	Boston, MA 02110-1301, USA.
	26
	27	*/
	28
	29	#include "phy_common.h"
	30	#include "phy_g.h"
	31	#include "phy_a.h"
3d0da751	32	#include "phy_n.h"
e63e4363	33	#include "phy_lp.h"
d7520b1d	34	#include "phy_ht.h"
58eb7ff3	35	#include "phy_lcn.h"
ef1a628d MB	36	#include "b43.h"
	37	#include "main.h"
	38
	39
fb11137a	40	int b43_phy_allocate(struct b43_wldev *dev)
ef1a628d MB	41	{
	42	struct b43_phy *phy = &(dev->phy);
	43	int err;
	44
	45	phy->ops = NULL;
	46
	47	switch (phy->type) {
ef1a628d	48	case B43_PHYTYPE_G:
418378fe	49	#ifdef CONFIG_B43_PHY_G
ef1a628d	50	phy->ops = &b43_phyops_g;
418378fe	51	#endif
ef1a628d MB	52	break;
ef1a628d MB	53	case B43_PHYTYPE_N:
692d2c0f	54	#ifdef CONFIG_B43_PHY_N
ef1a628d MB	55	phy->ops = &b43_phyops_n;
	56	#endif
	57	break;
	58	case B43_PHYTYPE_LP:
e63e4363 MB	59	#ifdef CONFIG_B43_PHY_LP
e63e4363 MB	60	phy->ops = &b43_phyops_lp;
d7520b1d RM	61	#endif
	62	break;
	63	case B43_PHYTYPE_HT:
	64	#ifdef CONFIG_B43_PHY_HT
	65	phy->ops = &b43_phyops_ht;
58eb7ff3 RM	66	#endif
	67	break;
	68	case B43_PHYTYPE_LCN:
	69	#ifdef CONFIG_B43_PHY_LCN
	70	phy->ops = &b43_phyops_lcn;
e63e4363	71	#endif
ef1a628d MB	72	break;
	73	}
	74	if (B43_WARN_ON(!phy->ops))
	75	return -ENODEV;
	76
	77	err = phy->ops->allocate(dev);
	78	if (err)
	79	phy->ops = NULL;
	80
	81	return err;
	82	}
	83
fb11137a MB	84	void b43_phy_free(struct b43_wldev *dev)
	85	{
	86	dev->phy.ops->free(dev);
	87	dev->phy.ops = NULL;
	88	}
	89
ef1a628d MB	90	int b43_phy_init(struct b43_wldev *dev)
	91	{
	92	struct b43_phy *phy = &dev->phy;
	93	const struct b43_phy_operations *ops = phy->ops;
	94	int err;
	95
ea42e71c RM	96	/* During PHY init we need to use some channel. On the first init this
	97	* function is called before b43_op_config, so our pointer is NULL.
	98	*/
	99	if (!phy->chandef) {
	100	phy->chandef = &dev->wl->hw->conf.chandef;
	101	phy->channel = phy->chandef->chan->hw_value;
	102	}
ef1a628d	103
7a8af8cf	104	phy->ops->switch_analog(dev, true);
a6316e28	105	b43_software_rfkill(dev, false);
09951ad4	106
ef1a628d MB	107	err = ops->init(dev);
	108	if (err) {
	109	b43err(dev->wl, "PHY init failed\n");
	110	goto err_block_rf;
	111	}
09951ad4 RM	112	phy->do_full_init = false;
09951ad4 RM	113
eb530b0f	114	err = b43_switch_channel(dev, phy->channel);
ef1a628d MB	115	if (err) {
	116	b43err(dev->wl, "PHY init: Channel switch to default failed\n");
	117	goto err_phy_exit;
	118	}
	119
	120	return 0;
	121
	122	err_phy_exit:
09951ad4	123	phy->do_full_init = true;
ef1a628d MB	124	if (ops->exit)
	125	ops->exit(dev);
	126	err_block_rf:
a6316e28	127	b43_software_rfkill(dev, true);
ef1a628d MB	128
	129	return err;
	130	}
	131
	132	void b43_phy_exit(struct b43_wldev *dev)
	133	{
	134	const struct b43_phy_operations *ops = dev->phy.ops;
	135
a6316e28	136	b43_software_rfkill(dev, true);
09951ad4	137	dev->phy.do_full_init = true;
ef1a628d MB	138	if (ops->exit)
	139	ops->exit(dev);
	140	}
	141
	142	bool b43_has_hardware_pctl(struct b43_wldev *dev)
	143	{
	144	if (!dev->phy.hardware_power_control)
1a2b250b	145	return false;
ef1a628d	146	if (!dev->phy.ops->supports_hwpctl)
1a2b250b	147	return false;
ef1a628d MB	148	return dev->phy.ops->supports_hwpctl(dev);
	149	}
	150
	151	void b43_radio_lock(struct b43_wldev *dev)
	152	{
	153	u32 macctl;
	154
591f3dc2 MB	155	#if B43_DEBUG
591f3dc2 MB	156	B43_WARN_ON(dev->phy.radio_locked);
3db1cd5c	157	dev->phy.radio_locked = true;
591f3dc2 MB	158	#endif
591f3dc2 MB	159
ef1a628d	160	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	161	macctl \|= B43_MACCTL_RADIOLOCK;
ef1a628d MB	162	b43_write32(dev, B43_MMIO_MACCTL, macctl);
591f3dc2 MB	163	/* Commit the write and wait for the firmware
591f3dc2 MB	164	* to finish any radio register access. */
ef1a628d MB	165	b43_read32(dev, B43_MMIO_MACCTL);
	166	udelay(10);
	167	}
	168
	169	void b43_radio_unlock(struct b43_wldev *dev)
	170	{
	171	u32 macctl;
	172
591f3dc2 MB	173	#if B43_DEBUG
591f3dc2 MB	174	B43_WARN_ON(!dev->phy.radio_locked);
3db1cd5c	175	dev->phy.radio_locked = false;
591f3dc2 MB	176	#endif
591f3dc2 MB	177
ef1a628d MB	178	/* Commit any write */
	179	b43_read16(dev, B43_MMIO_PHY_VER);
	180	/* unlock */
	181	macctl = b43_read32(dev, B43_MMIO_MACCTL);
ef1a628d MB	182	macctl &= ~B43_MACCTL_RADIOLOCK;
	183	b43_write32(dev, B43_MMIO_MACCTL, macctl);
	184	}
	185
	186	void b43_phy_lock(struct b43_wldev *dev)
	187	{
	188	#if B43_DEBUG
	189	B43_WARN_ON(dev->phy.phy_locked);
3db1cd5c	190	dev->phy.phy_locked = true;
ef1a628d	191	#endif
21d889d4	192	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	193
05c914fe	194	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	195	b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
	196	}
	197
	198	void b43_phy_unlock(struct b43_wldev *dev)
	199	{
	200	#if B43_DEBUG
	201	B43_WARN_ON(!dev->phy.phy_locked);
3db1cd5c	202	dev->phy.phy_locked = false;
ef1a628d	203	#endif
21d889d4	204	B43_WARN_ON(dev->dev->core_rev < 3);
ef1a628d	205
05c914fe	206	if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
ef1a628d MB	207	b43_power_saving_ctl_bits(dev, 0);
	208	}
	209
d10d0e57 MB	210	static inline void assert_mac_suspended(struct b43_wldev *dev)
	211	{
	212	if (!B43_DEBUG)
	213	return;
	214	if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
	215	(dev->mac_suspended <= 0)) {
	216	b43dbg(dev->wl, "PHY/RADIO register access with "
	217	"enabled MAC.\n");
	218	dump_stack();
	219	}
	220	}
	221
ef1a628d MB	222	u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	223	{
d10d0e57	224	assert_mac_suspended(dev);
6247d2aa	225	dev->phy.writes_counter = 0;
ef1a628d MB	226	return dev->phy.ops->radio_read(dev, reg);
	227	}
	228
	229	void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
	230	{
d10d0e57	231	assert_mac_suspended(dev);
6247d2aa RM	232	if (b43_bus_host_is_pci(dev->dev) &&
	233	++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
	234	b43_read32(dev, B43_MMIO_MACCTL);
	235	dev->phy.writes_counter = 1;
	236	}
ef1a628d MB	237	dev->phy.ops->radio_write(dev, reg, value);
	238	}
	239
	240	void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
	241	{
	242	b43_radio_write16(dev, offset,
	243	b43_radio_read16(dev, offset) & mask);
	244	}
	245
	246	void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
	247	{
	248	b43_radio_write16(dev, offset,
	249	b43_radio_read16(dev, offset) \| set);
	250	}
	251
	252	void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	253	{
	254	b43_radio_write16(dev, offset,
	255	(b43_radio_read16(dev, offset) & mask) \| set);
	256	}
	257
0f941777 RM	258	bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
	259	u16 value, int delay, int timeout)
	260	{
	261	u16 val;
	262	int i;
	263
	264	for (i = 0; i < timeout; i += delay) {
	265	val = b43_radio_read(dev, offset);
	266	if ((val & mask) == value)
	267	return true;
	268	udelay(delay);
	269	}
	270	return false;
	271	}
	272
ef1a628d MB	273	u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
ef1a628d MB	274	{
d10d0e57	275	assert_mac_suspended(dev);
15518080	276	dev->phy.writes_counter = 0;
d342b95d RM	277
	278	if (dev->phy.ops->phy_read)
	279	return dev->phy.ops->phy_read(dev, reg);
	280
25c15566	281	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
d342b95d	282	return b43_read16(dev, B43_MMIO_PHY_DATA);
ef1a628d MB	283	}
	284
	285	void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
	286	{
d10d0e57	287	assert_mac_suspended(dev);
6247d2aa RM	288	if (b43_bus_host_is_pci(dev->dev) &&
6247d2aa RM	289	++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
15518080	290	b43_read16(dev, B43_MMIO_PHY_VER);
6247d2aa	291	dev->phy.writes_counter = 1;
15518080	292	}
d342b95d RM	293
	294	if (dev->phy.ops->phy_write)
	295	return dev->phy.ops->phy_write(dev, reg, value);
	296
25c15566	297	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
d342b95d	298	b43_write16(dev, B43_MMIO_PHY_DATA, value);
ef1a628d MB	299	}
ef1a628d MB	300
738f0f43 GS	301	void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
	302	{
	303	assert_mac_suspended(dev);
	304	dev->phy.ops->phy_write(dev, destreg,
	305	dev->phy.ops->phy_read(dev, srcreg));
	306	}
	307
ef1a628d MB	308	void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
ef1a628d MB	309	{
68ec5329 GS	310	if (dev->phy.ops->phy_maskset) {
	311	assert_mac_suspended(dev);
	312	dev->phy.ops->phy_maskset(dev, offset, mask, 0);
	313	} else {
	314	b43_phy_write(dev, offset,
	315	b43_phy_read(dev, offset) & mask);
	316	}
ef1a628d MB	317	}
	318
	319	void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
	320	{
68ec5329 GS	321	if (dev->phy.ops->phy_maskset) {
	322	assert_mac_suspended(dev);
	323	dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
	324	} else {
	325	b43_phy_write(dev, offset,
	326	b43_phy_read(dev, offset) \| set);
	327	}
ef1a628d MB	328	}
	329
	330	void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
	331	{
68ec5329 GS	332	if (dev->phy.ops->phy_maskset) {
	333	assert_mac_suspended(dev);
	334	dev->phy.ops->phy_maskset(dev, offset, mask, set);
	335	} else {
	336	b43_phy_write(dev, offset,
	337	(b43_phy_read(dev, offset) & mask) \| set);
	338	}
ef1a628d MB	339	}
ef1a628d MB	340
b60c3c2f RM	341	void b43_phy_put_into_reset(struct b43_wldev *dev)
b60c3c2f RM	342	{
b60c3c2f	343	u32 tmp;
b60c3c2f RM	344
	345	switch (dev->dev->bus_type) {
	346	#ifdef CONFIG_B43_BCMA
	347	case B43_BUS_BCMA:
50c1b59e RM	348	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	349	tmp &= ~B43_BCMA_IOCTL_GMODE;
	350	tmp \|= B43_BCMA_IOCTL_PHY_RESET;
	351	tmp \|= BCMA_IOCTL_FGC;
	352	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	353	udelay(1);
	354
	355	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	356	tmp &= ~BCMA_IOCTL_FGC;
	357	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	358	udelay(1);
b60c3c2f RM	359	break;
	360	#endif
	361	#ifdef CONFIG_B43_SSB
	362	case B43_BUS_SSB:
	363	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	364	tmp &= ~B43_TMSLOW_GMODE;
	365	tmp \|= B43_TMSLOW_PHYRESET;
	366	tmp \|= SSB_TMSLOW_FGC;
	367	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
50c1b59e	368	usleep_range(1000, 2000);
b60c3c2f RM	369
	370	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	371	tmp &= ~SSB_TMSLOW_FGC;
b60c3c2f	372	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
50c1b59e	373	usleep_range(1000, 2000);
b60c3c2f RM	374
	375	break;
	376	#endif
	377	}
	378	}
	379
50c1b59e RM	380	void b43_phy_take_out_of_reset(struct b43_wldev *dev)
	381	{
	382	u32 tmp;
	383
	384	switch (dev->dev->bus_type) {
	385	#ifdef CONFIG_B43_BCMA
	386	case B43_BUS_BCMA:
	387	/* Unset reset bit (with forcing clock) */
	388	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	389	tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
	390	tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
	391	tmp \|= BCMA_IOCTL_FGC;
	392	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	393	udelay(1);
	394
	395	/* Do not force clock anymore */
	396	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	397	tmp &= ~BCMA_IOCTL_FGC;
	398	tmp \|= B43_BCMA_IOCTL_PHY_CLKEN;
	399	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	400	udelay(1);
	401	break;
	402	#endif
	403	#ifdef CONFIG_B43_SSB
	404	case B43_BUS_SSB:
	405	/* Unset reset bit (with forcing clock) */
	406	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	407	tmp &= ~B43_TMSLOW_PHYRESET;
	408	tmp &= ~B43_TMSLOW_PHYCLKEN;
	409	tmp \|= SSB_TMSLOW_FGC;
	410	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	411	ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
	412	usleep_range(1000, 2000);
	413
	414	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	415	tmp &= ~SSB_TMSLOW_FGC;
	416	tmp \|= B43_TMSLOW_PHYCLKEN;
	417	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	418	ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
	419	usleep_range(1000, 2000);
	420	break;
	421	#endif
	422	}
	423	}
	424
ef1a628d MB	425	int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
	426	{
	427	struct b43_phy *phy = &(dev->phy);
	428	u16 channelcookie, savedcookie;
	429	int err;
	430
ef1a628d MB	431	/* First we set the channel radio code to prevent the
	432	* firmware from sending ghost packets.
	433	*/
	434	channelcookie = new_channel;
	435	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
106cb09a RM	436	channelcookie \|= B43_SHM_SH_CHAN_5GHZ;
	437	/* FIXME: set 40Mhz flag if required */
	438	if (0)
	439	channelcookie \|= B43_SHM_SH_CHAN_40MHZ;
ef1a628d MB	440	savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
	441	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
	442
	443	/* Now try to switch the PHY hardware channel. */
	444	err = phy->ops->switch_channel(dev, new_channel);
	445	if (err)
	446	goto err_restore_cookie;
	447
ef1a628d MB	448	/* Wait for the radio to tune to the channel and stabilize. */
	449	msleep(8);
	450
	451	return 0;
	452
	453	err_restore_cookie:
	454	b43_shm_write16(dev, B43_SHM_SHARED,
	455	B43_SHM_SH_CHAN, savedcookie);
	456
	457	return err;
	458	}
	459
19d337df	460	void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
ef1a628d MB	461	{
	462	struct b43_phy *phy = &dev->phy;
	463
b929ecf7	464	b43_mac_suspend(dev);
19d337df JB	465	phy->ops->software_rfkill(dev, blocked);
19d337df JB	466	phy->radio_on = !blocked;
b929ecf7	467	b43_mac_enable(dev);
ef1a628d	468	}
18c8adeb MB	469
	470	/**
	471	* b43_phy_txpower_adjust_work - TX power workqueue.
	472	*
	473	* Workqueue for updating the TX power parameters in hardware.
	474	*/
	475	void b43_phy_txpower_adjust_work(struct work_struct *work)
	476	{
	477	struct b43_wl *wl = container_of(work, struct b43_wl,
	478	txpower_adjust_work);
	479	struct b43_wldev *dev;
	480
	481	mutex_lock(&wl->mutex);
	482	dev = wl->current_dev;
	483
	484	if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
	485	dev->phy.ops->adjust_txpower(dev);
	486
	487	mutex_unlock(&wl->mutex);
	488	}
	489
18c8adeb MB	490	void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
	491	{
	492	struct b43_phy *phy = &dev->phy;
	493	unsigned long now = jiffies;
	494	enum b43_txpwr_result result;
	495
	496	if (!(flags & B43_TXPWR_IGNORE_TIME)) {
	497	/* Check if it's time for a TXpower check. */
	498	if (time_before(now, phy->next_txpwr_check_time))
	499	return; /* Not yet */
	500	}
	501	/* The next check will be needed in two seconds, or later. */
	502	phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
	503
79d2232f RM	504	if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
79d2232f RM	505	(dev->dev->board_type == SSB_BOARD_BU4306))
18c8adeb MB	506	return; /* No software txpower adjustment needed */
	507
	508	result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
	509	if (result == B43_TXPWR_RES_DONE)
	510	return; /* We are done. */
	511	B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
	512	B43_WARN_ON(phy->ops->adjust_txpower == NULL);
	513
	514	/* We must adjust the transmission power in hardware.
	515	* Schedule b43_phy_txpower_adjust_work(). */
42935eca	516	ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
18c8adeb MB	517	}
	518
	519	int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
	520	{
	521	const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
	522	unsigned int a, b, c, d;
	523	unsigned int average;
	524	u32 tmp;
	525
	526	tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
	527	a = tmp & 0xFF;
	528	b = (tmp >> 8) & 0xFF;
	529	c = (tmp >> 16) & 0xFF;
	530	d = (tmp >> 24) & 0xFF;
	531	if (a == 0 \|\| a == B43_TSSI_MAX \|\|
	532	b == 0 \|\| b == B43_TSSI_MAX \|\|
	533	c == 0 \|\| c == B43_TSSI_MAX \|\|
	534	d == 0 \|\| d == B43_TSSI_MAX)
	535	return -ENOENT;
	536	/* The values are OK. Clear them. */
	537	tmp = B43_TSSI_MAX \| (B43_TSSI_MAX << 8) \|
	538	(B43_TSSI_MAX << 16) \| (B43_TSSI_MAX << 24);
	539	b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
	540
	541	if (is_ofdm) {
	542	a = (a + 32) & 0x3F;
	543	b = (b + 32) & 0x3F;
	544	c = (c + 32) & 0x3F;
	545	d = (d + 32) & 0x3F;
	546	}
	547
	548	/* Get the average of the values with 0.5 added to each value. */
	549	average = (a + b + c + d + 2) / 4;
	550	if (is_ofdm) {
	551	/* Adjust for CCK-boost */
6e6a2cd5	552	if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
18c8adeb MB	553	& B43_HF_CCKBOOST)
	554	average = (average >= 13) ? (average - 13) : 0;
	555	}
	556
	557	return average;
	558	}
cb24f57f MB	559
	560	void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
	561	{
	562	b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
	563	}
98650454	564
abc1f7cd	565
bee6d4b2 RM	566	bool b43_is_40mhz(struct b43_wldev *dev)
	567	{
	568	return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
	569	}
	570
f6a3e99d RM	571	/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
	572	void b43_phy_force_clock(struct b43_wldev *dev, bool force)
	573	{
	574	u32 tmp;
	575
	576	WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
	577	dev->phy.type != B43_PHYTYPE_HT);
	578
	579	switch (dev->dev->bus_type) {
	580	#ifdef CONFIG_B43_BCMA
	581	case B43_BUS_BCMA:
	582	tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
	583	if (force)
	584	tmp \|= BCMA_IOCTL_FGC;
	585	else
	586	tmp &= ~BCMA_IOCTL_FGC;
	587	bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
	588	break;
	589	#endif
	590	#ifdef CONFIG_B43_SSB
	591	case B43_BUS_SSB:
	592	tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
	593	if (force)
	594	tmp \|= SSB_TMSLOW_FGC;
	595	else
	596	tmp &= ~SSB_TMSLOW_FGC;
	597	ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
	598	break;
	599	#endif
	600	}
	601	}
	602
6f98e62a	603	/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
98650454 RM	604	struct b43_c32 b43_cordic(int theta)
98650454 RM	605	{
5b4bc649 JP	606	static const u32 arctg[] = {
	607	2949120, 1740967, 919879, 466945, 234379, 117304,
	608	58666, 29335, 14668, 7334, 3667, 1833,
	609	917, 458, 229, 115, 57, 29,
	610	};
6f98e62a RM	611	u8 i;
	612	s32 tmp;
	613	s8 signx = 1;
	614	u32 angle = 0;
98650454 RM	615	struct b43_c32 ret = { .i = 39797, .q = 0, };
98650454 RM	616
6f98e62a RM	617	while (theta > (180 << 16))
	618	theta -= (360 << 16);
	619	while (theta < -(180 << 16))
	620	theta += (360 << 16);
98650454	621
6f98e62a RM	622	if (theta > (90 << 16)) {
6f98e62a RM	623	theta -= (180 << 16);
98650454	624	signx = -1;
6f98e62a RM	625	} else if (theta < -(90 << 16)) {
6f98e62a RM	626	theta += (180 << 16);
98650454 RM	627	signx = -1;
	628	}
	629
	630	for (i = 0; i <= 17; i++) {
	631	if (theta > angle) {
	632	tmp = ret.i - (ret.q >> i);
	633	ret.q += ret.i >> i;
	634	ret.i = tmp;
	635	angle += arctg[i];
	636	} else {
	637	tmp = ret.i + (ret.q >> i);
	638	ret.q -= ret.i >> i;
	639	ret.i = tmp;
	640	angle -= arctg[i];
	641	}
	642	}
	643
	644	ret.i *= signx;
	645	ret.q *= signx;
	646
	647	return ret;
	648	}