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d7520b1d RM |
1 | #ifndef B43_PHY_HT_H_ |
2 | #define B43_PHY_HT_H_ | |
3 | ||
4 | #include "phy_common.h" | |
5 | ||
6 | ||
19240f36 RM |
7 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
8 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ | |
9 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ | |
bdb2dfb2 | 10 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
19240f36 | 11 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
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12 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
13 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ | |
14 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ | |
b372afae RM |
15 | #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */ |
16 | #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */ | |
17 | #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */ | |
18 | #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */ | |
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19 | #define B43_PHY_HT_BW1 0x1CE |
20 | #define B43_PHY_HT_BW2 0x1CF | |
21 | #define B43_PHY_HT_BW3 0x1D0 | |
22 | #define B43_PHY_HT_BW4 0x1D1 | |
23 | #define B43_PHY_HT_BW5 0x1D2 | |
24 | #define B43_PHY_HT_BW6 0x1D3 | |
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25 | #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ |
26 | #define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ | |
27 | #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ | |
28 | #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ | |
29 | #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ | |
30 | #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 | |
31 | #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F | |
d7520b1d | 32 | |
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33 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
34 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) | |
35 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) | |
36 | ||
c750f795 RM |
37 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) |
38 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) | |
39 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ | |
40 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ | |
41 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ | |
42 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ | |
43 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ | |
44 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ | |
45 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) | |
46 | /* Values for the status are the same as for the trigger */ | |
47 | ||
e7c62552 RM |
48 | #define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) |
49 | ||
a51ab258 RM |
50 | #define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c) |
51 | #define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c) | |
52 | #define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c) | |
53 | ||
47606922 RM |
54 | #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) |
55 | #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) | |
56 | #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) | |
57 | #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) | |
58 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) | |
59 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) | |
a8e82749 | 60 | |
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61 | #define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) |
62 | #define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F | |
63 | ||
b372afae RM |
64 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) |
65 | ||
d7520b1d | 66 | |
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67 | /* Values for PHY registers used on channel switching */ |
68 | struct b43_phy_ht_channeltab_e_phy { | |
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69 | u16 bw1; |
70 | u16 bw2; | |
71 | u16 bw3; | |
72 | u16 bw4; | |
73 | u16 bw5; | |
74 | u16 bw6; | |
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75 | }; |
76 | ||
77 | ||
d7520b1d | 78 | struct b43_phy_ht { |
a51ab258 | 79 | u16 rf_ctl_int_save[3]; |
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80 | |
81 | bool tx_pwr_ctl; | |
82 | u8 tx_pwr_idx[3]; | |
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83 | }; |
84 | ||
85 | ||
86 | struct b43_phy_operations; | |
87 | extern const struct b43_phy_operations b43_phyops_ht; | |
88 | ||
89 | #endif /* B43_PHY_HT_H_ */ |