[deliverable/linux.git] / drivers / net / wireless / b43 / phy_lcn.c

/*

  Broadcom B43 wireless driver
  IEEE 802.11n LCN-PHY support

  Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

  This file incorporates work covered by the following copyright and
  permission notice:

      Copyright (c) 2010 Broadcom Corporation

      Permission to use, copy, modify, and/or distribute this software for any
      purpose with or without fee is hereby granted, provided that the above
      copyright notice and this permission notice appear in all copies.
*/

#include <linux/slab.h>

#include "b43.h"
#include "phy_lcn.h"
#include "tables_phy_lcn.h"
#include "main.h"

/**************************************************
 * Radio 2064.
 **************************************************/

/* wlc_lcnphy_radio_2064_channel_tune_4313 */
static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
{
	u16 save[2];

	b43_radio_set(dev, 0x09d, 0x4);
	b43_radio_write(dev, 0x09e, 0xf);

	/* Channel specific values in theory, in practice always the same */
	b43_radio_write(dev, 0x02a, 0xb);
	b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
	b43_radio_maskset(dev, 0x091, ~0x3, 0);
	b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
	b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
	b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
	b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
	b43_radio_write(dev, 0x06c, 0x80);

	save[0] = b43_radio_read(dev, 0x044);
	save[1] = b43_radio_read(dev, 0x12b);

	b43_radio_set(dev, 0x044, 0x7);
	b43_radio_set(dev, 0x12b, 0xe);

	/* TODO */

	b43_radio_write(dev, 0x040, 0xfb);

	b43_radio_write(dev, 0x041, 0x9a);
	b43_radio_write(dev, 0x042, 0xa3);
	b43_radio_write(dev, 0x043, 0x0c);

	/* TODO */

	b43_radio_set(dev, 0x044, 0x0c);
	udelay(1);

	b43_radio_write(dev, 0x044, save[0]);
	b43_radio_write(dev, 0x12b, save[1]);

	if (dev->phy.rev == 1) {
		/* brcmsmac uses outdated 0x3 for 0x038 */
		b43_radio_write(dev, 0x038, 0x0);
		b43_radio_write(dev, 0x091, 0x7);
	}
}

/* wlc_radio_2064_init */
static void b43_radio_2064_init(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		b43_radio_write(dev, 0x09c, 0x0020);
		b43_radio_write(dev, 0x105, 0x0008);
	} else {
		/* TODO */
	}
	b43_radio_write(dev, 0x032, 0x0062);
	b43_radio_write(dev, 0x033, 0x0019);
	b43_radio_write(dev, 0x090, 0x0010);
	b43_radio_write(dev, 0x010, 0x0000);
	if (dev->phy.rev == 1) {
		b43_radio_write(dev, 0x060, 0x007f);
		b43_radio_write(dev, 0x061, 0x0072);
		b43_radio_write(dev, 0x062, 0x007f);
	}
	b43_radio_write(dev, 0x01d, 0x0002);
	b43_radio_write(dev, 0x01e, 0x0006);

	b43_phy_write(dev, 0x4ea, 0x4688);
	b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
	b43_phy_mask(dev, 0x4eb, ~0x01c0);
	b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);

	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);

	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	b43_radio_set(dev, 0x004, 0x40);
	b43_radio_set(dev, 0x120, 0x10);
	b43_radio_set(dev, 0x078, 0x80);
	b43_radio_set(dev, 0x129, 0x2);
	b43_radio_set(dev, 0x057, 0x1);
	b43_radio_set(dev, 0x05b, 0x2);

	/* TODO: wait for some bit to be set */
	b43_radio_read(dev, 0x05c);

	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	b43_radio_mask(dev, 0x057, (u16) ~0xff01);

	b43_phy_write(dev, 0x933, 0x2d6b);
	b43_phy_write(dev, 0x934, 0x2d6b);
	b43_phy_write(dev, 0x935, 0x2d6b);
	b43_phy_write(dev, 0x936, 0x2d6b);
	b43_phy_write(dev, 0x937, 0x016b);

	b43_radio_mask(dev, 0x057, (u16) ~0xff02);
	b43_radio_write(dev, 0x0c2, 0x006f);
}

/**************************************************
 * Various PHY ops
 **************************************************/

/* wlc_lcnphy_toggle_afe_pwdn */
static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
{
	u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
	u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
}

/* wlc_lcnphy_clear_tx_power_offsets */
static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)
{
	u8 i;

	if (1) { /* FIXME */
		b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
		for (i = 0; i < 30; i++) {
			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
		}
	}

	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
	for (i = 0; i < 64; i++) {
		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	}
}

/* wlc_lcnphy_rev0_baseband_init */
static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)
{
	b43_radio_write(dev, 0x11c, 0);

	b43_phy_write(dev, 0x43b, 0);
	b43_phy_write(dev, 0x43c, 0);
	b43_phy_write(dev, 0x44c, 0);
	b43_phy_write(dev, 0x4e6, 0);
	b43_phy_write(dev, 0x4f9, 0);
	b43_phy_write(dev, 0x4b0, 0);
	b43_phy_write(dev, 0x938, 0);
	b43_phy_write(dev, 0x4b0, 0);
	b43_phy_write(dev, 0x44e, 0);

	b43_phy_set(dev, 0x567, 0x03);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))
		; /* TODO */
	b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {
		b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
		b43_phy_write(dev, 0x910, 0x1);
	}

	b43_phy_write(dev, 0x910, 0x1);

	b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
	b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
	b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
}

/* wlc_lcnphy_bu_tweaks */
static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
{
	b43_phy_set(dev, 0x805, 0x1);

	b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
	b43_phy_maskset(dev, 0x030, ~0x7, 0x3);

	b43_phy_write(dev, 0x414, 0x1e10);
	b43_phy_write(dev, 0x415, 0x0640);

	b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
	b43_phy_maskset(dev, 0x420, ~0xff, 0x10);

	if (dev->dev->bus_sprom->board_rev >= 0x1204)
		b43_radio_set(dev, 0x09b, 0xf0);

	b43_phy_write(dev, 0x7d6, 0x0902);

	/* TODO: more ops */

	if (dev->phy.rev == 1) {
		/* TODO: more ops */

		b43_phy_lcn_clear_tx_power_offsets(dev);
	}
}

/* wlc_lcnphy_vbat_temp_sense_setup */
static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
{
	u8 i;

	u16 save_radio_regs[6][2] = {
		{ 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
		{ 0x025, 0 }, { 0x112, 0 },
	};
	u16 save_phy_regs[14][2] = {
		{ 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
		{ 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
		{ 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
		{ 0x40d, 0 }, { 0x4a2, 0 },
	};
	u16 save_radio_4a4;

	for (i = 0; i < 6; i++)
		save_radio_regs[i][1] = b43_radio_read(dev,
						       save_radio_regs[i][0]);
	for (i = 0; i < 14; i++)
		save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
	save_radio_4a4 = b43_radio_read(dev, 0x4a4);

	/* TODO: config sth */

	for (i = 0; i < 6; i++)
		b43_radio_write(dev, save_radio_regs[i][0],
				save_radio_regs[i][1]);
	for (i = 0; i < 14; i++)
		b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
	b43_radio_write(dev, 0x4a4, save_radio_4a4);
}

/**************************************************
 * Channel switching ops.
 **************************************************/

/* wlc_lcnphy_set_chanspec_tweaks */
static void b43_phy_lcn_set_channel_tweaks(struct b43_wldev *dev, int channel)
{
	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;

	b43_phy_maskset(dev, 0x448, ~0x300, (channel == 14) ? 0x200 : 0x100);

	if (channel == 1 || channel == 2 || channel == 3 || channel == 4 ||
	    channel == 9 || channel == 10 || channel == 11 || channel == 12) {
		bcma_chipco_pll_write(cc, 0x2, 0x03000c04);
		bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x0);
		bcma_chipco_pll_write(cc, 0x4, 0x200005c0);

		bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400);

		b43_phy_write(dev, 0x942, 0);

		/* b43_phy_lcn_txrx_spur_avoidance_mode(dev, false); */
		b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1b00);
		b43_phy_write(dev, 0x425, 0x5907);
	} else {
		bcma_chipco_pll_write(cc, 0x2, 0x03140c04);
		bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x333333);
		bcma_chipco_pll_write(cc, 0x4, 0x202c2820);

		bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400);

		b43_phy_write(dev, 0x942, 0);

		/* b43_phy_lcn_txrx_spur_avoidance_mode(dev, true); */
		b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1f00);
		b43_phy_write(dev, 0x425, 0x590a);
	}

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);
}

/* wlc_phy_chanspec_set_lcnphy */
static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
				   struct ieee80211_channel *channel,
				   enum nl80211_channel_type channel_type)
{
	b43_phy_lcn_set_channel_tweaks(dev, channel->hw_value);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	b43_radio_2064_channel_setup(dev);
	mdelay(1);

	b43_phy_lcn_afe_set_unset(dev);

	/* TODO */

	return 0;
}

/**************************************************
 * Basic PHY ops.
 **************************************************/

static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
{
	struct b43_phy_lcn *phy_lcn;

	phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
	if (!phy_lcn)
		return -ENOMEM;
	dev->phy.lcn = phy_lcn;

	return 0;
}

static void b43_phy_lcn_op_free(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_lcn *phy_lcn = phy->lcn;

	kfree(phy_lcn);
	phy->lcn = NULL;
}

static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_lcn *phy_lcn = phy->lcn;

	memset(phy_lcn, 0, sizeof(*phy_lcn));
}

/* wlc_phy_init_lcnphy */
static int b43_phy_lcn_op_init(struct b43_wldev *dev)
{
	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;

	b43_phy_set(dev, 0x44a, 0x80);
	b43_phy_mask(dev, 0x44a, 0x7f);
	b43_phy_set(dev, 0x6d1, 0x80);
	b43_phy_write(dev, 0x6d0, 0x7);

	b43_phy_lcn_afe_set_unset(dev);

	b43_phy_write(dev, 0x60a, 0xa0);
	b43_phy_write(dev, 0x46a, 0x19);
	b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);

	b43_phy_lcn_tables_init(dev);

	b43_phy_lcn_rev0_baseband_init(dev);
	b43_phy_lcn_bu_tweaks(dev);

	if (dev->phy.radio_ver == 0x2064)
		b43_radio_2064_init(dev);
	else
		B43_WARN_ON(1);

	b43_phy_lcn_sense_setup(dev);

	b43_switch_channel(dev, dev->phy.channel);

	bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9);
	bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd);

	/* TODO */

	b43_phy_set(dev, 0x448, 0x4000);
	udelay(100);
	b43_phy_mask(dev, 0x448, ~0x4000);

	/* TODO */

	return 0;
}

static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
					bool blocked)
{
	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
		b43err(dev->wl, "MAC not suspended\n");

	if (blocked) {
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);

		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);

		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
	} else {
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
	}
}

static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
{
	if (on) {
		b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
	} else {
		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
	}
}

static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
					unsigned int new_channel)
{
	struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
	enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		if ((new_channel < 1) || (new_channel > 14))
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	return b43_phy_lcn_set_channel(dev, channel, channel_type);
}

static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		return 1;
	return 36;
}

static enum b43_txpwr_result
b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
{
	return B43_TXPWR_RES_DONE;
}

static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
{
}

/**************************************************
 * R/W ops.
 **************************************************/

static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
				   u16 set)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA,
		    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
}

static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
{
	/* LCN-PHY needs 0x200 for read access */
	reg |= 0x200;

	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_RADIO24_DATA);
}

static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
				       u16 value)
{
	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
}

/**************************************************
 * PHY ops struct.
 **************************************************/

const struct b43_phy_operations b43_phyops_lcn = {
	.allocate		= b43_phy_lcn_op_allocate,
	.free			= b43_phy_lcn_op_free,
	.prepare_structs	= b43_phy_lcn_op_prepare_structs,
	.init			= b43_phy_lcn_op_init,
	.phy_read		= b43_phy_lcn_op_read,
	.phy_write		= b43_phy_lcn_op_write,
	.phy_maskset		= b43_phy_lcn_op_maskset,
	.radio_read		= b43_phy_lcn_op_radio_read,
	.radio_write		= b43_phy_lcn_op_radio_write,
	.software_rfkill	= b43_phy_lcn_op_software_rfkill,
	.switch_analog		= b43_phy_lcn_op_switch_analog,
	.switch_channel		= b43_phy_lcn_op_switch_channel,
	.get_default_chan	= b43_phy_lcn_op_get_default_chan,
	.recalc_txpower		= b43_phy_lcn_op_recalc_txpower,
	.adjust_txpower		= b43_phy_lcn_op_adjust_txpower,
};
Commit	Line	Data
1d738e64 RM	1	/*
	2
	3	Broadcom B43 wireless driver
	4	IEEE 802.11n LCN-PHY support
	5
108f4f3c RM	6	Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
108f4f3c RM	7
1d738e64 RM	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; see the file COPYING. If not, write to
	20	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	21	Boston, MA 02110-1301, USA.
	22
b534706a RM	23	This file incorporates work covered by the following copyright and
	24	permission notice:
	25
	26	Copyright (c) 2010 Broadcom Corporation
	27
	28	Permission to use, copy, modify, and/or distribute this software for any
	29	purpose with or without fee is hereby granted, provided that the above
	30	copyright notice and this permission notice appear in all copies.
1d738e64 RM	31	*/
	32
	33	#include <linux/slab.h>
	34
	35	#include "b43.h"
	36	#include "phy_lcn.h"
	37	#include "tables_phy_lcn.h"
	38	#include "main.h"
	39
dc713fb2 RM	40	/**************************************************
	41	* Radio 2064.
	42	**************************************************/
	43
bce4dc4a	44	/* wlc_lcnphy_radio_2064_channel_tune_4313 */
39f7d33c RM	45	static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
	46	{
	47	u16 save[2];
	48
	49	b43_radio_set(dev, 0x09d, 0x4);
	50	b43_radio_write(dev, 0x09e, 0xf);
	51
cf577fc2	52	/* Channel specific values in theory, in practice always the same */
39f7d33c RM	53	b43_radio_write(dev, 0x02a, 0xb);
	54	b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
	55	b43_radio_maskset(dev, 0x091, ~0x3, 0);
	56	b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
	57	b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
	58	b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
	59	b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
	60	b43_radio_write(dev, 0x06c, 0x80);
	61
	62	save[0] = b43_radio_read(dev, 0x044);
	63	save[1] = b43_radio_read(dev, 0x12b);
	64
	65	b43_radio_set(dev, 0x044, 0x7);
	66	b43_radio_set(dev, 0x12b, 0xe);
	67
	68	/* TODO */
	69
	70	b43_radio_write(dev, 0x040, 0xfb);
	71
	72	b43_radio_write(dev, 0x041, 0x9a);
	73	b43_radio_write(dev, 0x042, 0xa3);
	74	b43_radio_write(dev, 0x043, 0x0c);
	75
	76	/* TODO */
	77
	78	b43_radio_set(dev, 0x044, 0x0c);
	79	udelay(1);
	80
	81	b43_radio_write(dev, 0x044, save[0]);
	82	b43_radio_write(dev, 0x12b, save[1]);
	83
cf577fc2 RM	84	if (dev->phy.rev == 1) {
	85	/* brcmsmac uses outdated 0x3 for 0x038 */
	86	b43_radio_write(dev, 0x038, 0x0);
	87	b43_radio_write(dev, 0x091, 0x7);
	88	}
39f7d33c RM	89	}
39f7d33c RM	90
bce4dc4a	91	/* wlc_radio_2064_init */
dc713fb2 RM	92	static void b43_radio_2064_init(struct b43_wldev *dev)
dc713fb2 RM	93	{
cf577fc2 RM	94	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
	95	b43_radio_write(dev, 0x09c, 0x0020);
	96	b43_radio_write(dev, 0x105, 0x0008);
	97	} else {
	98	/* TODO */
	99	}
dc713fb2 RM	100	b43_radio_write(dev, 0x032, 0x0062);
	101	b43_radio_write(dev, 0x033, 0x0019);
	102	b43_radio_write(dev, 0x090, 0x0010);
	103	b43_radio_write(dev, 0x010, 0x0000);
cf577fc2 RM	104	if (dev->phy.rev == 1) {
	105	b43_radio_write(dev, 0x060, 0x007f);
	106	b43_radio_write(dev, 0x061, 0x0072);
	107	b43_radio_write(dev, 0x062, 0x007f);
	108	}
dc713fb2 RM	109	b43_radio_write(dev, 0x01d, 0x0002);
	110	b43_radio_write(dev, 0x01e, 0x0006);
	111
	112	b43_phy_write(dev, 0x4ea, 0x4688);
	113	b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
	114	b43_phy_mask(dev, 0x4eb, ~0x01c0);
bd3bf693	115	b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
dc713fb2 RM	116
	117	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
	118
	119	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	120	b43_radio_set(dev, 0x004, 0x40);
	121	b43_radio_set(dev, 0x120, 0x10);
	122	b43_radio_set(dev, 0x078, 0x80);
	123	b43_radio_set(dev, 0x129, 0x2);
	124	b43_radio_set(dev, 0x057, 0x1);
	125	b43_radio_set(dev, 0x05b, 0x2);
	126
	127	/* TODO: wait for some bit to be set */
	128	b43_radio_read(dev, 0x05c);
	129
	130	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	131	b43_radio_mask(dev, 0x057, (u16) ~0xff01);
	132
	133	b43_phy_write(dev, 0x933, 0x2d6b);
	134	b43_phy_write(dev, 0x934, 0x2d6b);
	135	b43_phy_write(dev, 0x935, 0x2d6b);
	136	b43_phy_write(dev, 0x936, 0x2d6b);
	137	b43_phy_write(dev, 0x937, 0x016b);
	138
	139	b43_radio_mask(dev, 0x057, (u16) ~0xff02);
	140	b43_radio_write(dev, 0x0c2, 0x006f);
	141	}
	142
78bc2463 RM	143	/**************************************************
	144	* Various PHY ops
	145	**************************************************/
	146
bce4dc4a	147	/* wlc_lcnphy_toggle_afe_pwdn */
78bc2463 RM	148	static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
	149	{
	150	u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
	151	u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
	152
	153	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 \| 0x1);
	154	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 \| 0x1);
	155
	156	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
	157	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
	158
	159	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
	160	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
	161	}
	162
bce4dc4a RM	163	/* wlc_lcnphy_clear_tx_power_offsets */
bce4dc4a RM	164	static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)
78bc2463 RM	165	{
	166	u8 i;
	167
cf577fc2 RM	168	if (1) { /* FIXME */
	169	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) \| 0x340);
	170	for (i = 0; i < 30; i++) {
	171	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
	172	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	173	}
78bc2463 RM	174	}
	175
	176	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) \| 0x80);
	177	for (i = 0; i < 64; i++) {
	178	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
	179	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	180	}
	181	}
	182
bce4dc4a RM	183	/* wlc_lcnphy_rev0_baseband_init */
bce4dc4a RM	184	static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)
bd3bf693 RM	185	{
	186	b43_radio_write(dev, 0x11c, 0);
	187
	188	b43_phy_write(dev, 0x43b, 0);
	189	b43_phy_write(dev, 0x43c, 0);
	190	b43_phy_write(dev, 0x44c, 0);
	191	b43_phy_write(dev, 0x4e6, 0);
	192	b43_phy_write(dev, 0x4f9, 0);
	193	b43_phy_write(dev, 0x4b0, 0);
	194	b43_phy_write(dev, 0x938, 0);
	195	b43_phy_write(dev, 0x4b0, 0);
	196	b43_phy_write(dev, 0x44e, 0);
	197
	198	b43_phy_set(dev, 0x567, 0x03);
	199
	200	b43_phy_set(dev, 0x44a, 0x44);
	201	b43_phy_write(dev, 0x44a, 0x80);
	202
cf577fc2 RM	203	if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))
cf577fc2 RM	204	; /* TODO */
bd3bf693	205	b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
cf577fc2 RM	206	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {
	207	b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
	208	b43_phy_write(dev, 0x910, 0x1);
	209	}
bd3bf693 RM	210
	211	b43_phy_write(dev, 0x910, 0x1);
	212
	213	b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
	214	b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
	215	b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
bce4dc4a	216	}
bd3bf693	217
bce4dc4a RM	218	/* wlc_lcnphy_bu_tweaks */
	219	static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
	220	{
bd3bf693 RM	221	b43_phy_set(dev, 0x805, 0x1);
	222
	223	b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
	224	b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
	225
	226	b43_phy_write(dev, 0x414, 0x1e10);
	227	b43_phy_write(dev, 0x415, 0x0640);
	228
	229	b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
	230
	231	b43_phy_set(dev, 0x44a, 0x44);
	232	b43_phy_write(dev, 0x44a, 0x80);
	233
	234	b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
	235	b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
	236
cf577fc2 RM	237	if (dev->dev->bus_sprom->board_rev >= 0x1204)
cf577fc2 RM	238	b43_radio_set(dev, 0x09b, 0xf0);
bd3bf693 RM	239
	240	b43_phy_write(dev, 0x7d6, 0x0902);
	241
	242	/* TODO: more ops */
bce4dc4a RM	243
	244	if (dev->phy.rev == 1) {
	245	/* TODO: more ops */
	246
	247	b43_phy_lcn_clear_tx_power_offsets(dev);
	248	}
bd3bf693 RM	249	}
bd3bf693 RM	250
bce4dc4a RM	251	/* wlc_lcnphy_vbat_temp_sense_setup */
bce4dc4a RM	252	static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
765b07e4 RM	253	{
	254	u8 i;
	255
	256	u16 save_radio_regs[6][2] = {
	257	{ 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
	258	{ 0x025, 0 }, { 0x112, 0 },
	259	};
	260	u16 save_phy_regs[14][2] = {
	261	{ 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
	262	{ 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
	263	{ 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
	264	{ 0x40d, 0 }, { 0x4a2, 0 },
	265	};
	266	u16 save_radio_4a4;
	267
	268	for (i = 0; i < 6; i++)
	269	save_radio_regs[i][1] = b43_radio_read(dev,
	270	save_radio_regs[i][0]);
	271	for (i = 0; i < 14; i++)
	272	save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
	273	save_radio_4a4 = b43_radio_read(dev, 0x4a4);
	274
	275	/* TODO: config sth */
	276
	277	for (i = 0; i < 6; i++)
	278	b43_radio_write(dev, save_radio_regs[i][0],
	279	save_radio_regs[i][1]);
	280	for (i = 0; i < 14; i++)
	281	b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
	282	b43_radio_write(dev, 0x4a4, save_radio_4a4);
	283	}
	284
39f7d33c RM	285	/**************************************************
	286	* Channel switching ops.
	287	**************************************************/
	288
b534706a RM	289	/* wlc_lcnphy_set_chanspec_tweaks */
b534706a RM	290	static void b43_phy_lcn_set_channel_tweaks(struct b43_wldev *dev, int channel)
39f7d33c	291	{
b534706a RM	292	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;
	293
	294	b43_phy_maskset(dev, 0x448, ~0x300, (channel == 14) ? 0x200 : 0x100);
	295
	296	if (channel == 1 \|\| channel == 2 \|\| channel == 3 \|\| channel == 4 \|\|
	297	channel == 9 \|\| channel == 10 \|\| channel == 11 \|\| channel == 12) {
	298	bcma_chipco_pll_write(cc, 0x2, 0x03000c04);
	299	bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x0);
	300	bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
	301
	302	bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400);
	303
	304	b43_phy_write(dev, 0x942, 0);
	305
	306	/* b43_phy_lcn_txrx_spur_avoidance_mode(dev, false); */
	307	b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1b00);
	308	b43_phy_write(dev, 0x425, 0x5907);
	309	} else {
	310	bcma_chipco_pll_write(cc, 0x2, 0x03140c04);
	311	bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x333333);
	312	bcma_chipco_pll_write(cc, 0x4, 0x202c2820);
	313
	314	bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400);
	315
	316	b43_phy_write(dev, 0x942, 0);
	317
	318	/* b43_phy_lcn_txrx_spur_avoidance_mode(dev, true); */
	319	b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1f00);
	320	b43_phy_write(dev, 0x425, 0x590a);
	321	}
39f7d33c RM	322
	323	b43_phy_set(dev, 0x44a, 0x44);
	324	b43_phy_write(dev, 0x44a, 0x80);
b534706a RM	325	}
	326
	327	/* wlc_phy_chanspec_set_lcnphy */
	328	static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
	329	struct ieee80211_channel *channel,
	330	enum nl80211_channel_type channel_type)
	331	{
	332	b43_phy_lcn_set_channel_tweaks(dev, channel->hw_value);
39f7d33c RM	333
	334	b43_phy_set(dev, 0x44a, 0x44);
	335	b43_phy_write(dev, 0x44a, 0x80);
	336
	337	b43_radio_2064_channel_setup(dev);
	338	mdelay(1);
	339
	340	b43_phy_lcn_afe_set_unset(dev);
	341
	342	/* TODO */
	343
	344	return 0;
	345	}
	346
f928668f RM	347	/**************************************************
	348	* Basic PHY ops.
	349	**************************************************/
	350
	351	static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
	352	{
	353	struct b43_phy_lcn *phy_lcn;
	354
	355	phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
	356	if (!phy_lcn)
	357	return -ENOMEM;
	358	dev->phy.lcn = phy_lcn;
	359
	360	return 0;
	361	}
	362
	363	static void b43_phy_lcn_op_free(struct b43_wldev *dev)
	364	{
	365	struct b43_phy *phy = &dev->phy;
	366	struct b43_phy_lcn *phy_lcn = phy->lcn;
	367
	368	kfree(phy_lcn);
	369	phy->lcn = NULL;
	370	}
	371
	372	static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
	373	{
	374	struct b43_phy *phy = &dev->phy;
	375	struct b43_phy_lcn *phy_lcn = phy->lcn;
	376
	377	memset(phy_lcn, 0, sizeof(*phy_lcn));
	378	}
	379
bce4dc4a	380	/* wlc_phy_init_lcnphy */
78bc2463 RM	381	static int b43_phy_lcn_op_init(struct b43_wldev *dev)
78bc2463 RM	382	{
b534706a RM	383	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;
b534706a RM	384
78bc2463 RM	385	b43_phy_set(dev, 0x44a, 0x80);
	386	b43_phy_mask(dev, 0x44a, 0x7f);
	387	b43_phy_set(dev, 0x6d1, 0x80);
	388	b43_phy_write(dev, 0x6d0, 0x7);
	389
	390	b43_phy_lcn_afe_set_unset(dev);
	391
	392	b43_phy_write(dev, 0x60a, 0xa0);
	393	b43_phy_write(dev, 0x46a, 0x19);
	394	b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
	395
	396	b43_phy_lcn_tables_init(dev);
78bc2463	397
bce4dc4a RM	398	b43_phy_lcn_rev0_baseband_init(dev);
bce4dc4a RM	399	b43_phy_lcn_bu_tweaks(dev);
78bc2463	400
dc713fb2 RM	401	if (dev->phy.radio_ver == 0x2064)
	402	b43_radio_2064_init(dev);
	403	else
	404	B43_WARN_ON(1);
	405
bce4dc4a	406	b43_phy_lcn_sense_setup(dev);
765b07e4	407
b534706a RM	408	b43_switch_channel(dev, dev->phy.channel);
	409
	410	bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9);
	411	bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd);
	412
	413	/* TODO */
	414
	415	b43_phy_set(dev, 0x448, 0x4000);
	416	udelay(100);
	417	b43_phy_mask(dev, 0x448, ~0x4000);
	418
	419	/* TODO */
	420
78bc2463 RM	421	return 0;
	422	}
	423
ba356b56 RM	424	static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
	425	bool blocked)
	426	{
	427	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
	428	b43err(dev->wl, "MAC not suspended\n");
	429
	430	if (blocked) {
	431	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
	432	b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
	433
	434	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
	435	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
	436	b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
	437
	438	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
	439	b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
	440	} else {
78bc2463 RM	441	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
	442	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
	443	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
ba356b56 RM	444	}
	445	}
	446
7ed88528 RM	447	static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
	448	{
	449	if (on) {
	450	b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
	451	} else {
	452	b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
	453	b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
	454	}
	455	}
	456
39f7d33c RM	457	static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
	458	unsigned int new_channel)
	459	{
	460	struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
	461	enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
	462
	463	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
	464	if ((new_channel < 1) \|\| (new_channel > 14))
	465	return -EINVAL;
	466	} else {
	467	return -EINVAL;
	468	}
	469
	470	return b43_phy_lcn_set_channel(dev, channel, channel_type);
	471	}
	472
f928668f RM	473	static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
	474	{
	475	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
	476	return 1;
	477	return 36;
	478	}
	479
	480	static enum b43_txpwr_result
	481	b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
	482	{
	483	return B43_TXPWR_RES_DONE;
	484	}
	485
	486	static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
	487	{
	488	}
	489
f533d0fa RM	490	/**************************************************
	491	* R/W ops.
	492	**************************************************/
	493
	494	static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
	495	{
	496	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	497	return b43_read16(dev, B43_MMIO_PHY_DATA);
	498	}
	499
	500	static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
	501	{
	502	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	503	b43_write16(dev, B43_MMIO_PHY_DATA, value);
	504	}
	505
	506	static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
	507	u16 set)
	508	{
	509	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	510	b43_write16(dev, B43_MMIO_PHY_DATA,
	511	(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) \| set);
	512	}
	513
	514	static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
	515	{
	516	/* LCN-PHY needs 0x200 for read access */
	517	reg \|= 0x200;
	518
	519	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	520	return b43_read16(dev, B43_MMIO_RADIO24_DATA);
	521	}
	522
	523	static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
	524	u16 value)
	525	{
	526	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	527	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
	528	}
	529
1d738e64 RM	530	/**************************************************
	531	* PHY ops struct.
	532	**************************************************/
	533
	534	const struct b43_phy_operations b43_phyops_lcn = {
1d738e64 RM	535	.allocate = b43_phy_lcn_op_allocate,
	536	.free = b43_phy_lcn_op_free,
	537	.prepare_structs = b43_phy_lcn_op_prepare_structs,
	538	.init = b43_phy_lcn_op_init,
	539	.phy_read = b43_phy_lcn_op_read,
	540	.phy_write = b43_phy_lcn_op_write,
	541	.phy_maskset = b43_phy_lcn_op_maskset,
	542	.radio_read = b43_phy_lcn_op_radio_read,
	543	.radio_write = b43_phy_lcn_op_radio_write,
	544	.software_rfkill = b43_phy_lcn_op_software_rfkill,
	545	.switch_analog = b43_phy_lcn_op_switch_analog,
	546	.switch_channel = b43_phy_lcn_op_switch_channel,
	547	.get_default_chan = b43_phy_lcn_op_get_default_chan,
	548	.recalc_txpower = b43_phy_lcn_op_recalc_txpower,
	549	.adjust_txpower = b43_phy_lcn_op_adjust_txpower,
1d738e64	550	};