[deliverable/linux.git] / drivers / net / wireless / b43 / phy_lcn.c

/*

  Broadcom B43 wireless driver
  IEEE 802.11n LCN-PHY support

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include <linux/slab.h>

#include "b43.h"
#include "phy_lcn.h"
#include "tables_phy_lcn.h"
#include "main.h"

/**************************************************
 * Radio 2064.
 **************************************************/

/* wlc_lcnphy_radio_2064_channel_tune_4313 */
static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
{
	u16 save[2];

	b43_radio_set(dev, 0x09d, 0x4);
	b43_radio_write(dev, 0x09e, 0xf);

	/* Channel specific values in theory, in practice always the same */
	b43_radio_write(dev, 0x02a, 0xb);
	b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
	b43_radio_maskset(dev, 0x091, ~0x3, 0);
	b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
	b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
	b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
	b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
	b43_radio_write(dev, 0x06c, 0x80);

	save[0] = b43_radio_read(dev, 0x044);
	save[1] = b43_radio_read(dev, 0x12b);

	b43_radio_set(dev, 0x044, 0x7);
	b43_radio_set(dev, 0x12b, 0xe);

	/* TODO */

	b43_radio_write(dev, 0x040, 0xfb);

	b43_radio_write(dev, 0x041, 0x9a);
	b43_radio_write(dev, 0x042, 0xa3);
	b43_radio_write(dev, 0x043, 0x0c);

	/* TODO */

	b43_radio_set(dev, 0x044, 0x0c);
	udelay(1);

	b43_radio_write(dev, 0x044, save[0]);
	b43_radio_write(dev, 0x12b, save[1]);

	if (dev->phy.rev == 1) {
		/* brcmsmac uses outdated 0x3 for 0x038 */
		b43_radio_write(dev, 0x038, 0x0);
		b43_radio_write(dev, 0x091, 0x7);
	}
}

/* wlc_radio_2064_init */
static void b43_radio_2064_init(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		b43_radio_write(dev, 0x09c, 0x0020);
		b43_radio_write(dev, 0x105, 0x0008);
	} else {
		/* TODO */
	}
	b43_radio_write(dev, 0x032, 0x0062);
	b43_radio_write(dev, 0x033, 0x0019);
	b43_radio_write(dev, 0x090, 0x0010);
	b43_radio_write(dev, 0x010, 0x0000);
	if (dev->phy.rev == 1) {
		b43_radio_write(dev, 0x060, 0x007f);
		b43_radio_write(dev, 0x061, 0x0072);
		b43_radio_write(dev, 0x062, 0x007f);
	}
	b43_radio_write(dev, 0x01d, 0x0002);
	b43_radio_write(dev, 0x01e, 0x0006);

	b43_phy_write(dev, 0x4ea, 0x4688);
	b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
	b43_phy_mask(dev, 0x4eb, ~0x01c0);
	b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);

	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);

	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	b43_radio_set(dev, 0x004, 0x40);
	b43_radio_set(dev, 0x120, 0x10);
	b43_radio_set(dev, 0x078, 0x80);
	b43_radio_set(dev, 0x129, 0x2);
	b43_radio_set(dev, 0x057, 0x1);
	b43_radio_set(dev, 0x05b, 0x2);

	/* TODO: wait for some bit to be set */
	b43_radio_read(dev, 0x05c);

	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	b43_radio_mask(dev, 0x057, (u16) ~0xff01);

	b43_phy_write(dev, 0x933, 0x2d6b);
	b43_phy_write(dev, 0x934, 0x2d6b);
	b43_phy_write(dev, 0x935, 0x2d6b);
	b43_phy_write(dev, 0x936, 0x2d6b);
	b43_phy_write(dev, 0x937, 0x016b);

	b43_radio_mask(dev, 0x057, (u16) ~0xff02);
	b43_radio_write(dev, 0x0c2, 0x006f);
}

/**************************************************
 * Various PHY ops
 **************************************************/

/* wlc_lcnphy_toggle_afe_pwdn */
static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
{
	u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
	u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);

	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
}

/* wlc_lcnphy_clear_tx_power_offsets */
static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)
{
	u8 i;

	if (1) { /* FIXME */
		b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
		for (i = 0; i < 30; i++) {
			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
		}
	}

	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
	for (i = 0; i < 64; i++) {
		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	}
}

/* wlc_lcnphy_rev0_baseband_init */
static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)
{
	b43_radio_write(dev, 0x11c, 0);

	b43_phy_write(dev, 0x43b, 0);
	b43_phy_write(dev, 0x43c, 0);
	b43_phy_write(dev, 0x44c, 0);
	b43_phy_write(dev, 0x4e6, 0);
	b43_phy_write(dev, 0x4f9, 0);
	b43_phy_write(dev, 0x4b0, 0);
	b43_phy_write(dev, 0x938, 0);
	b43_phy_write(dev, 0x4b0, 0);
	b43_phy_write(dev, 0x44e, 0);

	b43_phy_set(dev, 0x567, 0x03);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))
		; /* TODO */
	b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {
		b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
		b43_phy_write(dev, 0x910, 0x1);
	}

	b43_phy_write(dev, 0x910, 0x1);

	b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
	b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
	b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
}

/* wlc_lcnphy_bu_tweaks */
static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
{
	b43_phy_set(dev, 0x805, 0x1);

	b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
	b43_phy_maskset(dev, 0x030, ~0x7, 0x3);

	b43_phy_write(dev, 0x414, 0x1e10);
	b43_phy_write(dev, 0x415, 0x0640);

	b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
	b43_phy_maskset(dev, 0x420, ~0xff, 0x10);

	if (dev->dev->bus_sprom->board_rev >= 0x1204)
		b43_radio_set(dev, 0x09b, 0xf0);

	b43_phy_write(dev, 0x7d6, 0x0902);

	/* TODO: more ops */

	if (dev->phy.rev == 1) {
		/* TODO: more ops */

		b43_phy_lcn_clear_tx_power_offsets(dev);
	}
}

/* wlc_lcnphy_vbat_temp_sense_setup */
static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
{
	u8 i;

	u16 save_radio_regs[6][2] = {
		{ 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
		{ 0x025, 0 }, { 0x112, 0 },
	};
	u16 save_phy_regs[14][2] = {
		{ 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
		{ 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
		{ 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
		{ 0x40d, 0 }, { 0x4a2, 0 },
	};
	u16 save_radio_4a4;

	for (i = 0; i < 6; i++)
		save_radio_regs[i][1] = b43_radio_read(dev,
						       save_radio_regs[i][0]);
	for (i = 0; i < 14; i++)
		save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
	save_radio_4a4 = b43_radio_read(dev, 0x4a4);

	/* TODO: config sth */

	for (i = 0; i < 6; i++)
		b43_radio_write(dev, save_radio_regs[i][0],
				save_radio_regs[i][1]);
	for (i = 0; i < 14; i++)
		b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
	b43_radio_write(dev, 0x4a4, save_radio_4a4);
}

/**************************************************
 * Channel switching ops.
 **************************************************/

static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
				   struct ieee80211_channel *channel,
				   enum nl80211_channel_type channel_type)
{
	/* TODO: PLL and PHY ops */

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	b43_phy_set(dev, 0x44a, 0x44);
	b43_phy_write(dev, 0x44a, 0x80);

	b43_radio_2064_channel_setup(dev);
	mdelay(1);

	b43_phy_lcn_afe_set_unset(dev);

	/* TODO */

	return 0;
}

/**************************************************
 * Basic PHY ops.
 **************************************************/

static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
{
	struct b43_phy_lcn *phy_lcn;

	phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
	if (!phy_lcn)
		return -ENOMEM;
	dev->phy.lcn = phy_lcn;

	return 0;
}

static void b43_phy_lcn_op_free(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_lcn *phy_lcn = phy->lcn;

	kfree(phy_lcn);
	phy->lcn = NULL;
}

static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_lcn *phy_lcn = phy->lcn;

	memset(phy_lcn, 0, sizeof(*phy_lcn));
}

/* wlc_phy_init_lcnphy */
static int b43_phy_lcn_op_init(struct b43_wldev *dev)
{
	b43_phy_set(dev, 0x44a, 0x80);
	b43_phy_mask(dev, 0x44a, 0x7f);
	b43_phy_set(dev, 0x6d1, 0x80);
	b43_phy_write(dev, 0x6d0, 0x7);

	b43_phy_lcn_afe_set_unset(dev);

	b43_phy_write(dev, 0x60a, 0xa0);
	b43_phy_write(dev, 0x46a, 0x19);
	b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);

	b43_phy_lcn_tables_init(dev);

	b43_phy_lcn_rev0_baseband_init(dev);
	b43_phy_lcn_bu_tweaks(dev);

	if (dev->phy.radio_ver == 0x2064)
		b43_radio_2064_init(dev);
	else
		B43_WARN_ON(1);

	b43_phy_lcn_sense_setup(dev);

	return 0;
}

static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
					bool blocked)
{
	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
		b43err(dev->wl, "MAC not suspended\n");

	if (blocked) {
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);

		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);

		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
		b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
	} else {
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
	}
}

static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
{
	if (on) {
		b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
	} else {
		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
	}
}

static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
					unsigned int new_channel)
{
	struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
	enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;

	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		if ((new_channel < 1) || (new_channel > 14))
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	return b43_phy_lcn_set_channel(dev, channel, channel_type);
}

static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		return 1;
	return 36;
}

static enum b43_txpwr_result
b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
{
	return B43_TXPWR_RES_DONE;
}

static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
{
}

/**************************************************
 * R/W ops.
 **************************************************/

static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
				   u16 set)
{
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA,
		    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
}

static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
{
	/* LCN-PHY needs 0x200 for read access */
	reg |= 0x200;

	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_RADIO24_DATA);
}

static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
				       u16 value)
{
	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
}

/**************************************************
 * PHY ops struct.
 **************************************************/

const struct b43_phy_operations b43_phyops_lcn = {
	.allocate		= b43_phy_lcn_op_allocate,
	.free			= b43_phy_lcn_op_free,
	.prepare_structs	= b43_phy_lcn_op_prepare_structs,
	.init			= b43_phy_lcn_op_init,
	.phy_read		= b43_phy_lcn_op_read,
	.phy_write		= b43_phy_lcn_op_write,
	.phy_maskset		= b43_phy_lcn_op_maskset,
	.radio_read		= b43_phy_lcn_op_radio_read,
	.radio_write		= b43_phy_lcn_op_radio_write,
	.software_rfkill	= b43_phy_lcn_op_software_rfkill,
	.switch_analog		= b43_phy_lcn_op_switch_analog,
	.switch_channel		= b43_phy_lcn_op_switch_channel,
	.get_default_chan	= b43_phy_lcn_op_get_default_chan,
	.recalc_txpower		= b43_phy_lcn_op_recalc_txpower,
	.adjust_txpower		= b43_phy_lcn_op_adjust_txpower,
};
Commit	Line	Data
1d738e64 RM	1	/*
	2
	3	Broadcom B43 wireless driver
	4	IEEE 802.11n LCN-PHY support
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; see the file COPYING. If not, write to
	18	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	19	Boston, MA 02110-1301, USA.
	20
	21	*/
	22
	23	#include <linux/slab.h>
	24
	25	#include "b43.h"
	26	#include "phy_lcn.h"
	27	#include "tables_phy_lcn.h"
	28	#include "main.h"
	29
dc713fb2 RM	30	/**************************************************
	31	* Radio 2064.
	32	**************************************************/
	33
bce4dc4a	34	/* wlc_lcnphy_radio_2064_channel_tune_4313 */
39f7d33c RM	35	static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
	36	{
	37	u16 save[2];
	38
	39	b43_radio_set(dev, 0x09d, 0x4);
	40	b43_radio_write(dev, 0x09e, 0xf);
	41
cf577fc2	42	/* Channel specific values in theory, in practice always the same */
39f7d33c RM	43	b43_radio_write(dev, 0x02a, 0xb);
	44	b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
	45	b43_radio_maskset(dev, 0x091, ~0x3, 0);
	46	b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
	47	b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
	48	b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
	49	b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
	50	b43_radio_write(dev, 0x06c, 0x80);
	51
	52	save[0] = b43_radio_read(dev, 0x044);
	53	save[1] = b43_radio_read(dev, 0x12b);
	54
	55	b43_radio_set(dev, 0x044, 0x7);
	56	b43_radio_set(dev, 0x12b, 0xe);
	57
	58	/* TODO */
	59
	60	b43_radio_write(dev, 0x040, 0xfb);
	61
	62	b43_radio_write(dev, 0x041, 0x9a);
	63	b43_radio_write(dev, 0x042, 0xa3);
	64	b43_radio_write(dev, 0x043, 0x0c);
	65
	66	/* TODO */
	67
	68	b43_radio_set(dev, 0x044, 0x0c);
	69	udelay(1);
	70
	71	b43_radio_write(dev, 0x044, save[0]);
	72	b43_radio_write(dev, 0x12b, save[1]);
	73
cf577fc2 RM	74	if (dev->phy.rev == 1) {
	75	/* brcmsmac uses outdated 0x3 for 0x038 */
	76	b43_radio_write(dev, 0x038, 0x0);
	77	b43_radio_write(dev, 0x091, 0x7);
	78	}
39f7d33c RM	79	}
39f7d33c RM	80
bce4dc4a	81	/* wlc_radio_2064_init */
dc713fb2 RM	82	static void b43_radio_2064_init(struct b43_wldev *dev)
dc713fb2 RM	83	{
cf577fc2 RM	84	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
	85	b43_radio_write(dev, 0x09c, 0x0020);
	86	b43_radio_write(dev, 0x105, 0x0008);
	87	} else {
	88	/* TODO */
	89	}
dc713fb2 RM	90	b43_radio_write(dev, 0x032, 0x0062);
	91	b43_radio_write(dev, 0x033, 0x0019);
	92	b43_radio_write(dev, 0x090, 0x0010);
	93	b43_radio_write(dev, 0x010, 0x0000);
cf577fc2 RM	94	if (dev->phy.rev == 1) {
	95	b43_radio_write(dev, 0x060, 0x007f);
	96	b43_radio_write(dev, 0x061, 0x0072);
	97	b43_radio_write(dev, 0x062, 0x007f);
	98	}
dc713fb2 RM	99	b43_radio_write(dev, 0x01d, 0x0002);
	100	b43_radio_write(dev, 0x01e, 0x0006);
	101
	102	b43_phy_write(dev, 0x4ea, 0x4688);
	103	b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
	104	b43_phy_mask(dev, 0x4eb, ~0x01c0);
bd3bf693	105	b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
dc713fb2 RM	106
	107	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
	108
	109	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	110	b43_radio_set(dev, 0x004, 0x40);
	111	b43_radio_set(dev, 0x120, 0x10);
	112	b43_radio_set(dev, 0x078, 0x80);
	113	b43_radio_set(dev, 0x129, 0x2);
	114	b43_radio_set(dev, 0x057, 0x1);
	115	b43_radio_set(dev, 0x05b, 0x2);
	116
	117	/* TODO: wait for some bit to be set */
	118	b43_radio_read(dev, 0x05c);
	119
	120	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
	121	b43_radio_mask(dev, 0x057, (u16) ~0xff01);
	122
	123	b43_phy_write(dev, 0x933, 0x2d6b);
	124	b43_phy_write(dev, 0x934, 0x2d6b);
	125	b43_phy_write(dev, 0x935, 0x2d6b);
	126	b43_phy_write(dev, 0x936, 0x2d6b);
	127	b43_phy_write(dev, 0x937, 0x016b);
	128
	129	b43_radio_mask(dev, 0x057, (u16) ~0xff02);
	130	b43_radio_write(dev, 0x0c2, 0x006f);
	131	}
	132
78bc2463 RM	133	/**************************************************
	134	* Various PHY ops
	135	**************************************************/
	136
bce4dc4a	137	/* wlc_lcnphy_toggle_afe_pwdn */
78bc2463 RM	138	static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
	139	{
	140	u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
	141	u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
	142
	143	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 \| 0x1);
	144	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 \| 0x1);
	145
	146	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
	147	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
	148
	149	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
	150	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
	151	}
	152
bce4dc4a RM	153	/* wlc_lcnphy_clear_tx_power_offsets */
bce4dc4a RM	154	static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)
78bc2463 RM	155	{
	156	u8 i;
	157
cf577fc2 RM	158	if (1) { /* FIXME */
	159	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) \| 0x340);
	160	for (i = 0; i < 30; i++) {
	161	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
	162	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	163	}
78bc2463 RM	164	}
	165
	166	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) \| 0x80);
	167	for (i = 0; i < 64; i++) {
	168	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
	169	b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
	170	}
	171	}
	172
bce4dc4a RM	173	/* wlc_lcnphy_rev0_baseband_init */
bce4dc4a RM	174	static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)
bd3bf693 RM	175	{
	176	b43_radio_write(dev, 0x11c, 0);
	177
	178	b43_phy_write(dev, 0x43b, 0);
	179	b43_phy_write(dev, 0x43c, 0);
	180	b43_phy_write(dev, 0x44c, 0);
	181	b43_phy_write(dev, 0x4e6, 0);
	182	b43_phy_write(dev, 0x4f9, 0);
	183	b43_phy_write(dev, 0x4b0, 0);
	184	b43_phy_write(dev, 0x938, 0);
	185	b43_phy_write(dev, 0x4b0, 0);
	186	b43_phy_write(dev, 0x44e, 0);
	187
	188	b43_phy_set(dev, 0x567, 0x03);
	189
	190	b43_phy_set(dev, 0x44a, 0x44);
	191	b43_phy_write(dev, 0x44a, 0x80);
	192
cf577fc2 RM	193	if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))
cf577fc2 RM	194	; /* TODO */
bd3bf693	195	b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
cf577fc2 RM	196	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {
	197	b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
	198	b43_phy_write(dev, 0x910, 0x1);
	199	}
bd3bf693 RM	200
	201	b43_phy_write(dev, 0x910, 0x1);
	202
	203	b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
	204	b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
	205	b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
bce4dc4a	206	}
bd3bf693	207
bce4dc4a RM	208	/* wlc_lcnphy_bu_tweaks */
	209	static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
	210	{
bd3bf693 RM	211	b43_phy_set(dev, 0x805, 0x1);
	212
	213	b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
	214	b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
	215
	216	b43_phy_write(dev, 0x414, 0x1e10);
	217	b43_phy_write(dev, 0x415, 0x0640);
	218
	219	b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
	220
	221	b43_phy_set(dev, 0x44a, 0x44);
	222	b43_phy_write(dev, 0x44a, 0x80);
	223
	224	b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
	225	b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
	226
cf577fc2 RM	227	if (dev->dev->bus_sprom->board_rev >= 0x1204)
cf577fc2 RM	228	b43_radio_set(dev, 0x09b, 0xf0);
bd3bf693 RM	229
	230	b43_phy_write(dev, 0x7d6, 0x0902);
	231
	232	/* TODO: more ops */
bce4dc4a RM	233
	234	if (dev->phy.rev == 1) {
	235	/* TODO: more ops */
	236
	237	b43_phy_lcn_clear_tx_power_offsets(dev);
	238	}
bd3bf693 RM	239	}
bd3bf693 RM	240
bce4dc4a RM	241	/* wlc_lcnphy_vbat_temp_sense_setup */
bce4dc4a RM	242	static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
765b07e4 RM	243	{
	244	u8 i;
	245
	246	u16 save_radio_regs[6][2] = {
	247	{ 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
	248	{ 0x025, 0 }, { 0x112, 0 },
	249	};
	250	u16 save_phy_regs[14][2] = {
	251	{ 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
	252	{ 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
	253	{ 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
	254	{ 0x40d, 0 }, { 0x4a2, 0 },
	255	};
	256	u16 save_radio_4a4;
	257
	258	for (i = 0; i < 6; i++)
	259	save_radio_regs[i][1] = b43_radio_read(dev,
	260	save_radio_regs[i][0]);
	261	for (i = 0; i < 14; i++)
	262	save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
	263	save_radio_4a4 = b43_radio_read(dev, 0x4a4);
	264
	265	/* TODO: config sth */
	266
	267	for (i = 0; i < 6; i++)
	268	b43_radio_write(dev, save_radio_regs[i][0],
	269	save_radio_regs[i][1]);
	270	for (i = 0; i < 14; i++)
	271	b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
	272	b43_radio_write(dev, 0x4a4, save_radio_4a4);
	273	}
	274
39f7d33c RM	275	/**************************************************
	276	* Channel switching ops.
	277	**************************************************/
	278
	279	static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
	280	struct ieee80211_channel *channel,
	281	enum nl80211_channel_type channel_type)
	282	{
	283	/* TODO: PLL and PHY ops */
	284
	285	b43_phy_set(dev, 0x44a, 0x44);
	286	b43_phy_write(dev, 0x44a, 0x80);
	287
	288	b43_phy_set(dev, 0x44a, 0x44);
	289	b43_phy_write(dev, 0x44a, 0x80);
	290
	291	b43_radio_2064_channel_setup(dev);
	292	mdelay(1);
	293
	294	b43_phy_lcn_afe_set_unset(dev);
	295
	296	/* TODO */
	297
	298	return 0;
	299	}
	300
f928668f RM	301	/**************************************************
	302	* Basic PHY ops.
	303	**************************************************/
	304
	305	static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
	306	{
	307	struct b43_phy_lcn *phy_lcn;
	308
	309	phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
	310	if (!phy_lcn)
	311	return -ENOMEM;
	312	dev->phy.lcn = phy_lcn;
	313
	314	return 0;
	315	}
	316
	317	static void b43_phy_lcn_op_free(struct b43_wldev *dev)
	318	{
	319	struct b43_phy *phy = &dev->phy;
	320	struct b43_phy_lcn *phy_lcn = phy->lcn;
	321
	322	kfree(phy_lcn);
	323	phy->lcn = NULL;
	324	}
	325
	326	static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
	327	{
	328	struct b43_phy *phy = &dev->phy;
	329	struct b43_phy_lcn *phy_lcn = phy->lcn;
	330
	331	memset(phy_lcn, 0, sizeof(*phy_lcn));
	332	}
	333
bce4dc4a	334	/* wlc_phy_init_lcnphy */
78bc2463 RM	335	static int b43_phy_lcn_op_init(struct b43_wldev *dev)
	336	{
	337	b43_phy_set(dev, 0x44a, 0x80);
	338	b43_phy_mask(dev, 0x44a, 0x7f);
	339	b43_phy_set(dev, 0x6d1, 0x80);
	340	b43_phy_write(dev, 0x6d0, 0x7);
	341
	342	b43_phy_lcn_afe_set_unset(dev);
	343
	344	b43_phy_write(dev, 0x60a, 0xa0);
	345	b43_phy_write(dev, 0x46a, 0x19);
	346	b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
	347
	348	b43_phy_lcn_tables_init(dev);
78bc2463	349
bce4dc4a RM	350	b43_phy_lcn_rev0_baseband_init(dev);
bce4dc4a RM	351	b43_phy_lcn_bu_tweaks(dev);
78bc2463	352
dc713fb2 RM	353	if (dev->phy.radio_ver == 0x2064)
	354	b43_radio_2064_init(dev);
	355	else
	356	B43_WARN_ON(1);
	357
bce4dc4a	358	b43_phy_lcn_sense_setup(dev);
765b07e4	359
78bc2463 RM	360	return 0;
	361	}
	362
ba356b56 RM	363	static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
	364	bool blocked)
	365	{
	366	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
	367	b43err(dev->wl, "MAC not suspended\n");
	368
	369	if (blocked) {
	370	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
	371	b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
	372
	373	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
	374	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
	375	b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
	376
	377	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
	378	b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
	379	} else {
78bc2463 RM	380	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
	381	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
	382	b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
ba356b56 RM	383	}
	384	}
	385
7ed88528 RM	386	static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
	387	{
	388	if (on) {
	389	b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
	390	} else {
	391	b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
	392	b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
	393	}
	394	}
	395
39f7d33c RM	396	static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
	397	unsigned int new_channel)
	398	{
	399	struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
	400	enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
	401
	402	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
	403	if ((new_channel < 1) \|\| (new_channel > 14))
	404	return -EINVAL;
	405	} else {
	406	return -EINVAL;
	407	}
	408
	409	return b43_phy_lcn_set_channel(dev, channel, channel_type);
	410	}
	411
f928668f RM	412	static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
	413	{
	414	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
	415	return 1;
	416	return 36;
	417	}
	418
	419	static enum b43_txpwr_result
	420	b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
	421	{
	422	return B43_TXPWR_RES_DONE;
	423	}
	424
	425	static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
	426	{
	427	}
	428
f533d0fa RM	429	/**************************************************
	430	* R/W ops.
	431	**************************************************/
	432
	433	static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
	434	{
	435	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	436	return b43_read16(dev, B43_MMIO_PHY_DATA);
	437	}
	438
	439	static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
	440	{
	441	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	442	b43_write16(dev, B43_MMIO_PHY_DATA, value);
	443	}
	444
	445	static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
	446	u16 set)
	447	{
	448	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	449	b43_write16(dev, B43_MMIO_PHY_DATA,
	450	(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) \| set);
	451	}
	452
	453	static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
	454	{
	455	/* LCN-PHY needs 0x200 for read access */
	456	reg \|= 0x200;
	457
	458	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	459	return b43_read16(dev, B43_MMIO_RADIO24_DATA);
	460	}
	461
	462	static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
	463	u16 value)
	464	{
	465	b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
	466	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
	467	}
	468
1d738e64 RM	469	/**************************************************
	470	* PHY ops struct.
	471	**************************************************/
	472
	473	const struct b43_phy_operations b43_phyops_lcn = {
1d738e64 RM	474	.allocate = b43_phy_lcn_op_allocate,
	475	.free = b43_phy_lcn_op_free,
	476	.prepare_structs = b43_phy_lcn_op_prepare_structs,
	477	.init = b43_phy_lcn_op_init,
	478	.phy_read = b43_phy_lcn_op_read,
	479	.phy_write = b43_phy_lcn_op_write,
	480	.phy_maskset = b43_phy_lcn_op_maskset,
	481	.radio_read = b43_phy_lcn_op_radio_read,
	482	.radio_write = b43_phy_lcn_op_radio_write,
	483	.software_rfkill = b43_phy_lcn_op_software_rfkill,
	484	.switch_analog = b43_phy_lcn_op_switch_analog,
	485	.switch_channel = b43_phy_lcn_op_switch_channel,
	486	.get_default_chan = b43_phy_lcn_op_get_default_chan,
	487	.recalc_txpower = b43_phy_lcn_op_recalc_txpower,
	488	.adjust_txpower = b43_phy_lcn_op_adjust_txpower,
1d738e64	489	};