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b43: LP-PHY: Fix setting TX power control mode during RC calibration
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_lp.c
CommitLineData
e63e4363
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
6c1bb927 6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
e63e4363
MB		 7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
ce1a9ee3 26#include "main.h"
e63e4363
MB		 27#include "phy_lp.h"
28#include "phy_common.h"
6c1bb927 29#include "tables_lpphy.h"
e63e4363
MB		 30
31
588f8377
GS		 32static inline u16 channel2freq_lp(u8 channel)
33{
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42}
43
44static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45{
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49}
50
e63e4363
MB		 51static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52{
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
e63e4363
MB		 60 return 0;
61}
62
fb11137a 63static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
e63e4363 64{
fb11137a
MB		 65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
e63e4363 67
fb11137a 68 memset(lpphy, 0, sizeof(*lpphy));
e63e4363 69
fb11137a 70 //TODO
e63e4363
MB		 71}
72
fb11137a 73static void b43_lpphy_op_free(struct b43_wldev *dev)
e63e4363
MB		 74{
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
e63e4363
MB		 77 kfree(lpphy);
78 dev->phy.lp = NULL;
79}
80
84ec167d
GS		 81static void lpphy_read_band_sprom(struct b43_wldev *dev)
82{
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162}
163
588f8377 164static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
c65d6fbf
GS		 165{
166 struct b43_phy_lp *lpphy = dev->phy.lp;
c65d6fbf
GS		 167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187}
188
a387cc7d
MB		 189static void lpphy_table_init(struct b43_wldev *dev)
190{
588f8377
GS		 191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
c65d6fbf
GS		 193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
588f8377 201 lpphy_adjust_gain_table(dev, freq);
a387cc7d
MB		 202}
203
204static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205{
738f0f43 206 struct ssb_bus *bus = dev->dev->bus;
96909e97 207 struct b43_phy_lp *lpphy = dev->phy.lp;
738f0f43
GS		 208 u16 tmp, tmp2;
209
96909e97
GS		 210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 /* TODO:
238 * Set the LDO voltage to 0x0028 - FIXME: What is this?
239 * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
240 * as arguments
241 * Call sb_pmu_paref_ldo_enable with argument TRUE
242 */
243 if (dev->phy.rev == 0) {
244 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
245 0xFFCF, 0x0010);
246 }
247 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
248 } else {
249 //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
250 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
251 0xFFCF, 0x0020);
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
253 }
254 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
255 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
256 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
257 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
258 else
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
260 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
261 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
262 0xFFF9, (lpphy->bx_arch << 1));
738f0f43
GS		 263 if (dev->phy.rev == 1 &&
264 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
281 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
282 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
283 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
292 } else if (dev->phy.rev == 1 ||
293 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
302 } else {
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
311 }
96909e97 312 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
738f0f43
GS		 313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
314 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
317 }
318 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
319 (bus->chip_id == 0x5354) &&
320 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
321 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
322 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
323 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
96909e97 324 //FIXME the Broadcom driver caches & delays this HF write!
7c81e98a 325 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
738f0f43
GS		 326 }
327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
328 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
330 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
331 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
332 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
333 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
334 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
335 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
336 } else { /* 5GHz */
337 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
338 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
339 }
340 if (dev->phy.rev == 1) {
341 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
342 tmp2 = (tmp & 0x03E0) >> 5;
343 tmp2 |= tmp << 5;
344 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
346 tmp2 = (tmp & 0x1F00) >> 8;
347 tmp2 |= tmp << 5;
348 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
349 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
350 tmp2 = tmp & 0x00FF;
351 tmp2 |= tmp << 8;
352 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
353 }
a387cc7d
MB		 354}
355
a3e14f3d
GS		 356static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
357{
358 static const u16 addr[] = {
359 B43_PHY_OFDM(0xC1),
360 B43_PHY_OFDM(0xC2),
361 B43_PHY_OFDM(0xC3),
362 B43_PHY_OFDM(0xC4),
363 B43_PHY_OFDM(0xC5),
364 B43_PHY_OFDM(0xC6),
365 B43_PHY_OFDM(0xC7),
366 B43_PHY_OFDM(0xC8),
367 B43_PHY_OFDM(0xCF),
368 };
369
370 static const u16 coefs[] = {
371 0xDE5E, 0xE832, 0xE331, 0x4D26,
372 0x0026, 0x1420, 0x0020, 0xFE08,
373 0x0008,
374 };
375
376 struct b43_phy_lp *lpphy = dev->phy.lp;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(addr); i++) {
380 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
381 b43_phy_write(dev, addr[i], coefs[i]);
382 }
383}
384
385static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
386{
387 static const u16 addr[] = {
388 B43_PHY_OFDM(0xC1),
389 B43_PHY_OFDM(0xC2),
390 B43_PHY_OFDM(0xC3),
391 B43_PHY_OFDM(0xC4),
392 B43_PHY_OFDM(0xC5),
393 B43_PHY_OFDM(0xC6),
394 B43_PHY_OFDM(0xC7),
395 B43_PHY_OFDM(0xC8),
396 B43_PHY_OFDM(0xCF),
397 };
398
399 struct b43_phy_lp *lpphy = dev->phy.lp;
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(addr); i++)
403 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
404}
405
a387cc7d
MB		 406static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407{
686aa5f2 408 struct ssb_bus *bus = dev->dev->bus;
6c1bb927
MB		 409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
a3e14f3d 420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
6c1bb927
MB		 421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
a3e14f3d
GS		 428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
6c1bb927 434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
24b5bcc6 435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
6c1bb927
MB		 436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
96909e97 442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
6c1bb927
MB		 443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
686aa5f2
MB		 445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
6c1bb927
MB		 452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
96909e97 463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
a3e14f3d
GS		 464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
6c1bb927
MB		 467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
96909e97 474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
6c1bb927
MB		 475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
a3e14f3d
GS		 487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
a387cc7d
MB		 495}
496
497static void lpphy_baseband_init(struct b43_wldev *dev)
498{
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504}
505
24b5bcc6
MB		 506struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509};
510
511/* Initialize the 2062 radio. */
512static void lpphy_2062_init(struct b43_wldev *dev)
513{
1e711bee 514 struct b43_phy_lp *lpphy = dev->phy.lp;
99e0fca6 515 struct ssb_bus *bus = dev->dev->bus;
1e711bee 516 u32 crystalfreq, tmp, ref;
24b5bcc6
MB		 517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
7e4d8529 540 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
24b5bcc6
MB		 541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
542 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
544 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
7e4d8529
GS		 545 if (dev->phy.rev > 0) {
546 b43_radio_write(dev, B2062_S_BG_CTL1,
547 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
548 }
24b5bcc6
MB		 549 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
550 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
551 else
552 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
553
99e0fca6
MB		 554 /* Get the crystal freq, in Hz. */
555 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
556
557 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
558 B43_WARN_ON(crystalfreq == 0);
24b5bcc6 559
5269102e 560 if (crystalfreq <= 30000000) {
1e711bee 561 lpphy->pdiv = 1;
24b5bcc6
MB		 562 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
563 } else {
1e711bee 564 lpphy->pdiv = 2;
24b5bcc6
MB		 565 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
566 }
567
5269102e
GS		 568 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
569 (2 * crystalfreq)) - 8) & 0xFF;
570 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
571
572 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
573 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
24b5bcc6
MB		 574 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
575
5269102e
GS		 576 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
577 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
24b5bcc6
MB		 578 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
579
1e711bee 580 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
24b5bcc6
MB		 581 ref &= 0xFFFF;
582 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
583 if (ref < freqdata_tab[i].freq) {
584 fd = &freqdata_tab[i];
585 break;
586 }
587 }
99e0fca6
MB		 588 if (!fd)
589 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
590 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
591 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
24b5bcc6
MB		 592
593 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
594 ((u16)(fd->data[1]) << 4) | fd->data[0]);
595 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
99e0fca6 596 ((u16)(fd->data[3]) << 4) | fd->data[2]);
24b5bcc6
MB		 597 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
598 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
599}
600
601/* Initialize the 2063 radio. */
602static void lpphy_2063_init(struct b43_wldev *dev)
a387cc7d 603{
c10e47f4
GS		 604 b2063_upload_init_table(dev);
605 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
606 b43_radio_set(dev, B2063_COMM8, 0x38);
607 b43_radio_write(dev, B2063_REG_SP1, 0x56);
608 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
609 b43_radio_write(dev, B2063_PA_SP7, 0);
610 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
611 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
612 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
613 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
614 b43_radio_write(dev, B2063_PA_SP2, 0x18);
a387cc7d
MB		 615}
616
3281d95d
GS		 617struct lpphy_stx_table_entry {
618 u16 phy_offset;
619 u16 phy_shift;
620 u16 rf_addr;
621 u16 rf_shift;
622 u16 mask;
623};
624
625static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
626 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
627 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
628 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
629 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
630 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
631 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
632 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
633 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
634 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
635 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
636 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
637 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
638 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
639 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
640 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
641 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
642 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
643 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
644 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
645 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
646 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
647 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
648 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
649 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
650 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
651 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
652 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
653 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
654 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
655};
656
24b5bcc6
MB		 657static void lpphy_sync_stx(struct b43_wldev *dev)
658{
3281d95d
GS		 659 const struct lpphy_stx_table_entry *e;
660 unsigned int i;
661 u16 tmp;
662
663 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
664 e = &lpphy_stx_table[i];
665 tmp = b43_radio_read(dev, e->rf_addr);
666 tmp >>= e->rf_shift;
667 tmp <<= e->phy_shift;
668 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
d44517f2 669 ~(e->mask << e->phy_shift), tmp);
3281d95d 670 }
24b5bcc6
MB		 671}
672
673static void lpphy_radio_init(struct b43_wldev *dev)
674{
675 /* The radio is attached through the 4wire bus. */
676 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
677 udelay(1);
678 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
679 udelay(1);
680
5269102e 681 if (dev->phy.radio_ver == 0x2062) {
24b5bcc6
MB		 682 lpphy_2062_init(dev);
683 } else {
684 lpphy_2063_init(dev);
685 lpphy_sync_stx(dev);
686 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
687 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
3281d95d
GS		 688 if (dev->dev->bus->chip_id == 0x4325) {
689 // TODO SSB PMU recalibration
690 }
24b5bcc6
MB		 691 }
692}
693
560ad81b
GS		 694struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
695
d4de9532
GS		 696static void lpphy_set_rc_cap(struct b43_wldev *dev)
697{
5269102e
GS		 698 struct b43_phy_lp *lpphy = dev->phy.lp;
699
700 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
d4de9532 701
5269102e
GS		 702 if (dev->phy.rev == 1) //FIXME check channel 14!
703 rc_cap = max_t(u8, rc_cap + 5, 15);
704
705 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
706 max_t(u8, lpphy->rc_cap - 4, 0x80));
707 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
708 b43_radio_write(dev, B2062_S_RXG_CNT16,
709 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
d4de9532
GS		 710}
711
560ad81b 712static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
d4de9532 713{
560ad81b 714 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
d4de9532
GS		 715}
716
560ad81b 717static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
d4de9532 718{
560ad81b
GS		 719 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
720}
d4de9532 721
560ad81b
GS		 722static void lpphy_disable_crs(struct b43_wldev *dev)
723{
724 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
725 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
726 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
727 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
728 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
729 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
730 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
731 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
732 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
733 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
734 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
735 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
736 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
737 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
738 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
739 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
740 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
741 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
742 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
743 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
744 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
745 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
746 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
747 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
748 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
749 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
750}
d4de9532 751
560ad81b
GS		 752static void lpphy_restore_crs(struct b43_wldev *dev)
753{
754 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
755 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
756 else
757 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
758 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
759 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
760}
761
762struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
763
764static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
765{
766 struct lpphy_tx_gains gains;
767 u16 tmp;
768
769 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
770 if (dev->phy.rev < 2) {
771 tmp = b43_phy_read(dev,
772 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
773 gains.gm = tmp & 0x0007;
774 gains.pga = (tmp & 0x0078) >> 3;
775 gains.pad = (tmp & 0x780) >> 7;
776 } else {
777 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
778 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
779 gains.gm = tmp & 0xFF;
780 gains.pga = (tmp >> 8) & 0xFF;
d4de9532
GS		 781 }
782
560ad81b
GS		 783 return gains;
784}
d4de9532 785
560ad81b
GS		 786static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
787{
788 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
789 ctl |= dac << 7;
790 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
791}
d4de9532 792
560ad81b
GS		 793static void lpphy_set_tx_gains(struct b43_wldev *dev,
794 struct lpphy_tx_gains gains)
795{
796 u16 rf_gain, pa_gain;
d4de9532 797
560ad81b
GS		 798 if (dev->phy.rev < 2) {
799 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
800 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
801 0xF800, rf_gain);
d4de9532 802 } else {
560ad81b
GS		 803 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
804 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
805 (gains.pga << 8) | gains.gm);
806 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
807 0x8000, gains.pad | pa_gain);
808 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
809 (gains.pga << 8) | gains.gm);
810 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
811 0x8000, gains.pad | pa_gain);
d4de9532 812 }
560ad81b
GS		 813 lpphy_set_dac_gain(dev, gains.dac);
814 if (dev->phy.rev < 2) {
815 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
816 } else {
817 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
818 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
819 }
16373f65 820 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 6);
560ad81b 821}
d4de9532 822
560ad81b
GS		 823static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
824{
825 u16 trsw = gain & 0x1;
826 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
827 u16 ext_lna = (gain & 2) >> 1;
828
829 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
830 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
831 0xFBFF, ext_lna << 10);
832 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
833 0xF7FF, ext_lna << 11);
834 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
835}
d4de9532 836
560ad81b
GS		 837static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
838{
839 u16 low_gain = gain & 0xFFFF;
840 u16 high_gain = (gain >> 16) & 0xF;
841 u16 ext_lna = (gain >> 21) & 0x1;
842 u16 trsw = ~(gain >> 20) & 0x1;
843 u16 tmp;
844
845 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
846 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
847 0xFDFF, ext_lna << 9);
848 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
849 0xFBFF, ext_lna << 10);
850 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
851 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
852 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
853 tmp = (gain >> 2) & 0x3;
854 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
855 0xE7FF, tmp<<11);
856 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
857 }
858}
859
860static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
861{
862 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
863 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
864 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
865 if (dev->phy.rev >= 2) {
866 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
867 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
868 return;
869 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
870 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
871 } else {
872 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
873 }
874}
875
876static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
877{
878 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
879 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
880 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
881 if (dev->phy.rev >= 2) {
882 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
883 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
884 return;
885 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
886 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
887 } else {
888 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
889 }
890}
891
892static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
893{
894 if (dev->phy.rev < 2)
895 lpphy_rev0_1_set_rx_gain(dev, gain);
896 else
897 lpphy_rev2plus_set_rx_gain(dev, gain);
898 lpphy_enable_rx_gain_override(dev);
899}
900
901static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
902{
903 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
904 lpphy_set_rx_gain(dev, gain);
905}
906
907static void lpphy_stop_ddfs(struct b43_wldev *dev)
908{
909 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
910 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
911}
912
913static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
914 int incr1, int incr2, int scale_idx)
915{
916 lpphy_stop_ddfs(dev);
917 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
918 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
919 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
920 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
921 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
922 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
923 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
924 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
925 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
926 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
927}
928
929static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
930 struct lpphy_iq_est *iq_est)
931{
932 int i;
933
934 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
935 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
936 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
937 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
938 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
939
940 for (i = 0; i < 500; i++) {
941 if (!(b43_phy_read(dev,
942 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
d4de9532
GS		 943 break;
944 msleep(1);
945 }
946
560ad81b
GS		 947 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
948 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
949 return false;
950 }
d4de9532 951
560ad81b
GS		 952 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
953 iq_est->iq_prod <<= 16;
954 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
955
956 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
957 iq_est->i_pwr <<= 16;
958 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
959
960 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
961 iq_est->q_pwr <<= 16;
962 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
963
964 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
965 return true;
d4de9532
GS		 966}
967
560ad81b 968static int lpphy_loopback(struct b43_wldev *dev)
d4de9532 969{
560ad81b
GS		 970 struct lpphy_iq_est iq_est;
971 int i, index = -1;
972 u32 tmp;
973
974 memset(&iq_est, 0, sizeof(iq_est));
975
976 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
977 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
978 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
979 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
980 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
981 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
982 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
983 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
984 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
985 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
986 for (i = 0; i < 32; i++) {
987 lpphy_set_rx_gain_by_index(dev, i);
988 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
989 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
990 continue;
991 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
992 if ((tmp > 4000) && (tmp < 10000)) {
993 index = i;
994 break;
995 }
996 }
997 lpphy_stop_ddfs(dev);
998 return index;
999}
d4de9532 1000
560ad81b
GS		 1001static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1002{
1003 u32 quotient, remainder, rbit, roundup, tmp;
1004
1005 if (divisor == 0) {
1006 quotient = 0;
1007 remainder = 0;
d4de9532 1008 } else {
560ad81b
GS		 1009 quotient = dividend / divisor;
1010 remainder = dividend % divisor;
d4de9532 1011 }
560ad81b
GS		 1012
1013 rbit = divisor & 0x1;
1014 roundup = (divisor >> 1) + rbit;
1015 precision--;
1016
1017 while (precision != 0xFF) {
1018 tmp = remainder - roundup;
1019 quotient <<= 1;
1020 remainder <<= 1;
1021 if (remainder >= roundup) {
1022 remainder = (tmp << 1) + rbit;
1023 quotient--;
1024 }
1025 precision--;
1026 }
1027
1028 if (remainder >= roundup)
1029 quotient++;
1030
1031 return quotient;
d4de9532
GS		 1032}
1033
ce1a9ee3
MB		 1034/* Read the TX power control mode from hardware. */
1035static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1036{
1037 struct b43_phy_lp *lpphy = dev->phy.lp;
1038 u16 ctl;
1039
1040 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1041 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1042 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1043 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1044 break;
1045 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1046 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1047 break;
1048 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1049 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1050 break;
1051 default:
1052 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1053 B43_WARN_ON(1);
1054 break;
1055 }
1056}
1057
1058/* Set the TX power control mode in hardware. */
1059static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1060{
1061 struct b43_phy_lp *lpphy = dev->phy.lp;
1062 u16 ctl;
1063
1064 switch (lpphy->txpctl_mode) {
1065 case B43_LPPHY_TXPCTL_OFF:
1066 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1067 break;
1068 case B43_LPPHY_TXPCTL_HW:
1069 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1070 break;
1071 case B43_LPPHY_TXPCTL_SW:
1072 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1073 break;
1074 default:
1075 ctl = 0;
1076 B43_WARN_ON(1);
1077 }
1078 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1079 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1080}
1081
1082static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1083 enum b43_lpphy_txpctl_mode mode)
1084{
1085 struct b43_phy_lp *lpphy = dev->phy.lp;
1086 enum b43_lpphy_txpctl_mode oldmode;
1087
ce1a9ee3 1088 lpphy_read_tx_pctl_mode_from_hardware(dev);
12d4bba0
GS		 1089 oldmode = lpphy->txpctl_mode;
1090 if (oldmode == mode)
ce1a9ee3
MB		 1091 return;
1092 lpphy->txpctl_mode = mode;
1093
1094 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1095 //TODO Update TX Power NPT
1096 //TODO Clear all TX Power offsets
1097 } else {
1098 if (mode == B43_LPPHY_TXPCTL_HW) {
1099 //TODO Recalculate target TX power
1100 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1101 0xFF80, lpphy->tssi_idx);
1102 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1103 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1104 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1105 //TODO Disable TX gain override
1106 lpphy->tx_pwr_idx_over = -1;
1107 }
1108 }
1109 if (dev->phy.rev >= 2) {
1110 if (mode == B43_LPPHY_TXPCTL_HW)
1111 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1112 else
1113 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1114 }
1115 lpphy_write_tx_pctl_mode_to_hardware(dev);
1116}
1117
5269102e
GS		 1118static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1119 unsigned int new_channel);
1120
560ad81b
GS		 1121static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1122{
1123 struct b43_phy_lp *lpphy = dev->phy.lp;
1124 struct lpphy_iq_est iq_est;
1125 struct lpphy_tx_gains tx_gains;
1126 static const u32 ideal_pwr_table[22] = {
1127 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1128 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1129 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1130 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1131 };
1132 bool old_txg_ovr;
1133 u8 old_bbmult;
1134 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1245684c
GS		 1135 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1136 enum b43_lpphy_txpctl_mode old_txpctl;
560ad81b 1137 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
5269102e 1138 int loopback, i, j, inner_sum, err;
560ad81b
GS		 1139
1140 memset(&iq_est, 0, sizeof(iq_est));
1141
5269102e
GS		 1142 err = b43_lpphy_op_switch_channel(dev, 7);
1143 if (err) {
1144 b43dbg(dev->wl,
1145 "RC calib: Failed to switch to channel 7, error = %d",
1146 err);
1147 }
560ad81b
GS		 1148 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1149 old_bbmult = lpphy_get_bb_mult(dev);
1150 if (old_txg_ovr)
1151 tx_gains = lpphy_get_tx_gains(dev);
1152 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1153 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1154 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1155 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1156 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1157 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1158 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1245684c
GS		 1159 lpphy_read_tx_pctl_mode_from_hardware(dev);
1160 old_txpctl = lpphy->txpctl_mode;
560ad81b 1161
5f1c07d9 1162 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
560ad81b
GS		 1163 lpphy_disable_crs(dev);
1164 loopback = lpphy_loopback(dev);
1165 if (loopback == -1)
1166 goto finish;
1167 lpphy_set_rx_gain_by_index(dev, loopback);
1168 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1169 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1170 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1171 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1172 for (i = 128; i <= 159; i++) {
1173 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1174 inner_sum = 0;
1175 for (j = 5; j <= 25; j++) {
1176 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1177 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1178 goto finish;
1179 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1180 if (j == 5)
1181 tmp = mean_sq_pwr;
1182 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1183 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1184 mean_sq_pwr = ideal_pwr - normal_pwr;
1185 mean_sq_pwr *= mean_sq_pwr;
1186 inner_sum += mean_sq_pwr;
1187 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1188 lpphy->rc_cap = i;
1189 mean_sq_pwr_min = inner_sum;
1190 }
1191 }
1192 }
1193 lpphy_stop_ddfs(dev);
1194
1195finish:
1196 lpphy_restore_crs(dev);
1197 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1198 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1199 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1200 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1201 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1202 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1203 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1204
1205 lpphy_set_bb_mult(dev, old_bbmult);
1206 if (old_txg_ovr) {
1207 /*
1208 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1209 * illogical. According to lwfinger, vendor driver v4.150.10.5
1210 * has a Set here, while v4.174.64.19 has a Get - regression in
1211 * the vendor driver? This should be tested this once the code
1212 * is testable.
1213 */
1214 lpphy_set_tx_gains(dev, tx_gains);
1215 }
1216 lpphy_set_tx_power_control(dev, old_txpctl);
1217 if (lpphy->rc_cap)
1218 lpphy_set_rc_cap(dev);
1219}
1220
1221static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1222{
1223 struct ssb_bus *bus = dev->dev->bus;
1224 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1225 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1226 int i;
1227
1228 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1229 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1230 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1231 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1232 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1233 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1234 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1235 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1236 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1237
1238 for (i = 0; i < 10000; i++) {
1239 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1240 break;
1241 msleep(1);
1242 }
1243
1244 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1245 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1246
1247 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1248
1249 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1250 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1251 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1252 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1253 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1254
1255 if (crystal_freq == 24000000) {
1256 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1257 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1258 } else {
1259 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1260 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1261 }
1262
1263 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1264
1265 for (i = 0; i < 10000; i++) {
1266 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1267 break;
1268 msleep(1);
1269 }
1270
1271 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1272 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1273
1274 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1275}
1276
1277static void lpphy_calibrate_rc(struct b43_wldev *dev)
1278{
1279 struct b43_phy_lp *lpphy = dev->phy.lp;
1280
1281 if (dev->phy.rev >= 2) {
1282 lpphy_rev2plus_rc_calib(dev);
1283 } else if (!lpphy->rc_cap) {
1284 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1285 lpphy_rev0_1_rc_calib(dev);
1286 } else {
1287 lpphy_set_rc_cap(dev);
1288 }
1289}
1290
ce1a9ee3
MB		 1291static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1292{
1293 struct b43_phy_lp *lpphy = dev->phy.lp;
1294
1295 lpphy->tx_pwr_idx_over = index;
1296 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1297 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1298
1299 //TODO
1300}
1301
1302static void lpphy_btcoex_override(struct b43_wldev *dev)
1303{
1304 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1305 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1306}
1307
1308static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1309{
1310 struct b43_phy_lp *lpphy = dev->phy.lp;
1311 u32 *saved_tab;
1312 const unsigned int saved_tab_size = 256;
1313 enum b43_lpphy_txpctl_mode txpctl_mode;
1314 s8 tx_pwr_idx_over;
1315 u16 tssi_npt, tssi_idx;
1316
1317 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1318 if (!saved_tab) {
1319 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1320 return;
1321 }
1322
1323 lpphy_read_tx_pctl_mode_from_hardware(dev);
1324 txpctl_mode = lpphy->txpctl_mode;
1325 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1326 tssi_npt = lpphy->tssi_npt;
1327 tssi_idx = lpphy->tssi_idx;
1328
1329 if (dev->phy.rev < 2) {
1330 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1331 saved_tab_size, saved_tab);
1332 } else {
1333 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1334 saved_tab_size, saved_tab);
1335 }
1336 //TODO
1337
1338 kfree(saved_tab);
1339}
1340
1341static void lpphy_calibration(struct b43_wldev *dev)
1342{
1343 struct b43_phy_lp *lpphy = dev->phy.lp;
1344 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1345
1346 b43_mac_suspend(dev);
1347
1348 lpphy_btcoex_override(dev);
1349 lpphy_read_tx_pctl_mode_from_hardware(dev);
1350 saved_pctl_mode = lpphy->txpctl_mode;
1351 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1352 //TODO Perform transmit power table I/Q LO calibration
1353 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1354 lpphy_pr41573_workaround(dev);
1355 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1356 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1357 //TODO Perform I/Q calibration with a single control value set
1358
1359 b43_mac_enable(dev);
1360}
1361
7021f62a
GS		 1362static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1363{
1364 if (mode != TSSI_MUX_EXT) {
1365 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1366 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1367 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1368 if (mode == TSSI_MUX_POSTPA) {
1369 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1370 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1371 } else {
1372 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1373 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1374 0xFFC7, 0x20);
1375 }
1376 } else {
1377 B43_WARN_ON(1);
1378 }
1379}
1380
1381static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1382{
1383 u16 tmp;
1384 int i;
1385
1386 //SPEC TODO Call LP PHY Clear TX Power offsets
1387 for (i = 0; i < 64; i++) {
1388 if (dev->phy.rev >= 2)
1389 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1390 else
1391 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1392 }
1393
1394 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1395 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1396 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1397 if (dev->phy.rev < 2) {
1398 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1399 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1400 } else {
1401 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1402 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1403 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1404 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1405 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1406 }
1407 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1408 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1409 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1410 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1411 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1412 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1413 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1414 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1415 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1416 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1417
1418 if (dev->phy.rev < 2) {
1419 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1420 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1421 } else {
1422 lpphy_set_tx_power_by_index(dev, 0x7F);
1423 }
1424
1425 b43_dummy_transmission(dev, true, true);
1426
1427 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1428 if (tmp & 0x8000) {
1429 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1430 0xFFC0, (tmp & 0xFF) - 32);
1431 }
1432
1433 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1434
1435 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1436 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1437}
1438
1439static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1440{
1441 struct lpphy_tx_gains gains;
1442
1443 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1444 gains.gm = 4;
1445 gains.pad = 12;
1446 gains.pga = 12;
1447 gains.dac = 0;
1448 } else {
1449 gains.gm = 7;
1450 gains.pad = 14;
1451 gains.pga = 15;
1452 gains.dac = 0;
1453 }
1454 lpphy_set_tx_gains(dev, gains);
1455 lpphy_set_bb_mult(dev, 150);
1456}
1457
ce1a9ee3
MB		 1458/* Initialize TX power control */
1459static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1460{
1461 if (0/*FIXME HWPCTL capable */) {
7021f62a 1462 lpphy_tx_pctl_init_hw(dev);
ce1a9ee3 1463 } else { /* This device is only software TX power control capable. */
7021f62a 1464 lpphy_tx_pctl_init_sw(dev);
ce1a9ee3
MB		 1465 }
1466}
1467
e63e4363
MB		 1468static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1469{
0888707f
MB		 1470 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1471 return b43_read16(dev, B43_MMIO_PHY_DATA);
e63e4363
MB		 1472}
1473
1474static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1475{
0888707f
MB		 1476 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1477 b43_write16(dev, B43_MMIO_PHY_DATA, value);
e63e4363
MB		 1478}
1479
1480static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1481{
0888707f
MB		 1482 /* Register 1 is a 32-bit register. */
1483 B43_WARN_ON(reg == 1);
1484 /* LP-PHY needs a special bit set for read access */
1485 if (dev->phy.rev < 2) {
1486 if (reg != 0x4001)
1487 reg |= 0x100;
1488 } else
1489 reg |= 0x200;
1490
1491 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1492 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e63e4363
MB		 1493}
1494
1495static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1496{
1497 /* Register 1 is a 32-bit register. */
1498 B43_WARN_ON(reg == 1);
1499
0888707f
MB		 1500 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1501 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
e63e4363
MB		 1502}
1503
1504static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1505 bool blocked)
e63e4363
MB		 1506{
1507 //TODO
1508}
1509
588f8377
GS		 1510struct b206x_channel {
1511 u8 channel;
1512 u16 freq;
1513 u8 data[12];
1514};
1515
1e711bee
GS		 1516static const struct b206x_channel b2062_chantbl[] = {
1517 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1518 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1519 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1520 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1521 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1522 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1523 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1524 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1525 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1526 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1527 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1528 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1529 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1530 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1531 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1532 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1533 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1534 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1535 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1536 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1537 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1538 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1539 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1540 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1541 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1542 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1543 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1544 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1545 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1546 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1547 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1548 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1549 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1550 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1551 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1552 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1553 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1554 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1555 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1556 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1557 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1558 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1559 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1560 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1561 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1562 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1563 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1564 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1565 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1566 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1567 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1568 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1569 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1570 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1571 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1572 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1573 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1574 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1575 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1576 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1577 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1578 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1579 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1580 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1581 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1582 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1583 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1584 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1585 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1586 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1587 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1588 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1589 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1590 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1591 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1592 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1593 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1594 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1595 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1596 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1597 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1598 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1599 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1600 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1601 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1602 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1603 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1604 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1605 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1606 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1607 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1608 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1609 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1610 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1611 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1612 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1613 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1614 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1615 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1616 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1617 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1618 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1619 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1620 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1621 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1622 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1623 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1624 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1625 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1626 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1627 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1628 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1629 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1630 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1631 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1632 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1633 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1634 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1635 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1636 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1637 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1638 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1639 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1640 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1641 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1642 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1643 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1644 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1645 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1646 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1647 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1648 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1649 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1650 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1651 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1652 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1653 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1654 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1655 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1656 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1657 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1658 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1659 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1660 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1661 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1662 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1663 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1664 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1665 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1666 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1667 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1668 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1669 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1670};
1671
588f8377
GS		 1672static const struct b206x_channel b2063_chantbl[] = {
1673 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1674 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1675 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1676 .data[10] = 0x80, .data[11] = 0x70, },
1677 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1678 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1679 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1680 .data[10] = 0x80, .data[11] = 0x70, },
1681 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1682 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1683 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1684 .data[10] = 0x80, .data[11] = 0x70, },
1685 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1686 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1687 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1688 .data[10] = 0x80, .data[11] = 0x70, },
1689 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1690 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1691 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1692 .data[10] = 0x80, .data[11] = 0x70, },
1693 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1694 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1695 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1696 .data[10] = 0x80, .data[11] = 0x70, },
1697 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1698 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1699 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1700 .data[10] = 0x80, .data[11] = 0x70, },
1701 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1702 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1703 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1704 .data[10] = 0x80, .data[11] = 0x70, },
1705 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1706 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1707 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1708 .data[10] = 0x80, .data[11] = 0x70, },
1709 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1710 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1711 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1712 .data[10] = 0x80, .data[11] = 0x70, },
1713 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1714 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1715 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1716 .data[10] = 0x80, .data[11] = 0x70, },
1717 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1718 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1719 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1720 .data[10] = 0x80, .data[11] = 0x70, },
1721 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1722 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1723 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1724 .data[10] = 0x80, .data[11] = 0x70, },
1725 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1726 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1727 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1728 .data[10] = 0x80, .data[11] = 0x70, },
1729 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1730 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1731 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1732 .data[10] = 0x20, .data[11] = 0x00, },
1733 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1734 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1735 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1736 .data[10] = 0x20, .data[11] = 0x00, },
1737 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1738 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1739 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1740 .data[10] = 0x20, .data[11] = 0x00, },
1741 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1742 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1743 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1744 .data[10] = 0x20, .data[11] = 0x00, },
1745 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1746 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1747 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1748 .data[10] = 0x20, .data[11] = 0x00, },
1749 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1750 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1751 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1752 .data[10] = 0x20, .data[11] = 0x00, },
1753 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1754 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1755 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1756 .data[10] = 0x20, .data[11] = 0x00, },
1757 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1758 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1759 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1760 .data[10] = 0x20, .data[11] = 0x00, },
1761 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1762 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1763 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1764 .data[10] = 0x20, .data[11] = 0x00, },
1765 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1766 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1767 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1768 .data[10] = 0x10, .data[11] = 0x00, },
1769 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1770 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1771 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1772 .data[10] = 0x10, .data[11] = 0x00, },
1773 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1774 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1775 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1776 .data[10] = 0x10, .data[11] = 0x00, },
1777 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1778 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1779 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1780 .data[10] = 0x00, .data[11] = 0x00, },
1781 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1782 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1783 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1784 .data[10] = 0x00, .data[11] = 0x00, },
1785 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1786 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1787 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1788 .data[10] = 0x00, .data[11] = 0x00, },
1789 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1790 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1791 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1792 .data[10] = 0x00, .data[11] = 0x00, },
1793 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1794 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1795 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1796 .data[10] = 0x00, .data[11] = 0x00, },
1797 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1798 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1799 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1800 .data[10] = 0x00, .data[11] = 0x00, },
1801 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1802 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1803 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1804 .data[10] = 0x00, .data[11] = 0x00, },
1805 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1806 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1807 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1808 .data[10] = 0x00, .data[11] = 0x00, },
1809 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1810 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1811 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1812 .data[10] = 0x00, .data[11] = 0x00, },
1813 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1814 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1815 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1816 .data[10] = 0x00, .data[11] = 0x00, },
1817 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1818 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1819 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1820 .data[10] = 0x00, .data[11] = 0x00, },
1821 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1822 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1823 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1824 .data[10] = 0x00, .data[11] = 0x00, },
1825 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1826 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1827 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1828 .data[10] = 0x00, .data[11] = 0x00, },
1829 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1830 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1831 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1832 .data[10] = 0x00, .data[11] = 0x00, },
1833 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1834 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1835 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1836 .data[10] = 0x00, .data[11] = 0x00, },
1837 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1838 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1839 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1840 .data[10] = 0x00, .data[11] = 0x00, },
1841 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1842 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1843 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1844 .data[10] = 0x50, .data[11] = 0x00, },
1845 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1846 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1847 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1848 .data[10] = 0x50, .data[11] = 0x00, },
1849 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1850 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1851 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1852 .data[10] = 0x50, .data[11] = 0x00, },
1853 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1854 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1855 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1856 .data[10] = 0x40, .data[11] = 0x00, },
1857 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1858 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1859 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1860 .data[10] = 0x40, .data[11] = 0x00, },
1861 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1862 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1863 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1864 .data[10] = 0x40, .data[11] = 0x00, },
1865 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1866 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1867 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1868 .data[10] = 0x40, .data[11] = 0x00, },
1869 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1870 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1871 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1872 .data[10] = 0x40, .data[11] = 0x00, },
1873 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1874 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1875 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1876 .data[10] = 0x40, .data[11] = 0x00, },
1877};
1878
1e711bee 1879static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
588f8377 1880{
1e711bee
GS		 1881 struct ssb_bus *bus = dev->dev->bus;
1882
1883 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1884 udelay(20);
1885 if (bus->chip_id == 0x5354) {
1886 b43_radio_write(dev, B2062_N_COMM1, 4);
1887 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1888 } else {
1889 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1890 }
1891 udelay(5);
1892}
1893
1894static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1895{
1896 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1897 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1898 udelay(200);
1899}
1900
1901static int lpphy_b2062_tune(struct b43_wldev *dev,
1902 unsigned int channel)
1903{
1904 struct b43_phy_lp *lpphy = dev->phy.lp;
1905 struct ssb_bus *bus = dev->dev->bus;
5269102e 1906 const struct b206x_channel *chandata = NULL;
1e711bee
GS		 1907 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1908 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1909 int i, err = 0;
1910
5269102e
GS		 1911 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1912 if (b2062_chantbl[i].channel == channel) {
1913 chandata = &b2062_chantbl[i];
1e711bee
GS		 1914 break;
1915 }
1916 }
1917
1918 if (B43_WARN_ON(!chandata))
1919 return -EINVAL;
1920
1921 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1922 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1923 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1924 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1925 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1926 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1927 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1928 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1929 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1930 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1931
1932 tmp1 = crystal_freq / 1000;
1933 tmp2 = lpphy->pdiv * 1000;
1934 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1935 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1936 lpphy_b2062_reset_pll_bias(dev);
1937 tmp3 = tmp2 * channel2freq_lp(channel);
1938 if (channel2freq_lp(channel) < 4000)
1939 tmp3 *= 2;
1940 tmp4 = 48 * tmp1;
1941 tmp6 = tmp3 / tmp4;
1942 tmp7 = tmp3 % tmp4;
1943 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1944 tmp5 = tmp7 * 0x100;
1945 tmp6 = tmp5 / tmp4;
1946 tmp7 = tmp5 % tmp4;
055114a3
GS		 1947 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1948 tmp5 = tmp7 * 0x100;
1949 tmp6 = tmp5 / tmp4;
1950 tmp7 = tmp5 % tmp4;
1e711bee
GS		 1951 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1952 tmp5 = tmp7 * 0x100;
1953 tmp6 = tmp5 / tmp4;
1954 tmp7 = tmp5 % tmp4;
1955 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1956 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1957 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
ed07c4b3 1958 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
1e711bee
GS		 1959 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1960
1961 lpphy_b2062_vco_calib(dev);
1962 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1963 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1964 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1965 lpphy_b2062_reset_pll_bias(dev);
1966 lpphy_b2062_vco_calib(dev);
1967 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
96909e97 1968 err = -EIO;
1e711bee
GS		 1969 }
1970
1971 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
1972 return err;
1973}
1974
1975static void lpphy_japan_filter(struct b43_wldev *dev, int channel)
1976{
1977 struct b43_phy_lp *lpphy = dev->phy.lp;
1978 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1979
1980 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1981 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1982 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1983 lpphy_set_rc_cap(dev);
1984 } else {
1985 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1986 }
588f8377
GS		 1987}
1988
1989static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
1990{
1991 u16 tmp;
1992
1993 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
1994 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
1995 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
1996 udelay(1);
1997 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
1998 udelay(1);
1999 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2000 udelay(1);
2001 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2002 udelay(300);
2003 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
2004}
2005
1e711bee
GS		 2006static int lpphy_b2063_tune(struct b43_wldev *dev,
2007 unsigned int channel)
588f8377
GS		 2008{
2009 struct ssb_bus *bus = dev->dev->bus;
2010
2011 static const struct b206x_channel *chandata = NULL;
2012 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2013 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2014 u16 old_comm15, scale;
2015 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2016 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2017
2018 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2019 if (b2063_chantbl[i].channel == channel) {
2020 chandata = &b2063_chantbl[i];
2021 break;
2022 }
2023 }
2024
2025 if (B43_WARN_ON(!chandata))
1e711bee 2026 return -EINVAL;
588f8377
GS		 2027
2028 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2029 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2030 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2031 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2032 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2033 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2034 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2035 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2036 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2037 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2038 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2039 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2040
2041 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2042 b43_radio_set(dev, B2063_COMM15, 0x1E);
2043
2044 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2045 vco_freq = chandata->freq << 1;
2046 else
2047 vco_freq = chandata->freq << 2;
2048
2049 freqref = crystal_freq * 3;
2050 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2051 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2052 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2053 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2054 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2055 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2056 0xFFF8, timeout >> 2);
2057 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2058 0xFF9F,timeout << 5);
2059
2060 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2061 999999) / 1000000) + 1;
2062 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2063
2064 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2065 count *= (timeout + 1) * (timeoutref + 1);
2066 count--;
2067 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2068 0xF0, count >> 8);
2069 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2070
2071 tmp1 = ((val3 * 62500) / freqref) << 4;
2072 tmp2 = ((val3 * 62500) % freqref) << 4;
2073 while (tmp2 >= freqref) {
2074 tmp1++;
2075 tmp2 -= freqref;
2076 }
2077 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2078 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2079 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2080 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2081 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2082
2083 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2084 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2085 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2086 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2087
2088 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2089 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2090
2091 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2092 scale = 1;
2093 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2094 } else {
2095 scale = 0;
2096 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2097 }
2098 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2099 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2100
2101 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2102 tmp6 *= (tmp5 * 8) * (scale + 1);
2103 if (tmp6 > 150)
2104 tmp6 = 0;
2105
2106 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2107 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2108
2109 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2110 if (crystal_freq > 26000000)
2111 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2112 else
2113 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2114
2115 if (val1 == 45)
2116 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2117 else
2118 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2119
2120 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2121 udelay(1);
2122 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2123 lpphy_b2063_vco_calib(dev);
2124 b43_radio_write(dev, B2063_COMM15, old_comm15);
1e711bee
GS		 2125
2126 return 0;
588f8377
GS		 2127}
2128
e63e4363
MB		 2129static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2130 unsigned int new_channel)
2131{
1e711bee
GS		 2132 int err;
2133
588f8377
GS		 2134 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2135
2136 if (dev->phy.radio_ver == 0x2063) {
1e711bee
GS		 2137 err = lpphy_b2063_tune(dev, new_channel);
2138 if (err)
2139 return err;
588f8377 2140 } else {
1e711bee
GS		 2141 err = lpphy_b2062_tune(dev, new_channel);
2142 if (err)
2143 return err;
2144 lpphy_japan_filter(dev, new_channel);
0c61bb9a 2145 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
588f8377
GS		 2146 }
2147
e63e4363
MB		 2148 return 0;
2149}
2150
588f8377 2151static int b43_lpphy_op_init(struct b43_wldev *dev)
e63e4363 2152{
96909e97
GS		 2153 int err;
2154
588f8377
GS		 2155 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2156 lpphy_baseband_init(dev);
2157 lpphy_radio_init(dev);
2158 lpphy_calibrate_rc(dev);
96909e97
GS		 2159 err = b43_lpphy_op_switch_channel(dev,
2160 b43_lpphy_op_get_default_chan(dev));
2161 if (err) {
2162 b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
2163 err);
2164 }
588f8377
GS		 2165 lpphy_tx_pctl_init(dev);
2166 lpphy_calibration(dev);
2167 //TODO ACI init
2168
2169 return 0;
e63e4363
MB		 2170}
2171
2172static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2173{
2174 //TODO
2175}
2176
2177static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2178{
2179 //TODO
2180}
2181
2182static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2183 bool ignore_tssi)
2184{
2185 //TODO
2186 return B43_TXPWR_RES_DONE;
2187}
2188
e63e4363
MB		 2189const struct b43_phy_operations b43_phyops_lp = {
2190 .allocate = b43_lpphy_op_allocate,
fb11137a
MB		 2191 .free = b43_lpphy_op_free,
2192 .prepare_structs = b43_lpphy_op_prepare_structs,
e63e4363 2193 .init = b43_lpphy_op_init,
e63e4363
MB		 2194 .phy_read = b43_lpphy_op_read,
2195 .phy_write = b43_lpphy_op_write,
2196 .radio_read = b43_lpphy_op_radio_read,
2197 .radio_write = b43_lpphy_op_radio_write,
2198 .software_rfkill = b43_lpphy_op_software_rfkill,
cb24f57f 2199 .switch_analog = b43_phyop_switch_analog_generic,
e63e4363
MB		 2200 .switch_channel = b43_lpphy_op_switch_channel,
2201 .get_default_chan = b43_lpphy_op_get_default_chan,
2202 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2203 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2204 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2205};
Linux kernel - Deliverables
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