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b43: N-PHY: define missing registers
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
2a2d0589
RM		 72enum n_rssi_type {
73 N_RSSI_W1 = 0,
74 N_RSSI_W2,
75 N_RSSI_NB,
76 N_RSSI_IQ,
77 N_RSSI_TSSI_2G,
78 N_RSSI_TSSI_5G,
79 N_RSSI_TBD,
76b002bd
RM		 80};
81
6aa38725
RM		 82enum n_rail_type {
83 N_RAIL_I = 0,
84 N_RAIL_Q = 1,
85};
86
c002831a
RM		 87static inline bool b43_nphy_ipa(struct b43_wldev *dev)
88{
89 enum ieee80211_band band = b43_current_band(dev->wl);
90 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
91 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
92}
93
e0c9a021
RM		 94/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
95static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
96{
97 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
98 B43_NPHY_RFSEQCA_RXEN_SHIFT;
99}
100
ab499217
RM		 101/**************************************************
102 * RF (just without b43_nphy_rf_control_intc_override)
103 **************************************************/
18c8adeb 104
ab499217
RM		 105/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
106static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
107 enum b43_nphy_rf_sequence seq)
d1591314 108{
ab499217
RM		 109 static const u16 trigger[] = {
110 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
111 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
112 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
113 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
114 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
115 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
116 };
117 int i;
118 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 119
ab499217 120 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 121
ab499217
RM		 122 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
123 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
124 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
125 for (i = 0; i < 200; i++) {
126 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
127 goto ok;
128 msleep(1);
129 }
130 b43err(dev->wl, "RF sequence status timeout\n");
131ok:
132 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
133}
e5255ccc 134
c071b9f6
RM		 135/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
136static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
137 u16 value, u8 core, bool off,
138 u8 override)
139{
140 const struct nphy_rf_control_override_rev7 *e;
141 u16 en_addrs[3][2] = {
142 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
143 };
144 u16 en_addr;
145 u16 en_mask = field;
146 u16 val_addr;
147 u8 i;
148
149 /* Remember: we can get NULL! */
150 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
151
152 for (i = 0; i < 2; i++) {
153 if (override >= ARRAY_SIZE(en_addrs)) {
154 b43err(dev->wl, "Invalid override value %d\n", override);
155 return;
156 }
157 en_addr = en_addrs[override][i];
158
159 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
160
161 if (off) {
162 b43_phy_mask(dev, en_addr, ~en_mask);
163 if (e) /* Do it safer, better than wl */
164 b43_phy_mask(dev, val_addr, ~e->val_mask);
165 } else {
166 if (!core || (core & (1 << i))) {
167 b43_phy_set(dev, en_addr, en_mask);
168 if (e)
169 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
170 }
171 }
172 }
173}
174
ab499217
RM		 175/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
176static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
177 u16 value, u8 core, bool off)
178{
179 int i;
180 u8 index = fls(field);
181 u8 addr, en_addr, val_addr;
182 /* we expect only one bit set */
183 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 184
ab499217
RM		 185 if (dev->phy.rev >= 3) {
186 const struct nphy_rf_control_override_rev3 *rf_ctrl;
187 for (i = 0; i < 2; i++) {
188 if (index == 0 || index == 16) {
189 b43err(dev->wl,
190 "Unsupported RF Ctrl Override call\n");
191 return;
192 }
e5255ccc 193
ab499217
RM		 194 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
195 en_addr = B43_PHY_N((i == 0) ?
196 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
197 val_addr = B43_PHY_N((i == 0) ?
198 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 199
ab499217
RM		 200 if (off) {
201 b43_phy_mask(dev, en_addr, ~(field));
202 b43_phy_mask(dev, val_addr,
203 ~(rf_ctrl->val_mask));
204 } else {
b97c0718 205 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 206 b43_phy_set(dev, en_addr, field);
207 b43_phy_maskset(dev, val_addr,
208 ~(rf_ctrl->val_mask),
209 (value << rf_ctrl->val_shift));
210 }
211 }
212 }
213 } else {
214 const struct nphy_rf_control_override_rev2 *rf_ctrl;
215 if (off) {
216 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
217 value = 0;
218 } else {
219 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
220 }
d4814e69 221
ab499217
RM		 222 for (i = 0; i < 2; i++) {
223 if (index <= 1 || index == 16) {
224 b43err(dev->wl,
225 "Unsupported RF Ctrl Override call\n");
226 return;
227 }
d4814e69 228
ab499217
RM		 229 if (index == 2 || index == 10 ||
230 (index >= 13 && index <= 15)) {
231 core = 1;
232 }
d4814e69 233
ab499217
RM		 234 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
235 addr = B43_PHY_N((i == 0) ?
236 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 237
b97c0718 238 if ((1 << i) & core)
ab499217
RM		 239 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
240 (value << rf_ctrl->shift));
241
242 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
243 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
244 B43_NPHY_RFCTL_CMD_START);
245 udelay(1);
246 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
247 }
248 }
d4814e69
RM		 249}
250
ab499217
RM		 251/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
252static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
253 u16 value, u8 core)
d4814e69 254{
ab499217
RM		 255 u8 i, j;
256 u16 reg, tmp, val;
38646eba 257
d4814e69 258 B43_WARN_ON(dev->phy.rev < 3);
ab499217 259 B43_WARN_ON(field > 4);
d4814e69 260
ab499217
RM		 261 for (i = 0; i < 2; i++) {
262 if ((core == 1 && i == 1) || (core == 2 && !i))
263 continue;
38646eba 264
ab499217
RM		 265 reg = (i == 0) ?
266 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 267 b43_phy_set(dev, reg, 0x400);
38646eba 268
ab499217
RM		 269 switch (field) {
270 case 0:
271 b43_phy_write(dev, reg, 0);
272 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
273 break;
274 case 1:
275 if (!i) {
276 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
277 0xFC3F, (value << 6));
278 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
279 0xFFFE, 1);
280 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
281 B43_NPHY_RFCTL_CMD_START);
282 for (j = 0; j < 100; j++) {
603431e9 283 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 284 j = 0;
285 break;
286 }
287 udelay(10);
38646eba 288 }
ab499217
RM		 289 if (j)
290 b43err(dev->wl,
291 "intc override timeout\n");
292 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
293 0xFFFE);
38646eba 294 } else {
ab499217
RM		 295 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
296 0xFC3F, (value << 6));
297 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
298 0xFFFE, 1);
299 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
300 B43_NPHY_RFCTL_CMD_RXTX);
301 for (j = 0; j < 100; j++) {
603431e9 302 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 303 j = 0;
304 break;
305 }
306 udelay(10);
307 }
308 if (j)
309 b43err(dev->wl,
310 "intc override timeout\n");
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
312 0xFFFE);
38646eba 313 }
ab499217
RM		 314 break;
315 case 2:
316 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
317 tmp = 0x0020;
318 val = value << 5;
319 } else {
320 tmp = 0x0010;
321 val = value << 4;
322 }
323 b43_phy_maskset(dev, reg, ~tmp, val);
324 break;
325 case 3:
326 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
327 tmp = 0x0001;
328 val = value;
329 } else {
330 tmp = 0x0004;
331 val = value << 2;
332 }
333 b43_phy_maskset(dev, reg, ~tmp, val);
334 break;
335 case 4:
336 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
337 tmp = 0x0002;
338 val = value << 1;
339 } else {
340 tmp = 0x0008;
341 val = value << 3;
342 }
343 b43_phy_maskset(dev, reg, ~tmp, val);
344 break;
38646eba 345 }
38646eba 346 }
ab499217 347}
38646eba 348
ab499217
RM		 349/**************************************************
350 * Various PHY ops
351 **************************************************/
352
353/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
354static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
355 const u16 *clip_st)
356{
357 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
358 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 359}
360
ab499217
RM		 361/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
362static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 363{
ab499217
RM		 364 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
365 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 366}
367
ab499217
RM		 368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
369static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 370{
ab499217 371 u16 tmp;
161d540c 372
ab499217
RM		 373 if (dev->dev->core_rev == 16)
374 b43_mac_suspend(dev);
161d540c 375
ab499217
RM		 376 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
377 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
378 B43_NPHY_CLASSCTL_WAITEDEN);
379 tmp &= ~mask;
380 tmp |= (val & mask);
381 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 382
ab499217
RM		 383 if (dev->dev->core_rev == 16)
384 b43_mac_enable(dev);
161d540c 385
ab499217
RM		 386 return tmp;
387}
161d540c 388
ab499217
RM		 389/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
390static void b43_nphy_reset_cca(struct b43_wldev *dev)
391{
392 u16 bbcfg;
161d540c 393
ab499217
RM		 394 b43_phy_force_clock(dev, 1);
395 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
396 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
397 udelay(1);
398 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
399 b43_phy_force_clock(dev, 0);
400 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
401}
161d540c 402
ab499217
RM		 403/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
404static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
405{
406 struct b43_phy *phy = &dev->phy;
407 struct b43_phy_n *nphy = phy->n;
161d540c 408
ab499217
RM		 409 if (enable) {
410 static const u16 clip[] = { 0xFFFF, 0xFFFF };
411 if (nphy->deaf_count++ == 0) {
412 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
413 b43_nphy_classifier(dev, 0x7, 0);
414 b43_nphy_read_clip_detection(dev, nphy->clip_state);
415 b43_nphy_write_clip_detection(dev, clip);
416 }
417 b43_nphy_reset_cca(dev);
161d540c 418 } else {
ab499217
RM		 419 if (--nphy->deaf_count == 0) {
420 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
421 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 422 }
161d540c 423 }
161d540c
RM		 424}
425
64712095
RM		 426/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
427static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 428{
161d540c 429 struct b43_phy_n *nphy = dev->phy.n;
161d540c 430
64712095
RM		 431 u8 i;
432 s16 tmp;
433 u16 data[4];
434 s16 gain[2];
435 u16 minmax[2];
436 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 437
438 if (nphy->hang_avoid)
439 b43_nphy_stay_in_carrier_search(dev, 1);
440
64712095 441 if (nphy->gain_boost) {
161d540c 442 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 443 gain[0] = 6;
444 gain[1] = 6;
161d540c 445 } else {
64712095
RM		 446 tmp = 40370 - 315 * dev->phy.channel;
447 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
448 tmp = 23242 - 224 * dev->phy.channel;
449 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 450 }
64712095
RM		 451 } else {
452 gain[0] = 0;
453 gain[1] = 0;
161d540c 454 }
161d540c
RM		 455
456 for (i = 0; i < 2; i++) {
64712095
RM		 457 if (nphy->elna_gain_config) {
458 data[0] = 19 + gain[i];
459 data[1] = 25 + gain[i];
460 data[2] = 25 + gain[i];
461 data[3] = 25 + gain[i];
161d540c 462 } else {
64712095
RM		 463 data[0] = lna_gain[0] + gain[i];
464 data[1] = lna_gain[1] + gain[i];
465 data[2] = lna_gain[2] + gain[i];
466 data[3] = lna_gain[3] + gain[i];
161d540c 467 }
64712095 468 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 469
64712095 470 minmax[i] = 23 + gain[i];
161d540c
RM		 471 }
472
64712095
RM		 473 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
474 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
475 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
476 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 477
478 if (nphy->hang_avoid)
479 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 480}
481
ab499217
RM		 482/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
483static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
484 u8 *events, u8 *delays, u8 length)
0eff8fcd 485{
ab499217
RM		 486 struct b43_phy_n *nphy = dev->phy.n;
487 u8 i;
488 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
489 u16 offset1 = cmd << 4;
490 u16 offset2 = offset1 + 0x80;
0eff8fcd 491
ab499217
RM		 492 if (nphy->hang_avoid)
493 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 494
ab499217
RM		 495 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
496 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 497
ab499217
RM		 498 for (i = length; i < 16; i++) {
499 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
500 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 501 }
ab499217
RM		 502
503 if (nphy->hang_avoid)
504 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 505}
7955de0c 506
572d37a4
RM		 507/**************************************************
508 * Radio 0x2057
509 **************************************************/
510
511/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
512static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
513{
514 struct b43_phy *phy = &dev->phy;
515 u16 tmp;
516
517 if (phy->radio_rev == 5) {
518 b43_phy_mask(dev, 0x342, ~0x2);
519 udelay(10);
520 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
521 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
522 }
523
524 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
525 udelay(10);
526 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
527 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
528 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
529 return 0;
530 }
531 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
532 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
533 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
534
535 if (phy->radio_rev == 5) {
536 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
537 b43_radio_mask(dev, 0x1ca, ~0x2);
538 }
539 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
540 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
541 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
542 tmp << 2);
543 }
544
545 return tmp & 0x3e;
546}
547
548/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
549static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
550{
551 struct b43_phy *phy = &dev->phy;
552 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
553 phy->radio_rev == 6);
554 u16 tmp;
555
556 if (special) {
557 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
558 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
559 } else {
560 b43_radio_write(dev, 0x1AE, 0x61);
561 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
562 }
563 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
564 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
565 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
566 5000000))
567 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
568 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
569 if (special) {
570 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
571 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
572 } else {
573 b43_radio_write(dev, 0x1AE, 0x69);
574 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
575 }
576 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
577 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
578 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
579 5000000))
6c187236 580 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 581 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
582 if (special) {
583 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
584 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
585 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
586 } else {
587 b43_radio_write(dev, 0x1AE, 0x73);
588 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
589 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
590 }
591 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
592 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
593 5000000)) {
594 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
595 return 0;
596 }
597 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
598 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
599 return tmp;
600}
601
602static void b43_radio_2057_init_pre(struct b43_wldev *dev)
603{
604 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
605 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
606 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
607 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
608 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
609}
610
611static void b43_radio_2057_init_post(struct b43_wldev *dev)
612{
613 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
614
615 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
616 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
617 mdelay(2);
618 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
619 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
620
621 if (dev->phy.n->init_por) {
622 b43_radio_2057_rcal(dev);
623 b43_radio_2057_rccal(dev);
624 }
625 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
626
627 dev->phy.n->init_por = false;
628}
629
630/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
631static void b43_radio_2057_init(struct b43_wldev *dev)
632{
633 b43_radio_2057_init_pre(dev);
634 r2057_upload_inittabs(dev);
635 b43_radio_2057_init_post(dev);
636}
637
ab499217 638/**************************************************
884a5228 639 * Radio 0x2056
ab499217 640 **************************************************/
7955de0c 641
d4814e69
RM		 642static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
643 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 644{
d4814e69
RM		 645 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
646 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
647 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
648 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
649 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
650 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
651 e->radio_syn_pll_loopfilter1);
652 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
653 e->radio_syn_pll_loopfilter2);
654 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
655 e->radio_syn_pll_loopfilter3);
656 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
657 e->radio_syn_pll_loopfilter4);
658 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
659 e->radio_syn_pll_loopfilter5);
660 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
661 e->radio_syn_reserved_addr27);
662 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
663 e->radio_syn_reserved_addr28);
664 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
665 e->radio_syn_reserved_addr29);
666 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
667 e->radio_syn_logen_vcobuf1);
668 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
669 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
670 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
671
672 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
673 e->radio_rx0_lnaa_tune);
674 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
675 e->radio_rx0_lnag_tune);
676
677 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
678 e->radio_tx0_intpaa_boost_tune);
679 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
680 e->radio_tx0_intpag_boost_tune);
681 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
682 e->radio_tx0_pada_boost_tune);
683 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
684 e->radio_tx0_padg_boost_tune);
685 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
686 e->radio_tx0_pgaa_boost_tune);
687 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
688 e->radio_tx0_pgag_boost_tune);
689 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
690 e->radio_tx0_mixa_boost_tune);
691 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
692 e->radio_tx0_mixg_boost_tune);
693
694 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
695 e->radio_rx1_lnaa_tune);
696 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
697 e->radio_rx1_lnag_tune);
698
699 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
700 e->radio_tx1_intpaa_boost_tune);
701 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
702 e->radio_tx1_intpag_boost_tune);
703 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
704 e->radio_tx1_pada_boost_tune);
705 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
706 e->radio_tx1_padg_boost_tune);
707 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
708 e->radio_tx1_pgaa_boost_tune);
709 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
710 e->radio_tx1_pgag_boost_tune);
711 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
712 e->radio_tx1_mixa_boost_tune);
713 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
714 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 715}
716
d4814e69
RM		 717/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
718static void b43_radio_2056_setup(struct b43_wldev *dev,
719 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 720{
0581483a 721 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 722 enum ieee80211_band band = b43_current_band(dev->wl);
723 u16 offset;
724 u8 i;
d3d178f0
RM		 725 u16 bias, cbias;
726 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
727 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
036cafe4 728
d4814e69 729 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 730
d4814e69 731 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 732 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
733
734 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
735 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
737 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
738 if (dev->dev->chip_id == 0x4716) {
739 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
740 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
741 } else {
742 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
743 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 744 }
53a6e234 745 }
38646eba
RM		 746 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
747 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
748 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
749 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
750 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
751 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 752 }
53a6e234 753
38646eba
RM		 754 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
755 for (i = 0; i < 2; i++) {
756 offset = i ? B2056_TX1 : B2056_TX0;
757 if (dev->phy.rev >= 5) {
758 b43_radio_write(dev,
759 offset | B2056_TX_PADG_IDAC, 0xcc);
760
761 if (dev->dev->chip_id == 0x4716) {
762 bias = 0x40;
763 cbias = 0x45;
764 pag_boost = 0x5;
765 pgag_boost = 0x33;
766 mixg_boost = 0x55;
767 } else {
768 bias = 0x25;
769 cbias = 0x20;
770 pag_boost = 0x4;
771 pgag_boost = 0x03;
772 mixg_boost = 0x65;
773 }
774 padg_boost = 0x77;
775
776 b43_radio_write(dev,
777 offset | B2056_TX_INTPAG_IMAIN_STAT,
778 bias);
779 b43_radio_write(dev,
780 offset | B2056_TX_INTPAG_IAUX_STAT,
781 bias);
782 b43_radio_write(dev,
783 offset | B2056_TX_INTPAG_CASCBIAS,
784 cbias);
785 b43_radio_write(dev,
786 offset | B2056_TX_INTPAG_BOOST_TUNE,
787 pag_boost);
788 b43_radio_write(dev,
789 offset | B2056_TX_PGAG_BOOST_TUNE,
790 pgag_boost);
791 b43_radio_write(dev,
792 offset | B2056_TX_PADG_BOOST_TUNE,
793 padg_boost);
794 b43_radio_write(dev,
795 offset | B2056_TX_MIXG_BOOST_TUNE,
796 mixg_boost);
797 } else {
798 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
799 b43_radio_write(dev,
800 offset | B2056_TX_INTPAG_IMAIN_STAT,
801 bias);
802 b43_radio_write(dev,
803 offset | B2056_TX_INTPAG_IAUX_STAT,
804 bias);
805 b43_radio_write(dev,
806 offset | B2056_TX_INTPAG_CASCBIAS,
807 0x30);
808 }
809 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
810 }
811 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 812 u16 freq = dev->phy.channel_freq;
813 if (freq < 5100) {
814 paa_boost = 0xA;
815 pada_boost = 0x77;
816 pgaa_boost = 0xF;
817 mixa_boost = 0xF;
818 } else if (freq < 5340) {
819 paa_boost = 0x8;
820 pada_boost = 0x77;
821 pgaa_boost = 0xFB;
822 mixa_boost = 0xF;
823 } else if (freq < 5650) {
824 paa_boost = 0x0;
825 pada_boost = 0x77;
826 pgaa_boost = 0xB;
827 mixa_boost = 0xF;
828 } else {
829 paa_boost = 0x0;
830 pada_boost = 0x77;
831 if (freq != 5825)
832 pgaa_boost = -(freq - 18) / 36 + 168;
833 else
834 pgaa_boost = 6;
835 mixa_boost = 0xF;
836 }
837
838 for (i = 0; i < 2; i++) {
839 offset = i ? B2056_TX1 : B2056_TX0;
840
841 b43_radio_write(dev,
842 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
843 b43_radio_write(dev,
844 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
845 b43_radio_write(dev,
846 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
847 b43_radio_write(dev,
848 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
849 b43_radio_write(dev,
850 offset | B2056_TX_TXSPARE1, 0x30);
851 b43_radio_write(dev,
852 offset | B2056_TX_PA_SPARE2, 0xee);
853 b43_radio_write(dev,
854 offset | B2056_TX_PADA_CASCBIAS, 0x03);
855 b43_radio_write(dev,
856 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
857 b43_radio_write(dev,
858 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
859 b43_radio_write(dev,
860 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
861 }
a2d9bc6f 862 }
38646eba 863
d4814e69
RM		 864 udelay(50);
865 /* VCO calibration */
866 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
867 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
868 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
869 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
870 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
871 udelay(300);
53a6e234
MB		 872}
873
d3d178f0
RM		 874static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
875{
876 struct b43_phy *phy = &dev->phy;
877 u16 mast2, tmp;
878
879 if (phy->rev != 3)
880 return 0;
881
882 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
883 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
884
885 udelay(10);
886 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
887 udelay(10);
888 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
889
890 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
891 1000000)) {
892 b43err(dev->wl, "Radio recalibration timeout\n");
893 return 0;
894 }
895
896 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
897 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
898 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
899
900 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
901
902 return tmp & 0x1f;
903}
904
ea7ee14b
RM		 905static void b43_radio_init2056_pre(struct b43_wldev *dev)
906{
907 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
908 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
909 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
910 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
911 B43_NPHY_RFCTL_CMD_OEPORFORCE);
912 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
913 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
914 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
915 B43_NPHY_RFCTL_CMD_CHIP0PU);
916}
917
918static void b43_radio_init2056_post(struct b43_wldev *dev)
919{
920 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
921 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
922 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
923 msleep(1);
924 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
925 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
926 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 927 if (dev->phy.n->init_por)
928 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 929}
930
d817f4e1
RM		 931/*
932 * Initialize a Broadcom 2056 N-radio
933 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
934 */
935static void b43_radio_init2056(struct b43_wldev *dev)
936{
ea7ee14b
RM		 937 b43_radio_init2056_pre(dev);
938 b2056_upload_inittabs(dev, 0, 0);
939 b43_radio_init2056_post(dev);
d3d178f0
RM		 940
941 dev->phy.n->init_por = false;
d817f4e1
RM		 942}
943
884a5228
RM		 944/**************************************************
945 * Radio 0x2055
946 **************************************************/
947
948static void b43_chantab_radio_upload(struct b43_wldev *dev,
949 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 950{
884a5228
RM		 951 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
952 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
953 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
954 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
955 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 956
884a5228
RM		 957 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
958 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
959 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
960 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
961 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 962
884a5228
RM		 963 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
964 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
965 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
966 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
967 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 968
884a5228
RM		 969 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
970 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
971 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
972 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
973 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 974
884a5228
RM		 975 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
976 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
977 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
978 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
979 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 980
884a5228
RM		 981 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
982 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 983}
984
884a5228
RM		 985/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
986static void b43_radio_2055_setup(struct b43_wldev *dev,
987 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 988{
884a5228 989 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 990
884a5228
RM		 991 b43_chantab_radio_upload(dev, e);
992 udelay(50);
993 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
994 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
995 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
996 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
997 udelay(300);
95b66bad
MB		 998}
999
884a5228 1000static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1001{
884a5228
RM		 1002 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1003 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1004 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1005 B43_NPHY_RFCTL_CMD_CHIP0PU |
1006 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1007 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1008 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1009}
1010
884a5228 1011static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1012{
1013 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1014 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1015 bool workaround = false;
2faa6b83 1016
884a5228
RM		 1017 if (sprom->revision < 4)
1018 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1019 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1020 && dev->dev->board_rev >= 0x41);
2faa6b83 1021 else
884a5228
RM		 1022 workaround =
1023 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1024
884a5228
RM		 1025 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1026 if (workaround) {
1027 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1028 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1029 }
1030 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1031 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1032 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1033 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1034 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1035 msleep(1);
1036 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1037 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1038 b43err(dev->wl, "radio post init timeout\n");
1039 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1040 b43_switch_channel(dev, dev->phy.channel);
1041 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1042 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1043 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1044 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1045 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1046 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1047 if (!nphy->gain_boost) {
1048 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1049 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1050 } else {
1051 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1052 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1053 }
1054 udelay(2);
2faa6b83
RM		 1055}
1056
884a5228
RM		 1057/*
1058 * Initialize a Broadcom 2055 N-radio
1059 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1060 */
1061static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1062{
884a5228
RM		 1063 b43_radio_init2055_pre(dev);
1064 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1065 /* Follow wl, not specs. Do not force uploading all regs */
1066 b2055_upload_inittab(dev, 0, 0);
a67162ab 1067 } else {
884a5228
RM		 1068 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1069 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1070 }
884a5228 1071 b43_radio_init2055_post(dev);
a67162ab
RM		 1072}
1073
8be89535
RM		 1074/**************************************************
1075 * Samples
1076 **************************************************/
026816fc 1077
8be89535
RM		 1078/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1079static int b43_nphy_load_samples(struct b43_wldev *dev,
1080 struct b43_c32 *samples, u16 len) {
1081 struct b43_phy_n *nphy = dev->phy.n;
1082 u16 i;
1083 u32 *data;
1084
1085 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1086 if (!data) {
1087 b43err(dev->wl, "allocation for samples loading failed\n");
1088 return -ENOMEM;
1089 }
1090 if (nphy->hang_avoid)
1091 b43_nphy_stay_in_carrier_search(dev, 1);
1092
1093 for (i = 0; i < len; i++) {
1094 data[i] = (samples[i].i & 0x3FF << 10);
1095 data[i] |= samples[i].q & 0x3FF;
1096 }
1097 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1098
1099 kfree(data);
1100 if (nphy->hang_avoid)
1101 b43_nphy_stay_in_carrier_search(dev, 0);
1102 return 0;
026816fc
RM		 1103}
1104
8be89535
RM		 1105/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1106static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1107 bool test)
026816fc 1108{
8be89535
RM		 1109 int i;
1110 u16 bw, len, rot, angle;
1111 struct b43_c32 *samples;
026816fc 1112
026816fc 1113
8be89535
RM		 1114 bw = (dev->phy.is_40mhz) ? 40 : 20;
1115 len = bw << 3;
026816fc 1116
8be89535
RM		 1117 if (test) {
1118 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1119 bw = 82;
1120 else
1121 bw = 80;
026816fc 1122
8be89535
RM		 1123 if (dev->phy.is_40mhz)
1124 bw <<= 1;
1125
1126 len = bw << 1;
026816fc
RM		 1127 }
1128
8be89535
RM		 1129 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1130 if (!samples) {
1131 b43err(dev->wl, "allocation for samples generation failed\n");
1132 return 0;
1133 }
1134 rot = (((freq * 36) / bw) << 16) / 100;
1135 angle = 0;
026816fc 1136
8be89535
RM		 1137 for (i = 0; i < len; i++) {
1138 samples[i] = b43_cordic(angle);
1139 angle += rot;
1140 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1141 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1142 }
8be89535
RM		 1143
1144 i = b43_nphy_load_samples(dev, samples, len);
1145 kfree(samples);
1146 return (i < 0) ? 0 : len;
026816fc
RM		 1147}
1148
8be89535
RM		 1149/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1150static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1151 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1152{
8be89535 1153 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1154 int i;
8be89535
RM		 1155 u16 seq_mode;
1156 u32 tmp;
34a56f2c 1157
8be89535
RM		 1158 if (nphy->hang_avoid)
1159 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1160
8be89535
RM		 1161 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1162 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1163 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1164 }
34a56f2c 1165
8be89535
RM		 1166 if (!dev->phy.is_40mhz)
1167 tmp = 0x6464;
1168 else
1169 tmp = 0x4747;
1170 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1171
8be89535
RM		 1172 if (nphy->hang_avoid)
1173 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c 1174
8be89535 1175 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1176
8be89535
RM		 1177 if (loops != 0xFFFF)
1178 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1179 else
1180 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1181
8be89535 1182 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1183
8be89535 1184 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1185
8be89535
RM		 1186 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1187 if (iqmode) {
1188 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1189 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1190 } else {
1191 if (dac_test)
1192 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1193 else
1194 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1195 }
1196 for (i = 0; i < 100; i++) {
2c8ac7eb 1197 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1198 i = 0;
1199 break;
34a56f2c 1200 }
8be89535 1201 udelay(10);
34a56f2c 1202 }
8be89535
RM		 1203 if (i)
1204 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1205
8be89535 1206 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
34a56f2c
RM		 1207}
1208
4d9f46ba
RM		 1209/**************************************************
1210 * RSSI
1211 **************************************************/
1212
1213/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1214static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1215 s8 offset, u8 core,
1216 enum n_rail_type rail,
2a2d0589 1217 enum n_rssi_type rssi_type)
09146400 1218{
4d9f46ba
RM		 1219 u16 tmp;
1220 bool core1or5 = (core == 1) || (core == 5);
1221 bool core2or5 = (core == 2) || (core == 5);
09146400 1222
4d9f46ba
RM		 1223 offset = clamp_val(offset, -32, 31);
1224 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1225
e5ab1fd7 1226 switch (rssi_type) {
2a2d0589 1227 case N_RSSI_NB:
e5ab1fd7
RM		 1228 if (core1or5 && rail == N_RAIL_I)
1229 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1230 if (core1or5 && rail == N_RAIL_Q)
1231 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1232 if (core2or5 && rail == N_RAIL_I)
1233 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1234 if (core2or5 && rail == N_RAIL_Q)
1235 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1236 break;
2a2d0589 1237 case N_RSSI_W1:
e5ab1fd7
RM		 1238 if (core1or5 && rail == N_RAIL_I)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1240 if (core1or5 && rail == N_RAIL_Q)
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1242 if (core2or5 && rail == N_RAIL_I)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1244 if (core2or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1246 break;
2a2d0589 1247 case N_RSSI_W2:
e5ab1fd7
RM		 1248 if (core1or5 && rail == N_RAIL_I)
1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1250 if (core1or5 && rail == N_RAIL_Q)
1251 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1252 if (core2or5 && rail == N_RAIL_I)
1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1254 if (core2or5 && rail == N_RAIL_Q)
1255 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1256 break;
2a2d0589 1257 case N_RSSI_TBD:
e5ab1fd7
RM		 1258 if (core1or5 && rail == N_RAIL_I)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1260 if (core1or5 && rail == N_RAIL_Q)
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1262 if (core2or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1264 if (core2or5 && rail == N_RAIL_Q)
1265 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1266 break;
2a2d0589 1267 case N_RSSI_IQ:
e5ab1fd7
RM		 1268 if (core1or5 && rail == N_RAIL_I)
1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1270 if (core1or5 && rail == N_RAIL_Q)
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1272 if (core2or5 && rail == N_RAIL_I)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1274 if (core2or5 && rail == N_RAIL_Q)
1275 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1276 break;
2a2d0589 1277 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1278 if (core1or5)
1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1280 if (core2or5)
1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1282 break;
2a2d0589 1283 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1284 if (core1or5)
1285 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1286 if (core2or5)
1287 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1288 break;
1289 }
8987a9e9
RM		 1290}
1291
a3764ef7
RM		 1292static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1293 enum n_rssi_type rssi_type)
bbec398c 1294{
4d9f46ba
RM		 1295 u8 i;
1296 u16 reg, val;
bbec398c 1297
4d9f46ba
RM		 1298 if (code == 0) {
1299 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1300 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1301 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1302 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1303 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1304 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1305 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1306 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1307 } else {
1308 for (i = 0; i < 2; i++) {
1309 if ((code == 1 && i == 1) || (code == 2 && !i))
1310 continue;
bbec398c 1311
4d9f46ba
RM		 1312 reg = (i == 0) ?
1313 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1314 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1315
a3764ef7
RM		 1316 if (rssi_type == N_RSSI_W1 ||
1317 rssi_type == N_RSSI_W2 ||
1318 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1319 reg = (i == 0) ?
1320 B43_NPHY_AFECTL_C1 :
1321 B43_NPHY_AFECTL_C2;
1322 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1323
4d9f46ba
RM		 1324 reg = (i == 0) ?
1325 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1326 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1327 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1328
a3764ef7 1329 if (rssi_type == N_RSSI_W1)
4d9f46ba 1330 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1331 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1332 val = 16;
1333 else
1334 val = 32;
1335 b43_phy_set(dev, reg, val);
5c1a140a 1336
4d9f46ba
RM		 1337 reg = (i == 0) ?
1338 B43_NPHY_TXF_40CO_B1S0 :
1339 B43_NPHY_TXF_40CO_B32S1;
1340 b43_phy_set(dev, reg, 0x0020);
1341 } else {
a3764ef7 1342 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1343 val = 0x0100;
a3764ef7 1344 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1345 val = 0x0200;
1346 else
1347 val = 0x0300;
5c1a140a 1348
4d9f46ba
RM		 1349 reg = (i == 0) ?
1350 B43_NPHY_AFECTL_C1 :
1351 B43_NPHY_AFECTL_C2;
53ae8e8c 1352
4d9f46ba
RM		 1353 b43_phy_maskset(dev, reg, 0xFCFF, val);
1354 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1355
a3764ef7
RM		 1356 if (rssi_type != N_RSSI_IQ &&
1357 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1358 enum ieee80211_band band =
1359 b43_current_band(dev->wl);
53ae8e8c 1360
4d9f46ba
RM		 1361 if (b43_nphy_ipa(dev))
1362 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1363 else
1364 val = 0x11;
1365 reg = (i == 0) ? 0x2000 : 0x3000;
1366 reg |= B2055_PADDRV;
1367 b43_radio_write16(dev, reg, val);
53ae8e8c 1368
4d9f46ba
RM		 1369 reg = (i == 0) ?
1370 B43_NPHY_AFECTL_OVER1 :
1371 B43_NPHY_AFECTL_OVER;
1372 b43_phy_set(dev, reg, 0x0200);
1373 }
1374 }
1375 }
53ae8e8c 1376 }
53ae8e8c
RM		 1377}
1378
a3764ef7
RM		 1379static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1380 enum n_rssi_type rssi_type)
9442e5b5 1381{
4d9f46ba 1382 u16 val;
a3764ef7 1383 bool rssi_w1_w2_nb = false;
9442e5b5 1384
a3764ef7
RM		 1385 switch (rssi_type) {
1386 case N_RSSI_W1:
1387 case N_RSSI_W2:
1388 case N_RSSI_NB:
4d9f46ba 1389 val = 0;
a3764ef7
RM		 1390 rssi_w1_w2_nb = true;
1391 break;
1392 case N_RSSI_TBD:
4d9f46ba 1393 val = 1;
a3764ef7
RM		 1394 break;
1395 case N_RSSI_IQ:
4d9f46ba 1396 val = 2;
a3764ef7
RM		 1397 break;
1398 default:
4d9f46ba 1399 val = 3;
a3764ef7 1400 }
9442e5b5 1401
4d9f46ba
RM		 1402 val = (val << 12) | (val << 14);
1403 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1404 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1405
a3764ef7 1406 if (rssi_w1_w2_nb) {
4d9f46ba 1407 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1408 (rssi_type + 1) << 4);
4d9f46ba 1409 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1410 (rssi_type + 1) << 4);
9442e5b5
RM		 1411 }
1412
4d9f46ba
RM		 1413 if (code == 0) {
1414 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1415 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1416 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1417 ~(B43_NPHY_RFCTL_CMD_RXEN |
1418 B43_NPHY_RFCTL_CMD_CORESEL));
1419 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1420 ~(0x1 << 12 |
1421 0x1 << 5 |
1422 0x1 << 1 |
1423 0x1));
1424 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1425 ~B43_NPHY_RFCTL_CMD_START);
1426 udelay(20);
1427 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1428 }
1429 } else {
1430 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1431 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1432 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1433 ~(B43_NPHY_RFCTL_CMD_RXEN |
1434 B43_NPHY_RFCTL_CMD_CORESEL),
1435 (B43_NPHY_RFCTL_CMD_RXEN |
1436 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1437 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1438 (0x1 << 12 |
1439 0x1 << 5 |
1440 0x1 << 1 |
1441 0x1));
1442 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1443 B43_NPHY_RFCTL_CMD_START);
1444 udelay(20);
1445 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1446 }
9442e5b5 1447 }
9442e5b5
RM		 1448}
1449
4d9f46ba 1450/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1451static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1452 enum n_rssi_type type)
d24019ad 1453{
4d9f46ba
RM		 1454 if (dev->phy.rev >= 3)
1455 b43_nphy_rev3_rssi_select(dev, code, type);
1456 else
1457 b43_nphy_rev2_rssi_select(dev, code, type);
1458}
d24019ad 1459
5ecab603 1460/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1461static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1462 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1463{
1464 int i;
d24019ad 1465 for (i = 0; i < 2; i++) {
a3764ef7 1466 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1467 if (i == 0) {
1468 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1469 0xFC, buf[0]);
1470 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1471 0xFC, buf[1]);
1472 } else {
1473 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1474 0xFC, buf[2 * i]);
1475 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1476 0xFC, buf[2 * i + 1]);
1477 }
d24019ad 1478 } else {
5ecab603
RM		 1479 if (i == 0)
1480 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1481 0xF3, buf[0] << 2);
1482 else
1483 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1484 0xF3, buf[2 * i + 1] << 2);
d24019ad 1485 }
d24019ad 1486 }
d24019ad
RM		 1487}
1488
5ecab603 1489/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1490static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1491 s32 *buf, u8 nsamp)
ef5127a4 1492{
5ecab603
RM		 1493 int i;
1494 int out;
1495 u16 save_regs_phy[9];
1496 u16 s[2];
ef5127a4
RM		 1497
1498 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1499 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1500 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1501 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1502 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1503 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1504 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1505 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1506 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1507 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1508 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1509 save_regs_phy[8] = 0;
ef5127a4 1510 } else {
5ecab603
RM		 1511 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1512 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1513 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1514 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1515 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1516 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1517 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1518 save_regs_phy[7] = 0;
1519 save_regs_phy[8] = 0;
1520 }
ef5127a4 1521
a3764ef7 1522 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1523
5ecab603
RM		 1524 if (dev->phy.rev < 2) {
1525 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1526 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1527 }
ef5127a4 1528
5ecab603
RM		 1529 for (i = 0; i < 4; i++)
1530 buf[i] = 0;
1531
1532 for (i = 0; i < nsamp; i++) {
1533 if (dev->phy.rev < 2) {
1534 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1535 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1536 } else {
5ecab603
RM		 1537 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1538 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1539 }
1540
5ecab603
RM		 1541 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1542 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1543 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1544 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1545 }
1546 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1547 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1548
5ecab603
RM		 1549 if (dev->phy.rev < 2)
1550 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1551
5ecab603 1552 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1553 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1554 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1555 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1556 save_regs_phy[2]);
5ecab603 1557 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1558 save_regs_phy[3]);
5ecab603
RM		 1559 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1560 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1561 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1562 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1563 } else {
1564 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1565 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1566 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1567 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1568 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1569 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1570 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1571 }
ef5127a4 1572
5ecab603
RM		 1573 return out;
1574}
ef5127a4 1575
e0c9a021
RM		 1576/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1577static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1578{
1579 struct b43_phy_n *nphy = dev->phy.n;
1580
1581 u16 saved_regs_phy_rfctl[2];
1582 u16 saved_regs_phy[13];
1583 u16 regs_to_store[] = {
1584 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1585 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1586 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1587 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1588 B43_NPHY_RFCTL_CMD,
1589 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1590 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1591 };
1592
1593 u16 class;
1594
1595 u16 clip_state[2];
1596 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1597
1598 u8 vcm_final = 0;
2e1253d6 1599 s32 offset[4];
e0c9a021
RM		 1600 s32 results[8][4] = { };
1601 s32 results_min[4] = { };
1602 s32 poll_results[4] = { };
1603
1604 u16 *rssical_radio_regs = NULL;
1605 u16 *rssical_phy_regs = NULL;
1606
1607 u16 r; /* routing */
1608 u8 rx_core_state;
37859a75 1609 int core, i, j, vcm;
e0c9a021
RM		 1610
1611 class = b43_nphy_classifier(dev, 0, 0);
1612 b43_nphy_classifier(dev, 7, 4);
1613 b43_nphy_read_clip_detection(dev, clip_state);
1614 b43_nphy_write_clip_detection(dev, clip_off);
1615
1616 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1617 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1618 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1619 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1620
1621 b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1622 b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1623 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1624 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1625 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1626 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1627
1628 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1629 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1630 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1631 } else {
1632 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1633 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1634 }
1635
1636 rx_core_state = b43_nphy_get_rx_core_state(dev);
1637 for (core = 0; core < 2; core++) {
1638 if (!(rx_core_state & (1 << core)))
1639 continue;
1640 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1641 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1642 N_RSSI_NB);
1643 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1644 N_RSSI_NB);
37859a75
RM		 1645
1646 /* Grab RSSI results for every possible VCM */
1647 for (vcm = 0; vcm < 8; vcm++) {
e0c9a021 1648 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
37859a75 1649 vcm << 2);
a3764ef7 1650 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1651 }
37859a75
RM		 1652
1653 /* Find out which VCM got the best results */
cddec902 1654 for (i = 0; i < 4; i += 2) {
37859a75 1655 s32 currd;
e67dd874 1656 s32 mind = 0x100000;
e0c9a021
RM		 1657 s32 minpoll = 249;
1658 u8 minvcm = 0;
1659 if (2 * core != i)
1660 continue;
37859a75
RM		 1661 for (vcm = 0; vcm < 8; vcm++) {
1662 currd = results[vcm][i] * results[vcm][i] +
1663 results[vcm][i + 1] * results[vcm][i];
1664 if (currd < mind) {
1665 mind = currd;
1666 minvcm = vcm;
e0c9a021 1667 }
37859a75
RM		 1668 if (results[vcm][i] < minpoll)
1669 minpoll = results[vcm][i];
e0c9a021
RM		 1670 }
1671 vcm_final = minvcm;
1672 results_min[i] = minpoll;
1673 }
37859a75
RM		 1674
1675 /* Select the best VCM */
e0c9a021
RM		 1676 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1677 vcm_final << 2);
37859a75 1678
e0c9a021
RM		 1679 for (i = 0; i < 4; i++) {
1680 if (core != i / 2)
1681 continue;
1682 offset[i] = -results[vcm_final][i];
1683 if (offset[i] < 0)
1684 offset[i] = -((abs(offset[i]) + 4) / 8);
1685 else
1686 offset[i] = (offset[i] + 4) / 8;
1687 if (results_min[i] == 248)
1688 offset[i] = -32;
1689 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1690 (i / 2 == 0) ? 1 : 2,
6aa38725 1691 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1692 N_RSSI_NB);
e0c9a021
RM		 1693 }
1694 }
37859a75 1695
e0c9a021
RM		 1696 for (core = 0; core < 2; core++) {
1697 if (!(rx_core_state & (1 << core)))
1698 continue;
1699 for (i = 0; i < 2; i++) {
6aa38725
RM		 1700 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1701 N_RAIL_I, i);
1702 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1703 N_RAIL_Q, i);
e0c9a021
RM		 1704 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1705 for (j = 0; j < 4; j++) {
cddec902 1706 if (j / 2 == core) {
e0c9a021 1707 offset[j] = 232 - poll_results[j];
cddec902
RM		 1708 if (offset[j] < 0)
1709 offset[j] = -(abs(offset[j] + 4) / 8);
1710 else
1711 offset[j] = (offset[j] + 4) / 8;
1712 b43_nphy_scale_offset_rssi(dev, 0,
1713 offset[2 * core], core + 1, j % 2, i);
1714 }
e0c9a021
RM		 1715 }
1716 }
1717 }
1718
1719 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1720 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1721
1722 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1723
1724 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1725 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1726 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1727
1728 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1729 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1730 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1731
1732 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1733 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1734
1735 /* Store for future configuration */
1736 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1737 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1738 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1739 } else {
1740 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1741 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1742 }
1743 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1744 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1745 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1746 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1747 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1748 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1749 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1750 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1751 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1752 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1753 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1754 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1755 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1756 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1757
1758 /* Remember for which channel we store configuration */
1759 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1760 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1761 else
1762 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1763
1764 /* End of calibration, restore configuration */
1765 b43_nphy_classifier(dev, 7, class);
1766 b43_nphy_write_clip_detection(dev, clip_state);
1767}
1768
5ecab603 1769/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1770static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1771{
37859a75 1772 int i, j, vcm;
5ecab603
RM		 1773 u8 state[4];
1774 u8 code, val;
1775 u16 class, override;
1776 u8 regs_save_radio[2];
1777 u16 regs_save_phy[2];
1778
2e1253d6 1779 s32 offset[4];
5ecab603
RM		 1780 u8 core;
1781 u8 rail;
1782
1783 u16 clip_state[2];
1784 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1785 s32 results_min[4] = { };
1786 u8 vcm_final[4] = { };
1787 s32 results[4][4] = { };
1788 s32 miniq[4][2] = { };
1789
a3764ef7 1790 if (type == N_RSSI_NB) {
5ecab603
RM		 1791 code = 0;
1792 val = 6;
a3764ef7 1793 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1794 code = 25;
1795 val = 4;
1796 } else {
1797 B43_WARN_ON(1);
1798 return;
1799 }
1800
1801 class = b43_nphy_classifier(dev, 0, 0);
1802 b43_nphy_classifier(dev, 7, 4);
1803 b43_nphy_read_clip_detection(dev, clip_state);
1804 b43_nphy_write_clip_detection(dev, clip_off);
1805
1806 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1807 override = 0x140;
1808 else
1809 override = 0x110;
1810
1811 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1812 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1813 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1814 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1815
1816 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1817 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1818 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1819 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1820
1821 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1822 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1823 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1824 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1825 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1826 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1827
1828 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1829 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1830 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1831
37859a75 1832 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1833 u8 tmp[4];
1834 for (j = 0; j < 4; j++)
37859a75 1835 tmp[j] = vcm;
a3764ef7 1836 if (type != N_RSSI_W2)
5ecab603 1837 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1838 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1839 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1840 for (j = 0; j < 2; j++)
37859a75
RM		 1841 miniq[vcm][j] = min(results[vcm][2 * j],
1842 results[vcm][2 * j + 1]);
5ecab603
RM		 1843 }
1844
1845 for (i = 0; i < 4; i++) {
e67dd874 1846 s32 mind = 0x100000;
5ecab603
RM		 1847 u8 minvcm = 0;
1848 s32 minpoll = 249;
37859a75
RM		 1849 s32 currd;
1850 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1851 if (type == N_RSSI_NB)
542e15f3 1852 currd = abs(results[vcm][i] - code * 8);
5ecab603 1853 else
37859a75 1854 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1855
37859a75
RM		 1856 if (currd < mind) {
1857 mind = currd;
1858 minvcm = vcm;
5ecab603
RM		 1859 }
1860
37859a75
RM		 1861 if (results[vcm][i] < minpoll)
1862 minpoll = results[vcm][i];
8e60b044 1863 }
5ecab603
RM		 1864 results_min[i] = minpoll;
1865 vcm_final[i] = minvcm;
1866 }
ef5127a4 1867
a3764ef7 1868 if (type != N_RSSI_W2)
5ecab603 1869 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 1870
5ecab603
RM		 1871 for (i = 0; i < 4; i++) {
1872 offset[i] = (code * 8) - results[vcm_final[i]][i];
1873
1874 if (offset[i] < 0)
1875 offset[i] = -((abs(offset[i]) + 4) / 8);
1876 else
1877 offset[i] = (offset[i] + 4) / 8;
1878
1879 if (results_min[i] == 248)
1880 offset[i] = code - 32;
1881
1882 core = (i / 2) ? 2 : 1;
6aa38725 1883 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 1884
1885 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1886 type);
1887 }
1888
1889 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1890 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1891
1892 switch (state[2]) {
1893 case 1:
a3764ef7 1894 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 1895 break;
1896 case 4:
a3764ef7 1897 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 1898 break;
1899 case 2:
a3764ef7 1900 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 1901 break;
1902 default:
a3764ef7 1903 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 1904 break;
1905 }
1906
1907 switch (state[3]) {
1908 case 1:
a3764ef7 1909 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 1910 break;
1911 case 4:
a3764ef7 1912 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 1913 break;
1914 default:
a3764ef7 1915 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 1916 break;
1917 }
1918
1919 b43_nphy_rssi_select(dev, 0, type);
1920
1921 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1922 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1923 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1924 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1925
1926 b43_nphy_classifier(dev, 7, class);
1927 b43_nphy_write_clip_detection(dev, clip_state);
1928 /* Specs don't say about reset here, but it makes wl and b43 dumps
1929 identical, it really seems wl performs this */
1930 b43_nphy_reset_cca(dev);
1931}
1932
5ecab603
RM		 1933/*
1934 * RSSI Calibration
1935 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1936 */
1937static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1938{
1939 if (dev->phy.rev >= 3) {
1940 b43_nphy_rev3_rssi_cal(dev);
1941 } else {
2a2d0589
RM		 1942 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1943 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1944 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 1945 }
1946}
1947
64712095
RM		 1948/**************************************************
1949 * Workarounds
1950 **************************************************/
1951
1952static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1953{
1954 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1955
1956 bool ghz5;
1957 bool ext_lna;
1958 u16 rssi_gain;
1959 struct nphy_gain_ctl_workaround_entry *e;
1960 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1961 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1962
1963 /* Prepare values */
1964 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1965 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 1966 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1967 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 1968 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1969 if (ghz5 && dev->phy.rev >= 5)
1970 rssi_gain = 0x90;
1971 else
1972 rssi_gain = 0x50;
1973
1974 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1975
1976 /* Set Clip 2 detect */
04519dc6
RM		 1977 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1978 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 1979
1980 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1981 0x17);
1982 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1983 0x17);
1984 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1985 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1986 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1987 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1988 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1989 rssi_gain);
1990 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1991 rssi_gain);
1992 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1993 0x17);
1994 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1995 0x17);
1996 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1997 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1998
1999 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2000 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2001 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2002 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2003 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2004 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2005 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2006 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2007 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2008 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2009 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2010 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2011
04519dc6
RM		 2012 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2013 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2014
64712095
RM		 2015 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2016 e->rfseq_init);
64712095 2017
04519dc6
RM		 2018 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2019 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2020 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2021 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2022 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2023 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2024
2025 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2026 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2027 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2028 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2029 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2030 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2031 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2032 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2033 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2034 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2035}
2036
2037static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2038{
2039 struct b43_phy_n *nphy = dev->phy.n;
2040
2041 u8 i, j;
2042 u8 code;
2043 u16 tmp;
2044 u8 rfseq_events[3] = { 6, 8, 7 };
2045 u8 rfseq_delays[3] = { 10, 30, 1 };
2046
2047 /* Set Clip 2 detect */
2048 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2049 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2050
2051 /* Set narrowband clip threshold */
2052 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2053 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2054
2055 if (!dev->phy.is_40mhz) {
2056 /* Set dwell lengths */
2057 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2058 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2059 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2060 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2061 }
2062
2063 /* Set wideband clip 2 threshold */
2064 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2065 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2066 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2067 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2068
2069 if (!dev->phy.is_40mhz) {
2070 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2071 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2072 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2073 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2074 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2075 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2076 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2077 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2078 }
2079
2080 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2081
2082 if (nphy->gain_boost) {
2083 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2084 dev->phy.is_40mhz)
2085 code = 4;
2086 else
2087 code = 5;
2088 } else {
2089 code = dev->phy.is_40mhz ? 6 : 7;
2090 }
2091
2092 /* Set HPVGA2 index */
2093 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2094 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2095 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2096 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2097
2098 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2099 /* specs say about 2 loops, but wl does 4 */
2100 for (i = 0; i < 4; i++)
2101 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2102
2103 b43_nphy_adjust_lna_gain_table(dev);
2104
2105 if (nphy->elna_gain_config) {
2106 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2107 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2108 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2109 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2110 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2111
2112 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2113 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2114 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2115 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2116 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2117
2118 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2119 /* specs say about 2 loops, but wl does 4 */
2120 for (i = 0; i < 4; i++)
2121 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2122 (code << 8 | 0x74));
2123 }
2124
2125 if (dev->phy.rev == 2) {
2126 for (i = 0; i < 4; i++) {
2127 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2128 (0x0400 * i) + 0x0020);
2129 for (j = 0; j < 21; j++) {
2130 tmp = j * (i < 2 ? 3 : 1);
2131 b43_phy_write(dev,
2132 B43_NPHY_TABLE_DATALO, tmp);
2133 }
2134 }
ef5127a4 2135 }
64712095
RM		 2136
2137 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2138 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2139 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2140 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2141
2142 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2143 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2144}
2145
2146/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2147static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2148{
d11d354b
RM		 2149 if (dev->phy.rev >= 7)
2150 ; /* TODO */
2151 else if (dev->phy.rev >= 3)
64712095
RM		 2152 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2153 else
2154 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2155}
2156
d11d354b
RM		 2157/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2158static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2159{
2160 if (!offset)
2161 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2162 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2163}
2164
2165static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2166{
2167 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2168 struct b43_phy *phy = &dev->phy;
2169
2170 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2171 0x1F };
2172 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2173
2174 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2175 u8 ntab7_138_146[] = { 0x11, 0x11 };
2176 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2177
2178 u16 lpf_20, lpf_40, lpf_11b;
2179 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2180 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2181 bool rccal_ovrd = false;
2182
2183 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2184 u16 bias, conv, filt;
2185
2186 u32 tmp32;
2187 u8 core;
2188
2189 if (phy->rev == 7) {
2190 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2191 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2192 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2193 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2194 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2195 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2196 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2197 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2198 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2199 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2200 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2201 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2202 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2203 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2204 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2205 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2206 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2207 }
2208 if (phy->rev <= 8) {
04519dc6
RM		 2209 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2210 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2211 }
2212 if (phy->rev >= 8)
2213 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2214
2215 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2216 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2217 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2218 tmp32 &= 0xffffff;
2219 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2220 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2221 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2222
2223 if (b43_nphy_ipa(dev))
2224 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2225 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2226
04519dc6
RM		 2227 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2228 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2229
2230 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2231 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2232 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2233 if (b43_nphy_ipa(dev)) {
2234 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2235 phy->radio_rev == 7 || phy->radio_rev == 8) {
2236 bcap_val = b43_radio_read(dev, 0x16b);
2237 scap_val = b43_radio_read(dev, 0x16a);
2238 scap_val_11b = scap_val;
2239 bcap_val_11b = bcap_val;
2240 if (phy->radio_rev == 5 && phy->is_40mhz) {
2241 scap_val_11n_20 = scap_val;
2242 bcap_val_11n_20 = bcap_val;
2243 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2244 rccal_ovrd = true;
2245 } else { /* Rev 7/8 */
2246 lpf_20 = 4;
2247 lpf_11b = 1;
2248 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2249 scap_val_11n_20 = 0xc;
2250 bcap_val_11n_20 = 0xc;
2251 scap_val_11n_40 = 0xa;
2252 bcap_val_11n_40 = 0xa;
2253 } else {
2254 scap_val_11n_20 = 0x14;
2255 bcap_val_11n_20 = 0x14;
2256 scap_val_11n_40 = 0xf;
2257 bcap_val_11n_40 = 0xf;
2258 }
2259 rccal_ovrd = true;
2260 }
2261 }
2262 } else {
2263 if (phy->radio_rev == 5) {
2264 lpf_20 = 1;
2265 lpf_40 = 3;
2266 bcap_val = b43_radio_read(dev, 0x16b);
2267 scap_val = b43_radio_read(dev, 0x16a);
2268 scap_val_11b = scap_val;
2269 bcap_val_11b = bcap_val;
2270 scap_val_11n_20 = 0x11;
2271 scap_val_11n_40 = 0x11;
2272 bcap_val_11n_20 = 0x13;
2273 bcap_val_11n_40 = 0x13;
2274 rccal_ovrd = true;
2275 }
2276 }
2277 if (rccal_ovrd) {
2278 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2279 (scap_val_11b << 3) |
2280 lpf_11b;
2281 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2282 (scap_val_11n_20 << 3) |
2283 lpf_20;
2284 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2285 (scap_val_11n_40 << 3) |
2286 lpf_40;
2287 for (core = 0; core < 2; core++) {
2288 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2289 rx2tx_lut_20_11b);
2290 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2291 rx2tx_lut_20_11n);
2292 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2293 rx2tx_lut_20_11n);
2294 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2295 rx2tx_lut_40_11n);
2296 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2297 rx2tx_lut_40_11n);
2298 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2299 rx2tx_lut_40_11n);
2300 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2301 rx2tx_lut_40_11n);
2302 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2303 rx2tx_lut_40_11n);
2304 }
c071b9f6 2305 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2306 }
2307 b43_phy_write(dev, 0x32F, 0x3);
2308 if (phy->radio_rev == 4 || phy->radio_rev == 6)
c071b9f6 2309 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2310
2311 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2312 if (sprom->revision &&
2313 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2314 b43_radio_write(dev, 0x5, 0x05);
2315 b43_radio_write(dev, 0x6, 0x30);
2316 b43_radio_write(dev, 0x7, 0x00);
2317 b43_radio_set(dev, 0x4f, 0x1);
2318 b43_radio_set(dev, 0xd4, 0x1);
2319 bias = 0x1f;
2320 conv = 0x6f;
2321 filt = 0xaa;
2322 } else {
2323 bias = 0x2b;
2324 conv = 0x7f;
2325 filt = 0xee;
2326 }
2327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2328 for (core = 0; core < 2; core++) {
2329 if (core == 0) {
2330 b43_radio_write(dev, 0x5F, bias);
2331 b43_radio_write(dev, 0x64, conv);
2332 b43_radio_write(dev, 0x66, filt);
2333 } else {
2334 b43_radio_write(dev, 0xE8, bias);
2335 b43_radio_write(dev, 0xE9, conv);
2336 b43_radio_write(dev, 0xEB, filt);
2337 }
2338 }
2339 }
2340 }
2341
2342 if (b43_nphy_ipa(dev)) {
2343 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2344 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2345 phy->radio_rev == 6) {
2346 for (core = 0; core < 2; core++) {
2347 if (core == 0)
2348 b43_radio_write(dev, 0x51,
2349 0x7f);
2350 else
2351 b43_radio_write(dev, 0xd6,
2352 0x7f);
2353 }
2354 }
2355 if (phy->radio_rev == 3) {
2356 for (core = 0; core < 2; core++) {
2357 if (core == 0) {
2358 b43_radio_write(dev, 0x64,
2359 0x13);
2360 b43_radio_write(dev, 0x5F,
2361 0x1F);
2362 b43_radio_write(dev, 0x66,
2363 0xEE);
2364 b43_radio_write(dev, 0x59,
2365 0x8A);
2366 b43_radio_write(dev, 0x80,
2367 0x3E);
2368 } else {
2369 b43_radio_write(dev, 0x69,
2370 0x13);
2371 b43_radio_write(dev, 0xE8,
2372 0x1F);
2373 b43_radio_write(dev, 0xEB,
2374 0xEE);
2375 b43_radio_write(dev, 0xDE,
2376 0x8A);
2377 b43_radio_write(dev, 0x105,
2378 0x3E);
2379 }
2380 }
2381 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2382 if (!phy->is_40mhz) {
2383 b43_radio_write(dev, 0x5F, 0x14);
2384 b43_radio_write(dev, 0xE8, 0x12);
2385 } else {
2386 b43_radio_write(dev, 0x5F, 0x16);
2387 b43_radio_write(dev, 0xE8, 0x16);
2388 }
2389 }
2390 } else {
2391 u16 freq = phy->channel_freq;
2392 if ((freq >= 5180 && freq <= 5230) ||
2393 (freq >= 5745 && freq <= 5805)) {
2394 b43_radio_write(dev, 0x7D, 0xFF);
2395 b43_radio_write(dev, 0xFE, 0xFF);
2396 }
2397 }
2398 } else {
2399 if (phy->radio_rev != 5) {
2400 for (core = 0; core < 2; core++) {
2401 if (core == 0) {
2402 b43_radio_write(dev, 0x5c, 0x61);
2403 b43_radio_write(dev, 0x51, 0x70);
2404 } else {
2405 b43_radio_write(dev, 0xe1, 0x61);
2406 b43_radio_write(dev, 0xd6, 0x70);
2407 }
2408 }
2409 }
2410 }
2411
2412 if (phy->radio_rev == 4) {
2413 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2414 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2415 for (core = 0; core < 2; core++) {
2416 if (core == 0) {
2417 b43_radio_write(dev, 0x1a1, 0x00);
2418 b43_radio_write(dev, 0x1a2, 0x3f);
2419 b43_radio_write(dev, 0x1a6, 0x3f);
2420 } else {
2421 b43_radio_write(dev, 0x1a7, 0x00);
2422 b43_radio_write(dev, 0x1ab, 0x3f);
2423 b43_radio_write(dev, 0x1ac, 0x3f);
2424 }
2425 }
2426 } else {
2427 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2428 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2429 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2430 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2431
2432 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2433 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2434 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2435 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2436 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2437 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2438
2439 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2440 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2441 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2442 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2443 }
2444
2445 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2446
2447 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2448 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2449 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2450 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2451 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2452 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2453 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2454
2455 if (!phy->is_40mhz) {
2456 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2457 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2458 } else {
2459 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2460 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2461 }
2462
2463 b43_nphy_gain_ctl_workarounds(dev);
2464
2465 /* TODO
2466 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2467 aux_adc_vmid_rev7_core0);
2468 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2469 aux_adc_vmid_rev7_core1);
2470 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2471 aux_adc_gain_rev7);
2472 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2473 aux_adc_gain_rev7);
2474 */
2475}
2476
73d07a39 2477static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2478{
0eff8fcd 2479 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2480 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2481
0eff8fcd 2482 /* TX to RX */
c56da252
RM		 2483 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2484 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
0eff8fcd
RM		 2485 /* RX to TX */
2486 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2487 0x1F };
2488 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2489 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2490 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2491
ba9a6214
RM		 2492 u16 tmp16;
2493 u32 tmp32;
2494
04519dc6
RM		 2495 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2496 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2497
73d07a39
RM		 2498 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2499 tmp32 &= 0xffffff;
2500 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2501
73d07a39
RM		 2502 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2503 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2504 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2505 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2506 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2507 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2508
04519dc6
RM		 2509 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2510 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2511
0eff8fcd 2512 /* TX to RX */
c56da252
RM		 2513 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2514 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2515
2516 /* RX to TX */
2517 if (b43_nphy_ipa(dev))
c56da252
RM		 2518 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2519 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2520 if (nphy->hw_phyrxchain != 3 &&
2521 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2522 if (b43_nphy_ipa(dev)) {
2523 rx2tx_delays[5] = 59;
2524 rx2tx_delays[6] = 1;
2525 rx2tx_events[7] = 0x1F;
2526 }
fa0f2b38 2527 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2528 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2529 }
ba9a6214 2530
73d07a39
RM		 2531 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2532 0x2 : 0x9C40;
2533 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2534
04519dc6 2535 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2536
fa0f2b38
RM		 2537 if (!dev->phy.is_40mhz) {
2538 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2539 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2540 } else {
2541 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2542 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2543 }
ba9a6214 2544
3ccd0957 2545 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2546
c56da252
RM		 2547 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2548 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2549
73d07a39 2550 /* TODO */
ba9a6214 2551
73d07a39
RM		 2552 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2553 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2554 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2555 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2556 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2557 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2558 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2559 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2560 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2561 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2562 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2563 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2564
2565 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2566
2567 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2568 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2569 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2570 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2571 tmp32 = 0x00088888;
2572 else
2573 tmp32 = 0x88888888;
2574 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2575 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2576 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2577
2578 if (dev->phy.rev == 4 &&
fa0f2b38 2579 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2580 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2581 0x70);
2582 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2583 0x70);
2584 }
ba9a6214 2585
fa0f2b38 2586 /* Dropped probably-always-true condition */
04519dc6
RM		 2587 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2588 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2589 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2590 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2591 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2592 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2593 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2594 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2595 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2596 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2597 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2598 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2599
2600 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2601 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2602}
ba9a6214 2603
73d07a39
RM		 2604static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2605{
2606 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2607 struct b43_phy *phy = &dev->phy;
2608 struct b43_phy_n *nphy = phy->n;
ba9a6214 2609
73d07a39
RM		 2610 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2611 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2612
73d07a39
RM		 2613 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2614 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2615
fa0f2b38 2616 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2617 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2618 delays1[0] = 0x1;
2619 delays1[5] = 0x14;
2620 }
2621
73d07a39
RM		 2622 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2623 nphy->band5g_pwrgain) {
2624 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2625 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2626 } else {
73d07a39
RM		 2627 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2628 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2629 }
28fd7daa 2630
73d07a39
RM		 2631 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2632 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2633 if (dev->phy.rev < 3) {
2634 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2635 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2636 }
73d07a39
RM		 2637
2638 if (dev->phy.rev < 2) {
2639 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2640 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2641 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2642 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2643 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2644 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2645 }
28fd7daa 2646
73d07a39
RM		 2647 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2648 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2649 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2650 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2651
73d07a39
RM		 2652 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2653 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2654
3ccd0957 2655 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2656
2657 if (dev->phy.rev < 2) {
2658 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2659 b43_hf_write(dev, b43_hf_read(dev) |
2660 B43_HF_MLADVW);
2661 } else if (dev->phy.rev == 2) {
2662 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2663 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2664 }
28fd7daa 2665
73d07a39
RM		 2666 if (dev->phy.rev < 2)
2667 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2668 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2669
2670 /* Set phase track alpha and beta */
2671 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2672 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2673 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2674 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2675 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2676 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2677
fa0f2b38
RM		 2678 if (dev->phy.rev < 3) {
2679 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2680 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2681 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2682 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2683 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2684 }
73d07a39
RM		 2685
2686 if (dev->phy.rev == 2)
2687 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2688 B43_NPHY_FINERX2_CGC_DECGC);
2689}
28fd7daa 2690
73d07a39
RM		 2691/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2692static void b43_nphy_workarounds(struct b43_wldev *dev)
2693{
2694 struct b43_phy *phy = &dev->phy;
2695 struct b43_phy_n *nphy = phy->n;
28fd7daa 2696
73d07a39
RM		 2697 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2698 b43_nphy_classifier(dev, 1, 0);
2699 else
2700 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2701
73d07a39
RM		 2702 if (nphy->hang_avoid)
2703 b43_nphy_stay_in_carrier_search(dev, 1);
2704
2705 b43_phy_set(dev, B43_NPHY_IQFLIP,
2706 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2707
d11d354b
RM		 2708 if (dev->phy.rev >= 7)
2709 b43_nphy_workarounds_rev7plus(dev);
2710 else if (dev->phy.rev >= 3)
73d07a39
RM		 2711 b43_nphy_workarounds_rev3plus(dev);
2712 else
2713 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2714
2715 if (nphy->hang_avoid)
2716 b43_nphy_stay_in_carrier_search(dev, 0);
2717}
2718
9dd4d9b9
RM		 2719/**************************************************
2720 * Tx/Rx common
2721 **************************************************/
2722
2723/*
2724 * Transmits a known value for LO calibration
2725 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2726 */
2727static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2728 bool iqmode, bool dac_test)
2729{
2730 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2731 if (samp == 0)
2732 return -1;
2733 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2734 return 0;
2735}
2736
2737/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2738static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2739{
2740 struct b43_phy_n *nphy = dev->phy.n;
2741
2742 bool override = false;
2743 u16 chain = 0x33;
2744
2745 if (nphy->txrx_chain == 0) {
2746 chain = 0x11;
2747 override = true;
2748 } else if (nphy->txrx_chain == 1) {
2749 chain = 0x22;
2750 override = true;
2751 }
2752
2753 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2754 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2755 chain);
2756
2757 if (override)
2758 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2759 B43_NPHY_RFSEQMODE_CAOVER);
2760 else
2761 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2762 ~B43_NPHY_RFSEQMODE_CAOVER);
2763}
2764
2765/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2766static void b43_nphy_stop_playback(struct b43_wldev *dev)
2767{
2768 struct b43_phy_n *nphy = dev->phy.n;
2769 u16 tmp;
2770
2771 if (nphy->hang_avoid)
2772 b43_nphy_stay_in_carrier_search(dev, 1);
2773
2774 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2775 if (tmp & 0x1)
2776 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2777 else if (tmp & 0x2)
2778 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2779
2780 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2781
2782 if (nphy->bb_mult_save & 0x80000000) {
2783 tmp = nphy->bb_mult_save & 0xFFFF;
2784 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2785 nphy->bb_mult_save = 0;
2786 }
2787
2788 if (nphy->hang_avoid)
2789 b43_nphy_stay_in_carrier_search(dev, 0);
2790}
2791
2792/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2793static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2794 struct nphy_txgains target,
2795 struct nphy_iqcal_params *params)
2796{
2797 int i, j, indx;
2798 u16 gain;
2799
2800 if (dev->phy.rev >= 3) {
2801 params->txgm = target.txgm[core];
2802 params->pga = target.pga[core];
2803 params->pad = target.pad[core];
2804 params->ipa = target.ipa[core];
2805 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2806 (params->pad << 4) | (params->ipa);
2807 for (j = 0; j < 5; j++)
2808 params->ncorr[j] = 0x79;
2809 } else {
2810 gain = (target.pad[core]) | (target.pga[core] << 4) |
2811 (target.txgm[core] << 8);
2812
2813 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2814 1 : 0;
2815 for (i = 0; i < 9; i++)
2816 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2817 break;
2818 i = min(i, 8);
2819
2820 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2821 params->pga = tbl_iqcal_gainparams[indx][i][2];
2822 params->pad = tbl_iqcal_gainparams[indx][i][3];
2823 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2824 (params->pad << 2);
2825 for (j = 0; j < 4; j++)
2826 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2827 }
2828}
2829
884a5228 2830/**************************************************
104cfa88 2831 * Tx and Rx
884a5228 2832 **************************************************/
5f6393ec 2833
884a5228
RM		 2834static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2835{//TODO
2836}
59af099b 2837
884a5228
RM		 2838static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2839 bool ignore_tssi)
2840{//TODO
2841 return B43_TXPWR_RES_DONE;
2842}
59af099b 2843
161d540c
RM		 2844/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2845static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2846{
2847 struct b43_phy_n *nphy = dev->phy.n;
2848 u8 i;
c9c0d9ec
RM		 2849 u16 bmask, val, tmp;
2850 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 2851
161d540c
RM		 2852 if (nphy->hang_avoid)
2853 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 2854
161d540c
RM		 2855 nphy->txpwrctrl = enable;
2856 if (!enable) {
c9c0d9ec
RM		 2857 if (dev->phy.rev >= 3 &&
2858 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2859 (B43_NPHY_TXPCTL_CMD_COEFF |
2860 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2861 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2862 /* We disable enabled TX pwr ctl, save it's state */
2863 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2864 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2865 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2866 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2867 }
59af099b 2868
161d540c
RM		 2869 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2870 for (i = 0; i < 84; i++)
2871 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2872
161d540c
RM		 2873 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2874 for (i = 0; i < 84; i++)
2875 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2876
161d540c
RM		 2877 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2878 if (dev->phy.rev >= 3)
2879 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2880 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 2881
161d540c
RM		 2882 if (dev->phy.rev >= 3) {
2883 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2884 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2885 } else {
2886 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2887 }
10a79873 2888
161d540c
RM		 2889 if (dev->phy.rev == 2)
2890 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2891 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2892 else if (dev->phy.rev < 2)
2893 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2894 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 2895
c9c0d9ec
RM		 2896 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2897 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 2898 } else {
c9c0d9ec
RM		 2899 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2900 nphy->adj_pwr_tbl);
2901 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2902 nphy->adj_pwr_tbl);
10a79873 2903
c9c0d9ec
RM		 2904 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2905 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2906 /* wl does useless check for "enable" param here */
2907 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2908 if (dev->phy.rev >= 3) {
2909 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2910 if (val)
2911 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2912 }
2913 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 2914
c9c0d9ec
RM		 2915 if (band == IEEE80211_BAND_5GHZ) {
2916 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2917 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2918 if (dev->phy.rev > 1)
2919 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2920 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2921 0x64);
2922 }
10a79873 2923
c9c0d9ec
RM		 2924 if (dev->phy.rev >= 3) {
2925 if (nphy->tx_pwr_idx[0] != 128 &&
2926 nphy->tx_pwr_idx[1] != 128) {
2927 /* Recover TX pwr ctl state */
2928 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2929 ~B43_NPHY_TXPCTL_CMD_INIT,
2930 nphy->tx_pwr_idx[0]);
2931 if (dev->phy.rev > 1)
2932 b43_phy_maskset(dev,
2933 B43_NPHY_TXPCTL_INIT,
2934 ~0xff, nphy->tx_pwr_idx[1]);
2935 }
2936 }
10a79873 2937
c9c0d9ec
RM		 2938 if (dev->phy.rev >= 3) {
2939 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2940 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2941 } else {
2942 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2943 }
10a79873 2944
c9c0d9ec
RM		 2945 if (dev->phy.rev == 2)
2946 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2947 else if (dev->phy.rev < 2)
2948 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 2949
c9c0d9ec
RM		 2950 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2951 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 2952
c002831a 2953 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 2954 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2955 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 2956 }
10a79873 2957 }
10a79873 2958
161d540c
RM		 2959 if (nphy->hang_avoid)
2960 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 2961}
2962
161d540c 2963/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 2964static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 2965{
2966 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2967 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 2968
161d540c
RM		 2969 u8 txpi[2], bbmult, i;
2970 u16 tmp, radio_gain, dac_gain;
2971 u16 freq = dev->phy.channel_freq;
2972 u32 txgain;
2973 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 2974
2975 if (nphy->hang_avoid)
161d540c 2976 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 2977
dd5f13b8
RM		 2978 if (dev->phy.rev >= 7) {
2979 txpi[0] = txpi[1] = 30;
2980 } else if (dev->phy.rev >= 3) {
161d540c
RM		 2981 txpi[0] = 40;
2982 txpi[1] = 40;
2983 } else if (sprom->revision < 4) {
2984 txpi[0] = 72;
2985 txpi[1] = 72;
2986 } else {
2987 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2988 txpi[0] = sprom->txpid2g[0];
2989 txpi[1] = sprom->txpid2g[1];
2990 } else if (freq >= 4900 && freq < 5100) {
2991 txpi[0] = sprom->txpid5gl[0];
2992 txpi[1] = sprom->txpid5gl[1];
2993 } else if (freq >= 5100 && freq < 5500) {
2994 txpi[0] = sprom->txpid5g[0];
2995 txpi[1] = sprom->txpid5g[1];
2996 } else if (freq >= 5500) {
2997 txpi[0] = sprom->txpid5gh[0];
2998 txpi[1] = sprom->txpid5gh[1];
2999 } else {
3000 txpi[0] = 91;
3001 txpi[1] = 91;
6dcd9d91
RM		 3002 }
3003 }
dd5f13b8 3004 if (dev->phy.rev < 7 &&
9bd28571 3005 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3006 txpi[0] = txpi[1] = 91;
6dcd9d91 3007
161d540c
RM		 3008 /*
3009 for (i = 0; i < 2; i++) {
3010 nphy->txpwrindex[i].index_internal = txpi[i];
3011 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3012 }
161d540c 3013 */
75377b24 3014
161d540c 3015 for (i = 0; i < 2; i++) {
aeab5751
RM		 3016 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3017
3018 if (dev->phy.rev >= 3)
161d540c 3019 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3020 else
161d540c 3021 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3022
dd5f13b8
RM		 3023 if (dev->phy.rev >= 7)
3024 dac_gain = (txgain >> 8) & 0x7;
3025 else
3026 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3027 bbmult = txgain & 0xFF;
75377b24 3028
161d540c
RM		 3029 if (dev->phy.rev >= 3) {
3030 if (i == 0)
3031 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3032 else
3033 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3034 } else {
3035 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3036 }
75377b24 3037
161d540c
RM		 3038 if (i == 0)
3039 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3040 else
3041 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3042
44f4008b 3043 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3044
44f4008b 3045 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3046 if (i == 0)
3047 tmp = (tmp & 0x00FF) | (bbmult << 8);
3048 else
3049 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3050 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3051
0eff8fcd
RM		 3052 if (b43_nphy_ipa(dev)) {
3053 u32 tmp32;
3054 u16 reg = (i == 0) ?
3055 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3056 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3057 576 + txpi[i]));
0eff8fcd
RM		 3058 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3059 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3060 }
3061 }
75377b24 3062
161d540c 3063 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3064
161d540c
RM		 3065 if (nphy->hang_avoid)
3066 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3067}
67cbc3ed 3068
3dda07b6
RM		 3069static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3070{
3071 struct b43_phy *phy = &dev->phy;
3072
3073 u8 core;
3074 u16 r; /* routing */
3075
3076 if (phy->rev >= 7) {
3077 for (core = 0; core < 2; core++) {
3078 r = core ? 0x190 : 0x170;
3079 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3080 b43_radio_write(dev, r + 0x5, 0x5);
3081 b43_radio_write(dev, r + 0x9, 0xE);
3082 if (phy->rev != 5)
3083 b43_radio_write(dev, r + 0xA, 0);
3084 if (phy->rev != 7)
3085 b43_radio_write(dev, r + 0xB, 1);
3086 else
3087 b43_radio_write(dev, r + 0xB, 0x31);
3088 } else {
3089 b43_radio_write(dev, r + 0x5, 0x9);
3090 b43_radio_write(dev, r + 0x9, 0xC);
3091 b43_radio_write(dev, r + 0xB, 0x0);
3092 if (phy->rev != 5)
3093 b43_radio_write(dev, r + 0xA, 1);
3094 else
3095 b43_radio_write(dev, r + 0xA, 0x31);
3096 }
3097 b43_radio_write(dev, r + 0x6, 0);
3098 b43_radio_write(dev, r + 0x7, 0);
3099 b43_radio_write(dev, r + 0x8, 3);
3100 b43_radio_write(dev, r + 0xC, 0);
3101 }
3102 } else {
3103 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3104 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3105 else
3106 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3107 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3108 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3109
3110 for (core = 0; core < 2; core++) {
3111 r = core ? B2056_TX1 : B2056_TX0;
3112
3113 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3114 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3115 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3116 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3117 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3118 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3119 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3120 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3121 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3122 0x5);
3123 if (phy->rev != 5)
3124 b43_radio_write(dev, r | B2056_TX_TSSIA,
3125 0x00);
3126 if (phy->rev >= 5)
3127 b43_radio_write(dev, r | B2056_TX_TSSIG,
3128 0x31);
3129 else
3130 b43_radio_write(dev, r | B2056_TX_TSSIG,
3131 0x11);
3132 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3133 0xE);
3134 } else {
3135 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3136 0x9);
3137 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3138 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3139 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3140 0xC);
3141 }
3142 }
3143 }
3144}
3145
3146/*
3147 * Stop radio and transmit known signal. Then check received signal strength to
3148 * get TSSI (Transmit Signal Strength Indicator).
3149 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3150 */
3151static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3152{
3153 struct b43_phy *phy = &dev->phy;
3154 struct b43_phy_n *nphy = dev->phy.n;
3155
3156 u32 tmp;
3157 s32 rssi[4] = { };
3158
3159 /* TODO: check if we can transmit */
3160
3161 if (b43_nphy_ipa(dev))
3162 b43_nphy_ipa_internal_tssi_setup(dev);
3163
3164 if (phy->rev >= 7)
c071b9f6 3165 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6
RM		 3166 else if (phy->rev >= 3)
3167 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3168
3169 b43_nphy_stop_playback(dev);
3170 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3171 udelay(20);
a3764ef7 3172 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3173 b43_nphy_stop_playback(dev);
a3764ef7 3174 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3175
3176 if (phy->rev >= 7)
c071b9f6 3177 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6
RM		 3178 else if (phy->rev >= 3)
3179 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3180
3181 if (phy->rev >= 3) {
3182 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3183 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3184 } else {
3185 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3186 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3187 }
3188 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3189 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3190}
3191
d3fd8bf7
RM		 3192/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3193static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3194{
3195 struct b43_phy_n *nphy = dev->phy.n;
3196
3197 u8 idx, delta;
3198 u8 i, stf_mode;
3199
3200 for (i = 0; i < 4; i++)
3201 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3202
3203 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3204 delta = 0;
3205 switch (stf_mode) {
3206 case 0:
3207 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3208 idx = 68;
3209 } else {
3210 delta = 1;
3211 idx = dev->phy.is_40mhz ? 52 : 4;
3212 }
3213 break;
3214 case 1:
3215 idx = dev->phy.is_40mhz ? 76 : 28;
3216 break;
3217 case 2:
3218 idx = dev->phy.is_40mhz ? 84 : 36;
3219 break;
3220 case 3:
3221 idx = dev->phy.is_40mhz ? 92 : 44;
3222 break;
3223 }
3224
3225 for (i = 0; i < 20; i++) {
3226 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3227 nphy->tx_power_offset[idx];
3228 if (i == 0)
3229 idx += delta;
3230 if (i == 14)
3231 idx += 1 - delta;
3232 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3233 i == 13)
3234 idx += 1;
3235 }
3236 }
3237}
3238
3239/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3240static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3241{
3242 struct b43_phy_n *nphy = dev->phy.n;
3243 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3244
3245 s16 a1[2], b0[2], b1[2];
3246 u8 idle[2];
3247 s8 target[2];
3248 s32 num, den, pwr;
3249 u32 regval[64];
3250
3251 u16 freq = dev->phy.channel_freq;
3252 u16 tmp;
3253 u16 r; /* routing */
3254 u8 i, c;
3255
3256 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3257 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3258 b43_read32(dev, B43_MMIO_MACCTL);
3259 udelay(1);
3260 }
3261
3262 if (nphy->hang_avoid)
3263 b43_nphy_stay_in_carrier_search(dev, true);
3264
3265 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3266 if (dev->phy.rev >= 3)
3267 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3268 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3269 else
3270 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3271 B43_NPHY_TXPCTL_CMD_PCTLEN);
3272
3273 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3274 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3275
3276 if (sprom->revision < 4) {
3277 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3278 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3279 target[0] = target[1] = 52;
3280 a1[0] = a1[1] = -424;
3281 b0[0] = b0[1] = 5612;
3282 b1[0] = b1[1] = -1393;
3283 } else {
3284 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3285 for (c = 0; c < 2; c++) {
3286 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3287 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3288 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3289 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3290 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3291 }
3292 } else if (freq >= 4900 && freq < 5100) {
3293 for (c = 0; c < 2; c++) {
3294 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3295 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3296 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3297 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3298 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3299 }
3300 } else if (freq >= 5100 && freq < 5500) {
3301 for (c = 0; c < 2; c++) {
3302 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3303 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3304 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3305 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3306 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3307 }
3308 } else if (freq >= 5500) {
3309 for (c = 0; c < 2; c++) {
3310 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3311 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3312 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3313 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3314 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3315 }
3316 } else {
3317 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3318 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3319 target[0] = target[1] = 52;
3320 a1[0] = a1[1] = -424;
3321 b0[0] = b0[1] = 5612;
3322 b1[0] = b1[1] = -1393;
3323 }
3324 }
3325 /* target[0] = target[1] = nphy->tx_power_max; */
3326
3327 if (dev->phy.rev >= 3) {
3328 if (sprom->fem.ghz2.tssipos)
3329 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3330 if (dev->phy.rev >= 7) {
3331 for (c = 0; c < 2; c++) {
3332 r = c ? 0x190 : 0x170;
3333 if (b43_nphy_ipa(dev))
3334 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3335 }
3336 } else {
3337 if (b43_nphy_ipa(dev)) {
3338 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3339 b43_radio_write(dev,
3340 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3341 b43_radio_write(dev,
3342 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3343 } else {
3344 b43_radio_write(dev,
3345 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3346 b43_radio_write(dev,
3347 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3348 }
3349 }
3350 }
3351
3352 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3353 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3354 b43_read32(dev, B43_MMIO_MACCTL);
3355 udelay(1);
3356 }
3357
3358 if (dev->phy.rev >= 7) {
3359 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3360 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3361 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3362 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3363 } else {
3364 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3365 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3366 if (dev->phy.rev > 1)
3367 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3368 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3369 }
3370
3371 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3372 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3373
3374 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3375 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3376 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3377 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3378 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3379 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3380 B43_NPHY_TXPCTL_ITSSI_BINF);
3381 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3382 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3383 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3384
3385 for (c = 0; c < 2; c++) {
3386 for (i = 0; i < 64; i++) {
3387 num = 8 * (16 * b0[c] + b1[c] * i);
3388 den = 32768 + a1[c] * i;
3389 pwr = max((4 * num + den / 2) / den, -8);
3390 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3391 pwr = max(pwr, target[c] + 1);
3392 regval[i] = pwr;
3393 }
3394 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3395 }
3396
3397 b43_nphy_tx_prepare_adjusted_power_table(dev);
3398 /*
3399 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3400 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3401 */
3402
3403 if (nphy->hang_avoid)
3404 b43_nphy_stay_in_carrier_search(dev, false);
3405}
3406
0eff8fcd
RM		 3407static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3408{
3409 struct b43_phy *phy = &dev->phy;
67cbc3ed 3410
0eff8fcd 3411 const u32 *table = NULL;
0eff8fcd
RM		 3412 u32 rfpwr_offset;
3413 u8 pga_gain;
3414 int i;
0eff8fcd 3415
aeab5751 3416 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3417 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3418 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3419
3420 if (phy->rev >= 3) {
3421#if 0
3422 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3423#endif
0eff8fcd
RM		 3424
3425 for (i = 0; i < 128; i++) {
3426 pga_gain = (table[i] >> 24) & 0xF;
3427 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3428 rfpwr_offset =
3429 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3430 else
34c5cf20
RM		 3431 rfpwr_offset =
3432 0; /* FIXME */
0eff8fcd
RM		 3433 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3434 rfpwr_offset);
3435 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3436 rfpwr_offset);
3437 }
67cbc3ed
RM		 3438 }
3439}
3440
e50cbcf6
RM		 3441/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3442static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3443{
e50cbcf6
RM		 3444 struct b43_phy_n *nphy = dev->phy.n;
3445 enum ieee80211_band band;
3446 u16 tmp;
95b66bad 3447
e50cbcf6
RM		 3448 if (!enable) {
3449 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3450 B43_NPHY_RFCTL_INTC1);
3451 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3452 B43_NPHY_RFCTL_INTC2);
3453 band = b43_current_band(dev->wl);
3454 if (dev->phy.rev >= 3) {
3455 if (band == IEEE80211_BAND_5GHZ)
3456 tmp = 0x600;
3457 else
3458 tmp = 0x480;
3459 } else {
3460 if (band == IEEE80211_BAND_5GHZ)
3461 tmp = 0x180;
3462 else
3463 tmp = 0x120;
3464 }
3465 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3466 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3467 } else {
3468 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3469 nphy->rfctrl_intc1_save);
3470 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3471 nphy->rfctrl_intc2_save);
95b66bad 3472 }
95b66bad
MB		 3473}
3474
fe3e46e8
RM		 3475/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3476static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3477{
3478 u16 tmp;
3c95627d 3479
fe3e46e8 3480 if (dev->phy.rev >= 3) {
c002831a 3481 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3482 tmp = 4;
3483 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3484 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3485 }
76b002bd 3486
fe3e46e8
RM		 3487 tmp = 1;
3488 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3489 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3490 }
3491}
76b002bd 3492
2faa6b83
RM		 3493/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3494static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3495 u16 samps, u8 time, bool wait)
3c95627d 3496{
2faa6b83
RM		 3497 int i;
3498 u16 tmp;
3c95627d 3499
2faa6b83
RM		 3500 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3501 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3502 if (wait)
3503 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3504 else
2faa6b83 3505 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3506
2faa6b83 3507 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3508
2faa6b83
RM		 3509 for (i = 1000; i; i--) {
3510 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3511 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3512 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3513 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3514 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3515 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3516 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3517 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3518
2faa6b83
RM		 3519 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3520 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3521 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3522 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3523 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3524 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3525 return;
3c95627d 3526 }
2faa6b83 3527 udelay(10);
3c95627d 3528 }
2faa6b83 3529 memset(est, 0, sizeof(*est));
3c95627d
RM		 3530}
3531
a67162ab
RM		 3532/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3533static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3534 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3535{
a67162ab
RM		 3536 if (write) {
3537 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3538 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3539 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3540 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3541 } else {
a67162ab
RM		 3542 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3543 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3544 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3545 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3546 }
3547}
6e3b15a9 3548
c7455cf9
RM		 3549#if 0
3550/* Ready but not used anywhere */
026816fc
RM		 3551/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3552static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3553{
3554 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3555
026816fc
RM		 3556 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3557 if (core == 0) {
3558 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3559 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3560 } else {
3561 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3562 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3563 }
3564 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3565 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3566 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3567 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3568 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3569 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3570 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3571 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3572}
6e3b15a9 3573
026816fc
RM		 3574/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3575static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3576{
3577 u8 rxval, txval;
3578 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3579
026816fc
RM		 3580 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3581 if (core == 0) {
3582 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3583 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3584 } else {
3585 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3586 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3587 }
3588 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3589 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3590 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3591 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3592 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3593 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3594 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3595 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3596
026816fc
RM		 3597 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3598 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3599
acd82aa8
LF		 3600 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3601 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3602 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3603 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3604 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3605 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3606 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3607 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3608 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3609
026816fc
RM		 3610 if (core == 0) {
3611 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3612 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3613 } else {
3614 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3615 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3616 }
6e3b15a9 3617
67cbc3ed
RM		 3618 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3619 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 3620 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3621
026816fc
RM		 3622 if (core == 0) {
3623 rxval = 1;
3624 txval = 8;
3625 } else {
3626 rxval = 4;
3627 txval = 2;
6e3b15a9 3628 }
67cbc3ed
RM		 3629 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3630 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
99b82c41 3631}
c7455cf9 3632#endif
99b82c41 3633
34a56f2c
RM		 3634/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3635static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3636{
3637 int i;
34a56f2c
RM		 3638 s32 iq;
3639 u32 ii;
3640 u32 qq;
3641 int iq_nbits, qq_nbits;
3642 int arsh, brsh;
3643 u16 tmp, a, b;
3644
3645 struct nphy_iq_est est;
3646 struct b43_phy_n_iq_comp old;
3647 struct b43_phy_n_iq_comp new = { };
3648 bool error = false;
3649
3650 if (mask == 0)
3651 return;
3652
3653 b43_nphy_rx_iq_coeffs(dev, false, &old);
3654 b43_nphy_rx_iq_coeffs(dev, true, &new);
3655 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3656 new = old;
3657
dfb4aa5d 3658 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3659 if (i == 0 && (mask & 1)) {
3660 iq = est.iq0_prod;
3661 ii = est.i0_pwr;
3662 qq = est.q0_pwr;
3663 } else if (i == 1 && (mask & 2)) {
3664 iq = est.iq1_prod;
3665 ii = est.i1_pwr;
3666 qq = est.q1_pwr;
dfb4aa5d 3667 } else {
34a56f2c 3668 continue;
dfb4aa5d 3669 }
dfb4aa5d 3670
34a56f2c
RM		 3671 if (ii + qq < 2) {
3672 error = true;
3673 break;
3674 }
dfb4aa5d 3675
34a56f2c
RM		 3676 iq_nbits = fls(abs(iq));
3677 qq_nbits = fls(qq);
dfb4aa5d 3678
34a56f2c
RM		 3679 arsh = iq_nbits - 20;
3680 if (arsh >= 0) {
3681 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3682 tmp = ii >> arsh;
3683 } else {
3684 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3685 tmp = ii << -arsh;
3686 }
3687 if (tmp == 0) {
3688 error = true;
3689 break;
3690 }
3691 a /= tmp;
dfb4aa5d 3692
34a56f2c
RM		 3693 brsh = qq_nbits - 11;
3694 if (brsh >= 0) {
3695 b = (qq << (31 - qq_nbits));
3696 tmp = ii >> brsh;
dfb4aa5d 3697 } else {
34a56f2c
RM		 3698 b = (qq << (31 - qq_nbits));
3699 tmp = ii << -brsh;
3700 }
3701 if (tmp == 0) {
3702 error = true;
3703 break;
dfb4aa5d 3704 }
34a56f2c 3705 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3706
34a56f2c
RM		 3707 if (i == 0 && (mask & 0x1)) {
3708 if (dev->phy.rev >= 3) {
3709 new.a0 = a & 0x3FF;
3710 new.b0 = b & 0x3FF;
3711 } else {
3712 new.a0 = b & 0x3FF;
3713 new.b0 = a & 0x3FF;
3714 }
3715 } else if (i == 1 && (mask & 0x2)) {
3716 if (dev->phy.rev >= 3) {
3717 new.a1 = a & 0x3FF;
3718 new.b1 = b & 0x3FF;
3719 } else {
3720 new.a1 = b & 0x3FF;
3721 new.b1 = a & 0x3FF;
3722 }
3723 }
dfb4aa5d 3724 }
dfb4aa5d 3725
34a56f2c
RM		 3726 if (error)
3727 new = old;
dfb4aa5d 3728
34a56f2c
RM		 3729 b43_nphy_rx_iq_coeffs(dev, true, &new);
3730}
dfb4aa5d 3731
09146400
RM		 3732/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3733static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3734{
3735 u16 array[4];
44f4008b 3736 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3737
3738 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3739 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3740 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3741 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3742}
3743
9442e5b5
RM		 3744/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3745static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3746{
3747 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3748
204a665b 3749 u8 channel = dev->phy.channel;
9442e5b5
RM		 3750 int tone[2] = { 57, 58 };
3751 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3752
9442e5b5 3753 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3754
9442e5b5
RM		 3755 if (nphy->hang_avoid)
3756 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3757
9442e5b5
RM		 3758 if (nphy->gband_spurwar_en) {
3759 /* TODO: N PHY Adjust Analog Pfbw (7) */
3760 if (channel == 11 && dev->phy.is_40mhz)
3761 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3762 else
3763 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3764 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 3765 }
3766
9442e5b5
RM		 3767 if (nphy->aband_spurwar_en) {
3768 if (channel == 54) {
3769 tone[0] = 0x20;
3770 noise[0] = 0x25F;
3771 } else if (channel == 38 || channel == 102 || channel == 118) {
3772 if (0 /* FIXME */) {
3773 tone[0] = 0x20;
3774 noise[0] = 0x21F;
3775 } else {
3776 tone[0] = 0;
3777 noise[0] = 0;
90b9738d 3778 }
9442e5b5
RM		 3779 } else if (channel == 134) {
3780 tone[0] = 0x20;
3781 noise[0] = 0x21F;
3782 } else if (channel == 151) {
3783 tone[0] = 0x10;
3784 noise[0] = 0x23F;
3785 } else if (channel == 153 || channel == 161) {
3786 tone[0] = 0x30;
3787 noise[0] = 0x23F;
3788 } else {
3789 tone[0] = 0;
3790 noise[0] = 0;
90b9738d 3791 }
90b9738d 3792
9442e5b5
RM		 3793 if (!tone[0] && !noise[0])
3794 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 3795 else
9442e5b5
RM		 3796 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3797 }
90b9738d 3798
9442e5b5
RM		 3799 if (nphy->hang_avoid)
3800 b43_nphy_stay_in_carrier_search(dev, 0);
3801}
90b9738d 3802
5ecab603
RM		 3803/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3804static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3805{
3806 struct b43_phy_n *nphy = dev->phy.n;
3807 int i, j;
3808 u32 tmp;
3809 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 3810
5ecab603 3811 u16 buffer[7];
90b9738d 3812
5ecab603
RM		 3813 if (nphy->hang_avoid)
3814 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 3815
5ecab603 3816 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 3817
5ecab603
RM		 3818 for (i = 0; i < 2; i++) {
3819 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3820 (buffer[i * 2 + 1] & 0x3FF);
3821 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3822 (((i + 26) << 10) | 320));
3823 for (j = 0; j < 128; j++) {
3824 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3825 ((tmp >> 16) & 0xFFFF));
3826 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3827 (tmp & 0xFFFF));
90b9738d 3828 }
90b9738d 3829 }
90b9738d 3830
5ecab603
RM		 3831 for (i = 0; i < 2; i++) {
3832 tmp = buffer[5 + i];
3833 real_part = (tmp >> 8) & 0xFF;
3834 imag_part = (tmp & 0xFF);
3835 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3836 (((i + 26) << 10) | 448));
90b9738d 3837
5ecab603
RM		 3838 if (dev->phy.rev >= 3) {
3839 cur_real = real_part;
3840 cur_imag = imag_part;
3841 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3842 }
4cb99775 3843
5ecab603
RM		 3844 for (j = 0; j < 128; j++) {
3845 if (dev->phy.rev < 3) {
3846 cur_real = (real_part * loscale[j] + 128) >> 8;
3847 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3848 tmp = ((cur_real & 0xFF) << 8) |
3849 (cur_imag & 0xFF);
3850 }
3851 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3852 ((tmp >> 16) & 0xFFFF));
3853 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3854 (tmp & 0xFFFF));
3855 }
90b9738d 3856 }
4cb99775 3857
4cb99775 3858 if (dev->phy.rev >= 3) {
5ecab603
RM		 3859 b43_shm_write16(dev, B43_SHM_SHARED,
3860 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3861 b43_shm_write16(dev, B43_SHM_SHARED,
3862 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 3863 }
90b9738d 3864
5ecab603
RM		 3865 if (nphy->hang_avoid)
3866 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 3867}
3868
42e1547e
RM		 3869/*
3870 * Restore RSSI Calibration
3871 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3872 */
3873static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3874{
3875 struct b43_phy_n *nphy = dev->phy.n;
3876
3877 u16 *rssical_radio_regs = NULL;
3878 u16 *rssical_phy_regs = NULL;
3879
3880 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3881 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 3882 return;
3883 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3884 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3885 } else {
204a665b 3886 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 3887 return;
3888 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3889 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3890 }
3891
3892 /* TODO use some definitions */
3893 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3894 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3895
3896 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3897 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3898 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3899 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3900
3901 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3902 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3903 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3904 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3905
3906 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3907 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3908 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3909 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3910}
3911
c4a92003
RM		 3912/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3913static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3914{
3915 struct b43_phy_n *nphy = dev->phy.n;
3916 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 3917 u16 tmp;
3918 u8 offset, i;
c4a92003
RM		 3919
3920 if (dev->phy.rev >= 3) {
52cb5e97
RM		 3921 for (i = 0; i < 2; i++) {
3922 tmp = (i == 0) ? 0x2000 : 0x3000;
3923 offset = i * 11;
3924
3925 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3926 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3927 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3928 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3929 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3930 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3931 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3932 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3933 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3934 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3935 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3936
3937 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3938 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3939 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3940 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3941 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3942 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3943 if (nphy->ipa5g_on) {
3944 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3945 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3946 } else {
3947 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3948 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3949 }
3950 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3951 } else {
3952 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3953 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3954 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3955 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3956 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3957 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3958 if (nphy->ipa2g_on) {
3959 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3960 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3961 (dev->phy.rev < 5) ? 0x11 : 0x01);
3962 } else {
3963 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3964 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3965 }
3966 }
3967 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3968 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3969 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3970 }
c4a92003
RM		 3971 } else {
3972 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3973 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3974
3975 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3976 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3977
3978 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3979 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3980
3981 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3982 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3983
3984 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3985 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3986
3987 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3988 B43_NPHY_BANDCTL_5GHZ)) {
3989 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3990 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3991 } else {
3992 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3993 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3994 }
3995
3996 if (dev->phy.rev < 2) {
3997 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3998 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3999 } else {
4000 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4001 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4002 }
4003 }
4004}
4005
de7ed0c6
RM		 4006/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4007static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4008{
4009 struct b43_phy_n *nphy = dev->phy.n;
4010 int i;
4011 u16 scale, entry;
4012
4013 u16 tmp = nphy->txcal_bbmult;
4014 if (core == 0)
4015 tmp >>= 8;
4016 tmp &= 0xff;
4017
4018 for (i = 0; i < 18; i++) {
4019 scale = (ladder_lo[i].percent * tmp) / 100;
4020 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4021 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4022
4023 scale = (ladder_iq[i].percent * tmp) / 100;
4024 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4025 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4026 }
4027}
4028
45ca697e
RM		 4029/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4030static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4031{
4032 int i;
4033 for (i = 0; i < 15; i++)
4034 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4035 tbl_tx_filter_coef_rev4[2][i]);
4036}
4037
4038/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4039static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4040{
4041 int i, j;
4042 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4043 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4044
4045 for (i = 0; i < 3; i++)
4046 for (j = 0; j < 15; j++)
4047 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4048 tbl_tx_filter_coef_rev4[i][j]);
4049
4050 if (dev->phy.is_40mhz) {
4051 for (j = 0; j < 15; j++)
4052 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4053 tbl_tx_filter_coef_rev4[3][j]);
4054 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4055 for (j = 0; j < 15; j++)
4056 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4057 tbl_tx_filter_coef_rev4[5][j]);
4058 }
4059
4060 if (dev->phy.channel == 14)
4061 for (j = 0; j < 15; j++)
4062 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4063 tbl_tx_filter_coef_rev4[6][j]);
4064}
4065
b0022e15
RM		 4066/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4067static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4068{
4069 struct b43_phy_n *nphy = dev->phy.n;
4070
4071 u16 curr_gain[2];
4072 struct nphy_txgains target;
4073 const u32 *table = NULL;
4074
161d540c 4075 if (!nphy->txpwrctrl) {
b0022e15
RM		 4076 int i;
4077
4078 if (nphy->hang_avoid)
4079 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4080 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4081 if (nphy->hang_avoid)
4082 b43_nphy_stay_in_carrier_search(dev, false);
4083
4084 for (i = 0; i < 2; ++i) {
4085 if (dev->phy.rev >= 3) {
4086 target.ipa[i] = curr_gain[i] & 0x000F;
4087 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4088 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4089 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4090 } else {
4091 target.ipa[i] = curr_gain[i] & 0x0003;
4092 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4093 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4094 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4095 }
4096 }
4097 } else {
4098 int i;
4099 u16 index[2];
4100 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4101 B43_NPHY_TXPCTL_STAT_BIDX) >>
4102 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4103 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4104 B43_NPHY_TXPCTL_STAT_BIDX) >>
4105 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4106
4107 for (i = 0; i < 2; ++i) {
aeab5751 4108 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4109 if (dev->phy.rev >= 3) {
b0022e15
RM		 4110 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4111 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4112 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4113 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4114 } else {
b0022e15
RM		 4115 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4116 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4117 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4118 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4119 }
4120 }
4121 }
4122
4123 return target;
4124}
4125
e53de674
RM		 4126/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4127static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4128{
4129 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4130
4131 if (dev->phy.rev >= 3) {
4132 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4133 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4134 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4135 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4136 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4137 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4138 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4139 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4140 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4141 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4142 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4143 b43_nphy_reset_cca(dev);
4144 } else {
4145 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4146 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4147 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4148 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4149 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4150 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4151 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4152 }
4153}
4154
4155/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4156static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4157{
4158 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4159 u16 tmp;
4160
4161 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4162 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4163 if (dev->phy.rev >= 3) {
4164 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4165 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4166
4167 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4168 regs[2] = tmp;
4169 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4170
4171 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4172 regs[3] = tmp;
4173 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4174
4175 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4176 b43_phy_mask(dev, B43_NPHY_BBCFG,
4177 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4178
c643a66e 4179 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4180 regs[5] = tmp;
d41a3552 4181 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4182
4183 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4184 regs[6] = tmp;
d41a3552 4185 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4186 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4187 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4188
67cbc3ed
RM		 4189 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4190 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4191 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 4192
4193 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4194 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4195 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4196 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4197 } else {
4198 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4199 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4200 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4201 regs[2] = tmp;
4202 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4203 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4204 regs[3] = tmp;
4205 tmp |= 0x2000;
d41a3552 4206 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4207 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4208 regs[4] = tmp;
4209 tmp |= 0x2000;
d41a3552 4210 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4211 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4212 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4213 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4214 tmp = 0x0180;
4215 else
4216 tmp = 0x0120;
4217 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4218 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4219 }
4220}
4221
bbc6dc12
RM		 4222/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4223static void b43_nphy_save_cal(struct b43_wldev *dev)
4224{
4225 struct b43_phy_n *nphy = dev->phy.n;
4226
4227 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4228 u16 *txcal_radio_regs = NULL;
902db91d 4229 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4230 u16 *table = NULL;
4231
4232 if (nphy->hang_avoid)
4233 b43_nphy_stay_in_carrier_search(dev, 1);
4234
4235 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4236 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4237 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4238 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4239 table = nphy->cal_cache.txcal_coeffs_2G;
4240 } else {
4241 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4242 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4243 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4244 table = nphy->cal_cache.txcal_coeffs_5G;
4245 }
4246
4247 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4248 /* TODO use some definitions */
4249 if (dev->phy.rev >= 3) {
4250 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4251 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4252 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4253 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4254 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4255 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4256 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4257 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4258 } else {
4259 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4260 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4261 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4262 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4263 }
204a665b
RM		 4264 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4265 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4266 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4267
4268 if (nphy->hang_avoid)
4269 b43_nphy_stay_in_carrier_search(dev, 0);
4270}
4271
2f258b74
RM		 4272/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4273static void b43_nphy_restore_cal(struct b43_wldev *dev)
4274{
4275 struct b43_phy_n *nphy = dev->phy.n;
4276
4277 u16 coef[4];
4278 u16 *loft = NULL;
4279 u16 *table = NULL;
4280
4281 int i;
4282 u16 *txcal_radio_regs = NULL;
4283 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4284
4285 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4286 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4287 return;
4288 table = nphy->cal_cache.txcal_coeffs_2G;
4289 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4290 } else {
204a665b 4291 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4292 return;
4293 table = nphy->cal_cache.txcal_coeffs_5G;
4294 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4295 }
4296
2581b143 4297 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4298
4299 for (i = 0; i < 4; i++) {
4300 if (dev->phy.rev >= 3)
4301 table[i] = coef[i];
4302 else
4303 coef[i] = 0;
4304 }
4305
2581b143
RM		 4306 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4307 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4308 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4309
4310 if (dev->phy.rev < 2)
4311 b43_nphy_tx_iq_workaround(dev);
4312
4313 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4314 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4315 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4316 } else {
4317 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4318 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4319 }
4320
4321 /* TODO use some definitions */
4322 if (dev->phy.rev >= 3) {
4323 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4324 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4325 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4326 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4327 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4328 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4329 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4330 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4331 } else {
4332 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4333 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4334 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4335 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4336 }
4337 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4338}
4339
fb43b8e2
RM		 4340/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4341static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4342 struct nphy_txgains target,
4343 bool full, bool mphase)
4344{
4345 struct b43_phy_n *nphy = dev->phy.n;
4346 int i;
4347 int error = 0;
4348 int freq;
4349 bool avoid = false;
4350 u8 length;
fb23d863 4351 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4352 const u16 *table;
4353 bool phy6or5x;
4354
4355 u16 buffer[11];
4356 u16 diq_start = 0;
4357 u16 save[2];
4358 u16 gain[2];
4359 struct nphy_iqcal_params params[2];
4360 bool updated[2] = { };
4361
4362 b43_nphy_stay_in_carrier_search(dev, true);
4363
4364 if (dev->phy.rev >= 4) {
4365 avoid = nphy->hang_avoid;
3db1cd5c 4366 nphy->hang_avoid = false;
fb43b8e2
RM		 4367 }
4368
9145834e 4369 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4370
4371 for (i = 0; i < 2; i++) {
4372 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4373 gain[i] = params[i].cal_gain;
4374 }
2581b143
RM		 4375
4376 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4377
4378 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4379 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4380
4381 phy6or5x = dev->phy.rev >= 6 ||
4382 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4383 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4384 if (phy6or5x) {
38bb9029
RM		 4385 if (dev->phy.is_40mhz) {
4386 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4387 tbl_tx_iqlo_cal_loft_ladder_40);
4388 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4389 tbl_tx_iqlo_cal_iqimb_ladder_40);
4390 } else {
4391 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4392 tbl_tx_iqlo_cal_loft_ladder_20);
4393 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4394 tbl_tx_iqlo_cal_iqimb_ladder_20);
4395 }
fb43b8e2
RM		 4396 }
4397
4398 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4399
aa4c7b2a 4400 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4401 freq = 2500;
4402 else
4403 freq = 5000;
4404
4405 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4406 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4407 0xFFFF, 0, true, false);
fb43b8e2 4408 else
59af099b 4409 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4410
4411 if (error == 0) {
4412 if (nphy->mphase_cal_phase_id > 2) {
4413 table = nphy->mphase_txcal_bestcoeffs;
4414 length = 11;
4415 if (dev->phy.rev < 3)
4416 length -= 2;
4417 } else {
4418 if (!full && nphy->txiqlocal_coeffsvalid) {
4419 table = nphy->txiqlocal_bestc;
4420 length = 11;
4421 if (dev->phy.rev < 3)
4422 length -= 2;
4423 } else {
4424 full = true;
4425 if (dev->phy.rev >= 3) {
4426 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4427 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4428 } else {
4429 table = tbl_tx_iqlo_cal_startcoefs;
4430 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4431 }
4432 }
4433 }
4434
2581b143 4435 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4436
4437 if (full) {
4438 if (dev->phy.rev >= 3)
4439 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4440 else
4441 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4442 } else {
4443 if (dev->phy.rev >= 3)
4444 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4445 else
4446 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4447 }
4448
4449 if (mphase) {
4450 count = nphy->mphase_txcal_cmdidx;
4451 numb = min(max,
4452 (u16)(count + nphy->mphase_txcal_numcmds));
4453 } else {
4454 count = 0;
4455 numb = max;
4456 }
4457
4458 for (; count < numb; count++) {
4459 if (full) {
4460 if (dev->phy.rev >= 3)
4461 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4462 else
4463 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4464 } else {
4465 if (dev->phy.rev >= 3)
4466 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4467 else
4468 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4469 }
4470
4471 core = (cmd & 0x3000) >> 12;
4472 type = (cmd & 0x0F00) >> 8;
4473
4474 if (phy6or5x && updated[core] == 0) {
4475 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4476 updated[core] = true;
fb43b8e2
RM		 4477 }
4478
4479 tmp = (params[core].ncorr[type] << 8) | 0x66;
4480 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4481
4482 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4483 buffer[0] = b43_ntab_read(dev,
4484 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4485 diq_start = buffer[0];
4486 buffer[0] = 0;
d41a3552
RM		 4487 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4488 0);
fb43b8e2
RM		 4489 }
4490
4491 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4492 for (i = 0; i < 2000; i++) {
4493 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4494 if (tmp & 0xC000)
4495 break;
4496 udelay(10);
4497 }
4498
9145834e
RM		 4499 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4500 buffer);
2581b143
RM		 4501 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4502 buffer);
fb43b8e2
RM		 4503
4504 if (type == 1 || type == 3 || type == 4)
4505 buffer[0] = diq_start;
4506 }
4507
4508 if (mphase)
4509 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4510
4511 last = (dev->phy.rev < 3) ? 6 : 7;
4512
4513 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4514 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4515 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4516 if (dev->phy.rev < 3) {
4517 buffer[0] = 0;
4518 buffer[1] = 0;
4519 buffer[2] = 0;
4520 buffer[3] = 0;
4521 }
2581b143
RM		 4522 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4523 buffer);
bc53e512 4524 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4525 buffer);
4526 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4527 buffer);
4528 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4529 buffer);
fb43b8e2
RM		 4530 length = 11;
4531 if (dev->phy.rev < 3)
4532 length -= 2;
9145834e
RM		 4533 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4534 nphy->txiqlocal_bestc);
fb43b8e2 4535 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4536 nphy->txiqlocal_chanspec.center_freq =
4537 dev->phy.channel_freq;
4538 nphy->txiqlocal_chanspec.channel_type =
4539 dev->phy.channel_type;
fb43b8e2
RM		 4540 } else {
4541 length = 11;
4542 if (dev->phy.rev < 3)
4543 length -= 2;
9145834e
RM		 4544 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4545 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4546 }
4547
53ae8e8c 4548 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4549 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4550 }
4551
e53de674 4552 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4553 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4554
4555 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4556 b43_nphy_tx_iq_workaround(dev);
4557
4558 if (dev->phy.rev >= 4)
4559 nphy->hang_avoid = avoid;
4560
4561 b43_nphy_stay_in_carrier_search(dev, false);
4562
4563 return error;
4564}
4565
984ff4ff
RM		 4566/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4567static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4568{
4569 struct b43_phy_n *nphy = dev->phy.n;
4570 u8 i;
4571 u16 buffer[7];
4572 bool equal = true;
4573
902db91d 4574 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4575 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4576 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4577 return;
4578
4579 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4580 for (i = 0; i < 4; i++) {
4581 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4582 equal = false;
4583 break;
4584 }
4585 }
4586
4587 if (!equal) {
4588 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4589 nphy->txiqlocal_bestc);
4590 for (i = 0; i < 4; i++)
4591 buffer[i] = 0;
4592 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4593 buffer);
4594 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4595 &nphy->txiqlocal_bestc[5]);
4596 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4597 &nphy->txiqlocal_bestc[5]);
4598 }
4599}
4600
15931e31
RM		 4601/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4602static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4603 struct nphy_txgains target, u8 type, bool debug)
4604{
4605 struct b43_phy_n *nphy = dev->phy.n;
4606 int i, j, index;
4607 u8 rfctl[2];
4608 u8 afectl_core;
4609 u16 tmp[6];
c7455cf9 4610 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4611 u32 real, imag;
4612 enum ieee80211_band band;
4613
4614 u8 use;
4615 u16 cur_hpf;
4616 u16 lna[3] = { 3, 3, 1 };
4617 u16 hpf1[3] = { 7, 2, 0 };
4618 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4619 u32 power[3] = { };
15931e31
RM		 4620 u16 gain_save[2];
4621 u16 cal_gain[2];
4622 struct nphy_iqcal_params cal_params[2];
4623 struct nphy_iq_est est;
4624 int ret = 0;
4625 bool playtone = true;
4626 int desired = 13;
4627
4628 b43_nphy_stay_in_carrier_search(dev, 1);
4629
4630 if (dev->phy.rev < 2)
984ff4ff 4631 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4632 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4633 for (i = 0; i < 2; i++) {
4634 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4635 cal_gain[i] = cal_params[i].cal_gain;
4636 }
2581b143 4637 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4638
4639 for (i = 0; i < 2; i++) {
4640 if (i == 0) {
4641 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4642 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4643 afectl_core = B43_NPHY_AFECTL_C1;
4644 } else {
4645 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4646 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4647 afectl_core = B43_NPHY_AFECTL_C2;
4648 }
4649
4650 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4651 tmp[2] = b43_phy_read(dev, afectl_core);
4652 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4653 tmp[4] = b43_phy_read(dev, rfctl[0]);
4654 tmp[5] = b43_phy_read(dev, rfctl[1]);
4655
4656 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4657 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4658 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4659 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4660 (1 - i));
4661 b43_phy_set(dev, afectl_core, 0x0006);
4662 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4663
4664 band = b43_current_band(dev->wl);
4665
4666 if (nphy->rxcalparams & 0xFF000000) {
4667 if (band == IEEE80211_BAND_5GHZ)
4668 b43_phy_write(dev, rfctl[0], 0x140);
4669 else
4670 b43_phy_write(dev, rfctl[0], 0x110);
4671 } else {
4672 if (band == IEEE80211_BAND_5GHZ)
4673 b43_phy_write(dev, rfctl[0], 0x180);
4674 else
4675 b43_phy_write(dev, rfctl[0], 0x120);
4676 }
4677
4678 if (band == IEEE80211_BAND_5GHZ)
4679 b43_phy_write(dev, rfctl[1], 0x148);
4680 else
4681 b43_phy_write(dev, rfctl[1], 0x114);
4682
4683 if (nphy->rxcalparams & 0x10000) {
4684 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4685 (i + 1));
4686 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4687 (2 - i));
4688 }
4689
30115c22 4690 for (j = 0; j < 4; j++) {
15931e31
RM		 4691 if (j < 3) {
4692 cur_lna = lna[j];
4693 cur_hpf1 = hpf1[j];
4694 cur_hpf2 = hpf2[j];
4695 } else {
4696 if (power[1] > 10000) {
4697 use = 1;
4698 cur_hpf = cur_hpf1;
4699 index = 2;
4700 } else {
4701 if (power[0] > 10000) {
4702 use = 1;
4703 cur_hpf = cur_hpf1;
4704 index = 1;
4705 } else {
4706 index = 0;
4707 use = 2;
4708 cur_hpf = cur_hpf2;
4709 }
4710 }
4711 cur_lna = lna[index];
4712 cur_hpf1 = hpf1[index];
4713 cur_hpf2 = hpf2[index];
4714 cur_hpf += desired - hweight32(power[index]);
4715 cur_hpf = clamp_val(cur_hpf, 0, 10);
4716 if (use == 1)
4717 cur_hpf1 = cur_hpf;
4718 else
4719 cur_hpf2 = cur_hpf;
4720 }
4721
4722 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4723 (cur_lna << 2));
75377b24
RM		 4724 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4725 false);
de9a47f9 4726 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4727 b43_nphy_stop_playback(dev);
15931e31
RM		 4728
4729 if (playtone) {
59af099b
RM		 4730 ret = b43_nphy_tx_tone(dev, 4000,
4731 (nphy->rxcalparams & 0xFFFF),
4732 false, false);
15931e31
RM		 4733 playtone = false;
4734 } else {
10a79873
RM		 4735 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4736 false, false);
15931e31
RM		 4737 }
4738
4739 if (ret == 0) {
4740 if (j < 3) {
4741 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4742 false);
4743 if (i == 0) {
4744 real = est.i0_pwr;
4745 imag = est.q0_pwr;
4746 } else {
4747 real = est.i1_pwr;
4748 imag = est.q1_pwr;
4749 }
4750 power[i] = ((real + imag) / 1024) + 1;
4751 } else {
4752 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4753 }
53ae8e8c 4754 b43_nphy_stop_playback(dev);
15931e31
RM		 4755 }
4756
4757 if (ret != 0)
4758 break;
4759 }
4760
4761 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4762 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4763 b43_phy_write(dev, rfctl[1], tmp[5]);
4764 b43_phy_write(dev, rfctl[0], tmp[4]);
4765 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4766 b43_phy_write(dev, afectl_core, tmp[2]);
4767 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4768
4769 if (ret != 0)
4770 break;
4771 }
4772
75377b24 4773 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 4774 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 4775 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4776
4777 b43_nphy_stay_in_carrier_search(dev, 0);
4778
4779 return ret;
4780}
4781
4782static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4783 struct nphy_txgains target, u8 type, bool debug)
4784{
4785 return -1;
4786}
4787
4788/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4789static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4790 struct nphy_txgains target, u8 type, bool debug)
4791{
4792 if (dev->phy.rev >= 3)
4793 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4794 else
4795 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4796}
4797
4e687b22
GS		 4798/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4799static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4800{
4801 struct b43_phy *phy = &dev->phy;
4802 struct b43_phy_n *nphy = phy->n;
0b81c23d 4803 /* u16 buf[16]; it's rev3+ */
4e687b22 4804
049fbfee
RM		 4805 nphy->phyrxchain = mask;
4806
4e687b22
GS		 4807 if (0 /* FIXME clk */)
4808 return;
4809
4810 b43_mac_suspend(dev);
4811
4812 if (nphy->hang_avoid)
4813 b43_nphy_stay_in_carrier_search(dev, true);
4814
4815 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4816 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4817
049fbfee 4818 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 4819 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4820 if (dev->phy.rev >= 3) {
4821 /* TODO */
4822 }
4823 } else {
4824 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4825 if (dev->phy.rev >= 3) {
4826 /* TODO */
4827 }
4828 }
4829
4830 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4831
4832 if (nphy->hang_avoid)
4833 b43_nphy_stay_in_carrier_search(dev, false);
4834
4835 b43_mac_enable(dev);
4836}
4837
104cfa88
RM		 4838/**************************************************
4839 * N-PHY init
4840 **************************************************/
4841
0988a7a1 4842/*
104cfa88
RM		 4843 * Upload the N-PHY tables.
4844 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
0988a7a1 4845 */
104cfa88
RM		 4846static void b43_nphy_tables_init(struct b43_wldev *dev)
4847{
4848 if (dev->phy.rev < 3)
4849 b43_nphy_rev0_1_2_tables_init(dev);
4850 else
4851 b43_nphy_rev3plus_tables_init(dev);
4852}
4853
4854/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4855static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4856{
4857 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4858
4859 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4860 if (preamble == 1)
4861 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4862 else
4863 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4864
4865 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4866}
4867
4868/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4869static void b43_nphy_bphy_init(struct b43_wldev *dev)
4870{
4871 unsigned int i;
4872 u16 val;
4873
4874 val = 0x1E1F;
4875 for (i = 0; i < 16; i++) {
4876 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4877 val -= 0x202;
4878 }
4879 val = 0x3E3F;
4880 for (i = 0; i < 16; i++) {
4881 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4882 val -= 0x202;
4883 }
4884 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4885}
4886
4887/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4888static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4889{
4890 if (dev->phy.rev >= 3) {
4891 if (!init)
4892 return;
4893 if (0 /* FIXME */) {
4894 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4895 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4896 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4897 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4898 }
4899 } else {
4900 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4901 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4902
4903 switch (dev->dev->bus_type) {
4904#ifdef CONFIG_B43_BCMA
4905 case B43_BUS_BCMA:
4906 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4907 0xFC00, 0xFC00);
4908 break;
4909#endif
4910#ifdef CONFIG_B43_SSB
4911 case B43_BUS_SSB:
4912 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4913 0xFC00, 0xFC00);
4914 break;
4915#endif
4916 }
4917
5056635c
RM		 4918 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4919 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4920 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4921 0);
104cfa88
RM		 4922
4923 if (init) {
4924 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4925 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4926 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4927 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4928 }
4929 }
4930}
4931
4932/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 4933static int b43_phy_initn(struct b43_wldev *dev)
424047e6 4934{
0581483a 4935 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 4936 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 4937 struct b43_phy_n *nphy = phy->n;
4938 u8 tx_pwr_state;
4939 struct nphy_txgains target;
95b66bad 4940 u16 tmp;
0988a7a1
RM		 4941 enum ieee80211_band tmp2;
4942 bool do_rssi_cal;
4943
4944 u16 clip[2];
4945 bool do_cal = false;
95b66bad 4946
0988a7a1 4947 if ((dev->phy.rev >= 3) &&
0581483a 4948 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 4949 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 4950 switch (dev->dev->bus_type) {
42c9a458
RM		 4951#ifdef CONFIG_B43_BCMA
4952 case B43_BUS_BCMA:
4953 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4954 BCMA_CC_CHIPCTL, 0x40);
4955 break;
4956#endif
6cbab0d9
RM		 4957#ifdef CONFIG_B43_SSB
4958 case B43_BUS_SSB:
4959 chipco_set32(&dev->dev->sdev->bus->chipco,
4960 SSB_CHIPCO_CHIPCTL, 0x40);
4961 break;
4962#endif
4963 }
0988a7a1
RM		 4964 }
4965 nphy->deaf_count = 0;
95b66bad 4966 b43_nphy_tables_init(dev);
0988a7a1
RM		 4967 nphy->crsminpwr_adjusted = false;
4968 nphy->noisevars_adjusted = false;
95b66bad
MB		 4969
4970 /* Clear all overrides */
0988a7a1
RM		 4971 if (dev->phy.rev >= 3) {
4972 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4973 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4974 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4975 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4976 } else {
4977 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4978 }
95b66bad
MB		 4979 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4980 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 4981 if (dev->phy.rev < 6) {
4982 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4983 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4984 }
95b66bad
MB		 4985 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4986 ~(B43_NPHY_RFSEQMODE_CAOVER |
4987 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 4988 if (dev->phy.rev >= 3)
4989 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 4990 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4991
0988a7a1
RM		 4992 if (dev->phy.rev <= 2) {
4993 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4994 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4995 ~B43_NPHY_BPHY_CTL3_SCALE,
4996 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4997 }
95b66bad
MB		 4998 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4999 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5000
0eff8fcd 5001 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5002 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5003 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5004 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5005 else
5006 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5007 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5008 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5009 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5010
ad9716e8 5011 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5012 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5013
5014 if (phy->rev < 2) {
5015 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5016 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5017 }
0988a7a1
RM		 5018
5019 tmp2 = b43_current_band(dev->wl);
c002831a 5020 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5021 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5022 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5023 nphy->papd_epsilon_offset[0] << 7);
5024 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5025 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5026 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5027 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5028 } else if (phy->rev >= 5) {
45ca697e 5029 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5030 }
5031
95b66bad 5032 b43_nphy_workarounds(dev);
95b66bad 5033
0988a7a1 5034 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5035 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5036 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5037 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5038 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5039 b43_phy_force_clock(dev, 0);
0988a7a1 5040
858a1652 5041 b43_mac_phy_clock_set(dev, true);
0988a7a1 5042
e50cbcf6 5043 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5044 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5045 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5046 b43_nphy_pa_override(dev, true);
0988a7a1 5047
bbec398c
RM		 5048 b43_nphy_classifier(dev, 0, 0);
5049 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5050 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5051 b43_nphy_bphy_init(dev);
5052
0988a7a1 5053 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5054 b43_nphy_tx_power_ctrl(dev, false);
5055 b43_nphy_tx_power_fix(dev);
3dda07b6 5056 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5057 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5058 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5059
0988a7a1 5060 if (nphy->phyrxchain != 3)
4e687b22 5061 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5062 if (nphy->mphase_cal_phase_id > 0)
5063 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5064
5065 do_rssi_cal = false;
5066 if (phy->rev >= 3) {
5067 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5068 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5069 else
204a665b 5070 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5071
5072 if (do_rssi_cal)
4cb99775 5073 b43_nphy_rssi_cal(dev);
0988a7a1 5074 else
42e1547e 5075 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5076 } else {
4cb99775 5077 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5078 }
5079
5080 if (!((nphy->measure_hold & 0x6) != 0)) {
5081 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5082 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5083 else
204a665b 5084 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5085
5086 if (nphy->mute)
5087 do_cal = false;
5088
5089 if (do_cal) {
b0022e15 5090 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5091
5092 if (nphy->antsel_type == 2)
8987a9e9 5093 b43_nphy_superswitch_init(dev, true);
0988a7a1 5094 if (nphy->perical != 2) {
90b9738d 5095 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5096 if (phy->rev >= 3) {
5097 nphy->cal_orig_pwr_idx[0] =
5098 nphy->txpwrindex[0].index_internal;
5099 nphy->cal_orig_pwr_idx[1] =
5100 nphy->txpwrindex[1].index_internal;
5101 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5102 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5103 }
e7797bf2
RM		 5104 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5105 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5106 b43_nphy_save_cal(dev);
5107 } else if (nphy->mphase_cal_phase_id == 0)
5108 ;/* N PHY Periodic Calibration with arg 3 */
5109 } else {
5110 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5111 }
5112 }
5113
6dcd9d91 5114 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5115 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5116 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5117 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5118 if (phy->rev >= 3 && phy->rev <= 6)
5119 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 5120 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5121 if (phy->rev >= 3)
5122 b43_nphy_spur_workaround(dev);
95b66bad 5123
53a6e234 5124 return 0;
424047e6 5125}
ef1a628d 5126
104cfa88
RM		 5127/**************************************************
5128 * Channel switching ops.
5129 **************************************************/
5130
5131static void b43_chantab_phy_upload(struct b43_wldev *dev,
5132 const struct b43_phy_n_sfo_cfg *e)
5133{
5134 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5135 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5136 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5137 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5138 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5139 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5140}
5141
49d55cef
RM		 5142/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5143static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5144{
d66be829
RM		 5145 switch (dev->dev->bus_type) {
5146#ifdef CONFIG_B43_BCMA
5147 case B43_BUS_BCMA:
9b383672
HM		 5148 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5149 avoid);
d66be829 5150 break;
8b1fdb53 5151#endif
d66be829
RM		 5152#ifdef CONFIG_B43_SSB
5153 case B43_BUS_SSB:
5154 /* FIXME */
5155 break;
5156#endif
5157 }
49d55cef
RM		 5158}
5159
1b69ec7b 5160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5161static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5162 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5163 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5164{
5165 struct b43_phy *phy = &dev->phy;
5166 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5167 int ch = new_channel->hw_value;
1b69ec7b 5168
087de74a 5169 u16 old_band_5ghz;
1b69ec7b
RM		 5170 u32 tmp32;
5171
087de74a
RM		 5172 old_band_5ghz =
5173 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5174 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 5175 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5176 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5177 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5178 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5179 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5180 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 5181 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5182 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5183 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 5184 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 5185 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5186 }
5187
5188 b43_chantab_phy_upload(dev, e);
5189
a656b6a9 5190 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5191 b43_nphy_classifier(dev, 2, 0);
5192 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5193 } else {
5194 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5195 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5196 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5197 }
5198
161d540c 5199 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5200 b43_nphy_tx_power_fix(dev);
5201
5202 if (dev->phy.rev < 3)
5203 b43_nphy_adjust_lna_gain_table(dev);
5204
5205 b43_nphy_tx_lp_fbw(dev);
5206
49d55cef
RM		 5207 if (dev->phy.rev >= 3 &&
5208 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5209 bool avoid = false;
5210 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5211 avoid = true;
5212 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5213 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5214 avoid = true;
5215 } else { /* 40MHz */
5216 if (nphy->aband_spurwar_en &&
5217 (ch == 38 || ch == 102 || ch == 118))
5218 avoid = dev->dev->chip_id == 0x4716;
5219 }
5220
5221 b43_nphy_pmu_spur_avoid(dev, avoid);
5222
5223 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5224 dev->dev->chip_id == 43225) {
5225 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5226 avoid ? 0x5341 : 0x8889);
5227 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5228 }
5229
5230 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5231 ; /* TODO: reset PLL */
5232
5233 if (avoid)
5234 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5235 else
5236 b43_phy_mask(dev, B43_NPHY_BBCFG,
5237 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5238
5239 b43_nphy_reset_cca(dev);
5240
5241 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5242 }
5243
5244 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5245
5246 if (phy->rev >= 3)
5247 b43_nphy_spur_workaround(dev);
5248}
5249
eff66c51 5250/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5251static int b43_nphy_set_channel(struct b43_wldev *dev,
5252 struct ieee80211_channel *channel,
5253 enum nl80211_channel_type channel_type)
eff66c51 5254{
a656b6a9 5255 struct b43_phy *phy = &dev->phy;
eff66c51 5256
2eeb6fd0
JL		 5257 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5258 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5259
5260 u8 tmp;
eff66c51
RM		 5261
5262 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5263 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5264 channel->center_freq);
f19ebe7d
RM		 5265 if (!tabent_r3)
5266 return -ESRCH;
ffd2d9bd 5267 } else {
a656b6a9
RM		 5268 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5269 channel->hw_value);
f19ebe7d 5270 if (!tabent_r2)
ffd2d9bd 5271 return -ESRCH;
eff66c51
RM		 5272 }
5273
204a665b
RM		 5274 /* Channel is set later in common code, but we need to set it on our
5275 own to let this function's subcalls work properly. */
5276 phy->channel = channel->hw_value;
5277 phy->channel_freq = channel->center_freq;
eff66c51 5278
e5c407f9
RM		 5279 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5280 b43_channel_type_is_40mhz(channel_type))
5281 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5282
a656b6a9
RM		 5283 if (channel_type == NL80211_CHAN_HT40PLUS)
5284 b43_phy_set(dev, B43_NPHY_RXCTL,
5285 B43_NPHY_RXCTL_BSELU20);
5286 else if (channel_type == NL80211_CHAN_HT40MINUS)
5287 b43_phy_mask(dev, B43_NPHY_RXCTL,
5288 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5289
5290 if (dev->phy.rev >= 3) {
a656b6a9 5291 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5292 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5293 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5294 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5295 } else {
a656b6a9 5296 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5297 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5298 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5299 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5300 }
5301
5302 return 0;
5303}
5304
104cfa88
RM		 5305/**************************************************
5306 * Basic PHY ops.
5307 **************************************************/
5308
ef1a628d
MB		 5309static int b43_nphy_op_allocate(struct b43_wldev *dev)
5310{
5311 struct b43_phy_n *nphy;
5312
5313 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5314 if (!nphy)
5315 return -ENOMEM;
5316 dev->phy.n = nphy;
5317
ef1a628d
MB		 5318 return 0;
5319}
5320
fb11137a 5321static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5322{
fb11137a
MB		 5323 struct b43_phy *phy = &dev->phy;
5324 struct b43_phy_n *nphy = phy->n;
c7d64310 5325 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5326
fb11137a 5327 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5328
aca434d3 5329 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5330 nphy->spur_avoid = (phy->rev >= 3) ?
5331 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5332 nphy->init_por = true;
0b81c23d
RM		 5333 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5334 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5335 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5336 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5337 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5338 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5339 nphy->tx_pwr_idx[0] = 128;
5340 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5341
5342 /* Hardware TX power control and 5GHz power gain */
5343 nphy->txpwrctrl = false;
5344 nphy->pwg_gain_5ghz = false;
5345 if (dev->phy.rev >= 3 ||
5346 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5347 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5348 nphy->txpwrctrl = true;
5349 nphy->pwg_gain_5ghz = true;
5350 } else if (sprom->revision >= 4) {
5351 if (dev->phy.rev >= 2 &&
5352 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5353 nphy->txpwrctrl = true;
5354#ifdef CONFIG_B43_SSB
5355 if (dev->dev->bus_type == B43_BUS_SSB &&
5356 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5357 struct pci_dev *pdev =
5358 dev->dev->sdev->bus->host_pci;
5359 if (pdev->device == 0x4328 ||
5360 pdev->device == 0x432a)
5361 nphy->pwg_gain_5ghz = true;
5362 }
5363#endif
5364 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5365 nphy->pwg_gain_5ghz = true;
5366 }
5367 }
5368
5369 if (dev->phy.rev >= 3) {
5370 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5371 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5372 }
572d37a4
RM		 5373
5374 nphy->init_por = true;
ef1a628d
MB		 5375}
5376
fb11137a 5377static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5378{
fb11137a
MB		 5379 struct b43_phy *phy = &dev->phy;
5380 struct b43_phy_n *nphy = phy->n;
ef1a628d 5381
ef1a628d 5382 kfree(nphy);
fb11137a
MB		 5383 phy->n = NULL;
5384}
5385
5386static int b43_nphy_op_init(struct b43_wldev *dev)
5387{
5388 return b43_phy_initn(dev);
ef1a628d
MB		 5389}
5390
5391static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5392{
5393#if B43_DEBUG
5394 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5395 /* OFDM registers are onnly available on A/G-PHYs */
5396 b43err(dev->wl, "Invalid OFDM PHY access at "
5397 "0x%04X on N-PHY\n", offset);
5398 dump_stack();
5399 }
5400 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5401 /* Ext-G registers are only available on G-PHYs */
5402 b43err(dev->wl, "Invalid EXT-G PHY access at "
5403 "0x%04X on N-PHY\n", offset);
5404 dump_stack();
5405 }
5406#endif /* B43_DEBUG */
5407}
5408
5409static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5410{
5411 check_phyreg(dev, reg);
5412 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5413 return b43_read16(dev, B43_MMIO_PHY_DATA);
5414}
5415
5416static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5417{
5418 check_phyreg(dev, reg);
5419 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5420 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5421}
5422
755fd183
RM		 5423static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5424 u16 set)
5425{
5426 check_phyreg(dev, reg);
5427 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5428 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5429}
5430
ef1a628d
MB		 5431static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5432{
5433 /* Register 1 is a 32-bit register. */
5434 B43_WARN_ON(reg == 1);
5435 /* N-PHY needs 0x100 for read access */
5436 reg |= 0x100;
5437
5438 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5439 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5440}
5441
5442static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5443{
5444 /* Register 1 is a 32-bit register. */
5445 B43_WARN_ON(reg == 1);
5446
5447 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5448 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5449}
5450
c2b7aefd 5451/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5452static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5453 bool blocked)
c2b7aefd
RM		 5454{
5455 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5456 b43err(dev->wl, "MAC not suspended\n");
5457
5458 if (blocked) {
5459 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5460 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5461 if (dev->phy.rev >= 7) {
5462 /* TODO */
5463 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5464 b43_radio_mask(dev, 0x09, ~0x2);
5465
5466 b43_radio_write(dev, 0x204D, 0);
5467 b43_radio_write(dev, 0x2053, 0);
5468 b43_radio_write(dev, 0x2058, 0);
5469 b43_radio_write(dev, 0x205E, 0);
5470 b43_radio_mask(dev, 0x2062, ~0xF0);
5471 b43_radio_write(dev, 0x2064, 0);
5472
5473 b43_radio_write(dev, 0x304D, 0);
5474 b43_radio_write(dev, 0x3053, 0);
5475 b43_radio_write(dev, 0x3058, 0);
5476 b43_radio_write(dev, 0x305E, 0);
5477 b43_radio_mask(dev, 0x3062, ~0xF0);
5478 b43_radio_write(dev, 0x3064, 0);
5479 }
5480 } else {
572d37a4
RM		 5481 if (dev->phy.rev >= 7) {
5482 b43_radio_2057_init(dev);
5483 b43_switch_channel(dev, dev->phy.channel);
5484 } else if (dev->phy.rev >= 3) {
d817f4e1 5485 b43_radio_init2056(dev);
78159788 5486 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5487 } else {
5488 b43_radio_init2055(dev);
5489 }
5490 }
ef1a628d
MB		 5491}
5492
0f4091b9 5493/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5494static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5495{
2a870831
RM		 5496 u16 override = on ? 0x0 : 0x7FFF;
5497 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5498
2a870831
RM		 5499 if (dev->phy.rev >= 3) {
5500 if (on) {
5501 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5502 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5503 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5504 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5505 } else {
5506 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5507 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5508 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5509 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5510 }
5511 } else {
5512 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5513 }
cb24f57f
MB		 5514}
5515
ef1a628d
MB		 5516static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5517 unsigned int new_channel)
5518{
675a0b04
KB		 5519 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5520 enum nl80211_channel_type channel_type =
5521 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5522
ef1a628d
MB		 5523 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5524 if ((new_channel < 1) || (new_channel > 14))
5525 return -EINVAL;
5526 } else {
5527 if (new_channel > 200)
5528 return -EINVAL;
5529 }
5530
a656b6a9 5531 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5532}
5533
5534static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5535{
5536 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5537 return 1;
5538 return 36;
5539}
5540
ef1a628d
MB		 5541const struct b43_phy_operations b43_phyops_n = {
5542 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5543 .free = b43_nphy_op_free,
5544 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5545 .init = b43_nphy_op_init,
ef1a628d
MB		 5546 .phy_read = b43_nphy_op_read,
5547 .phy_write = b43_nphy_op_write,
755fd183 5548 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5549 .radio_read = b43_nphy_op_radio_read,
5550 .radio_write = b43_nphy_op_radio_write,
5551 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5552 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5553 .switch_channel = b43_nphy_op_switch_channel,
5554 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5555 .recalc_txpower = b43_nphy_op_recalc_txpower,
5556 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5557};
Linux kernel - Deliverables
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