[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c

/*

  Broadcom B43 wireless driver
  IEEE 802.11n PHY support

  Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; see the file COPYING.  If not, write to
  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  Boston, MA 02110-1301, USA.

*/

#include <linux/delay.h>
#include <linux/types.h>

#include "b43.h"
#include "phy_n.h"
#include "tables_nphy.h"

struct nphy_txgains {
	u16 txgm[2];
	u16 pga[2];
	u16 pad[2];
	u16 ipa[2];
};

struct nphy_iqcal_params {
	u16 txgm;
	u16 pga;
	u16 pad;
	u16 ipa;
	u16 cal_gain;
	u16 ncorr[5];
};

struct nphy_iq_est {
	s32 iq0_prod;
	u32 i0_pwr;
	u32 q0_pwr;
	s32 iq1_prod;
	u32 i1_pwr;
	u32 q1_pwr;
};

void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
{//TODO
}

static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
{//TODO
}

static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
							bool ignore_tssi)
{//TODO
	return B43_TXPWR_RES_DONE;
}

static void b43_chantab_radio_upload(struct b43_wldev *dev,
				     const struct b43_nphy_channeltab_entry *e)
{
	b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
	b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
	b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
	b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
	b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
	b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
	b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
	b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
	b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
	b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
	b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
	b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
	b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
	b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
	b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
	b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
	b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
	b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
	b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
	b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
	b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
	b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
}

static void b43_chantab_phy_upload(struct b43_wldev *dev,
				   const struct b43_nphy_channeltab_entry *e)
{
	b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
	b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
	b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
	b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
	b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
	b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
}

static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
{
	//TODO
}

/* Tune the hardware to a new channel. */
static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
{
	const struct b43_nphy_channeltab_entry *tabent;

	tabent = b43_nphy_get_chantabent(dev, channel);
	if (!tabent)
		return -ESRCH;

	//FIXME enable/disable band select upper20 in RXCTL
	if (0 /*FIXME 5Ghz*/)
		b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
	else
		b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
	b43_chantab_radio_upload(dev, tabent);
	udelay(50);
	b43_radio_write16(dev, B2055_VCO_CAL10, 5);
	b43_radio_write16(dev, B2055_VCO_CAL10, 45);
	b43_radio_write16(dev, B2055_VCO_CAL10, 65);
	udelay(300);
	if (0 /*FIXME 5Ghz*/)
		b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
	else
		b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
	b43_chantab_phy_upload(dev, tabent);
	b43_nphy_tx_power_fix(dev);

	return 0;
}

static void b43_radio_init2055_pre(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_PORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_CHIP0PU |
		    B43_NPHY_RFCTL_CMD_OEPORFORCE);
	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
		    B43_NPHY_RFCTL_CMD_PORFORCE);
}

static void b43_radio_init2055_post(struct b43_wldev *dev)
{
	struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
	struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
	int i;
	u16 val;

	b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
	msleep(1);
	if ((sprom->revision != 4) ||
	   !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
		if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
		    (binfo->type != 0x46D) ||
		    (binfo->rev < 0x41)) {
			b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
			b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
			msleep(1);
		}
	}
	b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
	msleep(1);
	b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
	msleep(1);
	b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_MISC, 0x1);
	msleep(1);
	b43_radio_set(dev, B2055_CAL_MISC, 0x40);
	msleep(1);
	for (i = 0; i < 100; i++) {
		val = b43_radio_read16(dev, B2055_CAL_COUT2);
		if (val & 0x80)
			break;
		udelay(10);
	}
	msleep(1);
	b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
	msleep(1);
	nphy_channel_switch(dev, dev->phy.channel);
	b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
	b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
	b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
	b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
}

/* Initialize a Broadcom 2055 N-radio */
static void b43_radio_init2055(struct b43_wldev *dev)
{
	b43_radio_init2055_pre(dev);
	if (b43_status(dev) < B43_STAT_INITIALIZED)
		b2055_upload_inittab(dev, 0, 1);
	else
		b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
	b43_radio_init2055_post(dev);
}

void b43_nphy_radio_turn_on(struct b43_wldev *dev)
{
	b43_radio_init2055(dev);
}

void b43_nphy_radio_turn_off(struct b43_wldev *dev)
{
	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
		     ~B43_NPHY_RFCTL_CMD_EN);
}

#define ntab_upload(dev, offset, data) do { \
		unsigned int i;						\
		for (i = 0; i < (offset##_SIZE); i++)			\
			b43_ntab_write(dev, (offset) + i, (data)[i]);	\
	} while (0)

/*
 * Upload the N-PHY tables.
 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 */
static void b43_nphy_tables_init(struct b43_wldev *dev)
{
	if (dev->phy.rev < 3)
		b43_nphy_rev0_1_2_tables_init(dev);
	else
		b43_nphy_rev3plus_tables_init(dev);
}

static void b43_nphy_workarounds(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	unsigned int i;

	b43_phy_set(dev, B43_NPHY_IQFLIP,
		    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
	if (1 /* FIXME band is 2.4GHz */) {
		b43_phy_set(dev, B43_NPHY_CLASSCTL,
			    B43_NPHY_CLASSCTL_CCKEN);
	} else {
		b43_phy_mask(dev, B43_NPHY_CLASSCTL,
			     ~B43_NPHY_CLASSCTL_CCKEN);
	}
	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
	b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);

	/* Fixup some tables */
	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);

	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);

	//TODO set RF sequence

	/* Set narrowband clip threshold */
	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);

	/* Set wideband clip 2 threshold */
	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
			~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
			21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
			~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
			21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);

	/* Set Clip 2 detect */
	b43_phy_set(dev, B43_NPHY_C1_CGAINI,
		    B43_NPHY_C1_CGAINI_CL2DETECT);
	b43_phy_set(dev, B43_NPHY_C2_CGAINI,
		    B43_NPHY_C2_CGAINI_CL2DETECT);

	if (0 /*FIXME*/) {
		/* Set dwell lengths */
		b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
		b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
		b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
		b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);

		/* Set gain backoff */
		b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
				~B43_NPHY_C1_CGAINI_GAINBKOFF,
				1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
		b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
				~B43_NPHY_C2_CGAINI_GAINBKOFF,
				1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);

		/* Set HPVGA2 index */
		b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
				~B43_NPHY_C1_INITGAIN_HPVGA2,
				6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
		b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
				~B43_NPHY_C2_INITGAIN_HPVGA2,
				6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);

		//FIXME verify that the specs really mean to use autoinc here.
		for (i = 0; i < 3; i++)
			b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
	}

	/* Set minimum gain value */
	b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
			~B43_NPHY_C1_MINGAIN,
			23 << B43_NPHY_C1_MINGAIN_SHIFT);
	b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
			~B43_NPHY_C2_MINGAIN,
			23 << B43_NPHY_C2_MINGAIN_SHIFT);

	if (phy->rev < 2) {
		b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
			     ~B43_NPHY_SCRAM_SIGCTL_SCM);
	}

	/* Set phase track alpha and beta */
	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
}

static void b43_nphy_reset_cca(struct b43_wldev *dev)
{
	u16 bbcfg;

	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
	bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
	b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
	b43_phy_write(dev, B43_NPHY_BBCFG,
		      bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
}

enum b43_nphy_rf_sequence {
	B43_RFSEQ_RX2TX,
	B43_RFSEQ_TX2RX,
	B43_RFSEQ_RESET2RX,
	B43_RFSEQ_UPDATE_GAINH,
	B43_RFSEQ_UPDATE_GAINL,
	B43_RFSEQ_UPDATE_GAINU,
};

static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
				       enum b43_nphy_rf_sequence seq)
{
	static const u16 trigger[] = {
		[B43_RFSEQ_RX2TX]		= B43_NPHY_RFSEQTR_RX2TX,
		[B43_RFSEQ_TX2RX]		= B43_NPHY_RFSEQTR_TX2RX,
		[B43_RFSEQ_RESET2RX]		= B43_NPHY_RFSEQTR_RST2RX,
		[B43_RFSEQ_UPDATE_GAINH]	= B43_NPHY_RFSEQTR_UPGH,
		[B43_RFSEQ_UPDATE_GAINL]	= B43_NPHY_RFSEQTR_UPGL,
		[B43_RFSEQ_UPDATE_GAINU]	= B43_NPHY_RFSEQTR_UPGU,
	};
	int i;

	B43_WARN_ON(seq >= ARRAY_SIZE(trigger));

	b43_phy_set(dev, B43_NPHY_RFSEQMODE,
		    B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
	b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
	for (i = 0; i < 200; i++) {
		if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
			goto ok;
		msleep(1);
	}
	b43err(dev->wl, "RF sequence status timeout\n");
ok:
	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
		     ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
}

static void b43_nphy_bphy_init(struct b43_wldev *dev)
{
	unsigned int i;
	u16 val;

	val = 0x1E1F;
	for (i = 0; i < 14; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
		val -= 0x202;
	}
	val = 0x3E3F;
	for (i = 0; i < 16; i++) {
		b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
		val -= 0x202;
	}
	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
}

/* RSSI Calibration */
static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
{
	//TODO
}

int b43_phy_initn(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	u16 tmp;

	//TODO: Spectral management
	b43_nphy_tables_init(dev);

	/* Clear all overrides */
	b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
	b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
		     ~(B43_NPHY_RFSEQMODE_CAOVER |
		       B43_NPHY_RFSEQMODE_TROVER));
	b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);

	tmp = (phy->rev < 2) ? 64 : 59;
	b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
			~B43_NPHY_BPHY_CTL3_SCALE,
			tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);

	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);

	b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
	b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
	b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
	b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);

	//TODO MIMO-Config
	//TODO Update TX/RX chain

	if (phy->rev < 2) {
		b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
		b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
	}
	b43_nphy_workarounds(dev);
	b43_nphy_reset_cca(dev);

	ssb_write32(dev->dev, SSB_TMSLOW,
		    ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);

	b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
	//TODO read core1/2 clip1 thres regs

	if (1 /* FIXME Band is 2.4GHz */)
		b43_nphy_bphy_init(dev);
	//TODO disable TX power control
	//TODO Fix the TX power settings
	//TODO Init periodic calibration with reason 3
	b43_nphy_rssi_cal(dev, 2);
	b43_nphy_rssi_cal(dev, 0);
	b43_nphy_rssi_cal(dev, 1);
	//TODO get TX gain
	//TODO init superswitch
	//TODO calibrate LO
	//TODO idle TSSI TX pctl
	//TODO TX power control power setup
	//TODO table writes
	//TODO TX power control coefficients
	//TODO enable TX power control
	//TODO control antenna selection
	//TODO init radar detection
	//TODO reset channel if changed

	b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
	return 0;
}

static int b43_nphy_op_allocate(struct b43_wldev *dev)
{
	struct b43_phy_n *nphy;

	nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
	if (!nphy)
		return -ENOMEM;
	dev->phy.n = nphy;

	return 0;
}

static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;

	memset(nphy, 0, sizeof(*nphy));

	//TODO init struct b43_phy_n
}

static void b43_nphy_op_free(struct b43_wldev *dev)
{
	struct b43_phy *phy = &dev->phy;
	struct b43_phy_n *nphy = phy->n;

	kfree(nphy);
	phy->n = NULL;
}

static int b43_nphy_op_init(struct b43_wldev *dev)
{
	return b43_phy_initn(dev);
}

static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
{
#if B43_DEBUG
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
		/* OFDM registers are onnly available on A/G-PHYs */
		b43err(dev->wl, "Invalid OFDM PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
		/* Ext-G registers are only available on G-PHYs */
		b43err(dev->wl, "Invalid EXT-G PHY access at "
		       "0x%04X on N-PHY\n", offset);
		dump_stack();
	}
#endif /* B43_DEBUG */
}

static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_PHY_DATA);
}

static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	check_phyreg(dev, reg);
	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
{
	/* Register 1 is a 32-bit register. */
	B43_WARN_ON(reg == 1);
	/* N-PHY needs 0x100 for read access */
	reg |= 0x100;

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}

static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
	/* Register 1 is a 32-bit register. */
	B43_WARN_ON(reg == 1);

	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}

static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
					bool blocked)
{//TODO
}

static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
{
	b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
		      on ? 0 : 0x7FFF);
}

static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
				      unsigned int new_channel)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
		if ((new_channel < 1) || (new_channel > 14))
			return -EINVAL;
	} else {
		if (new_channel > 200)
			return -EINVAL;
	}

	return nphy_channel_switch(dev, new_channel);
}

static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
{
	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
		return 1;
	return 36;
}

const struct b43_phy_operations b43_phyops_n = {
	.allocate		= b43_nphy_op_allocate,
	.free			= b43_nphy_op_free,
	.prepare_structs	= b43_nphy_op_prepare_structs,
	.init			= b43_nphy_op_init,
	.phy_read		= b43_nphy_op_read,
	.phy_write		= b43_nphy_op_write,
	.radio_read		= b43_nphy_op_radio_read,
	.radio_write		= b43_nphy_op_radio_write,
	.software_rfkill	= b43_nphy_op_software_rfkill,
	.switch_analog		= b43_nphy_op_switch_analog,
	.switch_channel		= b43_nphy_op_switch_channel,
	.get_default_chan	= b43_nphy_op_get_default_chan,
	.recalc_txpower		= b43_nphy_op_recalc_txpower,
	.adjust_txpower		= b43_nphy_op_adjust_txpower,
};
Commit	Line	Data
424047e6 MB	1	/*
	2
	3	Broadcom B43 wireless driver
	4	IEEE 802.11n PHY support
	5
	6	Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; see the file COPYING. If not, write to
	20	the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
	21	Boston, MA 02110-1301, USA.
	22
	23	*/
	24
819d772b JL	25	#include <linux/delay.h>
	26	#include <linux/types.h>
	27
424047e6	28	#include "b43.h"
3d0da751	29	#include "phy_n.h"
53a6e234	30	#include "tables_nphy.h"
424047e6	31
f8187b5b RM	32	struct nphy_txgains {
	33	u16 txgm[2];
	34	u16 pga[2];
	35	u16 pad[2];
	36	u16 ipa[2];
	37	};
	38
	39	struct nphy_iqcal_params {
	40	u16 txgm;
	41	u16 pga;
	42	u16 pad;
	43	u16 ipa;
	44	u16 cal_gain;
	45	u16 ncorr[5];
	46	};
	47
	48	struct nphy_iq_est {
	49	s32 iq0_prod;
	50	u32 i0_pwr;
	51	u32 q0_pwr;
	52	s32 iq1_prod;
	53	u32 i1_pwr;
	54	u32 q1_pwr;
	55	};
424047e6	56
53a6e234 MB	57	void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
	58	{//TODO
	59	}
	60
18c8adeb	61	static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234 MB	62	{//TODO
	63	}
	64
18c8adeb MB	65	static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
	66	bool ignore_tssi)
	67	{//TODO
	68	return B43_TXPWR_RES_DONE;
	69	}
	70
d1591314 MB	71	static void b43_chantab_radio_upload(struct b43_wldev *dev,
	72	const struct b43_nphy_channeltab_entry *e)
	73	{
	74	b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
	75	b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
	76	b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
	77	b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
	78	b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
	79	b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
	80	b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
	81	b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
	82	b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
	83	b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
	84	b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
	85	b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
	86	b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
	87	b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
	88	b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
	89	b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
	90	b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
	91	b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
	92	b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
	93	b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
	94	b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
	95	b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
	96	}
	97
	98	static void b43_chantab_phy_upload(struct b43_wldev *dev,
	99	const struct b43_nphy_channeltab_entry *e)
	100	{
	101	b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
	102	b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
	103	b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
	104	b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
	105	b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
	106	b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
	107	}
	108
	109	static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
	110	{
	111	//TODO
	112	}
	113
ef1a628d MB	114	/* Tune the hardware to a new channel. */
ef1a628d MB	115	static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234	116	{
d1591314 MB	117	const struct b43_nphy_channeltab_entry *tabent;
	118
	119	tabent = b43_nphy_get_chantabent(dev, channel);
	120	if (!tabent)
	121	return -ESRCH;
	122
	123	//FIXME enable/disable band select upper20 in RXCTL
	124	if (0 /FIXME 5Ghz/)
	125	b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
	126	else
	127	b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
	128	b43_chantab_radio_upload(dev, tabent);
	129	udelay(50);
	130	b43_radio_write16(dev, B2055_VCO_CAL10, 5);
	131	b43_radio_write16(dev, B2055_VCO_CAL10, 45);
	132	b43_radio_write16(dev, B2055_VCO_CAL10, 65);
	133	udelay(300);
	134	if (0 /FIXME 5Ghz/)
	135	b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
	136	else
	137	b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
	138	b43_chantab_phy_upload(dev, tabent);
	139	b43_nphy_tx_power_fix(dev);
53a6e234	140
d1591314	141	return 0;
53a6e234 MB	142	}
	143
	144	static void b43_radio_init2055_pre(struct b43_wldev *dev)
	145	{
	146	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
	147	~B43_NPHY_RFCTL_CMD_PORFORCE);
	148	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
	149	B43_NPHY_RFCTL_CMD_CHIP0PU \|
	150	B43_NPHY_RFCTL_CMD_OEPORFORCE);
	151	b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
	152	B43_NPHY_RFCTL_CMD_PORFORCE);
	153	}
	154
	155	static void b43_radio_init2055_post(struct b43_wldev *dev)
	156	{
	157	struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
	158	struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
	159	int i;
	160	u16 val;
	161
	162	b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
	163	msleep(1);
738f0f43 GS	164	if ((sprom->revision != 4) \|\|
738f0f43 GS	165	!(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234 MB	166	if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) \|\|
	167	(binfo->type != 0x46D) \|\|
	168	(binfo->rev < 0x41)) {
	169	b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
	170	b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
	171	msleep(1);
	172	}
	173	}
	174	b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
	175	msleep(1);
	176	b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
	177	msleep(1);
	178	b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
	179	msleep(1);
	180	b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
	181	msleep(1);
	182	b43_radio_set(dev, B2055_CAL_MISC, 0x1);
	183	msleep(1);
	184	b43_radio_set(dev, B2055_CAL_MISC, 0x40);
	185	msleep(1);
	186	for (i = 0; i < 100; i++) {
	187	val = b43_radio_read16(dev, B2055_CAL_COUT2);
	188	if (val & 0x80)
	189	break;
	190	udelay(10);
	191	}
	192	msleep(1);
	193	b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
	194	msleep(1);
ef1a628d	195	nphy_channel_switch(dev, dev->phy.channel);
53a6e234 MB	196	b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
	197	b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
	198	b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
	199	b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
	200	}
	201
	202	/* Initialize a Broadcom 2055 N-radio */
	203	static void b43_radio_init2055(struct b43_wldev *dev)
	204	{
	205	b43_radio_init2055_pre(dev);
	206	if (b43_status(dev) < B43_STAT_INITIALIZED)
	207	b2055_upload_inittab(dev, 0, 1);
	208	else
	209	b2055_upload_inittab(dev, 0/FIXME on 5ghz band/, 0);
	210	b43_radio_init2055_post(dev);
	211	}
	212
	213	void b43_nphy_radio_turn_on(struct b43_wldev *dev)
	214	{
	215	b43_radio_init2055(dev);
	216	}
	217
	218	void b43_nphy_radio_turn_off(struct b43_wldev *dev)
	219	{
	220	b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
	221	~B43_NPHY_RFCTL_CMD_EN);
	222	}
	223
95b66bad MB	224	#define ntab_upload(dev, offset, data) do { \
	225	unsigned int i; \
	226	for (i = 0; i < (offset##_SIZE); i++) \
	227	b43_ntab_write(dev, (offset) + i, (data)[i]); \
	228	} while (0)
	229
4772ae10 RM	230	/*
	231	* Upload the N-PHY tables.
	232	* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
	233	*/
95b66bad MB	234	static void b43_nphy_tables_init(struct b43_wldev *dev)
95b66bad MB	235	{
4772ae10 RM	236	if (dev->phy.rev < 3)
	237	b43_nphy_rev0_1_2_tables_init(dev);
	238	else
	239	b43_nphy_rev3plus_tables_init(dev);
95b66bad MB	240	}
	241
	242	static void b43_nphy_workarounds(struct b43_wldev *dev)
	243	{
	244	struct b43_phy *phy = &dev->phy;
	245	unsigned int i;
	246
	247	b43_phy_set(dev, B43_NPHY_IQFLIP,
	248	B43_NPHY_IQFLIP_ADC1 \| B43_NPHY_IQFLIP_ADC2);
95b66bad MB	249	if (1 /* FIXME band is 2.4GHz */) {
	250	b43_phy_set(dev, B43_NPHY_CLASSCTL,
	251	B43_NPHY_CLASSCTL_CCKEN);
	252	} else {
	253	b43_phy_mask(dev, B43_NPHY_CLASSCTL,
	254	~B43_NPHY_CLASSCTL_CCKEN);
	255	}
	256	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
	257	b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
	258
	259	/* Fixup some tables */
	260	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
	261	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
	262	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
	263	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
	264	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
	265	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
	266	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
	267	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
	268	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
	269	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
	270
	271	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
	272	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
	273	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
	274	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
	275
	276	//TODO set RF sequence
	277
	278	/* Set narrowband clip threshold */
	279	b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
	280	b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
	281
	282	/* Set wideband clip 2 threshold */
	283	b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
	284	~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
	285	21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
	286	b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
	287	~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
	288	21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
	289
	290	/* Set Clip 2 detect */
	291	b43_phy_set(dev, B43_NPHY_C1_CGAINI,
	292	B43_NPHY_C1_CGAINI_CL2DETECT);
	293	b43_phy_set(dev, B43_NPHY_C2_CGAINI,
	294	B43_NPHY_C2_CGAINI_CL2DETECT);
	295
	296	if (0 /FIXME/) {
	297	/* Set dwell lengths */
	298	b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
	299	b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
	300	b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
	301	b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
	302
	303	/* Set gain backoff */
	304	b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
	305	~B43_NPHY_C1_CGAINI_GAINBKOFF,
	306	1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
	307	b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
	308	~B43_NPHY_C2_CGAINI_GAINBKOFF,
	309	1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
	310
	311	/* Set HPVGA2 index */
	312	b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
313	~B43_NPHY_C1_INITGAIN_HPVGA2,
314	6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
315	b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
316	~B43_NPHY_C2_INITGAIN_HPVGA2,
317	6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
318
319	//FIXME verify that the specs really mean to use autoinc here.
320	for (i = 0; i < 3; i++)
321	b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
322	}
323
324	/* Set minimum gain value */
325	b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
326	~B43_NPHY_C1_MINGAIN,
327	23 << B43_NPHY_C1_MINGAIN_SHIFT);
328	b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
329	~B43_NPHY_C2_MINGAIN,
330	23 << B43_NPHY_C2_MINGAIN_SHIFT);
331
332	if (phy->rev < 2) {
333	b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
334	~B43_NPHY_SCRAM_SIGCTL_SCM);
335	}
336
337	/* Set phase track alpha and beta */
338	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
339	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
340	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
341	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
342	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
343	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
344	}
345
346	static void b43_nphy_reset_cca(struct b43_wldev *dev)
347	{
348	u16 bbcfg;
349
350	ssb_write32(dev->dev, SSB_TMSLOW,
351	ssb_read32(dev->dev, SSB_TMSLOW) \| SSB_TMSLOW_FGC);
352	bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
353	b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
354	b43_phy_write(dev, B43_NPHY_BBCFG,
355	bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
356	ssb_write32(dev->dev, SSB_TMSLOW,
357	ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
358	}
359
360	enum b43_nphy_rf_sequence {
361	B43_RFSEQ_RX2TX,
362	B43_RFSEQ_TX2RX,
363	B43_RFSEQ_RESET2RX,
364	B43_RFSEQ_UPDATE_GAINH,
365	B43_RFSEQ_UPDATE_GAINL,
366	B43_RFSEQ_UPDATE_GAINU,
367	};
368
369	static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
370	enum b43_nphy_rf_sequence seq)
371	{
372	static const u16 trigger[] = {
373	[B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
374	[B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
375	[B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
376	[B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
377	[B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
378	[B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
379	};
380	int i;
381
382	B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
383
384	b43_phy_set(dev, B43_NPHY_RFSEQMODE,
385	B43_NPHY_RFSEQMODE_CAOVER \| B43_NPHY_RFSEQMODE_TROVER);
386	b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
387	for (i = 0; i < 200; i++) {
388	if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
389	goto ok;
390	msleep(1);
391	}
392	b43err(dev->wl, "RF sequence status timeout\n");
393	ok:
394	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
395	~(B43_NPHY_RFSEQMODE_CAOVER \| B43_NPHY_RFSEQMODE_TROVER));
396	}
397
398	static void b43_nphy_bphy_init(struct b43_wldev *dev)
399	{
400	unsigned int i;
401	u16 val;
402
403	val = 0x1E1F;
404	for (i = 0; i < 14; i++) {
405	b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
406	val -= 0x202;
407	}
408	val = 0x3E3F;
409	for (i = 0; i < 16; i++) {
410	b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
411	val -= 0x202;
412	}
413	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
414	}
415
416	/* RSSI Calibration */
417	static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
418	{
419	//TODO
420	}
421
424047e6 MB	422	int b43_phy_initn(struct b43_wldev *dev)
424047e6 MB	423	{
95b66bad MB	424	struct b43_phy *phy = &dev->phy;
	425	u16 tmp;
	426
	427	//TODO: Spectral management
	428	b43_nphy_tables_init(dev);
	429
	430	/* Clear all overrides */
	431	b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
	432	b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
	433	b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
	434	b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
	435	b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
	436	b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
	437	~(B43_NPHY_RFSEQMODE_CAOVER \|
	438	B43_NPHY_RFSEQMODE_TROVER));
	439	b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
	440
	441	tmp = (phy->rev < 2) ? 64 : 59;
	442	b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
	443	~B43_NPHY_BPHY_CTL3_SCALE,
	444	tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
	445
	446	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
	447	b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
	448
	449	b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
	450	b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
	451	b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
	452	b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
424047e6	453
95b66bad MB	454	//TODO MIMO-Config
	455	//TODO Update TX/RX chain
	456
	457	if (phy->rev < 2) {
	458	b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
	459	b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
	460	}
	461	b43_nphy_workarounds(dev);
	462	b43_nphy_reset_cca(dev);
	463
	464	ssb_write32(dev->dev, SSB_TMSLOW,
	465	ssb_read32(dev->dev, SSB_TMSLOW) \| B43_TMSLOW_MACPHYCLKEN);
	466	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
	467	b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
	468
	469	b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
	470	//TODO read core1/2 clip1 thres regs
	471
	472	if (1 /* FIXME Band is 2.4GHz */)
	473	b43_nphy_bphy_init(dev);
	474	//TODO disable TX power control
	475	//TODO Fix the TX power settings
	476	//TODO Init periodic calibration with reason 3
	477	b43_nphy_rssi_cal(dev, 2);
	478	b43_nphy_rssi_cal(dev, 0);
	479	b43_nphy_rssi_cal(dev, 1);
	480	//TODO get TX gain
	481	//TODO init superswitch
	482	//TODO calibrate LO
	483	//TODO idle TSSI TX pctl
	484	//TODO TX power control power setup
	485	//TODO table writes
	486	//TODO TX power control coefficients
	487	//TODO enable TX power control
	488	//TODO control antenna selection
	489	//TODO init radar detection
	490	//TODO reset channel if changed
	491
	492	b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234	493	return 0;
424047e6	494	}
ef1a628d MB	495
	496	static int b43_nphy_op_allocate(struct b43_wldev *dev)
	497	{
	498	struct b43_phy_n *nphy;
	499
	500	nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
	501	if (!nphy)
	502	return -ENOMEM;
	503	dev->phy.n = nphy;
	504
ef1a628d MB	505	return 0;
	506	}
	507
fb11137a	508	static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d	509	{
fb11137a MB	510	struct b43_phy *phy = &dev->phy;
fb11137a MB	511	struct b43_phy_n *nphy = phy->n;
ef1a628d	512
fb11137a	513	memset(nphy, 0, sizeof(*nphy));
ef1a628d	514
fb11137a	515	//TODO init struct b43_phy_n
ef1a628d MB	516	}
ef1a628d MB	517
fb11137a	518	static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d	519	{
fb11137a MB	520	struct b43_phy *phy = &dev->phy;
fb11137a MB	521	struct b43_phy_n *nphy = phy->n;
ef1a628d	522
ef1a628d	523	kfree(nphy);
fb11137a MB	524	phy->n = NULL;
	525	}
	526
	527	static int b43_nphy_op_init(struct b43_wldev *dev)
	528	{
	529	return b43_phy_initn(dev);
ef1a628d MB	530	}
	531
	532	static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
	533	{
	534	#if B43_DEBUG
	535	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
	536	/* OFDM registers are onnly available on A/G-PHYs */
	537	b43err(dev->wl, "Invalid OFDM PHY access at "
	538	"0x%04X on N-PHY\n", offset);
	539	dump_stack();
	540	}
	541	if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
	542	/* Ext-G registers are only available on G-PHYs */
	543	b43err(dev->wl, "Invalid EXT-G PHY access at "
	544	"0x%04X on N-PHY\n", offset);
	545	dump_stack();
	546	}
	547	#endif /* B43_DEBUG */
	548	}
	549
	550	static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
	551	{
	552	check_phyreg(dev, reg);
	553	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	554	return b43_read16(dev, B43_MMIO_PHY_DATA);
	555	}
	556
	557	static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
	558	{
	559	check_phyreg(dev, reg);
	560	b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
	561	b43_write16(dev, B43_MMIO_PHY_DATA, value);
	562	}
	563
	564	static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
	565	{
	566	/* Register 1 is a 32-bit register. */
	567	B43_WARN_ON(reg == 1);
	568	/* N-PHY needs 0x100 for read access */
	569	reg \|= 0x100;
	570
	571	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	572	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
	573	}
	574
	575	static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
	576	{
	577	/* Register 1 is a 32-bit register. */
	578	B43_WARN_ON(reg == 1);
	579
	580	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
	581	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
	582	}
	583
	584	static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df	585	bool blocked)
ef1a628d MB	586	{//TODO
	587	}
	588
cb24f57f MB	589	static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
	590	{
	591	b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
	592	on ? 0 : 0x7FFF);
	593	}
	594
ef1a628d MB	595	static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
	596	unsigned int new_channel)
	597	{
	598	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
	599	if ((new_channel < 1) \|\| (new_channel > 14))
	600	return -EINVAL;
	601	} else {
	602	if (new_channel > 200)
	603	return -EINVAL;
	604	}
	605
	606	return nphy_channel_switch(dev, new_channel);
	607	}
	608
	609	static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
	610	{
	611	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
	612	return 1;
	613	return 36;
	614	}
	615
ef1a628d MB	616	const struct b43_phy_operations b43_phyops_n = {
ef1a628d MB	617	.allocate = b43_nphy_op_allocate,
fb11137a MB	618	.free = b43_nphy_op_free,
fb11137a MB	619	.prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d	620	.init = b43_nphy_op_init,
ef1a628d MB	621	.phy_read = b43_nphy_op_read,
	622	.phy_write = b43_nphy_op_write,
	623	.radio_read = b43_nphy_op_radio_read,
	624	.radio_write = b43_nphy_op_radio_write,
	625	.software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f	626	.switch_analog = b43_nphy_op_switch_analog,
ef1a628d MB	627	.switch_channel = b43_nphy_op_switch_channel,
ef1a628d MB	628	.get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb MB	629	.recalc_txpower = b43_nphy_op_recalc_txpower,
18c8adeb MB	630	.adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d	631	};