Commit | Line | Data |
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424047e6 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | IEEE 802.11n PHY support | |
5 | ||
6 | Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
21 | Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
819d772b JL |
25 | #include <linux/delay.h> |
26 | #include <linux/types.h> | |
27 | ||
424047e6 | 28 | #include "b43.h" |
3d0da751 | 29 | #include "phy_n.h" |
53a6e234 | 30 | #include "tables_nphy.h" |
bbec398c | 31 | #include "main.h" |
424047e6 | 32 | |
f8187b5b RM |
33 | struct nphy_txgains { |
34 | u16 txgm[2]; | |
35 | u16 pga[2]; | |
36 | u16 pad[2]; | |
37 | u16 ipa[2]; | |
38 | }; | |
39 | ||
40 | struct nphy_iqcal_params { | |
41 | u16 txgm; | |
42 | u16 pga; | |
43 | u16 pad; | |
44 | u16 ipa; | |
45 | u16 cal_gain; | |
46 | u16 ncorr[5]; | |
47 | }; | |
48 | ||
49 | struct nphy_iq_est { | |
50 | s32 iq0_prod; | |
51 | u32 i0_pwr; | |
52 | u32 q0_pwr; | |
53 | s32 iq1_prod; | |
54 | u32 i1_pwr; | |
55 | u32 q1_pwr; | |
56 | }; | |
424047e6 | 57 | |
67c0d6e2 RM |
58 | enum b43_nphy_rf_sequence { |
59 | B43_RFSEQ_RX2TX, | |
60 | B43_RFSEQ_TX2RX, | |
61 | B43_RFSEQ_RESET2RX, | |
62 | B43_RFSEQ_UPDATE_GAINH, | |
63 | B43_RFSEQ_UPDATE_GAINL, | |
64 | B43_RFSEQ_UPDATE_GAINU, | |
65 | }; | |
66 | ||
67 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, | |
68 | enum b43_nphy_rf_sequence seq); | |
69 | ||
53a6e234 MB |
70 | void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) |
71 | {//TODO | |
72 | } | |
73 | ||
18c8adeb | 74 | static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) |
53a6e234 MB |
75 | {//TODO |
76 | } | |
77 | ||
18c8adeb MB |
78 | static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, |
79 | bool ignore_tssi) | |
80 | {//TODO | |
81 | return B43_TXPWR_RES_DONE; | |
82 | } | |
83 | ||
d1591314 MB |
84 | static void b43_chantab_radio_upload(struct b43_wldev *dev, |
85 | const struct b43_nphy_channeltab_entry *e) | |
86 | { | |
87 | b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref); | |
88 | b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); | |
89 | b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); | |
90 | b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); | |
91 | b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1); | |
92 | b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2); | |
93 | b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); | |
94 | b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); | |
95 | b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); | |
96 | b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); | |
97 | b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); | |
98 | b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); | |
99 | b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); | |
100 | b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); | |
101 | b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); | |
102 | b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); | |
103 | b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); | |
104 | b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); | |
105 | b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); | |
106 | b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); | |
107 | b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); | |
108 | b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); | |
109 | } | |
110 | ||
111 | static void b43_chantab_phy_upload(struct b43_wldev *dev, | |
112 | const struct b43_nphy_channeltab_entry *e) | |
113 | { | |
114 | b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); | |
115 | b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); | |
116 | b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); | |
117 | b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); | |
118 | b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); | |
119 | b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); | |
120 | } | |
121 | ||
122 | static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |
123 | { | |
124 | //TODO | |
125 | } | |
126 | ||
ef1a628d MB |
127 | /* Tune the hardware to a new channel. */ |
128 | static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel) | |
53a6e234 | 129 | { |
d1591314 MB |
130 | const struct b43_nphy_channeltab_entry *tabent; |
131 | ||
132 | tabent = b43_nphy_get_chantabent(dev, channel); | |
133 | if (!tabent) | |
134 | return -ESRCH; | |
135 | ||
136 | //FIXME enable/disable band select upper20 in RXCTL | |
137 | if (0 /*FIXME 5Ghz*/) | |
138 | b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20); | |
139 | else | |
140 | b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50); | |
141 | b43_chantab_radio_upload(dev, tabent); | |
142 | udelay(50); | |
143 | b43_radio_write16(dev, B2055_VCO_CAL10, 5); | |
144 | b43_radio_write16(dev, B2055_VCO_CAL10, 45); | |
145 | b43_radio_write16(dev, B2055_VCO_CAL10, 65); | |
146 | udelay(300); | |
147 | if (0 /*FIXME 5Ghz*/) | |
148 | b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); | |
149 | else | |
150 | b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); | |
151 | b43_chantab_phy_upload(dev, tabent); | |
152 | b43_nphy_tx_power_fix(dev); | |
53a6e234 | 153 | |
d1591314 | 154 | return 0; |
53a6e234 MB |
155 | } |
156 | ||
157 | static void b43_radio_init2055_pre(struct b43_wldev *dev) | |
158 | { | |
159 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
160 | ~B43_NPHY_RFCTL_CMD_PORFORCE); | |
161 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
162 | B43_NPHY_RFCTL_CMD_CHIP0PU | | |
163 | B43_NPHY_RFCTL_CMD_OEPORFORCE); | |
164 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
165 | B43_NPHY_RFCTL_CMD_PORFORCE); | |
166 | } | |
167 | ||
168 | static void b43_radio_init2055_post(struct b43_wldev *dev) | |
169 | { | |
170 | struct ssb_sprom *sprom = &(dev->dev->bus->sprom); | |
171 | struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); | |
172 | int i; | |
173 | u16 val; | |
174 | ||
175 | b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); | |
176 | msleep(1); | |
738f0f43 GS |
177 | if ((sprom->revision != 4) || |
178 | !(sprom->boardflags_hi & B43_BFH_RSSIINV)) { | |
53a6e234 MB |
179 | if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) || |
180 | (binfo->type != 0x46D) || | |
181 | (binfo->rev < 0x41)) { | |
182 | b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); | |
183 | b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); | |
184 | msleep(1); | |
185 | } | |
186 | } | |
187 | b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C); | |
188 | msleep(1); | |
189 | b43_radio_write16(dev, B2055_CAL_MISC, 0x3C); | |
190 | msleep(1); | |
191 | b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); | |
192 | msleep(1); | |
193 | b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); | |
194 | msleep(1); | |
195 | b43_radio_set(dev, B2055_CAL_MISC, 0x1); | |
196 | msleep(1); | |
197 | b43_radio_set(dev, B2055_CAL_MISC, 0x40); | |
198 | msleep(1); | |
199 | for (i = 0; i < 100; i++) { | |
200 | val = b43_radio_read16(dev, B2055_CAL_COUT2); | |
201 | if (val & 0x80) | |
202 | break; | |
203 | udelay(10); | |
204 | } | |
205 | msleep(1); | |
206 | b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); | |
207 | msleep(1); | |
ef1a628d | 208 | nphy_channel_switch(dev, dev->phy.channel); |
53a6e234 MB |
209 | b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9); |
210 | b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9); | |
211 | b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83); | |
212 | b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83); | |
213 | } | |
214 | ||
215 | /* Initialize a Broadcom 2055 N-radio */ | |
216 | static void b43_radio_init2055(struct b43_wldev *dev) | |
217 | { | |
218 | b43_radio_init2055_pre(dev); | |
219 | if (b43_status(dev) < B43_STAT_INITIALIZED) | |
220 | b2055_upload_inittab(dev, 0, 1); | |
221 | else | |
222 | b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0); | |
223 | b43_radio_init2055_post(dev); | |
224 | } | |
225 | ||
226 | void b43_nphy_radio_turn_on(struct b43_wldev *dev) | |
227 | { | |
228 | b43_radio_init2055(dev); | |
229 | } | |
230 | ||
231 | void b43_nphy_radio_turn_off(struct b43_wldev *dev) | |
232 | { | |
233 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
234 | ~B43_NPHY_RFCTL_CMD_EN); | |
235 | } | |
236 | ||
4772ae10 RM |
237 | /* |
238 | * Upload the N-PHY tables. | |
239 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables | |
240 | */ | |
95b66bad MB |
241 | static void b43_nphy_tables_init(struct b43_wldev *dev) |
242 | { | |
4772ae10 RM |
243 | if (dev->phy.rev < 3) |
244 | b43_nphy_rev0_1_2_tables_init(dev); | |
245 | else | |
246 | b43_nphy_rev3plus_tables_init(dev); | |
95b66bad MB |
247 | } |
248 | ||
e50cbcf6 RM |
249 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ |
250 | static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) | |
251 | { | |
252 | struct b43_phy_n *nphy = dev->phy.n; | |
253 | enum ieee80211_band band; | |
254 | u16 tmp; | |
255 | ||
256 | if (!enable) { | |
257 | nphy->rfctrl_intc1_save = b43_phy_read(dev, | |
258 | B43_NPHY_RFCTL_INTC1); | |
259 | nphy->rfctrl_intc2_save = b43_phy_read(dev, | |
260 | B43_NPHY_RFCTL_INTC2); | |
261 | band = b43_current_band(dev->wl); | |
262 | if (dev->phy.rev >= 3) { | |
263 | if (band == IEEE80211_BAND_5GHZ) | |
264 | tmp = 0x600; | |
265 | else | |
266 | tmp = 0x480; | |
267 | } else { | |
268 | if (band == IEEE80211_BAND_5GHZ) | |
269 | tmp = 0x180; | |
270 | else | |
271 | tmp = 0x120; | |
272 | } | |
273 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
274 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
275 | } else { | |
276 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, | |
277 | nphy->rfctrl_intc1_save); | |
278 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, | |
279 | nphy->rfctrl_intc2_save); | |
280 | } | |
281 | } | |
282 | ||
fe3e46e8 RM |
283 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ |
284 | static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) | |
285 | { | |
286 | struct b43_phy_n *nphy = dev->phy.n; | |
287 | u16 tmp; | |
288 | enum ieee80211_band band = b43_current_band(dev->wl); | |
289 | bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || | |
290 | (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); | |
291 | ||
292 | if (dev->phy.rev >= 3) { | |
293 | if (ipa) { | |
294 | tmp = 4; | |
295 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, | |
296 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
297 | } | |
298 | ||
299 | tmp = 1; | |
300 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, | |
301 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
302 | } | |
303 | } | |
304 | ||
4a933c85 RM |
305 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ |
306 | static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) | |
307 | { | |
308 | u32 tmslow; | |
309 | ||
310 | if (dev->phy.type != B43_PHYTYPE_N) | |
311 | return; | |
312 | ||
313 | tmslow = ssb_read32(dev->dev, SSB_TMSLOW); | |
314 | if (force) | |
315 | tmslow |= SSB_TMSLOW_FGC; | |
316 | else | |
317 | tmslow &= ~SSB_TMSLOW_FGC; | |
318 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | |
319 | } | |
320 | ||
321 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ | |
95b66bad MB |
322 | static void b43_nphy_reset_cca(struct b43_wldev *dev) |
323 | { | |
324 | u16 bbcfg; | |
325 | ||
4a933c85 | 326 | b43_nphy_bmac_clock_fgc(dev, 1); |
95b66bad | 327 | bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); |
4a933c85 RM |
328 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); |
329 | udelay(1); | |
330 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); | |
331 | b43_nphy_bmac_clock_fgc(dev, 0); | |
67c0d6e2 | 332 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
95b66bad MB |
333 | } |
334 | ||
ad9716e8 RM |
335 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ |
336 | static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) | |
337 | { | |
338 | u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); | |
339 | ||
340 | mimocfg |= B43_NPHY_MIMOCFG_AUTO; | |
341 | if (preamble == 1) | |
342 | mimocfg |= B43_NPHY_MIMOCFG_GFMIX; | |
343 | else | |
344 | mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; | |
345 | ||
346 | b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); | |
347 | } | |
348 | ||
4f4ab6cd RM |
349 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ |
350 | static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) | |
351 | { | |
352 | struct b43_phy_n *nphy = dev->phy.n; | |
353 | ||
354 | bool override = false; | |
355 | u16 chain = 0x33; | |
356 | ||
357 | if (nphy->txrx_chain == 0) { | |
358 | chain = 0x11; | |
359 | override = true; | |
360 | } else if (nphy->txrx_chain == 1) { | |
361 | chain = 0x22; | |
362 | override = true; | |
363 | } | |
364 | ||
365 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
366 | ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), | |
367 | chain); | |
368 | ||
369 | if (override) | |
370 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
371 | B43_NPHY_RFSEQMODE_CAOVER); | |
372 | else | |
373 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, | |
374 | ~B43_NPHY_RFSEQMODE_CAOVER); | |
375 | } | |
376 | ||
2faa6b83 RM |
377 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ |
378 | static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, | |
379 | u16 samps, u8 time, bool wait) | |
380 | { | |
381 | int i; | |
382 | u16 tmp; | |
383 | ||
384 | b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); | |
385 | b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); | |
386 | if (wait) | |
387 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); | |
388 | else | |
389 | b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); | |
390 | ||
391 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); | |
392 | ||
393 | for (i = 1000; i; i--) { | |
394 | tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); | |
395 | if (!(tmp & B43_NPHY_IQEST_CMD_START)) { | |
396 | est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | | |
397 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); | |
398 | est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | | |
399 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); | |
400 | est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | | |
401 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); | |
402 | ||
403 | est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | | |
404 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); | |
405 | est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | | |
406 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); | |
407 | est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | | |
408 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); | |
409 | return; | |
410 | } | |
411 | udelay(10); | |
412 | } | |
413 | memset(est, 0, sizeof(*est)); | |
414 | } | |
415 | ||
a67162ab RM |
416 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ |
417 | static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, | |
418 | struct b43_phy_n_iq_comp *pcomp) | |
419 | { | |
420 | if (write) { | |
421 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); | |
422 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); | |
423 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); | |
424 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); | |
425 | } else { | |
426 | pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); | |
427 | pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); | |
428 | pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); | |
429 | pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); | |
430 | } | |
431 | } | |
432 | ||
026816fc RM |
433 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ |
434 | static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) | |
435 | { | |
436 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
437 | ||
438 | b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); | |
439 | if (core == 0) { | |
440 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); | |
441 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
442 | } else { | |
443 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
444 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
445 | } | |
446 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); | |
447 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); | |
448 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); | |
449 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); | |
450 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); | |
451 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); | |
452 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
453 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
454 | } | |
455 | ||
456 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ | |
457 | static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) | |
458 | { | |
459 | u8 rxval, txval; | |
460 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
461 | ||
462 | regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
463 | if (core == 0) { | |
464 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
465 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
466 | } else { | |
467 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
468 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
469 | } | |
470 | regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
471 | regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
472 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); | |
473 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); | |
474 | regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); | |
475 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); | |
476 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
477 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
478 | ||
479 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
480 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
481 | ||
482 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
483 | ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
484 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
485 | ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); | |
486 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, | |
487 | (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); | |
488 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, | |
489 | (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); | |
490 | ||
491 | if (core == 0) { | |
492 | b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); | |
493 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); | |
494 | } else { | |
495 | b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); | |
496 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); | |
497 | } | |
498 | ||
499 | /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */ | |
500 | /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */ | |
67c0d6e2 | 501 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
026816fc RM |
502 | |
503 | if (core == 0) { | |
504 | rxval = 1; | |
505 | txval = 8; | |
506 | } else { | |
507 | rxval = 4; | |
508 | txval = 2; | |
509 | } | |
510 | ||
511 | /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */ | |
512 | /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */ | |
513 | } | |
514 | ||
34a56f2c RM |
515 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ |
516 | static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) | |
517 | { | |
518 | int i; | |
519 | s32 iq; | |
520 | u32 ii; | |
521 | u32 qq; | |
522 | int iq_nbits, qq_nbits; | |
523 | int arsh, brsh; | |
524 | u16 tmp, a, b; | |
525 | ||
526 | struct nphy_iq_est est; | |
527 | struct b43_phy_n_iq_comp old; | |
528 | struct b43_phy_n_iq_comp new = { }; | |
529 | bool error = false; | |
530 | ||
531 | if (mask == 0) | |
532 | return; | |
533 | ||
534 | b43_nphy_rx_iq_coeffs(dev, false, &old); | |
535 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
536 | b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); | |
537 | new = old; | |
538 | ||
539 | for (i = 0; i < 2; i++) { | |
540 | if (i == 0 && (mask & 1)) { | |
541 | iq = est.iq0_prod; | |
542 | ii = est.i0_pwr; | |
543 | qq = est.q0_pwr; | |
544 | } else if (i == 1 && (mask & 2)) { | |
545 | iq = est.iq1_prod; | |
546 | ii = est.i1_pwr; | |
547 | qq = est.q1_pwr; | |
548 | } else { | |
549 | B43_WARN_ON(1); | |
550 | continue; | |
551 | } | |
552 | ||
553 | if (ii + qq < 2) { | |
554 | error = true; | |
555 | break; | |
556 | } | |
557 | ||
558 | iq_nbits = fls(abs(iq)); | |
559 | qq_nbits = fls(qq); | |
560 | ||
561 | arsh = iq_nbits - 20; | |
562 | if (arsh >= 0) { | |
563 | a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); | |
564 | tmp = ii >> arsh; | |
565 | } else { | |
566 | a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); | |
567 | tmp = ii << -arsh; | |
568 | } | |
569 | if (tmp == 0) { | |
570 | error = true; | |
571 | break; | |
572 | } | |
573 | a /= tmp; | |
574 | ||
575 | brsh = qq_nbits - 11; | |
576 | if (brsh >= 0) { | |
577 | b = (qq << (31 - qq_nbits)); | |
578 | tmp = ii >> brsh; | |
579 | } else { | |
580 | b = (qq << (31 - qq_nbits)); | |
581 | tmp = ii << -brsh; | |
582 | } | |
583 | if (tmp == 0) { | |
584 | error = true; | |
585 | break; | |
586 | } | |
587 | b = int_sqrt(b / tmp - a * a) - (1 << 10); | |
588 | ||
589 | if (i == 0 && (mask & 0x1)) { | |
590 | if (dev->phy.rev >= 3) { | |
591 | new.a0 = a & 0x3FF; | |
592 | new.b0 = b & 0x3FF; | |
593 | } else { | |
594 | new.a0 = b & 0x3FF; | |
595 | new.b0 = a & 0x3FF; | |
596 | } | |
597 | } else if (i == 1 && (mask & 0x2)) { | |
598 | if (dev->phy.rev >= 3) { | |
599 | new.a1 = a & 0x3FF; | |
600 | new.b1 = b & 0x3FF; | |
601 | } else { | |
602 | new.a1 = b & 0x3FF; | |
603 | new.b1 = a & 0x3FF; | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | if (error) | |
609 | new = old; | |
610 | ||
611 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
612 | } | |
613 | ||
09146400 RM |
614 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ |
615 | static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) | |
616 | { | |
617 | u16 array[4]; | |
618 | int i; | |
619 | ||
620 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); | |
621 | for (i = 0; i < 4; i++) | |
622 | array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); | |
623 | ||
624 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); | |
625 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); | |
626 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); | |
627 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); | |
628 | } | |
629 | ||
bbec398c RM |
630 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ |
631 | static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
632 | { | |
633 | b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); | |
634 | b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); | |
635 | } | |
636 | ||
637 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ | |
638 | static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
639 | { | |
640 | clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); | |
641 | clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); | |
642 | } | |
643 | ||
644 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ | |
645 | static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) | |
646 | { | |
647 | u16 tmp; | |
648 | ||
649 | if (dev->dev->id.revision == 16) | |
650 | b43_mac_suspend(dev); | |
651 | ||
652 | tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); | |
653 | tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | | |
654 | B43_NPHY_CLASSCTL_WAITEDEN); | |
655 | tmp &= ~mask; | |
656 | tmp |= (val & mask); | |
657 | b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); | |
658 | ||
659 | if (dev->dev->id.revision == 16) | |
660 | b43_mac_enable(dev); | |
661 | ||
662 | return tmp; | |
663 | } | |
664 | ||
5c1a140a RM |
665 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ |
666 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) | |
667 | { | |
668 | struct b43_phy *phy = &dev->phy; | |
669 | struct b43_phy_n *nphy = phy->n; | |
670 | ||
671 | if (enable) { | |
672 | u16 clip[] = { 0xFFFF, 0xFFFF }; | |
673 | if (nphy->deaf_count++ == 0) { | |
674 | nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); | |
675 | b43_nphy_classifier(dev, 0x7, 0); | |
676 | b43_nphy_read_clip_detection(dev, nphy->clip_state); | |
677 | b43_nphy_write_clip_detection(dev, clip); | |
678 | } | |
679 | b43_nphy_reset_cca(dev); | |
680 | } else { | |
681 | if (--nphy->deaf_count == 0) { | |
682 | b43_nphy_classifier(dev, 0x7, nphy->classifier_state); | |
683 | b43_nphy_write_clip_detection(dev, nphy->clip_state); | |
684 | } | |
685 | } | |
686 | } | |
687 | ||
53ae8e8c RM |
688 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ |
689 | static void b43_nphy_stop_playback(struct b43_wldev *dev) | |
690 | { | |
691 | struct b43_phy_n *nphy = dev->phy.n; | |
692 | u16 tmp; | |
693 | ||
694 | if (nphy->hang_avoid) | |
695 | b43_nphy_stay_in_carrier_search(dev, 1); | |
696 | ||
697 | tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); | |
698 | if (tmp & 0x1) | |
699 | b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); | |
700 | else if (tmp & 0x2) | |
701 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000); | |
702 | ||
703 | b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); | |
704 | ||
705 | if (nphy->bb_mult_save & 0x80000000) { | |
706 | tmp = nphy->bb_mult_save & 0xFFFF; | |
d41a3552 | 707 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); |
53ae8e8c RM |
708 | nphy->bb_mult_save = 0; |
709 | } | |
710 | ||
711 | if (nphy->hang_avoid) | |
712 | b43_nphy_stay_in_carrier_search(dev, 0); | |
713 | } | |
714 | ||
ef5127a4 RM |
715 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ |
716 | static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev) | |
717 | { | |
718 | struct b43_phy_n *nphy = dev->phy.n; | |
719 | u8 i, j; | |
720 | u8 code; | |
721 | ||
722 | /* TODO: for PHY >= 3 | |
723 | s8 *lna1_gain, *lna2_gain; | |
724 | u8 *gain_db, *gain_bits; | |
725 | u16 *rfseq_init; | |
726 | u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; | |
727 | u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; | |
728 | */ | |
729 | ||
730 | u8 rfseq_events[3] = { 6, 8, 7 }; | |
731 | u8 rfseq_delays[3] = { 10, 30, 1 }; | |
732 | ||
733 | if (dev->phy.rev >= 3) { | |
734 | /* TODO */ | |
735 | } else { | |
736 | /* Set Clip 2 detect */ | |
737 | b43_phy_set(dev, B43_NPHY_C1_CGAINI, | |
738 | B43_NPHY_C1_CGAINI_CL2DETECT); | |
739 | b43_phy_set(dev, B43_NPHY_C2_CGAINI, | |
740 | B43_NPHY_C2_CGAINI_CL2DETECT); | |
741 | ||
742 | /* Set narrowband clip threshold */ | |
743 | b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); | |
744 | b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); | |
745 | ||
746 | if (!dev->phy.is_40mhz) { | |
747 | /* Set dwell lengths */ | |
748 | b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); | |
749 | b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); | |
750 | b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); | |
751 | b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); | |
752 | } | |
753 | ||
754 | /* Set wideband clip 2 threshold */ | |
755 | b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, | |
756 | ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, | |
757 | 21); | |
758 | b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, | |
759 | ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, | |
760 | 21); | |
761 | ||
762 | if (!dev->phy.is_40mhz) { | |
763 | b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, | |
764 | ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); | |
765 | b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, | |
766 | ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); | |
767 | b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, | |
768 | ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); | |
769 | b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, | |
770 | ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); | |
771 | } | |
772 | ||
773 | b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); | |
774 | ||
775 | if (nphy->gain_boost) { | |
776 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && | |
777 | dev->phy.is_40mhz) | |
778 | code = 4; | |
779 | else | |
780 | code = 5; | |
781 | } else { | |
782 | code = dev->phy.is_40mhz ? 6 : 7; | |
783 | } | |
784 | ||
785 | /* Set HPVGA2 index */ | |
786 | b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, | |
787 | ~B43_NPHY_C1_INITGAIN_HPVGA2, | |
788 | code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); | |
789 | b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, | |
790 | ~B43_NPHY_C2_INITGAIN_HPVGA2, | |
791 | code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); | |
792 | ||
793 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
794 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
795 | (code << 8 | 0x7C)); | |
796 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
797 | (code << 8 | 0x7C)); | |
798 | ||
799 | /* TODO: b43_nphy_adjust_lna_gain_table(dev); */ | |
800 | ||
801 | if (nphy->elna_gain_config) { | |
802 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); | |
803 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
804 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
805 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
806 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
807 | ||
808 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); | |
809 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
810 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
811 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
812 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
813 | ||
814 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
815 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
816 | (code << 8 | 0x74)); | |
817 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
818 | (code << 8 | 0x74)); | |
819 | } | |
820 | ||
821 | if (dev->phy.rev == 2) { | |
822 | for (i = 0; i < 4; i++) { | |
823 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
824 | (0x0400 * i) + 0x0020); | |
825 | for (j = 0; j < 21; j++) | |
826 | b43_phy_write(dev, | |
827 | B43_NPHY_TABLE_DATALO, 3 * j); | |
828 | } | |
829 | ||
830 | /* TODO: b43_nphy_set_rf_sequence(dev, 5, | |
831 | rfseq_events, rfseq_delays, 3);*/ | |
832 | b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, | |
833 | (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV, | |
834 | 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); | |
835 | ||
836 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
837 | b43_phy_maskset(dev, B43_PHY_N(0xC5D), | |
838 | 0xFF80, 4); | |
839 | } | |
840 | } | |
841 | } | |
842 | ||
28fd7daa RM |
843 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ |
844 | static void b43_nphy_workarounds(struct b43_wldev *dev) | |
845 | { | |
846 | struct ssb_bus *bus = dev->dev->bus; | |
847 | struct b43_phy *phy = &dev->phy; | |
848 | struct b43_phy_n *nphy = phy->n; | |
849 | ||
850 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; | |
851 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | |
852 | ||
853 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; | |
854 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; | |
855 | ||
856 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
857 | b43_nphy_classifier(dev, 1, 0); | |
858 | else | |
859 | b43_nphy_classifier(dev, 1, 1); | |
860 | ||
861 | if (nphy->hang_avoid) | |
862 | b43_nphy_stay_in_carrier_search(dev, 1); | |
863 | ||
864 | b43_phy_set(dev, B43_NPHY_IQFLIP, | |
865 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | |
866 | ||
867 | if (dev->phy.rev >= 3) { | |
868 | /* TODO */ | |
869 | } else { | |
870 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && | |
871 | nphy->band5g_pwrgain) { | |
872 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | |
873 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | |
874 | } else { | |
875 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | |
876 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | |
877 | } | |
878 | ||
879 | /* TODO: convert to b43_ntab_write? */ | |
880 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); | |
881 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
882 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); | |
883 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
884 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); | |
885 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
886 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); | |
887 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
888 | ||
889 | if (dev->phy.rev < 2) { | |
890 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); | |
891 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
892 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); | |
893 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
894 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); | |
895 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
896 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); | |
897 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
898 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); | |
899 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
900 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); | |
901 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
902 | } | |
903 | ||
904 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | |
905 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | |
906 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | |
907 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | |
908 | ||
909 | if (bus->sprom.boardflags2_lo & 0x100 && | |
910 | bus->boardinfo.type == 0x8B) { | |
911 | delays1[0] = 0x1; | |
912 | delays1[5] = 0x14; | |
913 | } | |
914 | /*TODO:b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);*/ | |
915 | /*TODO:b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);*/ | |
916 | ||
ef5127a4 | 917 | b43_nphy_gain_crtl_workarounds(dev); |
28fd7daa RM |
918 | |
919 | if (dev->phy.rev < 2) { | |
920 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) | |
921 | ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/ | |
922 | } else if (dev->phy.rev == 2) { | |
923 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); | |
924 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); | |
925 | } | |
926 | ||
927 | if (dev->phy.rev < 2) | |
928 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | |
929 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | |
930 | ||
931 | /* Set phase track alpha and beta */ | |
932 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | |
933 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | |
934 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | |
935 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | |
936 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | |
937 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | |
938 | ||
939 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | |
940 | (u16)~B43_NPHY_PIL_DW_64QAM); | |
941 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | |
942 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | |
943 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | |
944 | ||
945 | if (dev->phy.rev == 2) | |
946 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | |
947 | B43_NPHY_FINERX2_CGC_DECGC); | |
948 | } | |
949 | ||
950 | if (nphy->hang_avoid) | |
951 | b43_nphy_stay_in_carrier_search(dev, 0); | |
952 | } | |
953 | ||
59af099b RM |
954 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ |
955 | static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, | |
956 | bool test) | |
957 | { | |
958 | int i; | |
f2982181 | 959 | u16 bw, len, rot, angle; |
da860475 | 960 | struct b43_c32 *samples; |
f2982181 | 961 | |
59af099b RM |
962 | |
963 | bw = (dev->phy.is_40mhz) ? 40 : 20; | |
964 | len = bw << 3; | |
965 | ||
966 | if (test) { | |
967 | if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) | |
968 | bw = 82; | |
969 | else | |
970 | bw = 80; | |
971 | ||
972 | if (dev->phy.is_40mhz) | |
973 | bw <<= 1; | |
974 | ||
975 | len = bw << 1; | |
976 | } | |
977 | ||
da860475 | 978 | samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL); |
59af099b RM |
979 | rot = (((freq * 36) / bw) << 16) / 100; |
980 | angle = 0; | |
981 | ||
f2982181 RM |
982 | for (i = 0; i < len; i++) { |
983 | samples[i] = b43_cordic(angle); | |
984 | angle += rot; | |
985 | samples[i].q = CORDIC_CONVERT(samples[i].q * max); | |
986 | samples[i].i = CORDIC_CONVERT(samples[i].i * max); | |
59af099b RM |
987 | } |
988 | ||
f2982181 RM |
989 | /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */ |
990 | kfree(samples); | |
991 | return len; | |
59af099b RM |
992 | } |
993 | ||
10a79873 RM |
994 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ |
995 | static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, | |
996 | u16 wait, bool iqmode, bool dac_test) | |
997 | { | |
998 | struct b43_phy_n *nphy = dev->phy.n; | |
999 | int i; | |
1000 | u16 seq_mode; | |
1001 | u32 tmp; | |
1002 | ||
1003 | if (nphy->hang_avoid) | |
1004 | b43_nphy_stay_in_carrier_search(dev, true); | |
1005 | ||
1006 | if ((nphy->bb_mult_save & 0x80000000) == 0) { | |
1007 | tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); | |
1008 | nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; | |
1009 | } | |
1010 | ||
1011 | if (!dev->phy.is_40mhz) | |
1012 | tmp = 0x6464; | |
1013 | else | |
1014 | tmp = 0x4747; | |
1015 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); | |
1016 | ||
1017 | if (nphy->hang_avoid) | |
1018 | b43_nphy_stay_in_carrier_search(dev, false); | |
1019 | ||
1020 | b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); | |
1021 | ||
1022 | if (loops != 0xFFFF) | |
1023 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); | |
1024 | else | |
1025 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); | |
1026 | ||
1027 | b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); | |
1028 | ||
1029 | seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); | |
1030 | ||
1031 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); | |
1032 | if (iqmode) { | |
1033 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); | |
1034 | b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); | |
1035 | } else { | |
1036 | if (dac_test) | |
1037 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); | |
1038 | else | |
1039 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); | |
1040 | } | |
1041 | for (i = 0; i < 100; i++) { | |
1042 | if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { | |
1043 | i = 0; | |
1044 | break; | |
1045 | } | |
1046 | udelay(10); | |
1047 | } | |
1048 | if (i) | |
1049 | b43err(dev->wl, "run samples timeout\n"); | |
1050 | ||
1051 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); | |
1052 | } | |
1053 | ||
59af099b RM |
1054 | /* |
1055 | * Transmits a known value for LO calibration | |
1056 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone | |
1057 | */ | |
1058 | static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, | |
1059 | bool iqmode, bool dac_test) | |
1060 | { | |
1061 | u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); | |
1062 | if (samp == 0) | |
1063 | return -1; | |
1064 | b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); | |
1065 | return 0; | |
1066 | } | |
1067 | ||
6dcd9d91 RM |
1068 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ |
1069 | static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) | |
1070 | { | |
1071 | struct b43_phy_n *nphy = dev->phy.n; | |
1072 | int i, j; | |
1073 | u32 tmp; | |
1074 | u32 cur_real, cur_imag, real_part, imag_part; | |
1075 | ||
1076 | u16 buffer[7]; | |
1077 | ||
1078 | if (nphy->hang_avoid) | |
1079 | b43_nphy_stay_in_carrier_search(dev, true); | |
1080 | ||
9145834e | 1081 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); |
6dcd9d91 RM |
1082 | |
1083 | for (i = 0; i < 2; i++) { | |
1084 | tmp = ((buffer[i * 2] & 0x3FF) << 10) | | |
1085 | (buffer[i * 2 + 1] & 0x3FF); | |
1086 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1087 | (((i + 26) << 10) | 320)); | |
1088 | for (j = 0; j < 128; j++) { | |
1089 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1090 | ((tmp >> 16) & 0xFFFF)); | |
1091 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1092 | (tmp & 0xFFFF)); | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | for (i = 0; i < 2; i++) { | |
1097 | tmp = buffer[5 + i]; | |
1098 | real_part = (tmp >> 8) & 0xFF; | |
1099 | imag_part = (tmp & 0xFF); | |
1100 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1101 | (((i + 26) << 10) | 448)); | |
1102 | ||
1103 | if (dev->phy.rev >= 3) { | |
1104 | cur_real = real_part; | |
1105 | cur_imag = imag_part; | |
1106 | tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); | |
1107 | } | |
1108 | ||
1109 | for (j = 0; j < 128; j++) { | |
1110 | if (dev->phy.rev < 3) { | |
1111 | cur_real = (real_part * loscale[j] + 128) >> 8; | |
1112 | cur_imag = (imag_part * loscale[j] + 128) >> 8; | |
1113 | tmp = ((cur_real & 0xFF) << 8) | | |
1114 | (cur_imag & 0xFF); | |
1115 | } | |
1116 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1117 | ((tmp >> 16) & 0xFFFF)); | |
1118 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1119 | (tmp & 0xFFFF)); | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | if (dev->phy.rev >= 3) { | |
1124 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1125 | B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); | |
1126 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1127 | B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); | |
1128 | } | |
1129 | ||
1130 | if (nphy->hang_avoid) | |
1131 | b43_nphy_stay_in_carrier_search(dev, false); | |
1132 | } | |
1133 | ||
67c0d6e2 | 1134 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ |
95b66bad MB |
1135 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, |
1136 | enum b43_nphy_rf_sequence seq) | |
1137 | { | |
1138 | static const u16 trigger[] = { | |
1139 | [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, | |
1140 | [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, | |
1141 | [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, | |
1142 | [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, | |
1143 | [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, | |
1144 | [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, | |
1145 | }; | |
1146 | int i; | |
c57199bc | 1147 | u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); |
95b66bad MB |
1148 | |
1149 | B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); | |
1150 | ||
1151 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
1152 | B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); | |
1153 | b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); | |
1154 | for (i = 0; i < 200; i++) { | |
1155 | if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) | |
1156 | goto ok; | |
1157 | msleep(1); | |
1158 | } | |
1159 | b43err(dev->wl, "RF sequence status timeout\n"); | |
1160 | ok: | |
c57199bc | 1161 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); |
95b66bad MB |
1162 | } |
1163 | ||
75377b24 RM |
1164 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ |
1165 | static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, | |
1166 | u16 value, u8 core, bool off) | |
1167 | { | |
1168 | int i; | |
1169 | u8 index = fls(field); | |
1170 | u8 addr, en_addr, val_addr; | |
1171 | /* we expect only one bit set */ | |
3ed0fac3 | 1172 | B43_WARN_ON(field & (~(1 << (index - 1)))); |
75377b24 RM |
1173 | |
1174 | if (dev->phy.rev >= 3) { | |
1175 | const struct nphy_rf_control_override_rev3 *rf_ctrl; | |
1176 | for (i = 0; i < 2; i++) { | |
1177 | if (index == 0 || index == 16) { | |
1178 | b43err(dev->wl, | |
1179 | "Unsupported RF Ctrl Override call\n"); | |
1180 | return; | |
1181 | } | |
1182 | ||
1183 | rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; | |
1184 | en_addr = B43_PHY_N((i == 0) ? | |
1185 | rf_ctrl->en_addr0 : rf_ctrl->en_addr1); | |
1186 | val_addr = B43_PHY_N((i == 0) ? | |
1187 | rf_ctrl->val_addr0 : rf_ctrl->val_addr1); | |
1188 | ||
1189 | if (off) { | |
1190 | b43_phy_mask(dev, en_addr, ~(field)); | |
1191 | b43_phy_mask(dev, val_addr, | |
1192 | ~(rf_ctrl->val_mask)); | |
1193 | } else { | |
1194 | if (core == 0 || ((1 << core) & i) != 0) { | |
1195 | b43_phy_set(dev, en_addr, field); | |
1196 | b43_phy_maskset(dev, val_addr, | |
1197 | ~(rf_ctrl->val_mask), | |
1198 | (value << rf_ctrl->val_shift)); | |
1199 | } | |
1200 | } | |
1201 | } | |
1202 | } else { | |
1203 | const struct nphy_rf_control_override_rev2 *rf_ctrl; | |
1204 | if (off) { | |
1205 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); | |
1206 | value = 0; | |
1207 | } else { | |
1208 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); | |
1209 | } | |
1210 | ||
1211 | for (i = 0; i < 2; i++) { | |
1212 | if (index <= 1 || index == 16) { | |
1213 | b43err(dev->wl, | |
1214 | "Unsupported RF Ctrl Override call\n"); | |
1215 | return; | |
1216 | } | |
1217 | ||
1218 | if (index == 2 || index == 10 || | |
1219 | (index >= 13 && index <= 15)) { | |
1220 | core = 1; | |
1221 | } | |
1222 | ||
1223 | rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; | |
1224 | addr = B43_PHY_N((i == 0) ? | |
1225 | rf_ctrl->addr0 : rf_ctrl->addr1); | |
1226 | ||
1227 | if ((core & (1 << i)) != 0) | |
1228 | b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), | |
1229 | (value << rf_ctrl->shift)); | |
1230 | ||
1231 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); | |
1232 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1233 | B43_NPHY_RFCTL_CMD_START); | |
1234 | udelay(1); | |
1235 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | ||
95b66bad MB |
1240 | static void b43_nphy_bphy_init(struct b43_wldev *dev) |
1241 | { | |
1242 | unsigned int i; | |
1243 | u16 val; | |
1244 | ||
1245 | val = 0x1E1F; | |
1246 | for (i = 0; i < 14; i++) { | |
1247 | b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); | |
1248 | val -= 0x202; | |
1249 | } | |
1250 | val = 0x3E3F; | |
1251 | for (i = 0; i < 16; i++) { | |
1252 | b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val); | |
1253 | val -= 0x202; | |
1254 | } | |
1255 | b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); | |
1256 | } | |
1257 | ||
3c95627d RM |
1258 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ |
1259 | static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |
1260 | s8 offset, u8 core, u8 rail, u8 type) | |
1261 | { | |
1262 | u16 tmp; | |
1263 | bool core1or5 = (core == 1) || (core == 5); | |
1264 | bool core2or5 = (core == 2) || (core == 5); | |
1265 | ||
1266 | offset = clamp_val(offset, -32, 31); | |
1267 | tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); | |
1268 | ||
1269 | if (core1or5 && (rail == 0) && (type == 2)) | |
1270 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); | |
1271 | if (core1or5 && (rail == 1) && (type == 2)) | |
1272 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); | |
1273 | if (core2or5 && (rail == 0) && (type == 2)) | |
1274 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); | |
1275 | if (core2or5 && (rail == 1) && (type == 2)) | |
1276 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); | |
1277 | if (core1or5 && (rail == 0) && (type == 0)) | |
1278 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); | |
1279 | if (core1or5 && (rail == 1) && (type == 0)) | |
1280 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); | |
1281 | if (core2or5 && (rail == 0) && (type == 0)) | |
1282 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); | |
1283 | if (core2or5 && (rail == 1) && (type == 0)) | |
1284 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); | |
1285 | if (core1or5 && (rail == 0) && (type == 1)) | |
1286 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); | |
1287 | if (core1or5 && (rail == 1) && (type == 1)) | |
1288 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); | |
1289 | if (core2or5 && (rail == 0) && (type == 1)) | |
1290 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); | |
1291 | if (core2or5 && (rail == 1) && (type == 1)) | |
1292 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); | |
1293 | if (core1or5 && (rail == 0) && (type == 6)) | |
1294 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); | |
1295 | if (core1or5 && (rail == 1) && (type == 6)) | |
1296 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); | |
1297 | if (core2or5 && (rail == 0) && (type == 6)) | |
1298 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); | |
1299 | if (core2or5 && (rail == 1) && (type == 6)) | |
1300 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); | |
1301 | if (core1or5 && (rail == 0) && (type == 3)) | |
1302 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); | |
1303 | if (core1or5 && (rail == 1) && (type == 3)) | |
1304 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); | |
1305 | if (core2or5 && (rail == 0) && (type == 3)) | |
1306 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); | |
1307 | if (core2or5 && (rail == 1) && (type == 3)) | |
1308 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); | |
1309 | if (core1or5 && (type == 4)) | |
1310 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); | |
1311 | if (core2or5 && (type == 4)) | |
1312 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); | |
1313 | if (core1or5 && (type == 5)) | |
1314 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); | |
1315 | if (core2or5 && (type == 5)) | |
1316 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); | |
1317 | } | |
1318 | ||
1319 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ | |
1320 | static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | |
1321 | { | |
1322 | u16 val; | |
1323 | ||
1324 | if (dev->phy.rev >= 3) { | |
1325 | /* TODO */ | |
1326 | } else { | |
1327 | if (type < 3) | |
1328 | val = 0; | |
1329 | else if (type == 6) | |
1330 | val = 1; | |
1331 | else if (type == 3) | |
1332 | val = 2; | |
1333 | else | |
1334 | val = 3; | |
1335 | ||
1336 | val = (val << 12) | (val << 14); | |
1337 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); | |
1338 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); | |
1339 | ||
1340 | if (type < 3) { | |
1341 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, | |
1342 | (type + 1) << 4); | |
1343 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, | |
1344 | (type + 1) << 4); | |
1345 | } | |
1346 | ||
1347 | /* TODO use some definitions */ | |
1348 | if (code == 0) { | |
1349 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0); | |
1350 | if (type < 3) { | |
1351 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1352 | 0xFEC7, 0); | |
1353 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1354 | 0xEFDC, 0); | |
1355 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1356 | 0xFFFE, 0); | |
1357 | udelay(20); | |
1358 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1359 | 0xFFFE, 0); | |
1360 | } | |
1361 | } else { | |
1362 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, | |
1363 | 0x3000); | |
1364 | if (type < 3) { | |
1365 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1366 | 0xFEC7, 0x0180); | |
1367 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1368 | 0xEFDC, (code << 1 | 0x1021)); | |
1369 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1370 | 0xFFFE, 0x0001); | |
1371 | udelay(20); | |
1372 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1373 | 0xFFFE, 0); | |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
dfb4aa5d RM |
1379 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ |
1380 | static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) | |
1381 | { | |
1382 | int i; | |
1383 | for (i = 0; i < 2; i++) { | |
1384 | if (type == 2) { | |
1385 | if (i == 0) { | |
1386 | b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, | |
1387 | 0xFC, buf[0]); | |
1388 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1389 | 0xFC, buf[1]); | |
1390 | } else { | |
1391 | b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, | |
1392 | 0xFC, buf[2 * i]); | |
1393 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1394 | 0xFC, buf[2 * i + 1]); | |
1395 | } | |
1396 | } else { | |
1397 | if (i == 0) | |
1398 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1399 | 0xF3, buf[0] << 2); | |
1400 | else | |
1401 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1402 | 0xF3, buf[2 * i + 1] << 2); | |
1403 | } | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ | |
1408 | static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, | |
1409 | u8 nsamp) | |
1410 | { | |
1411 | int i; | |
1412 | int out; | |
1413 | u16 save_regs_phy[9]; | |
1414 | u16 s[2]; | |
1415 | ||
1416 | if (dev->phy.rev >= 3) { | |
1417 | save_regs_phy[0] = b43_phy_read(dev, | |
1418 | B43_NPHY_RFCTL_LUT_TRSW_UP1); | |
1419 | save_regs_phy[1] = b43_phy_read(dev, | |
1420 | B43_NPHY_RFCTL_LUT_TRSW_UP2); | |
1421 | save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
1422 | save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
1423 | save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
1424 | save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
1425 | save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); | |
1426 | save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); | |
1427 | } | |
1428 | ||
1429 | b43_nphy_rssi_select(dev, 5, type); | |
1430 | ||
1431 | if (dev->phy.rev < 2) { | |
1432 | save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); | |
1433 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); | |
1434 | } | |
1435 | ||
1436 | for (i = 0; i < 4; i++) | |
1437 | buf[i] = 0; | |
1438 | ||
1439 | for (i = 0; i < nsamp; i++) { | |
1440 | if (dev->phy.rev < 2) { | |
1441 | s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); | |
1442 | s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); | |
1443 | } else { | |
1444 | s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); | |
1445 | s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); | |
1446 | } | |
1447 | ||
1448 | buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; | |
1449 | buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; | |
1450 | buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; | |
1451 | buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; | |
1452 | } | |
1453 | out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | | |
1454 | (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); | |
1455 | ||
1456 | if (dev->phy.rev < 2) | |
1457 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); | |
1458 | ||
1459 | if (dev->phy.rev >= 3) { | |
1460 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, | |
1461 | save_regs_phy[0]); | |
1462 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, | |
1463 | save_regs_phy[1]); | |
1464 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); | |
1465 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); | |
1466 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); | |
1467 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); | |
1468 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); | |
1469 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); | |
1470 | } | |
1471 | ||
1472 | return out; | |
1473 | } | |
1474 | ||
4cb99775 RM |
1475 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ |
1476 | static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) | |
95b66bad | 1477 | { |
90b9738d RM |
1478 | int i, j; |
1479 | u8 state[4]; | |
1480 | u8 code, val; | |
1481 | u16 class, override; | |
1482 | u8 regs_save_radio[2]; | |
1483 | u16 regs_save_phy[2]; | |
1484 | s8 offset[4]; | |
1485 | ||
1486 | u16 clip_state[2]; | |
1487 | u16 clip_off[2] = { 0xFFFF, 0xFFFF }; | |
1488 | s32 results_min[4] = { }; | |
1489 | u8 vcm_final[4] = { }; | |
1490 | s32 results[4][4] = { }; | |
1491 | s32 miniq[4][2] = { }; | |
1492 | ||
1493 | if (type == 2) { | |
1494 | code = 0; | |
1495 | val = 6; | |
1496 | } else if (type < 2) { | |
1497 | code = 25; | |
1498 | val = 4; | |
1499 | } else { | |
1500 | B43_WARN_ON(1); | |
1501 | return; | |
1502 | } | |
1503 | ||
1504 | class = b43_nphy_classifier(dev, 0, 0); | |
1505 | b43_nphy_classifier(dev, 7, 4); | |
1506 | b43_nphy_read_clip_detection(dev, clip_state); | |
1507 | b43_nphy_write_clip_detection(dev, clip_off); | |
1508 | ||
1509 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
1510 | override = 0x140; | |
1511 | else | |
1512 | override = 0x110; | |
1513 | ||
1514 | regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
1515 | regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); | |
1516 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); | |
1517 | b43_radio_write16(dev, B2055_C1_PD_RXTX, val); | |
1518 | ||
1519 | regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
1520 | regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); | |
1521 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); | |
1522 | b43_radio_write16(dev, B2055_C2_PD_RXTX, val); | |
1523 | ||
1524 | state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; | |
1525 | state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; | |
1526 | b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); | |
1527 | b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); | |
1528 | state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; | |
1529 | state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; | |
1530 | ||
1531 | b43_nphy_rssi_select(dev, 5, type); | |
1532 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); | |
1533 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); | |
1534 | ||
1535 | for (i = 0; i < 4; i++) { | |
1536 | u8 tmp[4]; | |
1537 | for (j = 0; j < 4; j++) | |
1538 | tmp[j] = i; | |
1539 | if (type != 1) | |
1540 | b43_nphy_set_rssi_2055_vcm(dev, type, tmp); | |
1541 | b43_nphy_poll_rssi(dev, type, results[i], 8); | |
1542 | if (type < 2) | |
1543 | for (j = 0; j < 2; j++) | |
1544 | miniq[i][j] = min(results[i][2 * j], | |
1545 | results[i][2 * j + 1]); | |
1546 | } | |
1547 | ||
1548 | for (i = 0; i < 4; i++) { | |
1549 | s32 mind = 40; | |
1550 | u8 minvcm = 0; | |
1551 | s32 minpoll = 249; | |
1552 | s32 curr; | |
1553 | for (j = 0; j < 4; j++) { | |
1554 | if (type == 2) | |
1555 | curr = abs(results[j][i]); | |
1556 | else | |
1557 | curr = abs(miniq[j][i / 2] - code * 8); | |
1558 | ||
1559 | if (curr < mind) { | |
1560 | mind = curr; | |
1561 | minvcm = j; | |
1562 | } | |
1563 | ||
1564 | if (results[j][i] < minpoll) | |
1565 | minpoll = results[j][i]; | |
1566 | } | |
1567 | results_min[i] = minpoll; | |
1568 | vcm_final[i] = minvcm; | |
1569 | } | |
1570 | ||
1571 | if (type != 1) | |
1572 | b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); | |
1573 | ||
1574 | for (i = 0; i < 4; i++) { | |
1575 | offset[i] = (code * 8) - results[vcm_final[i]][i]; | |
1576 | ||
1577 | if (offset[i] < 0) | |
1578 | offset[i] = -((abs(offset[i]) + 4) / 8); | |
1579 | else | |
1580 | offset[i] = (offset[i] + 4) / 8; | |
1581 | ||
1582 | if (results_min[i] == 248) | |
1583 | offset[i] = code - 32; | |
1584 | ||
1585 | if (i % 2 == 0) | |
1586 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0, | |
1587 | type); | |
1588 | else | |
1589 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1, | |
1590 | type); | |
1591 | } | |
1592 | ||
1593 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); | |
1594 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]); | |
1595 | ||
1596 | switch (state[2]) { | |
1597 | case 1: | |
1598 | b43_nphy_rssi_select(dev, 1, 2); | |
1599 | break; | |
1600 | case 4: | |
1601 | b43_nphy_rssi_select(dev, 1, 0); | |
1602 | break; | |
1603 | case 2: | |
1604 | b43_nphy_rssi_select(dev, 1, 1); | |
1605 | break; | |
1606 | default: | |
1607 | b43_nphy_rssi_select(dev, 1, 1); | |
1608 | break; | |
1609 | } | |
1610 | ||
1611 | switch (state[3]) { | |
1612 | case 1: | |
1613 | b43_nphy_rssi_select(dev, 2, 2); | |
1614 | break; | |
1615 | case 4: | |
1616 | b43_nphy_rssi_select(dev, 2, 0); | |
1617 | break; | |
1618 | default: | |
1619 | b43_nphy_rssi_select(dev, 2, 1); | |
1620 | break; | |
1621 | } | |
1622 | ||
1623 | b43_nphy_rssi_select(dev, 0, type); | |
1624 | ||
1625 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); | |
1626 | b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); | |
1627 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); | |
1628 | b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); | |
1629 | ||
1630 | b43_nphy_classifier(dev, 7, class); | |
1631 | b43_nphy_write_clip_detection(dev, clip_state); | |
4cb99775 RM |
1632 | } |
1633 | ||
1634 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ | |
1635 | static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) | |
1636 | { | |
1637 | /* TODO */ | |
1638 | } | |
1639 | ||
1640 | /* | |
1641 | * RSSI Calibration | |
1642 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal | |
1643 | */ | |
1644 | static void b43_nphy_rssi_cal(struct b43_wldev *dev) | |
1645 | { | |
1646 | if (dev->phy.rev >= 3) { | |
1647 | b43_nphy_rev3_rssi_cal(dev); | |
1648 | } else { | |
1649 | b43_nphy_rev2_rssi_cal(dev, 2); | |
1650 | b43_nphy_rev2_rssi_cal(dev, 0); | |
1651 | b43_nphy_rev2_rssi_cal(dev, 1); | |
1652 | } | |
95b66bad MB |
1653 | } |
1654 | ||
42e1547e RM |
1655 | /* |
1656 | * Restore RSSI Calibration | |
1657 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal | |
1658 | */ | |
1659 | static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) | |
1660 | { | |
1661 | struct b43_phy_n *nphy = dev->phy.n; | |
1662 | ||
1663 | u16 *rssical_radio_regs = NULL; | |
1664 | u16 *rssical_phy_regs = NULL; | |
1665 | ||
1666 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
1667 | if (!nphy->rssical_chanspec_2G) | |
1668 | return; | |
1669 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; | |
1670 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; | |
1671 | } else { | |
1672 | if (!nphy->rssical_chanspec_5G) | |
1673 | return; | |
1674 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; | |
1675 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; | |
1676 | } | |
1677 | ||
1678 | /* TODO use some definitions */ | |
1679 | b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); | |
1680 | b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); | |
1681 | ||
1682 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); | |
1683 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); | |
1684 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); | |
1685 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); | |
1686 | ||
1687 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); | |
1688 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); | |
1689 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); | |
1690 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); | |
1691 | ||
1692 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); | |
1693 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); | |
1694 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); | |
1695 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); | |
1696 | } | |
1697 | ||
2f258b74 RM |
1698 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ |
1699 | static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) | |
1700 | { | |
1701 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
1702 | if (dev->phy.rev >= 6) { | |
1703 | /* TODO If the chip is 47162 | |
1704 | return txpwrctrl_tx_gain_ipa_rev5 */ | |
1705 | return txpwrctrl_tx_gain_ipa_rev6; | |
1706 | } else if (dev->phy.rev >= 5) { | |
1707 | return txpwrctrl_tx_gain_ipa_rev5; | |
1708 | } else { | |
1709 | return txpwrctrl_tx_gain_ipa; | |
1710 | } | |
1711 | } else { | |
1712 | return txpwrctrl_tx_gain_ipa_5g; | |
1713 | } | |
1714 | } | |
1715 | ||
c4a92003 RM |
1716 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ |
1717 | static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) | |
1718 | { | |
1719 | struct b43_phy_n *nphy = dev->phy.n; | |
1720 | u16 *save = nphy->tx_rx_cal_radio_saveregs; | |
1721 | ||
1722 | if (dev->phy.rev >= 3) { | |
1723 | /* TODO */ | |
1724 | } else { | |
1725 | save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); | |
1726 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); | |
1727 | ||
1728 | save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); | |
1729 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); | |
1730 | ||
1731 | save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); | |
1732 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); | |
1733 | ||
1734 | save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); | |
1735 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); | |
1736 | ||
1737 | save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); | |
1738 | save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); | |
1739 | ||
1740 | if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & | |
1741 | B43_NPHY_BANDCTL_5GHZ)) { | |
1742 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); | |
1743 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); | |
1744 | } else { | |
1745 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); | |
1746 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); | |
1747 | } | |
1748 | ||
1749 | if (dev->phy.rev < 2) { | |
1750 | b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); | |
1751 | b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); | |
1752 | } else { | |
1753 | b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); | |
1754 | b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); | |
1755 | } | |
1756 | } | |
1757 | } | |
1758 | ||
e9762492 RM |
1759 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ |
1760 | static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, | |
1761 | struct nphy_txgains target, | |
1762 | struct nphy_iqcal_params *params) | |
1763 | { | |
1764 | int i, j, indx; | |
1765 | u16 gain; | |
1766 | ||
1767 | if (dev->phy.rev >= 3) { | |
1768 | params->txgm = target.txgm[core]; | |
1769 | params->pga = target.pga[core]; | |
1770 | params->pad = target.pad[core]; | |
1771 | params->ipa = target.ipa[core]; | |
1772 | params->cal_gain = (params->txgm << 12) | (params->pga << 8) | | |
1773 | (params->pad << 4) | (params->ipa); | |
1774 | for (j = 0; j < 5; j++) | |
1775 | params->ncorr[j] = 0x79; | |
1776 | } else { | |
1777 | gain = (target.pad[core]) | (target.pga[core] << 4) | | |
1778 | (target.txgm[core] << 8); | |
1779 | ||
1780 | indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? | |
1781 | 1 : 0; | |
1782 | for (i = 0; i < 9; i++) | |
1783 | if (tbl_iqcal_gainparams[indx][i][0] == gain) | |
1784 | break; | |
1785 | i = min(i, 8); | |
1786 | ||
1787 | params->txgm = tbl_iqcal_gainparams[indx][i][1]; | |
1788 | params->pga = tbl_iqcal_gainparams[indx][i][2]; | |
1789 | params->pad = tbl_iqcal_gainparams[indx][i][3]; | |
1790 | params->cal_gain = (params->txgm << 7) | (params->pga << 4) | | |
1791 | (params->pad << 2); | |
1792 | for (j = 0; j < 4; j++) | |
1793 | params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; | |
1794 | } | |
1795 | } | |
1796 | ||
de7ed0c6 RM |
1797 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ |
1798 | static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) | |
1799 | { | |
1800 | struct b43_phy_n *nphy = dev->phy.n; | |
1801 | int i; | |
1802 | u16 scale, entry; | |
1803 | ||
1804 | u16 tmp = nphy->txcal_bbmult; | |
1805 | if (core == 0) | |
1806 | tmp >>= 8; | |
1807 | tmp &= 0xff; | |
1808 | ||
1809 | for (i = 0; i < 18; i++) { | |
1810 | scale = (ladder_lo[i].percent * tmp) / 100; | |
1811 | entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; | |
d41a3552 | 1812 | b43_ntab_write(dev, B43_NTAB16(15, i), entry); |
de7ed0c6 RM |
1813 | |
1814 | scale = (ladder_iq[i].percent * tmp) / 100; | |
1815 | entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; | |
d41a3552 | 1816 | b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); |
de7ed0c6 RM |
1817 | } |
1818 | } | |
1819 | ||
45ca697e RM |
1820 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ |
1821 | static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
1822 | { | |
1823 | int i; | |
1824 | for (i = 0; i < 15; i++) | |
1825 | b43_phy_write(dev, B43_PHY_N(0x2C5 + i), | |
1826 | tbl_tx_filter_coef_rev4[2][i]); | |
1827 | } | |
1828 | ||
1829 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ | |
1830 | static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
1831 | { | |
1832 | int i, j; | |
1833 | /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ | |
1834 | u16 offset[] = { 0x186, 0x195, 0x2C5 }; | |
1835 | ||
1836 | for (i = 0; i < 3; i++) | |
1837 | for (j = 0; j < 15; j++) | |
1838 | b43_phy_write(dev, B43_PHY_N(offset[i] + j), | |
1839 | tbl_tx_filter_coef_rev4[i][j]); | |
1840 | ||
1841 | if (dev->phy.is_40mhz) { | |
1842 | for (j = 0; j < 15; j++) | |
1843 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
1844 | tbl_tx_filter_coef_rev4[3][j]); | |
1845 | } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1846 | for (j = 0; j < 15; j++) | |
1847 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
1848 | tbl_tx_filter_coef_rev4[5][j]); | |
1849 | } | |
1850 | ||
1851 | if (dev->phy.channel == 14) | |
1852 | for (j = 0; j < 15; j++) | |
1853 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
1854 | tbl_tx_filter_coef_rev4[6][j]); | |
1855 | } | |
1856 | ||
b0022e15 RM |
1857 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ |
1858 | static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) | |
1859 | { | |
1860 | struct b43_phy_n *nphy = dev->phy.n; | |
1861 | ||
1862 | u16 curr_gain[2]; | |
1863 | struct nphy_txgains target; | |
1864 | const u32 *table = NULL; | |
1865 | ||
1866 | if (nphy->txpwrctrl == 0) { | |
1867 | int i; | |
1868 | ||
1869 | if (nphy->hang_avoid) | |
1870 | b43_nphy_stay_in_carrier_search(dev, true); | |
9145834e | 1871 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); |
b0022e15 RM |
1872 | if (nphy->hang_avoid) |
1873 | b43_nphy_stay_in_carrier_search(dev, false); | |
1874 | ||
1875 | for (i = 0; i < 2; ++i) { | |
1876 | if (dev->phy.rev >= 3) { | |
1877 | target.ipa[i] = curr_gain[i] & 0x000F; | |
1878 | target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; | |
1879 | target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; | |
1880 | target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; | |
1881 | } else { | |
1882 | target.ipa[i] = curr_gain[i] & 0x0003; | |
1883 | target.pad[i] = (curr_gain[i] & 0x000C) >> 2; | |
1884 | target.pga[i] = (curr_gain[i] & 0x0070) >> 4; | |
1885 | target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; | |
1886 | } | |
1887 | } | |
1888 | } else { | |
1889 | int i; | |
1890 | u16 index[2]; | |
1891 | index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & | |
1892 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
1893 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
1894 | index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & | |
1895 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
1896 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
1897 | ||
1898 | for (i = 0; i < 2; ++i) { | |
1899 | if (dev->phy.rev >= 3) { | |
1900 | enum ieee80211_band band = | |
1901 | b43_current_band(dev->wl); | |
1902 | ||
1903 | if ((nphy->ipa2g_on && | |
1904 | band == IEEE80211_BAND_2GHZ) || | |
1905 | (nphy->ipa5g_on && | |
1906 | band == IEEE80211_BAND_5GHZ)) { | |
1907 | table = b43_nphy_get_ipa_gain_table(dev); | |
1908 | } else { | |
1909 | if (band == IEEE80211_BAND_5GHZ) { | |
1910 | if (dev->phy.rev == 3) | |
1911 | table = b43_ntab_tx_gain_rev3_5ghz; | |
1912 | else if (dev->phy.rev == 4) | |
1913 | table = b43_ntab_tx_gain_rev4_5ghz; | |
1914 | else | |
1915 | table = b43_ntab_tx_gain_rev5plus_5ghz; | |
1916 | } else { | |
1917 | table = b43_ntab_tx_gain_rev3plus_2ghz; | |
1918 | } | |
1919 | } | |
1920 | ||
1921 | target.ipa[i] = (table[index[i]] >> 16) & 0xF; | |
1922 | target.pad[i] = (table[index[i]] >> 20) & 0xF; | |
1923 | target.pga[i] = (table[index[i]] >> 24) & 0xF; | |
1924 | target.txgm[i] = (table[index[i]] >> 28) & 0xF; | |
1925 | } else { | |
1926 | table = b43_ntab_tx_gain_rev0_1_2; | |
1927 | ||
1928 | target.ipa[i] = (table[index[i]] >> 16) & 0x3; | |
1929 | target.pad[i] = (table[index[i]] >> 18) & 0x3; | |
1930 | target.pga[i] = (table[index[i]] >> 20) & 0x7; | |
1931 | target.txgm[i] = (table[index[i]] >> 23) & 0x7; | |
1932 | } | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | return target; | |
1937 | } | |
1938 | ||
e53de674 RM |
1939 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ |
1940 | static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) | |
1941 | { | |
1942 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
1943 | ||
1944 | if (dev->phy.rev >= 3) { | |
1945 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); | |
1946 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
1947 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
1948 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); | |
1949 | b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); | |
d41a3552 RM |
1950 | b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); |
1951 | b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); | |
e53de674 RM |
1952 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); |
1953 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); | |
1954 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
1955 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
1956 | b43_nphy_reset_cca(dev); | |
1957 | } else { | |
1958 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); | |
1959 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); | |
1960 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
d41a3552 RM |
1961 | b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); |
1962 | b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); | |
e53de674 RM |
1963 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); |
1964 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); | |
1965 | } | |
1966 | } | |
1967 | ||
1968 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ | |
1969 | static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) | |
1970 | { | |
1971 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
1972 | u16 tmp; | |
1973 | ||
1974 | regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
1975 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
1976 | if (dev->phy.rev >= 3) { | |
1977 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); | |
1978 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); | |
1979 | ||
1980 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
1981 | regs[2] = tmp; | |
1982 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); | |
1983 | ||
1984 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
1985 | regs[3] = tmp; | |
1986 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); | |
1987 | ||
1988 | regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); | |
de9a47f9 | 1989 | b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX); |
e53de674 | 1990 | |
c643a66e | 1991 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); |
e53de674 | 1992 | regs[5] = tmp; |
d41a3552 | 1993 | b43_ntab_write(dev, B43_NTAB16(8, 3), 0); |
c643a66e RM |
1994 | |
1995 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); | |
e53de674 | 1996 | regs[6] = tmp; |
d41a3552 | 1997 | b43_ntab_write(dev, B43_NTAB16(8, 19), 0); |
e53de674 RM |
1998 | regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
1999 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2000 | ||
2001 | /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */ | |
2002 | /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */ | |
2003 | /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */ | |
2004 | ||
2005 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
2006 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
2007 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
2008 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
2009 | } else { | |
2010 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); | |
2011 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); | |
2012 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2013 | regs[2] = tmp; | |
2014 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); | |
c643a66e | 2015 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); |
e53de674 RM |
2016 | regs[3] = tmp; |
2017 | tmp |= 0x2000; | |
d41a3552 | 2018 | b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); |
c643a66e | 2019 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); |
e53de674 RM |
2020 | regs[4] = tmp; |
2021 | tmp |= 0x2000; | |
d41a3552 | 2022 | b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); |
e53de674 RM |
2023 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
2024 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2025 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
2026 | tmp = 0x0180; | |
2027 | else | |
2028 | tmp = 0x0120; | |
2029 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
2030 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
2031 | } | |
2032 | } | |
2033 | ||
2f258b74 RM |
2034 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ |
2035 | static void b43_nphy_restore_cal(struct b43_wldev *dev) | |
2036 | { | |
2037 | struct b43_phy_n *nphy = dev->phy.n; | |
2038 | ||
2039 | u16 coef[4]; | |
2040 | u16 *loft = NULL; | |
2041 | u16 *table = NULL; | |
2042 | ||
2043 | int i; | |
2044 | u16 *txcal_radio_regs = NULL; | |
2045 | struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; | |
2046 | ||
2047 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2048 | if (nphy->iqcal_chanspec_2G == 0) | |
2049 | return; | |
2050 | table = nphy->cal_cache.txcal_coeffs_2G; | |
2051 | loft = &nphy->cal_cache.txcal_coeffs_2G[5]; | |
2052 | } else { | |
2053 | if (nphy->iqcal_chanspec_5G == 0) | |
2054 | return; | |
2055 | table = nphy->cal_cache.txcal_coeffs_5G; | |
2056 | loft = &nphy->cal_cache.txcal_coeffs_5G[5]; | |
2057 | } | |
2058 | ||
2581b143 | 2059 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); |
2f258b74 RM |
2060 | |
2061 | for (i = 0; i < 4; i++) { | |
2062 | if (dev->phy.rev >= 3) | |
2063 | table[i] = coef[i]; | |
2064 | else | |
2065 | coef[i] = 0; | |
2066 | } | |
2067 | ||
2581b143 RM |
2068 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); |
2069 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); | |
2070 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); | |
2f258b74 RM |
2071 | |
2072 | if (dev->phy.rev < 2) | |
2073 | b43_nphy_tx_iq_workaround(dev); | |
2074 | ||
2075 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2076 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; | |
2077 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; | |
2078 | } else { | |
2079 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; | |
2080 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; | |
2081 | } | |
2082 | ||
2083 | /* TODO use some definitions */ | |
2084 | if (dev->phy.rev >= 3) { | |
2085 | b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); | |
2086 | b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); | |
2087 | b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); | |
2088 | b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); | |
2089 | b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); | |
2090 | b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); | |
2091 | b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); | |
2092 | b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); | |
2093 | } else { | |
2094 | b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); | |
2095 | b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); | |
2096 | b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); | |
2097 | b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); | |
2098 | } | |
2099 | b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); | |
2100 | } | |
2101 | ||
fb43b8e2 RM |
2102 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ |
2103 | static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, | |
2104 | struct nphy_txgains target, | |
2105 | bool full, bool mphase) | |
2106 | { | |
2107 | struct b43_phy_n *nphy = dev->phy.n; | |
2108 | int i; | |
2109 | int error = 0; | |
2110 | int freq; | |
2111 | bool avoid = false; | |
2112 | u8 length; | |
2113 | u16 tmp, core, type, count, max, numb, last, cmd; | |
2114 | const u16 *table; | |
2115 | bool phy6or5x; | |
2116 | ||
2117 | u16 buffer[11]; | |
2118 | u16 diq_start = 0; | |
2119 | u16 save[2]; | |
2120 | u16 gain[2]; | |
2121 | struct nphy_iqcal_params params[2]; | |
2122 | bool updated[2] = { }; | |
2123 | ||
2124 | b43_nphy_stay_in_carrier_search(dev, true); | |
2125 | ||
2126 | if (dev->phy.rev >= 4) { | |
2127 | avoid = nphy->hang_avoid; | |
2128 | nphy->hang_avoid = 0; | |
2129 | } | |
2130 | ||
9145834e | 2131 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2132 | |
2133 | for (i = 0; i < 2; i++) { | |
2134 | b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); | |
2135 | gain[i] = params[i].cal_gain; | |
2136 | } | |
2581b143 RM |
2137 | |
2138 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); | |
fb43b8e2 RM |
2139 | |
2140 | b43_nphy_tx_cal_radio_setup(dev); | |
e53de674 | 2141 | b43_nphy_tx_cal_phy_setup(dev); |
fb43b8e2 RM |
2142 | |
2143 | phy6or5x = dev->phy.rev >= 6 || | |
2144 | (dev->phy.rev == 5 && nphy->ipa2g_on && | |
2145 | b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); | |
2146 | if (phy6or5x) { | |
2147 | /* TODO */ | |
2148 | } | |
2149 | ||
2150 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); | |
2151 | ||
aa4c7b2a | 2152 | if (!dev->phy.is_40mhz) |
fb43b8e2 RM |
2153 | freq = 2500; |
2154 | else | |
2155 | freq = 5000; | |
2156 | ||
2157 | if (nphy->mphase_cal_phase_id > 2) | |
10a79873 RM |
2158 | b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, |
2159 | 0xFFFF, 0, true, false); | |
fb43b8e2 | 2160 | else |
59af099b | 2161 | error = b43_nphy_tx_tone(dev, freq, 250, true, false); |
fb43b8e2 RM |
2162 | |
2163 | if (error == 0) { | |
2164 | if (nphy->mphase_cal_phase_id > 2) { | |
2165 | table = nphy->mphase_txcal_bestcoeffs; | |
2166 | length = 11; | |
2167 | if (dev->phy.rev < 3) | |
2168 | length -= 2; | |
2169 | } else { | |
2170 | if (!full && nphy->txiqlocal_coeffsvalid) { | |
2171 | table = nphy->txiqlocal_bestc; | |
2172 | length = 11; | |
2173 | if (dev->phy.rev < 3) | |
2174 | length -= 2; | |
2175 | } else { | |
2176 | full = true; | |
2177 | if (dev->phy.rev >= 3) { | |
2178 | table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; | |
2179 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; | |
2180 | } else { | |
2181 | table = tbl_tx_iqlo_cal_startcoefs; | |
2182 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; | |
2183 | } | |
2184 | } | |
2185 | } | |
2186 | ||
2581b143 | 2187 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); |
fb43b8e2 RM |
2188 | |
2189 | if (full) { | |
2190 | if (dev->phy.rev >= 3) | |
2191 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; | |
2192 | else | |
2193 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; | |
2194 | } else { | |
2195 | if (dev->phy.rev >= 3) | |
2196 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; | |
2197 | else | |
2198 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; | |
2199 | } | |
2200 | ||
2201 | if (mphase) { | |
2202 | count = nphy->mphase_txcal_cmdidx; | |
2203 | numb = min(max, | |
2204 | (u16)(count + nphy->mphase_txcal_numcmds)); | |
2205 | } else { | |
2206 | count = 0; | |
2207 | numb = max; | |
2208 | } | |
2209 | ||
2210 | for (; count < numb; count++) { | |
2211 | if (full) { | |
2212 | if (dev->phy.rev >= 3) | |
2213 | cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; | |
2214 | else | |
2215 | cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; | |
2216 | } else { | |
2217 | if (dev->phy.rev >= 3) | |
2218 | cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; | |
2219 | else | |
2220 | cmd = tbl_tx_iqlo_cal_cmds_recal[count]; | |
2221 | } | |
2222 | ||
2223 | core = (cmd & 0x3000) >> 12; | |
2224 | type = (cmd & 0x0F00) >> 8; | |
2225 | ||
2226 | if (phy6or5x && updated[core] == 0) { | |
2227 | b43_nphy_update_tx_cal_ladder(dev, core); | |
2228 | updated[core] = 1; | |
2229 | } | |
2230 | ||
2231 | tmp = (params[core].ncorr[type] << 8) | 0x66; | |
2232 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); | |
2233 | ||
2234 | if (type == 1 || type == 3 || type == 4) { | |
c643a66e RM |
2235 | buffer[0] = b43_ntab_read(dev, |
2236 | B43_NTAB16(15, 69 + core)); | |
fb43b8e2 RM |
2237 | diq_start = buffer[0]; |
2238 | buffer[0] = 0; | |
d41a3552 RM |
2239 | b43_ntab_write(dev, B43_NTAB16(15, 69 + core), |
2240 | 0); | |
fb43b8e2 RM |
2241 | } |
2242 | ||
2243 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); | |
2244 | for (i = 0; i < 2000; i++) { | |
2245 | tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); | |
2246 | if (tmp & 0xC000) | |
2247 | break; | |
2248 | udelay(10); | |
2249 | } | |
2250 | ||
9145834e RM |
2251 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2252 | buffer); | |
2581b143 RM |
2253 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, |
2254 | buffer); | |
fb43b8e2 RM |
2255 | |
2256 | if (type == 1 || type == 3 || type == 4) | |
2257 | buffer[0] = diq_start; | |
2258 | } | |
2259 | ||
2260 | if (mphase) | |
2261 | nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; | |
2262 | ||
2263 | last = (dev->phy.rev < 3) ? 6 : 7; | |
2264 | ||
2265 | if (!mphase || nphy->mphase_cal_phase_id == last) { | |
2581b143 | 2266 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); |
9145834e | 2267 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); |
fb43b8e2 RM |
2268 | if (dev->phy.rev < 3) { |
2269 | buffer[0] = 0; | |
2270 | buffer[1] = 0; | |
2271 | buffer[2] = 0; | |
2272 | buffer[3] = 0; | |
2273 | } | |
2581b143 RM |
2274 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, |
2275 | buffer); | |
2276 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2, | |
2277 | buffer); | |
2278 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, | |
2279 | buffer); | |
2280 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, | |
2281 | buffer); | |
fb43b8e2 RM |
2282 | length = 11; |
2283 | if (dev->phy.rev < 3) | |
2284 | length -= 2; | |
9145834e RM |
2285 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2286 | nphy->txiqlocal_bestc); | |
fb43b8e2 RM |
2287 | nphy->txiqlocal_coeffsvalid = true; |
2288 | /* TODO: Set nphy->txiqlocal_chanspec to | |
2289 | the current channel */ | |
2290 | } else { | |
2291 | length = 11; | |
2292 | if (dev->phy.rev < 3) | |
2293 | length -= 2; | |
9145834e RM |
2294 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2295 | nphy->mphase_txcal_bestcoeffs); | |
fb43b8e2 RM |
2296 | } |
2297 | ||
53ae8e8c | 2298 | b43_nphy_stop_playback(dev); |
fb43b8e2 RM |
2299 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); |
2300 | } | |
2301 | ||
e53de674 | 2302 | b43_nphy_tx_cal_phy_cleanup(dev); |
2581b143 | 2303 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2304 | |
2305 | if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) | |
2306 | b43_nphy_tx_iq_workaround(dev); | |
2307 | ||
2308 | if (dev->phy.rev >= 4) | |
2309 | nphy->hang_avoid = avoid; | |
2310 | ||
2311 | b43_nphy_stay_in_carrier_search(dev, false); | |
2312 | ||
2313 | return error; | |
2314 | } | |
2315 | ||
15931e31 RM |
2316 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ |
2317 | static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, | |
2318 | struct nphy_txgains target, u8 type, bool debug) | |
2319 | { | |
2320 | struct b43_phy_n *nphy = dev->phy.n; | |
2321 | int i, j, index; | |
2322 | u8 rfctl[2]; | |
2323 | u8 afectl_core; | |
2324 | u16 tmp[6]; | |
2325 | u16 cur_hpf1, cur_hpf2, cur_lna; | |
2326 | u32 real, imag; | |
2327 | enum ieee80211_band band; | |
2328 | ||
2329 | u8 use; | |
2330 | u16 cur_hpf; | |
2331 | u16 lna[3] = { 3, 3, 1 }; | |
2332 | u16 hpf1[3] = { 7, 2, 0 }; | |
2333 | u16 hpf2[3] = { 2, 0, 0 }; | |
de9a47f9 | 2334 | u32 power[3] = { }; |
15931e31 RM |
2335 | u16 gain_save[2]; |
2336 | u16 cal_gain[2]; | |
2337 | struct nphy_iqcal_params cal_params[2]; | |
2338 | struct nphy_iq_est est; | |
2339 | int ret = 0; | |
2340 | bool playtone = true; | |
2341 | int desired = 13; | |
2342 | ||
2343 | b43_nphy_stay_in_carrier_search(dev, 1); | |
2344 | ||
2345 | if (dev->phy.rev < 2) | |
2346 | ;/* TODO: Call N PHY Reapply TX Cal Coeffs */ | |
9145834e | 2347 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
2348 | for (i = 0; i < 2; i++) { |
2349 | b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); | |
2350 | cal_gain[i] = cal_params[i].cal_gain; | |
2351 | } | |
2581b143 | 2352 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); |
15931e31 RM |
2353 | |
2354 | for (i = 0; i < 2; i++) { | |
2355 | if (i == 0) { | |
2356 | rfctl[0] = B43_NPHY_RFCTL_INTC1; | |
2357 | rfctl[1] = B43_NPHY_RFCTL_INTC2; | |
2358 | afectl_core = B43_NPHY_AFECTL_C1; | |
2359 | } else { | |
2360 | rfctl[0] = B43_NPHY_RFCTL_INTC2; | |
2361 | rfctl[1] = B43_NPHY_RFCTL_INTC1; | |
2362 | afectl_core = B43_NPHY_AFECTL_C2; | |
2363 | } | |
2364 | ||
2365 | tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
2366 | tmp[2] = b43_phy_read(dev, afectl_core); | |
2367 | tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2368 | tmp[4] = b43_phy_read(dev, rfctl[0]); | |
2369 | tmp[5] = b43_phy_read(dev, rfctl[1]); | |
2370 | ||
2371 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
2372 | (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
2373 | ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
2374 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
2375 | (1 - i)); | |
2376 | b43_phy_set(dev, afectl_core, 0x0006); | |
2377 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); | |
2378 | ||
2379 | band = b43_current_band(dev->wl); | |
2380 | ||
2381 | if (nphy->rxcalparams & 0xFF000000) { | |
2382 | if (band == IEEE80211_BAND_5GHZ) | |
2383 | b43_phy_write(dev, rfctl[0], 0x140); | |
2384 | else | |
2385 | b43_phy_write(dev, rfctl[0], 0x110); | |
2386 | } else { | |
2387 | if (band == IEEE80211_BAND_5GHZ) | |
2388 | b43_phy_write(dev, rfctl[0], 0x180); | |
2389 | else | |
2390 | b43_phy_write(dev, rfctl[0], 0x120); | |
2391 | } | |
2392 | ||
2393 | if (band == IEEE80211_BAND_5GHZ) | |
2394 | b43_phy_write(dev, rfctl[1], 0x148); | |
2395 | else | |
2396 | b43_phy_write(dev, rfctl[1], 0x114); | |
2397 | ||
2398 | if (nphy->rxcalparams & 0x10000) { | |
2399 | b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, | |
2400 | (i + 1)); | |
2401 | b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, | |
2402 | (2 - i)); | |
2403 | } | |
2404 | ||
2405 | for (j = 0; i < 4; j++) { | |
2406 | if (j < 3) { | |
2407 | cur_lna = lna[j]; | |
2408 | cur_hpf1 = hpf1[j]; | |
2409 | cur_hpf2 = hpf2[j]; | |
2410 | } else { | |
2411 | if (power[1] > 10000) { | |
2412 | use = 1; | |
2413 | cur_hpf = cur_hpf1; | |
2414 | index = 2; | |
2415 | } else { | |
2416 | if (power[0] > 10000) { | |
2417 | use = 1; | |
2418 | cur_hpf = cur_hpf1; | |
2419 | index = 1; | |
2420 | } else { | |
2421 | index = 0; | |
2422 | use = 2; | |
2423 | cur_hpf = cur_hpf2; | |
2424 | } | |
2425 | } | |
2426 | cur_lna = lna[index]; | |
2427 | cur_hpf1 = hpf1[index]; | |
2428 | cur_hpf2 = hpf2[index]; | |
2429 | cur_hpf += desired - hweight32(power[index]); | |
2430 | cur_hpf = clamp_val(cur_hpf, 0, 10); | |
2431 | if (use == 1) | |
2432 | cur_hpf1 = cur_hpf; | |
2433 | else | |
2434 | cur_hpf2 = cur_hpf; | |
2435 | } | |
2436 | ||
2437 | tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | | |
2438 | (cur_lna << 2)); | |
75377b24 RM |
2439 | b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, |
2440 | false); | |
de9a47f9 | 2441 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
53ae8e8c | 2442 | b43_nphy_stop_playback(dev); |
15931e31 RM |
2443 | |
2444 | if (playtone) { | |
59af099b RM |
2445 | ret = b43_nphy_tx_tone(dev, 4000, |
2446 | (nphy->rxcalparams & 0xFFFF), | |
2447 | false, false); | |
15931e31 RM |
2448 | playtone = false; |
2449 | } else { | |
10a79873 RM |
2450 | b43_nphy_run_samples(dev, 160, 0xFFFF, 0, |
2451 | false, false); | |
15931e31 RM |
2452 | } |
2453 | ||
2454 | if (ret == 0) { | |
2455 | if (j < 3) { | |
2456 | b43_nphy_rx_iq_est(dev, &est, 1024, 32, | |
2457 | false); | |
2458 | if (i == 0) { | |
2459 | real = est.i0_pwr; | |
2460 | imag = est.q0_pwr; | |
2461 | } else { | |
2462 | real = est.i1_pwr; | |
2463 | imag = est.q1_pwr; | |
2464 | } | |
2465 | power[i] = ((real + imag) / 1024) + 1; | |
2466 | } else { | |
2467 | b43_nphy_calc_rx_iq_comp(dev, 1 << i); | |
2468 | } | |
53ae8e8c | 2469 | b43_nphy_stop_playback(dev); |
15931e31 RM |
2470 | } |
2471 | ||
2472 | if (ret != 0) | |
2473 | break; | |
2474 | } | |
2475 | ||
2476 | b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); | |
2477 | b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); | |
2478 | b43_phy_write(dev, rfctl[1], tmp[5]); | |
2479 | b43_phy_write(dev, rfctl[0], tmp[4]); | |
2480 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); | |
2481 | b43_phy_write(dev, afectl_core, tmp[2]); | |
2482 | b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); | |
2483 | ||
2484 | if (ret != 0) | |
2485 | break; | |
2486 | } | |
2487 | ||
75377b24 | 2488 | b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); |
67c0d6e2 | 2489 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
2581b143 | 2490 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
2491 | |
2492 | b43_nphy_stay_in_carrier_search(dev, 0); | |
2493 | ||
2494 | return ret; | |
2495 | } | |
2496 | ||
2497 | static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, | |
2498 | struct nphy_txgains target, u8 type, bool debug) | |
2499 | { | |
2500 | return -1; | |
2501 | } | |
2502 | ||
2503 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ | |
2504 | static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, | |
2505 | struct nphy_txgains target, u8 type, bool debug) | |
2506 | { | |
2507 | if (dev->phy.rev >= 3) | |
2508 | return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); | |
2509 | else | |
2510 | return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); | |
2511 | } | |
2512 | ||
0988a7a1 RM |
2513 | /* |
2514 | * Init N-PHY | |
2515 | * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N | |
2516 | */ | |
424047e6 MB |
2517 | int b43_phy_initn(struct b43_wldev *dev) |
2518 | { | |
0988a7a1 | 2519 | struct ssb_bus *bus = dev->dev->bus; |
95b66bad | 2520 | struct b43_phy *phy = &dev->phy; |
0988a7a1 RM |
2521 | struct b43_phy_n *nphy = phy->n; |
2522 | u8 tx_pwr_state; | |
2523 | struct nphy_txgains target; | |
95b66bad | 2524 | u16 tmp; |
0988a7a1 RM |
2525 | enum ieee80211_band tmp2; |
2526 | bool do_rssi_cal; | |
2527 | ||
2528 | u16 clip[2]; | |
2529 | bool do_cal = false; | |
95b66bad | 2530 | |
0988a7a1 RM |
2531 | if ((dev->phy.rev >= 3) && |
2532 | (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && | |
2533 | (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { | |
2534 | chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); | |
2535 | } | |
2536 | nphy->deaf_count = 0; | |
95b66bad | 2537 | b43_nphy_tables_init(dev); |
0988a7a1 RM |
2538 | nphy->crsminpwr_adjusted = false; |
2539 | nphy->noisevars_adjusted = false; | |
95b66bad MB |
2540 | |
2541 | /* Clear all overrides */ | |
0988a7a1 RM |
2542 | if (dev->phy.rev >= 3) { |
2543 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); | |
2544 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
2545 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); | |
2546 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); | |
2547 | } else { | |
2548 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
2549 | } | |
95b66bad MB |
2550 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); |
2551 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); | |
0988a7a1 RM |
2552 | if (dev->phy.rev < 6) { |
2553 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); | |
2554 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); | |
2555 | } | |
95b66bad MB |
2556 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, |
2557 | ~(B43_NPHY_RFSEQMODE_CAOVER | | |
2558 | B43_NPHY_RFSEQMODE_TROVER)); | |
0988a7a1 RM |
2559 | if (dev->phy.rev >= 3) |
2560 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); | |
95b66bad MB |
2561 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); |
2562 | ||
0988a7a1 RM |
2563 | if (dev->phy.rev <= 2) { |
2564 | tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; | |
2565 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, | |
2566 | ~B43_NPHY_BPHY_CTL3_SCALE, | |
2567 | tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); | |
2568 | } | |
95b66bad MB |
2569 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); |
2570 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); | |
2571 | ||
0988a7a1 RM |
2572 | if (bus->sprom.boardflags2_lo & 0x100 || |
2573 | (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && | |
2574 | bus->boardinfo.type == 0x8B)) | |
2575 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); | |
2576 | else | |
2577 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); | |
2578 | b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); | |
2579 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); | |
2580 | b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); | |
424047e6 | 2581 | |
ad9716e8 | 2582 | b43_nphy_update_mimo_config(dev, nphy->preamble_override); |
4f4ab6cd | 2583 | b43_nphy_update_txrx_chain(dev); |
95b66bad MB |
2584 | |
2585 | if (phy->rev < 2) { | |
2586 | b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); | |
2587 | b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); | |
2588 | } | |
0988a7a1 RM |
2589 | |
2590 | tmp2 = b43_current_band(dev->wl); | |
2591 | if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || | |
2592 | (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { | |
2593 | b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); | |
2594 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, | |
2595 | nphy->papd_epsilon_offset[0] << 7); | |
2596 | b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); | |
2597 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, | |
2598 | nphy->papd_epsilon_offset[1] << 7); | |
45ca697e | 2599 | b43_nphy_int_pa_set_tx_dig_filters(dev); |
0988a7a1 | 2600 | } else if (phy->rev >= 5) { |
45ca697e | 2601 | b43_nphy_ext_pa_set_tx_dig_filters(dev); |
0988a7a1 RM |
2602 | } |
2603 | ||
95b66bad | 2604 | b43_nphy_workarounds(dev); |
95b66bad | 2605 | |
0988a7a1 | 2606 | /* Reset CCA, in init code it differs a little from standard way */ |
730dd705 | 2607 | b43_nphy_bmac_clock_fgc(dev, 1); |
0988a7a1 RM |
2608 | tmp = b43_phy_read(dev, B43_NPHY_BBCFG); |
2609 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); | |
2610 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); | |
730dd705 | 2611 | b43_nphy_bmac_clock_fgc(dev, 0); |
0988a7a1 RM |
2612 | |
2613 | /* TODO N PHY MAC PHY Clock Set with argument 1 */ | |
2614 | ||
e50cbcf6 | 2615 | b43_nphy_pa_override(dev, false); |
95b66bad MB |
2616 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
2617 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); | |
e50cbcf6 | 2618 | b43_nphy_pa_override(dev, true); |
0988a7a1 | 2619 | |
bbec398c RM |
2620 | b43_nphy_classifier(dev, 0, 0); |
2621 | b43_nphy_read_clip_detection(dev, clip); | |
0988a7a1 RM |
2622 | tx_pwr_state = nphy->txpwrctrl; |
2623 | /* TODO N PHY TX power control with argument 0 | |
2624 | (turning off power control) */ | |
2625 | /* TODO Fix the TX Power Settings */ | |
2626 | /* TODO N PHY TX Power Control Idle TSSI */ | |
2627 | /* TODO N PHY TX Power Control Setup */ | |
2628 | ||
2629 | if (phy->rev >= 3) { | |
2630 | /* TODO */ | |
2631 | } else { | |
2581b143 RM |
2632 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, |
2633 | b43_ntab_tx_gain_rev0_1_2); | |
2634 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, | |
2635 | b43_ntab_tx_gain_rev0_1_2); | |
0988a7a1 | 2636 | } |
95b66bad | 2637 | |
0988a7a1 RM |
2638 | if (nphy->phyrxchain != 3) |
2639 | ;/* TODO N PHY RX Core Set State with phyrxchain as argument */ | |
2640 | if (nphy->mphase_cal_phase_id > 0) | |
2641 | ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ | |
2642 | ||
2643 | do_rssi_cal = false; | |
2644 | if (phy->rev >= 3) { | |
2645 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
2646 | do_rssi_cal = (nphy->rssical_chanspec_2G == 0); | |
2647 | else | |
2648 | do_rssi_cal = (nphy->rssical_chanspec_5G == 0); | |
2649 | ||
2650 | if (do_rssi_cal) | |
4cb99775 | 2651 | b43_nphy_rssi_cal(dev); |
0988a7a1 | 2652 | else |
42e1547e | 2653 | b43_nphy_restore_rssi_cal(dev); |
0988a7a1 | 2654 | } else { |
4cb99775 | 2655 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
2656 | } |
2657 | ||
2658 | if (!((nphy->measure_hold & 0x6) != 0)) { | |
2659 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
2660 | do_cal = (nphy->iqcal_chanspec_2G == 0); | |
2661 | else | |
2662 | do_cal = (nphy->iqcal_chanspec_5G == 0); | |
2663 | ||
2664 | if (nphy->mute) | |
2665 | do_cal = false; | |
2666 | ||
2667 | if (do_cal) { | |
b0022e15 | 2668 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
2669 | |
2670 | if (nphy->antsel_type == 2) | |
2671 | ;/*TODO NPHY Superswitch Init with argument 1*/ | |
2672 | if (nphy->perical != 2) { | |
90b9738d | 2673 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
2674 | if (phy->rev >= 3) { |
2675 | nphy->cal_orig_pwr_idx[0] = | |
2676 | nphy->txpwrindex[0].index_internal; | |
2677 | nphy->cal_orig_pwr_idx[1] = | |
2678 | nphy->txpwrindex[1].index_internal; | |
2679 | /* TODO N PHY Pre Calibrate TX Gain */ | |
b0022e15 | 2680 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
2681 | } |
2682 | } | |
2683 | } | |
2684 | } | |
2685 | ||
0988a7a1 RM |
2686 | if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) { |
2687 | if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) | |
15931e31 | 2688 | ;/* Call N PHY Save Cal */ |
0988a7a1 | 2689 | else if (nphy->mphase_cal_phase_id == 0) |
15931e31 | 2690 | ;/* N PHY Periodic Calibration with argument 3 */ |
0988a7a1 RM |
2691 | } else { |
2692 | b43_nphy_restore_cal(dev); | |
2693 | } | |
0988a7a1 | 2694 | |
6dcd9d91 | 2695 | b43_nphy_tx_pwr_ctrl_coef_setup(dev); |
0988a7a1 RM |
2696 | /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */ |
2697 | b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); | |
2698 | b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); | |
2699 | if (phy->rev >= 3 && phy->rev <= 6) | |
2700 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); | |
fe3e46e8 | 2701 | b43_nphy_tx_lp_fbw(dev); |
0988a7a1 | 2702 | /* TODO N PHY Spur Workaround */ |
95b66bad MB |
2703 | |
2704 | b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); | |
53a6e234 | 2705 | return 0; |
424047e6 | 2706 | } |
ef1a628d MB |
2707 | |
2708 | static int b43_nphy_op_allocate(struct b43_wldev *dev) | |
2709 | { | |
2710 | struct b43_phy_n *nphy; | |
2711 | ||
2712 | nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); | |
2713 | if (!nphy) | |
2714 | return -ENOMEM; | |
2715 | dev->phy.n = nphy; | |
2716 | ||
ef1a628d MB |
2717 | return 0; |
2718 | } | |
2719 | ||
fb11137a | 2720 | static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) |
ef1a628d | 2721 | { |
fb11137a MB |
2722 | struct b43_phy *phy = &dev->phy; |
2723 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 2724 | |
fb11137a | 2725 | memset(nphy, 0, sizeof(*nphy)); |
ef1a628d | 2726 | |
fb11137a | 2727 | //TODO init struct b43_phy_n |
ef1a628d MB |
2728 | } |
2729 | ||
fb11137a | 2730 | static void b43_nphy_op_free(struct b43_wldev *dev) |
ef1a628d | 2731 | { |
fb11137a MB |
2732 | struct b43_phy *phy = &dev->phy; |
2733 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 2734 | |
ef1a628d | 2735 | kfree(nphy); |
fb11137a MB |
2736 | phy->n = NULL; |
2737 | } | |
2738 | ||
2739 | static int b43_nphy_op_init(struct b43_wldev *dev) | |
2740 | { | |
2741 | return b43_phy_initn(dev); | |
ef1a628d MB |
2742 | } |
2743 | ||
2744 | static inline void check_phyreg(struct b43_wldev *dev, u16 offset) | |
2745 | { | |
2746 | #if B43_DEBUG | |
2747 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { | |
2748 | /* OFDM registers are onnly available on A/G-PHYs */ | |
2749 | b43err(dev->wl, "Invalid OFDM PHY access at " | |
2750 | "0x%04X on N-PHY\n", offset); | |
2751 | dump_stack(); | |
2752 | } | |
2753 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { | |
2754 | /* Ext-G registers are only available on G-PHYs */ | |
2755 | b43err(dev->wl, "Invalid EXT-G PHY access at " | |
2756 | "0x%04X on N-PHY\n", offset); | |
2757 | dump_stack(); | |
2758 | } | |
2759 | #endif /* B43_DEBUG */ | |
2760 | } | |
2761 | ||
2762 | static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) | |
2763 | { | |
2764 | check_phyreg(dev, reg); | |
2765 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
2766 | return b43_read16(dev, B43_MMIO_PHY_DATA); | |
2767 | } | |
2768 | ||
2769 | static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) | |
2770 | { | |
2771 | check_phyreg(dev, reg); | |
2772 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
2773 | b43_write16(dev, B43_MMIO_PHY_DATA, value); | |
2774 | } | |
2775 | ||
2776 | static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) | |
2777 | { | |
2778 | /* Register 1 is a 32-bit register. */ | |
2779 | B43_WARN_ON(reg == 1); | |
2780 | /* N-PHY needs 0x100 for read access */ | |
2781 | reg |= 0x100; | |
2782 | ||
2783 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
2784 | return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); | |
2785 | } | |
2786 | ||
2787 | static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) | |
2788 | { | |
2789 | /* Register 1 is a 32-bit register. */ | |
2790 | B43_WARN_ON(reg == 1); | |
2791 | ||
2792 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
2793 | b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); | |
2794 | } | |
2795 | ||
2796 | static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, | |
19d337df | 2797 | bool blocked) |
ef1a628d MB |
2798 | {//TODO |
2799 | } | |
2800 | ||
cb24f57f MB |
2801 | static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) |
2802 | { | |
2803 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, | |
2804 | on ? 0 : 0x7FFF); | |
2805 | } | |
2806 | ||
ef1a628d MB |
2807 | static int b43_nphy_op_switch_channel(struct b43_wldev *dev, |
2808 | unsigned int new_channel) | |
2809 | { | |
2810 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2811 | if ((new_channel < 1) || (new_channel > 14)) | |
2812 | return -EINVAL; | |
2813 | } else { | |
2814 | if (new_channel > 200) | |
2815 | return -EINVAL; | |
2816 | } | |
2817 | ||
2818 | return nphy_channel_switch(dev, new_channel); | |
2819 | } | |
2820 | ||
2821 | static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) | |
2822 | { | |
2823 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
2824 | return 1; | |
2825 | return 36; | |
2826 | } | |
2827 | ||
ef1a628d MB |
2828 | const struct b43_phy_operations b43_phyops_n = { |
2829 | .allocate = b43_nphy_op_allocate, | |
fb11137a MB |
2830 | .free = b43_nphy_op_free, |
2831 | .prepare_structs = b43_nphy_op_prepare_structs, | |
ef1a628d | 2832 | .init = b43_nphy_op_init, |
ef1a628d MB |
2833 | .phy_read = b43_nphy_op_read, |
2834 | .phy_write = b43_nphy_op_write, | |
2835 | .radio_read = b43_nphy_op_radio_read, | |
2836 | .radio_write = b43_nphy_op_radio_write, | |
2837 | .software_rfkill = b43_nphy_op_software_rfkill, | |
cb24f57f | 2838 | .switch_analog = b43_nphy_op_switch_analog, |
ef1a628d MB |
2839 | .switch_channel = b43_nphy_op_switch_channel, |
2840 | .get_default_chan = b43_nphy_op_get_default_chan, | |
18c8adeb MB |
2841 | .recalc_txpower = b43_nphy_op_recalc_txpower, |
2842 | .adjust_txpower = b43_nphy_op_adjust_txpower, | |
ef1a628d | 2843 | }; |