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b43: N-PHY: fix success condition of running samples
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
bbec398c 35#include "main.h"
424047e6 36
f8187b5b
RM		 37struct nphy_txgains {
38 u16 txgm[2];
39 u16 pga[2];
40 u16 pad[2];
41 u16 ipa[2];
42};
43
44struct nphy_iqcal_params {
45 u16 txgm;
46 u16 pga;
47 u16 pad;
48 u16 ipa;
49 u16 cal_gain;
50 u16 ncorr[5];
51};
52
53struct nphy_iq_est {
54 s32 iq0_prod;
55 u32 i0_pwr;
56 u32 q0_pwr;
57 s32 iq1_prod;
58 u32 i1_pwr;
59 u32 q1_pwr;
60};
424047e6 61
67c0d6e2
RM		 62enum b43_nphy_rf_sequence {
63 B43_RFSEQ_RX2TX,
64 B43_RFSEQ_TX2RX,
65 B43_RFSEQ_RESET2RX,
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
69};
70
76b002bd
RM		 71enum b43_nphy_rssi_type {
72 B43_NPHY_RSSI_X = 0,
73 B43_NPHY_RSSI_Y,
74 B43_NPHY_RSSI_Z,
75 B43_NPHY_RSSI_PWRDET,
76 B43_NPHY_RSSI_TSSI_I,
77 B43_NPHY_RSSI_TSSI_Q,
78 B43_NPHY_RSSI_TBD,
79};
80
c002831a
RM		 81static inline bool b43_nphy_ipa(struct b43_wldev *dev)
82{
83 enum ieee80211_band band = b43_current_band(dev->wl);
84 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
85 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
86}
87
ab499217
RM		 88/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
89static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
90{
91 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
92 if (dev->phy.rev >= 6) {
93 if (dev->dev->chip_id == 47162)
94 return txpwrctrl_tx_gain_ipa_rev5;
95 return txpwrctrl_tx_gain_ipa_rev6;
96 } else if (dev->phy.rev >= 5) {
97 return txpwrctrl_tx_gain_ipa_rev5;
98 } else {
99 return txpwrctrl_tx_gain_ipa;
100 }
101 } else {
102 return txpwrctrl_tx_gain_ipa_5g;
103 }
104}
105
106/**************************************************
107 * RF (just without b43_nphy_rf_control_intc_override)
108 **************************************************/
109
110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
111static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
112 enum b43_nphy_rf_sequence seq)
113{
114 static const u16 trigger[] = {
115 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
116 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
117 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
118 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
119 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
120 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
121 };
122 int i;
123 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
124
125 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
126
127 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
128 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
129 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
130 for (i = 0; i < 200; i++) {
131 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
132 goto ok;
133 msleep(1);
134 }
135 b43err(dev->wl, "RF sequence status timeout\n");
136ok:
137 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
138}
139
140/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
141static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
142 u16 value, u8 core, bool off)
143{
144 int i;
145 u8 index = fls(field);
146 u8 addr, en_addr, val_addr;
147 /* we expect only one bit set */
148 B43_WARN_ON(field & (~(1 << (index - 1))));
149
150 if (dev->phy.rev >= 3) {
151 const struct nphy_rf_control_override_rev3 *rf_ctrl;
152 for (i = 0; i < 2; i++) {
153 if (index == 0 || index == 16) {
154 b43err(dev->wl,
155 "Unsupported RF Ctrl Override call\n");
156 return;
157 }
158
159 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
160 en_addr = B43_PHY_N((i == 0) ?
161 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
162 val_addr = B43_PHY_N((i == 0) ?
163 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
164
165 if (off) {
166 b43_phy_mask(dev, en_addr, ~(field));
167 b43_phy_mask(dev, val_addr,
168 ~(rf_ctrl->val_mask));
169 } else {
170 if (core == 0 || ((1 << core) & i) != 0) {
171 b43_phy_set(dev, en_addr, field);
172 b43_phy_maskset(dev, val_addr,
173 ~(rf_ctrl->val_mask),
174 (value << rf_ctrl->val_shift));
175 }
176 }
177 }
178 } else {
179 const struct nphy_rf_control_override_rev2 *rf_ctrl;
180 if (off) {
181 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
182 value = 0;
183 } else {
184 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
185 }
186
187 for (i = 0; i < 2; i++) {
188 if (index <= 1 || index == 16) {
189 b43err(dev->wl,
190 "Unsupported RF Ctrl Override call\n");
191 return;
192 }
193
194 if (index == 2 || index == 10 ||
195 (index >= 13 && index <= 15)) {
196 core = 1;
197 }
198
199 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
200 addr = B43_PHY_N((i == 0) ?
201 rf_ctrl->addr0 : rf_ctrl->addr1);
202
203 if ((core & (1 << i)) != 0)
204 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
205 (value << rf_ctrl->shift));
206
207 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
208 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
209 B43_NPHY_RFCTL_CMD_START);
210 udelay(1);
211 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
212 }
213 }
214}
215
216/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
217static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
218 u16 value, u8 core)
219{
220 u8 i, j;
221 u16 reg, tmp, val;
222
223 B43_WARN_ON(dev->phy.rev < 3);
224 B43_WARN_ON(field > 4);
225
226 for (i = 0; i < 2; i++) {
227 if ((core == 1 && i == 1) || (core == 2 && !i))
228 continue;
229
230 reg = (i == 0) ?
231 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
232 b43_phy_mask(dev, reg, 0xFBFF);
233
234 switch (field) {
235 case 0:
236 b43_phy_write(dev, reg, 0);
237 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
238 break;
239 case 1:
240 if (!i) {
241 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
242 0xFC3F, (value << 6));
243 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
244 0xFFFE, 1);
245 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
246 B43_NPHY_RFCTL_CMD_START);
247 for (j = 0; j < 100; j++) {
248 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
249 j = 0;
250 break;
251 }
252 udelay(10);
253 }
254 if (j)
255 b43err(dev->wl,
256 "intc override timeout\n");
257 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
258 0xFFFE);
259 } else {
260 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
261 0xFC3F, (value << 6));
262 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
263 0xFFFE, 1);
264 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
265 B43_NPHY_RFCTL_CMD_RXTX);
266 for (j = 0; j < 100; j++) {
267 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
268 j = 0;
269 break;
270 }
271 udelay(10);
272 }
273 if (j)
274 b43err(dev->wl,
275 "intc override timeout\n");
276 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
277 0xFFFE);
278 }
279 break;
280 case 2:
281 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
282 tmp = 0x0020;
283 val = value << 5;
284 } else {
285 tmp = 0x0010;
286 val = value << 4;
287 }
288 b43_phy_maskset(dev, reg, ~tmp, val);
289 break;
290 case 3:
291 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
292 tmp = 0x0001;
293 val = value;
294 } else {
295 tmp = 0x0004;
296 val = value << 2;
297 }
298 b43_phy_maskset(dev, reg, ~tmp, val);
299 break;
300 case 4:
301 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
302 tmp = 0x0002;
303 val = value << 1;
304 } else {
305 tmp = 0x0008;
306 val = value << 3;
307 }
308 b43_phy_maskset(dev, reg, ~tmp, val);
309 break;
310 }
311 }
312}
313
314/**************************************************
315 * Various PHY ops
316 **************************************************/
317
318/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
319static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
320 const u16 *clip_st)
321{
322 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
323 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
324}
325
326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
327static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
328{
329 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
330 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
331}
332
333/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
334static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
335{
336 u16 tmp;
337
338 if (dev->dev->core_rev == 16)
339 b43_mac_suspend(dev);
340
341 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
342 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
343 B43_NPHY_CLASSCTL_WAITEDEN);
344 tmp &= ~mask;
345 tmp |= (val & mask);
346 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
347
348 if (dev->dev->core_rev == 16)
349 b43_mac_enable(dev);
350
351 return tmp;
352}
353
354/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
355static void b43_nphy_reset_cca(struct b43_wldev *dev)
356{
357 u16 bbcfg;
358
359 b43_phy_force_clock(dev, 1);
360 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
361 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
362 udelay(1);
363 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
364 b43_phy_force_clock(dev, 0);
365 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
366}
367
368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
369static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
370{
371 struct b43_phy *phy = &dev->phy;
372 struct b43_phy_n *nphy = phy->n;
373
374 if (enable) {
375 static const u16 clip[] = { 0xFFFF, 0xFFFF };
376 if (nphy->deaf_count++ == 0) {
377 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
378 b43_nphy_classifier(dev, 0x7, 0);
379 b43_nphy_read_clip_detection(dev, nphy->clip_state);
380 b43_nphy_write_clip_detection(dev, clip);
381 }
382 b43_nphy_reset_cca(dev);
383 } else {
384 if (--nphy->deaf_count == 0) {
385 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
386 b43_nphy_write_clip_detection(dev, nphy->clip_state);
387 }
388 }
389}
390
64712095
RM		 391/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
392static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
393{
394 struct b43_phy_n *nphy = dev->phy.n;
395
396 u8 i;
397 s16 tmp;
398 u16 data[4];
399 s16 gain[2];
400 u16 minmax[2];
401 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
402
403 if (nphy->hang_avoid)
404 b43_nphy_stay_in_carrier_search(dev, 1);
405
406 if (nphy->gain_boost) {
407 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
408 gain[0] = 6;
409 gain[1] = 6;
410 } else {
411 tmp = 40370 - 315 * dev->phy.channel;
412 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
413 tmp = 23242 - 224 * dev->phy.channel;
414 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
415 }
416 } else {
417 gain[0] = 0;
418 gain[1] = 0;
419 }
420
421 for (i = 0; i < 2; i++) {
422 if (nphy->elna_gain_config) {
423 data[0] = 19 + gain[i];
424 data[1] = 25 + gain[i];
425 data[2] = 25 + gain[i];
426 data[3] = 25 + gain[i];
427 } else {
428 data[0] = lna_gain[0] + gain[i];
429 data[1] = lna_gain[1] + gain[i];
430 data[2] = lna_gain[2] + gain[i];
431 data[3] = lna_gain[3] + gain[i];
432 }
433 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
434
435 minmax[i] = 23 + gain[i];
436 }
437
438 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
439 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
440 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
441 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
442
443 if (nphy->hang_avoid)
444 b43_nphy_stay_in_carrier_search(dev, 0);
445}
446
ab499217
RM		 447/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
448static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
449 u8 *events, u8 *delays, u8 length)
450{
451 struct b43_phy_n *nphy = dev->phy.n;
452 u8 i;
453 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
454 u16 offset1 = cmd << 4;
455 u16 offset2 = offset1 + 0x80;
456
457 if (nphy->hang_avoid)
458 b43_nphy_stay_in_carrier_search(dev, true);
459
460 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
461 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
462
463 for (i = length; i < 16; i++) {
464 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
465 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
466 }
467
468 if (nphy->hang_avoid)
469 b43_nphy_stay_in_carrier_search(dev, false);
470}
471
472/**************************************************
884a5228 473 * Radio 0x2056
ab499217
RM		 474 **************************************************/
475
d4814e69
RM		 476static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
477 const struct b43_nphy_channeltab_entry_rev3 *e)
478{
479 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
480 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
481 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
482 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
483 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
484 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
485 e->radio_syn_pll_loopfilter1);
486 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
487 e->radio_syn_pll_loopfilter2);
488 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
489 e->radio_syn_pll_loopfilter3);
490 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
491 e->radio_syn_pll_loopfilter4);
492 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
493 e->radio_syn_pll_loopfilter5);
494 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
495 e->radio_syn_reserved_addr27);
496 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
497 e->radio_syn_reserved_addr28);
498 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
499 e->radio_syn_reserved_addr29);
500 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
501 e->radio_syn_logen_vcobuf1);
502 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
503 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
504 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
505
506 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
507 e->radio_rx0_lnaa_tune);
508 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
509 e->radio_rx0_lnag_tune);
510
511 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
512 e->radio_tx0_intpaa_boost_tune);
513 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
514 e->radio_tx0_intpag_boost_tune);
515 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
516 e->radio_tx0_pada_boost_tune);
517 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
518 e->radio_tx0_padg_boost_tune);
519 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
520 e->radio_tx0_pgaa_boost_tune);
521 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
522 e->radio_tx0_pgag_boost_tune);
523 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
524 e->radio_tx0_mixa_boost_tune);
525 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
526 e->radio_tx0_mixg_boost_tune);
527
528 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
529 e->radio_rx1_lnaa_tune);
530 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
531 e->radio_rx1_lnag_tune);
532
533 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
534 e->radio_tx1_intpaa_boost_tune);
535 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
536 e->radio_tx1_intpag_boost_tune);
537 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
538 e->radio_tx1_pada_boost_tune);
539 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
540 e->radio_tx1_padg_boost_tune);
541 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
542 e->radio_tx1_pgaa_boost_tune);
543 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
544 e->radio_tx1_pgag_boost_tune);
545 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
546 e->radio_tx1_mixa_boost_tune);
547 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
548 e->radio_tx1_mixg_boost_tune);
549}
550
551/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
552static void b43_radio_2056_setup(struct b43_wldev *dev,
553 const struct b43_nphy_channeltab_entry_rev3 *e)
554{
38646eba
RM		 555 struct ssb_sprom *sprom = dev->dev->bus_sprom;
556 enum ieee80211_band band = b43_current_band(dev->wl);
557 u16 offset;
558 u8 i;
559 u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
560
d4814e69
RM		 561 B43_WARN_ON(dev->phy.rev < 3);
562
563 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 564 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
565
566 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
567 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
568 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
569 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
570 if (dev->dev->chip_id == 0x4716) {
571 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
572 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
573 } else {
574 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
575 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
576 }
577 }
578 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
579 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
580 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
581 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
582 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
583 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
584 }
585
586 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
587 for (i = 0; i < 2; i++) {
588 offset = i ? B2056_TX1 : B2056_TX0;
589 if (dev->phy.rev >= 5) {
590 b43_radio_write(dev,
591 offset | B2056_TX_PADG_IDAC, 0xcc);
592
593 if (dev->dev->chip_id == 0x4716) {
594 bias = 0x40;
595 cbias = 0x45;
596 pag_boost = 0x5;
597 pgag_boost = 0x33;
598 mixg_boost = 0x55;
599 } else {
600 bias = 0x25;
601 cbias = 0x20;
602 pag_boost = 0x4;
603 pgag_boost = 0x03;
604 mixg_boost = 0x65;
605 }
606 padg_boost = 0x77;
607
608 b43_radio_write(dev,
609 offset | B2056_TX_INTPAG_IMAIN_STAT,
610 bias);
611 b43_radio_write(dev,
612 offset | B2056_TX_INTPAG_IAUX_STAT,
613 bias);
614 b43_radio_write(dev,
615 offset | B2056_TX_INTPAG_CASCBIAS,
616 cbias);
617 b43_radio_write(dev,
618 offset | B2056_TX_INTPAG_BOOST_TUNE,
619 pag_boost);
620 b43_radio_write(dev,
621 offset | B2056_TX_PGAG_BOOST_TUNE,
622 pgag_boost);
623 b43_radio_write(dev,
624 offset | B2056_TX_PADG_BOOST_TUNE,
625 padg_boost);
626 b43_radio_write(dev,
627 offset | B2056_TX_MIXG_BOOST_TUNE,
628 mixg_boost);
629 } else {
630 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
631 b43_radio_write(dev,
632 offset | B2056_TX_INTPAG_IMAIN_STAT,
633 bias);
634 b43_radio_write(dev,
635 offset | B2056_TX_INTPAG_IAUX_STAT,
636 bias);
637 b43_radio_write(dev,
638 offset | B2056_TX_INTPAG_CASCBIAS,
639 0x30);
640 }
641 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
642 }
643 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
644 /* TODO */
645 }
646
d4814e69
RM		 647 udelay(50);
648 /* VCO calibration */
649 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
650 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
651 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
652 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
653 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
654 udelay(300);
655}
656
884a5228
RM		 657static void b43_radio_init2056_pre(struct b43_wldev *dev)
658{
659 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
660 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
661 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
662 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
663 B43_NPHY_RFCTL_CMD_OEPORFORCE);
664 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
665 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
666 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
667 B43_NPHY_RFCTL_CMD_CHIP0PU);
668}
669
670static void b43_radio_init2056_post(struct b43_wldev *dev)
671{
672 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
673 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
674 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
675 msleep(1);
676 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
677 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
678 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
679 /*
680 if (nphy->init_por)
681 Call Radio 2056 Recalibrate
682 */
683}
684
685/*
686 * Initialize a Broadcom 2056 N-radio
687 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
688 */
689static void b43_radio_init2056(struct b43_wldev *dev)
690{
691 b43_radio_init2056_pre(dev);
692 b2056_upload_inittabs(dev, 0, 0);
693 b43_radio_init2056_post(dev);
694}
695
696/**************************************************
697 * Radio 0x2055
698 **************************************************/
699
700static void b43_chantab_radio_upload(struct b43_wldev *dev,
701 const struct b43_nphy_channeltab_entry_rev2 *e)
702{
703 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
704 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
705 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
706 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
707 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
708
709 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
710 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
711 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
712 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
713 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
714
715 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
716 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
717 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
718 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
719 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
720
721 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
722 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
723 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
724 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
725 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
726
727 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
728 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
729 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
730 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
731 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
732
733 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
734 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
735}
736
737/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
738static void b43_radio_2055_setup(struct b43_wldev *dev,
739 const struct b43_nphy_channeltab_entry_rev2 *e)
740{
741 B43_WARN_ON(dev->phy.rev >= 3);
742
743 b43_chantab_radio_upload(dev, e);
744 udelay(50);
745 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
746 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
747 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
748 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
749 udelay(300);
750}
751
752static void b43_radio_init2055_pre(struct b43_wldev *dev)
753{
754 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
755 ~B43_NPHY_RFCTL_CMD_PORFORCE);
756 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
757 B43_NPHY_RFCTL_CMD_CHIP0PU |
758 B43_NPHY_RFCTL_CMD_OEPORFORCE);
759 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
760 B43_NPHY_RFCTL_CMD_PORFORCE);
761}
762
763static void b43_radio_init2055_post(struct b43_wldev *dev)
764{
765 struct b43_phy_n *nphy = dev->phy.n;
766 struct ssb_sprom *sprom = dev->dev->bus_sprom;
767 int i;
768 u16 val;
769 bool workaround = false;
770
771 if (sprom->revision < 4)
772 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
773 && dev->dev->board_type == 0x46D
774 && dev->dev->board_rev >= 0x41);
775 else
776 workaround =
777 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
778
779 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
780 if (workaround) {
781 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
782 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
783 }
784 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
785 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
786 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
787 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
788 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
789 msleep(1);
790 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
791 for (i = 0; i < 200; i++) {
792 val = b43_radio_read(dev, B2055_CAL_COUT2);
793 if (val & 0x80) {
794 i = 0;
795 break;
796 }
797 udelay(10);
798 }
799 if (i)
800 b43err(dev->wl, "radio post init timeout\n");
801 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
802 b43_switch_channel(dev, dev->phy.channel);
803 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
804 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
805 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
806 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
807 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
808 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
809 if (!nphy->gain_boost) {
810 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
811 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
812 } else {
813 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
814 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
815 }
816 udelay(2);
817}
818
819/*
820 * Initialize a Broadcom 2055 N-radio
821 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
822 */
823static void b43_radio_init2055(struct b43_wldev *dev)
824{
825 b43_radio_init2055_pre(dev);
826 if (b43_status(dev) < B43_STAT_INITIALIZED) {
827 /* Follow wl, not specs. Do not force uploading all regs */
828 b2055_upload_inittab(dev, 0, 0);
829 } else {
830 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
831 b2055_upload_inittab(dev, ghz5, 0);
832 }
833 b43_radio_init2055_post(dev);
834}
835
8be89535
RM		 836/**************************************************
837 * Samples
838 **************************************************/
839
840/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
841static int b43_nphy_load_samples(struct b43_wldev *dev,
842 struct b43_c32 *samples, u16 len) {
843 struct b43_phy_n *nphy = dev->phy.n;
844 u16 i;
845 u32 *data;
846
847 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
848 if (!data) {
849 b43err(dev->wl, "allocation for samples loading failed\n");
850 return -ENOMEM;
851 }
852 if (nphy->hang_avoid)
853 b43_nphy_stay_in_carrier_search(dev, 1);
854
855 for (i = 0; i < len; i++) {
856 data[i] = (samples[i].i & 0x3FF << 10);
857 data[i] |= samples[i].q & 0x3FF;
858 }
859 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
860
861 kfree(data);
862 if (nphy->hang_avoid)
863 b43_nphy_stay_in_carrier_search(dev, 0);
864 return 0;
865}
866
867/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
868static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
869 bool test)
870{
871 int i;
872 u16 bw, len, rot, angle;
873 struct b43_c32 *samples;
874
875
876 bw = (dev->phy.is_40mhz) ? 40 : 20;
877 len = bw << 3;
878
879 if (test) {
880 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
881 bw = 82;
882 else
883 bw = 80;
884
885 if (dev->phy.is_40mhz)
886 bw <<= 1;
887
888 len = bw << 1;
889 }
890
891 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
892 if (!samples) {
893 b43err(dev->wl, "allocation for samples generation failed\n");
894 return 0;
895 }
896 rot = (((freq * 36) / bw) << 16) / 100;
897 angle = 0;
898
899 for (i = 0; i < len; i++) {
900 samples[i] = b43_cordic(angle);
901 angle += rot;
902 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
903 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
904 }
905
906 i = b43_nphy_load_samples(dev, samples, len);
907 kfree(samples);
908 return (i < 0) ? 0 : len;
909}
910
911/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
912static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
913 u16 wait, bool iqmode, bool dac_test)
914{
915 struct b43_phy_n *nphy = dev->phy.n;
916 int i;
917 u16 seq_mode;
918 u32 tmp;
919
920 if (nphy->hang_avoid)
921 b43_nphy_stay_in_carrier_search(dev, true);
922
923 if ((nphy->bb_mult_save & 0x80000000) == 0) {
924 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
925 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
926 }
927
928 if (!dev->phy.is_40mhz)
929 tmp = 0x6464;
930 else
931 tmp = 0x4747;
932 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
933
934 if (nphy->hang_avoid)
935 b43_nphy_stay_in_carrier_search(dev, false);
936
937 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
938
939 if (loops != 0xFFFF)
940 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
941 else
942 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
943
944 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
945
946 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
947
948 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
949 if (iqmode) {
950 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
951 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
952 } else {
953 if (dac_test)
954 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
955 else
956 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
957 }
958 for (i = 0; i < 100; i++) {
2c8ac7eb 959 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 960 i = 0;
961 break;
962 }
963 udelay(10);
964 }
965 if (i)
966 b43err(dev->wl, "run samples timeout\n");
967
968 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
969}
970
4d9f46ba
RM		 971/**************************************************
972 * RSSI
973 **************************************************/
974
975/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
976static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
977 s8 offset, u8 core, u8 rail,
978 enum b43_nphy_rssi_type type)
979{
980 u16 tmp;
981 bool core1or5 = (core == 1) || (core == 5);
982 bool core2or5 = (core == 2) || (core == 5);
983
984 offset = clamp_val(offset, -32, 31);
985 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
986
987 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
988 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
989 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
990 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
991 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
992 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
993 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
994 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
995
996 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
997 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
998 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
999 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1000 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1001 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1002 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1003 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1004
1005 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1006 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1007 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1008 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1009 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1010 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1011 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1012 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1013
1014 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1015 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1016 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1017 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1018 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1019 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1020 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1021 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1022
1023 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1024 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1025 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1026 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1027 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1028 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1029 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1030 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1031
1032 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1033 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1034 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1035 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1036
1037 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1038 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1039 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1040 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1041}
1042
1043static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1044{
1045 u8 i;
1046 u16 reg, val;
1047
1048 if (code == 0) {
1049 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1050 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1051 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1052 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1053 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1054 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1055 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1056 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1057 } else {
1058 for (i = 0; i < 2; i++) {
1059 if ((code == 1 && i == 1) || (code == 2 && !i))
1060 continue;
1061
1062 reg = (i == 0) ?
1063 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1064 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1065
1066 if (type < 3) {
1067 reg = (i == 0) ?
1068 B43_NPHY_AFECTL_C1 :
1069 B43_NPHY_AFECTL_C2;
1070 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1071
1072 reg = (i == 0) ?
1073 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1074 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1075 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1076
1077 if (type == 0)
1078 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1079 else if (type == 1)
1080 val = 16;
1081 else
1082 val = 32;
1083 b43_phy_set(dev, reg, val);
1084
1085 reg = (i == 0) ?
1086 B43_NPHY_TXF_40CO_B1S0 :
1087 B43_NPHY_TXF_40CO_B32S1;
1088 b43_phy_set(dev, reg, 0x0020);
1089 } else {
1090 if (type == 6)
1091 val = 0x0100;
1092 else if (type == 3)
1093 val = 0x0200;
1094 else
1095 val = 0x0300;
1096
1097 reg = (i == 0) ?
1098 B43_NPHY_AFECTL_C1 :
1099 B43_NPHY_AFECTL_C2;
1100
1101 b43_phy_maskset(dev, reg, 0xFCFF, val);
1102 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1103
1104 if (type != 3 && type != 6) {
1105 enum ieee80211_band band =
1106 b43_current_band(dev->wl);
1107
1108 if (b43_nphy_ipa(dev))
1109 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1110 else
1111 val = 0x11;
1112 reg = (i == 0) ? 0x2000 : 0x3000;
1113 reg |= B2055_PADDRV;
1114 b43_radio_write16(dev, reg, val);
1115
1116 reg = (i == 0) ?
1117 B43_NPHY_AFECTL_OVER1 :
1118 B43_NPHY_AFECTL_OVER;
1119 b43_phy_set(dev, reg, 0x0200);
1120 }
1121 }
1122 }
1123 }
1124}
1125
1126static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1127{
1128 u16 val;
1129
1130 if (type < 3)
1131 val = 0;
1132 else if (type == 6)
1133 val = 1;
1134 else if (type == 3)
1135 val = 2;
1136 else
1137 val = 3;
1138
1139 val = (val << 12) | (val << 14);
1140 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1141 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1142
1143 if (type < 3) {
1144 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1145 (type + 1) << 4);
1146 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1147 (type + 1) << 4);
1148 }
1149
1150 if (code == 0) {
1151 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1152 if (type < 3) {
1153 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1154 ~(B43_NPHY_RFCTL_CMD_RXEN |
1155 B43_NPHY_RFCTL_CMD_CORESEL));
1156 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1157 ~(0x1 << 12 |
1158 0x1 << 5 |
1159 0x1 << 1 |
1160 0x1));
1161 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1162 ~B43_NPHY_RFCTL_CMD_START);
1163 udelay(20);
1164 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1165 }
1166 } else {
1167 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1168 if (type < 3) {
1169 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1170 ~(B43_NPHY_RFCTL_CMD_RXEN |
1171 B43_NPHY_RFCTL_CMD_CORESEL),
1172 (B43_NPHY_RFCTL_CMD_RXEN |
1173 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1174 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1175 (0x1 << 12 |
1176 0x1 << 5 |
1177 0x1 << 1 |
1178 0x1));
1179 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1180 B43_NPHY_RFCTL_CMD_START);
1181 udelay(20);
1182 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1183 }
1184 }
1185}
1186
1187/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1188static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1189{
1190 if (dev->phy.rev >= 3)
1191 b43_nphy_rev3_rssi_select(dev, code, type);
1192 else
1193 b43_nphy_rev2_rssi_select(dev, code, type);
1194}
1195
5ecab603
RM		 1196/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1197static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1198{
1199 int i;
1200 for (i = 0; i < 2; i++) {
1201 if (type == 2) {
1202 if (i == 0) {
1203 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1204 0xFC, buf[0]);
1205 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1206 0xFC, buf[1]);
1207 } else {
1208 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1209 0xFC, buf[2 * i]);
1210 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1211 0xFC, buf[2 * i + 1]);
1212 }
1213 } else {
1214 if (i == 0)
1215 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1216 0xF3, buf[0] << 2);
1217 else
1218 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1219 0xF3, buf[2 * i + 1] << 2);
1220 }
1221 }
1222}
1223
1224/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1225static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1226 u8 nsamp)
1227{
1228 int i;
1229 int out;
1230 u16 save_regs_phy[9];
1231 u16 s[2];
1232
1233 if (dev->phy.rev >= 3) {
1234 save_regs_phy[0] = b43_phy_read(dev,
1235 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1236 save_regs_phy[1] = b43_phy_read(dev,
1237 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1238 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1239 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1240 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1241 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1242 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1243 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1244 save_regs_phy[8] = 0;
1245 } else {
1246 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1247 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1248 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1249 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1250 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1251 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1252 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1253 save_regs_phy[7] = 0;
1254 save_regs_phy[8] = 0;
1255 }
1256
1257 b43_nphy_rssi_select(dev, 5, type);
1258
1259 if (dev->phy.rev < 2) {
1260 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1261 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1262 }
1263
1264 for (i = 0; i < 4; i++)
1265 buf[i] = 0;
1266
1267 for (i = 0; i < nsamp; i++) {
1268 if (dev->phy.rev < 2) {
1269 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1270 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1271 } else {
1272 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1273 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1274 }
1275
1276 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1277 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1278 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1279 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1280 }
1281 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1282 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1283
1284 if (dev->phy.rev < 2)
1285 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1286
1287 if (dev->phy.rev >= 3) {
1288 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1289 save_regs_phy[0]);
1290 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1291 save_regs_phy[1]);
1292 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1293 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1294 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1295 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1296 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1297 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1298 } else {
1299 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1300 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1301 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1302 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1303 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1304 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1305 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1306 }
1307
1308 return out;
1309}
1310
1311/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1312static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1313{
1314 int i, j;
1315 u8 state[4];
1316 u8 code, val;
1317 u16 class, override;
1318 u8 regs_save_radio[2];
1319 u16 regs_save_phy[2];
1320
1321 s8 offset[4];
1322 u8 core;
1323 u8 rail;
1324
1325 u16 clip_state[2];
1326 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1327 s32 results_min[4] = { };
1328 u8 vcm_final[4] = { };
1329 s32 results[4][4] = { };
1330 s32 miniq[4][2] = { };
1331
1332 if (type == 2) {
1333 code = 0;
1334 val = 6;
1335 } else if (type < 2) {
1336 code = 25;
1337 val = 4;
1338 } else {
1339 B43_WARN_ON(1);
1340 return;
1341 }
1342
1343 class = b43_nphy_classifier(dev, 0, 0);
1344 b43_nphy_classifier(dev, 7, 4);
1345 b43_nphy_read_clip_detection(dev, clip_state);
1346 b43_nphy_write_clip_detection(dev, clip_off);
1347
1348 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1349 override = 0x140;
1350 else
1351 override = 0x110;
1352
1353 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1354 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1355 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1356 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1357
1358 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1359 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1360 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1361 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1362
1363 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1364 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1365 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1366 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1367 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1368 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1369
1370 b43_nphy_rssi_select(dev, 5, type);
1371 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1372 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1373
1374 for (i = 0; i < 4; i++) {
1375 u8 tmp[4];
1376 for (j = 0; j < 4; j++)
1377 tmp[j] = i;
1378 if (type != 1)
1379 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1380 b43_nphy_poll_rssi(dev, type, results[i], 8);
1381 if (type < 2)
1382 for (j = 0; j < 2; j++)
1383 miniq[i][j] = min(results[i][2 * j],
1384 results[i][2 * j + 1]);
1385 }
1386
1387 for (i = 0; i < 4; i++) {
1388 s32 mind = 40;
1389 u8 minvcm = 0;
1390 s32 minpoll = 249;
1391 s32 curr;
1392 for (j = 0; j < 4; j++) {
1393 if (type == 2)
1394 curr = abs(results[j][i]);
1395 else
1396 curr = abs(miniq[j][i / 2] - code * 8);
1397
1398 if (curr < mind) {
1399 mind = curr;
1400 minvcm = j;
1401 }
1402
1403 if (results[j][i] < minpoll)
1404 minpoll = results[j][i];
1405 }
1406 results_min[i] = minpoll;
1407 vcm_final[i] = minvcm;
1408 }
1409
1410 if (type != 1)
1411 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1412
1413 for (i = 0; i < 4; i++) {
1414 offset[i] = (code * 8) - results[vcm_final[i]][i];
1415
1416 if (offset[i] < 0)
1417 offset[i] = -((abs(offset[i]) + 4) / 8);
1418 else
1419 offset[i] = (offset[i] + 4) / 8;
1420
1421 if (results_min[i] == 248)
1422 offset[i] = code - 32;
1423
1424 core = (i / 2) ? 2 : 1;
1425 rail = (i % 2) ? 1 : 0;
1426
1427 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1428 type);
1429 }
1430
1431 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1432 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1433
1434 switch (state[2]) {
1435 case 1:
1436 b43_nphy_rssi_select(dev, 1, 2);
1437 break;
1438 case 4:
1439 b43_nphy_rssi_select(dev, 1, 0);
1440 break;
1441 case 2:
1442 b43_nphy_rssi_select(dev, 1, 1);
1443 break;
1444 default:
1445 b43_nphy_rssi_select(dev, 1, 1);
1446 break;
1447 }
1448
1449 switch (state[3]) {
1450 case 1:
1451 b43_nphy_rssi_select(dev, 2, 2);
1452 break;
1453 case 4:
1454 b43_nphy_rssi_select(dev, 2, 0);
1455 break;
1456 default:
1457 b43_nphy_rssi_select(dev, 2, 1);
1458 break;
1459 }
1460
1461 b43_nphy_rssi_select(dev, 0, type);
1462
1463 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1464 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1465 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1466 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1467
1468 b43_nphy_classifier(dev, 7, class);
1469 b43_nphy_write_clip_detection(dev, clip_state);
1470 /* Specs don't say about reset here, but it makes wl and b43 dumps
1471 identical, it really seems wl performs this */
1472 b43_nphy_reset_cca(dev);
1473}
1474
1475/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1476static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1477{
1478 /* TODO */
1479}
1480
1481/*
1482 * RSSI Calibration
1483 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1484 */
1485static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1486{
1487 if (dev->phy.rev >= 3) {
1488 b43_nphy_rev3_rssi_cal(dev);
1489 } else {
1490 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1491 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1492 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1493 }
1494}
1495
64712095
RM		 1496/**************************************************
1497 * Workarounds
1498 **************************************************/
1499
1500static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1501{
1502 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1503
1504 bool ghz5;
1505 bool ext_lna;
1506 u16 rssi_gain;
1507 struct nphy_gain_ctl_workaround_entry *e;
1508 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1509 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1510
1511 /* Prepare values */
1512 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1513 & B43_NPHY_BANDCTL_5GHZ;
1514 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1515 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1516 if (ghz5 && dev->phy.rev >= 5)
1517 rssi_gain = 0x90;
1518 else
1519 rssi_gain = 0x50;
1520
1521 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1522
1523 /* Set Clip 2 detect */
1524 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1525 B43_NPHY_C1_CGAINI_CL2DETECT);
1526 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1527 B43_NPHY_C2_CGAINI_CL2DETECT);
1528
1529 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1530 0x17);
1531 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1532 0x17);
1533 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1534 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1535 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1536 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1537 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1538 rssi_gain);
1539 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1540 rssi_gain);
1541 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1542 0x17);
1543 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1544 0x17);
1545 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1546 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1547
1548 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1549 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1550 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1551 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1552 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1553 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1554 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1555 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1556 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1557 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1558 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1559 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1560
1561 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1562 b43_phy_write(dev, 0x2A7, e->init_gain);
1563 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1564 e->rfseq_init);
1565 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1566
1567 /* TODO: check defines. Do not match variables names */
1568 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1569 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1570 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1571 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1572 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1573 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1574
1575 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1576 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1577 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1578 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1579 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1580 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1581 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1582 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1583 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1584 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1585}
1586
1587static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1588{
1589 struct b43_phy_n *nphy = dev->phy.n;
1590
1591 u8 i, j;
1592 u8 code;
1593 u16 tmp;
1594 u8 rfseq_events[3] = { 6, 8, 7 };
1595 u8 rfseq_delays[3] = { 10, 30, 1 };
1596
1597 /* Set Clip 2 detect */
1598 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1599 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1600
1601 /* Set narrowband clip threshold */
1602 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1603 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1604
1605 if (!dev->phy.is_40mhz) {
1606 /* Set dwell lengths */
1607 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1608 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1609 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1610 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1611 }
1612
1613 /* Set wideband clip 2 threshold */
1614 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1615 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
1616 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1617 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
1618
1619 if (!dev->phy.is_40mhz) {
1620 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1621 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1622 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1623 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1624 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1625 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1626 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1627 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1628 }
1629
1630 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1631
1632 if (nphy->gain_boost) {
1633 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1634 dev->phy.is_40mhz)
1635 code = 4;
1636 else
1637 code = 5;
1638 } else {
1639 code = dev->phy.is_40mhz ? 6 : 7;
1640 }
1641
1642 /* Set HPVGA2 index */
1643 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
1644 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1645 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
1646 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1647
1648 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1649 /* specs say about 2 loops, but wl does 4 */
1650 for (i = 0; i < 4; i++)
1651 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
1652
1653 b43_nphy_adjust_lna_gain_table(dev);
1654
1655 if (nphy->elna_gain_config) {
1656 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1657 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1659 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1660 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1661
1662 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1663 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1664 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1665 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1666 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1667
1668 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1669 /* specs say about 2 loops, but wl does 4 */
1670 for (i = 0; i < 4; i++)
1671 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1672 (code << 8 | 0x74));
1673 }
1674
1675 if (dev->phy.rev == 2) {
1676 for (i = 0; i < 4; i++) {
1677 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1678 (0x0400 * i) + 0x0020);
1679 for (j = 0; j < 21; j++) {
1680 tmp = j * (i < 2 ? 3 : 1);
1681 b43_phy_write(dev,
1682 B43_NPHY_TABLE_DATALO, tmp);
1683 }
1684 }
1685 }
1686
1687 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
1688 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1689 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1690 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1691
1692 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1693 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
1694}
1695
1696/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1697static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
1698{
1699 if (dev->phy.rev >= 3)
1700 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
1701 else
1702 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
1703}
1704
3ccd0957
RM		 1705static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1706{
1707 struct b43_phy_n *nphy = dev->phy.n;
1708 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1709
1710 /* TX to RX */
1711 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1712 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1713 /* RX to TX */
1714 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1715 0x1F };
1716 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1717 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1718 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1719
1720 u16 tmp16;
1721 u32 tmp32;
1722
1723 b43_phy_write(dev, 0x23f, 0x1f8);
1724 b43_phy_write(dev, 0x240, 0x1f8);
1725
1726 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1727 tmp32 &= 0xffffff;
1728 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1729
1730 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1731 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1732 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1733 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1734 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1735 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1736
1737 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1738 b43_phy_write(dev, 0x2AE, 0x000C);
1739
1740 /* TX to RX */
1741 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1742 ARRAY_SIZE(tx2rx_events));
1743
1744 /* RX to TX */
1745 if (b43_nphy_ipa(dev))
1746 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1747 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1748 if (nphy->hw_phyrxchain != 3 &&
1749 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1750 if (b43_nphy_ipa(dev)) {
1751 rx2tx_delays[5] = 59;
1752 rx2tx_delays[6] = 1;
1753 rx2tx_events[7] = 0x1F;
1754 }
1755 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1756 ARRAY_SIZE(rx2tx_events));
1757 }
1758
1759 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1760 0x2 : 0x9C40;
1761 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1762
1763 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1764
1765 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1766 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1767
1768 b43_nphy_gain_ctl_workarounds(dev);
1769
1770 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1771 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1772
1773 /* TODO */
1774
1775 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1776 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1777 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1778 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1779 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1780 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1781 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1782 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1783 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1784 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1785 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1786 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1787
1788 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1789
1790 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1791 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1792 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1793 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1794 tmp32 = 0x00088888;
1795 else
1796 tmp32 = 0x88888888;
1797 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1798 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1799 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1800
1801 if (dev->phy.rev == 4 &&
1802 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1803 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1804 0x70);
1805 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1806 0x70);
1807 }
1808
1809 b43_phy_write(dev, 0x224, 0x03eb);
1810 b43_phy_write(dev, 0x225, 0x03eb);
1811 b43_phy_write(dev, 0x226, 0x0341);
1812 b43_phy_write(dev, 0x227, 0x0341);
1813 b43_phy_write(dev, 0x228, 0x042b);
1814 b43_phy_write(dev, 0x229, 0x042b);
1815 b43_phy_write(dev, 0x22a, 0x0381);
1816 b43_phy_write(dev, 0x22b, 0x0381);
1817 b43_phy_write(dev, 0x22c, 0x042b);
1818 b43_phy_write(dev, 0x22d, 0x042b);
1819 b43_phy_write(dev, 0x22e, 0x0381);
1820 b43_phy_write(dev, 0x22f, 0x0381);
1821}
1822
1823static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1824{
1825 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1826 struct b43_phy *phy = &dev->phy;
1827 struct b43_phy_n *nphy = phy->n;
1828
1829 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1830 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1831
1832 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1833 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1834
1835 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1836 nphy->band5g_pwrgain) {
1837 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1838 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1839 } else {
1840 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1841 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1842 }
1843
1844 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1845 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1846 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1847 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1848
1849 if (dev->phy.rev < 2) {
1850 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1851 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1852 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1853 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1854 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1855 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1856 }
1857
1858 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1859 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1860 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1861 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1862
1863 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1864 dev->dev->board_type == 0x8B) {
1865 delays1[0] = 0x1;
1866 delays1[5] = 0x14;
1867 }
1868 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1869 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1870
1871 b43_nphy_gain_ctl_workarounds(dev);
1872
1873 if (dev->phy.rev < 2) {
1874 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1875 b43_hf_write(dev, b43_hf_read(dev) |
1876 B43_HF_MLADVW);
1877 } else if (dev->phy.rev == 2) {
1878 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1879 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1880 }
1881
1882 if (dev->phy.rev < 2)
1883 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1884 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1885
1886 /* Set phase track alpha and beta */
1887 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1888 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1889 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1890 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1891 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1892 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1893
1894 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1895 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1896 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1897 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1898 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1899
1900 if (dev->phy.rev == 2)
1901 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1902 B43_NPHY_FINERX2_CGC_DECGC);
1903}
1904
1905/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1906static void b43_nphy_workarounds(struct b43_wldev *dev)
1907{
1908 struct b43_phy *phy = &dev->phy;
1909 struct b43_phy_n *nphy = phy->n;
1910
1911 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1912 b43_nphy_classifier(dev, 1, 0);
1913 else
1914 b43_nphy_classifier(dev, 1, 1);
1915
1916 if (nphy->hang_avoid)
1917 b43_nphy_stay_in_carrier_search(dev, 1);
1918
1919 b43_phy_set(dev, B43_NPHY_IQFLIP,
1920 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1921
1922 if (dev->phy.rev >= 3)
1923 b43_nphy_workarounds_rev3plus(dev);
1924 else
1925 b43_nphy_workarounds_rev1_2(dev);
1926
1927 if (nphy->hang_avoid)
1928 b43_nphy_stay_in_carrier_search(dev, 0);
1929}
1930
9dd4d9b9
RM		 1931/**************************************************
1932 * Tx/Rx common
1933 **************************************************/
1934
1935/*
1936 * Transmits a known value for LO calibration
1937 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1938 */
1939static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1940 bool iqmode, bool dac_test)
1941{
1942 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1943 if (samp == 0)
1944 return -1;
1945 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1946 return 0;
1947}
1948
1949/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
1950static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
1951{
1952 struct b43_phy_n *nphy = dev->phy.n;
1953
1954 bool override = false;
1955 u16 chain = 0x33;
1956
1957 if (nphy->txrx_chain == 0) {
1958 chain = 0x11;
1959 override = true;
1960 } else if (nphy->txrx_chain == 1) {
1961 chain = 0x22;
1962 override = true;
1963 }
1964
1965 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1966 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
1967 chain);
1968
1969 if (override)
1970 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1971 B43_NPHY_RFSEQMODE_CAOVER);
1972 else
1973 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1974 ~B43_NPHY_RFSEQMODE_CAOVER);
1975}
1976
1977/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1978static void b43_nphy_stop_playback(struct b43_wldev *dev)
1979{
1980 struct b43_phy_n *nphy = dev->phy.n;
1981 u16 tmp;
1982
1983 if (nphy->hang_avoid)
1984 b43_nphy_stay_in_carrier_search(dev, 1);
1985
1986 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1987 if (tmp & 0x1)
1988 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1989 else if (tmp & 0x2)
1990 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1991
1992 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1993
1994 if (nphy->bb_mult_save & 0x80000000) {
1995 tmp = nphy->bb_mult_save & 0xFFFF;
1996 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1997 nphy->bb_mult_save = 0;
1998 }
1999
2000 if (nphy->hang_avoid)
2001 b43_nphy_stay_in_carrier_search(dev, 0);
2002}
2003
2004/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2005static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2006 struct nphy_txgains target,
2007 struct nphy_iqcal_params *params)
2008{
2009 int i, j, indx;
2010 u16 gain;
2011
2012 if (dev->phy.rev >= 3) {
2013 params->txgm = target.txgm[core];
2014 params->pga = target.pga[core];
2015 params->pad = target.pad[core];
2016 params->ipa = target.ipa[core];
2017 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2018 (params->pad << 4) | (params->ipa);
2019 for (j = 0; j < 5; j++)
2020 params->ncorr[j] = 0x79;
2021 } else {
2022 gain = (target.pad[core]) | (target.pga[core] << 4) |
2023 (target.txgm[core] << 8);
2024
2025 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2026 1 : 0;
2027 for (i = 0; i < 9; i++)
2028 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2029 break;
2030 i = min(i, 8);
2031
2032 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2033 params->pga = tbl_iqcal_gainparams[indx][i][2];
2034 params->pad = tbl_iqcal_gainparams[indx][i][3];
2035 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2036 (params->pad << 2);
2037 for (j = 0; j < 4; j++)
2038 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2039 }
2040}
2041
884a5228 2042/**************************************************
104cfa88 2043 * Tx and Rx
884a5228
RM		 2044 **************************************************/
2045
2046void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
2047{//TODO
2048}
2049
2050static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2051{//TODO
2052}
2053
2054static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2055 bool ignore_tssi)
2056{//TODO
2057 return B43_TXPWR_RES_DONE;
2058}
2059
161d540c
RM		 2060/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2061static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2062{
2063 struct b43_phy_n *nphy = dev->phy.n;
2064 u8 i;
c9c0d9ec
RM		 2065 u16 bmask, val, tmp;
2066 enum ieee80211_band band = b43_current_band(dev->wl);
161d540c
RM		 2067
2068 if (nphy->hang_avoid)
2069 b43_nphy_stay_in_carrier_search(dev, 1);
2070
2071 nphy->txpwrctrl = enable;
2072 if (!enable) {
c9c0d9ec
RM		 2073 if (dev->phy.rev >= 3 &&
2074 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2075 (B43_NPHY_TXPCTL_CMD_COEFF |
2076 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2077 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2078 /* We disable enabled TX pwr ctl, save it's state */
2079 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2080 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2081 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2082 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2083 }
161d540c
RM		 2084
2085 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2086 for (i = 0; i < 84; i++)
2087 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2088
2089 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2090 for (i = 0; i < 84; i++)
2091 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2092
2093 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2094 if (dev->phy.rev >= 3)
2095 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2096 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2097
2098 if (dev->phy.rev >= 3) {
2099 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2100 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2101 } else {
2102 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2103 }
2104
2105 if (dev->phy.rev == 2)
2106 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2107 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2108 else if (dev->phy.rev < 2)
2109 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2110 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2111
c9c0d9ec
RM		 2112 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2113 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 2114 } else {
c9c0d9ec
RM		 2115 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2116 nphy->adj_pwr_tbl);
2117 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2118 nphy->adj_pwr_tbl);
2119
2120 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2121 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2122 /* wl does useless check for "enable" param here */
2123 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2124 if (dev->phy.rev >= 3) {
2125 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2126 if (val)
2127 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2128 }
2129 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2130
2131 if (band == IEEE80211_BAND_5GHZ) {
2132 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2133 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2134 if (dev->phy.rev > 1)
2135 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2136 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2137 0x64);
2138 }
2139
2140 if (dev->phy.rev >= 3) {
2141 if (nphy->tx_pwr_idx[0] != 128 &&
2142 nphy->tx_pwr_idx[1] != 128) {
2143 /* Recover TX pwr ctl state */
2144 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2145 ~B43_NPHY_TXPCTL_CMD_INIT,
2146 nphy->tx_pwr_idx[0]);
2147 if (dev->phy.rev > 1)
2148 b43_phy_maskset(dev,
2149 B43_NPHY_TXPCTL_INIT,
2150 ~0xff, nphy->tx_pwr_idx[1]);
2151 }
2152 }
2153
2154 if (dev->phy.rev >= 3) {
2155 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2156 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2157 } else {
2158 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2159 }
2160
2161 if (dev->phy.rev == 2)
2162 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2163 else if (dev->phy.rev < 2)
2164 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2165
2166 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2167 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2168
c002831a 2169 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 2170 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2171 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2172 }
161d540c
RM		 2173 }
2174
2175 if (nphy->hang_avoid)
2176 b43_nphy_stay_in_carrier_search(dev, 0);
2177}
2178
2179/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314
MB		 2180static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2181{
161d540c 2182 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2183 struct ssb_sprom *sprom = dev->dev->bus_sprom;
161d540c
RM		 2184
2185 u8 txpi[2], bbmult, i;
2186 u16 tmp, radio_gain, dac_gain;
2187 u16 freq = dev->phy.channel_freq;
2188 u32 txgain;
2189 /* u32 gaintbl; rev3+ */
2190
2191 if (nphy->hang_avoid)
2192 b43_nphy_stay_in_carrier_search(dev, 1);
2193
dd5f13b8
RM		 2194 if (dev->phy.rev >= 7) {
2195 txpi[0] = txpi[1] = 30;
2196 } else if (dev->phy.rev >= 3) {
161d540c
RM		 2197 txpi[0] = 40;
2198 txpi[1] = 40;
2199 } else if (sprom->revision < 4) {
2200 txpi[0] = 72;
2201 txpi[1] = 72;
2202 } else {
2203 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2204 txpi[0] = sprom->txpid2g[0];
2205 txpi[1] = sprom->txpid2g[1];
2206 } else if (freq >= 4900 && freq < 5100) {
2207 txpi[0] = sprom->txpid5gl[0];
2208 txpi[1] = sprom->txpid5gl[1];
2209 } else if (freq >= 5100 && freq < 5500) {
2210 txpi[0] = sprom->txpid5g[0];
2211 txpi[1] = sprom->txpid5g[1];
2212 } else if (freq >= 5500) {
2213 txpi[0] = sprom->txpid5gh[0];
2214 txpi[1] = sprom->txpid5gh[1];
2215 } else {
2216 txpi[0] = 91;
2217 txpi[1] = 91;
2218 }
2219 }
dd5f13b8
RM		 2220 if (dev->phy.rev < 7 &&
2221 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
2222 txpi[0] = txpi[1] = 91;
161d540c
RM		 2223
2224 /*
2225 for (i = 0; i < 2; i++) {
2226 nphy->txpwrindex[i].index_internal = txpi[i];
2227 nphy->txpwrindex[i].index_internal_save = txpi[i];
2228 }
2229 */
2230
2231 for (i = 0; i < 2; i++) {
2232 if (dev->phy.rev >= 3) {
dd5f13b8
RM		 2233 if (b43_nphy_ipa(dev)) {
2234 txgain = *(b43_nphy_get_ipa_gain_table(dev) +
2235 txpi[i]);
2236 } else if (b43_current_band(dev->wl) ==
2237 IEEE80211_BAND_5GHZ) {
2238 /* FIXME: use 5GHz tables */
2239 txgain =
2240 b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
2241 } else {
2242 if (dev->phy.rev >= 5 &&
2243 sprom->fem.ghz5.extpa_gain == 3)
2244 ; /* FIXME: 5GHz_txgain_HiPwrEPA */
2245 txgain =
2246 b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
2247 }
161d540c
RM		 2248 radio_gain = (txgain >> 16) & 0x1FFFF;
2249 } else {
2250 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
2251 radio_gain = (txgain >> 16) & 0x1FFF;
2252 }
2253
dd5f13b8
RM		 2254 if (dev->phy.rev >= 7)
2255 dac_gain = (txgain >> 8) & 0x7;
2256 else
2257 dac_gain = (txgain >> 8) & 0x3F;
161d540c
RM		 2258 bbmult = txgain & 0xFF;
2259
2260 if (dev->phy.rev >= 3) {
2261 if (i == 0)
2262 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2263 else
2264 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2265 } else {
2266 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2267 }
2268
2269 if (i == 0)
2270 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2271 else
2272 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
2273
44f4008b 2274 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
161d540c 2275
44f4008b 2276 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 2277 if (i == 0)
2278 tmp = (tmp & 0x00FF) | (bbmult << 8);
2279 else
2280 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 2281 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 2282
0eff8fcd
RM		 2283 if (b43_nphy_ipa(dev)) {
2284 u32 tmp32;
2285 u16 reg = (i == 0) ?
2286 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 2287 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
2288 576 + txpi[i]));
0eff8fcd
RM		 2289 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
2290 b43_phy_set(dev, reg, 0x4);
2291 }
161d540c
RM		 2292 }
2293
2294 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
2295
2296 if (nphy->hang_avoid)
2297 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 2298}
2299
0eff8fcd
RM		 2300static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
2301{
2302 struct b43_phy *phy = &dev->phy;
2303
2304 const u32 *table = NULL;
2305#if 0
2306 TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
2307 u32 rfpwr_offset;
2308 u8 pga_gain;
2309 int i;
2310#endif
2311
2312 if (phy->rev >= 3) {
2313 if (b43_nphy_ipa(dev)) {
2314 table = b43_nphy_get_ipa_gain_table(dev);
2315 } else {
2316 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2317 if (phy->rev == 3)
2318 table = b43_ntab_tx_gain_rev3_5ghz;
2319 if (phy->rev == 4)
2320 table = b43_ntab_tx_gain_rev4_5ghz;
2321 else
2322 table = b43_ntab_tx_gain_rev5plus_5ghz;
2323 } else {
2324 table = b43_ntab_tx_gain_rev3plus_2ghz;
2325 }
2326 }
2327 } else {
2328 table = b43_ntab_tx_gain_rev0_1_2;
2329 }
2330 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
2331 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
2332
2333 if (phy->rev >= 3) {
2334#if 0
2335 nphy->gmval = (table[0] >> 16) & 0x7000;
2336
2337 for (i = 0; i < 128; i++) {
2338 pga_gain = (table[i] >> 24) & 0xF;
2339 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2340 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
2341 else
2342 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
2343 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
2344 rfpwr_offset);
2345 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
2346 rfpwr_offset);
2347 }
2348#endif
2349 }
2350}
7955de0c 2351
e50cbcf6
RM		 2352/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
2353static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
2354{
2355 struct b43_phy_n *nphy = dev->phy.n;
2356 enum ieee80211_band band;
2357 u16 tmp;
2358
2359 if (!enable) {
2360 nphy->rfctrl_intc1_save = b43_phy_read(dev,
2361 B43_NPHY_RFCTL_INTC1);
2362 nphy->rfctrl_intc2_save = b43_phy_read(dev,
2363 B43_NPHY_RFCTL_INTC2);
2364 band = b43_current_band(dev->wl);
2365 if (dev->phy.rev >= 3) {
2366 if (band == IEEE80211_BAND_5GHZ)
2367 tmp = 0x600;
2368 else
2369 tmp = 0x480;
2370 } else {
2371 if (band == IEEE80211_BAND_5GHZ)
2372 tmp = 0x180;
2373 else
2374 tmp = 0x120;
2375 }
2376 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2377 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2378 } else {
2379 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
2380 nphy->rfctrl_intc1_save);
2381 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
2382 nphy->rfctrl_intc2_save);
2383 }
2384}
2385
fe3e46e8
RM		 2386/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
2387static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
2388{
fe3e46e8 2389 u16 tmp;
fe3e46e8
RM		 2390
2391 if (dev->phy.rev >= 3) {
c002831a 2392 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 2393 tmp = 4;
2394 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
2395 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2396 }
2397
2398 tmp = 1;
2399 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
2400 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2401 }
2402}
2403
2faa6b83
RM		 2404/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
2405static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
2406 u16 samps, u8 time, bool wait)
2407{
2408 int i;
2409 u16 tmp;
2410
2411 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
2412 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
2413 if (wait)
2414 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
2415 else
2416 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
2417
2418 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
2419
2420 for (i = 1000; i; i--) {
2421 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
2422 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
2423 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
2424 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
2425 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
2426 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
2427 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
2428 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
2429
2430 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
2431 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
2432 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
2433 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
2434 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
2435 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
2436 return;
2437 }
2438 udelay(10);
2439 }
2440 memset(est, 0, sizeof(*est));
2441}
2442
a67162ab
RM		 2443/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
2444static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
2445 struct b43_phy_n_iq_comp *pcomp)
2446{
2447 if (write) {
2448 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
2449 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
2450 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
2451 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
2452 } else {
2453 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
2454 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
2455 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
2456 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
2457 }
2458}
2459
c7455cf9
RM		 2460#if 0
2461/* Ready but not used anywhere */
026816fc
RM		 2462/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
2463static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
2464{
2465 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2466
2467 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
2468 if (core == 0) {
2469 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
2470 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2471 } else {
2472 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2473 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2474 }
2475 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
2476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
2477 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
2478 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
2479 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
2480 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
2481 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2482 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2483}
2484
2485/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
2486static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
2487{
2488 u8 rxval, txval;
2489 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2490
2491 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2492 if (core == 0) {
2493 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2494 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2495 } else {
2496 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2497 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2498 }
2499 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2500 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2501 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2502 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2503 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
2504 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2505 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2506 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2507
2508 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2509 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2510
acd82aa8
LF		 2511 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2512 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 2513 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2514 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2515 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
2516 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
2517 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
2518 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
2519 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
2520
2521 if (core == 0) {
2522 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
2523 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
2524 } else {
2525 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
2526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
2527 }
2528
67cbc3ed
RM		 2529 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
2530 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 2531 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 2532
2533 if (core == 0) {
2534 rxval = 1;
2535 txval = 8;
2536 } else {
2537 rxval = 4;
2538 txval = 2;
2539 }
67cbc3ed
RM		 2540 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
2541 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc 2542}
c7455cf9 2543#endif
026816fc 2544
34a56f2c
RM		 2545/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
2546static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
2547{
2548 int i;
2549 s32 iq;
2550 u32 ii;
2551 u32 qq;
2552 int iq_nbits, qq_nbits;
2553 int arsh, brsh;
2554 u16 tmp, a, b;
2555
2556 struct nphy_iq_est est;
2557 struct b43_phy_n_iq_comp old;
2558 struct b43_phy_n_iq_comp new = { };
2559 bool error = false;
2560
2561 if (mask == 0)
2562 return;
2563
2564 b43_nphy_rx_iq_coeffs(dev, false, &old);
2565 b43_nphy_rx_iq_coeffs(dev, true, &new);
2566 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
2567 new = old;
2568
2569 for (i = 0; i < 2; i++) {
2570 if (i == 0 && (mask & 1)) {
2571 iq = est.iq0_prod;
2572 ii = est.i0_pwr;
2573 qq = est.q0_pwr;
2574 } else if (i == 1 && (mask & 2)) {
2575 iq = est.iq1_prod;
2576 ii = est.i1_pwr;
2577 qq = est.q1_pwr;
2578 } else {
34a56f2c
RM		 2579 continue;
2580 }
2581
2582 if (ii + qq < 2) {
2583 error = true;
2584 break;
2585 }
2586
2587 iq_nbits = fls(abs(iq));
2588 qq_nbits = fls(qq);
2589
2590 arsh = iq_nbits - 20;
2591 if (arsh >= 0) {
2592 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
2593 tmp = ii >> arsh;
2594 } else {
2595 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
2596 tmp = ii << -arsh;
2597 }
2598 if (tmp == 0) {
2599 error = true;
2600 break;
2601 }
2602 a /= tmp;
2603
2604 brsh = qq_nbits - 11;
2605 if (brsh >= 0) {
2606 b = (qq << (31 - qq_nbits));
2607 tmp = ii >> brsh;
2608 } else {
2609 b = (qq << (31 - qq_nbits));
2610 tmp = ii << -brsh;
2611 }
2612 if (tmp == 0) {
2613 error = true;
2614 break;
2615 }
2616 b = int_sqrt(b / tmp - a * a) - (1 << 10);
2617
2618 if (i == 0 && (mask & 0x1)) {
2619 if (dev->phy.rev >= 3) {
2620 new.a0 = a & 0x3FF;
2621 new.b0 = b & 0x3FF;
2622 } else {
2623 new.a0 = b & 0x3FF;
2624 new.b0 = a & 0x3FF;
2625 }
2626 } else if (i == 1 && (mask & 0x2)) {
2627 if (dev->phy.rev >= 3) {
2628 new.a1 = a & 0x3FF;
2629 new.b1 = b & 0x3FF;
2630 } else {
2631 new.a1 = b & 0x3FF;
2632 new.b1 = a & 0x3FF;
2633 }
2634 }
2635 }
2636
2637 if (error)
2638 new = old;
2639
2640 b43_nphy_rx_iq_coeffs(dev, true, &new);
2641}
2642
09146400
RM		 2643/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
2644static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
2645{
2646 u16 array[4];
44f4008b 2647 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 2648
2649 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
2650 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
2651 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
2652 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
2653}
2654
9442e5b5
RM		 2655/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
2656static void b43_nphy_spur_workaround(struct b43_wldev *dev)
2657{
2658 struct b43_phy_n *nphy = dev->phy.n;
2659
204a665b 2660 u8 channel = dev->phy.channel;
9442e5b5
RM		 2661 int tone[2] = { 57, 58 };
2662 u32 noise[2] = { 0x3FF, 0x3FF };
2663
2664 B43_WARN_ON(dev->phy.rev < 3);
2665
2666 if (nphy->hang_avoid)
2667 b43_nphy_stay_in_carrier_search(dev, 1);
2668
9442e5b5
RM		 2669 if (nphy->gband_spurwar_en) {
2670 /* TODO: N PHY Adjust Analog Pfbw (7) */
2671 if (channel == 11 && dev->phy.is_40mhz)
2672 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
2673 else
2674 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
2675 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
2676 }
2677
2678 if (nphy->aband_spurwar_en) {
2679 if (channel == 54) {
2680 tone[0] = 0x20;
2681 noise[0] = 0x25F;
2682 } else if (channel == 38 || channel == 102 || channel == 118) {
2683 if (0 /* FIXME */) {
2684 tone[0] = 0x20;
2685 noise[0] = 0x21F;
2686 } else {
2687 tone[0] = 0;
2688 noise[0] = 0;
2689 }
2690 } else if (channel == 134) {
2691 tone[0] = 0x20;
2692 noise[0] = 0x21F;
2693 } else if (channel == 151) {
2694 tone[0] = 0x10;
2695 noise[0] = 0x23F;
2696 } else if (channel == 153 || channel == 161) {
2697 tone[0] = 0x30;
2698 noise[0] = 0x23F;
2699 } else {
2700 tone[0] = 0;
2701 noise[0] = 0;
2702 }
2703
2704 if (!tone[0] && !noise[0])
2705 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
2706 else
2707 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
2708 }
2709
2710 if (nphy->hang_avoid)
2711 b43_nphy_stay_in_carrier_search(dev, 0);
2712}
2713
5ecab603
RM		 2714/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
2715static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
2716{
2717 struct b43_phy_n *nphy = dev->phy.n;
2718 int i, j;
2719 u32 tmp;
2720 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 2721
5ecab603 2722 u16 buffer[7];
90b9738d 2723
5ecab603
RM		 2724 if (nphy->hang_avoid)
2725 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 2726
5ecab603 2727 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 2728
5ecab603
RM		 2729 for (i = 0; i < 2; i++) {
2730 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
2731 (buffer[i * 2 + 1] & 0x3FF);
2732 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2733 (((i + 26) << 10) | 320));
2734 for (j = 0; j < 128; j++) {
2735 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2736 ((tmp >> 16) & 0xFFFF));
2737 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2738 (tmp & 0xFFFF));
90b9738d 2739 }
90b9738d
RM		 2740 }
2741
5ecab603
RM		 2742 for (i = 0; i < 2; i++) {
2743 tmp = buffer[5 + i];
2744 real_part = (tmp >> 8) & 0xFF;
2745 imag_part = (tmp & 0xFF);
2746 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2747 (((i + 26) << 10) | 448));
90b9738d 2748
5ecab603
RM		 2749 if (dev->phy.rev >= 3) {
2750 cur_real = real_part;
2751 cur_imag = imag_part;
2752 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
2753 }
90b9738d 2754
5ecab603
RM		 2755 for (j = 0; j < 128; j++) {
2756 if (dev->phy.rev < 3) {
2757 cur_real = (real_part * loscale[j] + 128) >> 8;
2758 cur_imag = (imag_part * loscale[j] + 128) >> 8;
2759 tmp = ((cur_real & 0xFF) << 8) |
2760 (cur_imag & 0xFF);
2761 }
2762 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2763 ((tmp >> 16) & 0xFFFF));
2764 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2765 (tmp & 0xFFFF));
2766 }
90b9738d
RM		 2767 }
2768
5ecab603
RM		 2769 if (dev->phy.rev >= 3) {
2770 b43_shm_write16(dev, B43_SHM_SHARED,
2771 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2772 b43_shm_write16(dev, B43_SHM_SHARED,
2773 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
90b9738d
RM		 2774 }
2775
5ecab603
RM		 2776 if (nphy->hang_avoid)
2777 b43_nphy_stay_in_carrier_search(dev, false);
4cb99775
RM		 2778}
2779
42e1547e
RM		 2780/*
2781 * Restore RSSI Calibration
2782 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2783 */
2784static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2785{
2786 struct b43_phy_n *nphy = dev->phy.n;
2787
2788 u16 *rssical_radio_regs = NULL;
2789 u16 *rssical_phy_regs = NULL;
2790
2791 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2792 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 2793 return;
2794 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2795 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2796 } else {
204a665b 2797 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 2798 return;
2799 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2800 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2801 }
2802
2803 /* TODO use some definitions */
2804 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2805 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2806
2807 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2808 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2809 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2810 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2811
2812 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2813 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2814 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2815 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2816
2817 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2818 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2819 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2820 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2821}
2822
c4a92003
RM		 2823/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2824static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2825{
2826 struct b43_phy_n *nphy = dev->phy.n;
2827 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2828 u16 tmp;
2829 u8 offset, i;
c4a92003
RM		 2830
2831 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2832 for (i = 0; i < 2; i++) {
2833 tmp = (i == 0) ? 0x2000 : 0x3000;
2834 offset = i * 11;
2835
2836 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2837 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2838 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2839 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2840 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2841 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2842 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2843 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2844 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2845 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2846 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2847
2848 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2849 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2850 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2851 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2852 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2853 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2854 if (nphy->ipa5g_on) {
2855 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2856 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2857 } else {
2858 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2859 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2860 }
2861 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2862 } else {
2863 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2864 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2865 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2866 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2867 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2868 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2869 if (nphy->ipa2g_on) {
2870 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2871 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2872 (dev->phy.rev < 5) ? 0x11 : 0x01);
2873 } else {
2874 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2875 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2876 }
2877 }
2878 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2879 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2880 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2881 }
c4a92003
RM		 2882 } else {
2883 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2884 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2885
2886 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2887 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2888
2889 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2890 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2891
2892 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2893 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2894
2895 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2896 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2897
2898 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2899 B43_NPHY_BANDCTL_5GHZ)) {
2900 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2901 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2902 } else {
2903 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2904 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2905 }
2906
2907 if (dev->phy.rev < 2) {
2908 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2909 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2910 } else {
2911 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2912 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2913 }
2914 }
2915}
2916
de7ed0c6
RM		 2917/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2918static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2919{
2920 struct b43_phy_n *nphy = dev->phy.n;
2921 int i;
2922 u16 scale, entry;
2923
2924 u16 tmp = nphy->txcal_bbmult;
2925 if (core == 0)
2926 tmp >>= 8;
2927 tmp &= 0xff;
2928
2929 for (i = 0; i < 18; i++) {
2930 scale = (ladder_lo[i].percent * tmp) / 100;
2931 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 2932 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 2933
2934 scale = (ladder_iq[i].percent * tmp) / 100;
2935 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 2936 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 2937 }
2938}
2939
45ca697e
RM		 2940/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2941static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2942{
2943 int i;
2944 for (i = 0; i < 15; i++)
2945 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2946 tbl_tx_filter_coef_rev4[2][i]);
2947}
2948
2949/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2950static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2951{
2952 int i, j;
2953 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 2954 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 2955
2956 for (i = 0; i < 3; i++)
2957 for (j = 0; j < 15; j++)
2958 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2959 tbl_tx_filter_coef_rev4[i][j]);
2960
2961 if (dev->phy.is_40mhz) {
2962 for (j = 0; j < 15; j++)
2963 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2964 tbl_tx_filter_coef_rev4[3][j]);
2965 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2966 for (j = 0; j < 15; j++)
2967 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2968 tbl_tx_filter_coef_rev4[5][j]);
2969 }
2970
2971 if (dev->phy.channel == 14)
2972 for (j = 0; j < 15; j++)
2973 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2974 tbl_tx_filter_coef_rev4[6][j]);
2975}
2976
b0022e15
RM		 2977/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2978static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2979{
2980 struct b43_phy_n *nphy = dev->phy.n;
2981
2982 u16 curr_gain[2];
2983 struct nphy_txgains target;
2984 const u32 *table = NULL;
2985
161d540c 2986 if (!nphy->txpwrctrl) {
b0022e15
RM		 2987 int i;
2988
2989 if (nphy->hang_avoid)
2990 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 2991 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 2992 if (nphy->hang_avoid)
2993 b43_nphy_stay_in_carrier_search(dev, false);
2994
2995 for (i = 0; i < 2; ++i) {
2996 if (dev->phy.rev >= 3) {
2997 target.ipa[i] = curr_gain[i] & 0x000F;
2998 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2999 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3000 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3001 } else {
3002 target.ipa[i] = curr_gain[i] & 0x0003;
3003 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3004 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3005 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3006 }
3007 }
3008 } else {
3009 int i;
3010 u16 index[2];
3011 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3012 B43_NPHY_TXPCTL_STAT_BIDX) >>
3013 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3014 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3015 B43_NPHY_TXPCTL_STAT_BIDX) >>
3016 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3017
3018 for (i = 0; i < 2; ++i) {
3019 if (dev->phy.rev >= 3) {
3020 enum ieee80211_band band =
3021 b43_current_band(dev->wl);
3022
c002831a 3023 if (b43_nphy_ipa(dev)) {
b0022e15
RM		 3024 table = b43_nphy_get_ipa_gain_table(dev);
3025 } else {
3026 if (band == IEEE80211_BAND_5GHZ) {
3027 if (dev->phy.rev == 3)
3028 table = b43_ntab_tx_gain_rev3_5ghz;
3029 else if (dev->phy.rev == 4)
3030 table = b43_ntab_tx_gain_rev4_5ghz;
3031 else
3032 table = b43_ntab_tx_gain_rev5plus_5ghz;
3033 } else {
3034 table = b43_ntab_tx_gain_rev3plus_2ghz;
3035 }
3036 }
3037
3038 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3039 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3040 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3041 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3042 } else {
3043 table = b43_ntab_tx_gain_rev0_1_2;
3044
3045 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3046 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3047 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3048 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3049 }
3050 }
3051 }
3052
3053 return target;
3054}
3055
e53de674
RM		 3056/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3057static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3058{
3059 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3060
3061 if (dev->phy.rev >= 3) {
3062 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3063 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3064 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3065 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3066 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 3067 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3068 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 3069 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3070 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3071 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3072 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3073 b43_nphy_reset_cca(dev);
3074 } else {
3075 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3076 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3077 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 3078 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3079 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 3080 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3081 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3082 }
3083}
3084
3085/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3086static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3087{
3088 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3089 u16 tmp;
3090
3091 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3092 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3093 if (dev->phy.rev >= 3) {
3094 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3095 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3096
3097 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3098 regs[2] = tmp;
3099 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3100
3101 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3102 regs[3] = tmp;
3103 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3104
3105 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 3106 b43_phy_mask(dev, B43_NPHY_BBCFG,
3107 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 3108
c643a66e 3109 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 3110 regs[5] = tmp;
d41a3552 3111 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 3112
3113 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 3114 regs[6] = tmp;
d41a3552 3115 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 3116 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3117 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3118
67cbc3ed
RM		 3119 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3120 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3121 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 3122
3123 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3124 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3125 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3126 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3127 } else {
3128 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3129 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3130 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3131 regs[2] = tmp;
3132 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 3133 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 3134 regs[3] = tmp;
3135 tmp |= 0x2000;
d41a3552 3136 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 3137 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 3138 regs[4] = tmp;
3139 tmp |= 0x2000;
d41a3552 3140 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 3141 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3142 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3143 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3144 tmp = 0x0180;
3145 else
3146 tmp = 0x0120;
3147 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3148 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3149 }
3150}
3151
bbc6dc12
RM		 3152/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3153static void b43_nphy_save_cal(struct b43_wldev *dev)
3154{
3155 struct b43_phy_n *nphy = dev->phy.n;
3156
3157 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3158 u16 *txcal_radio_regs = NULL;
902db91d 3159 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 3160 u16 *table = NULL;
3161
3162 if (nphy->hang_avoid)
3163 b43_nphy_stay_in_carrier_search(dev, 1);
3164
3165 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3166 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3167 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3168 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3169 table = nphy->cal_cache.txcal_coeffs_2G;
3170 } else {
3171 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3172 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3173 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3174 table = nphy->cal_cache.txcal_coeffs_5G;
3175 }
3176
3177 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3178 /* TODO use some definitions */
3179 if (dev->phy.rev >= 3) {
3180 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3181 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3182 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3183 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3184 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3185 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3186 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3187 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3188 } else {
3189 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3190 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3191 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3192 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3193 }
204a665b
RM		 3194 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3195 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 3196 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 3197
3198 if (nphy->hang_avoid)
3199 b43_nphy_stay_in_carrier_search(dev, 0);
3200}
3201
2f258b74
RM		 3202/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3203static void b43_nphy_restore_cal(struct b43_wldev *dev)
3204{
3205 struct b43_phy_n *nphy = dev->phy.n;
3206
3207 u16 coef[4];
3208 u16 *loft = NULL;
3209 u16 *table = NULL;
3210
3211 int i;
3212 u16 *txcal_radio_regs = NULL;
3213 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3214
3215 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3216 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 3217 return;
3218 table = nphy->cal_cache.txcal_coeffs_2G;
3219 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3220 } else {
204a665b 3221 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 3222 return;
3223 table = nphy->cal_cache.txcal_coeffs_5G;
3224 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3225 }
3226
2581b143 3227 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 3228
3229 for (i = 0; i < 4; i++) {
3230 if (dev->phy.rev >= 3)
3231 table[i] = coef[i];
3232 else
3233 coef[i] = 0;
3234 }
3235
2581b143
RM		 3236 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3237 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3238 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 3239
3240 if (dev->phy.rev < 2)
3241 b43_nphy_tx_iq_workaround(dev);
3242
3243 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3244 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3245 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3246 } else {
3247 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3248 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3249 }
3250
3251 /* TODO use some definitions */
3252 if (dev->phy.rev >= 3) {
3253 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3254 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3255 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3256 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3257 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3258 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3259 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3260 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3261 } else {
3262 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3263 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3264 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3265 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3266 }
3267 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3268}
3269
fb43b8e2
RM		 3270/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3271static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3272 struct nphy_txgains target,
3273 bool full, bool mphase)
3274{
3275 struct b43_phy_n *nphy = dev->phy.n;
3276 int i;
3277 int error = 0;
3278 int freq;
3279 bool avoid = false;
3280 u8 length;
fb23d863 3281 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 3282 const u16 *table;
3283 bool phy6or5x;
3284
3285 u16 buffer[11];
3286 u16 diq_start = 0;
3287 u16 save[2];
3288 u16 gain[2];
3289 struct nphy_iqcal_params params[2];
3290 bool updated[2] = { };
3291
3292 b43_nphy_stay_in_carrier_search(dev, true);
3293
3294 if (dev->phy.rev >= 4) {
3295 avoid = nphy->hang_avoid;
3296 nphy->hang_avoid = 0;
3297 }
3298
9145834e 3299 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3300
3301 for (i = 0; i < 2; i++) {
3302 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3303 gain[i] = params[i].cal_gain;
3304 }
2581b143
RM		 3305
3306 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 3307
3308 b43_nphy_tx_cal_radio_setup(dev);
e53de674 3309 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 3310
3311 phy6or5x = dev->phy.rev >= 6 ||
3312 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3313 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3314 if (phy6or5x) {
38bb9029
RM		 3315 if (dev->phy.is_40mhz) {
3316 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3317 tbl_tx_iqlo_cal_loft_ladder_40);
3318 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3319 tbl_tx_iqlo_cal_iqimb_ladder_40);
3320 } else {
3321 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3322 tbl_tx_iqlo_cal_loft_ladder_20);
3323 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3324 tbl_tx_iqlo_cal_iqimb_ladder_20);
3325 }
fb43b8e2
RM		 3326 }
3327
3328 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3329
aa4c7b2a 3330 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 3331 freq = 2500;
3332 else
3333 freq = 5000;
3334
3335 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 3336 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3337 0xFFFF, 0, true, false);
fb43b8e2 3338 else
59af099b 3339 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 3340
3341 if (error == 0) {
3342 if (nphy->mphase_cal_phase_id > 2) {
3343 table = nphy->mphase_txcal_bestcoeffs;
3344 length = 11;
3345 if (dev->phy.rev < 3)
3346 length -= 2;
3347 } else {
3348 if (!full && nphy->txiqlocal_coeffsvalid) {
3349 table = nphy->txiqlocal_bestc;
3350 length = 11;
3351 if (dev->phy.rev < 3)
3352 length -= 2;
3353 } else {
3354 full = true;
3355 if (dev->phy.rev >= 3) {
3356 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3357 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3358 } else {
3359 table = tbl_tx_iqlo_cal_startcoefs;
3360 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3361 }
3362 }
3363 }
3364
2581b143 3365 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 3366
3367 if (full) {
3368 if (dev->phy.rev >= 3)
3369 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3370 else
3371 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3372 } else {
3373 if (dev->phy.rev >= 3)
3374 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3375 else
3376 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3377 }
3378
3379 if (mphase) {
3380 count = nphy->mphase_txcal_cmdidx;
3381 numb = min(max,
3382 (u16)(count + nphy->mphase_txcal_numcmds));
3383 } else {
3384 count = 0;
3385 numb = max;
3386 }
3387
3388 for (; count < numb; count++) {
3389 if (full) {
3390 if (dev->phy.rev >= 3)
3391 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3392 else
3393 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3394 } else {
3395 if (dev->phy.rev >= 3)
3396 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3397 else
3398 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3399 }
3400
3401 core = (cmd & 0x3000) >> 12;
3402 type = (cmd & 0x0F00) >> 8;
3403
3404 if (phy6or5x && updated[core] == 0) {
3405 b43_nphy_update_tx_cal_ladder(dev, core);
3406 updated[core] = 1;
3407 }
3408
3409 tmp = (params[core].ncorr[type] << 8) | 0x66;
3410 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3411
3412 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 3413 buffer[0] = b43_ntab_read(dev,
3414 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 3415 diq_start = buffer[0];
3416 buffer[0] = 0;
d41a3552
RM		 3417 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3418 0);
fb43b8e2
RM		 3419 }
3420
3421 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3422 for (i = 0; i < 2000; i++) {
3423 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3424 if (tmp & 0xC000)
3425 break;
3426 udelay(10);
3427 }
3428
9145834e
RM		 3429 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3430 buffer);
2581b143
RM		 3431 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3432 buffer);
fb43b8e2
RM		 3433
3434 if (type == 1 || type == 3 || type == 4)
3435 buffer[0] = diq_start;
3436 }
3437
3438 if (mphase)
3439 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3440
3441 last = (dev->phy.rev < 3) ? 6 : 7;
3442
3443 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 3444 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 3445 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 3446 if (dev->phy.rev < 3) {
3447 buffer[0] = 0;
3448 buffer[1] = 0;
3449 buffer[2] = 0;
3450 buffer[3] = 0;
3451 }
2581b143
RM		 3452 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3453 buffer);
bc53e512 3454 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 3455 buffer);
3456 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3457 buffer);
3458 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3459 buffer);
fb43b8e2
RM		 3460 length = 11;
3461 if (dev->phy.rev < 3)
3462 length -= 2;
9145834e
RM		 3463 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3464 nphy->txiqlocal_bestc);
fb43b8e2 3465 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 3466 nphy->txiqlocal_chanspec.center_freq =
3467 dev->phy.channel_freq;
3468 nphy->txiqlocal_chanspec.channel_type =
3469 dev->phy.channel_type;
fb43b8e2
RM		 3470 } else {
3471 length = 11;
3472 if (dev->phy.rev < 3)
3473 length -= 2;
9145834e
RM		 3474 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3475 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 3476 }
3477
53ae8e8c 3478 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 3479 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3480 }
3481
e53de674 3482 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 3483 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3484
3485 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3486 b43_nphy_tx_iq_workaround(dev);
3487
3488 if (dev->phy.rev >= 4)
3489 nphy->hang_avoid = avoid;
3490
3491 b43_nphy_stay_in_carrier_search(dev, false);
3492
3493 return error;
3494}
3495
984ff4ff
RM		 3496/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3497static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3498{
3499 struct b43_phy_n *nphy = dev->phy.n;
3500 u8 i;
3501 u16 buffer[7];
3502 bool equal = true;
3503
902db91d 3504 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 3505 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3506 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 3507 return;
3508
3509 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3510 for (i = 0; i < 4; i++) {
3511 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3512 equal = false;
3513 break;
3514 }
3515 }
3516
3517 if (!equal) {
3518 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3519 nphy->txiqlocal_bestc);
3520 for (i = 0; i < 4; i++)
3521 buffer[i] = 0;
3522 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3523 buffer);
3524 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3525 &nphy->txiqlocal_bestc[5]);
3526 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3527 &nphy->txiqlocal_bestc[5]);
3528 }
3529}
3530
15931e31
RM		 3531/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3532static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3533 struct nphy_txgains target, u8 type, bool debug)
3534{
3535 struct b43_phy_n *nphy = dev->phy.n;
3536 int i, j, index;
3537 u8 rfctl[2];
3538 u8 afectl_core;
3539 u16 tmp[6];
c7455cf9 3540 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 3541 u32 real, imag;
3542 enum ieee80211_band band;
3543
3544 u8 use;
3545 u16 cur_hpf;
3546 u16 lna[3] = { 3, 3, 1 };
3547 u16 hpf1[3] = { 7, 2, 0 };
3548 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 3549 u32 power[3] = { };
15931e31
RM		 3550 u16 gain_save[2];
3551 u16 cal_gain[2];
3552 struct nphy_iqcal_params cal_params[2];
3553 struct nphy_iq_est est;
3554 int ret = 0;
3555 bool playtone = true;
3556 int desired = 13;
3557
3558 b43_nphy_stay_in_carrier_search(dev, 1);
3559
3560 if (dev->phy.rev < 2)
984ff4ff 3561 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 3562 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3563 for (i = 0; i < 2; i++) {
3564 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3565 cal_gain[i] = cal_params[i].cal_gain;
3566 }
2581b143 3567 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 3568
3569 for (i = 0; i < 2; i++) {
3570 if (i == 0) {
3571 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3572 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3573 afectl_core = B43_NPHY_AFECTL_C1;
3574 } else {
3575 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3576 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3577 afectl_core = B43_NPHY_AFECTL_C2;
3578 }
3579
3580 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3581 tmp[2] = b43_phy_read(dev, afectl_core);
3582 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3583 tmp[4] = b43_phy_read(dev, rfctl[0]);
3584 tmp[5] = b43_phy_read(dev, rfctl[1]);
3585
3586 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 3587 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 3588 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3589 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3590 (1 - i));
3591 b43_phy_set(dev, afectl_core, 0x0006);
3592 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3593
3594 band = b43_current_band(dev->wl);
3595
3596 if (nphy->rxcalparams & 0xFF000000) {
3597 if (band == IEEE80211_BAND_5GHZ)
3598 b43_phy_write(dev, rfctl[0], 0x140);
3599 else
3600 b43_phy_write(dev, rfctl[0], 0x110);
3601 } else {
3602 if (band == IEEE80211_BAND_5GHZ)
3603 b43_phy_write(dev, rfctl[0], 0x180);
3604 else
3605 b43_phy_write(dev, rfctl[0], 0x120);
3606 }
3607
3608 if (band == IEEE80211_BAND_5GHZ)
3609 b43_phy_write(dev, rfctl[1], 0x148);
3610 else
3611 b43_phy_write(dev, rfctl[1], 0x114);
3612
3613 if (nphy->rxcalparams & 0x10000) {
3614 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3615 (i + 1));
3616 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3617 (2 - i));
3618 }
3619
30115c22 3620 for (j = 0; j < 4; j++) {
15931e31
RM		 3621 if (j < 3) {
3622 cur_lna = lna[j];
3623 cur_hpf1 = hpf1[j];
3624 cur_hpf2 = hpf2[j];
3625 } else {
3626 if (power[1] > 10000) {
3627 use = 1;
3628 cur_hpf = cur_hpf1;
3629 index = 2;
3630 } else {
3631 if (power[0] > 10000) {
3632 use = 1;
3633 cur_hpf = cur_hpf1;
3634 index = 1;
3635 } else {
3636 index = 0;
3637 use = 2;
3638 cur_hpf = cur_hpf2;
3639 }
3640 }
3641 cur_lna = lna[index];
3642 cur_hpf1 = hpf1[index];
3643 cur_hpf2 = hpf2[index];
3644 cur_hpf += desired - hweight32(power[index]);
3645 cur_hpf = clamp_val(cur_hpf, 0, 10);
3646 if (use == 1)
3647 cur_hpf1 = cur_hpf;
3648 else
3649 cur_hpf2 = cur_hpf;
3650 }
3651
3652 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3653 (cur_lna << 2));
75377b24
RM		 3654 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3655 false);
de9a47f9 3656 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3657 b43_nphy_stop_playback(dev);
15931e31
RM		 3658
3659 if (playtone) {
59af099b
RM		 3660 ret = b43_nphy_tx_tone(dev, 4000,
3661 (nphy->rxcalparams & 0xFFFF),
3662 false, false);
15931e31
RM		 3663 playtone = false;
3664 } else {
10a79873
RM		 3665 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3666 false, false);
15931e31
RM		 3667 }
3668
3669 if (ret == 0) {
3670 if (j < 3) {
3671 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3672 false);
3673 if (i == 0) {
3674 real = est.i0_pwr;
3675 imag = est.q0_pwr;
3676 } else {
3677 real = est.i1_pwr;
3678 imag = est.q1_pwr;
3679 }
3680 power[i] = ((real + imag) / 1024) + 1;
3681 } else {
3682 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3683 }
53ae8e8c 3684 b43_nphy_stop_playback(dev);
15931e31
RM		 3685 }
3686
3687 if (ret != 0)
3688 break;
3689 }
3690
3691 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3692 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3693 b43_phy_write(dev, rfctl[1], tmp[5]);
3694 b43_phy_write(dev, rfctl[0], tmp[4]);
3695 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3696 b43_phy_write(dev, afectl_core, tmp[2]);
3697 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3698
3699 if (ret != 0)
3700 break;
3701 }
3702
75377b24 3703 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3704 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3705 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3706
3707 b43_nphy_stay_in_carrier_search(dev, 0);
3708
3709 return ret;
3710}
3711
3712static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3713 struct nphy_txgains target, u8 type, bool debug)
3714{
3715 return -1;
3716}
3717
3718/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3719static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3720 struct nphy_txgains target, u8 type, bool debug)
3721{
3722 if (dev->phy.rev >= 3)
3723 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3724 else
3725 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3726}
3727
4e687b22
GS		 3728/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3729static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3730{
3731 struct b43_phy *phy = &dev->phy;
3732 struct b43_phy_n *nphy = phy->n;
0b81c23d 3733 /* u16 buf[16]; it's rev3+ */
4e687b22 3734
049fbfee
RM		 3735 nphy->phyrxchain = mask;
3736
4e687b22
GS		 3737 if (0 /* FIXME clk */)
3738 return;
3739
3740 b43_mac_suspend(dev);
3741
3742 if (nphy->hang_avoid)
3743 b43_nphy_stay_in_carrier_search(dev, true);
3744
3745 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3746 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3747
049fbfee 3748 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 3749 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3750 if (dev->phy.rev >= 3) {
3751 /* TODO */
3752 }
3753 } else {
3754 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3755 if (dev->phy.rev >= 3) {
3756 /* TODO */
3757 }
3758 }
3759
3760 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3761
3762 if (nphy->hang_avoid)
3763 b43_nphy_stay_in_carrier_search(dev, false);
3764
3765 b43_mac_enable(dev);
3766}
3767
104cfa88
RM		 3768/**************************************************
3769 * N-PHY init
3770 **************************************************/
3771
0988a7a1 3772/*
104cfa88
RM		 3773 * Upload the N-PHY tables.
3774 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
0988a7a1 3775 */
104cfa88
RM		 3776static void b43_nphy_tables_init(struct b43_wldev *dev)
3777{
3778 if (dev->phy.rev < 3)
3779 b43_nphy_rev0_1_2_tables_init(dev);
3780 else
3781 b43_nphy_rev3plus_tables_init(dev);
3782}
3783
3784/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
3785static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
3786{
3787 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
3788
3789 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
3790 if (preamble == 1)
3791 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
3792 else
3793 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
3794
3795 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
3796}
3797
3798/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
3799static void b43_nphy_bphy_init(struct b43_wldev *dev)
3800{
3801 unsigned int i;
3802 u16 val;
3803
3804 val = 0x1E1F;
3805 for (i = 0; i < 16; i++) {
3806 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
3807 val -= 0x202;
3808 }
3809 val = 0x3E3F;
3810 for (i = 0; i < 16; i++) {
3811 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
3812 val -= 0x202;
3813 }
3814 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
3815}
3816
3817/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
3818static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
3819{
3820 if (dev->phy.rev >= 3) {
3821 if (!init)
3822 return;
3823 if (0 /* FIXME */) {
3824 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
3825 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
3826 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
3827 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
3828 }
3829 } else {
3830 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
3831 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
3832
3833 switch (dev->dev->bus_type) {
3834#ifdef CONFIG_B43_BCMA
3835 case B43_BUS_BCMA:
3836 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
3837 0xFC00, 0xFC00);
3838 break;
3839#endif
3840#ifdef CONFIG_B43_SSB
3841 case B43_BUS_SSB:
3842 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
3843 0xFC00, 0xFC00);
3844 break;
3845#endif
3846 }
3847
3848 b43_write32(dev, B43_MMIO_MACCTL,
3849 b43_read32(dev, B43_MMIO_MACCTL) &
3850 ~B43_MACCTL_GPOUTSMSK);
3851 b43_write16(dev, B43_MMIO_GPIO_MASK,
3852 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
3853 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
3854 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
3855
3856 if (init) {
3857 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3858 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3859 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3860 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3861 }
3862 }
3863}
3864
3865/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
424047e6
MB		 3866int b43_phy_initn(struct b43_wldev *dev)
3867{
0581483a 3868 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 3869 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3870 struct b43_phy_n *nphy = phy->n;
3871 u8 tx_pwr_state;
3872 struct nphy_txgains target;
95b66bad 3873 u16 tmp;
0988a7a1
RM		 3874 enum ieee80211_band tmp2;
3875 bool do_rssi_cal;
3876
3877 u16 clip[2];
3878 bool do_cal = false;
95b66bad 3879
0988a7a1 3880 if ((dev->phy.rev >= 3) &&
0581483a 3881 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 3882 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 3883 switch (dev->dev->bus_type) {
42c9a458
RM		 3884#ifdef CONFIG_B43_BCMA
3885 case B43_BUS_BCMA:
3886 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3887 BCMA_CC_CHIPCTL, 0x40);
3888 break;
3889#endif
6cbab0d9
RM		 3890#ifdef CONFIG_B43_SSB
3891 case B43_BUS_SSB:
3892 chipco_set32(&dev->dev->sdev->bus->chipco,
3893 SSB_CHIPCO_CHIPCTL, 0x40);
3894 break;
3895#endif
3896 }
0988a7a1
RM		 3897 }
3898 nphy->deaf_count = 0;
95b66bad 3899 b43_nphy_tables_init(dev);
0988a7a1
RM		 3900 nphy->crsminpwr_adjusted = false;
3901 nphy->noisevars_adjusted = false;
95b66bad
MB		 3902
3903 /* Clear all overrides */
0988a7a1
RM		 3904 if (dev->phy.rev >= 3) {
3905 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3906 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3907 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3908 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3909 } else {
3910 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3911 }
95b66bad
MB		 3912 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3913 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3914 if (dev->phy.rev < 6) {
3915 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3916 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3917 }
95b66bad
MB		 3918 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3919 ~(B43_NPHY_RFSEQMODE_CAOVER |
3920 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3921 if (dev->phy.rev >= 3)
3922 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3923 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3924
0988a7a1
RM		 3925 if (dev->phy.rev <= 2) {
3926 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3927 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3928 ~B43_NPHY_BPHY_CTL3_SCALE,
3929 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3930 }
95b66bad
MB		 3931 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3932 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3933
0eff8fcd 3934 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f
RM		 3935 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3936 dev->dev->board_type == 0x8B))
0988a7a1
RM		 3937 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3938 else
3939 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3940 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3941 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3942 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3943
ad9716e8 3944 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3945 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3946
3947 if (phy->rev < 2) {
3948 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3949 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3950 }
0988a7a1
RM		 3951
3952 tmp2 = b43_current_band(dev->wl);
c002831a 3953 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 3954 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3955 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3956 nphy->papd_epsilon_offset[0] << 7);
3957 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3958 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3959 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3960 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3961 } else if (phy->rev >= 5) {
45ca697e 3962 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3963 }
3964
95b66bad 3965 b43_nphy_workarounds(dev);
95b66bad 3966
0988a7a1 3967 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 3968 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 3969 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3970 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3971 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 3972 b43_phy_force_clock(dev, 0);
0988a7a1 3973
858a1652 3974 b43_mac_phy_clock_set(dev, true);
0988a7a1 3975
e50cbcf6 3976 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3977 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3978 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3979 b43_nphy_pa_override(dev, true);
0988a7a1 3980
bbec398c
RM		 3981 b43_nphy_classifier(dev, 0, 0);
3982 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 3983 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3984 b43_nphy_bphy_init(dev);
3985
0988a7a1 3986 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 3987 b43_nphy_tx_power_ctrl(dev, false);
3988 b43_nphy_tx_power_fix(dev);
0988a7a1
RM		 3989 /* TODO N PHY TX Power Control Idle TSSI */
3990 /* TODO N PHY TX Power Control Setup */
0eff8fcd 3991 b43_nphy_tx_gain_table_upload(dev);
95b66bad 3992
0988a7a1 3993 if (nphy->phyrxchain != 3)
4e687b22 3994 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 3995 if (nphy->mphase_cal_phase_id > 0)
3996 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3997
3998 do_rssi_cal = false;
3999 if (phy->rev >= 3) {
4000 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 4001 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 4002 else
204a665b 4003 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 4004
4005 if (do_rssi_cal)
4cb99775 4006 b43_nphy_rssi_cal(dev);
0988a7a1 4007 else
42e1547e 4008 b43_nphy_restore_rssi_cal(dev);
0988a7a1 4009 } else {
4cb99775 4010 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 4011 }
4012
4013 if (!((nphy->measure_hold & 0x6) != 0)) {
4014 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 4015 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 4016 else
204a665b 4017 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 4018
4019 if (nphy->mute)
4020 do_cal = false;
4021
4022 if (do_cal) {
b0022e15 4023 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 4024
4025 if (nphy->antsel_type == 2)
8987a9e9 4026 b43_nphy_superswitch_init(dev, true);
0988a7a1 4027 if (nphy->perical != 2) {
90b9738d 4028 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 4029 if (phy->rev >= 3) {
4030 nphy->cal_orig_pwr_idx[0] =
4031 nphy->txpwrindex[0].index_internal;
4032 nphy->cal_orig_pwr_idx[1] =
4033 nphy->txpwrindex[1].index_internal;
4034 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 4035 target = b43_nphy_get_tx_gains(dev);
0988a7a1 4036 }
e7797bf2
RM		 4037 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4038 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4039 b43_nphy_save_cal(dev);
4040 } else if (nphy->mphase_cal_phase_id == 0)
4041 ;/* N PHY Periodic Calibration with arg 3 */
4042 } else {
4043 b43_nphy_restore_cal(dev);
0988a7a1
RM		 4044 }
4045 }
4046
6dcd9d91 4047 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 4048 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 4049 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4050 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4051 if (phy->rev >= 3 && phy->rev <= 6)
4052 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 4053 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 4054 if (phy->rev >= 3)
4055 b43_nphy_spur_workaround(dev);
95b66bad 4056
53a6e234 4057 return 0;
424047e6 4058}
ef1a628d 4059
104cfa88
RM		 4060/**************************************************
4061 * Channel switching ops.
4062 **************************************************/
4063
4064static void b43_chantab_phy_upload(struct b43_wldev *dev,
4065 const struct b43_phy_n_sfo_cfg *e)
4066{
4067 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
4068 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
4069 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
4070 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
4071 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
4072 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
4073}
4074
49d55cef
RM		 4075/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4076static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4077{
9b682c78
JL		 4078 struct bcma_drv_cc __maybe_unused *cc;
4079 u32 __maybe_unused pmu_ctl;
d66be829
RM		 4080
4081 switch (dev->dev->bus_type) {
4082#ifdef CONFIG_B43_BCMA
4083 case B43_BUS_BCMA:
4084 cc = &dev->dev->bdev->bus->drv_cc;
4085 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4086 if (avoid) {
4087 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4088 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4089 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4090 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4091 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4092 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4093 } else {
4094 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4095 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4096 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4097 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4098 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4099 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4100 }
4101 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4102 } else if (dev->dev->chip_id == 0x4716) {
4103 if (avoid) {
4104 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4105 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4106 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4107 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4108 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4109 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4110 } else {
4111 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4112 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4113 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4114 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4115 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4116 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4117 }
4118 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4119 BCMA_CC_PMU_CTL_NOILPONW;
4120 } else if (dev->dev->chip_id == 0x4322 ||
4121 dev->dev->chip_id == 0x4340 ||
4122 dev->dev->chip_id == 0x4341) {
4123 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4124 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4125 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4126 if (avoid)
4127 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4128 else
4129 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4130 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
49d55cef 4131 } else {
d66be829 4132 return;
49d55cef 4133 }
d66be829
RM		 4134 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4135 break;
8b1fdb53 4136#endif
d66be829
RM		 4137#ifdef CONFIG_B43_SSB
4138 case B43_BUS_SSB:
4139 /* FIXME */
4140 break;
4141#endif
4142 }
49d55cef
RM		 4143}
4144
1b69ec7b 4145/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 4146static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 4147 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 4148 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 4149{
4150 struct b43_phy *phy = &dev->phy;
4151 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 4152 int ch = new_channel->hw_value;
1b69ec7b 4153
087de74a 4154 u16 old_band_5ghz;
1b69ec7b
RM		 4155 u32 tmp32;
4156
087de74a
RM		 4157 old_band_5ghz =
4158 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4159 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 4160 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4161 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4162 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4163 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4164 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 4165 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 4166 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4167 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4168 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 4169 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 4170 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4171 }
4172
4173 b43_chantab_phy_upload(dev, e);
4174
a656b6a9 4175 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 4176 b43_nphy_classifier(dev, 2, 0);
4177 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4178 } else {
4179 b43_nphy_classifier(dev, 2, 2);
a656b6a9 4180 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 4181 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4182 }
4183
161d540c 4184 if (!nphy->txpwrctrl)
1b69ec7b
RM		 4185 b43_nphy_tx_power_fix(dev);
4186
4187 if (dev->phy.rev < 3)
4188 b43_nphy_adjust_lna_gain_table(dev);
4189
4190 b43_nphy_tx_lp_fbw(dev);
4191
49d55cef
RM		 4192 if (dev->phy.rev >= 3 &&
4193 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4194 bool avoid = false;
4195 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4196 avoid = true;
4197 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4198 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4199 avoid = true;
4200 } else { /* 40MHz */
4201 if (nphy->aband_spurwar_en &&
4202 (ch == 38 || ch == 102 || ch == 118))
4203 avoid = dev->dev->chip_id == 0x4716;
4204 }
4205
4206 b43_nphy_pmu_spur_avoid(dev, avoid);
4207
4208 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4209 dev->dev->chip_id == 43225) {
4210 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4211 avoid ? 0x5341 : 0x8889);
4212 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4213 }
4214
4215 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4216 ; /* TODO: reset PLL */
4217
4218 if (avoid)
4219 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4220 else
4221 b43_phy_mask(dev, B43_NPHY_BBCFG,
4222 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4223
4224 b43_nphy_reset_cca(dev);
4225
4226 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 4227 }
4228
4229 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4230
4231 if (phy->rev >= 3)
4232 b43_nphy_spur_workaround(dev);
4233}
4234
eff66c51 4235/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 4236static int b43_nphy_set_channel(struct b43_wldev *dev,
4237 struct ieee80211_channel *channel,
4238 enum nl80211_channel_type channel_type)
eff66c51 4239{
a656b6a9 4240 struct b43_phy *phy = &dev->phy;
eff66c51 4241
2eeb6fd0
JL		 4242 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4243 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 4244
4245 u8 tmp;
eff66c51
RM		 4246
4247 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 4248 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4249 channel->center_freq);
f19ebe7d
RM		 4250 if (!tabent_r3)
4251 return -ESRCH;
ffd2d9bd 4252 } else {
a656b6a9
RM		 4253 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4254 channel->hw_value);
f19ebe7d 4255 if (!tabent_r2)
ffd2d9bd 4256 return -ESRCH;
eff66c51
RM		 4257 }
4258
204a665b
RM		 4259 /* Channel is set later in common code, but we need to set it on our
4260 own to let this function's subcalls work properly. */
4261 phy->channel = channel->hw_value;
4262 phy->channel_freq = channel->center_freq;
eff66c51 4263
e5c407f9
RM		 4264 if (b43_channel_type_is_40mhz(phy->channel_type) !=
4265 b43_channel_type_is_40mhz(channel_type))
4266 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 4267
a656b6a9
RM		 4268 if (channel_type == NL80211_CHAN_HT40PLUS)
4269 b43_phy_set(dev, B43_NPHY_RXCTL,
4270 B43_NPHY_RXCTL_BSELU20);
4271 else if (channel_type == NL80211_CHAN_HT40MINUS)
4272 b43_phy_mask(dev, B43_NPHY_RXCTL,
4273 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 4274
4275 if (dev->phy.rev >= 3) {
a656b6a9 4276 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 4277 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 4278 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 4279 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 4280 } else {
a656b6a9 4281 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 4282 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 4283 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 4284 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 4285 }
4286
4287 return 0;
4288}
4289
104cfa88
RM		 4290/**************************************************
4291 * Basic PHY ops.
4292 **************************************************/
4293
ef1a628d
MB		 4294static int b43_nphy_op_allocate(struct b43_wldev *dev)
4295{
4296 struct b43_phy_n *nphy;
4297
4298 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4299 if (!nphy)
4300 return -ENOMEM;
4301 dev->phy.n = nphy;
4302
ef1a628d
MB		 4303 return 0;
4304}
4305
fb11137a 4306static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 4307{
fb11137a
MB		 4308 struct b43_phy *phy = &dev->phy;
4309 struct b43_phy_n *nphy = phy->n;
c7d64310 4310 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 4311
fb11137a 4312 memset(nphy, 0, sizeof(*nphy));
ef1a628d 4313
aca434d3 4314 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 4315 nphy->spur_avoid = (phy->rev >= 3) ?
4316 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 4317 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4318 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4319 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 4320 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 4321 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4322 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4323 nphy->tx_pwr_idx[0] = 128;
4324 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 4325
4326 /* Hardware TX power control and 5GHz power gain */
4327 nphy->txpwrctrl = false;
4328 nphy->pwg_gain_5ghz = false;
4329 if (dev->phy.rev >= 3 ||
4330 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4331 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4332 nphy->txpwrctrl = true;
4333 nphy->pwg_gain_5ghz = true;
4334 } else if (sprom->revision >= 4) {
4335 if (dev->phy.rev >= 2 &&
4336 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4337 nphy->txpwrctrl = true;
4338#ifdef CONFIG_B43_SSB
4339 if (dev->dev->bus_type == B43_BUS_SSB &&
4340 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4341 struct pci_dev *pdev =
4342 dev->dev->sdev->bus->host_pci;
4343 if (pdev->device == 0x4328 ||
4344 pdev->device == 0x432a)
4345 nphy->pwg_gain_5ghz = true;
4346 }
4347#endif
4348 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4349 nphy->pwg_gain_5ghz = true;
4350 }
4351 }
4352
4353 if (dev->phy.rev >= 3) {
4354 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4355 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4356 }
ef1a628d
MB		 4357}
4358
fb11137a 4359static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 4360{
fb11137a
MB		 4361 struct b43_phy *phy = &dev->phy;
4362 struct b43_phy_n *nphy = phy->n;
ef1a628d 4363
ef1a628d 4364 kfree(nphy);
fb11137a
MB		 4365 phy->n = NULL;
4366}
4367
4368static int b43_nphy_op_init(struct b43_wldev *dev)
4369{
4370 return b43_phy_initn(dev);
ef1a628d
MB		 4371}
4372
4373static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4374{
4375#if B43_DEBUG
4376 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4377 /* OFDM registers are onnly available on A/G-PHYs */
4378 b43err(dev->wl, "Invalid OFDM PHY access at "
4379 "0x%04X on N-PHY\n", offset);
4380 dump_stack();
4381 }
4382 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4383 /* Ext-G registers are only available on G-PHYs */
4384 b43err(dev->wl, "Invalid EXT-G PHY access at "
4385 "0x%04X on N-PHY\n", offset);
4386 dump_stack();
4387 }
4388#endif /* B43_DEBUG */
4389}
4390
4391static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4392{
4393 check_phyreg(dev, reg);
4394 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4395 return b43_read16(dev, B43_MMIO_PHY_DATA);
4396}
4397
4398static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4399{
4400 check_phyreg(dev, reg);
4401 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4402 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4403}
4404
755fd183
RM		 4405static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4406 u16 set)
4407{
4408 check_phyreg(dev, reg);
4409 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4410 b43_write16(dev, B43_MMIO_PHY_DATA,
4411 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4412}
4413
ef1a628d
MB		 4414static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4415{
4416 /* Register 1 is a 32-bit register. */
4417 B43_WARN_ON(reg == 1);
4418 /* N-PHY needs 0x100 for read access */
4419 reg |= 0x100;
4420
4421 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4422 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4423}
4424
4425static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4426{
4427 /* Register 1 is a 32-bit register. */
4428 B43_WARN_ON(reg == 1);
4429
4430 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4431 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4432}
4433
c2b7aefd 4434/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 4435static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 4436 bool blocked)
c2b7aefd
RM		 4437{
4438 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4439 b43err(dev->wl, "MAC not suspended\n");
4440
4441 if (blocked) {
4442 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4443 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4444 if (dev->phy.rev >= 3) {
4445 b43_radio_mask(dev, 0x09, ~0x2);
4446
4447 b43_radio_write(dev, 0x204D, 0);
4448 b43_radio_write(dev, 0x2053, 0);
4449 b43_radio_write(dev, 0x2058, 0);
4450 b43_radio_write(dev, 0x205E, 0);
4451 b43_radio_mask(dev, 0x2062, ~0xF0);
4452 b43_radio_write(dev, 0x2064, 0);
4453
4454 b43_radio_write(dev, 0x304D, 0);
4455 b43_radio_write(dev, 0x3053, 0);
4456 b43_radio_write(dev, 0x3058, 0);
4457 b43_radio_write(dev, 0x305E, 0);
4458 b43_radio_mask(dev, 0x3062, ~0xF0);
4459 b43_radio_write(dev, 0x3064, 0);
4460 }
4461 } else {
4462 if (dev->phy.rev >= 3) {
d817f4e1 4463 b43_radio_init2056(dev);
78159788 4464 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 4465 } else {
4466 b43_radio_init2055(dev);
4467 }
4468 }
ef1a628d
MB		 4469}
4470
0f4091b9 4471/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 4472static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4473{
2a870831
RM		 4474 u16 override = on ? 0x0 : 0x7FFF;
4475 u16 core = on ? 0xD : 0x00FD;
0f4091b9 4476
2a870831
RM		 4477 if (dev->phy.rev >= 3) {
4478 if (on) {
4479 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4480 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4481 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4482 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4483 } else {
4484 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4485 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4486 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4487 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4488 }
4489 } else {
4490 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4491 }
cb24f57f
MB		 4492}
4493
ef1a628d
MB		 4494static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4495 unsigned int new_channel)
4496{
a656b6a9
RM		 4497 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4498 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 4499
ef1a628d
MB		 4500 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4501 if ((new_channel < 1) || (new_channel > 14))
4502 return -EINVAL;
4503 } else {
4504 if (new_channel > 200)
4505 return -EINVAL;
4506 }
4507
a656b6a9 4508 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 4509}
4510
4511static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4512{
4513 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4514 return 1;
4515 return 36;
4516}
4517
ef1a628d
MB		 4518const struct b43_phy_operations b43_phyops_n = {
4519 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 4520 .free = b43_nphy_op_free,
4521 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 4522 .init = b43_nphy_op_init,
ef1a628d
MB		 4523 .phy_read = b43_nphy_op_read,
4524 .phy_write = b43_nphy_op_write,
755fd183 4525 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 4526 .radio_read = b43_nphy_op_radio_read,
4527 .radio_write = b43_nphy_op_radio_write,
4528 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 4529 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 4530 .switch_channel = b43_nphy_op_switch_channel,
4531 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 4532 .recalc_txpower = b43_nphy_op_recalc_txpower,
4533 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 4534};
Linux kernel - Deliverables
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