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b43: be more user friendly with PHY info
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
76b002bd
RM		 72enum b43_nphy_rssi_type {
73 B43_NPHY_RSSI_X = 0,
74 B43_NPHY_RSSI_Y,
75 B43_NPHY_RSSI_Z,
76 B43_NPHY_RSSI_PWRDET,
77 B43_NPHY_RSSI_TSSI_I,
78 B43_NPHY_RSSI_TSSI_Q,
79 B43_NPHY_RSSI_TBD,
80};
81
c002831a
RM		 82static inline bool b43_nphy_ipa(struct b43_wldev *dev)
83{
84 enum ieee80211_band band = b43_current_band(dev->wl);
85 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
86 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
87}
88
e0c9a021
RM		 89/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
90static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
91{
92 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
93 B43_NPHY_RFSEQCA_RXEN_SHIFT;
94}
95
ab499217
RM		 96/**************************************************
97 * RF (just without b43_nphy_rf_control_intc_override)
98 **************************************************/
18c8adeb 99
ab499217
RM		 100/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
101static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
102 enum b43_nphy_rf_sequence seq)
d1591314 103{
ab499217
RM		 104 static const u16 trigger[] = {
105 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
106 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
107 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
108 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
109 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
110 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
111 };
112 int i;
113 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 114
ab499217 115 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 116
ab499217
RM		 117 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
118 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
119 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
120 for (i = 0; i < 200; i++) {
121 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
122 goto ok;
123 msleep(1);
124 }
125 b43err(dev->wl, "RF sequence status timeout\n");
126ok:
127 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
128}
e5255ccc 129
ab499217
RM		 130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
131static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
132 u16 value, u8 core, bool off)
133{
134 int i;
135 u8 index = fls(field);
136 u8 addr, en_addr, val_addr;
137 /* we expect only one bit set */
138 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 139
ab499217
RM		 140 if (dev->phy.rev >= 3) {
141 const struct nphy_rf_control_override_rev3 *rf_ctrl;
142 for (i = 0; i < 2; i++) {
143 if (index == 0 || index == 16) {
144 b43err(dev->wl,
145 "Unsupported RF Ctrl Override call\n");
146 return;
147 }
e5255ccc 148
ab499217
RM		 149 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
150 en_addr = B43_PHY_N((i == 0) ?
151 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
152 val_addr = B43_PHY_N((i == 0) ?
153 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 154
ab499217
RM		 155 if (off) {
156 b43_phy_mask(dev, en_addr, ~(field));
157 b43_phy_mask(dev, val_addr,
158 ~(rf_ctrl->val_mask));
159 } else {
b97c0718 160 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 161 b43_phy_set(dev, en_addr, field);
162 b43_phy_maskset(dev, val_addr,
163 ~(rf_ctrl->val_mask),
164 (value << rf_ctrl->val_shift));
165 }
166 }
167 }
168 } else {
169 const struct nphy_rf_control_override_rev2 *rf_ctrl;
170 if (off) {
171 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
172 value = 0;
173 } else {
174 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
175 }
d4814e69 176
ab499217
RM		 177 for (i = 0; i < 2; i++) {
178 if (index <= 1 || index == 16) {
179 b43err(dev->wl,
180 "Unsupported RF Ctrl Override call\n");
181 return;
182 }
d4814e69 183
ab499217
RM		 184 if (index == 2 || index == 10 ||
185 (index >= 13 && index <= 15)) {
186 core = 1;
187 }
d4814e69 188
ab499217
RM		 189 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
190 addr = B43_PHY_N((i == 0) ?
191 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 192
b97c0718 193 if ((1 << i) & core)
ab499217
RM		 194 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
195 (value << rf_ctrl->shift));
196
197 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
198 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
199 B43_NPHY_RFCTL_CMD_START);
200 udelay(1);
201 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
202 }
203 }
d4814e69
RM		 204}
205
ab499217
RM		 206/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
207static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
208 u16 value, u8 core)
d4814e69 209{
ab499217
RM		 210 u8 i, j;
211 u16 reg, tmp, val;
38646eba 212
d4814e69 213 B43_WARN_ON(dev->phy.rev < 3);
ab499217 214 B43_WARN_ON(field > 4);
d4814e69 215
ab499217
RM		 216 for (i = 0; i < 2; i++) {
217 if ((core == 1 && i == 1) || (core == 2 && !i))
218 continue;
38646eba 219
ab499217
RM		 220 reg = (i == 0) ?
221 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 222 b43_phy_set(dev, reg, 0x400);
38646eba 223
ab499217
RM		 224 switch (field) {
225 case 0:
226 b43_phy_write(dev, reg, 0);
227 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
228 break;
229 case 1:
230 if (!i) {
231 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
232 0xFC3F, (value << 6));
233 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
234 0xFFFE, 1);
235 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
236 B43_NPHY_RFCTL_CMD_START);
237 for (j = 0; j < 100; j++) {
603431e9 238 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 239 j = 0;
240 break;
241 }
242 udelay(10);
38646eba 243 }
ab499217
RM		 244 if (j)
245 b43err(dev->wl,
246 "intc override timeout\n");
247 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
248 0xFFFE);
38646eba 249 } else {
ab499217
RM		 250 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
251 0xFC3F, (value << 6));
252 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
253 0xFFFE, 1);
254 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
255 B43_NPHY_RFCTL_CMD_RXTX);
256 for (j = 0; j < 100; j++) {
603431e9 257 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 258 j = 0;
259 break;
260 }
261 udelay(10);
262 }
263 if (j)
264 b43err(dev->wl,
265 "intc override timeout\n");
266 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
267 0xFFFE);
38646eba 268 }
ab499217
RM		 269 break;
270 case 2:
271 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
272 tmp = 0x0020;
273 val = value << 5;
274 } else {
275 tmp = 0x0010;
276 val = value << 4;
277 }
278 b43_phy_maskset(dev, reg, ~tmp, val);
279 break;
280 case 3:
281 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
282 tmp = 0x0001;
283 val = value;
284 } else {
285 tmp = 0x0004;
286 val = value << 2;
287 }
288 b43_phy_maskset(dev, reg, ~tmp, val);
289 break;
290 case 4:
291 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
292 tmp = 0x0002;
293 val = value << 1;
294 } else {
295 tmp = 0x0008;
296 val = value << 3;
297 }
298 b43_phy_maskset(dev, reg, ~tmp, val);
299 break;
38646eba 300 }
38646eba 301 }
ab499217 302}
38646eba 303
ab499217
RM		 304/**************************************************
305 * Various PHY ops
306 **************************************************/
307
308/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
309static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
310 const u16 *clip_st)
311{
312 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
313 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 314}
315
ab499217
RM		 316/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
317static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 318{
ab499217
RM		 319 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
320 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 321}
322
ab499217
RM		 323/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
324static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 325{
ab499217 326 u16 tmp;
161d540c 327
ab499217
RM		 328 if (dev->dev->core_rev == 16)
329 b43_mac_suspend(dev);
161d540c 330
ab499217
RM		 331 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
332 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
333 B43_NPHY_CLASSCTL_WAITEDEN);
334 tmp &= ~mask;
335 tmp |= (val & mask);
336 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 337
ab499217
RM		 338 if (dev->dev->core_rev == 16)
339 b43_mac_enable(dev);
161d540c 340
ab499217
RM		 341 return tmp;
342}
161d540c 343
ab499217
RM		 344/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
345static void b43_nphy_reset_cca(struct b43_wldev *dev)
346{
347 u16 bbcfg;
161d540c 348
ab499217
RM		 349 b43_phy_force_clock(dev, 1);
350 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
351 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
352 udelay(1);
353 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
354 b43_phy_force_clock(dev, 0);
355 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
356}
161d540c 357
ab499217
RM		 358/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
359static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
360{
361 struct b43_phy *phy = &dev->phy;
362 struct b43_phy_n *nphy = phy->n;
161d540c 363
ab499217
RM		 364 if (enable) {
365 static const u16 clip[] = { 0xFFFF, 0xFFFF };
366 if (nphy->deaf_count++ == 0) {
367 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
368 b43_nphy_classifier(dev, 0x7, 0);
369 b43_nphy_read_clip_detection(dev, nphy->clip_state);
370 b43_nphy_write_clip_detection(dev, clip);
371 }
372 b43_nphy_reset_cca(dev);
161d540c 373 } else {
ab499217
RM		 374 if (--nphy->deaf_count == 0) {
375 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
376 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 377 }
161d540c 378 }
161d540c
RM		 379}
380
64712095
RM		 381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
382static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 383{
161d540c 384 struct b43_phy_n *nphy = dev->phy.n;
161d540c 385
64712095
RM		 386 u8 i;
387 s16 tmp;
388 u16 data[4];
389 s16 gain[2];
390 u16 minmax[2];
391 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 392
393 if (nphy->hang_avoid)
394 b43_nphy_stay_in_carrier_search(dev, 1);
395
64712095 396 if (nphy->gain_boost) {
161d540c 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 398 gain[0] = 6;
399 gain[1] = 6;
161d540c 400 } else {
64712095
RM		 401 tmp = 40370 - 315 * dev->phy.channel;
402 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
403 tmp = 23242 - 224 * dev->phy.channel;
404 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 405 }
64712095
RM		 406 } else {
407 gain[0] = 0;
408 gain[1] = 0;
161d540c 409 }
161d540c
RM		 410
411 for (i = 0; i < 2; i++) {
64712095
RM		 412 if (nphy->elna_gain_config) {
413 data[0] = 19 + gain[i];
414 data[1] = 25 + gain[i];
415 data[2] = 25 + gain[i];
416 data[3] = 25 + gain[i];
161d540c 417 } else {
64712095
RM		 418 data[0] = lna_gain[0] + gain[i];
419 data[1] = lna_gain[1] + gain[i];
420 data[2] = lna_gain[2] + gain[i];
421 data[3] = lna_gain[3] + gain[i];
161d540c 422 }
64712095 423 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 424
64712095 425 minmax[i] = 23 + gain[i];
161d540c
RM		 426 }
427
64712095
RM		 428 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
429 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
430 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
431 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 432
433 if (nphy->hang_avoid)
434 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 435}
436
ab499217
RM		 437/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
438static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
439 u8 *events, u8 *delays, u8 length)
0eff8fcd 440{
ab499217
RM		 441 struct b43_phy_n *nphy = dev->phy.n;
442 u8 i;
443 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
444 u16 offset1 = cmd << 4;
445 u16 offset2 = offset1 + 0x80;
0eff8fcd 446
ab499217
RM		 447 if (nphy->hang_avoid)
448 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 449
ab499217
RM		 450 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
451 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 452
ab499217
RM		 453 for (i = length; i < 16; i++) {
454 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
455 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 456 }
ab499217
RM		 457
458 if (nphy->hang_avoid)
459 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 460}
7955de0c 461
572d37a4
RM		 462/**************************************************
463 * Radio 0x2057
464 **************************************************/
465
466/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
467static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
468{
469 struct b43_phy *phy = &dev->phy;
470 u16 tmp;
471
472 if (phy->radio_rev == 5) {
473 b43_phy_mask(dev, 0x342, ~0x2);
474 udelay(10);
475 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
476 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
477 }
478
479 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
480 udelay(10);
481 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
482 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
483 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
484 return 0;
485 }
486 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
487 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
488 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
489
490 if (phy->radio_rev == 5) {
491 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
492 b43_radio_mask(dev, 0x1ca, ~0x2);
493 }
494 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
495 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
496 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
497 tmp << 2);
498 }
499
500 return tmp & 0x3e;
501}
502
503/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
504static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
505{
506 struct b43_phy *phy = &dev->phy;
507 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
508 phy->radio_rev == 6);
509 u16 tmp;
510
511 if (special) {
512 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
513 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
514 } else {
515 b43_radio_write(dev, 0x1AE, 0x61);
516 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
517 }
518 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
519 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
520 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
521 5000000))
522 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
523 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
524 if (special) {
525 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
526 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
527 } else {
528 b43_radio_write(dev, 0x1AE, 0x69);
529 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
530 }
531 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
532 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
533 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
534 5000000))
535 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
536 if (special) {
537 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
538 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
539 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
540 } else {
541 b43_radio_write(dev, 0x1AE, 0x73);
542 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
543 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
544 }
545 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
546 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
547 5000000)) {
548 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
549 return 0;
550 }
551 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
552 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
553 return tmp;
554}
555
556static void b43_radio_2057_init_pre(struct b43_wldev *dev)
557{
558 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
559 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
560 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
561 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
562 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
563}
564
565static void b43_radio_2057_init_post(struct b43_wldev *dev)
566{
567 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
568
569 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
570 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
571 mdelay(2);
572 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
573 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
574
575 if (dev->phy.n->init_por) {
576 b43_radio_2057_rcal(dev);
577 b43_radio_2057_rccal(dev);
578 }
579 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
580
581 dev->phy.n->init_por = false;
582}
583
584/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
585static void b43_radio_2057_init(struct b43_wldev *dev)
586{
587 b43_radio_2057_init_pre(dev);
588 r2057_upload_inittabs(dev);
589 b43_radio_2057_init_post(dev);
590}
591
ab499217 592/**************************************************
884a5228 593 * Radio 0x2056
ab499217 594 **************************************************/
7955de0c 595
d4814e69
RM		 596static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
597 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 598{
d4814e69
RM		 599 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
600 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
601 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
602 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
603 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
604 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
605 e->radio_syn_pll_loopfilter1);
606 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
607 e->radio_syn_pll_loopfilter2);
608 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
609 e->radio_syn_pll_loopfilter3);
610 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
611 e->radio_syn_pll_loopfilter4);
612 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
613 e->radio_syn_pll_loopfilter5);
614 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
615 e->radio_syn_reserved_addr27);
616 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
617 e->radio_syn_reserved_addr28);
618 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
619 e->radio_syn_reserved_addr29);
620 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
621 e->radio_syn_logen_vcobuf1);
622 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
623 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
624 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
625
626 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
627 e->radio_rx0_lnaa_tune);
628 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
629 e->radio_rx0_lnag_tune);
630
631 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
632 e->radio_tx0_intpaa_boost_tune);
633 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
634 e->radio_tx0_intpag_boost_tune);
635 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
636 e->radio_tx0_pada_boost_tune);
637 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
638 e->radio_tx0_padg_boost_tune);
639 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
640 e->radio_tx0_pgaa_boost_tune);
641 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
642 e->radio_tx0_pgag_boost_tune);
643 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
644 e->radio_tx0_mixa_boost_tune);
645 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
646 e->radio_tx0_mixg_boost_tune);
647
648 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
649 e->radio_rx1_lnaa_tune);
650 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
651 e->radio_rx1_lnag_tune);
652
653 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
654 e->radio_tx1_intpaa_boost_tune);
655 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
656 e->radio_tx1_intpag_boost_tune);
657 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
658 e->radio_tx1_pada_boost_tune);
659 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
660 e->radio_tx1_padg_boost_tune);
661 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
662 e->radio_tx1_pgaa_boost_tune);
663 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
664 e->radio_tx1_pgag_boost_tune);
665 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
666 e->radio_tx1_mixa_boost_tune);
667 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
668 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 669}
670
d4814e69
RM		 671/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
672static void b43_radio_2056_setup(struct b43_wldev *dev,
673 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 674{
0581483a 675 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 676 enum ieee80211_band band = b43_current_band(dev->wl);
677 u16 offset;
678 u8 i;
d3d178f0
RM		 679 u16 bias, cbias;
680 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
681 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
036cafe4 682
d4814e69 683 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 684
d4814e69 685 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 686 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
687
688 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
689 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
690 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
691 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
692 if (dev->dev->chip_id == 0x4716) {
693 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
694 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
695 } else {
696 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
697 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 698 }
53a6e234 699 }
38646eba
RM		 700 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
701 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
702 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
703 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
704 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
705 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 706 }
53a6e234 707
38646eba
RM		 708 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
709 for (i = 0; i < 2; i++) {
710 offset = i ? B2056_TX1 : B2056_TX0;
711 if (dev->phy.rev >= 5) {
712 b43_radio_write(dev,
713 offset | B2056_TX_PADG_IDAC, 0xcc);
714
715 if (dev->dev->chip_id == 0x4716) {
716 bias = 0x40;
717 cbias = 0x45;
718 pag_boost = 0x5;
719 pgag_boost = 0x33;
720 mixg_boost = 0x55;
721 } else {
722 bias = 0x25;
723 cbias = 0x20;
724 pag_boost = 0x4;
725 pgag_boost = 0x03;
726 mixg_boost = 0x65;
727 }
728 padg_boost = 0x77;
729
730 b43_radio_write(dev,
731 offset | B2056_TX_INTPAG_IMAIN_STAT,
732 bias);
733 b43_radio_write(dev,
734 offset | B2056_TX_INTPAG_IAUX_STAT,
735 bias);
736 b43_radio_write(dev,
737 offset | B2056_TX_INTPAG_CASCBIAS,
738 cbias);
739 b43_radio_write(dev,
740 offset | B2056_TX_INTPAG_BOOST_TUNE,
741 pag_boost);
742 b43_radio_write(dev,
743 offset | B2056_TX_PGAG_BOOST_TUNE,
744 pgag_boost);
745 b43_radio_write(dev,
746 offset | B2056_TX_PADG_BOOST_TUNE,
747 padg_boost);
748 b43_radio_write(dev,
749 offset | B2056_TX_MIXG_BOOST_TUNE,
750 mixg_boost);
751 } else {
752 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
753 b43_radio_write(dev,
754 offset | B2056_TX_INTPAG_IMAIN_STAT,
755 bias);
756 b43_radio_write(dev,
757 offset | B2056_TX_INTPAG_IAUX_STAT,
758 bias);
759 b43_radio_write(dev,
760 offset | B2056_TX_INTPAG_CASCBIAS,
761 0x30);
762 }
763 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
764 }
765 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 766 u16 freq = dev->phy.channel_freq;
767 if (freq < 5100) {
768 paa_boost = 0xA;
769 pada_boost = 0x77;
770 pgaa_boost = 0xF;
771 mixa_boost = 0xF;
772 } else if (freq < 5340) {
773 paa_boost = 0x8;
774 pada_boost = 0x77;
775 pgaa_boost = 0xFB;
776 mixa_boost = 0xF;
777 } else if (freq < 5650) {
778 paa_boost = 0x0;
779 pada_boost = 0x77;
780 pgaa_boost = 0xB;
781 mixa_boost = 0xF;
782 } else {
783 paa_boost = 0x0;
784 pada_boost = 0x77;
785 if (freq != 5825)
786 pgaa_boost = -(freq - 18) / 36 + 168;
787 else
788 pgaa_boost = 6;
789 mixa_boost = 0xF;
790 }
791
792 for (i = 0; i < 2; i++) {
793 offset = i ? B2056_TX1 : B2056_TX0;
794
795 b43_radio_write(dev,
796 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
797 b43_radio_write(dev,
798 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
799 b43_radio_write(dev,
800 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
801 b43_radio_write(dev,
802 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
803 b43_radio_write(dev,
804 offset | B2056_TX_TXSPARE1, 0x30);
805 b43_radio_write(dev,
806 offset | B2056_TX_PA_SPARE2, 0xee);
807 b43_radio_write(dev,
808 offset | B2056_TX_PADA_CASCBIAS, 0x03);
809 b43_radio_write(dev,
810 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
811 b43_radio_write(dev,
812 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
813 b43_radio_write(dev,
814 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
815 }
a2d9bc6f 816 }
38646eba 817
d4814e69
RM		 818 udelay(50);
819 /* VCO calibration */
820 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
821 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
822 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
823 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
824 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
825 udelay(300);
53a6e234
MB		 826}
827
d3d178f0
RM		 828static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
829{
830 struct b43_phy *phy = &dev->phy;
831 u16 mast2, tmp;
832
833 if (phy->rev != 3)
834 return 0;
835
836 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
837 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
838
839 udelay(10);
840 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
841 udelay(10);
842 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
843
844 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
845 1000000)) {
846 b43err(dev->wl, "Radio recalibration timeout\n");
847 return 0;
848 }
849
850 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
851 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
852 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
853
854 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
855
856 return tmp & 0x1f;
857}
858
ea7ee14b
RM		 859static void b43_radio_init2056_pre(struct b43_wldev *dev)
860{
861 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
862 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
863 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
864 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
865 B43_NPHY_RFCTL_CMD_OEPORFORCE);
866 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
867 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
868 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
869 B43_NPHY_RFCTL_CMD_CHIP0PU);
870}
871
872static void b43_radio_init2056_post(struct b43_wldev *dev)
873{
874 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
875 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
876 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
877 msleep(1);
878 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
879 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
880 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 881 if (dev->phy.n->init_por)
882 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 883}
884
d817f4e1
RM		 885/*
886 * Initialize a Broadcom 2056 N-radio
887 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
888 */
889static void b43_radio_init2056(struct b43_wldev *dev)
890{
ea7ee14b
RM		 891 b43_radio_init2056_pre(dev);
892 b2056_upload_inittabs(dev, 0, 0);
893 b43_radio_init2056_post(dev);
d3d178f0
RM		 894
895 dev->phy.n->init_por = false;
d817f4e1
RM		 896}
897
884a5228
RM		 898/**************************************************
899 * Radio 0x2055
900 **************************************************/
901
902static void b43_chantab_radio_upload(struct b43_wldev *dev,
903 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 904{
884a5228
RM		 905 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
906 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
907 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
908 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
909 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 910
884a5228
RM		 911 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
912 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
913 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
914 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
915 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 916
884a5228
RM		 917 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
918 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
919 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
920 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
921 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 922
884a5228
RM		 923 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
924 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
925 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
926 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
927 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 928
884a5228
RM		 929 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
930 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
931 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
932 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
933 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 934
884a5228
RM		 935 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
936 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 937}
938
884a5228
RM		 939/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
940static void b43_radio_2055_setup(struct b43_wldev *dev,
941 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 942{
884a5228 943 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 944
884a5228
RM		 945 b43_chantab_radio_upload(dev, e);
946 udelay(50);
947 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
948 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
949 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
950 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
951 udelay(300);
95b66bad
MB		 952}
953
884a5228 954static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 955{
884a5228
RM		 956 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
957 ~B43_NPHY_RFCTL_CMD_PORFORCE);
958 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
959 B43_NPHY_RFCTL_CMD_CHIP0PU |
960 B43_NPHY_RFCTL_CMD_OEPORFORCE);
961 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
962 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 963}
964
884a5228 965static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 966{
967 struct b43_phy_n *nphy = dev->phy.n;
884a5228 968 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 969 bool workaround = false;
2faa6b83 970
884a5228
RM		 971 if (sprom->revision < 4)
972 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
973 && dev->dev->board_type == 0x46D
974 && dev->dev->board_rev >= 0x41);
2faa6b83 975 else
884a5228
RM		 976 workaround =
977 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 978
884a5228
RM		 979 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
980 if (workaround) {
981 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
982 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
983 }
984 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
985 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
986 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
987 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
988 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
989 msleep(1);
990 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 991 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 992 b43err(dev->wl, "radio post init timeout\n");
993 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
994 b43_switch_channel(dev, dev->phy.channel);
995 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
996 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
997 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
998 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
999 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1000 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1001 if (!nphy->gain_boost) {
1002 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1003 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1004 } else {
1005 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1006 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1007 }
1008 udelay(2);
2faa6b83
RM		 1009}
1010
884a5228
RM		 1011/*
1012 * Initialize a Broadcom 2055 N-radio
1013 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1014 */
1015static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1016{
884a5228
RM		 1017 b43_radio_init2055_pre(dev);
1018 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1019 /* Follow wl, not specs. Do not force uploading all regs */
1020 b2055_upload_inittab(dev, 0, 0);
a67162ab 1021 } else {
884a5228
RM		 1022 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1023 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1024 }
884a5228 1025 b43_radio_init2055_post(dev);
a67162ab
RM		 1026}
1027
8be89535
RM		 1028/**************************************************
1029 * Samples
1030 **************************************************/
026816fc 1031
8be89535
RM		 1032/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1033static int b43_nphy_load_samples(struct b43_wldev *dev,
1034 struct b43_c32 *samples, u16 len) {
1035 struct b43_phy_n *nphy = dev->phy.n;
1036 u16 i;
1037 u32 *data;
1038
1039 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1040 if (!data) {
1041 b43err(dev->wl, "allocation for samples loading failed\n");
1042 return -ENOMEM;
1043 }
1044 if (nphy->hang_avoid)
1045 b43_nphy_stay_in_carrier_search(dev, 1);
1046
1047 for (i = 0; i < len; i++) {
1048 data[i] = (samples[i].i & 0x3FF << 10);
1049 data[i] |= samples[i].q & 0x3FF;
1050 }
1051 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1052
1053 kfree(data);
1054 if (nphy->hang_avoid)
1055 b43_nphy_stay_in_carrier_search(dev, 0);
1056 return 0;
026816fc
RM		 1057}
1058
8be89535
RM		 1059/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1060static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1061 bool test)
026816fc 1062{
8be89535
RM		 1063 int i;
1064 u16 bw, len, rot, angle;
1065 struct b43_c32 *samples;
026816fc 1066
026816fc 1067
8be89535
RM		 1068 bw = (dev->phy.is_40mhz) ? 40 : 20;
1069 len = bw << 3;
026816fc 1070
8be89535
RM		 1071 if (test) {
1072 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1073 bw = 82;
1074 else
1075 bw = 80;
026816fc 1076
8be89535
RM		 1077 if (dev->phy.is_40mhz)
1078 bw <<= 1;
1079
1080 len = bw << 1;
026816fc
RM		 1081 }
1082
8be89535
RM		 1083 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1084 if (!samples) {
1085 b43err(dev->wl, "allocation for samples generation failed\n");
1086 return 0;
1087 }
1088 rot = (((freq * 36) / bw) << 16) / 100;
1089 angle = 0;
026816fc 1090
8be89535
RM		 1091 for (i = 0; i < len; i++) {
1092 samples[i] = b43_cordic(angle);
1093 angle += rot;
1094 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1095 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1096 }
8be89535
RM		 1097
1098 i = b43_nphy_load_samples(dev, samples, len);
1099 kfree(samples);
1100 return (i < 0) ? 0 : len;
026816fc
RM		 1101}
1102
8be89535
RM		 1103/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1104static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1105 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1106{
8be89535 1107 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1108 int i;
8be89535
RM		 1109 u16 seq_mode;
1110 u32 tmp;
34a56f2c 1111
8be89535
RM		 1112 if (nphy->hang_avoid)
1113 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1114
8be89535
RM		 1115 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1116 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1117 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1118 }
34a56f2c 1119
8be89535
RM		 1120 if (!dev->phy.is_40mhz)
1121 tmp = 0x6464;
1122 else
1123 tmp = 0x4747;
1124 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1125
8be89535
RM		 1126 if (nphy->hang_avoid)
1127 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c 1128
8be89535 1129 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1130
8be89535
RM		 1131 if (loops != 0xFFFF)
1132 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1133 else
1134 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1135
8be89535 1136 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1137
8be89535 1138 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1139
8be89535
RM		 1140 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1141 if (iqmode) {
1142 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1143 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1144 } else {
1145 if (dac_test)
1146 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1147 else
1148 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1149 }
1150 for (i = 0; i < 100; i++) {
2c8ac7eb 1151 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1152 i = 0;
1153 break;
34a56f2c 1154 }
8be89535 1155 udelay(10);
34a56f2c 1156 }
8be89535
RM		 1157 if (i)
1158 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1159
8be89535 1160 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
34a56f2c
RM		 1161}
1162
4d9f46ba
RM		 1163/**************************************************
1164 * RSSI
1165 **************************************************/
1166
1167/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1168static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1169 s8 offset, u8 core, u8 rail,
1170 enum b43_nphy_rssi_type type)
09146400 1171{
4d9f46ba
RM		 1172 u16 tmp;
1173 bool core1or5 = (core == 1) || (core == 5);
1174 bool core2or5 = (core == 2) || (core == 5);
09146400 1175
4d9f46ba
RM		 1176 offset = clamp_val(offset, -32, 31);
1177 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1178
4d9f46ba
RM		 1179 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1180 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1181 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1182 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1183 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1184 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1185 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1186 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
bbec398c 1187
4d9f46ba
RM		 1188 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1189 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1190 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1191 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1192 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1193 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1194 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1195 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
bbec398c 1196
4d9f46ba
RM		 1197 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1198 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1199 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1200 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1201 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1202 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1203 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1204 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
8987a9e9 1205
4d9f46ba
RM		 1206 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1207 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1208 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1209 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1210 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1211 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1212 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1213 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
6cbab0d9 1214
4d9f46ba
RM		 1215 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1216 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1217 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1218 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1219 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1220 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1221 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1222 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
8987a9e9 1223
4d9f46ba
RM		 1224 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1225 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1226 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1227 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1228
1229 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1230 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1231 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1232 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
8987a9e9
RM		 1233}
1234
4d9f46ba 1235static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
bbec398c 1236{
4d9f46ba
RM		 1237 u8 i;
1238 u16 reg, val;
bbec398c 1239
4d9f46ba
RM		 1240 if (code == 0) {
1241 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1242 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1243 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1244 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1245 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1246 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1247 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1248 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1249 } else {
1250 for (i = 0; i < 2; i++) {
1251 if ((code == 1 && i == 1) || (code == 2 && !i))
1252 continue;
bbec398c 1253
4d9f46ba
RM		 1254 reg = (i == 0) ?
1255 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1256 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1257
4d9f46ba
RM		 1258 if (type < 3) {
1259 reg = (i == 0) ?
1260 B43_NPHY_AFECTL_C1 :
1261 B43_NPHY_AFECTL_C2;
1262 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1263
4d9f46ba
RM		 1264 reg = (i == 0) ?
1265 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1266 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1267 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1268
4d9f46ba
RM		 1269 if (type == 0)
1270 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1271 else if (type == 1)
1272 val = 16;
1273 else
1274 val = 32;
1275 b43_phy_set(dev, reg, val);
5c1a140a 1276
4d9f46ba
RM		 1277 reg = (i == 0) ?
1278 B43_NPHY_TXF_40CO_B1S0 :
1279 B43_NPHY_TXF_40CO_B32S1;
1280 b43_phy_set(dev, reg, 0x0020);
1281 } else {
1282 if (type == 6)
1283 val = 0x0100;
1284 else if (type == 3)
1285 val = 0x0200;
1286 else
1287 val = 0x0300;
5c1a140a 1288
4d9f46ba
RM		 1289 reg = (i == 0) ?
1290 B43_NPHY_AFECTL_C1 :
1291 B43_NPHY_AFECTL_C2;
53ae8e8c 1292
4d9f46ba
RM		 1293 b43_phy_maskset(dev, reg, 0xFCFF, val);
1294 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1295
4d9f46ba
RM		 1296 if (type != 3 && type != 6) {
1297 enum ieee80211_band band =
1298 b43_current_band(dev->wl);
53ae8e8c 1299
4d9f46ba
RM		 1300 if (b43_nphy_ipa(dev))
1301 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1302 else
1303 val = 0x11;
1304 reg = (i == 0) ? 0x2000 : 0x3000;
1305 reg |= B2055_PADDRV;
1306 b43_radio_write16(dev, reg, val);
53ae8e8c 1307
4d9f46ba
RM		 1308 reg = (i == 0) ?
1309 B43_NPHY_AFECTL_OVER1 :
1310 B43_NPHY_AFECTL_OVER;
1311 b43_phy_set(dev, reg, 0x0200);
1312 }
1313 }
1314 }
53ae8e8c 1315 }
53ae8e8c
RM		 1316}
1317
4d9f46ba 1318static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
9442e5b5 1319{
4d9f46ba 1320 u16 val;
9442e5b5 1321
4d9f46ba
RM		 1322 if (type < 3)
1323 val = 0;
1324 else if (type == 6)
1325 val = 1;
1326 else if (type == 3)
1327 val = 2;
1328 else
1329 val = 3;
9442e5b5 1330
4d9f46ba
RM		 1331 val = (val << 12) | (val << 14);
1332 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1333 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1334
4d9f46ba
RM		 1335 if (type < 3) {
1336 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1337 (type + 1) << 4);
1338 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1339 (type + 1) << 4);
9442e5b5
RM		 1340 }
1341
4d9f46ba
RM		 1342 if (code == 0) {
1343 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1344 if (type < 3) {
1345 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1346 ~(B43_NPHY_RFCTL_CMD_RXEN |
1347 B43_NPHY_RFCTL_CMD_CORESEL));
1348 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1349 ~(0x1 << 12 |
1350 0x1 << 5 |
1351 0x1 << 1 |
1352 0x1));
1353 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1354 ~B43_NPHY_RFCTL_CMD_START);
1355 udelay(20);
1356 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1357 }
1358 } else {
1359 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1360 if (type < 3) {
1361 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1362 ~(B43_NPHY_RFCTL_CMD_RXEN |
1363 B43_NPHY_RFCTL_CMD_CORESEL),
1364 (B43_NPHY_RFCTL_CMD_RXEN |
1365 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1366 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1367 (0x1 << 12 |
1368 0x1 << 5 |
1369 0x1 << 1 |
1370 0x1));
1371 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1372 B43_NPHY_RFCTL_CMD_START);
1373 udelay(20);
1374 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1375 }
9442e5b5 1376 }
9442e5b5
RM		 1377}
1378
4d9f46ba
RM		 1379/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1380static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
d24019ad 1381{
4d9f46ba
RM		 1382 if (dev->phy.rev >= 3)
1383 b43_nphy_rev3_rssi_select(dev, code, type);
1384 else
1385 b43_nphy_rev2_rssi_select(dev, code, type);
1386}
d24019ad 1387
5ecab603
RM		 1388/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1389static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1390{
1391 int i;
d24019ad 1392 for (i = 0; i < 2; i++) {
5ecab603
RM		 1393 if (type == 2) {
1394 if (i == 0) {
1395 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1396 0xFC, buf[0]);
1397 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1398 0xFC, buf[1]);
1399 } else {
1400 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1401 0xFC, buf[2 * i]);
1402 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1403 0xFC, buf[2 * i + 1]);
1404 }
d24019ad 1405 } else {
5ecab603
RM		 1406 if (i == 0)
1407 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1408 0xF3, buf[0] << 2);
1409 else
1410 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1411 0xF3, buf[2 * i + 1] << 2);
d24019ad 1412 }
d24019ad 1413 }
d24019ad
RM		 1414}
1415
5ecab603
RM		 1416/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1417static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1418 u8 nsamp)
ef5127a4 1419{
5ecab603
RM		 1420 int i;
1421 int out;
1422 u16 save_regs_phy[9];
1423 u16 s[2];
ef5127a4
RM		 1424
1425 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1426 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1427 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1428 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1429 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1430 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1431 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1432 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1433 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1434 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1435 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1436 save_regs_phy[8] = 0;
ef5127a4 1437 } else {
5ecab603
RM		 1438 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1439 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1440 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1441 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1442 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1443 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1444 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1445 save_regs_phy[7] = 0;
1446 save_regs_phy[8] = 0;
1447 }
ef5127a4 1448
5ecab603 1449 b43_nphy_rssi_select(dev, 5, type);
ef5127a4 1450
5ecab603
RM		 1451 if (dev->phy.rev < 2) {
1452 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1453 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1454 }
ef5127a4 1455
5ecab603
RM		 1456 for (i = 0; i < 4; i++)
1457 buf[i] = 0;
1458
1459 for (i = 0; i < nsamp; i++) {
1460 if (dev->phy.rev < 2) {
1461 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1462 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1463 } else {
5ecab603
RM		 1464 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1465 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1466 }
1467
5ecab603
RM		 1468 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1469 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1470 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1471 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1472 }
1473 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1474 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1475
5ecab603
RM		 1476 if (dev->phy.rev < 2)
1477 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1478
5ecab603 1479 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1480 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1481 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1482 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1483 save_regs_phy[2]);
5ecab603 1484 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1485 save_regs_phy[3]);
5ecab603
RM		 1486 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1487 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1488 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1489 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1490 } else {
1491 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1492 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1493 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1494 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1495 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1496 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1497 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1498 }
ef5127a4 1499
5ecab603
RM		 1500 return out;
1501}
ef5127a4 1502
e0c9a021
RM		 1503/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1504static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1505{
1506 struct b43_phy_n *nphy = dev->phy.n;
1507
1508 u16 saved_regs_phy_rfctl[2];
1509 u16 saved_regs_phy[13];
1510 u16 regs_to_store[] = {
1511 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1512 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1513 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1514 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1515 B43_NPHY_RFCTL_CMD,
1516 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1517 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1518 };
1519
1520 u16 class;
1521
1522 u16 clip_state[2];
1523 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1524
1525 u8 vcm_final = 0;
1526 s8 offset[4];
1527 s32 results[8][4] = { };
1528 s32 results_min[4] = { };
1529 s32 poll_results[4] = { };
1530
1531 u16 *rssical_radio_regs = NULL;
1532 u16 *rssical_phy_regs = NULL;
1533
1534 u16 r; /* routing */
1535 u8 rx_core_state;
1536 u8 core, i, j;
1537
1538 class = b43_nphy_classifier(dev, 0, 0);
1539 b43_nphy_classifier(dev, 7, 4);
1540 b43_nphy_read_clip_detection(dev, clip_state);
1541 b43_nphy_write_clip_detection(dev, clip_off);
1542
1543 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1544 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1545 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1546 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1547
1548 b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1549 b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1550 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1551 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1552 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1553 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1554
1555 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1556 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1557 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1558 } else {
1559 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1560 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1561 }
1562
1563 rx_core_state = b43_nphy_get_rx_core_state(dev);
1564 for (core = 0; core < 2; core++) {
1565 if (!(rx_core_state & (1 << core)))
1566 continue;
1567 r = core ? B2056_RX1 : B2056_RX0;
1568 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2);
1569 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2);
1570 for (i = 0; i < 8; i++) {
1571 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1572 i << 2);
1573 b43_nphy_poll_rssi(dev, 2, results[i], 8);
1574 }
cddec902 1575 for (i = 0; i < 4; i += 2) {
e0c9a021
RM		 1576 s32 curr;
1577 s32 mind = 40;
1578 s32 minpoll = 249;
1579 u8 minvcm = 0;
1580 if (2 * core != i)
1581 continue;
1582 for (j = 0; j < 8; j++) {
1583 curr = results[j][i] * results[j][i] +
1584 results[j][i + 1] * results[j][i];
1585 if (curr < mind) {
1586 mind = curr;
1587 minvcm = j;
1588 }
1589 if (results[j][i] < minpoll)
1590 minpoll = results[j][i];
1591 }
1592 vcm_final = minvcm;
1593 results_min[i] = minpoll;
1594 }
1595 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1596 vcm_final << 2);
1597 for (i = 0; i < 4; i++) {
1598 if (core != i / 2)
1599 continue;
1600 offset[i] = -results[vcm_final][i];
1601 if (offset[i] < 0)
1602 offset[i] = -((abs(offset[i]) + 4) / 8);
1603 else
1604 offset[i] = (offset[i] + 4) / 8;
1605 if (results_min[i] == 248)
1606 offset[i] = -32;
1607 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1608 (i / 2 == 0) ? 1 : 2,
1609 (i % 2 == 0) ? 0 : 1,
1610 2);
1611 }
1612 }
1613 for (core = 0; core < 2; core++) {
1614 if (!(rx_core_state & (1 << core)))
1615 continue;
1616 for (i = 0; i < 2; i++) {
1617 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i);
1618 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i);
1619 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1620 for (j = 0; j < 4; j++) {
cddec902 1621 if (j / 2 == core) {
e0c9a021 1622 offset[j] = 232 - poll_results[j];
cddec902
RM		 1623 if (offset[j] < 0)
1624 offset[j] = -(abs(offset[j] + 4) / 8);
1625 else
1626 offset[j] = (offset[j] + 4) / 8;
1627 b43_nphy_scale_offset_rssi(dev, 0,
1628 offset[2 * core], core + 1, j % 2, i);
1629 }
e0c9a021
RM		 1630 }
1631 }
1632 }
1633
1634 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1635 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1636
1637 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1638
1639 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1640 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1641 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1642
1643 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1644 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1645 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1646
1647 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1648 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1649
1650 /* Store for future configuration */
1651 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1652 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1653 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1654 } else {
1655 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1656 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1657 }
1658 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1659 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1660 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1661 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1662 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1663 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1664 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1665 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1666 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1667 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1668 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1669 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1670 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1671 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1672
1673 /* Remember for which channel we store configuration */
1674 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1675 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1676 else
1677 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1678
1679 /* End of calibration, restore configuration */
1680 b43_nphy_classifier(dev, 7, class);
1681 b43_nphy_write_clip_detection(dev, clip_state);
1682}
1683
5ecab603
RM		 1684/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1685static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1686{
1687 int i, j;
1688 u8 state[4];
1689 u8 code, val;
1690 u16 class, override;
1691 u8 regs_save_radio[2];
1692 u16 regs_save_phy[2];
1693
1694 s8 offset[4];
1695 u8 core;
1696 u8 rail;
1697
1698 u16 clip_state[2];
1699 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1700 s32 results_min[4] = { };
1701 u8 vcm_final[4] = { };
1702 s32 results[4][4] = { };
1703 s32 miniq[4][2] = { };
1704
1705 if (type == 2) {
1706 code = 0;
1707 val = 6;
1708 } else if (type < 2) {
1709 code = 25;
1710 val = 4;
1711 } else {
1712 B43_WARN_ON(1);
1713 return;
1714 }
1715
1716 class = b43_nphy_classifier(dev, 0, 0);
1717 b43_nphy_classifier(dev, 7, 4);
1718 b43_nphy_read_clip_detection(dev, clip_state);
1719 b43_nphy_write_clip_detection(dev, clip_off);
1720
1721 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1722 override = 0x140;
1723 else
1724 override = 0x110;
1725
1726 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1727 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1728 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1729 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1730
1731 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1732 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1733 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1734 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1735
1736 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1737 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1738 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1739 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1740 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1741 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1742
1743 b43_nphy_rssi_select(dev, 5, type);
1744 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1745 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1746
1747 for (i = 0; i < 4; i++) {
1748 u8 tmp[4];
1749 for (j = 0; j < 4; j++)
1750 tmp[j] = i;
1751 if (type != 1)
1752 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1753 b43_nphy_poll_rssi(dev, type, results[i], 8);
1754 if (type < 2)
1755 for (j = 0; j < 2; j++)
1756 miniq[i][j] = min(results[i][2 * j],
1757 results[i][2 * j + 1]);
1758 }
1759
1760 for (i = 0; i < 4; i++) {
1761 s32 mind = 40;
1762 u8 minvcm = 0;
1763 s32 minpoll = 249;
1764 s32 curr;
1765 for (j = 0; j < 4; j++) {
1766 if (type == 2)
1767 curr = abs(results[j][i]);
1768 else
1769 curr = abs(miniq[j][i / 2] - code * 8);
1770
1771 if (curr < mind) {
1772 mind = curr;
1773 minvcm = j;
1774 }
1775
1776 if (results[j][i] < minpoll)
1777 minpoll = results[j][i];
8e60b044 1778 }
5ecab603
RM		 1779 results_min[i] = minpoll;
1780 vcm_final[i] = minvcm;
1781 }
ef5127a4 1782
5ecab603
RM		 1783 if (type != 1)
1784 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 1785
5ecab603
RM		 1786 for (i = 0; i < 4; i++) {
1787 offset[i] = (code * 8) - results[vcm_final[i]][i];
1788
1789 if (offset[i] < 0)
1790 offset[i] = -((abs(offset[i]) + 4) / 8);
1791 else
1792 offset[i] = (offset[i] + 4) / 8;
1793
1794 if (results_min[i] == 248)
1795 offset[i] = code - 32;
1796
1797 core = (i / 2) ? 2 : 1;
1798 rail = (i % 2) ? 1 : 0;
1799
1800 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1801 type);
1802 }
1803
1804 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1805 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1806
1807 switch (state[2]) {
1808 case 1:
1809 b43_nphy_rssi_select(dev, 1, 2);
1810 break;
1811 case 4:
1812 b43_nphy_rssi_select(dev, 1, 0);
1813 break;
1814 case 2:
1815 b43_nphy_rssi_select(dev, 1, 1);
1816 break;
1817 default:
1818 b43_nphy_rssi_select(dev, 1, 1);
1819 break;
1820 }
1821
1822 switch (state[3]) {
1823 case 1:
1824 b43_nphy_rssi_select(dev, 2, 2);
1825 break;
1826 case 4:
1827 b43_nphy_rssi_select(dev, 2, 0);
1828 break;
1829 default:
1830 b43_nphy_rssi_select(dev, 2, 1);
1831 break;
1832 }
1833
1834 b43_nphy_rssi_select(dev, 0, type);
1835
1836 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1837 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1838 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1839 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1840
1841 b43_nphy_classifier(dev, 7, class);
1842 b43_nphy_write_clip_detection(dev, clip_state);
1843 /* Specs don't say about reset here, but it makes wl and b43 dumps
1844 identical, it really seems wl performs this */
1845 b43_nphy_reset_cca(dev);
1846}
1847
5ecab603
RM		 1848/*
1849 * RSSI Calibration
1850 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1851 */
1852static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1853{
1854 if (dev->phy.rev >= 3) {
1855 b43_nphy_rev3_rssi_cal(dev);
1856 } else {
1857 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1858 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1859 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1860 }
1861}
1862
64712095
RM		 1863/**************************************************
1864 * Workarounds
1865 **************************************************/
1866
1867static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1868{
1869 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1870
1871 bool ghz5;
1872 bool ext_lna;
1873 u16 rssi_gain;
1874 struct nphy_gain_ctl_workaround_entry *e;
1875 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1876 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1877
1878 /* Prepare values */
1879 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1880 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 1881 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1882 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 1883 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1884 if (ghz5 && dev->phy.rev >= 5)
1885 rssi_gain = 0x90;
1886 else
1887 rssi_gain = 0x50;
1888
1889 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1890
1891 /* Set Clip 2 detect */
1892 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1893 B43_NPHY_C1_CGAINI_CL2DETECT);
1894 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1895 B43_NPHY_C2_CGAINI_CL2DETECT);
1896
1897 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1898 0x17);
1899 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1900 0x17);
1901 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1902 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1903 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1904 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1905 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1906 rssi_gain);
1907 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1908 rssi_gain);
1909 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1910 0x17);
1911 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1912 0x17);
1913 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1914 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1915
1916 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1917 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1918 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1919 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1920 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1921 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1922 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1923 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1924 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1925 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1926 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1927 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1928
1929 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1930 b43_phy_write(dev, 0x2A7, e->init_gain);
1931 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1932 e->rfseq_init);
64712095
RM		 1933
1934 /* TODO: check defines. Do not match variables names */
1935 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1936 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1937 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1938 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1939 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1940 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1941
1942 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1943 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1944 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1945 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1946 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1947 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1948 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1949 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1950 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1951 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1952}
1953
1954static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1955{
1956 struct b43_phy_n *nphy = dev->phy.n;
1957
1958 u8 i, j;
1959 u8 code;
1960 u16 tmp;
1961 u8 rfseq_events[3] = { 6, 8, 7 };
1962 u8 rfseq_delays[3] = { 10, 30, 1 };
1963
1964 /* Set Clip 2 detect */
1965 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1966 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1967
1968 /* Set narrowband clip threshold */
1969 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1970 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1971
1972 if (!dev->phy.is_40mhz) {
1973 /* Set dwell lengths */
1974 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1975 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1976 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1977 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1978 }
1979
1980 /* Set wideband clip 2 threshold */
1981 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1982 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
1983 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1984 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
1985
1986 if (!dev->phy.is_40mhz) {
1987 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1988 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1989 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1990 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1991 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1992 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1993 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1994 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1995 }
1996
1997 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1998
1999 if (nphy->gain_boost) {
2000 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2001 dev->phy.is_40mhz)
2002 code = 4;
2003 else
2004 code = 5;
2005 } else {
2006 code = dev->phy.is_40mhz ? 6 : 7;
2007 }
2008
2009 /* Set HPVGA2 index */
2010 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2011 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2012 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2013 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2014
2015 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2016 /* specs say about 2 loops, but wl does 4 */
2017 for (i = 0; i < 4; i++)
2018 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2019
2020 b43_nphy_adjust_lna_gain_table(dev);
2021
2022 if (nphy->elna_gain_config) {
2023 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2024 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2025 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2026 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2027 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2028
2029 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2030 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2031 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2032 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2033 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2034
2035 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2036 /* specs say about 2 loops, but wl does 4 */
2037 for (i = 0; i < 4; i++)
2038 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2039 (code << 8 | 0x74));
2040 }
2041
2042 if (dev->phy.rev == 2) {
2043 for (i = 0; i < 4; i++) {
2044 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2045 (0x0400 * i) + 0x0020);
2046 for (j = 0; j < 21; j++) {
2047 tmp = j * (i < 2 ? 3 : 1);
2048 b43_phy_write(dev,
2049 B43_NPHY_TABLE_DATALO, tmp);
2050 }
2051 }
ef5127a4 2052 }
64712095
RM		 2053
2054 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2055 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2056 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2057 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2058
2059 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2060 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2061}
2062
2063/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2064static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2065{
d11d354b
RM		 2066 if (dev->phy.rev >= 7)
2067 ; /* TODO */
2068 else if (dev->phy.rev >= 3)
64712095
RM		 2069 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2070 else
2071 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2072}
2073
d11d354b
RM		 2074/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2075static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2076{
2077 if (!offset)
2078 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2079 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2080}
2081
2082static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2083{
2084 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2085 struct b43_phy *phy = &dev->phy;
2086
2087 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2088 0x1F };
2089 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2090
2091 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2092 u8 ntab7_138_146[] = { 0x11, 0x11 };
2093 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2094
2095 u16 lpf_20, lpf_40, lpf_11b;
2096 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2097 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2098 bool rccal_ovrd = false;
2099
2100 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2101 u16 bias, conv, filt;
2102
2103 u32 tmp32;
2104 u8 core;
2105
2106 if (phy->rev == 7) {
2107 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2108 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2109 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2110 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2111 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2112 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2113 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2114 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2115 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2116 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2117 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2118 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2119 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2120 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2121 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2122 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2123 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2124 }
2125 if (phy->rev <= 8) {
2126 b43_phy_write(dev, 0x23F, 0x1B0);
2127 b43_phy_write(dev, 0x240, 0x1B0);
2128 }
2129 if (phy->rev >= 8)
2130 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2131
2132 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2133 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2134 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2135 tmp32 &= 0xffffff;
2136 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2137 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2138 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2139
2140 if (b43_nphy_ipa(dev))
2141 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2142 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2143
2144 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2145 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2146
2147 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2148 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2149 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2150 if (b43_nphy_ipa(dev)) {
2151 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2152 phy->radio_rev == 7 || phy->radio_rev == 8) {
2153 bcap_val = b43_radio_read(dev, 0x16b);
2154 scap_val = b43_radio_read(dev, 0x16a);
2155 scap_val_11b = scap_val;
2156 bcap_val_11b = bcap_val;
2157 if (phy->radio_rev == 5 && phy->is_40mhz) {
2158 scap_val_11n_20 = scap_val;
2159 bcap_val_11n_20 = bcap_val;
2160 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2161 rccal_ovrd = true;
2162 } else { /* Rev 7/8 */
2163 lpf_20 = 4;
2164 lpf_11b = 1;
2165 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2166 scap_val_11n_20 = 0xc;
2167 bcap_val_11n_20 = 0xc;
2168 scap_val_11n_40 = 0xa;
2169 bcap_val_11n_40 = 0xa;
2170 } else {
2171 scap_val_11n_20 = 0x14;
2172 bcap_val_11n_20 = 0x14;
2173 scap_val_11n_40 = 0xf;
2174 bcap_val_11n_40 = 0xf;
2175 }
2176 rccal_ovrd = true;
2177 }
2178 }
2179 } else {
2180 if (phy->radio_rev == 5) {
2181 lpf_20 = 1;
2182 lpf_40 = 3;
2183 bcap_val = b43_radio_read(dev, 0x16b);
2184 scap_val = b43_radio_read(dev, 0x16a);
2185 scap_val_11b = scap_val;
2186 bcap_val_11b = bcap_val;
2187 scap_val_11n_20 = 0x11;
2188 scap_val_11n_40 = 0x11;
2189 bcap_val_11n_20 = 0x13;
2190 bcap_val_11n_40 = 0x13;
2191 rccal_ovrd = true;
2192 }
2193 }
2194 if (rccal_ovrd) {
2195 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2196 (scap_val_11b << 3) |
2197 lpf_11b;
2198 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2199 (scap_val_11n_20 << 3) |
2200 lpf_20;
2201 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2202 (scap_val_11n_40 << 3) |
2203 lpf_40;
2204 for (core = 0; core < 2; core++) {
2205 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2206 rx2tx_lut_20_11b);
2207 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2208 rx2tx_lut_20_11n);
2209 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2210 rx2tx_lut_20_11n);
2211 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2212 rx2tx_lut_40_11n);
2213 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2214 rx2tx_lut_40_11n);
2215 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2216 rx2tx_lut_40_11n);
2217 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2218 rx2tx_lut_40_11n);
2219 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2220 rx2tx_lut_40_11n);
2221 }
2222 /* b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, 0, 2); */
2223 }
2224 b43_phy_write(dev, 0x32F, 0x3);
2225 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2226 ; /* b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, 0, 0); */
2227
2228 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2229 if (sprom->revision &&
2230 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2231 b43_radio_write(dev, 0x5, 0x05);
2232 b43_radio_write(dev, 0x6, 0x30);
2233 b43_radio_write(dev, 0x7, 0x00);
2234 b43_radio_set(dev, 0x4f, 0x1);
2235 b43_radio_set(dev, 0xd4, 0x1);
2236 bias = 0x1f;
2237 conv = 0x6f;
2238 filt = 0xaa;
2239 } else {
2240 bias = 0x2b;
2241 conv = 0x7f;
2242 filt = 0xee;
2243 }
2244 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2245 for (core = 0; core < 2; core++) {
2246 if (core == 0) {
2247 b43_radio_write(dev, 0x5F, bias);
2248 b43_radio_write(dev, 0x64, conv);
2249 b43_radio_write(dev, 0x66, filt);
2250 } else {
2251 b43_radio_write(dev, 0xE8, bias);
2252 b43_radio_write(dev, 0xE9, conv);
2253 b43_radio_write(dev, 0xEB, filt);
2254 }
2255 }
2256 }
2257 }
2258
2259 if (b43_nphy_ipa(dev)) {
2260 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2261 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2262 phy->radio_rev == 6) {
2263 for (core = 0; core < 2; core++) {
2264 if (core == 0)
2265 b43_radio_write(dev, 0x51,
2266 0x7f);
2267 else
2268 b43_radio_write(dev, 0xd6,
2269 0x7f);
2270 }
2271 }
2272 if (phy->radio_rev == 3) {
2273 for (core = 0; core < 2; core++) {
2274 if (core == 0) {
2275 b43_radio_write(dev, 0x64,
2276 0x13);
2277 b43_radio_write(dev, 0x5F,
2278 0x1F);
2279 b43_radio_write(dev, 0x66,
2280 0xEE);
2281 b43_radio_write(dev, 0x59,
2282 0x8A);
2283 b43_radio_write(dev, 0x80,
2284 0x3E);
2285 } else {
2286 b43_radio_write(dev, 0x69,
2287 0x13);
2288 b43_radio_write(dev, 0xE8,
2289 0x1F);
2290 b43_radio_write(dev, 0xEB,
2291 0xEE);
2292 b43_radio_write(dev, 0xDE,
2293 0x8A);
2294 b43_radio_write(dev, 0x105,
2295 0x3E);
2296 }
2297 }
2298 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2299 if (!phy->is_40mhz) {
2300 b43_radio_write(dev, 0x5F, 0x14);
2301 b43_radio_write(dev, 0xE8, 0x12);
2302 } else {
2303 b43_radio_write(dev, 0x5F, 0x16);
2304 b43_radio_write(dev, 0xE8, 0x16);
2305 }
2306 }
2307 } else {
2308 u16 freq = phy->channel_freq;
2309 if ((freq >= 5180 && freq <= 5230) ||
2310 (freq >= 5745 && freq <= 5805)) {
2311 b43_radio_write(dev, 0x7D, 0xFF);
2312 b43_radio_write(dev, 0xFE, 0xFF);
2313 }
2314 }
2315 } else {
2316 if (phy->radio_rev != 5) {
2317 for (core = 0; core < 2; core++) {
2318 if (core == 0) {
2319 b43_radio_write(dev, 0x5c, 0x61);
2320 b43_radio_write(dev, 0x51, 0x70);
2321 } else {
2322 b43_radio_write(dev, 0xe1, 0x61);
2323 b43_radio_write(dev, 0xd6, 0x70);
2324 }
2325 }
2326 }
2327 }
2328
2329 if (phy->radio_rev == 4) {
2330 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2331 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2332 for (core = 0; core < 2; core++) {
2333 if (core == 0) {
2334 b43_radio_write(dev, 0x1a1, 0x00);
2335 b43_radio_write(dev, 0x1a2, 0x3f);
2336 b43_radio_write(dev, 0x1a6, 0x3f);
2337 } else {
2338 b43_radio_write(dev, 0x1a7, 0x00);
2339 b43_radio_write(dev, 0x1ab, 0x3f);
2340 b43_radio_write(dev, 0x1ac, 0x3f);
2341 }
2342 }
2343 } else {
2344 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2345 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2346 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2347 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2348
2349 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2350 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2351 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2352 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2353 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2354 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2355
2356 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2357 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2358 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2359 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2360 }
2361
2362 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2363
2364 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2365 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2366 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2367 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2368 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2369 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2370 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2371
2372 if (!phy->is_40mhz) {
2373 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2374 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2375 } else {
2376 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2377 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2378 }
2379
2380 b43_nphy_gain_ctl_workarounds(dev);
2381
2382 /* TODO
2383 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2384 aux_adc_vmid_rev7_core0);
2385 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2386 aux_adc_vmid_rev7_core1);
2387 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2388 aux_adc_gain_rev7);
2389 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2390 aux_adc_gain_rev7);
2391 */
2392}
2393
73d07a39 2394static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2395{
0eff8fcd 2396 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2397 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2398
0eff8fcd 2399 /* TX to RX */
c56da252
RM		 2400 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2401 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
0eff8fcd
RM		 2402 /* RX to TX */
2403 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2404 0x1F };
2405 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2406 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2407 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2408
ba9a6214
RM		 2409 u16 tmp16;
2410 u32 tmp32;
2411
c56da252
RM		 2412 b43_phy_write(dev, 0x23f, 0x1f8);
2413 b43_phy_write(dev, 0x240, 0x1f8);
2414
73d07a39
RM		 2415 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2416 tmp32 &= 0xffffff;
2417 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2418
73d07a39
RM		 2419 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2420 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2421 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2422 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2423 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2424 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2425
73d07a39
RM		 2426 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2427 b43_phy_write(dev, 0x2AE, 0x000C);
ba9a6214 2428
0eff8fcd 2429 /* TX to RX */
c56da252
RM		 2430 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2431 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2432
2433 /* RX to TX */
2434 if (b43_nphy_ipa(dev))
c56da252
RM		 2435 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2436 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2437 if (nphy->hw_phyrxchain != 3 &&
2438 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2439 if (b43_nphy_ipa(dev)) {
2440 rx2tx_delays[5] = 59;
2441 rx2tx_delays[6] = 1;
2442 rx2tx_events[7] = 0x1F;
2443 }
fa0f2b38 2444 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2445 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2446 }
ba9a6214 2447
73d07a39
RM		 2448 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2449 0x2 : 0x9C40;
2450 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2451
73d07a39 2452 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
ba9a6214 2453
fa0f2b38
RM		 2454 if (!dev->phy.is_40mhz) {
2455 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2456 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2457 } else {
2458 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2459 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2460 }
ba9a6214 2461
3ccd0957 2462 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2463
c56da252
RM		 2464 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2465 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2466
73d07a39 2467 /* TODO */
ba9a6214 2468
73d07a39
RM		 2469 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2470 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2471 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2472 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2473 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2474 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2475 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2476 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2477 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2478 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2479 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2480 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2481
2482 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2483
2484 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2485 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2486 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2487 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2488 tmp32 = 0x00088888;
2489 else
2490 tmp32 = 0x88888888;
2491 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2492 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2493 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2494
2495 if (dev->phy.rev == 4 &&
fa0f2b38 2496 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2497 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2498 0x70);
2499 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2500 0x70);
2501 }
ba9a6214 2502
fa0f2b38 2503 /* Dropped probably-always-true condition */
3c17dd41
RM		 2504 b43_phy_write(dev, 0x224, 0x03eb);
2505 b43_phy_write(dev, 0x225, 0x03eb);
2506 b43_phy_write(dev, 0x226, 0x0341);
2507 b43_phy_write(dev, 0x227, 0x0341);
2508 b43_phy_write(dev, 0x228, 0x042b);
2509 b43_phy_write(dev, 0x229, 0x042b);
2510 b43_phy_write(dev, 0x22a, 0x0381);
2511 b43_phy_write(dev, 0x22b, 0x0381);
2512 b43_phy_write(dev, 0x22c, 0x042b);
2513 b43_phy_write(dev, 0x22d, 0x042b);
2514 b43_phy_write(dev, 0x22e, 0x0381);
2515 b43_phy_write(dev, 0x22f, 0x0381);
fa0f2b38
RM		 2516
2517 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2518 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2519}
ba9a6214 2520
73d07a39
RM		 2521static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2522{
2523 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2524 struct b43_phy *phy = &dev->phy;
2525 struct b43_phy_n *nphy = phy->n;
ba9a6214 2526
73d07a39
RM		 2527 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2528 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2529
73d07a39
RM		 2530 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2531 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2532
fa0f2b38
RM		 2533 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2534 dev->dev->board_type == 0x8B) {
2535 delays1[0] = 0x1;
2536 delays1[5] = 0x14;
2537 }
2538
73d07a39
RM		 2539 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2540 nphy->band5g_pwrgain) {
2541 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2542 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2543 } else {
73d07a39
RM		 2544 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2545 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2546 }
28fd7daa 2547
73d07a39
RM		 2548 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2549 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2550 if (dev->phy.rev < 3) {
2551 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2552 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2553 }
73d07a39
RM		 2554
2555 if (dev->phy.rev < 2) {
2556 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2557 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2558 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2559 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2560 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2561 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2562 }
28fd7daa 2563
73d07a39
RM		 2564 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2565 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2566 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2567 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2568
73d07a39
RM		 2569 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2570 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2571
3ccd0957 2572 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2573
2574 if (dev->phy.rev < 2) {
2575 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2576 b43_hf_write(dev, b43_hf_read(dev) |
2577 B43_HF_MLADVW);
2578 } else if (dev->phy.rev == 2) {
2579 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2580 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2581 }
28fd7daa 2582
73d07a39
RM		 2583 if (dev->phy.rev < 2)
2584 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2585 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2586
2587 /* Set phase track alpha and beta */
2588 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2589 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2590 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2591 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2592 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2593 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2594
fa0f2b38
RM		 2595 if (dev->phy.rev < 3) {
2596 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2597 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2598 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2599 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2600 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2601 }
73d07a39
RM		 2602
2603 if (dev->phy.rev == 2)
2604 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2605 B43_NPHY_FINERX2_CGC_DECGC);
2606}
28fd7daa 2607
73d07a39
RM		 2608/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2609static void b43_nphy_workarounds(struct b43_wldev *dev)
2610{
2611 struct b43_phy *phy = &dev->phy;
2612 struct b43_phy_n *nphy = phy->n;
28fd7daa 2613
73d07a39
RM		 2614 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2615 b43_nphy_classifier(dev, 1, 0);
2616 else
2617 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2618
73d07a39
RM		 2619 if (nphy->hang_avoid)
2620 b43_nphy_stay_in_carrier_search(dev, 1);
2621
2622 b43_phy_set(dev, B43_NPHY_IQFLIP,
2623 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2624
d11d354b
RM		 2625 if (dev->phy.rev >= 7)
2626 b43_nphy_workarounds_rev7plus(dev);
2627 else if (dev->phy.rev >= 3)
73d07a39
RM		 2628 b43_nphy_workarounds_rev3plus(dev);
2629 else
2630 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2631
2632 if (nphy->hang_avoid)
2633 b43_nphy_stay_in_carrier_search(dev, 0);
2634}
2635
9dd4d9b9
RM		 2636/**************************************************
2637 * Tx/Rx common
2638 **************************************************/
2639
2640/*
2641 * Transmits a known value for LO calibration
2642 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2643 */
2644static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2645 bool iqmode, bool dac_test)
2646{
2647 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2648 if (samp == 0)
2649 return -1;
2650 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2651 return 0;
2652}
2653
2654/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2655static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2656{
2657 struct b43_phy_n *nphy = dev->phy.n;
2658
2659 bool override = false;
2660 u16 chain = 0x33;
2661
2662 if (nphy->txrx_chain == 0) {
2663 chain = 0x11;
2664 override = true;
2665 } else if (nphy->txrx_chain == 1) {
2666 chain = 0x22;
2667 override = true;
2668 }
2669
2670 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2671 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2672 chain);
2673
2674 if (override)
2675 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2676 B43_NPHY_RFSEQMODE_CAOVER);
2677 else
2678 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2679 ~B43_NPHY_RFSEQMODE_CAOVER);
2680}
2681
2682/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2683static void b43_nphy_stop_playback(struct b43_wldev *dev)
2684{
2685 struct b43_phy_n *nphy = dev->phy.n;
2686 u16 tmp;
2687
2688 if (nphy->hang_avoid)
2689 b43_nphy_stay_in_carrier_search(dev, 1);
2690
2691 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2692 if (tmp & 0x1)
2693 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2694 else if (tmp & 0x2)
2695 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2696
2697 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2698
2699 if (nphy->bb_mult_save & 0x80000000) {
2700 tmp = nphy->bb_mult_save & 0xFFFF;
2701 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2702 nphy->bb_mult_save = 0;
2703 }
2704
2705 if (nphy->hang_avoid)
2706 b43_nphy_stay_in_carrier_search(dev, 0);
2707}
2708
2709/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2710static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2711 struct nphy_txgains target,
2712 struct nphy_iqcal_params *params)
2713{
2714 int i, j, indx;
2715 u16 gain;
2716
2717 if (dev->phy.rev >= 3) {
2718 params->txgm = target.txgm[core];
2719 params->pga = target.pga[core];
2720 params->pad = target.pad[core];
2721 params->ipa = target.ipa[core];
2722 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2723 (params->pad << 4) | (params->ipa);
2724 for (j = 0; j < 5; j++)
2725 params->ncorr[j] = 0x79;
2726 } else {
2727 gain = (target.pad[core]) | (target.pga[core] << 4) |
2728 (target.txgm[core] << 8);
2729
2730 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2731 1 : 0;
2732 for (i = 0; i < 9; i++)
2733 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2734 break;
2735 i = min(i, 8);
2736
2737 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2738 params->pga = tbl_iqcal_gainparams[indx][i][2];
2739 params->pad = tbl_iqcal_gainparams[indx][i][3];
2740 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2741 (params->pad << 2);
2742 for (j = 0; j < 4; j++)
2743 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2744 }
2745}
2746
884a5228 2747/**************************************************
104cfa88 2748 * Tx and Rx
884a5228 2749 **************************************************/
5f6393ec 2750
884a5228
RM		 2751void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
2752{//TODO
5f6393ec
RM		 2753}
2754
884a5228
RM		 2755static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2756{//TODO
2757}
59af099b 2758
884a5228
RM		 2759static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2760 bool ignore_tssi)
2761{//TODO
2762 return B43_TXPWR_RES_DONE;
2763}
59af099b 2764
161d540c
RM		 2765/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2766static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2767{
2768 struct b43_phy_n *nphy = dev->phy.n;
2769 u8 i;
c9c0d9ec
RM		 2770 u16 bmask, val, tmp;
2771 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 2772
161d540c
RM		 2773 if (nphy->hang_avoid)
2774 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 2775
161d540c
RM		 2776 nphy->txpwrctrl = enable;
2777 if (!enable) {
c9c0d9ec
RM		 2778 if (dev->phy.rev >= 3 &&
2779 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2780 (B43_NPHY_TXPCTL_CMD_COEFF |
2781 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2782 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2783 /* We disable enabled TX pwr ctl, save it's state */
2784 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2785 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2786 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2787 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2788 }
59af099b 2789
161d540c
RM		 2790 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2791 for (i = 0; i < 84; i++)
2792 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2793
161d540c
RM		 2794 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2795 for (i = 0; i < 84; i++)
2796 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2797
161d540c
RM		 2798 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2799 if (dev->phy.rev >= 3)
2800 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2801 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 2802
161d540c
RM		 2803 if (dev->phy.rev >= 3) {
2804 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2805 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2806 } else {
2807 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2808 }
10a79873 2809
161d540c
RM		 2810 if (dev->phy.rev == 2)
2811 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2812 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2813 else if (dev->phy.rev < 2)
2814 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2815 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 2816
c9c0d9ec
RM		 2817 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2818 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 2819 } else {
c9c0d9ec
RM		 2820 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2821 nphy->adj_pwr_tbl);
2822 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2823 nphy->adj_pwr_tbl);
10a79873 2824
c9c0d9ec
RM		 2825 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2826 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2827 /* wl does useless check for "enable" param here */
2828 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2829 if (dev->phy.rev >= 3) {
2830 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2831 if (val)
2832 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2833 }
2834 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 2835
c9c0d9ec
RM		 2836 if (band == IEEE80211_BAND_5GHZ) {
2837 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2838 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2839 if (dev->phy.rev > 1)
2840 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2841 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2842 0x64);
2843 }
10a79873 2844
c9c0d9ec
RM		 2845 if (dev->phy.rev >= 3) {
2846 if (nphy->tx_pwr_idx[0] != 128 &&
2847 nphy->tx_pwr_idx[1] != 128) {
2848 /* Recover TX pwr ctl state */
2849 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2850 ~B43_NPHY_TXPCTL_CMD_INIT,
2851 nphy->tx_pwr_idx[0]);
2852 if (dev->phy.rev > 1)
2853 b43_phy_maskset(dev,
2854 B43_NPHY_TXPCTL_INIT,
2855 ~0xff, nphy->tx_pwr_idx[1]);
2856 }
2857 }
10a79873 2858
c9c0d9ec
RM		 2859 if (dev->phy.rev >= 3) {
2860 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2861 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2862 } else {
2863 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2864 }
10a79873 2865
c9c0d9ec
RM		 2866 if (dev->phy.rev == 2)
2867 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2868 else if (dev->phy.rev < 2)
2869 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 2870
c9c0d9ec
RM		 2871 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2872 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 2873
c002831a 2874 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 2875 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2876 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 2877 }
10a79873 2878 }
10a79873 2879
161d540c
RM		 2880 if (nphy->hang_avoid)
2881 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 2882}
2883
161d540c 2884/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 2885static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 2886{
2887 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2888 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 2889
161d540c
RM		 2890 u8 txpi[2], bbmult, i;
2891 u16 tmp, radio_gain, dac_gain;
2892 u16 freq = dev->phy.channel_freq;
2893 u32 txgain;
2894 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 2895
2896 if (nphy->hang_avoid)
161d540c 2897 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 2898
dd5f13b8
RM		 2899 if (dev->phy.rev >= 7) {
2900 txpi[0] = txpi[1] = 30;
2901 } else if (dev->phy.rev >= 3) {
161d540c
RM		 2902 txpi[0] = 40;
2903 txpi[1] = 40;
2904 } else if (sprom->revision < 4) {
2905 txpi[0] = 72;
2906 txpi[1] = 72;
2907 } else {
2908 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2909 txpi[0] = sprom->txpid2g[0];
2910 txpi[1] = sprom->txpid2g[1];
2911 } else if (freq >= 4900 && freq < 5100) {
2912 txpi[0] = sprom->txpid5gl[0];
2913 txpi[1] = sprom->txpid5gl[1];
2914 } else if (freq >= 5100 && freq < 5500) {
2915 txpi[0] = sprom->txpid5g[0];
2916 txpi[1] = sprom->txpid5g[1];
2917 } else if (freq >= 5500) {
2918 txpi[0] = sprom->txpid5gh[0];
2919 txpi[1] = sprom->txpid5gh[1];
2920 } else {
2921 txpi[0] = 91;
2922 txpi[1] = 91;
6dcd9d91
RM		 2923 }
2924 }
dd5f13b8 2925 if (dev->phy.rev < 7 &&
9bd28571 2926 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 2927 txpi[0] = txpi[1] = 91;
6dcd9d91 2928
161d540c
RM		 2929 /*
2930 for (i = 0; i < 2; i++) {
2931 nphy->txpwrindex[i].index_internal = txpi[i];
2932 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 2933 }
161d540c 2934 */
75377b24 2935
161d540c 2936 for (i = 0; i < 2; i++) {
aeab5751
RM		 2937 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2938
2939 if (dev->phy.rev >= 3)
161d540c 2940 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 2941 else
161d540c 2942 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 2943
dd5f13b8
RM		 2944 if (dev->phy.rev >= 7)
2945 dac_gain = (txgain >> 8) & 0x7;
2946 else
2947 dac_gain = (txgain >> 8) & 0x3F;
161d540c 2948 bbmult = txgain & 0xFF;
75377b24 2949
161d540c
RM		 2950 if (dev->phy.rev >= 3) {
2951 if (i == 0)
2952 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2953 else
2954 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2955 } else {
2956 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2957 }
75377b24 2958
161d540c
RM		 2959 if (i == 0)
2960 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2961 else
2962 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 2963
44f4008b 2964 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 2965
44f4008b 2966 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 2967 if (i == 0)
2968 tmp = (tmp & 0x00FF) | (bbmult << 8);
2969 else
2970 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 2971 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 2972
0eff8fcd
RM		 2973 if (b43_nphy_ipa(dev)) {
2974 u32 tmp32;
2975 u16 reg = (i == 0) ?
2976 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 2977 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
2978 576 + txpi[i]));
0eff8fcd
RM		 2979 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
2980 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 2981 }
2982 }
75377b24 2983
161d540c 2984 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 2985
161d540c
RM		 2986 if (nphy->hang_avoid)
2987 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 2988}
67cbc3ed 2989
3dda07b6
RM		 2990static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
2991{
2992 struct b43_phy *phy = &dev->phy;
2993
2994 u8 core;
2995 u16 r; /* routing */
2996
2997 if (phy->rev >= 7) {
2998 for (core = 0; core < 2; core++) {
2999 r = core ? 0x190 : 0x170;
3000 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3001 b43_radio_write(dev, r + 0x5, 0x5);
3002 b43_radio_write(dev, r + 0x9, 0xE);
3003 if (phy->rev != 5)
3004 b43_radio_write(dev, r + 0xA, 0);
3005 if (phy->rev != 7)
3006 b43_radio_write(dev, r + 0xB, 1);
3007 else
3008 b43_radio_write(dev, r + 0xB, 0x31);
3009 } else {
3010 b43_radio_write(dev, r + 0x5, 0x9);
3011 b43_radio_write(dev, r + 0x9, 0xC);
3012 b43_radio_write(dev, r + 0xB, 0x0);
3013 if (phy->rev != 5)
3014 b43_radio_write(dev, r + 0xA, 1);
3015 else
3016 b43_radio_write(dev, r + 0xA, 0x31);
3017 }
3018 b43_radio_write(dev, r + 0x6, 0);
3019 b43_radio_write(dev, r + 0x7, 0);
3020 b43_radio_write(dev, r + 0x8, 3);
3021 b43_radio_write(dev, r + 0xC, 0);
3022 }
3023 } else {
3024 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3025 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3026 else
3027 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3028 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3029 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3030
3031 for (core = 0; core < 2; core++) {
3032 r = core ? B2056_TX1 : B2056_TX0;
3033
3034 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3035 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3036 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3037 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3038 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3039 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3040 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3041 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3042 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3043 0x5);
3044 if (phy->rev != 5)
3045 b43_radio_write(dev, r | B2056_TX_TSSIA,
3046 0x00);
3047 if (phy->rev >= 5)
3048 b43_radio_write(dev, r | B2056_TX_TSSIG,
3049 0x31);
3050 else
3051 b43_radio_write(dev, r | B2056_TX_TSSIG,
3052 0x11);
3053 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3054 0xE);
3055 } else {
3056 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3057 0x9);
3058 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3059 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3060 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3061 0xC);
3062 }
3063 }
3064 }
3065}
3066
3067/*
3068 * Stop radio and transmit known signal. Then check received signal strength to
3069 * get TSSI (Transmit Signal Strength Indicator).
3070 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3071 */
3072static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3073{
3074 struct b43_phy *phy = &dev->phy;
3075 struct b43_phy_n *nphy = dev->phy.n;
3076
3077 u32 tmp;
3078 s32 rssi[4] = { };
3079
3080 /* TODO: check if we can transmit */
3081
3082 if (b43_nphy_ipa(dev))
3083 b43_nphy_ipa_internal_tssi_setup(dev);
3084
3085 if (phy->rev >= 7)
3086 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 0, 0 as arguments */
3087 else if (phy->rev >= 3)
3088 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3089
3090 b43_nphy_stop_playback(dev);
3091 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3092 udelay(20);
3093 tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
3094 b43_nphy_stop_playback(dev);
3095 b43_nphy_rssi_select(dev, 0, 0);
3096
3097 if (phy->rev >= 7)
3098 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 1, 0 as arguments */
3099 else if (phy->rev >= 3)
3100 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3101
3102 if (phy->rev >= 3) {
3103 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3104 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3105 } else {
3106 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3107 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3108 }
3109 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3110 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3111}
3112
d3fd8bf7
RM		 3113/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3114static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3115{
3116 struct b43_phy_n *nphy = dev->phy.n;
3117
3118 u8 idx, delta;
3119 u8 i, stf_mode;
3120
3121 for (i = 0; i < 4; i++)
3122 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3123
3124 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3125 delta = 0;
3126 switch (stf_mode) {
3127 case 0:
3128 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3129 idx = 68;
3130 } else {
3131 delta = 1;
3132 idx = dev->phy.is_40mhz ? 52 : 4;
3133 }
3134 break;
3135 case 1:
3136 idx = dev->phy.is_40mhz ? 76 : 28;
3137 break;
3138 case 2:
3139 idx = dev->phy.is_40mhz ? 84 : 36;
3140 break;
3141 case 3:
3142 idx = dev->phy.is_40mhz ? 92 : 44;
3143 break;
3144 }
3145
3146 for (i = 0; i < 20; i++) {
3147 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3148 nphy->tx_power_offset[idx];
3149 if (i == 0)
3150 idx += delta;
3151 if (i == 14)
3152 idx += 1 - delta;
3153 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3154 i == 13)
3155 idx += 1;
3156 }
3157 }
3158}
3159
3160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3161static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3162{
3163 struct b43_phy_n *nphy = dev->phy.n;
3164 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3165
3166 s16 a1[2], b0[2], b1[2];
3167 u8 idle[2];
3168 s8 target[2];
3169 s32 num, den, pwr;
3170 u32 regval[64];
3171
3172 u16 freq = dev->phy.channel_freq;
3173 u16 tmp;
3174 u16 r; /* routing */
3175 u8 i, c;
3176
3177 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3178 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3179 b43_read32(dev, B43_MMIO_MACCTL);
3180 udelay(1);
3181 }
3182
3183 if (nphy->hang_avoid)
3184 b43_nphy_stay_in_carrier_search(dev, true);
3185
3186 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3187 if (dev->phy.rev >= 3)
3188 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3189 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3190 else
3191 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3192 B43_NPHY_TXPCTL_CMD_PCTLEN);
3193
3194 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3195 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3196
3197 if (sprom->revision < 4) {
3198 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3199 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3200 target[0] = target[1] = 52;
3201 a1[0] = a1[1] = -424;
3202 b0[0] = b0[1] = 5612;
3203 b1[0] = b1[1] = -1393;
3204 } else {
3205 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3206 for (c = 0; c < 2; c++) {
3207 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3208 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3209 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3210 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3211 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3212 }
3213 } else if (freq >= 4900 && freq < 5100) {
3214 for (c = 0; c < 2; c++) {
3215 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3216 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3217 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3218 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3219 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3220 }
3221 } else if (freq >= 5100 && freq < 5500) {
3222 for (c = 0; c < 2; c++) {
3223 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3224 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3225 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3226 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3227 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3228 }
3229 } else if (freq >= 5500) {
3230 for (c = 0; c < 2; c++) {
3231 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3232 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3233 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3234 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3235 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3236 }
3237 } else {
3238 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3239 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3240 target[0] = target[1] = 52;
3241 a1[0] = a1[1] = -424;
3242 b0[0] = b0[1] = 5612;
3243 b1[0] = b1[1] = -1393;
3244 }
3245 }
3246 /* target[0] = target[1] = nphy->tx_power_max; */
3247
3248 if (dev->phy.rev >= 3) {
3249 if (sprom->fem.ghz2.tssipos)
3250 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3251 if (dev->phy.rev >= 7) {
3252 for (c = 0; c < 2; c++) {
3253 r = c ? 0x190 : 0x170;
3254 if (b43_nphy_ipa(dev))
3255 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3256 }
3257 } else {
3258 if (b43_nphy_ipa(dev)) {
3259 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3260 b43_radio_write(dev,
3261 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3262 b43_radio_write(dev,
3263 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3264 } else {
3265 b43_radio_write(dev,
3266 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3267 b43_radio_write(dev,
3268 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3269 }
3270 }
3271 }
3272
3273 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3274 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3275 b43_read32(dev, B43_MMIO_MACCTL);
3276 udelay(1);
3277 }
3278
3279 if (dev->phy.rev >= 7) {
3280 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3281 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3282 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3283 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3284 } else {
3285 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3286 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3287 if (dev->phy.rev > 1)
3288 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3289 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3290 }
3291
3292 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3293 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3294
3295 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3296 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3297 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3298 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3299 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3300 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3301 B43_NPHY_TXPCTL_ITSSI_BINF);
3302 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3303 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3304 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3305
3306 for (c = 0; c < 2; c++) {
3307 for (i = 0; i < 64; i++) {
3308 num = 8 * (16 * b0[c] + b1[c] * i);
3309 den = 32768 + a1[c] * i;
3310 pwr = max((4 * num + den / 2) / den, -8);
3311 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3312 pwr = max(pwr, target[c] + 1);
3313 regval[i] = pwr;
3314 }
3315 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3316 }
3317
3318 b43_nphy_tx_prepare_adjusted_power_table(dev);
3319 /*
3320 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3321 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3322 */
3323
3324 if (nphy->hang_avoid)
3325 b43_nphy_stay_in_carrier_search(dev, false);
3326}
3327
0eff8fcd
RM		 3328static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3329{
3330 struct b43_phy *phy = &dev->phy;
67cbc3ed 3331
0eff8fcd 3332 const u32 *table = NULL;
0eff8fcd
RM		 3333 u32 rfpwr_offset;
3334 u8 pga_gain;
3335 int i;
0eff8fcd 3336
aeab5751 3337 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3338 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3339 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3340
3341 if (phy->rev >= 3) {
3342#if 0
3343 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3344#endif
0eff8fcd
RM		 3345
3346 for (i = 0; i < 128; i++) {
3347 pga_gain = (table[i] >> 24) & 0xF;
3348 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3349 rfpwr_offset =
3350 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3351 else
34c5cf20
RM		 3352 rfpwr_offset =
3353 0; /* FIXME */
0eff8fcd
RM		 3354 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3355 rfpwr_offset);
3356 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3357 rfpwr_offset);
3358 }
67cbc3ed
RM		 3359 }
3360}
3361
e50cbcf6
RM		 3362/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3363static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3364{
e50cbcf6
RM		 3365 struct b43_phy_n *nphy = dev->phy.n;
3366 enum ieee80211_band band;
3367 u16 tmp;
95b66bad 3368
e50cbcf6
RM		 3369 if (!enable) {
3370 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3371 B43_NPHY_RFCTL_INTC1);
3372 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3373 B43_NPHY_RFCTL_INTC2);
3374 band = b43_current_band(dev->wl);
3375 if (dev->phy.rev >= 3) {
3376 if (band == IEEE80211_BAND_5GHZ)
3377 tmp = 0x600;
3378 else
3379 tmp = 0x480;
3380 } else {
3381 if (band == IEEE80211_BAND_5GHZ)
3382 tmp = 0x180;
3383 else
3384 tmp = 0x120;
3385 }
3386 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3387 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3388 } else {
3389 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3390 nphy->rfctrl_intc1_save);
3391 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3392 nphy->rfctrl_intc2_save);
95b66bad 3393 }
95b66bad
MB		 3394}
3395
fe3e46e8
RM		 3396/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3397static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3398{
3399 u16 tmp;
3c95627d 3400
fe3e46e8 3401 if (dev->phy.rev >= 3) {
c002831a 3402 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3403 tmp = 4;
3404 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3405 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3406 }
76b002bd 3407
fe3e46e8
RM		 3408 tmp = 1;
3409 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3410 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3411 }
3412}
76b002bd 3413
2faa6b83
RM		 3414/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3415static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3416 u16 samps, u8 time, bool wait)
3c95627d 3417{
2faa6b83
RM		 3418 int i;
3419 u16 tmp;
3c95627d 3420
2faa6b83
RM		 3421 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3422 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3423 if (wait)
3424 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3425 else
2faa6b83 3426 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3427
2faa6b83 3428 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3429
2faa6b83
RM		 3430 for (i = 1000; i; i--) {
3431 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3432 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3433 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3434 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3435 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3436 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3437 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3438 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3439
2faa6b83
RM		 3440 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3441 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3442 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3443 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3444 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3445 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3446 return;
3c95627d 3447 }
2faa6b83 3448 udelay(10);
3c95627d 3449 }
2faa6b83 3450 memset(est, 0, sizeof(*est));
3c95627d
RM		 3451}
3452
a67162ab
RM		 3453/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3454static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3455 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3456{
a67162ab
RM		 3457 if (write) {
3458 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3459 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3460 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3461 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3462 } else {
a67162ab
RM		 3463 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3464 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3465 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3466 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3467 }
3468}
6e3b15a9 3469
c7455cf9
RM		 3470#if 0
3471/* Ready but not used anywhere */
026816fc
RM		 3472/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3473static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3474{
3475 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3476
026816fc
RM		 3477 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3478 if (core == 0) {
3479 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3480 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3481 } else {
3482 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3483 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3484 }
3485 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3486 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3487 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3488 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3489 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3490 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3491 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3492 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3493}
6e3b15a9 3494
026816fc
RM		 3495/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3496static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3497{
3498 u8 rxval, txval;
3499 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3500
026816fc
RM		 3501 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3502 if (core == 0) {
3503 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3504 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3505 } else {
3506 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3507 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3508 }
3509 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3510 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3511 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3512 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3513 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3514 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3515 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3516 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3517
026816fc
RM		 3518 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3519 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3520
acd82aa8
LF		 3521 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3522 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3523 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3524 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3525 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3526 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3527 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3528 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3529 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3530
026816fc
RM		 3531 if (core == 0) {
3532 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3533 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3534 } else {
3535 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3536 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3537 }
6e3b15a9 3538
67cbc3ed
RM		 3539 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3540 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 3541 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3542
026816fc
RM		 3543 if (core == 0) {
3544 rxval = 1;
3545 txval = 8;
3546 } else {
3547 rxval = 4;
3548 txval = 2;
6e3b15a9 3549 }
67cbc3ed
RM		 3550 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3551 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
99b82c41 3552}
c7455cf9 3553#endif
99b82c41 3554
34a56f2c
RM		 3555/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3556static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3557{
3558 int i;
34a56f2c
RM		 3559 s32 iq;
3560 u32 ii;
3561 u32 qq;
3562 int iq_nbits, qq_nbits;
3563 int arsh, brsh;
3564 u16 tmp, a, b;
3565
3566 struct nphy_iq_est est;
3567 struct b43_phy_n_iq_comp old;
3568 struct b43_phy_n_iq_comp new = { };
3569 bool error = false;
3570
3571 if (mask == 0)
3572 return;
3573
3574 b43_nphy_rx_iq_coeffs(dev, false, &old);
3575 b43_nphy_rx_iq_coeffs(dev, true, &new);
3576 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3577 new = old;
3578
dfb4aa5d 3579 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3580 if (i == 0 && (mask & 1)) {
3581 iq = est.iq0_prod;
3582 ii = est.i0_pwr;
3583 qq = est.q0_pwr;
3584 } else if (i == 1 && (mask & 2)) {
3585 iq = est.iq1_prod;
3586 ii = est.i1_pwr;
3587 qq = est.q1_pwr;
dfb4aa5d 3588 } else {
34a56f2c 3589 continue;
dfb4aa5d 3590 }
dfb4aa5d 3591
34a56f2c
RM		 3592 if (ii + qq < 2) {
3593 error = true;
3594 break;
3595 }
dfb4aa5d 3596
34a56f2c
RM		 3597 iq_nbits = fls(abs(iq));
3598 qq_nbits = fls(qq);
dfb4aa5d 3599
34a56f2c
RM		 3600 arsh = iq_nbits - 20;
3601 if (arsh >= 0) {
3602 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3603 tmp = ii >> arsh;
3604 } else {
3605 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3606 tmp = ii << -arsh;
3607 }
3608 if (tmp == 0) {
3609 error = true;
3610 break;
3611 }
3612 a /= tmp;
dfb4aa5d 3613
34a56f2c
RM		 3614 brsh = qq_nbits - 11;
3615 if (brsh >= 0) {
3616 b = (qq << (31 - qq_nbits));
3617 tmp = ii >> brsh;
dfb4aa5d 3618 } else {
34a56f2c
RM		 3619 b = (qq << (31 - qq_nbits));
3620 tmp = ii << -brsh;
3621 }
3622 if (tmp == 0) {
3623 error = true;
3624 break;
dfb4aa5d 3625 }
34a56f2c 3626 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3627
34a56f2c
RM		 3628 if (i == 0 && (mask & 0x1)) {
3629 if (dev->phy.rev >= 3) {
3630 new.a0 = a & 0x3FF;
3631 new.b0 = b & 0x3FF;
3632 } else {
3633 new.a0 = b & 0x3FF;
3634 new.b0 = a & 0x3FF;
3635 }
3636 } else if (i == 1 && (mask & 0x2)) {
3637 if (dev->phy.rev >= 3) {
3638 new.a1 = a & 0x3FF;
3639 new.b1 = b & 0x3FF;
3640 } else {
3641 new.a1 = b & 0x3FF;
3642 new.b1 = a & 0x3FF;
3643 }
3644 }
dfb4aa5d 3645 }
dfb4aa5d 3646
34a56f2c
RM		 3647 if (error)
3648 new = old;
dfb4aa5d 3649
34a56f2c
RM		 3650 b43_nphy_rx_iq_coeffs(dev, true, &new);
3651}
dfb4aa5d 3652
09146400
RM		 3653/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3654static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3655{
3656 u16 array[4];
44f4008b 3657 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3658
3659 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3660 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3661 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3662 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3663}
3664
9442e5b5
RM		 3665/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3666static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3667{
3668 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3669
204a665b 3670 u8 channel = dev->phy.channel;
9442e5b5
RM		 3671 int tone[2] = { 57, 58 };
3672 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3673
9442e5b5 3674 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3675
9442e5b5
RM		 3676 if (nphy->hang_avoid)
3677 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3678
9442e5b5
RM		 3679 if (nphy->gband_spurwar_en) {
3680 /* TODO: N PHY Adjust Analog Pfbw (7) */
3681 if (channel == 11 && dev->phy.is_40mhz)
3682 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3683 else
3684 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3685 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 3686 }
3687
9442e5b5
RM		 3688 if (nphy->aband_spurwar_en) {
3689 if (channel == 54) {
3690 tone[0] = 0x20;
3691 noise[0] = 0x25F;
3692 } else if (channel == 38 || channel == 102 || channel == 118) {
3693 if (0 /* FIXME */) {
3694 tone[0] = 0x20;
3695 noise[0] = 0x21F;
3696 } else {
3697 tone[0] = 0;
3698 noise[0] = 0;
90b9738d 3699 }
9442e5b5
RM		 3700 } else if (channel == 134) {
3701 tone[0] = 0x20;
3702 noise[0] = 0x21F;
3703 } else if (channel == 151) {
3704 tone[0] = 0x10;
3705 noise[0] = 0x23F;
3706 } else if (channel == 153 || channel == 161) {
3707 tone[0] = 0x30;
3708 noise[0] = 0x23F;
3709 } else {
3710 tone[0] = 0;
3711 noise[0] = 0;
90b9738d 3712 }
90b9738d 3713
9442e5b5
RM		 3714 if (!tone[0] && !noise[0])
3715 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 3716 else
9442e5b5
RM		 3717 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3718 }
90b9738d 3719
9442e5b5
RM		 3720 if (nphy->hang_avoid)
3721 b43_nphy_stay_in_carrier_search(dev, 0);
3722}
90b9738d 3723
5ecab603
RM		 3724/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3725static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3726{
3727 struct b43_phy_n *nphy = dev->phy.n;
3728 int i, j;
3729 u32 tmp;
3730 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 3731
5ecab603 3732 u16 buffer[7];
90b9738d 3733
5ecab603
RM		 3734 if (nphy->hang_avoid)
3735 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 3736
5ecab603 3737 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 3738
5ecab603
RM		 3739 for (i = 0; i < 2; i++) {
3740 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3741 (buffer[i * 2 + 1] & 0x3FF);
3742 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3743 (((i + 26) << 10) | 320));
3744 for (j = 0; j < 128; j++) {
3745 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3746 ((tmp >> 16) & 0xFFFF));
3747 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3748 (tmp & 0xFFFF));
90b9738d 3749 }
90b9738d 3750 }
90b9738d 3751
5ecab603
RM		 3752 for (i = 0; i < 2; i++) {
3753 tmp = buffer[5 + i];
3754 real_part = (tmp >> 8) & 0xFF;
3755 imag_part = (tmp & 0xFF);
3756 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3757 (((i + 26) << 10) | 448));
90b9738d 3758
5ecab603
RM		 3759 if (dev->phy.rev >= 3) {
3760 cur_real = real_part;
3761 cur_imag = imag_part;
3762 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3763 }
4cb99775 3764
5ecab603
RM		 3765 for (j = 0; j < 128; j++) {
3766 if (dev->phy.rev < 3) {
3767 cur_real = (real_part * loscale[j] + 128) >> 8;
3768 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3769 tmp = ((cur_real & 0xFF) << 8) |
3770 (cur_imag & 0xFF);
3771 }
3772 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3773 ((tmp >> 16) & 0xFFFF));
3774 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3775 (tmp & 0xFFFF));
3776 }
90b9738d 3777 }
4cb99775 3778
4cb99775 3779 if (dev->phy.rev >= 3) {
5ecab603
RM		 3780 b43_shm_write16(dev, B43_SHM_SHARED,
3781 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3782 b43_shm_write16(dev, B43_SHM_SHARED,
3783 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 3784 }
90b9738d 3785
5ecab603
RM		 3786 if (nphy->hang_avoid)
3787 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 3788}
3789
42e1547e
RM		 3790/*
3791 * Restore RSSI Calibration
3792 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3793 */
3794static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3795{
3796 struct b43_phy_n *nphy = dev->phy.n;
3797
3798 u16 *rssical_radio_regs = NULL;
3799 u16 *rssical_phy_regs = NULL;
3800
3801 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3802 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 3803 return;
3804 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3805 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3806 } else {
204a665b 3807 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 3808 return;
3809 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3810 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3811 }
3812
3813 /* TODO use some definitions */
3814 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3815 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3816
3817 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3818 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3819 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3820 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3821
3822 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3823 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3824 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3825 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3826
3827 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3828 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3829 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3830 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3831}
3832
c4a92003
RM		 3833/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3834static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3835{
3836 struct b43_phy_n *nphy = dev->phy.n;
3837 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 3838 u16 tmp;
3839 u8 offset, i;
c4a92003
RM		 3840
3841 if (dev->phy.rev >= 3) {
52cb5e97
RM		 3842 for (i = 0; i < 2; i++) {
3843 tmp = (i == 0) ? 0x2000 : 0x3000;
3844 offset = i * 11;
3845
3846 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3847 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3848 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3849 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3850 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3851 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3852 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3853 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3854 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3855 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3856 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3857
3858 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3859 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3860 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3861 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3862 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3863 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3864 if (nphy->ipa5g_on) {
3865 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3866 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3867 } else {
3868 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3869 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3870 }
3871 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3872 } else {
3873 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3874 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3875 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3876 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3877 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3878 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3879 if (nphy->ipa2g_on) {
3880 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3881 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3882 (dev->phy.rev < 5) ? 0x11 : 0x01);
3883 } else {
3884 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3885 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3886 }
3887 }
3888 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3889 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3890 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3891 }
c4a92003
RM		 3892 } else {
3893 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3894 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3895
3896 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3897 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3898
3899 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3900 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3901
3902 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3903 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3904
3905 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3906 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3907
3908 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3909 B43_NPHY_BANDCTL_5GHZ)) {
3910 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3911 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3912 } else {
3913 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3914 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3915 }
3916
3917 if (dev->phy.rev < 2) {
3918 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3919 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3920 } else {
3921 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3922 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3923 }
3924 }
3925}
3926
de7ed0c6
RM		 3927/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3928static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3929{
3930 struct b43_phy_n *nphy = dev->phy.n;
3931 int i;
3932 u16 scale, entry;
3933
3934 u16 tmp = nphy->txcal_bbmult;
3935 if (core == 0)
3936 tmp >>= 8;
3937 tmp &= 0xff;
3938
3939 for (i = 0; i < 18; i++) {
3940 scale = (ladder_lo[i].percent * tmp) / 100;
3941 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 3942 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 3943
3944 scale = (ladder_iq[i].percent * tmp) / 100;
3945 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 3946 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 3947 }
3948}
3949
45ca697e
RM		 3950/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3951static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3952{
3953 int i;
3954 for (i = 0; i < 15; i++)
3955 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3956 tbl_tx_filter_coef_rev4[2][i]);
3957}
3958
3959/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3960static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3961{
3962 int i, j;
3963 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 3964 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 3965
3966 for (i = 0; i < 3; i++)
3967 for (j = 0; j < 15; j++)
3968 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3969 tbl_tx_filter_coef_rev4[i][j]);
3970
3971 if (dev->phy.is_40mhz) {
3972 for (j = 0; j < 15; j++)
3973 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3974 tbl_tx_filter_coef_rev4[3][j]);
3975 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3976 for (j = 0; j < 15; j++)
3977 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3978 tbl_tx_filter_coef_rev4[5][j]);
3979 }
3980
3981 if (dev->phy.channel == 14)
3982 for (j = 0; j < 15; j++)
3983 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3984 tbl_tx_filter_coef_rev4[6][j]);
3985}
3986
b0022e15
RM		 3987/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3988static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3989{
3990 struct b43_phy_n *nphy = dev->phy.n;
3991
3992 u16 curr_gain[2];
3993 struct nphy_txgains target;
3994 const u32 *table = NULL;
3995
161d540c 3996 if (!nphy->txpwrctrl) {
b0022e15
RM		 3997 int i;
3998
3999 if (nphy->hang_avoid)
4000 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4001 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4002 if (nphy->hang_avoid)
4003 b43_nphy_stay_in_carrier_search(dev, false);
4004
4005 for (i = 0; i < 2; ++i) {
4006 if (dev->phy.rev >= 3) {
4007 target.ipa[i] = curr_gain[i] & 0x000F;
4008 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4009 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4010 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4011 } else {
4012 target.ipa[i] = curr_gain[i] & 0x0003;
4013 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4014 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4015 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4016 }
4017 }
4018 } else {
4019 int i;
4020 u16 index[2];
4021 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4022 B43_NPHY_TXPCTL_STAT_BIDX) >>
4023 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4024 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4025 B43_NPHY_TXPCTL_STAT_BIDX) >>
4026 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4027
4028 for (i = 0; i < 2; ++i) {
aeab5751 4029 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4030 if (dev->phy.rev >= 3) {
b0022e15
RM		 4031 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4032 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4033 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4034 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4035 } else {
b0022e15
RM		 4036 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4037 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4038 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4039 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4040 }
4041 }
4042 }
4043
4044 return target;
4045}
4046
e53de674
RM		 4047/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4048static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4049{
4050 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4051
4052 if (dev->phy.rev >= 3) {
4053 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4054 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4055 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4056 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4057 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4058 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4059 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4060 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4061 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4062 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4063 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4064 b43_nphy_reset_cca(dev);
4065 } else {
4066 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4067 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4068 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4069 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4070 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4071 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4072 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4073 }
4074}
4075
4076/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4077static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4078{
4079 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4080 u16 tmp;
4081
4082 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4083 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4084 if (dev->phy.rev >= 3) {
4085 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4086 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4087
4088 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4089 regs[2] = tmp;
4090 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4091
4092 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4093 regs[3] = tmp;
4094 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4095
4096 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4097 b43_phy_mask(dev, B43_NPHY_BBCFG,
4098 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4099
c643a66e 4100 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4101 regs[5] = tmp;
d41a3552 4102 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4103
4104 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4105 regs[6] = tmp;
d41a3552 4106 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4107 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4108 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4109
67cbc3ed
RM		 4110 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4111 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4112 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 4113
4114 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4115 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4116 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4117 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4118 } else {
4119 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4120 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4121 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4122 regs[2] = tmp;
4123 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4124 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4125 regs[3] = tmp;
4126 tmp |= 0x2000;
d41a3552 4127 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4128 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4129 regs[4] = tmp;
4130 tmp |= 0x2000;
d41a3552 4131 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4132 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4133 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4134 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4135 tmp = 0x0180;
4136 else
4137 tmp = 0x0120;
4138 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4139 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4140 }
4141}
4142
bbc6dc12
RM		 4143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4144static void b43_nphy_save_cal(struct b43_wldev *dev)
4145{
4146 struct b43_phy_n *nphy = dev->phy.n;
4147
4148 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4149 u16 *txcal_radio_regs = NULL;
902db91d 4150 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4151 u16 *table = NULL;
4152
4153 if (nphy->hang_avoid)
4154 b43_nphy_stay_in_carrier_search(dev, 1);
4155
4156 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4157 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4158 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4159 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4160 table = nphy->cal_cache.txcal_coeffs_2G;
4161 } else {
4162 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4163 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4164 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4165 table = nphy->cal_cache.txcal_coeffs_5G;
4166 }
4167
4168 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4169 /* TODO use some definitions */
4170 if (dev->phy.rev >= 3) {
4171 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4172 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4173 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4174 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4175 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4176 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4177 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4178 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4179 } else {
4180 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4181 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4182 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4183 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4184 }
204a665b
RM		 4185 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4186 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4187 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4188
4189 if (nphy->hang_avoid)
4190 b43_nphy_stay_in_carrier_search(dev, 0);
4191}
4192
2f258b74
RM		 4193/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4194static void b43_nphy_restore_cal(struct b43_wldev *dev)
4195{
4196 struct b43_phy_n *nphy = dev->phy.n;
4197
4198 u16 coef[4];
4199 u16 *loft = NULL;
4200 u16 *table = NULL;
4201
4202 int i;
4203 u16 *txcal_radio_regs = NULL;
4204 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4205
4206 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4207 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4208 return;
4209 table = nphy->cal_cache.txcal_coeffs_2G;
4210 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4211 } else {
204a665b 4212 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4213 return;
4214 table = nphy->cal_cache.txcal_coeffs_5G;
4215 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4216 }
4217
2581b143 4218 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4219
4220 for (i = 0; i < 4; i++) {
4221 if (dev->phy.rev >= 3)
4222 table[i] = coef[i];
4223 else
4224 coef[i] = 0;
4225 }
4226
2581b143
RM		 4227 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4228 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4229 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4230
4231 if (dev->phy.rev < 2)
4232 b43_nphy_tx_iq_workaround(dev);
4233
4234 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4235 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4236 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4237 } else {
4238 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4239 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4240 }
4241
4242 /* TODO use some definitions */
4243 if (dev->phy.rev >= 3) {
4244 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4245 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4246 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4247 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4248 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4249 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4250 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4251 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4252 } else {
4253 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4254 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4255 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4256 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4257 }
4258 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4259}
4260
fb43b8e2
RM		 4261/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4262static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4263 struct nphy_txgains target,
4264 bool full, bool mphase)
4265{
4266 struct b43_phy_n *nphy = dev->phy.n;
4267 int i;
4268 int error = 0;
4269 int freq;
4270 bool avoid = false;
4271 u8 length;
fb23d863 4272 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4273 const u16 *table;
4274 bool phy6or5x;
4275
4276 u16 buffer[11];
4277 u16 diq_start = 0;
4278 u16 save[2];
4279 u16 gain[2];
4280 struct nphy_iqcal_params params[2];
4281 bool updated[2] = { };
4282
4283 b43_nphy_stay_in_carrier_search(dev, true);
4284
4285 if (dev->phy.rev >= 4) {
4286 avoid = nphy->hang_avoid;
3db1cd5c 4287 nphy->hang_avoid = false;
fb43b8e2
RM		 4288 }
4289
9145834e 4290 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4291
4292 for (i = 0; i < 2; i++) {
4293 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4294 gain[i] = params[i].cal_gain;
4295 }
2581b143
RM		 4296
4297 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4298
4299 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4300 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4301
4302 phy6or5x = dev->phy.rev >= 6 ||
4303 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4304 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4305 if (phy6or5x) {
38bb9029
RM		 4306 if (dev->phy.is_40mhz) {
4307 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4308 tbl_tx_iqlo_cal_loft_ladder_40);
4309 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4310 tbl_tx_iqlo_cal_iqimb_ladder_40);
4311 } else {
4312 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4313 tbl_tx_iqlo_cal_loft_ladder_20);
4314 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4315 tbl_tx_iqlo_cal_iqimb_ladder_20);
4316 }
fb43b8e2
RM		 4317 }
4318
4319 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4320
aa4c7b2a 4321 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4322 freq = 2500;
4323 else
4324 freq = 5000;
4325
4326 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4327 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4328 0xFFFF, 0, true, false);
fb43b8e2 4329 else
59af099b 4330 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4331
4332 if (error == 0) {
4333 if (nphy->mphase_cal_phase_id > 2) {
4334 table = nphy->mphase_txcal_bestcoeffs;
4335 length = 11;
4336 if (dev->phy.rev < 3)
4337 length -= 2;
4338 } else {
4339 if (!full && nphy->txiqlocal_coeffsvalid) {
4340 table = nphy->txiqlocal_bestc;
4341 length = 11;
4342 if (dev->phy.rev < 3)
4343 length -= 2;
4344 } else {
4345 full = true;
4346 if (dev->phy.rev >= 3) {
4347 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4348 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4349 } else {
4350 table = tbl_tx_iqlo_cal_startcoefs;
4351 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4352 }
4353 }
4354 }
4355
2581b143 4356 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4357
4358 if (full) {
4359 if (dev->phy.rev >= 3)
4360 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4361 else
4362 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4363 } else {
4364 if (dev->phy.rev >= 3)
4365 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4366 else
4367 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4368 }
4369
4370 if (mphase) {
4371 count = nphy->mphase_txcal_cmdidx;
4372 numb = min(max,
4373 (u16)(count + nphy->mphase_txcal_numcmds));
4374 } else {
4375 count = 0;
4376 numb = max;
4377 }
4378
4379 for (; count < numb; count++) {
4380 if (full) {
4381 if (dev->phy.rev >= 3)
4382 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4383 else
4384 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4385 } else {
4386 if (dev->phy.rev >= 3)
4387 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4388 else
4389 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4390 }
4391
4392 core = (cmd & 0x3000) >> 12;
4393 type = (cmd & 0x0F00) >> 8;
4394
4395 if (phy6or5x && updated[core] == 0) {
4396 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4397 updated[core] = true;
fb43b8e2
RM		 4398 }
4399
4400 tmp = (params[core].ncorr[type] << 8) | 0x66;
4401 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4402
4403 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4404 buffer[0] = b43_ntab_read(dev,
4405 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4406 diq_start = buffer[0];
4407 buffer[0] = 0;
d41a3552
RM		 4408 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4409 0);
fb43b8e2
RM		 4410 }
4411
4412 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4413 for (i = 0; i < 2000; i++) {
4414 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4415 if (tmp & 0xC000)
4416 break;
4417 udelay(10);
4418 }
4419
9145834e
RM		 4420 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4421 buffer);
2581b143
RM		 4422 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4423 buffer);
fb43b8e2
RM		 4424
4425 if (type == 1 || type == 3 || type == 4)
4426 buffer[0] = diq_start;
4427 }
4428
4429 if (mphase)
4430 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4431
4432 last = (dev->phy.rev < 3) ? 6 : 7;
4433
4434 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4435 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4436 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4437 if (dev->phy.rev < 3) {
4438 buffer[0] = 0;
4439 buffer[1] = 0;
4440 buffer[2] = 0;
4441 buffer[3] = 0;
4442 }
2581b143
RM		 4443 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4444 buffer);
bc53e512 4445 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4446 buffer);
4447 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4448 buffer);
4449 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4450 buffer);
fb43b8e2
RM		 4451 length = 11;
4452 if (dev->phy.rev < 3)
4453 length -= 2;
9145834e
RM		 4454 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4455 nphy->txiqlocal_bestc);
fb43b8e2 4456 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4457 nphy->txiqlocal_chanspec.center_freq =
4458 dev->phy.channel_freq;
4459 nphy->txiqlocal_chanspec.channel_type =
4460 dev->phy.channel_type;
fb43b8e2
RM		 4461 } else {
4462 length = 11;
4463 if (dev->phy.rev < 3)
4464 length -= 2;
9145834e
RM		 4465 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4466 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4467 }
4468
53ae8e8c 4469 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4470 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4471 }
4472
e53de674 4473 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4474 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4475
4476 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4477 b43_nphy_tx_iq_workaround(dev);
4478
4479 if (dev->phy.rev >= 4)
4480 nphy->hang_avoid = avoid;
4481
4482 b43_nphy_stay_in_carrier_search(dev, false);
4483
4484 return error;
4485}
4486
984ff4ff
RM		 4487/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4488static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4489{
4490 struct b43_phy_n *nphy = dev->phy.n;
4491 u8 i;
4492 u16 buffer[7];
4493 bool equal = true;
4494
902db91d 4495 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4496 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4497 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4498 return;
4499
4500 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4501 for (i = 0; i < 4; i++) {
4502 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4503 equal = false;
4504 break;
4505 }
4506 }
4507
4508 if (!equal) {
4509 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4510 nphy->txiqlocal_bestc);
4511 for (i = 0; i < 4; i++)
4512 buffer[i] = 0;
4513 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4514 buffer);
4515 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4516 &nphy->txiqlocal_bestc[5]);
4517 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4518 &nphy->txiqlocal_bestc[5]);
4519 }
4520}
4521
15931e31
RM		 4522/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4523static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4524 struct nphy_txgains target, u8 type, bool debug)
4525{
4526 struct b43_phy_n *nphy = dev->phy.n;
4527 int i, j, index;
4528 u8 rfctl[2];
4529 u8 afectl_core;
4530 u16 tmp[6];
c7455cf9 4531 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4532 u32 real, imag;
4533 enum ieee80211_band band;
4534
4535 u8 use;
4536 u16 cur_hpf;
4537 u16 lna[3] = { 3, 3, 1 };
4538 u16 hpf1[3] = { 7, 2, 0 };
4539 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4540 u32 power[3] = { };
15931e31
RM		 4541 u16 gain_save[2];
4542 u16 cal_gain[2];
4543 struct nphy_iqcal_params cal_params[2];
4544 struct nphy_iq_est est;
4545 int ret = 0;
4546 bool playtone = true;
4547 int desired = 13;
4548
4549 b43_nphy_stay_in_carrier_search(dev, 1);
4550
4551 if (dev->phy.rev < 2)
984ff4ff 4552 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4553 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4554 for (i = 0; i < 2; i++) {
4555 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4556 cal_gain[i] = cal_params[i].cal_gain;
4557 }
2581b143 4558 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4559
4560 for (i = 0; i < 2; i++) {
4561 if (i == 0) {
4562 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4563 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4564 afectl_core = B43_NPHY_AFECTL_C1;
4565 } else {
4566 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4567 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4568 afectl_core = B43_NPHY_AFECTL_C2;
4569 }
4570
4571 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4572 tmp[2] = b43_phy_read(dev, afectl_core);
4573 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4574 tmp[4] = b43_phy_read(dev, rfctl[0]);
4575 tmp[5] = b43_phy_read(dev, rfctl[1]);
4576
4577 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4578 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4579 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4580 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4581 (1 - i));
4582 b43_phy_set(dev, afectl_core, 0x0006);
4583 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4584
4585 band = b43_current_band(dev->wl);
4586
4587 if (nphy->rxcalparams & 0xFF000000) {
4588 if (band == IEEE80211_BAND_5GHZ)
4589 b43_phy_write(dev, rfctl[0], 0x140);
4590 else
4591 b43_phy_write(dev, rfctl[0], 0x110);
4592 } else {
4593 if (band == IEEE80211_BAND_5GHZ)
4594 b43_phy_write(dev, rfctl[0], 0x180);
4595 else
4596 b43_phy_write(dev, rfctl[0], 0x120);
4597 }
4598
4599 if (band == IEEE80211_BAND_5GHZ)
4600 b43_phy_write(dev, rfctl[1], 0x148);
4601 else
4602 b43_phy_write(dev, rfctl[1], 0x114);
4603
4604 if (nphy->rxcalparams & 0x10000) {
4605 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4606 (i + 1));
4607 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4608 (2 - i));
4609 }
4610
30115c22 4611 for (j = 0; j < 4; j++) {
15931e31
RM		 4612 if (j < 3) {
4613 cur_lna = lna[j];
4614 cur_hpf1 = hpf1[j];
4615 cur_hpf2 = hpf2[j];
4616 } else {
4617 if (power[1] > 10000) {
4618 use = 1;
4619 cur_hpf = cur_hpf1;
4620 index = 2;
4621 } else {
4622 if (power[0] > 10000) {
4623 use = 1;
4624 cur_hpf = cur_hpf1;
4625 index = 1;
4626 } else {
4627 index = 0;
4628 use = 2;
4629 cur_hpf = cur_hpf2;
4630 }
4631 }
4632 cur_lna = lna[index];
4633 cur_hpf1 = hpf1[index];
4634 cur_hpf2 = hpf2[index];
4635 cur_hpf += desired - hweight32(power[index]);
4636 cur_hpf = clamp_val(cur_hpf, 0, 10);
4637 if (use == 1)
4638 cur_hpf1 = cur_hpf;
4639 else
4640 cur_hpf2 = cur_hpf;
4641 }
4642
4643 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4644 (cur_lna << 2));
75377b24
RM		 4645 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4646 false);
de9a47f9 4647 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4648 b43_nphy_stop_playback(dev);
15931e31
RM		 4649
4650 if (playtone) {
59af099b
RM		 4651 ret = b43_nphy_tx_tone(dev, 4000,
4652 (nphy->rxcalparams & 0xFFFF),
4653 false, false);
15931e31
RM		 4654 playtone = false;
4655 } else {
10a79873
RM		 4656 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4657 false, false);
15931e31
RM		 4658 }
4659
4660 if (ret == 0) {
4661 if (j < 3) {
4662 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4663 false);
4664 if (i == 0) {
4665 real = est.i0_pwr;
4666 imag = est.q0_pwr;
4667 } else {
4668 real = est.i1_pwr;
4669 imag = est.q1_pwr;
4670 }
4671 power[i] = ((real + imag) / 1024) + 1;
4672 } else {
4673 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4674 }
53ae8e8c 4675 b43_nphy_stop_playback(dev);
15931e31
RM		 4676 }
4677
4678 if (ret != 0)
4679 break;
4680 }
4681
4682 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4683 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4684 b43_phy_write(dev, rfctl[1], tmp[5]);
4685 b43_phy_write(dev, rfctl[0], tmp[4]);
4686 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4687 b43_phy_write(dev, afectl_core, tmp[2]);
4688 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4689
4690 if (ret != 0)
4691 break;
4692 }
4693
75377b24 4694 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 4695 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 4696 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4697
4698 b43_nphy_stay_in_carrier_search(dev, 0);
4699
4700 return ret;
4701}
4702
4703static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4704 struct nphy_txgains target, u8 type, bool debug)
4705{
4706 return -1;
4707}
4708
4709/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4710static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4711 struct nphy_txgains target, u8 type, bool debug)
4712{
4713 if (dev->phy.rev >= 3)
4714 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4715 else
4716 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4717}
4718
4e687b22
GS		 4719/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4720static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4721{
4722 struct b43_phy *phy = &dev->phy;
4723 struct b43_phy_n *nphy = phy->n;
0b81c23d 4724 /* u16 buf[16]; it's rev3+ */
4e687b22 4725
049fbfee
RM		 4726 nphy->phyrxchain = mask;
4727
4e687b22
GS		 4728 if (0 /* FIXME clk */)
4729 return;
4730
4731 b43_mac_suspend(dev);
4732
4733 if (nphy->hang_avoid)
4734 b43_nphy_stay_in_carrier_search(dev, true);
4735
4736 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4737 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4738
049fbfee 4739 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 4740 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4741 if (dev->phy.rev >= 3) {
4742 /* TODO */
4743 }
4744 } else {
4745 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4746 if (dev->phy.rev >= 3) {
4747 /* TODO */
4748 }
4749 }
4750
4751 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4752
4753 if (nphy->hang_avoid)
4754 b43_nphy_stay_in_carrier_search(dev, false);
4755
4756 b43_mac_enable(dev);
4757}
4758
104cfa88
RM		 4759/**************************************************
4760 * N-PHY init
4761 **************************************************/
4762
0988a7a1 4763/*
104cfa88
RM		 4764 * Upload the N-PHY tables.
4765 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
0988a7a1 4766 */
104cfa88
RM		 4767static void b43_nphy_tables_init(struct b43_wldev *dev)
4768{
4769 if (dev->phy.rev < 3)
4770 b43_nphy_rev0_1_2_tables_init(dev);
4771 else
4772 b43_nphy_rev3plus_tables_init(dev);
4773}
4774
4775/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4776static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4777{
4778 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4779
4780 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4781 if (preamble == 1)
4782 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4783 else
4784 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4785
4786 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4787}
4788
4789/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4790static void b43_nphy_bphy_init(struct b43_wldev *dev)
4791{
4792 unsigned int i;
4793 u16 val;
4794
4795 val = 0x1E1F;
4796 for (i = 0; i < 16; i++) {
4797 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4798 val -= 0x202;
4799 }
4800 val = 0x3E3F;
4801 for (i = 0; i < 16; i++) {
4802 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4803 val -= 0x202;
4804 }
4805 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4806}
4807
4808/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4809static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4810{
4811 if (dev->phy.rev >= 3) {
4812 if (!init)
4813 return;
4814 if (0 /* FIXME */) {
4815 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4816 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4817 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4818 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4819 }
4820 } else {
4821 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4822 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4823
4824 switch (dev->dev->bus_type) {
4825#ifdef CONFIG_B43_BCMA
4826 case B43_BUS_BCMA:
4827 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4828 0xFC00, 0xFC00);
4829 break;
4830#endif
4831#ifdef CONFIG_B43_SSB
4832 case B43_BUS_SSB:
4833 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4834 0xFC00, 0xFC00);
4835 break;
4836#endif
4837 }
4838
5056635c
RM		 4839 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4840 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4841 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4842 0);
104cfa88
RM		 4843
4844 if (init) {
4845 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4846 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4847 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4848 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4849 }
4850 }
4851}
4852
4853/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
424047e6
MB		 4854int b43_phy_initn(struct b43_wldev *dev)
4855{
0581483a 4856 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 4857 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 4858 struct b43_phy_n *nphy = phy->n;
4859 u8 tx_pwr_state;
4860 struct nphy_txgains target;
95b66bad 4861 u16 tmp;
0988a7a1
RM		 4862 enum ieee80211_band tmp2;
4863 bool do_rssi_cal;
4864
4865 u16 clip[2];
4866 bool do_cal = false;
95b66bad 4867
0988a7a1 4868 if ((dev->phy.rev >= 3) &&
0581483a 4869 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 4870 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 4871 switch (dev->dev->bus_type) {
42c9a458
RM		 4872#ifdef CONFIG_B43_BCMA
4873 case B43_BUS_BCMA:
4874 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4875 BCMA_CC_CHIPCTL, 0x40);
4876 break;
4877#endif
6cbab0d9
RM		 4878#ifdef CONFIG_B43_SSB
4879 case B43_BUS_SSB:
4880 chipco_set32(&dev->dev->sdev->bus->chipco,
4881 SSB_CHIPCO_CHIPCTL, 0x40);
4882 break;
4883#endif
4884 }
0988a7a1
RM		 4885 }
4886 nphy->deaf_count = 0;
95b66bad 4887 b43_nphy_tables_init(dev);
0988a7a1
RM		 4888 nphy->crsminpwr_adjusted = false;
4889 nphy->noisevars_adjusted = false;
95b66bad
MB		 4890
4891 /* Clear all overrides */
0988a7a1
RM		 4892 if (dev->phy.rev >= 3) {
4893 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4894 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4895 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4896 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4897 } else {
4898 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4899 }
95b66bad
MB		 4900 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4901 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 4902 if (dev->phy.rev < 6) {
4903 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4904 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4905 }
95b66bad
MB		 4906 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4907 ~(B43_NPHY_RFSEQMODE_CAOVER |
4908 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 4909 if (dev->phy.rev >= 3)
4910 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 4911 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4912
0988a7a1
RM		 4913 if (dev->phy.rev <= 2) {
4914 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4915 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4916 ~B43_NPHY_BPHY_CTL3_SCALE,
4917 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4918 }
95b66bad
MB		 4919 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4920 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4921
0eff8fcd 4922 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f
RM		 4923 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4924 dev->dev->board_type == 0x8B))
0988a7a1
RM		 4925 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4926 else
4927 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4928 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4929 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4930 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 4931
ad9716e8 4932 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 4933 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 4934
4935 if (phy->rev < 2) {
4936 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4937 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4938 }
0988a7a1
RM		 4939
4940 tmp2 = b43_current_band(dev->wl);
c002831a 4941 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 4942 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4943 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4944 nphy->papd_epsilon_offset[0] << 7);
4945 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
4946 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
4947 nphy->papd_epsilon_offset[1] << 7);
45ca697e 4948 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 4949 } else if (phy->rev >= 5) {
45ca697e 4950 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 4951 }
4952
95b66bad 4953 b43_nphy_workarounds(dev);
95b66bad 4954
0988a7a1 4955 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 4956 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 4957 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
4958 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
4959 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 4960 b43_phy_force_clock(dev, 0);
0988a7a1 4961
858a1652 4962 b43_mac_phy_clock_set(dev, true);
0988a7a1 4963
e50cbcf6 4964 b43_nphy_pa_override(dev, false);
95b66bad
MB		 4965 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4966 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 4967 b43_nphy_pa_override(dev, true);
0988a7a1 4968
bbec398c
RM		 4969 b43_nphy_classifier(dev, 0, 0);
4970 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 4971 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4972 b43_nphy_bphy_init(dev);
4973
0988a7a1 4974 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 4975 b43_nphy_tx_power_ctrl(dev, false);
4976 b43_nphy_tx_power_fix(dev);
3dda07b6 4977 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 4978 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 4979 b43_nphy_tx_gain_table_upload(dev);
95b66bad 4980
0988a7a1 4981 if (nphy->phyrxchain != 3)
4e687b22 4982 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 4983 if (nphy->mphase_cal_phase_id > 0)
4984 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
4985
4986 do_rssi_cal = false;
4987 if (phy->rev >= 3) {
4988 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 4989 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 4990 else
204a665b 4991 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 4992
4993 if (do_rssi_cal)
4cb99775 4994 b43_nphy_rssi_cal(dev);
0988a7a1 4995 else
42e1547e 4996 b43_nphy_restore_rssi_cal(dev);
0988a7a1 4997 } else {
4cb99775 4998 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 4999 }
5000
5001 if (!((nphy->measure_hold & 0x6) != 0)) {
5002 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5003 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5004 else
204a665b 5005 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5006
5007 if (nphy->mute)
5008 do_cal = false;
5009
5010 if (do_cal) {
b0022e15 5011 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5012
5013 if (nphy->antsel_type == 2)
8987a9e9 5014 b43_nphy_superswitch_init(dev, true);
0988a7a1 5015 if (nphy->perical != 2) {
90b9738d 5016 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5017 if (phy->rev >= 3) {
5018 nphy->cal_orig_pwr_idx[0] =
5019 nphy->txpwrindex[0].index_internal;
5020 nphy->cal_orig_pwr_idx[1] =
5021 nphy->txpwrindex[1].index_internal;
5022 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5023 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5024 }
e7797bf2
RM		 5025 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5026 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5027 b43_nphy_save_cal(dev);
5028 } else if (nphy->mphase_cal_phase_id == 0)
5029 ;/* N PHY Periodic Calibration with arg 3 */
5030 } else {
5031 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5032 }
5033 }
5034
6dcd9d91 5035 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5036 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5037 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5038 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5039 if (phy->rev >= 3 && phy->rev <= 6)
5040 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 5041 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5042 if (phy->rev >= 3)
5043 b43_nphy_spur_workaround(dev);
95b66bad 5044
53a6e234 5045 return 0;
424047e6 5046}
ef1a628d 5047
104cfa88
RM		 5048/**************************************************
5049 * Channel switching ops.
5050 **************************************************/
5051
5052static void b43_chantab_phy_upload(struct b43_wldev *dev,
5053 const struct b43_phy_n_sfo_cfg *e)
5054{
5055 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5056 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5057 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5058 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5059 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5060 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5061}
5062
49d55cef
RM		 5063/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5064static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5065{
9b682c78
JL		 5066 struct bcma_drv_cc __maybe_unused *cc;
5067 u32 __maybe_unused pmu_ctl;
d66be829
RM		 5068
5069 switch (dev->dev->bus_type) {
5070#ifdef CONFIG_B43_BCMA
5071 case B43_BUS_BCMA:
5072 cc = &dev->dev->bdev->bus->drv_cc;
5073 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
5074 if (avoid) {
5075 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
5076 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
5077 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
5078 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5079 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
5080 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5081 } else {
5082 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
5083 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
5084 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
5085 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5086 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5087 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5088 }
5089 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
5090 } else if (dev->dev->chip_id == 0x4716) {
5091 if (avoid) {
5092 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
5093 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
5094 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
5095 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5096 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
5097 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5098 } else {
5099 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
5100 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
5101 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
5102 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5103 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5104 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5105 }
5106 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
5107 BCMA_CC_PMU_CTL_NOILPONW;
5108 } else if (dev->dev->chip_id == 0x4322 ||
5109 dev->dev->chip_id == 0x4340 ||
5110 dev->dev->chip_id == 0x4341) {
5111 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
5112 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
5113 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
5114 if (avoid)
5115 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
5116 else
5117 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
5118 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
49d55cef 5119 } else {
d66be829 5120 return;
49d55cef 5121 }
d66be829
RM		 5122 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
5123 break;
8b1fdb53 5124#endif
d66be829
RM		 5125#ifdef CONFIG_B43_SSB
5126 case B43_BUS_SSB:
5127 /* FIXME */
5128 break;
5129#endif
5130 }
49d55cef
RM		 5131}
5132
1b69ec7b 5133/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5134static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5135 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5136 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5137{
5138 struct b43_phy *phy = &dev->phy;
5139 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5140 int ch = new_channel->hw_value;
1b69ec7b 5141
087de74a 5142 u16 old_band_5ghz;
1b69ec7b
RM		 5143 u32 tmp32;
5144
087de74a
RM		 5145 old_band_5ghz =
5146 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5147 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 5148 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5149 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5150 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5151 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5152 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5153 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 5154 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5155 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5156 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 5157 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 5158 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5159 }
5160
5161 b43_chantab_phy_upload(dev, e);
5162
a656b6a9 5163 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5164 b43_nphy_classifier(dev, 2, 0);
5165 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5166 } else {
5167 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5168 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5169 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5170 }
5171
161d540c 5172 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5173 b43_nphy_tx_power_fix(dev);
5174
5175 if (dev->phy.rev < 3)
5176 b43_nphy_adjust_lna_gain_table(dev);
5177
5178 b43_nphy_tx_lp_fbw(dev);
5179
49d55cef
RM		 5180 if (dev->phy.rev >= 3 &&
5181 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5182 bool avoid = false;
5183 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5184 avoid = true;
5185 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5186 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5187 avoid = true;
5188 } else { /* 40MHz */
5189 if (nphy->aband_spurwar_en &&
5190 (ch == 38 || ch == 102 || ch == 118))
5191 avoid = dev->dev->chip_id == 0x4716;
5192 }
5193
5194 b43_nphy_pmu_spur_avoid(dev, avoid);
5195
5196 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5197 dev->dev->chip_id == 43225) {
5198 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5199 avoid ? 0x5341 : 0x8889);
5200 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5201 }
5202
5203 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5204 ; /* TODO: reset PLL */
5205
5206 if (avoid)
5207 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5208 else
5209 b43_phy_mask(dev, B43_NPHY_BBCFG,
5210 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5211
5212 b43_nphy_reset_cca(dev);
5213
5214 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5215 }
5216
5217 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5218
5219 if (phy->rev >= 3)
5220 b43_nphy_spur_workaround(dev);
5221}
5222
eff66c51 5223/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5224static int b43_nphy_set_channel(struct b43_wldev *dev,
5225 struct ieee80211_channel *channel,
5226 enum nl80211_channel_type channel_type)
eff66c51 5227{
a656b6a9 5228 struct b43_phy *phy = &dev->phy;
eff66c51 5229
2eeb6fd0
JL		 5230 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5231 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5232
5233 u8 tmp;
eff66c51
RM		 5234
5235 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5236 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5237 channel->center_freq);
f19ebe7d
RM		 5238 if (!tabent_r3)
5239 return -ESRCH;
ffd2d9bd 5240 } else {
a656b6a9
RM		 5241 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5242 channel->hw_value);
f19ebe7d 5243 if (!tabent_r2)
ffd2d9bd 5244 return -ESRCH;
eff66c51
RM		 5245 }
5246
204a665b
RM		 5247 /* Channel is set later in common code, but we need to set it on our
5248 own to let this function's subcalls work properly. */
5249 phy->channel = channel->hw_value;
5250 phy->channel_freq = channel->center_freq;
eff66c51 5251
e5c407f9
RM		 5252 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5253 b43_channel_type_is_40mhz(channel_type))
5254 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5255
a656b6a9
RM		 5256 if (channel_type == NL80211_CHAN_HT40PLUS)
5257 b43_phy_set(dev, B43_NPHY_RXCTL,
5258 B43_NPHY_RXCTL_BSELU20);
5259 else if (channel_type == NL80211_CHAN_HT40MINUS)
5260 b43_phy_mask(dev, B43_NPHY_RXCTL,
5261 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5262
5263 if (dev->phy.rev >= 3) {
a656b6a9 5264 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5265 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5266 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5267 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5268 } else {
a656b6a9 5269 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5270 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5271 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5272 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5273 }
5274
5275 return 0;
5276}
5277
104cfa88
RM		 5278/**************************************************
5279 * Basic PHY ops.
5280 **************************************************/
5281
ef1a628d
MB		 5282static int b43_nphy_op_allocate(struct b43_wldev *dev)
5283{
5284 struct b43_phy_n *nphy;
5285
5286 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5287 if (!nphy)
5288 return -ENOMEM;
5289 dev->phy.n = nphy;
5290
ef1a628d
MB		 5291 return 0;
5292}
5293
fb11137a 5294static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5295{
fb11137a
MB		 5296 struct b43_phy *phy = &dev->phy;
5297 struct b43_phy_n *nphy = phy->n;
c7d64310 5298 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5299
fb11137a 5300 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5301
aca434d3 5302 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5303 nphy->spur_avoid = (phy->rev >= 3) ?
5304 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5305 nphy->init_por = true;
0b81c23d
RM		 5306 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5307 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5308 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5309 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5310 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5311 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5312 nphy->tx_pwr_idx[0] = 128;
5313 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5314
5315 /* Hardware TX power control and 5GHz power gain */
5316 nphy->txpwrctrl = false;
5317 nphy->pwg_gain_5ghz = false;
5318 if (dev->phy.rev >= 3 ||
5319 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5320 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5321 nphy->txpwrctrl = true;
5322 nphy->pwg_gain_5ghz = true;
5323 } else if (sprom->revision >= 4) {
5324 if (dev->phy.rev >= 2 &&
5325 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5326 nphy->txpwrctrl = true;
5327#ifdef CONFIG_B43_SSB
5328 if (dev->dev->bus_type == B43_BUS_SSB &&
5329 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5330 struct pci_dev *pdev =
5331 dev->dev->sdev->bus->host_pci;
5332 if (pdev->device == 0x4328 ||
5333 pdev->device == 0x432a)
5334 nphy->pwg_gain_5ghz = true;
5335 }
5336#endif
5337 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5338 nphy->pwg_gain_5ghz = true;
5339 }
5340 }
5341
5342 if (dev->phy.rev >= 3) {
5343 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5344 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5345 }
572d37a4
RM		 5346
5347 nphy->init_por = true;
ef1a628d
MB		 5348}
5349
fb11137a 5350static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5351{
fb11137a
MB		 5352 struct b43_phy *phy = &dev->phy;
5353 struct b43_phy_n *nphy = phy->n;
ef1a628d 5354
ef1a628d 5355 kfree(nphy);
fb11137a
MB		 5356 phy->n = NULL;
5357}
5358
5359static int b43_nphy_op_init(struct b43_wldev *dev)
5360{
5361 return b43_phy_initn(dev);
ef1a628d
MB		 5362}
5363
5364static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5365{
5366#if B43_DEBUG
5367 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5368 /* OFDM registers are onnly available on A/G-PHYs */
5369 b43err(dev->wl, "Invalid OFDM PHY access at "
5370 "0x%04X on N-PHY\n", offset);
5371 dump_stack();
5372 }
5373 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5374 /* Ext-G registers are only available on G-PHYs */
5375 b43err(dev->wl, "Invalid EXT-G PHY access at "
5376 "0x%04X on N-PHY\n", offset);
5377 dump_stack();
5378 }
5379#endif /* B43_DEBUG */
5380}
5381
5382static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5383{
5384 check_phyreg(dev, reg);
5385 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5386 return b43_read16(dev, B43_MMIO_PHY_DATA);
5387}
5388
5389static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5390{
5391 check_phyreg(dev, reg);
5392 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5393 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5394}
5395
755fd183
RM		 5396static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5397 u16 set)
5398{
5399 check_phyreg(dev, reg);
5400 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5401 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5402}
5403
ef1a628d
MB		 5404static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5405{
5406 /* Register 1 is a 32-bit register. */
5407 B43_WARN_ON(reg == 1);
5408 /* N-PHY needs 0x100 for read access */
5409 reg |= 0x100;
5410
5411 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5412 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5413}
5414
5415static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5416{
5417 /* Register 1 is a 32-bit register. */
5418 B43_WARN_ON(reg == 1);
5419
5420 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5421 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5422}
5423
c2b7aefd 5424/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5425static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5426 bool blocked)
c2b7aefd
RM		 5427{
5428 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5429 b43err(dev->wl, "MAC not suspended\n");
5430
5431 if (blocked) {
5432 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5433 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5434 if (dev->phy.rev >= 7) {
5435 /* TODO */
5436 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5437 b43_radio_mask(dev, 0x09, ~0x2);
5438
5439 b43_radio_write(dev, 0x204D, 0);
5440 b43_radio_write(dev, 0x2053, 0);
5441 b43_radio_write(dev, 0x2058, 0);
5442 b43_radio_write(dev, 0x205E, 0);
5443 b43_radio_mask(dev, 0x2062, ~0xF0);
5444 b43_radio_write(dev, 0x2064, 0);
5445
5446 b43_radio_write(dev, 0x304D, 0);
5447 b43_radio_write(dev, 0x3053, 0);
5448 b43_radio_write(dev, 0x3058, 0);
5449 b43_radio_write(dev, 0x305E, 0);
5450 b43_radio_mask(dev, 0x3062, ~0xF0);
5451 b43_radio_write(dev, 0x3064, 0);
5452 }
5453 } else {
572d37a4
RM		 5454 if (dev->phy.rev >= 7) {
5455 b43_radio_2057_init(dev);
5456 b43_switch_channel(dev, dev->phy.channel);
5457 } else if (dev->phy.rev >= 3) {
d817f4e1 5458 b43_radio_init2056(dev);
78159788 5459 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5460 } else {
5461 b43_radio_init2055(dev);
5462 }
5463 }
ef1a628d
MB		 5464}
5465
0f4091b9 5466/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5467static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5468{
2a870831
RM		 5469 u16 override = on ? 0x0 : 0x7FFF;
5470 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5471
2a870831
RM		 5472 if (dev->phy.rev >= 3) {
5473 if (on) {
5474 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5475 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5476 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5477 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5478 } else {
5479 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5480 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5481 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5482 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5483 }
5484 } else {
5485 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5486 }
cb24f57f
MB		 5487}
5488
ef1a628d
MB		 5489static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5490 unsigned int new_channel)
5491{
a656b6a9
RM		 5492 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
5493 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 5494
ef1a628d
MB		 5495 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5496 if ((new_channel < 1) || (new_channel > 14))
5497 return -EINVAL;
5498 } else {
5499 if (new_channel > 200)
5500 return -EINVAL;
5501 }
5502
a656b6a9 5503 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5504}
5505
5506static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5507{
5508 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5509 return 1;
5510 return 36;
5511}
5512
ef1a628d
MB		 5513const struct b43_phy_operations b43_phyops_n = {
5514 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5515 .free = b43_nphy_op_free,
5516 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5517 .init = b43_nphy_op_init,
ef1a628d
MB		 5518 .phy_read = b43_nphy_op_read,
5519 .phy_write = b43_nphy_op_write,
755fd183 5520 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5521 .radio_read = b43_nphy_op_radio_read,
5522 .radio_write = b43_nphy_op_radio_write,
5523 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5524 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5525 .switch_channel = b43_nphy_op_switch_channel,
5526 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5527 .recalc_txpower = b43_nphy_op_recalc_txpower,
5528 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5529};
Linux kernel - Deliverables
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