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b43: N-PHY: add placeholders for new devices support
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
303415e2
RM		 143static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field,
144 u16 value, u8 core, bool off,
145 u8 override_id)
146{
147 /* TODO */
148}
149
c071b9f6 150/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 151static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
152 u16 value, u8 core, bool off,
153 u8 override)
c071b9f6 154{
303415e2 155 struct b43_phy *phy = &dev->phy;
c071b9f6
RM		 156 const struct nphy_rf_control_override_rev7 *e;
157 u16 en_addrs[3][2] = {
158 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
159 };
160 u16 en_addr;
161 u16 en_mask = field;
162 u16 val_addr;
163 u8 i;
164
303415e2
RM		 165 if (phy->rev >= 19 || phy->rev < 3) {
166 B43_WARN_ON(1);
167 return;
168 }
169
c071b9f6
RM		 170 /* Remember: we can get NULL! */
171 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
172
173 for (i = 0; i < 2; i++) {
174 if (override >= ARRAY_SIZE(en_addrs)) {
175 b43err(dev->wl, "Invalid override value %d\n", override);
176 return;
177 }
178 en_addr = en_addrs[override][i];
179
8ce9beac
FP		 180 if (e)
181 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 182
183 if (off) {
184 b43_phy_mask(dev, en_addr, ~en_mask);
185 if (e) /* Do it safer, better than wl */
186 b43_phy_mask(dev, val_addr, ~e->val_mask);
187 } else {
188 if (!core || (core & (1 << i))) {
189 b43_phy_set(dev, en_addr, en_mask);
190 if (e)
191 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
192 }
193 }
194 }
195}
196
ab499217 197/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 198static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
199 u16 value, u8 core, bool off)
ab499217
RM		 200{
201 int i;
202 u8 index = fls(field);
203 u8 addr, en_addr, val_addr;
204 /* we expect only one bit set */
205 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 206
ab499217
RM		 207 if (dev->phy.rev >= 3) {
208 const struct nphy_rf_control_override_rev3 *rf_ctrl;
209 for (i = 0; i < 2; i++) {
210 if (index == 0 || index == 16) {
211 b43err(dev->wl,
212 "Unsupported RF Ctrl Override call\n");
213 return;
214 }
e5255ccc 215
ab499217
RM		 216 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
217 en_addr = B43_PHY_N((i == 0) ?
218 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
219 val_addr = B43_PHY_N((i == 0) ?
220 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 221
ab499217
RM		 222 if (off) {
223 b43_phy_mask(dev, en_addr, ~(field));
224 b43_phy_mask(dev, val_addr,
225 ~(rf_ctrl->val_mask));
226 } else {
b97c0718 227 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 228 b43_phy_set(dev, en_addr, field);
229 b43_phy_maskset(dev, val_addr,
230 ~(rf_ctrl->val_mask),
231 (value << rf_ctrl->val_shift));
232 }
233 }
234 }
235 } else {
236 const struct nphy_rf_control_override_rev2 *rf_ctrl;
237 if (off) {
238 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
239 value = 0;
240 } else {
241 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
242 }
d4814e69 243
ab499217
RM		 244 for (i = 0; i < 2; i++) {
245 if (index <= 1 || index == 16) {
246 b43err(dev->wl,
247 "Unsupported RF Ctrl Override call\n");
248 return;
249 }
d4814e69 250
ab499217
RM		 251 if (index == 2 || index == 10 ||
252 (index >= 13 && index <= 15)) {
253 core = 1;
254 }
d4814e69 255
ab499217
RM		 256 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
257 addr = B43_PHY_N((i == 0) ?
258 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 259
b97c0718 260 if ((1 << i) & core)
ab499217
RM		 261 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
262 (value << rf_ctrl->shift));
263
264 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
265 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
266 B43_NPHY_RFCTL_CMD_START);
267 udelay(1);
268 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
269 }
270 }
d4814e69
RM		 271}
272
4256ba77
RM		 273static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
274 enum n_intc_override intc_override,
275 u16 value, u8 core_sel)
276{
277 u16 reg, tmp, tmp2, val;
278 int core;
279
303415e2
RM		 280 /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */
281
4256ba77
RM		 282 for (core = 0; core < 2; core++) {
283 if ((core_sel == 1 && core != 0) ||
284 (core_sel == 2 && core != 1))
285 continue;
286
287 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
288
289 switch (intc_override) {
290 case N_INTC_OVERRIDE_OFF:
291 b43_phy_write(dev, reg, 0);
292 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
293 break;
294 case N_INTC_OVERRIDE_TRSW:
295 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
296 b43_phy_set(dev, reg, 0x400);
297
298 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
299 b43_phy_set(dev, 0x2ff, 0x2000);
300 b43_phy_set(dev, 0x2ff, 0x0001);
301 break;
302 case N_INTC_OVERRIDE_PA:
303 tmp = 0x0030;
304 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
305 val = value << 5;
306 else
307 val = value << 4;
308 b43_phy_maskset(dev, reg, ~tmp, val);
309 b43_phy_set(dev, reg, 0x1000);
310 break;
311 case N_INTC_OVERRIDE_EXT_LNA_PU:
312 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
313 tmp = 0x0001;
314 tmp2 = 0x0004;
315 val = value;
316 } else {
317 tmp = 0x0004;
318 tmp2 = 0x0001;
319 val = value << 2;
320 }
321 b43_phy_maskset(dev, reg, ~tmp, val);
322 b43_phy_mask(dev, reg, ~tmp2);
323 break;
324 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
325 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
326 tmp = 0x0002;
327 tmp2 = 0x0008;
328 val = value << 1;
329 } else {
330 tmp = 0x0008;
331 tmp2 = 0x0002;
332 val = value << 3;
333 }
334 b43_phy_maskset(dev, reg, ~tmp, val);
335 b43_phy_mask(dev, reg, ~tmp2);
336 break;
337 }
338 }
339}
340
ab499217 341/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 342static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
343 enum n_intc_override intc_override,
344 u16 value, u8 core)
d4814e69 345{
ab499217
RM		 346 u8 i, j;
347 u16 reg, tmp, val;
38646eba 348
4256ba77
RM		 349 if (dev->phy.rev >= 7) {
350 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
351 core);
352 return;
353 }
354
d4814e69
RM		 355 B43_WARN_ON(dev->phy.rev < 3);
356
ab499217
RM		 357 for (i = 0; i < 2; i++) {
358 if ((core == 1 && i == 1) || (core == 2 && !i))
359 continue;
38646eba 360
ab499217
RM		 361 reg = (i == 0) ?
362 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 363 b43_phy_set(dev, reg, 0x400);
38646eba 364
89e43dad
RM		 365 switch (intc_override) {
366 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 367 b43_phy_write(dev, reg, 0);
368 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
369 break;
89e43dad 370 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 371 if (!i) {
372 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
373 0xFC3F, (value << 6));
374 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
375 0xFFFE, 1);
376 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
377 B43_NPHY_RFCTL_CMD_START);
378 for (j = 0; j < 100; j++) {
603431e9 379 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 380 j = 0;
381 break;
382 }
383 udelay(10);
38646eba 384 }
ab499217
RM		 385 if (j)
386 b43err(dev->wl,
387 "intc override timeout\n");
388 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
389 0xFFFE);
38646eba 390 } else {
ab499217
RM		 391 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
392 0xFC3F, (value << 6));
393 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
394 0xFFFE, 1);
395 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
396 B43_NPHY_RFCTL_CMD_RXTX);
397 for (j = 0; j < 100; j++) {
603431e9 398 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 399 j = 0;
400 break;
401 }
402 udelay(10);
403 }
404 if (j)
405 b43err(dev->wl,
406 "intc override timeout\n");
407 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
408 0xFFFE);
38646eba 409 }
ab499217 410 break;
89e43dad 411 case N_INTC_OVERRIDE_PA:
ab499217
RM		 412 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
413 tmp = 0x0020;
414 val = value << 5;
415 } else {
416 tmp = 0x0010;
417 val = value << 4;
418 }
419 b43_phy_maskset(dev, reg, ~tmp, val);
420 break;
89e43dad 421 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 422 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
423 tmp = 0x0001;
424 val = value;
425 } else {
426 tmp = 0x0004;
427 val = value << 2;
428 }
429 b43_phy_maskset(dev, reg, ~tmp, val);
430 break;
89e43dad 431 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 432 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
433 tmp = 0x0002;
434 val = value << 1;
435 } else {
436 tmp = 0x0008;
437 val = value << 3;
438 }
439 b43_phy_maskset(dev, reg, ~tmp, val);
440 break;
38646eba 441 }
38646eba 442 }
ab499217 443}
38646eba 444
ab499217
RM		 445/**************************************************
446 * Various PHY ops
447 **************************************************/
448
449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
450static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
451 const u16 *clip_st)
452{
453 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
454 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 455}
456
ab499217
RM		 457/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
458static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 459{
ab499217
RM		 460 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
461 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 462}
463
ab499217
RM		 464/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
465static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 466{
ab499217 467 u16 tmp;
161d540c 468
ab499217
RM		 469 if (dev->dev->core_rev == 16)
470 b43_mac_suspend(dev);
161d540c 471
ab499217
RM		 472 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
473 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
474 B43_NPHY_CLASSCTL_WAITEDEN);
475 tmp &= ~mask;
476 tmp |= (val & mask);
477 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 478
ab499217
RM		 479 if (dev->dev->core_rev == 16)
480 b43_mac_enable(dev);
161d540c 481
ab499217
RM		 482 return tmp;
483}
161d540c 484
ab499217
RM		 485/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
486static void b43_nphy_reset_cca(struct b43_wldev *dev)
487{
488 u16 bbcfg;
161d540c 489
ab499217
RM		 490 b43_phy_force_clock(dev, 1);
491 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
492 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
493 udelay(1);
494 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
495 b43_phy_force_clock(dev, 0);
496 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
497}
161d540c 498
ab499217
RM		 499/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
500static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
501{
502 struct b43_phy *phy = &dev->phy;
503 struct b43_phy_n *nphy = phy->n;
161d540c 504
ab499217
RM		 505 if (enable) {
506 static const u16 clip[] = { 0xFFFF, 0xFFFF };
507 if (nphy->deaf_count++ == 0) {
508 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 509 b43_nphy_classifier(dev, 0x7,
510 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 511 b43_nphy_read_clip_detection(dev, nphy->clip_state);
512 b43_nphy_write_clip_detection(dev, clip);
513 }
514 b43_nphy_reset_cca(dev);
161d540c 515 } else {
ab499217
RM		 516 if (--nphy->deaf_count == 0) {
517 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
518 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 519 }
161d540c 520 }
161d540c
RM		 521}
522
64712095
RM		 523/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
524static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 525{
161d540c 526 struct b43_phy_n *nphy = dev->phy.n;
161d540c 527
64712095
RM		 528 u8 i;
529 s16 tmp;
530 u16 data[4];
531 s16 gain[2];
532 u16 minmax[2];
533 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 534
535 if (nphy->hang_avoid)
536 b43_nphy_stay_in_carrier_search(dev, 1);
537
64712095 538 if (nphy->gain_boost) {
161d540c 539 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 540 gain[0] = 6;
541 gain[1] = 6;
161d540c 542 } else {
64712095
RM		 543 tmp = 40370 - 315 * dev->phy.channel;
544 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
545 tmp = 23242 - 224 * dev->phy.channel;
546 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 547 }
64712095
RM		 548 } else {
549 gain[0] = 0;
550 gain[1] = 0;
161d540c 551 }
161d540c
RM		 552
553 for (i = 0; i < 2; i++) {
64712095
RM		 554 if (nphy->elna_gain_config) {
555 data[0] = 19 + gain[i];
556 data[1] = 25 + gain[i];
557 data[2] = 25 + gain[i];
558 data[3] = 25 + gain[i];
161d540c 559 } else {
64712095
RM		 560 data[0] = lna_gain[0] + gain[i];
561 data[1] = lna_gain[1] + gain[i];
562 data[2] = lna_gain[2] + gain[i];
563 data[3] = lna_gain[3] + gain[i];
161d540c 564 }
64712095 565 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 566
64712095 567 minmax[i] = 23 + gain[i];
161d540c
RM		 568 }
569
64712095
RM		 570 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
571 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
572 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
573 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 574
575 if (nphy->hang_avoid)
576 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 577}
578
ab499217
RM		 579/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
580static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
581 u8 *events, u8 *delays, u8 length)
0eff8fcd 582{
ab499217
RM		 583 struct b43_phy_n *nphy = dev->phy.n;
584 u8 i;
585 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
586 u16 offset1 = cmd << 4;
587 u16 offset2 = offset1 + 0x80;
0eff8fcd 588
ab499217
RM		 589 if (nphy->hang_avoid)
590 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 591
ab499217
RM		 592 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
593 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 594
ab499217
RM		 595 for (i = length; i < 16; i++) {
596 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
597 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 598 }
ab499217
RM		 599
600 if (nphy->hang_avoid)
601 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 602}
7955de0c 603
572d37a4
RM		 604/**************************************************
605 * Radio 0x2057
606 **************************************************/
607
fe255b40
RM		 608static void b43_radio_2057_chantab_upload(struct b43_wldev *dev,
609 const struct b43_nphy_chantabent_rev7 *e_r7,
610 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g)
611{
612 if (e_r7_2g) {
613 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
614 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
615 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
616 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
617 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
618 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
619 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
620 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
621 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
622 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
623 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
624 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
625 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
626 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
627 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
628 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
629 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
630 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
631
632 } else {
633 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
634 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
635 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
636 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
637 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
638 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
639 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
640 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
641 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
642 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
643 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
644 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
645 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
646 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
647 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
648 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
649 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
650 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
651 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
652 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
653 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
654 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
655 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
656 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
657 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
658 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
659 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
660 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
661 }
662}
663
664static void b43_radio_2057_setup(struct b43_wldev *dev,
665 const struct b43_nphy_chantabent_rev7 *tabent_r7,
666 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g)
667{
668 struct b43_phy *phy = &dev->phy;
669
670 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g);
671
672 switch (phy->radio_rev) {
673 case 0 ... 4:
674 case 6:
675 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
676 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
677 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
678 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
679 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
680 } else {
681 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
682 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f);
683 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8);
684 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8);
685 }
686 break;
687 /* TODO */
688 }
689
690 /* TODO */
691
692 usleep_range(50, 100);
693
694 /* VCO calibration */
695 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01);
696 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
698 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
699 usleep_range(300, 600);
700}
701
e90cf1c7
RM		 702/* Calibrate resistors in LPF of PLL?
703 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal
704 */
572d37a4
RM		 705static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
706{
707 struct b43_phy *phy = &dev->phy;
708 u16 tmp;
709
710 if (phy->radio_rev == 5) {
711 b43_phy_mask(dev, 0x342, ~0x2);
712 udelay(10);
713 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
714 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
715 }
716
e90cf1c7 717 /* Enable */
572d37a4
RM		 718 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
719 udelay(10);
e90cf1c7
RM		 720
721 /* Start */
722 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
723 usleep_range(100, 200);
724
725 /* Stop */
726 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
727
728 /* Wait and check for result */
729 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
572d37a4
RM		 730 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
731 return 0;
732 }
572d37a4 733 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
e90cf1c7
RM		 734
735 /* Disable */
572d37a4
RM		 736 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
737
738 if (phy->radio_rev == 5) {
739 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
740 b43_radio_mask(dev, 0x1ca, ~0x2);
741 }
742 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
743 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
744 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
745 tmp << 2);
746 }
747
748 return tmp & 0x3e;
749}
750
e90cf1c7
RM		 751/* Calibrate the internal RC oscillator?
752 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal
753 */
572d37a4
RM		 754static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
755{
756 struct b43_phy *phy = &dev->phy;
757 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
758 phy->radio_rev == 6);
759 u16 tmp;
760
e90cf1c7 761 /* Setup cal */
572d37a4
RM		 762 if (special) {
763 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
764 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
765 } else {
e90cf1c7 766 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61);
572d37a4
RM		 767 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
768 }
769 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 770
771 /* Start, wait, stop */
572d37a4 772 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7 773 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 774 5000000))
775 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 776 usleep_range(35, 70);
572d37a4 777 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 778 usleep_range(70, 140);
779
780 /* Setup cal */
572d37a4
RM		 781 if (special) {
782 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
783 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
784 } else {
e90cf1c7 785 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69);
572d37a4
RM		 786 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
787 }
788 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
e90cf1c7
RM		 789
790 /* Start, wait, stop */
791 usleep_range(35, 70);
572d37a4 792 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 793 usleep_range(70, 140);
794 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4 795 5000000))
6c187236 796 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
e90cf1c7 797 usleep_range(35, 70);
572d37a4 798 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 799 usleep_range(70, 140);
800
801 /* Setup cal */
572d37a4
RM		 802 if (special) {
803 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
804 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
805 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
806 } else {
e90cf1c7 807 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73);
572d37a4
RM		 808 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
809 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
810 }
e90cf1c7
RM		 811
812 /* Start, wait, stop */
813 usleep_range(35, 70);
572d37a4 814 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
e90cf1c7
RM		 815 usleep_range(70, 140);
816 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
572d37a4
RM		 817 5000000)) {
818 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
819 return 0;
820 }
821 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
e90cf1c7 822 usleep_range(35, 70);
572d37a4 823 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
e90cf1c7
RM		 824 usleep_range(70, 140);
825
826 if (special)
827 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1);
828 else
829 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1);
830
572d37a4
RM		 831 return tmp;
832}
833
834static void b43_radio_2057_init_pre(struct b43_wldev *dev)
835{
836 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
837 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
838 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
839 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
840 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
841}
842
843static void b43_radio_2057_init_post(struct b43_wldev *dev)
844{
845 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
846
847 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
848 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
849 mdelay(2);
850 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
851 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
852
90e569d1 853 if (dev->phy.do_full_init) {
572d37a4
RM		 854 b43_radio_2057_rcal(dev);
855 b43_radio_2057_rccal(dev);
856 }
857 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
572d37a4
RM		 858}
859
860/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
861static void b43_radio_2057_init(struct b43_wldev *dev)
862{
863 b43_radio_2057_init_pre(dev);
864 r2057_upload_inittabs(dev);
865 b43_radio_2057_init_post(dev);
866}
867
ab499217 868/**************************************************
884a5228 869 * Radio 0x2056
ab499217 870 **************************************************/
7955de0c 871
d4814e69
RM		 872static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
873 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 874{
d4814e69
RM		 875 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
876 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
877 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
878 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
879 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
880 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
881 e->radio_syn_pll_loopfilter1);
882 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
883 e->radio_syn_pll_loopfilter2);
884 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
885 e->radio_syn_pll_loopfilter3);
886 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
887 e->radio_syn_pll_loopfilter4);
888 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
889 e->radio_syn_pll_loopfilter5);
890 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
891 e->radio_syn_reserved_addr27);
892 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
893 e->radio_syn_reserved_addr28);
894 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
895 e->radio_syn_reserved_addr29);
896 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
897 e->radio_syn_logen_vcobuf1);
898 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
899 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
900 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
901
902 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
903 e->radio_rx0_lnaa_tune);
904 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
905 e->radio_rx0_lnag_tune);
906
907 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
908 e->radio_tx0_intpaa_boost_tune);
909 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
910 e->radio_tx0_intpag_boost_tune);
911 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
912 e->radio_tx0_pada_boost_tune);
913 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
914 e->radio_tx0_padg_boost_tune);
915 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
916 e->radio_tx0_pgaa_boost_tune);
917 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
918 e->radio_tx0_pgag_boost_tune);
919 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
920 e->radio_tx0_mixa_boost_tune);
921 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
922 e->radio_tx0_mixg_boost_tune);
923
924 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
925 e->radio_rx1_lnaa_tune);
926 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
927 e->radio_rx1_lnag_tune);
928
929 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
930 e->radio_tx1_intpaa_boost_tune);
931 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
932 e->radio_tx1_intpag_boost_tune);
933 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
934 e->radio_tx1_pada_boost_tune);
935 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
936 e->radio_tx1_padg_boost_tune);
937 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
938 e->radio_tx1_pgaa_boost_tune);
939 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
940 e->radio_tx1_pgag_boost_tune);
941 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
942 e->radio_tx1_mixa_boost_tune);
943 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
944 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 945}
946
d4814e69
RM		 947/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
948static void b43_radio_2056_setup(struct b43_wldev *dev,
949 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 950{
39e971ef 951 struct b43_phy *phy = &dev->phy;
0581483a 952 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 953 enum ieee80211_band band = b43_current_band(dev->wl);
954 u16 offset;
955 u8 i;
d3d178f0
RM		 956 u16 bias, cbias;
957 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
958 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 959 bool is_pkg_fab_smic;
036cafe4 960
d4814e69 961 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 962
b88cdde9
RM		 963 is_pkg_fab_smic =
964 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
965 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
966 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
967 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
968
d4814e69 969 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 970 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
971
972 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
973 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
974 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
975 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 976 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
977 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 978 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
979 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
980 } else {
981 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
982 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 983 }
53a6e234 984 }
b88cdde9
RM		 985 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
986 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
987 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
988 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
989 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
990 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
991 }
38646eba
RM		 992 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
993 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
994 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
995 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
996 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
997 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 998 }
53a6e234 999
38646eba
RM		 1000 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
1001 for (i = 0; i < 2; i++) {
1002 offset = i ? B2056_TX1 : B2056_TX0;
1003 if (dev->phy.rev >= 5) {
1004 b43_radio_write(dev,
1005 offset | B2056_TX_PADG_IDAC, 0xcc);
1006
b88cdde9
RM		 1007 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
1008 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 1009 bias = 0x40;
1010 cbias = 0x45;
1011 pag_boost = 0x5;
1012 pgag_boost = 0x33;
1013 mixg_boost = 0x55;
1014 } else {
1015 bias = 0x25;
1016 cbias = 0x20;
b88cdde9
RM		 1017 if (is_pkg_fab_smic) {
1018 bias = 0x2a;
1019 cbias = 0x38;
1020 }
38646eba
RM		 1021 pag_boost = 0x4;
1022 pgag_boost = 0x03;
1023 mixg_boost = 0x65;
1024 }
1025 padg_boost = 0x77;
1026
1027 b43_radio_write(dev,
1028 offset | B2056_TX_INTPAG_IMAIN_STAT,
1029 bias);
1030 b43_radio_write(dev,
1031 offset | B2056_TX_INTPAG_IAUX_STAT,
1032 bias);
1033 b43_radio_write(dev,
1034 offset | B2056_TX_INTPAG_CASCBIAS,
1035 cbias);
1036 b43_radio_write(dev,
1037 offset | B2056_TX_INTPAG_BOOST_TUNE,
1038 pag_boost);
1039 b43_radio_write(dev,
1040 offset | B2056_TX_PGAG_BOOST_TUNE,
1041 pgag_boost);
1042 b43_radio_write(dev,
1043 offset | B2056_TX_PADG_BOOST_TUNE,
1044 padg_boost);
1045 b43_radio_write(dev,
1046 offset | B2056_TX_MIXG_BOOST_TUNE,
1047 mixg_boost);
1048 } else {
bee6d4b2 1049 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
38646eba
RM		 1050 b43_radio_write(dev,
1051 offset | B2056_TX_INTPAG_IMAIN_STAT,
1052 bias);
1053 b43_radio_write(dev,
1054 offset | B2056_TX_INTPAG_IAUX_STAT,
1055 bias);
1056 b43_radio_write(dev,
1057 offset | B2056_TX_INTPAG_CASCBIAS,
1058 0x30);
1059 }
1060 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
1061 }
1062 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
39e971ef 1063 u16 freq = phy->chandef->chan->center_freq;
d3d178f0
RM		 1064 if (freq < 5100) {
1065 paa_boost = 0xA;
1066 pada_boost = 0x77;
1067 pgaa_boost = 0xF;
1068 mixa_boost = 0xF;
1069 } else if (freq < 5340) {
1070 paa_boost = 0x8;
1071 pada_boost = 0x77;
1072 pgaa_boost = 0xFB;
1073 mixa_boost = 0xF;
1074 } else if (freq < 5650) {
1075 paa_boost = 0x0;
1076 pada_boost = 0x77;
1077 pgaa_boost = 0xB;
1078 mixa_boost = 0xF;
1079 } else {
1080 paa_boost = 0x0;
1081 pada_boost = 0x77;
1082 if (freq != 5825)
1083 pgaa_boost = -(freq - 18) / 36 + 168;
1084 else
1085 pgaa_boost = 6;
1086 mixa_boost = 0xF;
1087 }
1088
b88cdde9
RM		 1089 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
1090
d3d178f0
RM		 1091 for (i = 0; i < 2; i++) {
1092 offset = i ? B2056_TX1 : B2056_TX0;
1093
1094 b43_radio_write(dev,
1095 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
1096 b43_radio_write(dev,
1097 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
1098 b43_radio_write(dev,
1099 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
1100 b43_radio_write(dev,
1101 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
1102 b43_radio_write(dev,
1103 offset | B2056_TX_TXSPARE1, 0x30);
1104 b43_radio_write(dev,
1105 offset | B2056_TX_PA_SPARE2, 0xee);
1106 b43_radio_write(dev,
1107 offset | B2056_TX_PADA_CASCBIAS, 0x03);
1108 b43_radio_write(dev,
b88cdde9 1109 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 1110 b43_radio_write(dev,
b88cdde9 1111 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 1112 b43_radio_write(dev,
b88cdde9 1113 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 1114 }
a2d9bc6f 1115 }
38646eba 1116
d4814e69
RM		 1117 udelay(50);
1118 /* VCO calibration */
1119 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
1120 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1121 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
1122 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
1123 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
1124 udelay(300);
53a6e234
MB		 1125}
1126
d3d178f0
RM		 1127static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
1128{
1129 struct b43_phy *phy = &dev->phy;
1130 u16 mast2, tmp;
1131
1132 if (phy->rev != 3)
1133 return 0;
1134
1135 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
1136 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1137
1138 udelay(10);
1139 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1140 udelay(10);
1141 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
1142
1143 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1144 1000000)) {
1145 b43err(dev->wl, "Radio recalibration timeout\n");
1146 return 0;
1147 }
1148
1149 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1150 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1151 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1152
1153 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1154
1155 return tmp & 0x1f;
1156}
1157
ea7ee14b
RM		 1158static void b43_radio_init2056_pre(struct b43_wldev *dev)
1159{
1160 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1161 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1162 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1163 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1164 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1165 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1166 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1167 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1168 B43_NPHY_RFCTL_CMD_CHIP0PU);
1169}
1170
1171static void b43_radio_init2056_post(struct b43_wldev *dev)
1172{
1173 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1174 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1175 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1176 msleep(1);
1177 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1178 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1179 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
90e569d1 1180 if (dev->phy.do_full_init)
d3d178f0 1181 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1182}
1183
d817f4e1
RM		 1184/*
1185 * Initialize a Broadcom 2056 N-radio
1186 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1187 */
1188static void b43_radio_init2056(struct b43_wldev *dev)
1189{
ea7ee14b
RM		 1190 b43_radio_init2056_pre(dev);
1191 b2056_upload_inittabs(dev, 0, 0);
1192 b43_radio_init2056_post(dev);
d817f4e1
RM		 1193}
1194
884a5228
RM		 1195/**************************************************
1196 * Radio 0x2055
1197 **************************************************/
1198
1199static void b43_chantab_radio_upload(struct b43_wldev *dev,
1200 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1201{
884a5228
RM		 1202 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1203 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1204 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1205 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1206 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1207
884a5228
RM		 1208 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1209 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1210 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1211 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1212 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1213
884a5228
RM		 1214 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1215 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1216 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1217 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1218 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1219
884a5228
RM		 1220 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1221 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1222 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1223 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1224 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1225
884a5228
RM		 1226 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1227 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1228 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1229 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1230 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1231
884a5228
RM		 1232 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1233 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1234}
1235
884a5228
RM		 1236/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1237static void b43_radio_2055_setup(struct b43_wldev *dev,
1238 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1239{
884a5228 1240 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1241
884a5228
RM		 1242 b43_chantab_radio_upload(dev, e);
1243 udelay(50);
1244 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1245 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1246 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1247 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1248 udelay(300);
95b66bad
MB		 1249}
1250
884a5228 1251static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1252{
884a5228
RM		 1253 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1254 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1255 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1256 B43_NPHY_RFCTL_CMD_CHIP0PU |
1257 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1258 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1259 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1260}
1261
884a5228 1262static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1263{
1264 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1265 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1266 bool workaround = false;
2faa6b83 1267
884a5228
RM		 1268 if (sprom->revision < 4)
1269 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1270 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1271 && dev->dev->board_rev >= 0x41);
2faa6b83 1272 else
884a5228
RM		 1273 workaround =
1274 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1275
884a5228
RM		 1276 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1277 if (workaround) {
1278 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1279 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1280 }
1281 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1282 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1283 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1284 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1285 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1286 msleep(1);
1287 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1288 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1289 b43err(dev->wl, "radio post init timeout\n");
1290 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1291 b43_switch_channel(dev, dev->phy.channel);
1292 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1293 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1294 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1295 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1296 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1297 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1298 if (!nphy->gain_boost) {
1299 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1300 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1301 } else {
1302 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1303 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1304 }
1305 udelay(2);
2faa6b83
RM		 1306}
1307
884a5228
RM		 1308/*
1309 * Initialize a Broadcom 2055 N-radio
1310 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1311 */
1312static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1313{
884a5228
RM		 1314 b43_radio_init2055_pre(dev);
1315 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1316 /* Follow wl, not specs. Do not force uploading all regs */
1317 b2055_upload_inittab(dev, 0, 0);
a67162ab 1318 } else {
884a5228
RM		 1319 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1320 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1321 }
884a5228 1322 b43_radio_init2055_post(dev);
a67162ab
RM		 1323}
1324
8be89535
RM		 1325/**************************************************
1326 * Samples
1327 **************************************************/
026816fc 1328
8be89535
RM		 1329/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1330static int b43_nphy_load_samples(struct b43_wldev *dev,
1331 struct b43_c32 *samples, u16 len) {
1332 struct b43_phy_n *nphy = dev->phy.n;
1333 u16 i;
1334 u32 *data;
1335
1336 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1337 if (!data) {
1338 b43err(dev->wl, "allocation for samples loading failed\n");
1339 return -ENOMEM;
1340 }
1341 if (nphy->hang_avoid)
1342 b43_nphy_stay_in_carrier_search(dev, 1);
1343
1344 for (i = 0; i < len; i++) {
1345 data[i] = (samples[i].i & 0x3FF << 10);
1346 data[i] |= samples[i].q & 0x3FF;
1347 }
1348 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1349
1350 kfree(data);
1351 if (nphy->hang_avoid)
1352 b43_nphy_stay_in_carrier_search(dev, 0);
1353 return 0;
026816fc
RM		 1354}
1355
8be89535
RM		 1356/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1357static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1358 bool test)
026816fc 1359{
8be89535
RM		 1360 int i;
1361 u16 bw, len, rot, angle;
1362 struct b43_c32 *samples;
026816fc 1363
bee6d4b2 1364 bw = b43_is_40mhz(dev) ? 40 : 20;
8be89535 1365 len = bw << 3;
026816fc 1366
8be89535
RM		 1367 if (test) {
1368 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1369 bw = 82;
1370 else
1371 bw = 80;
026816fc 1372
bee6d4b2 1373 if (b43_is_40mhz(dev))
8be89535
RM		 1374 bw <<= 1;
1375
1376 len = bw << 1;
026816fc
RM		 1377 }
1378
8be89535
RM		 1379 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1380 if (!samples) {
1381 b43err(dev->wl, "allocation for samples generation failed\n");
1382 return 0;
1383 }
1384 rot = (((freq * 36) / bw) << 16) / 100;
1385 angle = 0;
026816fc 1386
8be89535
RM		 1387 for (i = 0; i < len; i++) {
1388 samples[i] = b43_cordic(angle);
1389 angle += rot;
1390 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1391 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1392 }
8be89535
RM		 1393
1394 i = b43_nphy_load_samples(dev, samples, len);
1395 kfree(samples);
1396 return (i < 0) ? 0 : len;
026816fc
RM		 1397}
1398
8be89535
RM		 1399/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1400static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
ed03033e
RM		 1401 u16 wait, bool iqmode, bool dac_test,
1402 bool modify_bbmult)
34a56f2c 1403{
303415e2 1404 struct b43_phy *phy = &dev->phy;
8be89535 1405 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1406 int i;
8be89535
RM		 1407 u16 seq_mode;
1408 u32 tmp;
34a56f2c 1409
bc36e994 1410 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1411
303415e2
RM		 1412 if (phy->rev >= 7) {
1413 /* TODO */
1414 }
1415
8be89535
RM		 1416 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1417 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1418 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1419 }
34a56f2c 1420
ed03033e
RM		 1421 if (modify_bbmult) {
1422 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747;
1423 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1424 }
34a56f2c 1425
8be89535 1426 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1427
8be89535
RM		 1428 if (loops != 0xFFFF)
1429 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1430 else
1431 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1432
8be89535 1433 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1434
8be89535 1435 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1436
8be89535
RM		 1437 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1438 if (iqmode) {
1439 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1440 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1441 } else {
ed03033e
RM		 1442 tmp = dac_test ? 5 : 1;
1443 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp);
8be89535
RM		 1444 }
1445 for (i = 0; i < 100; i++) {
2c8ac7eb 1446 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1447 i = 0;
1448 break;
34a56f2c 1449 }
8be89535 1450 udelay(10);
34a56f2c 1451 }
8be89535
RM		 1452 if (i)
1453 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1454
8be89535 1455 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1456
1457 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1458}
1459
4d9f46ba
RM		 1460/**************************************************
1461 * RSSI
1462 **************************************************/
1463
1464/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1465static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1466 s8 offset, u8 core,
1467 enum n_rail_type rail,
2a2d0589 1468 enum n_rssi_type rssi_type)
09146400 1469{
4d9f46ba
RM		 1470 u16 tmp;
1471 bool core1or5 = (core == 1) || (core == 5);
1472 bool core2or5 = (core == 2) || (core == 5);
09146400 1473
4d9f46ba
RM		 1474 offset = clamp_val(offset, -32, 31);
1475 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1476
e5ab1fd7 1477 switch (rssi_type) {
2a2d0589 1478 case N_RSSI_NB:
e5ab1fd7
RM		 1479 if (core1or5 && rail == N_RAIL_I)
1480 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1481 if (core1or5 && rail == N_RAIL_Q)
1482 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1483 if (core2or5 && rail == N_RAIL_I)
1484 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1485 if (core2or5 && rail == N_RAIL_Q)
1486 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1487 break;
2a2d0589 1488 case N_RSSI_W1:
e5ab1fd7
RM		 1489 if (core1or5 && rail == N_RAIL_I)
1490 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1491 if (core1or5 && rail == N_RAIL_Q)
1492 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1493 if (core2or5 && rail == N_RAIL_I)
1494 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1495 if (core2or5 && rail == N_RAIL_Q)
1496 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1497 break;
2a2d0589 1498 case N_RSSI_W2:
e5ab1fd7
RM		 1499 if (core1or5 && rail == N_RAIL_I)
1500 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1501 if (core1or5 && rail == N_RAIL_Q)
1502 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1503 if (core2or5 && rail == N_RAIL_I)
1504 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1505 if (core2or5 && rail == N_RAIL_Q)
1506 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1507 break;
2a2d0589 1508 case N_RSSI_TBD:
e5ab1fd7
RM		 1509 if (core1or5 && rail == N_RAIL_I)
1510 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1511 if (core1or5 && rail == N_RAIL_Q)
1512 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1513 if (core2or5 && rail == N_RAIL_I)
1514 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1515 if (core2or5 && rail == N_RAIL_Q)
1516 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1517 break;
2a2d0589 1518 case N_RSSI_IQ:
e5ab1fd7
RM		 1519 if (core1or5 && rail == N_RAIL_I)
1520 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1521 if (core1or5 && rail == N_RAIL_Q)
1522 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1523 if (core2or5 && rail == N_RAIL_I)
1524 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1525 if (core2or5 && rail == N_RAIL_Q)
1526 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1527 break;
2a2d0589 1528 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1529 if (core1or5)
1530 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1531 if (core2or5)
1532 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1533 break;
2a2d0589 1534 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1535 if (core1or5)
1536 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1537 if (core2or5)
1538 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1539 break;
1540 }
8987a9e9
RM		 1541}
1542
303415e2
RM		 1543static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code,
1544 enum n_rssi_type rssi_type)
1545{
1546 /* TODO */
1547}
1548
a3764ef7
RM		 1549static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1550 enum n_rssi_type rssi_type)
bbec398c 1551{
4d9f46ba
RM		 1552 u8 i;
1553 u16 reg, val;
bbec398c 1554
4d9f46ba
RM		 1555 if (code == 0) {
1556 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1557 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1558 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1559 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1560 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1561 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1562 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1563 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1564 } else {
1565 for (i = 0; i < 2; i++) {
1566 if ((code == 1 && i == 1) || (code == 2 && !i))
1567 continue;
bbec398c 1568
4d9f46ba
RM		 1569 reg = (i == 0) ?
1570 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1571 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1572
a3764ef7
RM		 1573 if (rssi_type == N_RSSI_W1 ||
1574 rssi_type == N_RSSI_W2 ||
1575 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1576 reg = (i == 0) ?
1577 B43_NPHY_AFECTL_C1 :
1578 B43_NPHY_AFECTL_C2;
1579 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1580
4d9f46ba
RM		 1581 reg = (i == 0) ?
1582 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1583 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1584 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1585
a3764ef7 1586 if (rssi_type == N_RSSI_W1)
4d9f46ba 1587 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1588 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1589 val = 16;
1590 else
1591 val = 32;
1592 b43_phy_set(dev, reg, val);
5c1a140a 1593
4d9f46ba
RM		 1594 reg = (i == 0) ?
1595 B43_NPHY_TXF_40CO_B1S0 :
1596 B43_NPHY_TXF_40CO_B32S1;
1597 b43_phy_set(dev, reg, 0x0020);
1598 } else {
a3764ef7 1599 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1600 val = 0x0100;
a3764ef7 1601 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1602 val = 0x0200;
1603 else
1604 val = 0x0300;
5c1a140a 1605
4d9f46ba
RM		 1606 reg = (i == 0) ?
1607 B43_NPHY_AFECTL_C1 :
1608 B43_NPHY_AFECTL_C2;
53ae8e8c 1609
4d9f46ba
RM		 1610 b43_phy_maskset(dev, reg, 0xFCFF, val);
1611 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1612
a3764ef7
RM		 1613 if (rssi_type != N_RSSI_IQ &&
1614 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1615 enum ieee80211_band band =
1616 b43_current_band(dev->wl);
53ae8e8c 1617
303415e2
RM		 1618 if (dev->phy.rev < 7) {
1619 if (b43_nphy_ipa(dev))
1620 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1621 else
1622 val = 0x11;
1623 reg = (i == 0) ? B2056_TX0 : B2056_TX1;
1624 reg |= B2056_TX_TX_SSI_MUX;
1625 b43_radio_write(dev, reg, val);
1626 }
53ae8e8c 1627
4d9f46ba
RM		 1628 reg = (i == 0) ?
1629 B43_NPHY_AFECTL_OVER1 :
1630 B43_NPHY_AFECTL_OVER;
1631 b43_phy_set(dev, reg, 0x0200);
1632 }
1633 }
1634 }
53ae8e8c 1635 }
53ae8e8c
RM		 1636}
1637
a3764ef7
RM		 1638static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1639 enum n_rssi_type rssi_type)
9442e5b5 1640{
4d9f46ba 1641 u16 val;
a3764ef7 1642 bool rssi_w1_w2_nb = false;
9442e5b5 1643
a3764ef7
RM		 1644 switch (rssi_type) {
1645 case N_RSSI_W1:
1646 case N_RSSI_W2:
1647 case N_RSSI_NB:
4d9f46ba 1648 val = 0;
a3764ef7
RM		 1649 rssi_w1_w2_nb = true;
1650 break;
1651 case N_RSSI_TBD:
4d9f46ba 1652 val = 1;
a3764ef7
RM		 1653 break;
1654 case N_RSSI_IQ:
4d9f46ba 1655 val = 2;
a3764ef7
RM		 1656 break;
1657 default:
4d9f46ba 1658 val = 3;
a3764ef7 1659 }
9442e5b5 1660
4d9f46ba
RM		 1661 val = (val << 12) | (val << 14);
1662 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1663 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1664
a3764ef7 1665 if (rssi_w1_w2_nb) {
4d9f46ba 1666 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1667 (rssi_type + 1) << 4);
4d9f46ba 1668 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1669 (rssi_type + 1) << 4);
9442e5b5
RM		 1670 }
1671
4d9f46ba
RM		 1672 if (code == 0) {
1673 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1674 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1675 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1676 ~(B43_NPHY_RFCTL_CMD_RXEN |
1677 B43_NPHY_RFCTL_CMD_CORESEL));
1678 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1679 ~(0x1 << 12 |
1680 0x1 << 5 |
1681 0x1 << 1 |
1682 0x1));
1683 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1684 ~B43_NPHY_RFCTL_CMD_START);
1685 udelay(20);
1686 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1687 }
1688 } else {
1689 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1690 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1691 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1692 ~(B43_NPHY_RFCTL_CMD_RXEN |
1693 B43_NPHY_RFCTL_CMD_CORESEL),
1694 (B43_NPHY_RFCTL_CMD_RXEN |
1695 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1696 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1697 (0x1 << 12 |
1698 0x1 << 5 |
1699 0x1 << 1 |
1700 0x1));
1701 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1702 B43_NPHY_RFCTL_CMD_START);
1703 udelay(20);
1704 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1705 }
9442e5b5 1706 }
9442e5b5
RM		 1707}
1708
4d9f46ba 1709/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1710static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1711 enum n_rssi_type type)
d24019ad 1712{
303415e2
RM		 1713 if (dev->phy.rev >= 19)
1714 b43_nphy_rssi_select_rev19(dev, code, type);
1715 else if (dev->phy.rev >= 3)
4d9f46ba
RM		 1716 b43_nphy_rev3_rssi_select(dev, code, type);
1717 else
1718 b43_nphy_rev2_rssi_select(dev, code, type);
1719}
d24019ad 1720
5ecab603 1721/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1722static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1723 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1724{
1725 int i;
d24019ad 1726 for (i = 0; i < 2; i++) {
a3764ef7 1727 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1728 if (i == 0) {
1729 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1730 0xFC, buf[0]);
1731 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1732 0xFC, buf[1]);
1733 } else {
1734 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1735 0xFC, buf[2 * i]);
1736 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1737 0xFC, buf[2 * i + 1]);
1738 }
d24019ad 1739 } else {
5ecab603
RM		 1740 if (i == 0)
1741 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1742 0xF3, buf[0] << 2);
1743 else
1744 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1745 0xF3, buf[2 * i + 1] << 2);
d24019ad 1746 }
d24019ad 1747 }
d24019ad
RM		 1748}
1749
5ecab603 1750/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1751static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1752 s32 *buf, u8 nsamp)
ef5127a4 1753{
5ecab603
RM		 1754 int i;
1755 int out;
1756 u16 save_regs_phy[9];
1757 u16 s[2];
ef5127a4 1758
303415e2
RM		 1759 /* TODO: rev7+ is treated like rev3+, what about rev19+? */
1760
ef5127a4 1761 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1762 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1763 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1764 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1765 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1766 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1767 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1768 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1769 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1770 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1771 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1772 save_regs_phy[8] = 0;
ef5127a4 1773 } else {
5ecab603
RM		 1774 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1775 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1776 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1777 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1778 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1779 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1780 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1781 save_regs_phy[7] = 0;
1782 save_regs_phy[8] = 0;
1783 }
ef5127a4 1784
a3764ef7 1785 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1786
5ecab603
RM		 1787 if (dev->phy.rev < 2) {
1788 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1789 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1790 }
ef5127a4 1791
5ecab603
RM		 1792 for (i = 0; i < 4; i++)
1793 buf[i] = 0;
1794
1795 for (i = 0; i < nsamp; i++) {
1796 if (dev->phy.rev < 2) {
1797 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1798 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1799 } else {
5ecab603
RM		 1800 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1801 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1802 }
1803
5ecab603
RM		 1804 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1805 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1806 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1807 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1808 }
1809 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1810 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1811
5ecab603
RM		 1812 if (dev->phy.rev < 2)
1813 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1814
5ecab603 1815 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1816 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1817 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1818 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1819 save_regs_phy[2]);
5ecab603 1820 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1821 save_regs_phy[3]);
5ecab603
RM		 1822 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1823 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1824 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1825 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1826 } else {
1827 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1828 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1829 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1830 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1831 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1832 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1833 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1834 }
ef5127a4 1835
5ecab603
RM		 1836 return out;
1837}
ef5127a4 1838
e0c9a021
RM		 1839/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1840static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1841{
39e971ef 1842 struct b43_phy *phy = &dev->phy;
e0c9a021
RM		 1843 struct b43_phy_n *nphy = dev->phy.n;
1844
1845 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1846 u16 saved_regs_phy[22];
1847 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1848 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1849 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1850 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1851 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1852 B43_NPHY_RFCTL_CMD,
1853 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1854 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1855 };
97e2a1a1
RM		 1856 u16 regs_to_store_rev7[] = {
1857 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1858 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1859 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1860 0x342, 0x343, 0x346, 0x347,
1861 0x2ff,
1862 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1863 B43_NPHY_RFCTL_CMD,
1864 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1865 0x340, 0x341, 0x344, 0x345,
1866 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1867 };
1868 u16 *regs_to_store;
1869 int regs_amount;
e0c9a021
RM		 1870
1871 u16 class;
1872
1873 u16 clip_state[2];
1874 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1875
1876 u8 vcm_final = 0;
2e1253d6 1877 s32 offset[4];
e0c9a021
RM		 1878 s32 results[8][4] = { };
1879 s32 results_min[4] = { };
1880 s32 poll_results[4] = { };
1881
1882 u16 *rssical_radio_regs = NULL;
1883 u16 *rssical_phy_regs = NULL;
1884
1885 u16 r; /* routing */
1886 u8 rx_core_state;
37859a75 1887 int core, i, j, vcm;
e0c9a021 1888
97e2a1a1
RM		 1889 if (dev->phy.rev >= 7) {
1890 regs_to_store = regs_to_store_rev7;
1891 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1892 } else {
1893 regs_to_store = regs_to_store_rev3;
1894 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1895 }
1896 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1897
e0c9a021
RM		 1898 class = b43_nphy_classifier(dev, 0, 0);
1899 b43_nphy_classifier(dev, 7, 4);
1900 b43_nphy_read_clip_detection(dev, clip_state);
1901 b43_nphy_write_clip_detection(dev, clip_off);
1902
1903 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1904 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1905 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1906 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1907
89e43dad
RM		 1908 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1909 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1910
1911 if (dev->phy.rev >= 7) {
1912 /* TODO */
1913 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1914 } else {
1915 }
e0c9a021 1916 } else {
97e2a1a1
RM		 1917 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1918 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1919 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1920 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1921 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1922 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1923 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1924 } else {
1925 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1926 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1927 }
e0c9a021
RM		 1928 }
1929
1930 rx_core_state = b43_nphy_get_rx_core_state(dev);
1931 for (core = 0; core < 2; core++) {
1932 if (!(rx_core_state & (1 << core)))
1933 continue;
1934 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1935 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1936 N_RSSI_NB);
1937 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1938 N_RSSI_NB);
37859a75
RM		 1939
1940 /* Grab RSSI results for every possible VCM */
1941 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1942 if (dev->phy.rev >= 7)
1943 ;
1944 else
1945 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1946 0xE3, vcm << 2);
a3764ef7 1947 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1948 }
37859a75
RM		 1949
1950 /* Find out which VCM got the best results */
cddec902 1951 for (i = 0; i < 4; i += 2) {
37859a75 1952 s32 currd;
e67dd874 1953 s32 mind = 0x100000;
e0c9a021
RM		 1954 s32 minpoll = 249;
1955 u8 minvcm = 0;
1956 if (2 * core != i)
1957 continue;
37859a75
RM		 1958 for (vcm = 0; vcm < 8; vcm++) {
1959 currd = results[vcm][i] * results[vcm][i] +
1960 results[vcm][i + 1] * results[vcm][i];
1961 if (currd < mind) {
1962 mind = currd;
1963 minvcm = vcm;
e0c9a021 1964 }
37859a75
RM		 1965 if (results[vcm][i] < minpoll)
1966 minpoll = results[vcm][i];
e0c9a021
RM		 1967 }
1968 vcm_final = minvcm;
1969 results_min[i] = minpoll;
1970 }
37859a75
RM		 1971
1972 /* Select the best VCM */
97e2a1a1
RM		 1973 if (dev->phy.rev >= 7)
1974 ;
1975 else
1976 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1977 0xE3, vcm_final << 2);
37859a75 1978
e0c9a021
RM		 1979 for (i = 0; i < 4; i++) {
1980 if (core != i / 2)
1981 continue;
1982 offset[i] = -results[vcm_final][i];
1983 if (offset[i] < 0)
1984 offset[i] = -((abs(offset[i]) + 4) / 8);
1985 else
1986 offset[i] = (offset[i] + 4) / 8;
1987 if (results_min[i] == 248)
1988 offset[i] = -32;
1989 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1990 (i / 2 == 0) ? 1 : 2,
6aa38725 1991 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1992 N_RSSI_NB);
e0c9a021
RM		 1993 }
1994 }
37859a75 1995
e0c9a021
RM		 1996 for (core = 0; core < 2; core++) {
1997 if (!(rx_core_state & (1 << core)))
1998 continue;
1999 for (i = 0; i < 2; i++) {
6aa38725
RM		 2000 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2001 N_RAIL_I, i);
2002 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
2003 N_RAIL_Q, i);
e0c9a021
RM		 2004 b43_nphy_poll_rssi(dev, i, poll_results, 8);
2005 for (j = 0; j < 4; j++) {
cddec902 2006 if (j / 2 == core) {
e0c9a021 2007 offset[j] = 232 - poll_results[j];
cddec902
RM		 2008 if (offset[j] < 0)
2009 offset[j] = -(abs(offset[j] + 4) / 8);
2010 else
2011 offset[j] = (offset[j] + 4) / 8;
2012 b43_nphy_scale_offset_rssi(dev, 0,
2013 offset[2 * core], core + 1, j % 2, i);
2014 }
e0c9a021
RM		 2015 }
2016 }
2017 }
2018
2019 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2020 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2021
2022 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2023
2024 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
2025 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
2026 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
2027
2028 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2029 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 2030 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 2031
97e2a1a1 2032 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 2033 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
2034
2035 /* Store for future configuration */
2036 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2037 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2038 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2039 } else {
2040 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2041 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2042 }
9a98979e
RM		 2043 if (dev->phy.rev >= 7) {
2044 } else {
2045 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
2046 B2056_RX_RSSI_MISC);
2047 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
2048 B2056_RX_RSSI_MISC);
2049 }
e0c9a021
RM		 2050 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
2051 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
2052 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
2053 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
2054 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
2055 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
2056 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
2057 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
2058 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
2059 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
2060 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
2061 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
2062
2063 /* Remember for which channel we store configuration */
2064 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
39e971ef 2065 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
e0c9a021 2066 else
39e971ef 2067 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
e0c9a021
RM		 2068
2069 /* End of calibration, restore configuration */
2070 b43_nphy_classifier(dev, 7, class);
2071 b43_nphy_write_clip_detection(dev, clip_state);
2072}
2073
5ecab603 2074/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 2075static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 2076{
37859a75 2077 int i, j, vcm;
5ecab603
RM		 2078 u8 state[4];
2079 u8 code, val;
2080 u16 class, override;
2081 u8 regs_save_radio[2];
2082 u16 regs_save_phy[2];
2083
2e1253d6 2084 s32 offset[4];
5ecab603
RM		 2085 u8 core;
2086 u8 rail;
2087
2088 u16 clip_state[2];
2089 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2090 s32 results_min[4] = { };
2091 u8 vcm_final[4] = { };
2092 s32 results[4][4] = { };
2093 s32 miniq[4][2] = { };
2094
a3764ef7 2095 if (type == N_RSSI_NB) {
5ecab603
RM		 2096 code = 0;
2097 val = 6;
a3764ef7 2098 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 2099 code = 25;
2100 val = 4;
2101 } else {
2102 B43_WARN_ON(1);
2103 return;
2104 }
2105
2106 class = b43_nphy_classifier(dev, 0, 0);
2107 b43_nphy_classifier(dev, 7, 4);
2108 b43_nphy_read_clip_detection(dev, clip_state);
2109 b43_nphy_write_clip_detection(dev, clip_off);
2110
2111 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2112 override = 0x140;
2113 else
2114 override = 0x110;
2115
2116 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 2117 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 2118 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 2119 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 2120
2121 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 2122 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 2123 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 2124 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 2125
0c201cfb
RM		 2126 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2127 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 2128 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2129 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 2130 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
2131 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 2132
2133 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 2134 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
2135 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 2136
37859a75 2137 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 2138 u8 tmp[4];
2139 for (j = 0; j < 4; j++)
37859a75 2140 tmp[j] = vcm;
a3764ef7 2141 if (type != N_RSSI_W2)
5ecab603 2142 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 2143 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 2144 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 2145 for (j = 0; j < 2; j++)
37859a75
RM		 2146 miniq[vcm][j] = min(results[vcm][2 * j],
2147 results[vcm][2 * j + 1]);
5ecab603
RM		 2148 }
2149
2150 for (i = 0; i < 4; i++) {
e67dd874 2151 s32 mind = 0x100000;
5ecab603
RM		 2152 u8 minvcm = 0;
2153 s32 minpoll = 249;
37859a75
RM		 2154 s32 currd;
2155 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 2156 if (type == N_RSSI_NB)
542e15f3 2157 currd = abs(results[vcm][i] - code * 8);
5ecab603 2158 else
37859a75 2159 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 2160
37859a75
RM		 2161 if (currd < mind) {
2162 mind = currd;
2163 minvcm = vcm;
5ecab603
RM		 2164 }
2165
37859a75
RM		 2166 if (results[vcm][i] < minpoll)
2167 minpoll = results[vcm][i];
8e60b044 2168 }
5ecab603
RM		 2169 results_min[i] = minpoll;
2170 vcm_final[i] = minvcm;
2171 }
ef5127a4 2172
a3764ef7 2173 if (type != N_RSSI_W2)
5ecab603 2174 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2175
5ecab603
RM		 2176 for (i = 0; i < 4; i++) {
2177 offset[i] = (code * 8) - results[vcm_final[i]][i];
2178
2179 if (offset[i] < 0)
2180 offset[i] = -((abs(offset[i]) + 4) / 8);
2181 else
2182 offset[i] = (offset[i] + 4) / 8;
2183
2184 if (results_min[i] == 248)
2185 offset[i] = code - 32;
2186
2187 core = (i / 2) ? 2 : 1;
6aa38725 2188 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2189
2190 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2191 type);
2192 }
2193
2194 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2195 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2196
2197 switch (state[2]) {
2198 case 1:
a3764ef7 2199 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2200 break;
2201 case 4:
a3764ef7 2202 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2203 break;
2204 case 2:
a3764ef7 2205 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2206 break;
2207 default:
a3764ef7 2208 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2209 break;
2210 }
2211
2212 switch (state[3]) {
2213 case 1:
a3764ef7 2214 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2215 break;
2216 case 4:
a3764ef7 2217 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2218 break;
2219 default:
a3764ef7 2220 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2221 break;
2222 }
2223
2224 b43_nphy_rssi_select(dev, 0, type);
2225
2226 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2227 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2228 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2229 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2230
2231 b43_nphy_classifier(dev, 7, class);
2232 b43_nphy_write_clip_detection(dev, clip_state);
2233 /* Specs don't say about reset here, but it makes wl and b43 dumps
2234 identical, it really seems wl performs this */
2235 b43_nphy_reset_cca(dev);
2236}
2237
5ecab603
RM		 2238/*
2239 * RSSI Calibration
2240 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2241 */
2242static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2243{
303415e2
RM		 2244 if (dev->phy.rev >= 19) {
2245 /* TODO */
2246 } else if (dev->phy.rev >= 3) {
5ecab603
RM		 2247 b43_nphy_rev3_rssi_cal(dev);
2248 } else {
2a2d0589
RM		 2249 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2250 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2251 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2252 }
2253}
2254
64712095
RM		 2255/**************************************************
2256 * Workarounds
2257 **************************************************/
2258
303415e2
RM		 2259static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev)
2260{
2261 /* TODO */
2262}
2263
2264static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev)
2265{
2266 struct b43_phy *phy = &dev->phy;
2267
2268 switch (phy->rev) {
2269 /* TODO */
2270 }
2271}
2272
2273static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev)
64712095
RM		 2274{
2275 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2276
2277 bool ghz5;
2278 bool ext_lna;
2279 u16 rssi_gain;
2280 struct nphy_gain_ctl_workaround_entry *e;
2281 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2282 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2283
2284 /* Prepare values */
2285 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2286 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2287 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2288 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2289 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2290 if (ghz5 && dev->phy.rev >= 5)
2291 rssi_gain = 0x90;
2292 else
2293 rssi_gain = 0x50;
2294
2295 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2296
2297 /* Set Clip 2 detect */
04519dc6
RM		 2298 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2299 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2300
2301 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2302 0x17);
2303 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2304 0x17);
2305 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2306 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2307 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2308 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2309 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2310 rssi_gain);
2311 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2312 rssi_gain);
2313 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2314 0x17);
2315 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2316 0x17);
2317 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2318 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2319
2320 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2321 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2322 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2323 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2324 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2325 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2326 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2327 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2328 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2329 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2330 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2331 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2332
04519dc6
RM		 2333 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2334 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2335
64712095
RM		 2336 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2337 e->rfseq_init);
64712095 2338
04519dc6
RM		 2339 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2340 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2341 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2342 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2343 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2344 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2345
2346 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2347 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2348 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2349 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2350 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2351 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2352 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2353 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2354 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2355 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2356}
2357
2358static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2359{
2360 struct b43_phy_n *nphy = dev->phy.n;
2361
2362 u8 i, j;
2363 u8 code;
2364 u16 tmp;
2365 u8 rfseq_events[3] = { 6, 8, 7 };
2366 u8 rfseq_delays[3] = { 10, 30, 1 };
2367
2368 /* Set Clip 2 detect */
2369 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2370 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2371
2372 /* Set narrowband clip threshold */
2373 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2374 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2375
bee6d4b2 2376 if (!b43_is_40mhz(dev)) {
64712095
RM		 2377 /* Set dwell lengths */
2378 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2379 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2380 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2381 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2382 }
2383
2384 /* Set wideband clip 2 threshold */
2385 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2386 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2387 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2388 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2389
bee6d4b2 2390 if (!b43_is_40mhz(dev)) {
64712095
RM		 2391 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2392 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2393 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2394 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2395 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2396 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2397 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2398 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2399 }
2400
2401 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2402
2403 if (nphy->gain_boost) {
2404 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
bee6d4b2 2405 b43_is_40mhz(dev))
64712095
RM		 2406 code = 4;
2407 else
2408 code = 5;
2409 } else {
bee6d4b2 2410 code = b43_is_40mhz(dev) ? 6 : 7;
64712095
RM		 2411 }
2412
2413 /* Set HPVGA2 index */
2414 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2415 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2416 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2417 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2418
2419 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2420 /* specs say about 2 loops, but wl does 4 */
2421 for (i = 0; i < 4; i++)
2422 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2423
2424 b43_nphy_adjust_lna_gain_table(dev);
2425
2426 if (nphy->elna_gain_config) {
2427 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2428 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2429 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2430 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2431 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2432
2433 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2434 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2435 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2436 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2437 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2438
2439 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2440 /* specs say about 2 loops, but wl does 4 */
2441 for (i = 0; i < 4; i++)
2442 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2443 (code << 8 | 0x74));
2444 }
2445
2446 if (dev->phy.rev == 2) {
2447 for (i = 0; i < 4; i++) {
2448 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2449 (0x0400 * i) + 0x0020);
2450 for (j = 0; j < 21; j++) {
2451 tmp = j * (i < 2 ? 3 : 1);
2452 b43_phy_write(dev,
2453 B43_NPHY_TABLE_DATALO, tmp);
2454 }
2455 }
ef5127a4 2456 }
64712095
RM		 2457
2458 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2459 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2460 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2461 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2462
2463 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2464 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2465}
2466
2467/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2468static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2469{
303415e2
RM		 2470 if (dev->phy.rev >= 19)
2471 b43_nphy_gain_ctl_workarounds_rev19(dev);
2472 else if (dev->phy.rev >= 7)
2473 b43_nphy_gain_ctl_workarounds_rev7(dev);
d11d354b 2474 else if (dev->phy.rev >= 3)
303415e2 2475 b43_nphy_gain_ctl_workarounds_rev3(dev);
64712095
RM		 2476 else
2477 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2478}
2479
d11d354b
RM		 2480/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2481static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2482{
2483 if (!offset)
bee6d4b2 2484 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
d11d354b
RM		 2485 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2486}
2487
2488static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2489{
2490 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2491 struct b43_phy *phy = &dev->phy;
2492
2493 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2494 0x1F };
2495 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2496
2497 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2498 u8 ntab7_138_146[] = { 0x11, 0x11 };
2499 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2500
2501 u16 lpf_20, lpf_40, lpf_11b;
2502 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2503 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2504 bool rccal_ovrd = false;
2505
2506 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2507 u16 bias, conv, filt;
2508
2509 u32 tmp32;
2510 u8 core;
2511
2512 if (phy->rev == 7) {
2513 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2514 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2515 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2516 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2517 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2518 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2519 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2520 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2521 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2522 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2523 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2524 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2525 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2526 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2527 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2528 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2529 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2530 }
2531 if (phy->rev <= 8) {
04519dc6
RM		 2532 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2533 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2534 }
2535 if (phy->rev >= 8)
2536 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2537
2538 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2539 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2540 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2541 tmp32 &= 0xffffff;
2542 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2543 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2544 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2545
2546 if (b43_nphy_ipa(dev))
2547 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2548 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2549
04519dc6
RM		 2550 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2551 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2552
2553 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2554 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2555 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2556 if (b43_nphy_ipa(dev)) {
bee6d4b2 2557 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
d11d354b
RM		 2558 phy->radio_rev == 7 || phy->radio_rev == 8) {
2559 bcap_val = b43_radio_read(dev, 0x16b);
2560 scap_val = b43_radio_read(dev, 0x16a);
2561 scap_val_11b = scap_val;
2562 bcap_val_11b = bcap_val;
bee6d4b2 2563 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
d11d354b
RM		 2564 scap_val_11n_20 = scap_val;
2565 bcap_val_11n_20 = bcap_val;
2566 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2567 rccal_ovrd = true;
2568 } else { /* Rev 7/8 */
2569 lpf_20 = 4;
2570 lpf_11b = 1;
2571 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2572 scap_val_11n_20 = 0xc;
2573 bcap_val_11n_20 = 0xc;
2574 scap_val_11n_40 = 0xa;
2575 bcap_val_11n_40 = 0xa;
2576 } else {
2577 scap_val_11n_20 = 0x14;
2578 bcap_val_11n_20 = 0x14;
2579 scap_val_11n_40 = 0xf;
2580 bcap_val_11n_40 = 0xf;
2581 }
2582 rccal_ovrd = true;
2583 }
2584 }
2585 } else {
2586 if (phy->radio_rev == 5) {
2587 lpf_20 = 1;
2588 lpf_40 = 3;
2589 bcap_val = b43_radio_read(dev, 0x16b);
2590 scap_val = b43_radio_read(dev, 0x16a);
2591 scap_val_11b = scap_val;
2592 bcap_val_11b = bcap_val;
2593 scap_val_11n_20 = 0x11;
2594 scap_val_11n_40 = 0x11;
2595 bcap_val_11n_20 = 0x13;
2596 bcap_val_11n_40 = 0x13;
2597 rccal_ovrd = true;
2598 }
2599 }
2600 if (rccal_ovrd) {
2601 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2602 (scap_val_11b << 3) |
2603 lpf_11b;
2604 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2605 (scap_val_11n_20 << 3) |
2606 lpf_20;
2607 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2608 (scap_val_11n_40 << 3) |
2609 lpf_40;
2610 for (core = 0; core < 2; core++) {
2611 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2612 rx2tx_lut_20_11b);
2613 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2614 rx2tx_lut_20_11n);
2615 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2616 rx2tx_lut_20_11n);
2617 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2618 rx2tx_lut_40_11n);
2619 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2620 rx2tx_lut_40_11n);
2621 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2622 rx2tx_lut_40_11n);
2623 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2624 rx2tx_lut_40_11n);
2625 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2626 rx2tx_lut_40_11n);
2627 }
78ae7532 2628 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2629 }
2630 b43_phy_write(dev, 0x32F, 0x3);
2631 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2632 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2633
2634 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2635 if (sprom->revision &&
2636 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2637 b43_radio_write(dev, 0x5, 0x05);
2638 b43_radio_write(dev, 0x6, 0x30);
2639 b43_radio_write(dev, 0x7, 0x00);
2640 b43_radio_set(dev, 0x4f, 0x1);
2641 b43_radio_set(dev, 0xd4, 0x1);
2642 bias = 0x1f;
2643 conv = 0x6f;
2644 filt = 0xaa;
2645 } else {
2646 bias = 0x2b;
2647 conv = 0x7f;
2648 filt = 0xee;
2649 }
2650 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2651 for (core = 0; core < 2; core++) {
2652 if (core == 0) {
2653 b43_radio_write(dev, 0x5F, bias);
2654 b43_radio_write(dev, 0x64, conv);
2655 b43_radio_write(dev, 0x66, filt);
2656 } else {
2657 b43_radio_write(dev, 0xE8, bias);
2658 b43_radio_write(dev, 0xE9, conv);
2659 b43_radio_write(dev, 0xEB, filt);
2660 }
2661 }
2662 }
2663 }
2664
2665 if (b43_nphy_ipa(dev)) {
2666 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2667 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2668 phy->radio_rev == 6) {
2669 for (core = 0; core < 2; core++) {
2670 if (core == 0)
2671 b43_radio_write(dev, 0x51,
2672 0x7f);
2673 else
2674 b43_radio_write(dev, 0xd6,
2675 0x7f);
2676 }
2677 }
2678 if (phy->radio_rev == 3) {
2679 for (core = 0; core < 2; core++) {
2680 if (core == 0) {
2681 b43_radio_write(dev, 0x64,
2682 0x13);
2683 b43_radio_write(dev, 0x5F,
2684 0x1F);
2685 b43_radio_write(dev, 0x66,
2686 0xEE);
2687 b43_radio_write(dev, 0x59,
2688 0x8A);
2689 b43_radio_write(dev, 0x80,
2690 0x3E);
2691 } else {
2692 b43_radio_write(dev, 0x69,
2693 0x13);
2694 b43_radio_write(dev, 0xE8,
2695 0x1F);
2696 b43_radio_write(dev, 0xEB,
2697 0xEE);
2698 b43_radio_write(dev, 0xDE,
2699 0x8A);
2700 b43_radio_write(dev, 0x105,
2701 0x3E);
2702 }
2703 }
2704 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
bee6d4b2 2705 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2706 b43_radio_write(dev, 0x5F, 0x14);
2707 b43_radio_write(dev, 0xE8, 0x12);
2708 } else {
2709 b43_radio_write(dev, 0x5F, 0x16);
2710 b43_radio_write(dev, 0xE8, 0x16);
2711 }
2712 }
2713 } else {
39e971ef 2714 u16 freq = phy->chandef->chan->center_freq;
d11d354b
RM		 2715 if ((freq >= 5180 && freq <= 5230) ||
2716 (freq >= 5745 && freq <= 5805)) {
2717 b43_radio_write(dev, 0x7D, 0xFF);
2718 b43_radio_write(dev, 0xFE, 0xFF);
2719 }
2720 }
2721 } else {
2722 if (phy->radio_rev != 5) {
2723 for (core = 0; core < 2; core++) {
2724 if (core == 0) {
2725 b43_radio_write(dev, 0x5c, 0x61);
2726 b43_radio_write(dev, 0x51, 0x70);
2727 } else {
2728 b43_radio_write(dev, 0xe1, 0x61);
2729 b43_radio_write(dev, 0xd6, 0x70);
2730 }
2731 }
2732 }
2733 }
2734
2735 if (phy->radio_rev == 4) {
2736 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2737 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2738 for (core = 0; core < 2; core++) {
2739 if (core == 0) {
2740 b43_radio_write(dev, 0x1a1, 0x00);
2741 b43_radio_write(dev, 0x1a2, 0x3f);
2742 b43_radio_write(dev, 0x1a6, 0x3f);
2743 } else {
2744 b43_radio_write(dev, 0x1a7, 0x00);
2745 b43_radio_write(dev, 0x1ab, 0x3f);
2746 b43_radio_write(dev, 0x1ac, 0x3f);
2747 }
2748 }
2749 } else {
2750 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2751 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2752 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2753 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2754
2755 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2756 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2757 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2758 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2759 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2760 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2761
2762 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2763 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2764 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2765 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2766 }
2767
2768 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2769
2770 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2771 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2772 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2773 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2774 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2775 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2776 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2777
bee6d4b2 2778 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2779 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2780 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2781 } else {
2782 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2783 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2784 }
2785
2786 b43_nphy_gain_ctl_workarounds(dev);
2787
2788 /* TODO
2789 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2790 aux_adc_vmid_rev7_core0);
2791 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2792 aux_adc_vmid_rev7_core1);
2793 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2794 aux_adc_gain_rev7);
2795 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2796 aux_adc_gain_rev7);
2797 */
2798}
2799
73d07a39 2800static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2801{
0eff8fcd 2802 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2803 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2804
0eff8fcd 2805 /* TX to RX */
c378bb97
RM		 2806 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2807 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2808 /* RX to TX */
2809 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2810 0x1F };
2811 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2812 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2813 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2814
c378bb97
RM		 2815 u16 vmids[5][4] = {
2816 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2817 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2818 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2819 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2820 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2821 };
2822 u16 gains[5][4] = {
2823 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2824 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2825 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2826 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2827 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2828 };
2829 u16 *vmid, *gain;
2830
2831 u8 pdet_range;
ba9a6214
RM		 2832 u16 tmp16;
2833 u32 tmp32;
2834
04519dc6
RM		 2835 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2836 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2837
73d07a39
RM		 2838 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2839 tmp32 &= 0xffffff;
2840 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2841
73d07a39
RM		 2842 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2843 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2844 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2845 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2846 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2847 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2848
04519dc6
RM		 2849 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2850 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2851
0eff8fcd 2852 /* TX to RX */
c56da252
RM		 2853 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2854 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2855
2856 /* RX to TX */
2857 if (b43_nphy_ipa(dev))
c56da252
RM		 2858 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2859 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2860 if (nphy->hw_phyrxchain != 3 &&
2861 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2862 if (b43_nphy_ipa(dev)) {
2863 rx2tx_delays[5] = 59;
2864 rx2tx_delays[6] = 1;
2865 rx2tx_events[7] = 0x1F;
2866 }
fa0f2b38 2867 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2868 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2869 }
ba9a6214 2870
73d07a39
RM		 2871 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2872 0x2 : 0x9C40;
2873 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2874
04519dc6 2875 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2876
bee6d4b2 2877 if (!b43_is_40mhz(dev)) {
fa0f2b38
RM		 2878 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2879 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2880 } else {
2881 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2882 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2883 }
ba9a6214 2884
3ccd0957 2885 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2886
c56da252
RM		 2887 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2888 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2889
c378bb97
RM		 2890 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2891 pdet_range = sprom->fem.ghz2.pdet_range;
2892 else
2893 pdet_range = sprom->fem.ghz5.pdet_range;
2894 vmid = vmids[min_t(u16, pdet_range, 4)];
2895 gain = gains[min_t(u16, pdet_range, 4)];
2896 switch (pdet_range) {
2897 case 3:
2898 if (!(dev->phy.rev >= 4 &&
2899 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2900 break;
2901 /* FALL THROUGH */
2902 case 0:
2903 case 1:
2904 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2905 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2906 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2907 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2908 break;
2909 case 2:
2910 if (dev->phy.rev >= 6) {
2911 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2912 vmid[3] = 0x94;
2913 else
2914 vmid[3] = 0x8e;
2915 gain[3] = 3;
2916 } else if (dev->phy.rev == 5) {
2917 vmid[3] = 0x84;
2918 gain[3] = 2;
2919 }
2920 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2921 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2922 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2923 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2924 break;
2925 case 4:
2926 case 5:
2927 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2928 if (pdet_range == 4) {
2929 vmid[3] = 0x8e;
2930 tmp16 = 0x96;
2931 gain[3] = 0x2;
2932 } else {
2933 vmid[3] = 0x89;
2934 tmp16 = 0x89;
2935 gain[3] = 0;
2936 }
2937 } else {
2938 if (pdet_range == 4) {
2939 vmid[3] = 0x89;
2940 tmp16 = 0x8b;
2941 gain[3] = 0x2;
2942 } else {
2943 vmid[3] = 0x74;
2944 tmp16 = 0x70;
2945 gain[3] = 0;
2946 }
2947 }
2948 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2949 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2950 vmid[3] = tmp16;
2951 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2952 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2953 break;
2954 }
ba9a6214 2955
73d07a39
RM		 2956 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2957 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2958 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2959 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2960 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2961 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2962 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2963 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2964 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2965 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2966 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2967 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2968
2969 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2970
2971 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2972 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2973 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2974 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2975 tmp32 = 0x00088888;
2976 else
2977 tmp32 = 0x88888888;
2978 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2979 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2980 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2981
2982 if (dev->phy.rev == 4 &&
fa0f2b38 2983 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2984 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2985 0x70);
2986 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2987 0x70);
2988 }
ba9a6214 2989
fa0f2b38 2990 /* Dropped probably-always-true condition */
04519dc6
RM		 2991 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2992 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2993 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2994 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2995 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2996 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2997 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2998 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2999 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3000 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3001 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3002 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 3003
3004 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
3005 ; /* TODO: 0x0080000000000000 HF */
73d07a39 3006}
ba9a6214 3007
73d07a39
RM		 3008static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
3009{
3010 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3011 struct b43_phy *phy = &dev->phy;
3012 struct b43_phy_n *nphy = phy->n;
ba9a6214 3013
73d07a39
RM		 3014 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
3015 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 3016
73d07a39
RM		 3017 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
3018 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 3019
fa0f2b38 3020 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 3021 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 3022 delays1[0] = 0x1;
3023 delays1[5] = 0x14;
3024 }
3025
73d07a39
RM		 3026 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
3027 nphy->band5g_pwrgain) {
3028 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
3029 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 3030 } else {
73d07a39
RM		 3031 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
3032 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
3033 }
28fd7daa 3034
73d07a39
RM		 3035 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
3036 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 3037 if (dev->phy.rev < 3) {
3038 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
3039 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
3040 }
73d07a39
RM		 3041
3042 if (dev->phy.rev < 2) {
3043 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
3044 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
3045 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
3046 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
3047 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
3048 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
3049 }
28fd7daa 3050
73d07a39
RM		 3051 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3052 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3053 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3054 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 3055
73d07a39
RM		 3056 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
3057 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
3058
3ccd0957 3059 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 3060
3061 if (dev->phy.rev < 2) {
3062 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
3063 b43_hf_write(dev, b43_hf_read(dev) |
3064 B43_HF_MLADVW);
3065 } else if (dev->phy.rev == 2) {
3066 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
3067 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
3068 }
28fd7daa 3069
73d07a39
RM		 3070 if (dev->phy.rev < 2)
3071 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
3072 ~B43_NPHY_SCRAM_SIGCTL_SCM);
3073
3074 /* Set phase track alpha and beta */
3075 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
3076 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
3077 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
3078 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
3079 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
3080 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
3081
fa0f2b38
RM		 3082 if (dev->phy.rev < 3) {
3083 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
3084 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
3085 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
3086 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
3087 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
3088 }
73d07a39
RM		 3089
3090 if (dev->phy.rev == 2)
3091 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
3092 B43_NPHY_FINERX2_CGC_DECGC);
3093}
28fd7daa 3094
73d07a39
RM		 3095/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
3096static void b43_nphy_workarounds(struct b43_wldev *dev)
3097{
3098 struct b43_phy *phy = &dev->phy;
3099 struct b43_phy_n *nphy = phy->n;
28fd7daa 3100
73d07a39
RM		 3101 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3102 b43_nphy_classifier(dev, 1, 0);
3103 else
3104 b43_nphy_classifier(dev, 1, 1);
28fd7daa 3105
73d07a39
RM		 3106 if (nphy->hang_avoid)
3107 b43_nphy_stay_in_carrier_search(dev, 1);
3108
3109 b43_phy_set(dev, B43_NPHY_IQFLIP,
3110 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
3111
303415e2 3112 /* TODO: rev19+ */
d11d354b
RM		 3113 if (dev->phy.rev >= 7)
3114 b43_nphy_workarounds_rev7plus(dev);
3115 else if (dev->phy.rev >= 3)
73d07a39
RM		 3116 b43_nphy_workarounds_rev3plus(dev);
3117 else
3118 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 3119
3120 if (nphy->hang_avoid)
3121 b43_nphy_stay_in_carrier_search(dev, 0);
3122}
3123
9dd4d9b9
RM		 3124/**************************************************
3125 * Tx/Rx common
3126 **************************************************/
3127
3128/*
3129 * Transmits a known value for LO calibration
3130 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
3131 */
3132static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
ed03033e 3133 bool iqmode, bool dac_test, bool modify_bbmult)
9dd4d9b9
RM		 3134{
3135 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
3136 if (samp == 0)
3137 return -1;
ed03033e
RM		 3138 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test,
3139 modify_bbmult);
9dd4d9b9
RM		 3140 return 0;
3141}
3142
3143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
3144static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
3145{
3146 struct b43_phy_n *nphy = dev->phy.n;
3147
3148 bool override = false;
3149 u16 chain = 0x33;
3150
3151 if (nphy->txrx_chain == 0) {
3152 chain = 0x11;
3153 override = true;
3154 } else if (nphy->txrx_chain == 1) {
3155 chain = 0x22;
3156 override = true;
3157 }
3158
3159 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3160 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
3161 chain);
3162
3163 if (override)
3164 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
3165 B43_NPHY_RFSEQMODE_CAOVER);
3166 else
3167 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3168 ~B43_NPHY_RFSEQMODE_CAOVER);
3169}
3170
3171/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
3172static void b43_nphy_stop_playback(struct b43_wldev *dev)
3173{
3174 struct b43_phy_n *nphy = dev->phy.n;
3175 u16 tmp;
3176
3177 if (nphy->hang_avoid)
3178 b43_nphy_stay_in_carrier_search(dev, 1);
3179
3180 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3181 if (tmp & 0x1)
3182 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3183 else if (tmp & 0x2)
3184 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3185
3186 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3187
3188 if (nphy->bb_mult_save & 0x80000000) {
3189 tmp = nphy->bb_mult_save & 0xFFFF;
3190 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3191 nphy->bb_mult_save = 0;
3192 }
3193
303415e2
RM		 3194 if (dev->phy.rev >= 7) {
3195 /* TODO */
3196 }
3197
9dd4d9b9
RM		 3198 if (nphy->hang_avoid)
3199 b43_nphy_stay_in_carrier_search(dev, 0);
3200}
3201
3202/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3203static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3204 struct nphy_txgains target,
3205 struct nphy_iqcal_params *params)
3206{
303415e2 3207 struct b43_phy *phy = &dev->phy;
9dd4d9b9
RM		 3208 int i, j, indx;
3209 u16 gain;
3210
3211 if (dev->phy.rev >= 3) {
3212 params->txgm = target.txgm[core];
3213 params->pga = target.pga[core];
3214 params->pad = target.pad[core];
3215 params->ipa = target.ipa[core];
303415e2
RM		 3216 if (phy->rev >= 19) {
3217 /* TODO */
3218 } else if (phy->rev >= 7) {
3219 /* TODO */
3220 } else {
3221 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa);
3222 }
9dd4d9b9
RM		 3223 for (j = 0; j < 5; j++)
3224 params->ncorr[j] = 0x79;
3225 } else {
3226 gain = (target.pad[core]) | (target.pga[core] << 4) |
3227 (target.txgm[core] << 8);
3228
3229 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3230 1 : 0;
3231 for (i = 0; i < 9; i++)
3232 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3233 break;
3234 i = min(i, 8);
3235
3236 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3237 params->pga = tbl_iqcal_gainparams[indx][i][2];
3238 params->pad = tbl_iqcal_gainparams[indx][i][3];
3239 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3240 (params->pad << 2);
3241 for (j = 0; j < 4; j++)
3242 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3243 }
3244}
3245
884a5228 3246/**************************************************
104cfa88 3247 * Tx and Rx
884a5228 3248 **************************************************/
5f6393ec 3249
884a5228
RM		 3250static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3251{//TODO
3252}
59af099b 3253
884a5228
RM		 3254static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3255 bool ignore_tssi)
3256{//TODO
3257 return B43_TXPWR_RES_DONE;
3258}
59af099b 3259
161d540c
RM		 3260/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3261static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3262{
303415e2 3263 struct b43_phy *phy = &dev->phy;
161d540c
RM		 3264 struct b43_phy_n *nphy = dev->phy.n;
3265 u8 i;
c9c0d9ec
RM		 3266 u16 bmask, val, tmp;
3267 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3268
161d540c
RM		 3269 if (nphy->hang_avoid)
3270 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3271
161d540c
RM		 3272 nphy->txpwrctrl = enable;
3273 if (!enable) {
c9c0d9ec
RM		 3274 if (dev->phy.rev >= 3 &&
3275 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3276 (B43_NPHY_TXPCTL_CMD_COEFF |
3277 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3278 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3279 /* We disable enabled TX pwr ctl, save it's state */
3280 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3281 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3282 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3283 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3284 }
59af099b 3285
161d540c
RM		 3286 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3287 for (i = 0; i < 84; i++)
3288 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3289
161d540c
RM		 3290 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3291 for (i = 0; i < 84; i++)
3292 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3293
161d540c
RM		 3294 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3295 if (dev->phy.rev >= 3)
3296 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3297 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3298
161d540c
RM		 3299 if (dev->phy.rev >= 3) {
3300 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3301 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3302 } else {
3303 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3304 }
10a79873 3305
161d540c
RM		 3306 if (dev->phy.rev == 2)
3307 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3308 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3309 else if (dev->phy.rev < 2)
3310 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3311 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3312
bee6d4b2 3313 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3314 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3315 } else {
c9c0d9ec
RM		 3316 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3317 nphy->adj_pwr_tbl);
3318 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3319 nphy->adj_pwr_tbl);
10a79873 3320
c9c0d9ec
RM		 3321 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3322 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3323 /* wl does useless check for "enable" param here */
3324 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3325 if (dev->phy.rev >= 3) {
3326 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3327 if (val)
3328 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3329 }
3330 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3331
c9c0d9ec 3332 if (band == IEEE80211_BAND_5GHZ) {
303415e2
RM		 3333 if (phy->rev >= 19) {
3334 /* TODO */
3335 } else if (phy->rev >= 7) {
3336 /* TODO */
3337 } else {
3338 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3339 ~B43_NPHY_TXPCTL_CMD_INIT,
c9c0d9ec 3340 0x64);
303415e2
RM		 3341 if (phy->rev > 1)
3342 b43_phy_maskset(dev,
3343 B43_NPHY_TXPCTL_INIT,
3344 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3345 0x64);
3346 }
c9c0d9ec 3347 }
10a79873 3348
c9c0d9ec
RM		 3349 if (dev->phy.rev >= 3) {
3350 if (nphy->tx_pwr_idx[0] != 128 &&
3351 nphy->tx_pwr_idx[1] != 128) {
3352 /* Recover TX pwr ctl state */
3353 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3354 ~B43_NPHY_TXPCTL_CMD_INIT,
3355 nphy->tx_pwr_idx[0]);
3356 if (dev->phy.rev > 1)
3357 b43_phy_maskset(dev,
3358 B43_NPHY_TXPCTL_INIT,
3359 ~0xff, nphy->tx_pwr_idx[1]);
3360 }
3361 }
10a79873 3362
303415e2
RM		 3363 if (phy->rev >= 7) {
3364 /* TODO */
3365 }
3366
c9c0d9ec
RM		 3367 if (dev->phy.rev >= 3) {
3368 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3369 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3370 } else {
3371 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3372 }
10a79873 3373
c9c0d9ec
RM		 3374 if (dev->phy.rev == 2)
3375 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3376 else if (dev->phy.rev < 2)
3377 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3378
bee6d4b2 3379 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3380 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3381
c002831a 3382 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3383 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3384 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3385 }
10a79873 3386 }
10a79873 3387
161d540c
RM		 3388 if (nphy->hang_avoid)
3389 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3390}
3391
161d540c 3392/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3393static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91 3394{
39e971ef 3395 struct b43_phy *phy = &dev->phy;
6dcd9d91 3396 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3397 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3398
161d540c
RM		 3399 u8 txpi[2], bbmult, i;
3400 u16 tmp, radio_gain, dac_gain;
39e971ef 3401 u16 freq = phy->chandef->chan->center_freq;
161d540c
RM		 3402 u32 txgain;
3403 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3404
3405 if (nphy->hang_avoid)
161d540c 3406 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3407
303415e2 3408 /* TODO: rev19+ */
dd5f13b8
RM		 3409 if (dev->phy.rev >= 7) {
3410 txpi[0] = txpi[1] = 30;
3411 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3412 txpi[0] = 40;
3413 txpi[1] = 40;
3414 } else if (sprom->revision < 4) {
3415 txpi[0] = 72;
3416 txpi[1] = 72;
3417 } else {
3418 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3419 txpi[0] = sprom->txpid2g[0];
3420 txpi[1] = sprom->txpid2g[1];
3421 } else if (freq >= 4900 && freq < 5100) {
3422 txpi[0] = sprom->txpid5gl[0];
3423 txpi[1] = sprom->txpid5gl[1];
3424 } else if (freq >= 5100 && freq < 5500) {
3425 txpi[0] = sprom->txpid5g[0];
3426 txpi[1] = sprom->txpid5g[1];
3427 } else if (freq >= 5500) {
3428 txpi[0] = sprom->txpid5gh[0];
3429 txpi[1] = sprom->txpid5gh[1];
3430 } else {
3431 txpi[0] = 91;
3432 txpi[1] = 91;
6dcd9d91
RM		 3433 }
3434 }
dd5f13b8 3435 if (dev->phy.rev < 7 &&
9bd28571 3436 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3437 txpi[0] = txpi[1] = 91;
6dcd9d91 3438
161d540c
RM		 3439 /*
3440 for (i = 0; i < 2; i++) {
3441 nphy->txpwrindex[i].index_internal = txpi[i];
3442 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3443 }
161d540c 3444 */
75377b24 3445
161d540c 3446 for (i = 0; i < 2; i++) {
7ef5cd24
RM		 3447 const u32 *table = b43_nphy_get_tx_gain_table(dev);
3448
3449 if (!table)
3450 break;
3451 txgain = *(table + txpi[i]);
aeab5751
RM		 3452
3453 if (dev->phy.rev >= 3)
161d540c 3454 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3455 else
161d540c 3456 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3457
dd5f13b8
RM		 3458 if (dev->phy.rev >= 7)
3459 dac_gain = (txgain >> 8) & 0x7;
3460 else
3461 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3462 bbmult = txgain & 0xFF;
75377b24 3463
161d540c
RM		 3464 if (dev->phy.rev >= 3) {
3465 if (i == 0)
3466 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3467 else
3468 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3469 } else {
3470 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3471 }
75377b24 3472
161d540c
RM		 3473 if (i == 0)
3474 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3475 else
3476 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3477
44f4008b 3478 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3479
44f4008b 3480 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3481 if (i == 0)
3482 tmp = (tmp & 0x00FF) | (bbmult << 8);
3483 else
3484 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3485 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3486
0eff8fcd
RM		 3487 if (b43_nphy_ipa(dev)) {
3488 u32 tmp32;
3489 u16 reg = (i == 0) ?
3490 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3491 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3492 576 + txpi[i]));
0eff8fcd
RM		 3493 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3494 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3495 }
3496 }
75377b24 3497
161d540c 3498 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3499
161d540c
RM		 3500 if (nphy->hang_avoid)
3501 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3502}
67cbc3ed 3503
3dda07b6
RM		 3504static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3505{
3506 struct b43_phy *phy = &dev->phy;
3507
3508 u8 core;
3509 u16 r; /* routing */
3510
303415e2
RM		 3511 if (phy->rev >= 19) {
3512 /* TODO */
3513 } else if (phy->rev >= 7) {
3dda07b6
RM		 3514 for (core = 0; core < 2; core++) {
3515 r = core ? 0x190 : 0x170;
3516 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3517 b43_radio_write(dev, r + 0x5, 0x5);
3518 b43_radio_write(dev, r + 0x9, 0xE);
3519 if (phy->rev != 5)
3520 b43_radio_write(dev, r + 0xA, 0);
3521 if (phy->rev != 7)
3522 b43_radio_write(dev, r + 0xB, 1);
3523 else
3524 b43_radio_write(dev, r + 0xB, 0x31);
3525 } else {
3526 b43_radio_write(dev, r + 0x5, 0x9);
3527 b43_radio_write(dev, r + 0x9, 0xC);
3528 b43_radio_write(dev, r + 0xB, 0x0);
3529 if (phy->rev != 5)
3530 b43_radio_write(dev, r + 0xA, 1);
3531 else
3532 b43_radio_write(dev, r + 0xA, 0x31);
3533 }
3534 b43_radio_write(dev, r + 0x6, 0);
3535 b43_radio_write(dev, r + 0x7, 0);
3536 b43_radio_write(dev, r + 0x8, 3);
3537 b43_radio_write(dev, r + 0xC, 0);
3538 }
3539 } else {
3540 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3541 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3542 else
3543 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3544 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3545 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3546
3547 for (core = 0; core < 2; core++) {
3548 r = core ? B2056_TX1 : B2056_TX0;
3549
3550 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3551 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3552 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3553 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3554 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3555 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3556 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3557 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3558 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3559 0x5);
3560 if (phy->rev != 5)
3561 b43_radio_write(dev, r | B2056_TX_TSSIA,
3562 0x00);
3563 if (phy->rev >= 5)
3564 b43_radio_write(dev, r | B2056_TX_TSSIG,
3565 0x31);
3566 else
3567 b43_radio_write(dev, r | B2056_TX_TSSIG,
3568 0x11);
3569 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3570 0xE);
3571 } else {
3572 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3573 0x9);
3574 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3575 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3576 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3577 0xC);
3578 }
3579 }
3580 }
3581}
3582
3583/*
3584 * Stop radio and transmit known signal. Then check received signal strength to
3585 * get TSSI (Transmit Signal Strength Indicator).
3586 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3587 */
3588static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3589{
3590 struct b43_phy *phy = &dev->phy;
3591 struct b43_phy_n *nphy = dev->phy.n;
3592
3593 u32 tmp;
3594 s32 rssi[4] = { };
3595
3596 /* TODO: check if we can transmit */
3597
3598 if (b43_nphy_ipa(dev))
3599 b43_nphy_ipa_internal_tssi_setup(dev);
3600
303415e2
RM		 3601 if (phy->rev >= 19)
3602 b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, false, 0);
3603 else if (phy->rev >= 7)
78ae7532 3604 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3605 else if (phy->rev >= 3)
78ae7532 3606 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3607
3608 b43_nphy_stop_playback(dev);
ed03033e 3609 b43_nphy_tx_tone(dev, 4000, 0, false, false, false);
3dda07b6 3610 udelay(20);
a3764ef7 3611 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3612 b43_nphy_stop_playback(dev);
303415e2 3613
a3764ef7 3614 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6 3615
303415e2
RM		 3616 if (phy->rev >= 19)
3617 b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, true, 0);
3618 else if (phy->rev >= 7)
78ae7532 3619 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3620 else if (phy->rev >= 3)
78ae7532 3621 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6 3622
303415e2
RM		 3623 if (phy->rev >= 19) {
3624 /* TODO */
3625 return;
3626 } else if (phy->rev >= 3) {
3dda07b6
RM		 3627 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3628 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3629 } else {
3630 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3631 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3632 }
3633 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3634 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3635}
3636
d3fd8bf7
RM		 3637/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3638static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3639{
3640 struct b43_phy_n *nphy = dev->phy.n;
3641
3642 u8 idx, delta;
3643 u8 i, stf_mode;
3644
55757927
RM		 3645 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3646 * 21 groups, each containing 4 entries.
3647 *
3648 * First group has entries for CCK modulation.
3649 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3650 *
3651 * Group 0 is for CCK
3652 * Groups 1..4 use BPSK (group per coding rate)
3653 * Groups 5..8 use QPSK (group per coding rate)
3654 * Groups 9..12 use 16-QAM (group per coding rate)
3655 * Groups 13..16 use 64-QAM (group per coding rate)
3656 * Groups 17..20 are unknown
3657 */
3658
d3fd8bf7
RM		 3659 for (i = 0; i < 4; i++)
3660 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3661
3662 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3663 delta = 0;
3664 switch (stf_mode) {
3665 case 0:
bee6d4b2 3666 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
d3fd8bf7
RM		 3667 idx = 68;
3668 } else {
3669 delta = 1;
bee6d4b2 3670 idx = b43_is_40mhz(dev) ? 52 : 4;
d3fd8bf7
RM		 3671 }
3672 break;
3673 case 1:
bee6d4b2 3674 idx = b43_is_40mhz(dev) ? 76 : 28;
d3fd8bf7
RM		 3675 break;
3676 case 2:
bee6d4b2 3677 idx = b43_is_40mhz(dev) ? 84 : 36;
d3fd8bf7
RM		 3678 break;
3679 case 3:
bee6d4b2 3680 idx = b43_is_40mhz(dev) ? 92 : 44;
d3fd8bf7
RM		 3681 break;
3682 }
3683
3684 for (i = 0; i < 20; i++) {
3685 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3686 nphy->tx_power_offset[idx];
3687 if (i == 0)
3688 idx += delta;
3689 if (i == 14)
3690 idx += 1 - delta;
3691 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3692 i == 13)
3693 idx += 1;
3694 }
3695 }
3696}
3697
3698/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3699static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3700{
39e971ef 3701 struct b43_phy *phy = &dev->phy;
d3fd8bf7
RM		 3702 struct b43_phy_n *nphy = dev->phy.n;
3703 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3704
3705 s16 a1[2], b0[2], b1[2];
3706 u8 idle[2];
3707 s8 target[2];
3708 s32 num, den, pwr;
3709 u32 regval[64];
3710
39e971ef 3711 u16 freq = phy->chandef->chan->center_freq;
d3fd8bf7
RM		 3712 u16 tmp;
3713 u16 r; /* routing */
3714 u8 i, c;
3715
3716 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3717 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3718 b43_read32(dev, B43_MMIO_MACCTL);
3719 udelay(1);
3720 }
3721
3722 if (nphy->hang_avoid)
3723 b43_nphy_stay_in_carrier_search(dev, true);
3724
3725 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3726 if (dev->phy.rev >= 3)
3727 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3728 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3729 else
3730 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3731 B43_NPHY_TXPCTL_CMD_PCTLEN);
3732
3733 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3734 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3735
3736 if (sprom->revision < 4) {
3737 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3738 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3739 target[0] = target[1] = 52;
3740 a1[0] = a1[1] = -424;
3741 b0[0] = b0[1] = 5612;
3742 b1[0] = b1[1] = -1393;
3743 } else {
3744 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3745 for (c = 0; c < 2; c++) {
3746 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3747 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3748 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3749 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3750 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3751 }
3752 } else if (freq >= 4900 && freq < 5100) {
3753 for (c = 0; c < 2; c++) {
3754 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3755 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3756 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3757 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3758 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3759 }
3760 } else if (freq >= 5100 && freq < 5500) {
3761 for (c = 0; c < 2; c++) {
3762 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3763 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3764 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3765 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3766 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3767 }
3768 } else if (freq >= 5500) {
3769 for (c = 0; c < 2; c++) {
3770 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3771 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3772 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3773 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3774 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3775 }
3776 } else {
3777 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3778 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3779 target[0] = target[1] = 52;
3780 a1[0] = a1[1] = -424;
3781 b0[0] = b0[1] = 5612;
3782 b1[0] = b1[1] = -1393;
3783 }
3784 }
3785 /* target[0] = target[1] = nphy->tx_power_max; */
3786
3787 if (dev->phy.rev >= 3) {
3788 if (sprom->fem.ghz2.tssipos)
3789 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3790 if (dev->phy.rev >= 7) {
3791 for (c = 0; c < 2; c++) {
3792 r = c ? 0x190 : 0x170;
3793 if (b43_nphy_ipa(dev))
3794 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3795 }
3796 } else {
3797 if (b43_nphy_ipa(dev)) {
3798 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3799 b43_radio_write(dev,
3800 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3801 b43_radio_write(dev,
3802 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3803 } else {
3804 b43_radio_write(dev,
3805 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3806 b43_radio_write(dev,
3807 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3808 }
3809 }
3810 }
3811
3812 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3813 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3814 b43_read32(dev, B43_MMIO_MACCTL);
3815 udelay(1);
3816 }
3817
303415e2
RM		 3818 if (phy->rev >= 19) {
3819 /* TODO */
3820 } else if (phy->rev >= 7) {
d3fd8bf7
RM		 3821 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3822 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3823 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3824 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3825 } else {
3826 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3827 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3828 if (dev->phy.rev > 1)
3829 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3830 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3831 }
3832
3833 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3834 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3835
3836 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3837 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3838 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3839 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3840 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3841 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3842 B43_NPHY_TXPCTL_ITSSI_BINF);
3843 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3844 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3845 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3846
3847 for (c = 0; c < 2; c++) {
3848 for (i = 0; i < 64; i++) {
3849 num = 8 * (16 * b0[c] + b1[c] * i);
3850 den = 32768 + a1[c] * i;
3851 pwr = max((4 * num + den / 2) / den, -8);
3852 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3853 pwr = max(pwr, target[c] + 1);
3854 regval[i] = pwr;
3855 }
3856 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3857 }
3858
3859 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3860 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3861 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3862
3863 if (nphy->hang_avoid)
3864 b43_nphy_stay_in_carrier_search(dev, false);
3865}
3866
0eff8fcd
RM		 3867static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3868{
3869 struct b43_phy *phy = &dev->phy;
67cbc3ed 3870
0eff8fcd 3871 const u32 *table = NULL;
0eff8fcd
RM		 3872 u32 rfpwr_offset;
3873 u8 pga_gain;
3874 int i;
0eff8fcd 3875
aeab5751 3876 table = b43_nphy_get_tx_gain_table(dev);
7ef5cd24
RM		 3877 if (!table)
3878 return;
3879
0eff8fcd
RM		 3880 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3881 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3882
303415e2
RM		 3883 if (phy->rev < 3)
3884 return;
3885
0eff8fcd 3886#if 0
303415e2 3887 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3888#endif
0eff8fcd 3889
303415e2
RM		 3890 for (i = 0; i < 128; i++) {
3891 if (phy->rev >= 19) {
3892 /* TODO */
3893 return;
3894 } else if (phy->rev >= 7) {
3895 /* TODO */
3896 return;
3897 } else {
0eff8fcd
RM		 3898 pga_gain = (table[i] >> 24) & 0xF;
3899 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
303415e2 3900 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3901 else
303415e2 3902 rfpwr_offset = 0; /* FIXME */
0eff8fcd 3903 }
303415e2
RM		 3904
3905 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset);
3906 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset);
67cbc3ed
RM		 3907 }
3908}
3909
e50cbcf6
RM		 3910/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3911static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3912{
e50cbcf6
RM		 3913 struct b43_phy_n *nphy = dev->phy.n;
3914 enum ieee80211_band band;
3915 u16 tmp;
95b66bad 3916
e50cbcf6
RM		 3917 if (!enable) {
3918 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3919 B43_NPHY_RFCTL_INTC1);
3920 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3921 B43_NPHY_RFCTL_INTC2);
3922 band = b43_current_band(dev->wl);
303415e2
RM		 3923 if (dev->phy.rev >= 7) {
3924 /* TODO */
3925 return;
3926 } else if (dev->phy.rev >= 3) {
e50cbcf6
RM		 3927 if (band == IEEE80211_BAND_5GHZ)
3928 tmp = 0x600;
3929 else
3930 tmp = 0x480;
3931 } else {
3932 if (band == IEEE80211_BAND_5GHZ)
3933 tmp = 0x180;
3934 else
3935 tmp = 0x120;
3936 }
3937 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3938 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3939 } else {
3940 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3941 nphy->rfctrl_intc1_save);
3942 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3943 nphy->rfctrl_intc2_save);
95b66bad 3944 }
95b66bad
MB		 3945}
3946
8ac3a2aa
RM		 3947/*
3948 * TX low-pass filter bandwidth setup
3949 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw
3950 */
3951static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev)
3c95627d
RM		 3952{
3953 u16 tmp;
3c95627d 3954
8ac3a2aa
RM		 3955 if (dev->phy.rev < 3 || dev->phy.rev >= 7)
3956 return;
76b002bd 3957
8ac3a2aa
RM		 3958 if (b43_nphy_ipa(dev))
3959 tmp = b43_is_40mhz(dev) ? 5 : 4;
3960 else
3961 tmp = b43_is_40mhz(dev) ? 3 : 1;
3962 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3963 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
3964
3965 if (b43_nphy_ipa(dev)) {
3966 tmp = b43_is_40mhz(dev) ? 4 : 1;
fe3e46e8 3967 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
8ac3a2aa 3968 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp);
fe3e46e8
RM		 3969 }
3970}
76b002bd 3971
2faa6b83
RM		 3972/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3973static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3974 u16 samps, u8 time, bool wait)
3c95627d 3975{
2faa6b83
RM		 3976 int i;
3977 u16 tmp;
3c95627d 3978
2faa6b83
RM		 3979 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3980 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3981 if (wait)
3982 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3983 else
2faa6b83 3984 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3985
2faa6b83 3986 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3987
2faa6b83
RM		 3988 for (i = 1000; i; i--) {
3989 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3990 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3991 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3992 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3993 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3994 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3995 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3996 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3997
2faa6b83
RM		 3998 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3999 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
4000 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
4001 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
4002 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
4003 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
4004 return;
3c95627d 4005 }
2faa6b83 4006 udelay(10);
3c95627d 4007 }
2faa6b83 4008 memset(est, 0, sizeof(*est));
3c95627d
RM		 4009}
4010
a67162ab
RM		 4011/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
4012static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
4013 struct b43_phy_n_iq_comp *pcomp)
99b82c41 4014{
a67162ab
RM		 4015 if (write) {
4016 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4017 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4018 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4019 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 4020 } else {
a67162ab
RM		 4021 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
4022 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
4023 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
4024 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
4025 }
4026}
6e3b15a9 4027
c7455cf9
RM		 4028#if 0
4029/* Ready but not used anywhere */
026816fc
RM		 4030/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
4031static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4032{
4033 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 4034
026816fc
RM		 4035 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4036 if (core == 0) {
4037 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4038 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4039 } else {
4040 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4041 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4042 }
4043 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4044 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4045 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4046 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4047 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4048 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4049 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4050 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4051}
6e3b15a9 4052
026816fc
RM		 4053/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
4054static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4055{
4056 u8 rxval, txval;
4057 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 4058
026816fc
RM		 4059 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4060 if (core == 0) {
4061 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4062 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4063 } else {
4064 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4065 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4066 }
4067 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4068 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4069 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4070 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4071 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4072 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4073 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4074 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 4075
026816fc
RM		 4076 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4077 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 4078
acd82aa8
LF		 4079 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4080 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 4081 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4082 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4083 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
4084 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4085 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
4086 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4087 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 4088
026816fc
RM		 4089 if (core == 0) {
4090 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4091 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4092 } else {
4093 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4094 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4095 }
6e3b15a9 4096
89e43dad 4097 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 4098 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 4099 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 4100
026816fc
RM		 4101 if (core == 0) {
4102 rxval = 1;
4103 txval = 8;
4104 } else {
4105 rxval = 4;
4106 txval = 2;
6e3b15a9 4107 }
89e43dad
RM		 4108 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4109 core + 1);
4110 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4111 2 - core);
99b82c41 4112}
c7455cf9 4113#endif
99b82c41 4114
34a56f2c
RM		 4115/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
4116static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 4117{
4118 int i;
34a56f2c
RM		 4119 s32 iq;
4120 u32 ii;
4121 u32 qq;
4122 int iq_nbits, qq_nbits;
4123 int arsh, brsh;
4124 u16 tmp, a, b;
4125
4126 struct nphy_iq_est est;
4127 struct b43_phy_n_iq_comp old;
4128 struct b43_phy_n_iq_comp new = { };
4129 bool error = false;
4130
4131 if (mask == 0)
4132 return;
4133
4134 b43_nphy_rx_iq_coeffs(dev, false, &old);
4135 b43_nphy_rx_iq_coeffs(dev, true, &new);
4136 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
4137 new = old;
4138
dfb4aa5d 4139 for (i = 0; i < 2; i++) {
34a56f2c
RM		 4140 if (i == 0 && (mask & 1)) {
4141 iq = est.iq0_prod;
4142 ii = est.i0_pwr;
4143 qq = est.q0_pwr;
4144 } else if (i == 1 && (mask & 2)) {
4145 iq = est.iq1_prod;
4146 ii = est.i1_pwr;
4147 qq = est.q1_pwr;
dfb4aa5d 4148 } else {
34a56f2c 4149 continue;
dfb4aa5d 4150 }
dfb4aa5d 4151
34a56f2c
RM		 4152 if (ii + qq < 2) {
4153 error = true;
4154 break;
4155 }
dfb4aa5d 4156
34a56f2c
RM		 4157 iq_nbits = fls(abs(iq));
4158 qq_nbits = fls(qq);
dfb4aa5d 4159
34a56f2c
RM		 4160 arsh = iq_nbits - 20;
4161 if (arsh >= 0) {
4162 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
4163 tmp = ii >> arsh;
4164 } else {
4165 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
4166 tmp = ii << -arsh;
4167 }
4168 if (tmp == 0) {
4169 error = true;
4170 break;
4171 }
4172 a /= tmp;
dfb4aa5d 4173
34a56f2c
RM		 4174 brsh = qq_nbits - 11;
4175 if (brsh >= 0) {
4176 b = (qq << (31 - qq_nbits));
4177 tmp = ii >> brsh;
dfb4aa5d 4178 } else {
34a56f2c
RM		 4179 b = (qq << (31 - qq_nbits));
4180 tmp = ii << -brsh;
4181 }
4182 if (tmp == 0) {
4183 error = true;
4184 break;
dfb4aa5d 4185 }
34a56f2c 4186 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 4187
34a56f2c
RM		 4188 if (i == 0 && (mask & 0x1)) {
4189 if (dev->phy.rev >= 3) {
4190 new.a0 = a & 0x3FF;
4191 new.b0 = b & 0x3FF;
4192 } else {
4193 new.a0 = b & 0x3FF;
4194 new.b0 = a & 0x3FF;
4195 }
4196 } else if (i == 1 && (mask & 0x2)) {
4197 if (dev->phy.rev >= 3) {
4198 new.a1 = a & 0x3FF;
4199 new.b1 = b & 0x3FF;
4200 } else {
4201 new.a1 = b & 0x3FF;
4202 new.b1 = a & 0x3FF;
4203 }
4204 }
dfb4aa5d 4205 }
dfb4aa5d 4206
34a56f2c
RM		 4207 if (error)
4208 new = old;
dfb4aa5d 4209
34a56f2c
RM		 4210 b43_nphy_rx_iq_coeffs(dev, true, &new);
4211}
dfb4aa5d 4212
09146400
RM		 4213/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
4214static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
4215{
4216 u16 array[4];
44f4008b 4217 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 4218
4219 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
4220 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
4221 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
4222 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 4223}
4224
9442e5b5
RM		 4225/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
4226static void b43_nphy_spur_workaround(struct b43_wldev *dev)
4227{
4228 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 4229
204a665b 4230 u8 channel = dev->phy.channel;
9442e5b5
RM		 4231 int tone[2] = { 57, 58 };
4232 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 4233
9442e5b5 4234 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 4235
9442e5b5
RM		 4236 if (nphy->hang_avoid)
4237 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 4238
9442e5b5
RM		 4239 if (nphy->gband_spurwar_en) {
4240 /* TODO: N PHY Adjust Analog Pfbw (7) */
bee6d4b2 4241 if (channel == 11 && b43_is_40mhz(dev))
9442e5b5
RM		 4242 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4243 else
4244 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4245 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4246 }
4247
9442e5b5
RM		 4248 if (nphy->aband_spurwar_en) {
4249 if (channel == 54) {
4250 tone[0] = 0x20;
4251 noise[0] = 0x25F;
4252 } else if (channel == 38 || channel == 102 || channel == 118) {
4253 if (0 /* FIXME */) {
4254 tone[0] = 0x20;
4255 noise[0] = 0x21F;
4256 } else {
4257 tone[0] = 0;
4258 noise[0] = 0;
90b9738d 4259 }
9442e5b5
RM		 4260 } else if (channel == 134) {
4261 tone[0] = 0x20;
4262 noise[0] = 0x21F;
4263 } else if (channel == 151) {
4264 tone[0] = 0x10;
4265 noise[0] = 0x23F;
4266 } else if (channel == 153 || channel == 161) {
4267 tone[0] = 0x30;
4268 noise[0] = 0x23F;
4269 } else {
4270 tone[0] = 0;
4271 noise[0] = 0;
90b9738d 4272 }
90b9738d 4273
9442e5b5
RM		 4274 if (!tone[0] && !noise[0])
4275 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4276 else
9442e5b5
RM		 4277 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4278 }
90b9738d 4279
9442e5b5
RM		 4280 if (nphy->hang_avoid)
4281 b43_nphy_stay_in_carrier_search(dev, 0);
4282}
90b9738d 4283
5ecab603
RM		 4284/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4285static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4286{
4287 struct b43_phy_n *nphy = dev->phy.n;
4288 int i, j;
4289 u32 tmp;
4290 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4291
5ecab603 4292 u16 buffer[7];
90b9738d 4293
5ecab603
RM		 4294 if (nphy->hang_avoid)
4295 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4296
5ecab603 4297 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4298
5ecab603
RM		 4299 for (i = 0; i < 2; i++) {
4300 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4301 (buffer[i * 2 + 1] & 0x3FF);
4302 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4303 (((i + 26) << 10) | 320));
4304 for (j = 0; j < 128; j++) {
4305 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4306 ((tmp >> 16) & 0xFFFF));
4307 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4308 (tmp & 0xFFFF));
90b9738d 4309 }
90b9738d 4310 }
90b9738d 4311
5ecab603
RM		 4312 for (i = 0; i < 2; i++) {
4313 tmp = buffer[5 + i];
4314 real_part = (tmp >> 8) & 0xFF;
4315 imag_part = (tmp & 0xFF);
4316 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4317 (((i + 26) << 10) | 448));
90b9738d 4318
5ecab603
RM		 4319 if (dev->phy.rev >= 3) {
4320 cur_real = real_part;
4321 cur_imag = imag_part;
4322 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4323 }
4cb99775 4324
5ecab603
RM		 4325 for (j = 0; j < 128; j++) {
4326 if (dev->phy.rev < 3) {
4327 cur_real = (real_part * loscale[j] + 128) >> 8;
4328 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4329 tmp = ((cur_real & 0xFF) << 8) |
4330 (cur_imag & 0xFF);
4331 }
4332 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4333 ((tmp >> 16) & 0xFFFF));
4334 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4335 (tmp & 0xFFFF));
4336 }
90b9738d 4337 }
4cb99775 4338
4cb99775 4339 if (dev->phy.rev >= 3) {
5ecab603
RM		 4340 b43_shm_write16(dev, B43_SHM_SHARED,
4341 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4342 b43_shm_write16(dev, B43_SHM_SHARED,
4343 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4344 }
90b9738d 4345
5ecab603
RM		 4346 if (nphy->hang_avoid)
4347 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4348}
4349
42e1547e
RM		 4350/*
4351 * Restore RSSI Calibration
4352 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4353 */
4354static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4355{
4356 struct b43_phy_n *nphy = dev->phy.n;
4357
4358 u16 *rssical_radio_regs = NULL;
4359 u16 *rssical_phy_regs = NULL;
4360
4361 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4362 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4363 return;
4364 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4365 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4366 } else {
204a665b 4367 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4368 return;
4369 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4370 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4371 }
4372
303415e2
RM		 4373 if (dev->phy.rev >= 19) {
4374 /* TODO */
4375 } else if (dev->phy.rev >= 7) {
4376 /* TODO */
9a98979e
RM		 4377 } else {
4378 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4379 rssical_radio_regs[0]);
4380 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4381 rssical_radio_regs[1]);
4382 }
42e1547e
RM		 4383
4384 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4385 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4386 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4387 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4388
4389 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4390 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4391 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4392 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4393
4394 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4395 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4396 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4397 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4398}
4399
303415e2
RM		 4400static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev)
4401{
4402 /* TODO */
4403}
4404
4405static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev)
4406{
4407 /* TODO */
4408}
4409
c4a92003
RM		 4410/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4411static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4412{
303415e2 4413 struct b43_phy *phy = &dev->phy;
c4a92003
RM		 4414 struct b43_phy_n *nphy = dev->phy.n;
4415 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4416 u16 tmp;
4417 u8 offset, i;
c4a92003 4418
303415e2
RM		 4419 if (phy->rev >= 19) {
4420 b43_nphy_tx_cal_radio_setup_rev19(dev);
4421 } else if (phy->rev >= 7) {
4422 b43_nphy_tx_cal_radio_setup_rev7(dev);
4423 } else if (phy->rev >= 3) {
52cb5e97
RM		 4424 for (i = 0; i < 2; i++) {
4425 tmp = (i == 0) ? 0x2000 : 0x3000;
4426 offset = i * 11;
4427
0c201cfb
RM		 4428 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4429 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4430 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4431 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4432 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4433 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4434 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4435 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4436 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4437 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4438 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4439
4440 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4441 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4442 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4443 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4444 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4445 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4446 if (nphy->ipa5g_on) {
0c201cfb
RM		 4447 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4448 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4449 } else {
0c201cfb
RM		 4450 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4451 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4452 }
0c201cfb 4453 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4454 } else {
0c201cfb
RM		 4455 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4456 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4457 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4458 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4459 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4460 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4461 if (nphy->ipa2g_on) {
0c201cfb
RM		 4462 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4463 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4464 (dev->phy.rev < 5) ? 0x11 : 0x01);
4465 } else {
0c201cfb
RM		 4466 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4467 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4468 }
4469 }
0c201cfb
RM		 4470 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4471 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4472 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4473 }
c4a92003 4474 } else {
0c201cfb
RM		 4475 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4476 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4477
0c201cfb
RM		 4478 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4479 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4480
0c201cfb
RM		 4481 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4482 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4483
0c201cfb
RM		 4484 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4485 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4486
0c201cfb
RM		 4487 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4488 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4489
4490 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4491 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4492 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4493 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4494 } else {
0c201cfb
RM		 4495 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4496 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4497 }
4498
4499 if (dev->phy.rev < 2) {
4500 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4501 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4502 } else {
4503 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4504 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4505 }
4506 }
4507}
4508
de7ed0c6
RM		 4509/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4510static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4511{
4512 struct b43_phy_n *nphy = dev->phy.n;
4513 int i;
4514 u16 scale, entry;
4515
4516 u16 tmp = nphy->txcal_bbmult;
4517 if (core == 0)
4518 tmp >>= 8;
4519 tmp &= 0xff;
4520
4521 for (i = 0; i < 18; i++) {
4522 scale = (ladder_lo[i].percent * tmp) / 100;
4523 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4524 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4525
4526 scale = (ladder_iq[i].percent * tmp) / 100;
4527 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4528 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4529 }
4530}
4531
45ca697e
RM		 4532/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4533static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4534{
4535 int i;
4536 for (i = 0; i < 15; i++)
4537 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4538 tbl_tx_filter_coef_rev4[2][i]);
4539}
4540
4541/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4542static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4543{
4544 int i, j;
4545 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4546 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4547
4548 for (i = 0; i < 3; i++)
4549 for (j = 0; j < 15; j++)
4550 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4551 tbl_tx_filter_coef_rev4[i][j]);
4552
bee6d4b2 4553 if (b43_is_40mhz(dev)) {
45ca697e
RM		 4554 for (j = 0; j < 15; j++)
4555 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4556 tbl_tx_filter_coef_rev4[3][j]);
4557 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4558 for (j = 0; j < 15; j++)
4559 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4560 tbl_tx_filter_coef_rev4[5][j]);
4561 }
4562
4563 if (dev->phy.channel == 14)
4564 for (j = 0; j < 15; j++)
4565 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4566 tbl_tx_filter_coef_rev4[6][j]);
4567}
4568
b0022e15
RM		 4569/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4570static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4571{
4572 struct b43_phy_n *nphy = dev->phy.n;
4573
4574 u16 curr_gain[2];
4575 struct nphy_txgains target;
4576 const u32 *table = NULL;
4577
161d540c 4578 if (!nphy->txpwrctrl) {
b0022e15
RM		 4579 int i;
4580
4581 if (nphy->hang_avoid)
4582 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4583 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4584 if (nphy->hang_avoid)
4585 b43_nphy_stay_in_carrier_search(dev, false);
4586
4587 for (i = 0; i < 2; ++i) {
4588 if (dev->phy.rev >= 3) {
4589 target.ipa[i] = curr_gain[i] & 0x000F;
4590 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4591 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4592 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4593 } else {
4594 target.ipa[i] = curr_gain[i] & 0x0003;
4595 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4596 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4597 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4598 }
4599 }
4600 } else {
4601 int i;
4602 u16 index[2];
4603 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4604 B43_NPHY_TXPCTL_STAT_BIDX) >>
4605 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4606 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4607 B43_NPHY_TXPCTL_STAT_BIDX) >>
4608 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4609
4610 for (i = 0; i < 2; ++i) {
aeab5751 4611 table = b43_nphy_get_tx_gain_table(dev);
7ef5cd24
RM		 4612 if (!table)
4613 break;
4614
b0022e15 4615 if (dev->phy.rev >= 3) {
b0022e15
RM		 4616 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4617 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4618 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4619 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4620 } else {
b0022e15
RM		 4621 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4622 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4623 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4624 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4625 }
4626 }
4627 }
4628
4629 return target;
4630}
4631
e53de674
RM		 4632/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4633static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4634{
4635 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4636
4637 if (dev->phy.rev >= 3) {
4638 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4639 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4640 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4641 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4642 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4643 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4644 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4645 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4646 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4647 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4648 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4649 b43_nphy_reset_cca(dev);
4650 } else {
4651 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4652 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4653 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4654 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4655 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4656 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4657 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4658 }
4659}
4660
4661/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4662static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4663{
303415e2 4664 struct b43_phy *phy = &dev->phy;
e53de674
RM		 4665 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4666 u16 tmp;
4667
4668 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4669 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4670 if (dev->phy.rev >= 3) {
4671 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4672 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4673
4674 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4675 regs[2] = tmp;
4676 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4677
4678 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4679 regs[3] = tmp;
4680 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4681
4682 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4683 b43_phy_mask(dev, B43_NPHY_BBCFG,
4684 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4685
c643a66e 4686 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4687 regs[5] = tmp;
d41a3552 4688 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4689
4690 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4691 regs[6] = tmp;
d41a3552 4692 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4693 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4694 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4695
89e43dad
RM		 4696 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4697 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4698 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4699
4700 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4701 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4702 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4703 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
303415e2
RM		 4704
4705 if (phy->rev >= 19)
4706 ; /* TODO */
4707 else if (phy->rev >= 7)
4708 ; /* TODO */
4709
4710 if (0 /* FIXME */) {
4711 if (phy->rev >= 19) {
4712 /* TODO */
4713 } else if (phy->rev >= 8) {
4714 /* TODO */
4715 } else if (phy->rev == 7) {
4716 /* TODO */
4717 }
4718 }
e53de674
RM		 4719 } else {
4720 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4721 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4722 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4723 regs[2] = tmp;
4724 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4725 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4726 regs[3] = tmp;
4727 tmp |= 0x2000;
d41a3552 4728 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4729 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4730 regs[4] = tmp;
4731 tmp |= 0x2000;
d41a3552 4732 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4733 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4734 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4735 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4736 tmp = 0x0180;
4737 else
4738 tmp = 0x0120;
4739 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4740 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4741 }
4742}
4743
bbc6dc12
RM		 4744/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4745static void b43_nphy_save_cal(struct b43_wldev *dev)
4746{
303415e2 4747 struct b43_phy *phy = &dev->phy;
bbc6dc12
RM		 4748 struct b43_phy_n *nphy = dev->phy.n;
4749
4750 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4751 u16 *txcal_radio_regs = NULL;
902db91d 4752 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4753 u16 *table = NULL;
4754
4755 if (nphy->hang_avoid)
4756 b43_nphy_stay_in_carrier_search(dev, 1);
4757
4758 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4759 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4760 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4761 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4762 table = nphy->cal_cache.txcal_coeffs_2G;
4763 } else {
4764 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4765 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4766 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4767 table = nphy->cal_cache.txcal_coeffs_5G;
4768 }
4769
4770 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4771 /* TODO use some definitions */
303415e2
RM		 4772 if (phy->rev >= 19) {
4773 /* TODO */
4774 } else if (phy->rev >= 7) {
4775 /* TODO */
4776 } else if (phy->rev >= 3) {
bbc6dc12
RM		 4777 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4778 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4779 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4780 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4781 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4782 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4783 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4784 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4785 } else {
4786 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4787 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4788 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4789 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4790 }
39e971ef 4791 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
427fa00b
RM		 4792 iqcal_chanspec->channel_type =
4793 cfg80211_get_chandef_type(dev->phy.chandef);
5818e989 4794 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4795
4796 if (nphy->hang_avoid)
4797 b43_nphy_stay_in_carrier_search(dev, 0);
4798}
4799
2f258b74
RM		 4800/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4801static void b43_nphy_restore_cal(struct b43_wldev *dev)
4802{
303415e2 4803 struct b43_phy *phy = &dev->phy;
2f258b74
RM		 4804 struct b43_phy_n *nphy = dev->phy.n;
4805
4806 u16 coef[4];
4807 u16 *loft = NULL;
4808 u16 *table = NULL;
4809
4810 int i;
4811 u16 *txcal_radio_regs = NULL;
4812 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4813
4814 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4815 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4816 return;
4817 table = nphy->cal_cache.txcal_coeffs_2G;
4818 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4819 } else {
204a665b 4820 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4821 return;
4822 table = nphy->cal_cache.txcal_coeffs_5G;
4823 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4824 }
4825
2581b143 4826 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4827
4828 for (i = 0; i < 4; i++) {
4829 if (dev->phy.rev >= 3)
4830 table[i] = coef[i];
4831 else
4832 coef[i] = 0;
4833 }
4834
2581b143
RM		 4835 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4836 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4837 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4838
4839 if (dev->phy.rev < 2)
4840 b43_nphy_tx_iq_workaround(dev);
4841
4842 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4843 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4844 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4845 } else {
4846 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4847 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4848 }
4849
4850 /* TODO use some definitions */
303415e2
RM		 4851 if (phy->rev >= 19) {
4852 /* TODO */
4853 } else if (phy->rev >= 7) {
4854 /* TODO */
4855 } else if (phy->rev >= 3) {
2f258b74
RM		 4856 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4857 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4858 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4859 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4860 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4861 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4862 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4863 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4864 } else {
4865 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4866 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4867 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4868 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4869 }
4870 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4871}
4872
fb43b8e2
RM		 4873/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4874static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4875 struct nphy_txgains target,
4876 bool full, bool mphase)
4877{
39e971ef 4878 struct b43_phy *phy = &dev->phy;
fb43b8e2
RM		 4879 struct b43_phy_n *nphy = dev->phy.n;
4880 int i;
4881 int error = 0;
4882 int freq;
4883 bool avoid = false;
4884 u8 length;
fb23d863 4885 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4886 const u16 *table;
4887 bool phy6or5x;
4888
4889 u16 buffer[11];
4890 u16 diq_start = 0;
4891 u16 save[2];
4892 u16 gain[2];
4893 struct nphy_iqcal_params params[2];
4894 bool updated[2] = { };
4895
4896 b43_nphy_stay_in_carrier_search(dev, true);
4897
4898 if (dev->phy.rev >= 4) {
4899 avoid = nphy->hang_avoid;
3db1cd5c 4900 nphy->hang_avoid = false;
fb43b8e2
RM		 4901 }
4902
9145834e 4903 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4904
4905 for (i = 0; i < 2; i++) {
4906 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4907 gain[i] = params[i].cal_gain;
4908 }
2581b143
RM		 4909
4910 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4911
4912 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4913 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4914
4915 phy6or5x = dev->phy.rev >= 6 ||
4916 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4917 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4918 if (phy6or5x) {
bee6d4b2 4919 if (b43_is_40mhz(dev)) {
38bb9029
RM		 4920 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4921 tbl_tx_iqlo_cal_loft_ladder_40);
4922 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4923 tbl_tx_iqlo_cal_iqimb_ladder_40);
4924 } else {
4925 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4926 tbl_tx_iqlo_cal_loft_ladder_20);
4927 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4928 tbl_tx_iqlo_cal_iqimb_ladder_20);
4929 }
fb43b8e2
RM		 4930 }
4931
303415e2
RM		 4932 if (phy->rev >= 19) {
4933 /* TODO */
4934 } else if (phy->rev >= 7) {
4935 /* TODO */
4936 } else {
4937 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4938 }
fb43b8e2 4939
bee6d4b2 4940 if (!b43_is_40mhz(dev))
fb43b8e2
RM		 4941 freq = 2500;
4942 else
4943 freq = 5000;
4944
4945 if (nphy->mphase_cal_phase_id > 2)
bee6d4b2 4946 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
ed03033e 4947 0xFFFF, 0, true, false, false);
fb43b8e2 4948 else
ed03033e 4949 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false);
fb43b8e2
RM		 4950
4951 if (error == 0) {
4952 if (nphy->mphase_cal_phase_id > 2) {
4953 table = nphy->mphase_txcal_bestcoeffs;
4954 length = 11;
4955 if (dev->phy.rev < 3)
4956 length -= 2;
4957 } else {
4958 if (!full && nphy->txiqlocal_coeffsvalid) {
4959 table = nphy->txiqlocal_bestc;
4960 length = 11;
4961 if (dev->phy.rev < 3)
4962 length -= 2;
4963 } else {
4964 full = true;
4965 if (dev->phy.rev >= 3) {
4966 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4967 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4968 } else {
4969 table = tbl_tx_iqlo_cal_startcoefs;
4970 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4971 }
4972 }
4973 }
4974
2581b143 4975 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4976
4977 if (full) {
4978 if (dev->phy.rev >= 3)
4979 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4980 else
4981 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4982 } else {
4983 if (dev->phy.rev >= 3)
4984 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4985 else
4986 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4987 }
4988
4989 if (mphase) {
4990 count = nphy->mphase_txcal_cmdidx;
4991 numb = min(max,
4992 (u16)(count + nphy->mphase_txcal_numcmds));
4993 } else {
4994 count = 0;
4995 numb = max;
4996 }
4997
4998 for (; count < numb; count++) {
4999 if (full) {
5000 if (dev->phy.rev >= 3)
5001 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
5002 else
5003 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
5004 } else {
5005 if (dev->phy.rev >= 3)
5006 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
5007 else
5008 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
5009 }
5010
5011 core = (cmd & 0x3000) >> 12;
5012 type = (cmd & 0x0F00) >> 8;
5013
5014 if (phy6or5x && updated[core] == 0) {
5015 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 5016 updated[core] = true;
fb43b8e2
RM		 5017 }
5018
5019 tmp = (params[core].ncorr[type] << 8) | 0x66;
5020 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
5021
5022 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 5023 buffer[0] = b43_ntab_read(dev,
5024 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 5025 diq_start = buffer[0];
5026 buffer[0] = 0;
d41a3552
RM		 5027 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
5028 0);
fb43b8e2
RM		 5029 }
5030
5031 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
5032 for (i = 0; i < 2000; i++) {
5033 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
5034 if (tmp & 0xC000)
5035 break;
5036 udelay(10);
5037 }
5038
9145834e
RM		 5039 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5040 buffer);
2581b143
RM		 5041 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
5042 buffer);
fb43b8e2
RM		 5043
5044 if (type == 1 || type == 3 || type == 4)
5045 buffer[0] = diq_start;
5046 }
5047
5048 if (mphase)
5049 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
5050
5051 last = (dev->phy.rev < 3) ? 6 : 7;
5052
5053 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 5054 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 5055 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 5056 if (dev->phy.rev < 3) {
5057 buffer[0] = 0;
5058 buffer[1] = 0;
5059 buffer[2] = 0;
5060 buffer[3] = 0;
5061 }
2581b143
RM		 5062 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5063 buffer);
bc53e512 5064 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 5065 buffer);
5066 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5067 buffer);
5068 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5069 buffer);
fb43b8e2
RM		 5070 length = 11;
5071 if (dev->phy.rev < 3)
5072 length -= 2;
9145834e
RM		 5073 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5074 nphy->txiqlocal_bestc);
fb43b8e2 5075 nphy->txiqlocal_coeffsvalid = true;
204a665b 5076 nphy->txiqlocal_chanspec.center_freq =
39e971ef 5077 phy->chandef->chan->center_freq;
204a665b 5078 nphy->txiqlocal_chanspec.channel_type =
427fa00b 5079 cfg80211_get_chandef_type(phy->chandef);
fb43b8e2
RM		 5080 } else {
5081 length = 11;
5082 if (dev->phy.rev < 3)
5083 length -= 2;
9145834e
RM		 5084 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
5085 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 5086 }
5087
53ae8e8c 5088 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 5089 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
5090 }
5091
e53de674 5092 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 5093 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 5094
5095 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5096 b43_nphy_tx_iq_workaround(dev);
5097
5098 if (dev->phy.rev >= 4)
5099 nphy->hang_avoid = avoid;
5100
5101 b43_nphy_stay_in_carrier_search(dev, false);
5102
5103 return error;
5104}
5105
984ff4ff
RM		 5106/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
5107static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
5108{
5109 struct b43_phy_n *nphy = dev->phy.n;
5110 u8 i;
5111 u16 buffer[7];
5112 bool equal = true;
5113
902db91d 5114 if (!nphy->txiqlocal_coeffsvalid ||
39e971ef 5115 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
427fa00b 5116 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef))
984ff4ff
RM		 5117 return;
5118
5119 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
5120 for (i = 0; i < 4; i++) {
5121 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
5122 equal = false;
5123 break;
5124 }
5125 }
5126
5127 if (!equal) {
5128 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
5129 nphy->txiqlocal_bestc);
5130 for (i = 0; i < 4; i++)
5131 buffer[i] = 0;
5132 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
5133 buffer);
5134 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
5135 &nphy->txiqlocal_bestc[5]);
5136 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
5137 &nphy->txiqlocal_bestc[5]);
5138 }
5139}
5140
15931e31
RM		 5141/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
5142static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
5143 struct nphy_txgains target, u8 type, bool debug)
5144{
5145 struct b43_phy_n *nphy = dev->phy.n;
5146 int i, j, index;
5147 u8 rfctl[2];
5148 u8 afectl_core;
5149 u16 tmp[6];
c7455cf9 5150 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 5151 u32 real, imag;
5152 enum ieee80211_band band;
5153
5154 u8 use;
5155 u16 cur_hpf;
5156 u16 lna[3] = { 3, 3, 1 };
5157 u16 hpf1[3] = { 7, 2, 0 };
5158 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 5159 u32 power[3] = { };
15931e31
RM		 5160 u16 gain_save[2];
5161 u16 cal_gain[2];
5162 struct nphy_iqcal_params cal_params[2];
5163 struct nphy_iq_est est;
5164 int ret = 0;
5165 bool playtone = true;
5166 int desired = 13;
5167
5168 b43_nphy_stay_in_carrier_search(dev, 1);
5169
5170 if (dev->phy.rev < 2)
984ff4ff 5171 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 5172 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5173 for (i = 0; i < 2; i++) {
5174 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
5175 cal_gain[i] = cal_params[i].cal_gain;
5176 }
2581b143 5177 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 5178
5179 for (i = 0; i < 2; i++) {
5180 if (i == 0) {
5181 rfctl[0] = B43_NPHY_RFCTL_INTC1;
5182 rfctl[1] = B43_NPHY_RFCTL_INTC2;
5183 afectl_core = B43_NPHY_AFECTL_C1;
5184 } else {
5185 rfctl[0] = B43_NPHY_RFCTL_INTC2;
5186 rfctl[1] = B43_NPHY_RFCTL_INTC1;
5187 afectl_core = B43_NPHY_AFECTL_C2;
5188 }
5189
5190 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
5191 tmp[2] = b43_phy_read(dev, afectl_core);
5192 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
5193 tmp[4] = b43_phy_read(dev, rfctl[0]);
5194 tmp[5] = b43_phy_read(dev, rfctl[1]);
5195
5196 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 5197 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 5198 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
5199 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
5200 (1 - i));
5201 b43_phy_set(dev, afectl_core, 0x0006);
5202 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
5203
5204 band = b43_current_band(dev->wl);
5205
5206 if (nphy->rxcalparams & 0xFF000000) {
5207 if (band == IEEE80211_BAND_5GHZ)
5208 b43_phy_write(dev, rfctl[0], 0x140);
5209 else
5210 b43_phy_write(dev, rfctl[0], 0x110);
5211 } else {
5212 if (band == IEEE80211_BAND_5GHZ)
5213 b43_phy_write(dev, rfctl[0], 0x180);
5214 else
5215 b43_phy_write(dev, rfctl[0], 0x120);
5216 }
5217
5218 if (band == IEEE80211_BAND_5GHZ)
5219 b43_phy_write(dev, rfctl[1], 0x148);
5220 else
5221 b43_phy_write(dev, rfctl[1], 0x114);
5222
5223 if (nphy->rxcalparams & 0x10000) {
5224 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
5225 (i + 1));
5226 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
5227 (2 - i));
5228 }
5229
30115c22 5230 for (j = 0; j < 4; j++) {
15931e31
RM		 5231 if (j < 3) {
5232 cur_lna = lna[j];
5233 cur_hpf1 = hpf1[j];
5234 cur_hpf2 = hpf2[j];
5235 } else {
5236 if (power[1] > 10000) {
5237 use = 1;
5238 cur_hpf = cur_hpf1;
5239 index = 2;
5240 } else {
5241 if (power[0] > 10000) {
5242 use = 1;
5243 cur_hpf = cur_hpf1;
5244 index = 1;
5245 } else {
5246 index = 0;
5247 use = 2;
5248 cur_hpf = cur_hpf2;
5249 }
5250 }
5251 cur_lna = lna[index];
5252 cur_hpf1 = hpf1[index];
5253 cur_hpf2 = hpf2[index];
5254 cur_hpf += desired - hweight32(power[index]);
5255 cur_hpf = clamp_val(cur_hpf, 0, 10);
5256 if (use == 1)
5257 cur_hpf1 = cur_hpf;
5258 else
5259 cur_hpf2 = cur_hpf;
5260 }
5261
5262 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
5263 (cur_lna << 2));
78ae7532 5264 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 5265 false);
de9a47f9 5266 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 5267 b43_nphy_stop_playback(dev);
15931e31
RM		 5268
5269 if (playtone) {
59af099b
RM		 5270 ret = b43_nphy_tx_tone(dev, 4000,
5271 (nphy->rxcalparams & 0xFFFF),
ed03033e 5272 false, false, true);
15931e31
RM		 5273 playtone = false;
5274 } else {
ed03033e
RM		 5275 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false,
5276 false, true);
15931e31
RM		 5277 }
5278
5279 if (ret == 0) {
5280 if (j < 3) {
5281 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
5282 false);
5283 if (i == 0) {
5284 real = est.i0_pwr;
5285 imag = est.q0_pwr;
5286 } else {
5287 real = est.i1_pwr;
5288 imag = est.q1_pwr;
5289 }
5290 power[i] = ((real + imag) / 1024) + 1;
5291 } else {
5292 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
5293 }
53ae8e8c 5294 b43_nphy_stop_playback(dev);
15931e31
RM		 5295 }
5296
5297 if (ret != 0)
5298 break;
5299 }
5300
5301 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5302 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5303 b43_phy_write(dev, rfctl[1], tmp[5]);
5304 b43_phy_write(dev, rfctl[0], tmp[4]);
5305 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5306 b43_phy_write(dev, afectl_core, tmp[2]);
5307 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5308
5309 if (ret != 0)
5310 break;
5311 }
5312
78ae7532 5313 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5314 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5315 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5316
5317 b43_nphy_stay_in_carrier_search(dev, 0);
5318
5319 return ret;
5320}
5321
5322static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5323 struct nphy_txgains target, u8 type, bool debug)
5324{
5325 return -1;
5326}
5327
5328/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5329static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5330 struct nphy_txgains target, u8 type, bool debug)
5331{
303415e2
RM		 5332 if (dev->phy.rev >= 7)
5333 type = 0;
5334
15931e31
RM		 5335 if (dev->phy.rev >= 3)
5336 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5337 else
5338 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5339}
5340
4e687b22
GS		 5341/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5342static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5343{
5344 struct b43_phy *phy = &dev->phy;
5345 struct b43_phy_n *nphy = phy->n;
0b81c23d 5346 /* u16 buf[16]; it's rev3+ */
4e687b22 5347
049fbfee
RM		 5348 nphy->phyrxchain = mask;
5349
4e687b22
GS		 5350 if (0 /* FIXME clk */)
5351 return;
5352
5353 b43_mac_suspend(dev);
5354
5355 if (nphy->hang_avoid)
5356 b43_nphy_stay_in_carrier_search(dev, true);
5357
5358 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5359 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5360
049fbfee 5361 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5362 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5363 if (dev->phy.rev >= 3) {
5364 /* TODO */
5365 }
5366 } else {
5367 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5368 if (dev->phy.rev >= 3) {
5369 /* TODO */
5370 }
5371 }
5372
5373 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5374
5375 if (nphy->hang_avoid)
5376 b43_nphy_stay_in_carrier_search(dev, false);
5377
5378 b43_mac_enable(dev);
5379}
5380
104cfa88
RM		 5381/**************************************************
5382 * N-PHY init
5383 **************************************************/
5384
104cfa88
RM		 5385/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5386static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5387{
5388 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5389
5390 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5391 if (preamble == 1)
5392 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5393 else
5394 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5395
5396 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5397}
5398
5399/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5400static void b43_nphy_bphy_init(struct b43_wldev *dev)
5401{
5402 unsigned int i;
5403 u16 val;
5404
5405 val = 0x1E1F;
5406 for (i = 0; i < 16; i++) {
5407 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5408 val -= 0x202;
5409 }
5410 val = 0x3E3F;
5411 for (i = 0; i < 16; i++) {
5412 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5413 val -= 0x202;
5414 }
5415 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5416}
5417
5418/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5419static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5420{
303415e2
RM		 5421 if (dev->phy.rev >= 7)
5422 return;
5423
104cfa88
RM		 5424 if (dev->phy.rev >= 3) {
5425 if (!init)
5426 return;
5427 if (0 /* FIXME */) {
5428 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5429 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5430 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5431 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5432 }
5433 } else {
5434 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5435 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5436
5437 switch (dev->dev->bus_type) {
5438#ifdef CONFIG_B43_BCMA
5439 case B43_BUS_BCMA:
5440 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5441 0xFC00, 0xFC00);
5442 break;
5443#endif
5444#ifdef CONFIG_B43_SSB
5445 case B43_BUS_SSB:
5446 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5447 0xFC00, 0xFC00);
5448 break;
5449#endif
5450 }
5451
5056635c
RM		 5452 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5453 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5454 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5455 0);
104cfa88
RM		 5456
5457 if (init) {
5458 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5459 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5460 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5461 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5462 }
5463 }
5464}
5465
5466/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5467static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5468{
0581483a 5469 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5470 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5471 struct b43_phy_n *nphy = phy->n;
5472 u8 tx_pwr_state;
5473 struct nphy_txgains target;
95b66bad 5474 u16 tmp;
0988a7a1
RM		 5475 enum ieee80211_band tmp2;
5476 bool do_rssi_cal;
5477
5478 u16 clip[2];
5479 bool do_cal = false;
95b66bad 5480
0988a7a1 5481 if ((dev->phy.rev >= 3) &&
0581483a 5482 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5483 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5484 switch (dev->dev->bus_type) {
42c9a458
RM		 5485#ifdef CONFIG_B43_BCMA
5486 case B43_BUS_BCMA:
5487 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5488 BCMA_CC_CHIPCTL, 0x40);
5489 break;
5490#endif
6cbab0d9
RM		 5491#ifdef CONFIG_B43_SSB
5492 case B43_BUS_SSB:
5493 chipco_set32(&dev->dev->sdev->bus->chipco,
5494 SSB_CHIPCO_CHIPCTL, 0x40);
5495 break;
5496#endif
5497 }
0988a7a1
RM		 5498 }
5499 nphy->deaf_count = 0;
95b66bad 5500 b43_nphy_tables_init(dev);
0988a7a1
RM		 5501 nphy->crsminpwr_adjusted = false;
5502 nphy->noisevars_adjusted = false;
95b66bad
MB		 5503
5504 /* Clear all overrides */
0988a7a1
RM		 5505 if (dev->phy.rev >= 3) {
5506 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5507 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
303415e2
RM		 5508 if (phy->rev >= 7) {
5509 /* TODO */
5510 }
5511 if (phy->rev >= 19) {
5512 /* TODO */
5513 }
5514
0988a7a1
RM		 5515 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5516 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5517 } else {
5518 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5519 }
95b66bad
MB		 5520 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5521 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5522 if (dev->phy.rev < 6) {
5523 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5524 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5525 }
95b66bad
MB		 5526 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5527 ~(B43_NPHY_RFSEQMODE_CAOVER |
5528 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5529 if (dev->phy.rev >= 3)
5530 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5531 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5532
0988a7a1
RM		 5533 if (dev->phy.rev <= 2) {
5534 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5535 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5536 ~B43_NPHY_BPHY_CTL3_SCALE,
5537 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5538 }
95b66bad
MB		 5539 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5540 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5541
0eff8fcd 5542 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5543 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5544 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5545 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5546 else
5547 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5548 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5549 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5550 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5551
303415e2
RM		 5552 if (phy->rev < 8)
5553 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5554
4f4ab6cd 5555 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5556
5557 if (phy->rev < 2) {
5558 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5559 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5560 }
0988a7a1
RM		 5561
5562 tmp2 = b43_current_band(dev->wl);
c002831a 5563 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5564 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5565 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5566 nphy->papd_epsilon_offset[0] << 7);
5567 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5568 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5569 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5570 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5571 } else if (phy->rev >= 5) {
45ca697e 5572 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5573 }
5574
95b66bad 5575 b43_nphy_workarounds(dev);
95b66bad 5576
0988a7a1 5577 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5578 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5579 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5580 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5581 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5582 b43_phy_force_clock(dev, 0);
0988a7a1 5583
858a1652 5584 b43_mac_phy_clock_set(dev, true);
0988a7a1 5585
303415e2
RM		 5586 if (phy->rev < 7) {
5587 b43_nphy_pa_override(dev, false);
5588 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5589 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5590 b43_nphy_pa_override(dev, true);
5591 }
0988a7a1 5592
bbec398c
RM		 5593 b43_nphy_classifier(dev, 0, 0);
5594 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5595 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5596 b43_nphy_bphy_init(dev);
5597
0988a7a1 5598 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5599 b43_nphy_tx_power_ctrl(dev, false);
5600 b43_nphy_tx_power_fix(dev);
3dda07b6 5601 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5602 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5603 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5604
0988a7a1 5605 if (nphy->phyrxchain != 3)
4e687b22 5606 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5607 if (nphy->mphase_cal_phase_id > 0)
5608 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5609
5610 do_rssi_cal = false;
5611 if (phy->rev >= 3) {
5612 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5613 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5614 else
204a665b 5615 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5616
5617 if (do_rssi_cal)
4cb99775 5618 b43_nphy_rssi_cal(dev);
0988a7a1 5619 else
42e1547e 5620 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5621 } else {
4cb99775 5622 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5623 }
5624
5625 if (!((nphy->measure_hold & 0x6) != 0)) {
5626 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5627 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5628 else
204a665b 5629 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5630
5631 if (nphy->mute)
5632 do_cal = false;
5633
5634 if (do_cal) {
b0022e15 5635 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5636
5637 if (nphy->antsel_type == 2)
8987a9e9 5638 b43_nphy_superswitch_init(dev, true);
0988a7a1 5639 if (nphy->perical != 2) {
90b9738d 5640 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5641 if (phy->rev >= 3) {
5642 nphy->cal_orig_pwr_idx[0] =
5643 nphy->txpwrindex[0].index_internal;
5644 nphy->cal_orig_pwr_idx[1] =
5645 nphy->txpwrindex[1].index_internal;
5646 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5647 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5648 }
e7797bf2
RM		 5649 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5650 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5651 b43_nphy_save_cal(dev);
5652 } else if (nphy->mphase_cal_phase_id == 0)
5653 ;/* N PHY Periodic Calibration with arg 3 */
5654 } else {
5655 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5656 }
5657 }
5658
6dcd9d91 5659 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5660 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5661 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5662 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5663 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5664 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
8ac3a2aa 5665 b43_nphy_tx_lpf_bw(dev);
9442e5b5
RM		 5666 if (phy->rev >= 3)
5667 b43_nphy_spur_workaround(dev);
95b66bad 5668
53a6e234 5669 return 0;
424047e6 5670}
ef1a628d 5671
104cfa88
RM		 5672/**************************************************
5673 * Channel switching ops.
5674 **************************************************/
5675
5676static void b43_chantab_phy_upload(struct b43_wldev *dev,
5677 const struct b43_phy_n_sfo_cfg *e)
5678{
5679 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5680 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5681 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5682 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5683 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5684 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5685}
5686
49d55cef
RM		 5687/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5688static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5689{
d66be829
RM		 5690 switch (dev->dev->bus_type) {
5691#ifdef CONFIG_B43_BCMA
5692 case B43_BUS_BCMA:
9b383672
HM		 5693 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5694 avoid);
d66be829 5695 break;
8b1fdb53 5696#endif
d66be829
RM		 5697#ifdef CONFIG_B43_SSB
5698 case B43_BUS_SSB:
46fc4c90
RM		 5699 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5700 avoid);
d66be829
RM		 5701 break;
5702#endif
5703 }
49d55cef
RM		 5704}
5705
1b69ec7b 5706/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5707static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5708 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5709 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5710{
5711 struct b43_phy *phy = &dev->phy;
5712 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5713 int ch = new_channel->hw_value;
1b69ec7b 5714
087de74a 5715 u16 old_band_5ghz;
12cd43c6 5716 u16 tmp16;
1b69ec7b 5717
087de74a
RM		 5718 old_band_5ghz =
5719 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5720 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5721 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5722 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5723 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5724 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5725 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5726 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5727 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5728 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5729 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5730 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5731 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5732 }
5733
5734 b43_chantab_phy_upload(dev, e);
5735
a656b6a9 5736 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5737 b43_nphy_classifier(dev, 2, 0);
5738 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5739 } else {
5740 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5741 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5742 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5743 }
5744
161d540c 5745 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5746 b43_nphy_tx_power_fix(dev);
5747
5748 if (dev->phy.rev < 3)
5749 b43_nphy_adjust_lna_gain_table(dev);
5750
8ac3a2aa 5751 b43_nphy_tx_lpf_bw(dev);
1b69ec7b 5752
49d55cef
RM		 5753 if (dev->phy.rev >= 3 &&
5754 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5755 bool avoid = false;
5756 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5757 avoid = true;
427fa00b 5758 } else if (!b43_is_40mhz(dev)) {
49d55cef
RM		 5759 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5760 avoid = true;
5761 } else { /* 40MHz */
5762 if (nphy->aband_spurwar_en &&
5763 (ch == 38 || ch == 102 || ch == 118))
5764 avoid = dev->dev->chip_id == 0x4716;
5765 }
5766
5767 b43_nphy_pmu_spur_avoid(dev, avoid);
5768
5769 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5770 dev->dev->chip_id == 43225) {
5771 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5772 avoid ? 0x5341 : 0x8889);
5773 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5774 }
5775
5776 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5777 ; /* TODO: reset PLL */
5778
5779 if (avoid)
5780 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5781 else
5782 b43_phy_mask(dev, B43_NPHY_BBCFG,
5783 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5784
5785 b43_nphy_reset_cca(dev);
5786
5787 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5788 }
5789
5790 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5791
5792 if (phy->rev >= 3)
5793 b43_nphy_spur_workaround(dev);
5794}
5795
eff66c51 5796/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5797static int b43_nphy_set_channel(struct b43_wldev *dev,
5798 struct ieee80211_channel *channel,
5799 enum nl80211_channel_type channel_type)
eff66c51 5800{
a656b6a9 5801 struct b43_phy *phy = &dev->phy;
eff66c51 5802
2eeb6fd0
JL		 5803 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5804 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
fe255b40
RM		 5805 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL;
5806 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
eff66c51
RM		 5807
5808 u8 tmp;
eff66c51 5809
303415e2
RM		 5810 if (phy->rev >= 19) {
5811 return -ESRCH;
5812 /* TODO */
5813 } else if (phy->rev >= 7) {
fe255b40
RM		 5814 r2057_get_chantabent_rev7(dev, channel->center_freq,
5815 &tabent_r7, &tabent_r7_2g);
5816 if (!tabent_r7 && !tabent_r7_2g)
5817 return -ESRCH;
5818 } else if (phy->rev >= 3) {
f2a6d6a0
RM		 5819 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5820 channel->center_freq);
f19ebe7d
RM		 5821 if (!tabent_r3)
5822 return -ESRCH;
ffd2d9bd 5823 } else {
a656b6a9
RM		 5824 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5825 channel->hw_value);
f19ebe7d 5826 if (!tabent_r2)
ffd2d9bd 5827 return -ESRCH;
eff66c51
RM		 5828 }
5829
204a665b
RM		 5830 /* Channel is set later in common code, but we need to set it on our
5831 own to let this function's subcalls work properly. */
5832 phy->channel = channel->hw_value;
eff66c51 5833
427fa00b 5834#if 0
e5c407f9
RM		 5835 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5836 b43_channel_type_is_40mhz(channel_type))
5837 ; /* TODO: BMAC BW Set (channel_type) */
427fa00b 5838#endif
eff66c51 5839
fe255b40
RM		 5840 if (channel_type == NL80211_CHAN_HT40PLUS) {
5841 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20);
5842 if (phy->rev >= 7)
5843 b43_phy_set(dev, 0x310, 0x8000);
5844 } else if (channel_type == NL80211_CHAN_HT40MINUS) {
5845 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20);
5846 if (phy->rev >= 7)
5847 b43_phy_mask(dev, 0x310, (u16)~0x8000);
5848 }
eff66c51 5849
303415e2
RM		 5850 if (phy->rev >= 19) {
5851 /* TODO */
5852 } else if (phy->rev >= 7) {
fe255b40
RM		 5853 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
5854 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
5855
5856 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
5857 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0;
5858 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp);
5859 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp);
5860 }
5861
5862 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g);
5863 b43_nphy_channel_setup(dev, phy_regs, channel);
5864 } else if (phy->rev >= 3) {
a656b6a9 5865 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5866 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5867 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5868 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5869 } else {
a656b6a9 5870 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5871 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5872 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5873 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5874 }
5875
5876 return 0;
5877}
5878
104cfa88
RM		 5879/**************************************************
5880 * Basic PHY ops.
5881 **************************************************/
5882
ef1a628d
MB		 5883static int b43_nphy_op_allocate(struct b43_wldev *dev)
5884{
5885 struct b43_phy_n *nphy;
5886
5887 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5888 if (!nphy)
5889 return -ENOMEM;
5890 dev->phy.n = nphy;
5891
ef1a628d
MB		 5892 return 0;
5893}
5894
fb11137a 5895static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5896{
fb11137a
MB		 5897 struct b43_phy *phy = &dev->phy;
5898 struct b43_phy_n *nphy = phy->n;
c7d64310 5899 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5900
fb11137a 5901 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5902
aca434d3 5903 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5904 nphy->spur_avoid = (phy->rev >= 3) ?
5905 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 5906 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5907 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5908 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5909 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5910 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5911 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5912 nphy->tx_pwr_idx[0] = 128;
5913 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5914
5915 /* Hardware TX power control and 5GHz power gain */
5916 nphy->txpwrctrl = false;
5917 nphy->pwg_gain_5ghz = false;
5918 if (dev->phy.rev >= 3 ||
5919 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5920 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5921 nphy->txpwrctrl = true;
5922 nphy->pwg_gain_5ghz = true;
5923 } else if (sprom->revision >= 4) {
5924 if (dev->phy.rev >= 2 &&
5925 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5926 nphy->txpwrctrl = true;
5927#ifdef CONFIG_B43_SSB
5928 if (dev->dev->bus_type == B43_BUS_SSB &&
5929 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5930 struct pci_dev *pdev =
5931 dev->dev->sdev->bus->host_pci;
5932 if (pdev->device == 0x4328 ||
5933 pdev->device == 0x432a)
5934 nphy->pwg_gain_5ghz = true;
5935 }
5936#endif
5937 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5938 nphy->pwg_gain_5ghz = true;
5939 }
5940 }
5941
5942 if (dev->phy.rev >= 3) {
5943 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5944 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5945 }
ef1a628d
MB		 5946}
5947
fb11137a 5948static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5949{
fb11137a
MB		 5950 struct b43_phy *phy = &dev->phy;
5951 struct b43_phy_n *nphy = phy->n;
ef1a628d 5952
ef1a628d 5953 kfree(nphy);
fb11137a
MB		 5954 phy->n = NULL;
5955}
5956
5957static int b43_nphy_op_init(struct b43_wldev *dev)
5958{
5959 return b43_phy_initn(dev);
ef1a628d
MB		 5960}
5961
5962static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5963{
5964#if B43_DEBUG
5965 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5966 /* OFDM registers are onnly available on A/G-PHYs */
5967 b43err(dev->wl, "Invalid OFDM PHY access at "
5968 "0x%04X on N-PHY\n", offset);
5969 dump_stack();
5970 }
5971 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5972 /* Ext-G registers are only available on G-PHYs */
5973 b43err(dev->wl, "Invalid EXT-G PHY access at "
5974 "0x%04X on N-PHY\n", offset);
5975 dump_stack();
5976 }
5977#endif /* B43_DEBUG */
5978}
5979
5980static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5981{
5982 check_phyreg(dev, reg);
5983 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5984 return b43_read16(dev, B43_MMIO_PHY_DATA);
5985}
5986
5987static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5988{
5989 check_phyreg(dev, reg);
5990 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5991 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5992}
5993
755fd183
RM		 5994static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5995 u16 set)
5996{
5997 check_phyreg(dev, reg);
5998 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5999 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 6000}
6001
ef1a628d
MB		 6002static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
6003{
6004 /* Register 1 is a 32-bit register. */
0933ecf9 6005 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
a6aa05d6
RM		 6006
6007 if (dev->phy.rev >= 7)
6008 reg |= 0x200; /* Radio 0x2057 */
6009 else
6010 reg |= 0x100;
ef1a628d
MB		 6011
6012 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6013 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
6014}
6015
6016static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
6017{
6018 /* Register 1 is a 32-bit register. */
0933ecf9 6019 B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
ef1a628d
MB		 6020
6021 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
6022 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
6023}
6024
c2b7aefd 6025/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 6026static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 6027 bool blocked)
c2b7aefd 6028{
303415e2
RM		 6029 struct b43_phy *phy = &dev->phy;
6030
c2b7aefd
RM		 6031 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
6032 b43err(dev->wl, "MAC not suspended\n");
6033
6034 if (blocked) {
6035 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
6036 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
303415e2 6037 if (phy->rev >= 19) {
572d37a4 6038 /* TODO */
303415e2
RM		 6039 } else if (phy->rev >= 7) {
6040 /* TODO */
6041 } else if (phy->rev >= 3) {
c2b7aefd
RM		 6042 b43_radio_mask(dev, 0x09, ~0x2);
6043
6044 b43_radio_write(dev, 0x204D, 0);
6045 b43_radio_write(dev, 0x2053, 0);
6046 b43_radio_write(dev, 0x2058, 0);
6047 b43_radio_write(dev, 0x205E, 0);
6048 b43_radio_mask(dev, 0x2062, ~0xF0);
6049 b43_radio_write(dev, 0x2064, 0);
6050
6051 b43_radio_write(dev, 0x304D, 0);
6052 b43_radio_write(dev, 0x3053, 0);
6053 b43_radio_write(dev, 0x3058, 0);
6054 b43_radio_write(dev, 0x305E, 0);
6055 b43_radio_mask(dev, 0x3062, ~0xF0);
6056 b43_radio_write(dev, 0x3064, 0);
6057 }
6058 } else {
303415e2
RM		 6059 if (phy->rev >= 19) {
6060 /* TODO */
6061 } else if (phy->rev >= 7) {
6fe55143
RM		 6062 if (!dev->phy.radio_on)
6063 b43_radio_2057_init(dev);
572d37a4 6064 b43_switch_channel(dev, dev->phy.channel);
303415e2 6065 } else if (phy->rev >= 3) {
6fe55143
RM		 6066 if (!dev->phy.radio_on)
6067 b43_radio_init2056(dev);
78159788 6068 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 6069 } else {
6070 b43_radio_init2055(dev);
6071 }
6072 }
ef1a628d
MB		 6073}
6074
0f4091b9 6075/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 6076static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
6077{
303415e2 6078 struct b43_phy *phy = &dev->phy;
2a870831
RM		 6079 u16 override = on ? 0x0 : 0x7FFF;
6080 u16 core = on ? 0xD : 0x00FD;
0f4091b9 6081
303415e2
RM		 6082 if (phy->rev >= 19) {
6083 /* TODO */
6084 } else if (phy->rev >= 3) {
2a870831
RM		 6085 if (on) {
6086 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6087 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6088 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6089 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6090 } else {
6091 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
6092 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
6093 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6094 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
6095 }
6096 } else {
6097 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
6098 }
cb24f57f
MB		 6099}
6100
ef1a628d
MB		 6101static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
6102 unsigned int new_channel)
6103{
675a0b04
KB		 6104 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
6105 enum nl80211_channel_type channel_type =
6106 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 6107
ef1a628d
MB		 6108 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
6109 if ((new_channel < 1) || (new_channel > 14))
6110 return -EINVAL;
6111 } else {
6112 if (new_channel > 200)
6113 return -EINVAL;
6114 }
6115
a656b6a9 6116 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 6117}
6118
6119static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
6120{
6121 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
6122 return 1;
6123 return 36;
6124}
6125
ef1a628d
MB		 6126const struct b43_phy_operations b43_phyops_n = {
6127 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 6128 .free = b43_nphy_op_free,
6129 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 6130 .init = b43_nphy_op_init,
ef1a628d
MB		 6131 .phy_read = b43_nphy_op_read,
6132 .phy_write = b43_nphy_op_write,
755fd183 6133 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 6134 .radio_read = b43_nphy_op_radio_read,
6135 .radio_write = b43_nphy_op_radio_write,
6136 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 6137 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 6138 .switch_channel = b43_nphy_op_switch_channel,
6139 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 6140 .recalc_txpower = b43_nphy_op_recalc_txpower,
6141 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 6142};
Linux kernel - Deliverables
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