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b43: N-PHY: implement calculating RX IQ comp
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
53a6e234
MB		 58void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
59{//TODO
60}
61
18c8adeb 62static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 63{//TODO
64}
65
18c8adeb
MB		 66static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
67 bool ignore_tssi)
68{//TODO
69 return B43_TXPWR_RES_DONE;
70}
71
d1591314
MB		 72static void b43_chantab_radio_upload(struct b43_wldev *dev,
73 const struct b43_nphy_channeltab_entry *e)
74{
75 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
76 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
77 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
78 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
79 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
80 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
81 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
82 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
83 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
84 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
85 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
86 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
87 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
88 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
89 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
90 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
91 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
92 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
93 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
94 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
95 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
96 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
97}
98
99static void b43_chantab_phy_upload(struct b43_wldev *dev,
100 const struct b43_nphy_channeltab_entry *e)
101{
102 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
103 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
104 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
105 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
106 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
107 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
108}
109
110static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
111{
112 //TODO
113}
114
ef1a628d
MB		 115/* Tune the hardware to a new channel. */
116static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 117{
d1591314
MB		 118 const struct b43_nphy_channeltab_entry *tabent;
119
120 tabent = b43_nphy_get_chantabent(dev, channel);
121 if (!tabent)
122 return -ESRCH;
123
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
127 else
128 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev, tabent);
130 udelay(50);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
133 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
134 udelay(300);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
137 else
138 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
139 b43_chantab_phy_upload(dev, tabent);
140 b43_nphy_tx_power_fix(dev);
53a6e234 141
d1591314 142 return 0;
53a6e234
MB		 143}
144
145static void b43_radio_init2055_pre(struct b43_wldev *dev)
146{
147 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE);
149 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
150 B43_NPHY_RFCTL_CMD_CHIP0PU |
151 B43_NPHY_RFCTL_CMD_OEPORFORCE);
152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
153 B43_NPHY_RFCTL_CMD_PORFORCE);
154}
155
156static void b43_radio_init2055_post(struct b43_wldev *dev)
157{
158 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
159 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
160 int i;
161 u16 val;
162
163 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
164 msleep(1);
738f0f43
GS		 165 if ((sprom->revision != 4) ||
166 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 167 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
168 (binfo->type != 0x46D) ||
169 (binfo->rev < 0x41)) {
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
172 msleep(1);
173 }
174 }
175 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
176 msleep(1);
177 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
178 msleep(1);
179 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
180 msleep(1);
181 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
182 msleep(1);
183 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
184 msleep(1);
185 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
186 msleep(1);
187 for (i = 0; i < 100; i++) {
188 val = b43_radio_read16(dev, B2055_CAL_COUT2);
189 if (val & 0x80)
190 break;
191 udelay(10);
192 }
193 msleep(1);
194 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
195 msleep(1);
ef1a628d 196 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 197 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
199 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
200 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
201}
202
203/* Initialize a Broadcom 2055 N-radio */
204static void b43_radio_init2055(struct b43_wldev *dev)
205{
206 b43_radio_init2055_pre(dev);
207 if (b43_status(dev) < B43_STAT_INITIALIZED)
208 b2055_upload_inittab(dev, 0, 1);
209 else
210 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev);
212}
213
214void b43_nphy_radio_turn_on(struct b43_wldev *dev)
215{
216 b43_radio_init2055(dev);
217}
218
219void b43_nphy_radio_turn_off(struct b43_wldev *dev)
220{
221 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
222 ~B43_NPHY_RFCTL_CMD_EN);
223}
224
95b66bad
MB		 225#define ntab_upload(dev, offset, data) do { \
226 unsigned int i; \
227 for (i = 0; i < (offset##_SIZE); i++) \
228 b43_ntab_write(dev, (offset) + i, (data)[i]); \
229 } while (0)
230
4772ae10
RM		 231/*
232 * Upload the N-PHY tables.
233 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
234 */
95b66bad
MB		 235static void b43_nphy_tables_init(struct b43_wldev *dev)
236{
4772ae10
RM		 237 if (dev->phy.rev < 3)
238 b43_nphy_rev0_1_2_tables_init(dev);
239 else
240 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 241}
242
243static void b43_nphy_workarounds(struct b43_wldev *dev)
244{
245 struct b43_phy *phy = &dev->phy;
246 unsigned int i;
247
248 b43_phy_set(dev, B43_NPHY_IQFLIP,
249 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 250 if (1 /* FIXME band is 2.4GHz */) {
251 b43_phy_set(dev, B43_NPHY_CLASSCTL,
252 B43_NPHY_CLASSCTL_CCKEN);
253 } else {
254 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
255 ~B43_NPHY_CLASSCTL_CCKEN);
256 }
257 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
258 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
259
260 /* Fixup some tables */
261 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
271
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
275 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
276
277 //TODO set RF sequence
278
279 /* Set narrowband clip threshold */
280 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
281 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
282
283 /* Set wideband clip 2 threshold */
284 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
285 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
287 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
288 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
289 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
290
291 /* Set Clip 2 detect */
292 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
293 B43_NPHY_C1_CGAINI_CL2DETECT);
294 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
295 B43_NPHY_C2_CGAINI_CL2DETECT);
296
297 if (0 /*FIXME*/) {
298 /* Set dwell lengths */
299 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
301 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
302 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
303
304 /* Set gain backoff */
305 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
306 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
308 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
309 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
310 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
311
312 /* Set HPVGA2 index */
313 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
314 ~B43_NPHY_C1_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
316 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
317 ~B43_NPHY_C2_INITGAIN_HPVGA2,
318 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
319
320 //FIXME verify that the specs really mean to use autoinc here.
321 for (i = 0; i < 3; i++)
322 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
323 }
324
325 /* Set minimum gain value */
326 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
327 ~B43_NPHY_C1_MINGAIN,
328 23 << B43_NPHY_C1_MINGAIN_SHIFT);
329 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
330 ~B43_NPHY_C2_MINGAIN,
331 23 << B43_NPHY_C2_MINGAIN_SHIFT);
332
333 if (phy->rev < 2) {
334 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
335 ~B43_NPHY_SCRAM_SIGCTL_SCM);
336 }
337
338 /* Set phase track alpha and beta */
339 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
341 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
344 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
345}
346
e50cbcf6
RM		 347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
348static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
349{
350 struct b43_phy_n *nphy = dev->phy.n;
351 enum ieee80211_band band;
352 u16 tmp;
353
354 if (!enable) {
355 nphy->rfctrl_intc1_save = b43_phy_read(dev,
356 B43_NPHY_RFCTL_INTC1);
357 nphy->rfctrl_intc2_save = b43_phy_read(dev,
358 B43_NPHY_RFCTL_INTC2);
359 band = b43_current_band(dev->wl);
360 if (dev->phy.rev >= 3) {
361 if (band == IEEE80211_BAND_5GHZ)
362 tmp = 0x600;
363 else
364 tmp = 0x480;
365 } else {
366 if (band == IEEE80211_BAND_5GHZ)
367 tmp = 0x180;
368 else
369 tmp = 0x120;
370 }
371 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
372 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
373 } else {
374 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
375 nphy->rfctrl_intc1_save);
376 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
377 nphy->rfctrl_intc2_save);
378 }
379}
380
4a933c85
RM		 381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
382static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
383{
384 u32 tmslow;
385
386 if (dev->phy.type != B43_PHYTYPE_N)
387 return;
388
389 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
390 if (force)
391 tmslow |= SSB_TMSLOW_FGC;
392 else
393 tmslow &= ~SSB_TMSLOW_FGC;
394 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
395}
396
397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 398static void b43_nphy_reset_cca(struct b43_wldev *dev)
399{
400 u16 bbcfg;
401
4a933c85 402 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 403 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 404 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
405 udelay(1);
406 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
407 b43_nphy_bmac_clock_fgc(dev, 0);
408 /* TODO: N PHY Force RF Seq with argument 2 */
95b66bad
MB		 409}
410
2faa6b83
RM		 411/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
412static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
413 u16 samps, u8 time, bool wait)
414{
415 int i;
416 u16 tmp;
417
418 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
419 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
420 if (wait)
421 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
422 else
423 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
424
425 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
426
427 for (i = 1000; i; i--) {
428 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
429 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
430 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
432 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
433 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
434 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
435 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
436
437 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
438 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
439 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
440 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
441 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
442 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
443 return;
444 }
445 udelay(10);
446 }
447 memset(est, 0, sizeof(*est));
448}
449
a67162ab
RM		 450/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
451static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
452 struct b43_phy_n_iq_comp *pcomp)
453{
454 if (write) {
455 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
456 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
457 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
458 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
459 } else {
460 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
461 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
462 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
463 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
464 }
465}
466
34a56f2c
RM		 467/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
468static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
469{
470 int i;
471 s32 iq;
472 u32 ii;
473 u32 qq;
474 int iq_nbits, qq_nbits;
475 int arsh, brsh;
476 u16 tmp, a, b;
477
478 struct nphy_iq_est est;
479 struct b43_phy_n_iq_comp old;
480 struct b43_phy_n_iq_comp new = { };
481 bool error = false;
482
483 if (mask == 0)
484 return;
485
486 b43_nphy_rx_iq_coeffs(dev, false, &old);
487 b43_nphy_rx_iq_coeffs(dev, true, &new);
488 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
489 new = old;
490
491 for (i = 0; i < 2; i++) {
492 if (i == 0 && (mask & 1)) {
493 iq = est.iq0_prod;
494 ii = est.i0_pwr;
495 qq = est.q0_pwr;
496 } else if (i == 1 && (mask & 2)) {
497 iq = est.iq1_prod;
498 ii = est.i1_pwr;
499 qq = est.q1_pwr;
500 } else {
501 B43_WARN_ON(1);
502 continue;
503 }
504
505 if (ii + qq < 2) {
506 error = true;
507 break;
508 }
509
510 iq_nbits = fls(abs(iq));
511 qq_nbits = fls(qq);
512
513 arsh = iq_nbits - 20;
514 if (arsh >= 0) {
515 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
516 tmp = ii >> arsh;
517 } else {
518 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
519 tmp = ii << -arsh;
520 }
521 if (tmp == 0) {
522 error = true;
523 break;
524 }
525 a /= tmp;
526
527 brsh = qq_nbits - 11;
528 if (brsh >= 0) {
529 b = (qq << (31 - qq_nbits));
530 tmp = ii >> brsh;
531 } else {
532 b = (qq << (31 - qq_nbits));
533 tmp = ii << -brsh;
534 }
535 if (tmp == 0) {
536 error = true;
537 break;
538 }
539 b = int_sqrt(b / tmp - a * a) - (1 << 10);
540
541 if (i == 0 && (mask & 0x1)) {
542 if (dev->phy.rev >= 3) {
543 new.a0 = a & 0x3FF;
544 new.b0 = b & 0x3FF;
545 } else {
546 new.a0 = b & 0x3FF;
547 new.b0 = a & 0x3FF;
548 }
549 } else if (i == 1 && (mask & 0x2)) {
550 if (dev->phy.rev >= 3) {
551 new.a1 = a & 0x3FF;
552 new.b1 = b & 0x3FF;
553 } else {
554 new.a1 = b & 0x3FF;
555 new.b1 = a & 0x3FF;
556 }
557 }
558 }
559
560 if (error)
561 new = old;
562
563 b43_nphy_rx_iq_coeffs(dev, true, &new);
564}
565
09146400
RM		 566/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
567static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
568{
569 u16 array[4];
570 int i;
571
572 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
573 for (i = 0; i < 4; i++)
574 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
575
576 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
577 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
578 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
579 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
580}
581
bbec398c
RM		 582/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
583static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
584{
585 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
586 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
587}
588
589/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
590static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
591{
592 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
593 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
594}
595
596/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
597static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
598{
599 u16 tmp;
600
601 if (dev->dev->id.revision == 16)
602 b43_mac_suspend(dev);
603
604 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
605 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
606 B43_NPHY_CLASSCTL_WAITEDEN);
607 tmp &= ~mask;
608 tmp |= (val & mask);
609 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
610
611 if (dev->dev->id.revision == 16)
612 b43_mac_enable(dev);
613
614 return tmp;
615}
616
5c1a140a
RM		 617/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
618static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
619{
620 struct b43_phy *phy = &dev->phy;
621 struct b43_phy_n *nphy = phy->n;
622
623 if (enable) {
624 u16 clip[] = { 0xFFFF, 0xFFFF };
625 if (nphy->deaf_count++ == 0) {
626 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
627 b43_nphy_classifier(dev, 0x7, 0);
628 b43_nphy_read_clip_detection(dev, nphy->clip_state);
629 b43_nphy_write_clip_detection(dev, clip);
630 }
631 b43_nphy_reset_cca(dev);
632 } else {
633 if (--nphy->deaf_count == 0) {
634 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
635 b43_nphy_write_clip_detection(dev, nphy->clip_state);
636 }
637 }
638}
639
95b66bad
MB		 640enum b43_nphy_rf_sequence {
641 B43_RFSEQ_RX2TX,
642 B43_RFSEQ_TX2RX,
643 B43_RFSEQ_RESET2RX,
644 B43_RFSEQ_UPDATE_GAINH,
645 B43_RFSEQ_UPDATE_GAINL,
646 B43_RFSEQ_UPDATE_GAINU,
647};
648
649static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
650 enum b43_nphy_rf_sequence seq)
651{
652 static const u16 trigger[] = {
653 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
654 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
655 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
656 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
657 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
658 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
659 };
660 int i;
661
662 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
663
664 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
665 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
666 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
667 for (i = 0; i < 200; i++) {
668 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
669 goto ok;
670 msleep(1);
671 }
672 b43err(dev->wl, "RF sequence status timeout\n");
673ok:
674 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
675 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
676}
677
678static void b43_nphy_bphy_init(struct b43_wldev *dev)
679{
680 unsigned int i;
681 u16 val;
682
683 val = 0x1E1F;
684 for (i = 0; i < 14; i++) {
685 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
686 val -= 0x202;
687 }
688 val = 0x3E3F;
689 for (i = 0; i < 16; i++) {
690 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
691 val -= 0x202;
692 }
693 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
694}
695
3c95627d
RM		 696/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
697static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
698 s8 offset, u8 core, u8 rail, u8 type)
699{
700 u16 tmp;
701 bool core1or5 = (core == 1) || (core == 5);
702 bool core2or5 = (core == 2) || (core == 5);
703
704 offset = clamp_val(offset, -32, 31);
705 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
706
707 if (core1or5 && (rail == 0) && (type == 2))
708 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
709 if (core1or5 && (rail == 1) && (type == 2))
710 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
711 if (core2or5 && (rail == 0) && (type == 2))
712 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
713 if (core2or5 && (rail == 1) && (type == 2))
714 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
715 if (core1or5 && (rail == 0) && (type == 0))
716 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
717 if (core1or5 && (rail == 1) && (type == 0))
718 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
719 if (core2or5 && (rail == 0) && (type == 0))
720 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
721 if (core2or5 && (rail == 1) && (type == 0))
722 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
723 if (core1or5 && (rail == 0) && (type == 1))
724 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
725 if (core1or5 && (rail == 1) && (type == 1))
726 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
727 if (core2or5 && (rail == 0) && (type == 1))
728 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
729 if (core2or5 && (rail == 1) && (type == 1))
730 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
731 if (core1or5 && (rail == 0) && (type == 6))
732 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
733 if (core1or5 && (rail == 1) && (type == 6))
734 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
735 if (core2or5 && (rail == 0) && (type == 6))
736 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
737 if (core2or5 && (rail == 1) && (type == 6))
738 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
739 if (core1or5 && (rail == 0) && (type == 3))
740 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
741 if (core1or5 && (rail == 1) && (type == 3))
742 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
743 if (core2or5 && (rail == 0) && (type == 3))
744 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
745 if (core2or5 && (rail == 1) && (type == 3))
746 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
747 if (core1or5 && (type == 4))
748 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
749 if (core2or5 && (type == 4))
750 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
751 if (core1or5 && (type == 5))
752 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
753 if (core2or5 && (type == 5))
754 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
755}
756
757/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
758static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
759{
760 u16 val;
761
762 if (dev->phy.rev >= 3) {
763 /* TODO */
764 } else {
765 if (type < 3)
766 val = 0;
767 else if (type == 6)
768 val = 1;
769 else if (type == 3)
770 val = 2;
771 else
772 val = 3;
773
774 val = (val << 12) | (val << 14);
775 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
776 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
777
778 if (type < 3) {
779 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
780 (type + 1) << 4);
781 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
782 (type + 1) << 4);
783 }
784
785 /* TODO use some definitions */
786 if (code == 0) {
787 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
788 if (type < 3) {
789 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
790 0xFEC7, 0);
791 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
792 0xEFDC, 0);
793 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
794 0xFFFE, 0);
795 udelay(20);
796 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
797 0xFFFE, 0);
798 }
799 } else {
800 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
801 0x3000);
802 if (type < 3) {
803 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
804 0xFEC7, 0x0180);
805 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
806 0xEFDC, (code << 1 | 0x1021));
807 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
808 0xFFFE, 0x0001);
809 udelay(20);
810 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
811 0xFFFE, 0);
812 }
813 }
814 }
815}
816
dfb4aa5d
RM		 817/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
818static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
819{
820 int i;
821 for (i = 0; i < 2; i++) {
822 if (type == 2) {
823 if (i == 0) {
824 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
825 0xFC, buf[0]);
826 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
827 0xFC, buf[1]);
828 } else {
829 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
830 0xFC, buf[2 * i]);
831 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
832 0xFC, buf[2 * i + 1]);
833 }
834 } else {
835 if (i == 0)
836 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
837 0xF3, buf[0] << 2);
838 else
839 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
840 0xF3, buf[2 * i + 1] << 2);
841 }
842 }
843}
844
845/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
846static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
847 u8 nsamp)
848{
849 int i;
850 int out;
851 u16 save_regs_phy[9];
852 u16 s[2];
853
854 if (dev->phy.rev >= 3) {
855 save_regs_phy[0] = b43_phy_read(dev,
856 B43_NPHY_RFCTL_LUT_TRSW_UP1);
857 save_regs_phy[1] = b43_phy_read(dev,
858 B43_NPHY_RFCTL_LUT_TRSW_UP2);
859 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
860 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
861 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
862 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
863 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
864 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
865 }
866
867 b43_nphy_rssi_select(dev, 5, type);
868
869 if (dev->phy.rev < 2) {
870 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
871 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
872 }
873
874 for (i = 0; i < 4; i++)
875 buf[i] = 0;
876
877 for (i = 0; i < nsamp; i++) {
878 if (dev->phy.rev < 2) {
879 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
880 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
881 } else {
882 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
883 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
884 }
885
886 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
887 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
888 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
889 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
890 }
891 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
892 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
893
894 if (dev->phy.rev < 2)
895 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
896
897 if (dev->phy.rev >= 3) {
898 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
899 save_regs_phy[0]);
900 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
901 save_regs_phy[1]);
902 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
903 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
904 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
905 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
906 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
907 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
908 }
909
910 return out;
911}
912
4cb99775
RM		 913/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
914static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 915{
90b9738d
RM		 916 int i, j;
917 u8 state[4];
918 u8 code, val;
919 u16 class, override;
920 u8 regs_save_radio[2];
921 u16 regs_save_phy[2];
922 s8 offset[4];
923
924 u16 clip_state[2];
925 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
926 s32 results_min[4] = { };
927 u8 vcm_final[4] = { };
928 s32 results[4][4] = { };
929 s32 miniq[4][2] = { };
930
931 if (type == 2) {
932 code = 0;
933 val = 6;
934 } else if (type < 2) {
935 code = 25;
936 val = 4;
937 } else {
938 B43_WARN_ON(1);
939 return;
940 }
941
942 class = b43_nphy_classifier(dev, 0, 0);
943 b43_nphy_classifier(dev, 7, 4);
944 b43_nphy_read_clip_detection(dev, clip_state);
945 b43_nphy_write_clip_detection(dev, clip_off);
946
947 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
948 override = 0x140;
949 else
950 override = 0x110;
951
952 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
953 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
954 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
955 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
956
957 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
958 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
959 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
960 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
961
962 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
963 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
964 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
965 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
966 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
967 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
968
969 b43_nphy_rssi_select(dev, 5, type);
970 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
971 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
972
973 for (i = 0; i < 4; i++) {
974 u8 tmp[4];
975 for (j = 0; j < 4; j++)
976 tmp[j] = i;
977 if (type != 1)
978 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
979 b43_nphy_poll_rssi(dev, type, results[i], 8);
980 if (type < 2)
981 for (j = 0; j < 2; j++)
982 miniq[i][j] = min(results[i][2 * j],
983 results[i][2 * j + 1]);
984 }
985
986 for (i = 0; i < 4; i++) {
987 s32 mind = 40;
988 u8 minvcm = 0;
989 s32 minpoll = 249;
990 s32 curr;
991 for (j = 0; j < 4; j++) {
992 if (type == 2)
993 curr = abs(results[j][i]);
994 else
995 curr = abs(miniq[j][i / 2] - code * 8);
996
997 if (curr < mind) {
998 mind = curr;
999 minvcm = j;
1000 }
1001
1002 if (results[j][i] < minpoll)
1003 minpoll = results[j][i];
1004 }
1005 results_min[i] = minpoll;
1006 vcm_final[i] = minvcm;
1007 }
1008
1009 if (type != 1)
1010 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1011
1012 for (i = 0; i < 4; i++) {
1013 offset[i] = (code * 8) - results[vcm_final[i]][i];
1014
1015 if (offset[i] < 0)
1016 offset[i] = -((abs(offset[i]) + 4) / 8);
1017 else
1018 offset[i] = (offset[i] + 4) / 8;
1019
1020 if (results_min[i] == 248)
1021 offset[i] = code - 32;
1022
1023 if (i % 2 == 0)
1024 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1025 type);
1026 else
1027 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1028 type);
1029 }
1030
1031 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1032 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1033
1034 switch (state[2]) {
1035 case 1:
1036 b43_nphy_rssi_select(dev, 1, 2);
1037 break;
1038 case 4:
1039 b43_nphy_rssi_select(dev, 1, 0);
1040 break;
1041 case 2:
1042 b43_nphy_rssi_select(dev, 1, 1);
1043 break;
1044 default:
1045 b43_nphy_rssi_select(dev, 1, 1);
1046 break;
1047 }
1048
1049 switch (state[3]) {
1050 case 1:
1051 b43_nphy_rssi_select(dev, 2, 2);
1052 break;
1053 case 4:
1054 b43_nphy_rssi_select(dev, 2, 0);
1055 break;
1056 default:
1057 b43_nphy_rssi_select(dev, 2, 1);
1058 break;
1059 }
1060
1061 b43_nphy_rssi_select(dev, 0, type);
1062
1063 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1064 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1065 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1066 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1067
1068 b43_nphy_classifier(dev, 7, class);
1069 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 1070}
1071
1072/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1073static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1074{
1075 /* TODO */
1076}
1077
1078/*
1079 * RSSI Calibration
1080 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1081 */
1082static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1083{
1084 if (dev->phy.rev >= 3) {
1085 b43_nphy_rev3_rssi_cal(dev);
1086 } else {
1087 b43_nphy_rev2_rssi_cal(dev, 2);
1088 b43_nphy_rev2_rssi_cal(dev, 0);
1089 b43_nphy_rev2_rssi_cal(dev, 1);
1090 }
95b66bad
MB		 1091}
1092
42e1547e
RM		 1093/*
1094 * Restore RSSI Calibration
1095 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1096 */
1097static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1098{
1099 struct b43_phy_n *nphy = dev->phy.n;
1100
1101 u16 *rssical_radio_regs = NULL;
1102 u16 *rssical_phy_regs = NULL;
1103
1104 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1105 if (!nphy->rssical_chanspec_2G)
1106 return;
1107 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1108 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1109 } else {
1110 if (!nphy->rssical_chanspec_5G)
1111 return;
1112 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1113 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1114 }
1115
1116 /* TODO use some definitions */
1117 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1118 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1119
1120 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1121 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1122 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1123 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1124
1125 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1126 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1127 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1128 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1129
1130 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1131 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1132 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1133 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1134}
1135
2f258b74
RM		 1136/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1137static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1138{
1139 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1140 if (dev->phy.rev >= 6) {
1141 /* TODO If the chip is 47162
1142 return txpwrctrl_tx_gain_ipa_rev5 */
1143 return txpwrctrl_tx_gain_ipa_rev6;
1144 } else if (dev->phy.rev >= 5) {
1145 return txpwrctrl_tx_gain_ipa_rev5;
1146 } else {
1147 return txpwrctrl_tx_gain_ipa;
1148 }
1149 } else {
1150 return txpwrctrl_tx_gain_ipa_5g;
1151 }
1152}
1153
1154/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1155static void b43_nphy_restore_cal(struct b43_wldev *dev)
1156{
1157 struct b43_phy_n *nphy = dev->phy.n;
1158
1159 u16 coef[4];
1160 u16 *loft = NULL;
1161 u16 *table = NULL;
1162
1163 int i;
1164 u16 *txcal_radio_regs = NULL;
1165 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1166
1167 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1168 if (nphy->iqcal_chanspec_2G == 0)
1169 return;
1170 table = nphy->cal_cache.txcal_coeffs_2G;
1171 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1172 } else {
1173 if (nphy->iqcal_chanspec_5G == 0)
1174 return;
1175 table = nphy->cal_cache.txcal_coeffs_5G;
1176 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1177 }
1178
1179 /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1180 width 16, and data from table */
1181
1182 for (i = 0; i < 4; i++) {
1183 if (dev->phy.rev >= 3)
1184 table[i] = coef[i];
1185 else
1186 coef[i] = 0;
1187 }
1188
1189 /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1190 width 16, and data from coef */
1191 /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1192 width 16 and data from loft */
1193 /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1194 width 16 and data from loft */
1195
1196 if (dev->phy.rev < 2)
1197 b43_nphy_tx_iq_workaround(dev);
1198
1199 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1200 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1201 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1202 } else {
1203 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1204 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1205 }
1206
1207 /* TODO use some definitions */
1208 if (dev->phy.rev >= 3) {
1209 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1210 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1211 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1212 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1213 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1214 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1215 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1216 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1217 } else {
1218 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1219 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1220 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1221 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1222 }
1223 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1224}
1225
0988a7a1
RM		 1226/*
1227 * Init N-PHY
1228 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
1229 */
424047e6
MB		 1230int b43_phy_initn(struct b43_wldev *dev)
1231{
0988a7a1 1232 struct ssb_bus *bus = dev->dev->bus;
95b66bad 1233 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 1234 struct b43_phy_n *nphy = phy->n;
1235 u8 tx_pwr_state;
1236 struct nphy_txgains target;
95b66bad 1237 u16 tmp;
0988a7a1
RM		 1238 enum ieee80211_band tmp2;
1239 bool do_rssi_cal;
1240
1241 u16 clip[2];
1242 bool do_cal = false;
95b66bad 1243
0988a7a1
RM		 1244 if ((dev->phy.rev >= 3) &&
1245 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
1246 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1247 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1248 }
1249 nphy->deaf_count = 0;
95b66bad 1250 b43_nphy_tables_init(dev);
0988a7a1
RM		 1251 nphy->crsminpwr_adjusted = false;
1252 nphy->noisevars_adjusted = false;
95b66bad
MB		 1253
1254 /* Clear all overrides */
0988a7a1
RM		 1255 if (dev->phy.rev >= 3) {
1256 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
1257 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1258 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
1259 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
1260 } else {
1261 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1262 }
95b66bad
MB		 1263 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
1264 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 1265 if (dev->phy.rev < 6) {
1266 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
1267 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
1268 }
95b66bad
MB		 1269 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1270 ~(B43_NPHY_RFSEQMODE_CAOVER |
1271 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 1272 if (dev->phy.rev >= 3)
1273 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 1274 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
1275
0988a7a1
RM		 1276 if (dev->phy.rev <= 2) {
1277 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
1278 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1279 ~B43_NPHY_BPHY_CTL3_SCALE,
1280 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
1281 }
95b66bad
MB		 1282 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
1283 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
1284
0988a7a1
RM		 1285 if (bus->sprom.boardflags2_lo & 0x100 ||
1286 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
1287 bus->boardinfo.type == 0x8B))
1288 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
1289 else
1290 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
1291 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
1292 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
1293 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 1294
0988a7a1
RM		 1295 /* TODO MIMO-Config */
1296 /* TODO Update TX/RX chain */
95b66bad
MB		 1297
1298 if (phy->rev < 2) {
1299 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
1300 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
1301 }
0988a7a1
RM		 1302
1303 tmp2 = b43_current_band(dev->wl);
1304 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
1305 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
1306 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
1307 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
1308 nphy->papd_epsilon_offset[0] << 7);
1309 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
1310 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
1311 nphy->papd_epsilon_offset[1] << 7);
1312 /* TODO N PHY IPA Set TX Dig Filters */
1313 } else if (phy->rev >= 5) {
1314 /* TODO N PHY Ext PA Set TX Dig Filters */
1315 }
1316
95b66bad 1317 b43_nphy_workarounds(dev);
95b66bad 1318
0988a7a1
RM		 1319 /* Reset CCA, in init code it differs a little from standard way */
1320 /* b43_nphy_bmac_clock_fgc(dev, 1); */
1321 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
1322 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
1323 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
1324 /* b43_nphy_bmac_clock_fgc(dev, 0); */
1325
1326 /* TODO N PHY MAC PHY Clock Set with argument 1 */
1327
e50cbcf6 1328 b43_nphy_pa_override(dev, false);
95b66bad
MB		 1329 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1330 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 1331 b43_nphy_pa_override(dev, true);
0988a7a1 1332
bbec398c
RM		 1333 b43_nphy_classifier(dev, 0, 0);
1334 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 1335 tx_pwr_state = nphy->txpwrctrl;
1336 /* TODO N PHY TX power control with argument 0
1337 (turning off power control) */
1338 /* TODO Fix the TX Power Settings */
1339 /* TODO N PHY TX Power Control Idle TSSI */
1340 /* TODO N PHY TX Power Control Setup */
1341
1342 if (phy->rev >= 3) {
1343 /* TODO */
1344 } else {
1345 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1346 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1347 }
95b66bad 1348
0988a7a1
RM		 1349 if (nphy->phyrxchain != 3)
1350 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1351 if (nphy->mphase_cal_phase_id > 0)
1352 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1353
1354 do_rssi_cal = false;
1355 if (phy->rev >= 3) {
1356 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1357 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1358 else
1359 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1360
1361 if (do_rssi_cal)
4cb99775 1362 b43_nphy_rssi_cal(dev);
0988a7a1 1363 else
42e1547e 1364 b43_nphy_restore_rssi_cal(dev);
0988a7a1 1365 } else {
4cb99775 1366 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1367 }
1368
1369 if (!((nphy->measure_hold & 0x6) != 0)) {
1370 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1371 do_cal = (nphy->iqcal_chanspec_2G == 0);
1372 else
1373 do_cal = (nphy->iqcal_chanspec_5G == 0);
1374
1375 if (nphy->mute)
1376 do_cal = false;
1377
1378 if (do_cal) {
1379 /* target = b43_nphy_get_tx_gains(dev); */
1380
1381 if (nphy->antsel_type == 2)
1382 ;/*TODO NPHY Superswitch Init with argument 1*/
1383 if (nphy->perical != 2) {
90b9738d 1384 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1385 if (phy->rev >= 3) {
1386 nphy->cal_orig_pwr_idx[0] =
1387 nphy->txpwrindex[0].index_internal;
1388 nphy->cal_orig_pwr_idx[1] =
1389 nphy->txpwrindex[1].index_internal;
1390 /* TODO N PHY Pre Calibrate TX Gain */
1391 /*target = b43_nphy_get_tx_gains(dev)*/
1392 }
1393 }
1394 }
1395 }
1396
1397 /*
1398 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1399 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1400 Call N PHY Save Cal
1401 else if (nphy->mphase_cal_phase_id == 0)
1402 N PHY Periodic Calibration with argument 3
1403 } else {
1404 b43_nphy_restore_cal(dev);
1405 }
1406 */
1407
1408 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1409 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1410 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1411 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1412 if (phy->rev >= 3 && phy->rev <= 6)
1413 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1414 /* b43_nphy_tx_lp_fbw(dev); */
1415 /* TODO N PHY Spur Workaround */
95b66bad
MB		 1416
1417 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 1418 return 0;
424047e6 1419}
ef1a628d
MB		 1420
1421static int b43_nphy_op_allocate(struct b43_wldev *dev)
1422{
1423 struct b43_phy_n *nphy;
1424
1425 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1426 if (!nphy)
1427 return -ENOMEM;
1428 dev->phy.n = nphy;
1429
ef1a628d
MB		 1430 return 0;
1431}
1432
fb11137a 1433static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 1434{
fb11137a
MB		 1435 struct b43_phy *phy = &dev->phy;
1436 struct b43_phy_n *nphy = phy->n;
ef1a628d 1437
fb11137a 1438 memset(nphy, 0, sizeof(*nphy));
ef1a628d 1439
fb11137a 1440 //TODO init struct b43_phy_n
ef1a628d
MB		 1441}
1442
fb11137a 1443static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 1444{
fb11137a
MB		 1445 struct b43_phy *phy = &dev->phy;
1446 struct b43_phy_n *nphy = phy->n;
ef1a628d 1447
ef1a628d 1448 kfree(nphy);
fb11137a
MB		 1449 phy->n = NULL;
1450}
1451
1452static int b43_nphy_op_init(struct b43_wldev *dev)
1453{
1454 return b43_phy_initn(dev);
ef1a628d
MB		 1455}
1456
1457static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1458{
1459#if B43_DEBUG
1460 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1461 /* OFDM registers are onnly available on A/G-PHYs */
1462 b43err(dev->wl, "Invalid OFDM PHY access at "
1463 "0x%04X on N-PHY\n", offset);
1464 dump_stack();
1465 }
1466 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1467 /* Ext-G registers are only available on G-PHYs */
1468 b43err(dev->wl, "Invalid EXT-G PHY access at "
1469 "0x%04X on N-PHY\n", offset);
1470 dump_stack();
1471 }
1472#endif /* B43_DEBUG */
1473}
1474
1475static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1476{
1477 check_phyreg(dev, reg);
1478 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1479 return b43_read16(dev, B43_MMIO_PHY_DATA);
1480}
1481
1482static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1483{
1484 check_phyreg(dev, reg);
1485 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1486 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1487}
1488
1489static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1490{
1491 /* Register 1 is a 32-bit register. */
1492 B43_WARN_ON(reg == 1);
1493 /* N-PHY needs 0x100 for read access */
1494 reg |= 0x100;
1495
1496 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1497 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1498}
1499
1500static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1501{
1502 /* Register 1 is a 32-bit register. */
1503 B43_WARN_ON(reg == 1);
1504
1505 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1506 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1507}
1508
1509static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1510 bool blocked)
ef1a628d
MB		 1511{//TODO
1512}
1513
cb24f57f
MB		 1514static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1515{
1516 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1517 on ? 0 : 0x7FFF);
1518}
1519
ef1a628d
MB		 1520static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1521 unsigned int new_channel)
1522{
1523 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1524 if ((new_channel < 1) || (new_channel > 14))
1525 return -EINVAL;
1526 } else {
1527 if (new_channel > 200)
1528 return -EINVAL;
1529 }
1530
1531 return nphy_channel_switch(dev, new_channel);
1532}
1533
1534static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1535{
1536 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1537 return 1;
1538 return 36;
1539}
1540
ef1a628d
MB		 1541const struct b43_phy_operations b43_phyops_n = {
1542 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 1543 .free = b43_nphy_op_free,
1544 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 1545 .init = b43_nphy_op_init,
ef1a628d
MB		 1546 .phy_read = b43_nphy_op_read,
1547 .phy_write = b43_nphy_op_write,
1548 .radio_read = b43_nphy_op_radio_read,
1549 .radio_write = b43_nphy_op_radio_write,
1550 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 1551 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 1552 .switch_channel = b43_nphy_op_switch_channel,
1553 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 1554 .recalc_txpower = b43_nphy_op_recalc_txpower,
1555 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 1556};
Linux kernel - Deliverables
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