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b43: N-PHY: use more friendly variables names in RSSI code
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
76b002bd
RM		 72enum b43_nphy_rssi_type {
73 B43_NPHY_RSSI_X = 0,
74 B43_NPHY_RSSI_Y,
75 B43_NPHY_RSSI_Z,
76 B43_NPHY_RSSI_PWRDET,
77 B43_NPHY_RSSI_TSSI_I,
78 B43_NPHY_RSSI_TSSI_Q,
79 B43_NPHY_RSSI_TBD,
80};
81
6aa38725
RM		 82enum n_rail_type {
83 N_RAIL_I = 0,
84 N_RAIL_Q = 1,
85};
86
c002831a
RM		 87static inline bool b43_nphy_ipa(struct b43_wldev *dev)
88{
89 enum ieee80211_band band = b43_current_band(dev->wl);
90 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
91 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
92}
93
e0c9a021
RM		 94/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
95static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
96{
97 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
98 B43_NPHY_RFSEQCA_RXEN_SHIFT;
99}
100
ab499217
RM		 101/**************************************************
102 * RF (just without b43_nphy_rf_control_intc_override)
103 **************************************************/
18c8adeb 104
ab499217
RM		 105/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
106static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
107 enum b43_nphy_rf_sequence seq)
d1591314 108{
ab499217
RM		 109 static const u16 trigger[] = {
110 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
111 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
112 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
113 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
114 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
115 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
116 };
117 int i;
118 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 119
ab499217 120 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 121
ab499217
RM		 122 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
123 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
124 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
125 for (i = 0; i < 200; i++) {
126 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
127 goto ok;
128 msleep(1);
129 }
130 b43err(dev->wl, "RF sequence status timeout\n");
131ok:
132 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
133}
e5255ccc 134
c071b9f6
RM		 135/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
136static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
137 u16 value, u8 core, bool off,
138 u8 override)
139{
140 const struct nphy_rf_control_override_rev7 *e;
141 u16 en_addrs[3][2] = {
142 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
143 };
144 u16 en_addr;
145 u16 en_mask = field;
146 u16 val_addr;
147 u8 i;
148
149 /* Remember: we can get NULL! */
150 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
151
152 for (i = 0; i < 2; i++) {
153 if (override >= ARRAY_SIZE(en_addrs)) {
154 b43err(dev->wl, "Invalid override value %d\n", override);
155 return;
156 }
157 en_addr = en_addrs[override][i];
158
159 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
160
161 if (off) {
162 b43_phy_mask(dev, en_addr, ~en_mask);
163 if (e) /* Do it safer, better than wl */
164 b43_phy_mask(dev, val_addr, ~e->val_mask);
165 } else {
166 if (!core || (core & (1 << i))) {
167 b43_phy_set(dev, en_addr, en_mask);
168 if (e)
169 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
170 }
171 }
172 }
173}
174
ab499217
RM		 175/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
176static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
177 u16 value, u8 core, bool off)
178{
179 int i;
180 u8 index = fls(field);
181 u8 addr, en_addr, val_addr;
182 /* we expect only one bit set */
183 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 184
ab499217
RM		 185 if (dev->phy.rev >= 3) {
186 const struct nphy_rf_control_override_rev3 *rf_ctrl;
187 for (i = 0; i < 2; i++) {
188 if (index == 0 || index == 16) {
189 b43err(dev->wl,
190 "Unsupported RF Ctrl Override call\n");
191 return;
192 }
e5255ccc 193
ab499217
RM		 194 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
195 en_addr = B43_PHY_N((i == 0) ?
196 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
197 val_addr = B43_PHY_N((i == 0) ?
198 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 199
ab499217
RM		 200 if (off) {
201 b43_phy_mask(dev, en_addr, ~(field));
202 b43_phy_mask(dev, val_addr,
203 ~(rf_ctrl->val_mask));
204 } else {
b97c0718 205 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 206 b43_phy_set(dev, en_addr, field);
207 b43_phy_maskset(dev, val_addr,
208 ~(rf_ctrl->val_mask),
209 (value << rf_ctrl->val_shift));
210 }
211 }
212 }
213 } else {
214 const struct nphy_rf_control_override_rev2 *rf_ctrl;
215 if (off) {
216 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
217 value = 0;
218 } else {
219 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
220 }
d4814e69 221
ab499217
RM		 222 for (i = 0; i < 2; i++) {
223 if (index <= 1 || index == 16) {
224 b43err(dev->wl,
225 "Unsupported RF Ctrl Override call\n");
226 return;
227 }
d4814e69 228
ab499217
RM		 229 if (index == 2 || index == 10 ||
230 (index >= 13 && index <= 15)) {
231 core = 1;
232 }
d4814e69 233
ab499217
RM		 234 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
235 addr = B43_PHY_N((i == 0) ?
236 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 237
b97c0718 238 if ((1 << i) & core)
ab499217
RM		 239 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
240 (value << rf_ctrl->shift));
241
242 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
243 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
244 B43_NPHY_RFCTL_CMD_START);
245 udelay(1);
246 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
247 }
248 }
d4814e69
RM		 249}
250
ab499217
RM		 251/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
252static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
253 u16 value, u8 core)
d4814e69 254{
ab499217
RM		 255 u8 i, j;
256 u16 reg, tmp, val;
38646eba 257
d4814e69 258 B43_WARN_ON(dev->phy.rev < 3);
ab499217 259 B43_WARN_ON(field > 4);
d4814e69 260
ab499217
RM		 261 for (i = 0; i < 2; i++) {
262 if ((core == 1 && i == 1) || (core == 2 && !i))
263 continue;
38646eba 264
ab499217
RM		 265 reg = (i == 0) ?
266 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 267 b43_phy_set(dev, reg, 0x400);
38646eba 268
ab499217
RM		 269 switch (field) {
270 case 0:
271 b43_phy_write(dev, reg, 0);
272 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
273 break;
274 case 1:
275 if (!i) {
276 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
277 0xFC3F, (value << 6));
278 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
279 0xFFFE, 1);
280 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
281 B43_NPHY_RFCTL_CMD_START);
282 for (j = 0; j < 100; j++) {
603431e9 283 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 284 j = 0;
285 break;
286 }
287 udelay(10);
38646eba 288 }
ab499217
RM		 289 if (j)
290 b43err(dev->wl,
291 "intc override timeout\n");
292 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
293 0xFFFE);
38646eba 294 } else {
ab499217
RM		 295 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
296 0xFC3F, (value << 6));
297 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
298 0xFFFE, 1);
299 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
300 B43_NPHY_RFCTL_CMD_RXTX);
301 for (j = 0; j < 100; j++) {
603431e9 302 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 303 j = 0;
304 break;
305 }
306 udelay(10);
307 }
308 if (j)
309 b43err(dev->wl,
310 "intc override timeout\n");
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
312 0xFFFE);
38646eba 313 }
ab499217
RM		 314 break;
315 case 2:
316 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
317 tmp = 0x0020;
318 val = value << 5;
319 } else {
320 tmp = 0x0010;
321 val = value << 4;
322 }
323 b43_phy_maskset(dev, reg, ~tmp, val);
324 break;
325 case 3:
326 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
327 tmp = 0x0001;
328 val = value;
329 } else {
330 tmp = 0x0004;
331 val = value << 2;
332 }
333 b43_phy_maskset(dev, reg, ~tmp, val);
334 break;
335 case 4:
336 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
337 tmp = 0x0002;
338 val = value << 1;
339 } else {
340 tmp = 0x0008;
341 val = value << 3;
342 }
343 b43_phy_maskset(dev, reg, ~tmp, val);
344 break;
38646eba 345 }
38646eba 346 }
ab499217 347}
38646eba 348
ab499217
RM		 349/**************************************************
350 * Various PHY ops
351 **************************************************/
352
353/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
354static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
355 const u16 *clip_st)
356{
357 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
358 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 359}
360
ab499217
RM		 361/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
362static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 363{
ab499217
RM		 364 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
365 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 366}
367
ab499217
RM		 368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
369static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 370{
ab499217 371 u16 tmp;
161d540c 372
ab499217
RM		 373 if (dev->dev->core_rev == 16)
374 b43_mac_suspend(dev);
161d540c 375
ab499217
RM		 376 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
377 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
378 B43_NPHY_CLASSCTL_WAITEDEN);
379 tmp &= ~mask;
380 tmp |= (val & mask);
381 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 382
ab499217
RM		 383 if (dev->dev->core_rev == 16)
384 b43_mac_enable(dev);
161d540c 385
ab499217
RM		 386 return tmp;
387}
161d540c 388
ab499217
RM		 389/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
390static void b43_nphy_reset_cca(struct b43_wldev *dev)
391{
392 u16 bbcfg;
161d540c 393
ab499217
RM		 394 b43_phy_force_clock(dev, 1);
395 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
396 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
397 udelay(1);
398 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
399 b43_phy_force_clock(dev, 0);
400 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
401}
161d540c 402
ab499217
RM		 403/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
404static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
405{
406 struct b43_phy *phy = &dev->phy;
407 struct b43_phy_n *nphy = phy->n;
161d540c 408
ab499217
RM		 409 if (enable) {
410 static const u16 clip[] = { 0xFFFF, 0xFFFF };
411 if (nphy->deaf_count++ == 0) {
412 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
413 b43_nphy_classifier(dev, 0x7, 0);
414 b43_nphy_read_clip_detection(dev, nphy->clip_state);
415 b43_nphy_write_clip_detection(dev, clip);
416 }
417 b43_nphy_reset_cca(dev);
161d540c 418 } else {
ab499217
RM		 419 if (--nphy->deaf_count == 0) {
420 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
421 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 422 }
161d540c 423 }
161d540c
RM		 424}
425
64712095
RM		 426/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
427static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 428{
161d540c 429 struct b43_phy_n *nphy = dev->phy.n;
161d540c 430
64712095
RM		 431 u8 i;
432 s16 tmp;
433 u16 data[4];
434 s16 gain[2];
435 u16 minmax[2];
436 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 437
438 if (nphy->hang_avoid)
439 b43_nphy_stay_in_carrier_search(dev, 1);
440
64712095 441 if (nphy->gain_boost) {
161d540c 442 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 443 gain[0] = 6;
444 gain[1] = 6;
161d540c 445 } else {
64712095
RM		 446 tmp = 40370 - 315 * dev->phy.channel;
447 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
448 tmp = 23242 - 224 * dev->phy.channel;
449 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 450 }
64712095
RM		 451 } else {
452 gain[0] = 0;
453 gain[1] = 0;
161d540c 454 }
161d540c
RM		 455
456 for (i = 0; i < 2; i++) {
64712095
RM		 457 if (nphy->elna_gain_config) {
458 data[0] = 19 + gain[i];
459 data[1] = 25 + gain[i];
460 data[2] = 25 + gain[i];
461 data[3] = 25 + gain[i];
161d540c 462 } else {
64712095
RM		 463 data[0] = lna_gain[0] + gain[i];
464 data[1] = lna_gain[1] + gain[i];
465 data[2] = lna_gain[2] + gain[i];
466 data[3] = lna_gain[3] + gain[i];
161d540c 467 }
64712095 468 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 469
64712095 470 minmax[i] = 23 + gain[i];
161d540c
RM		 471 }
472
64712095
RM		 473 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
474 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
475 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
476 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 477
478 if (nphy->hang_avoid)
479 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 480}
481
ab499217
RM		 482/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
483static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
484 u8 *events, u8 *delays, u8 length)
0eff8fcd 485{
ab499217
RM		 486 struct b43_phy_n *nphy = dev->phy.n;
487 u8 i;
488 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
489 u16 offset1 = cmd << 4;
490 u16 offset2 = offset1 + 0x80;
0eff8fcd 491
ab499217
RM		 492 if (nphy->hang_avoid)
493 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 494
ab499217
RM		 495 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
496 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 497
ab499217
RM		 498 for (i = length; i < 16; i++) {
499 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
500 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 501 }
ab499217
RM		 502
503 if (nphy->hang_avoid)
504 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 505}
7955de0c 506
572d37a4
RM		 507/**************************************************
508 * Radio 0x2057
509 **************************************************/
510
511/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
512static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
513{
514 struct b43_phy *phy = &dev->phy;
515 u16 tmp;
516
517 if (phy->radio_rev == 5) {
518 b43_phy_mask(dev, 0x342, ~0x2);
519 udelay(10);
520 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
521 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
522 }
523
524 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
525 udelay(10);
526 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
527 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
528 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
529 return 0;
530 }
531 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
532 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
533 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
534
535 if (phy->radio_rev == 5) {
536 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
537 b43_radio_mask(dev, 0x1ca, ~0x2);
538 }
539 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
540 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
541 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
542 tmp << 2);
543 }
544
545 return tmp & 0x3e;
546}
547
548/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
549static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
550{
551 struct b43_phy *phy = &dev->phy;
552 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
553 phy->radio_rev == 6);
554 u16 tmp;
555
556 if (special) {
557 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
558 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
559 } else {
560 b43_radio_write(dev, 0x1AE, 0x61);
561 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
562 }
563 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
564 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
565 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
566 5000000))
567 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
568 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
569 if (special) {
570 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
571 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
572 } else {
573 b43_radio_write(dev, 0x1AE, 0x69);
574 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
575 }
576 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
577 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
578 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
579 5000000))
6c187236 580 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 581 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
582 if (special) {
583 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
584 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
585 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
586 } else {
587 b43_radio_write(dev, 0x1AE, 0x73);
588 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
589 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
590 }
591 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
592 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
593 5000000)) {
594 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
595 return 0;
596 }
597 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
598 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
599 return tmp;
600}
601
602static void b43_radio_2057_init_pre(struct b43_wldev *dev)
603{
604 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
605 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
606 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
607 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
608 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
609}
610
611static void b43_radio_2057_init_post(struct b43_wldev *dev)
612{
613 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
614
615 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
616 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
617 mdelay(2);
618 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
619 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
620
621 if (dev->phy.n->init_por) {
622 b43_radio_2057_rcal(dev);
623 b43_radio_2057_rccal(dev);
624 }
625 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
626
627 dev->phy.n->init_por = false;
628}
629
630/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
631static void b43_radio_2057_init(struct b43_wldev *dev)
632{
633 b43_radio_2057_init_pre(dev);
634 r2057_upload_inittabs(dev);
635 b43_radio_2057_init_post(dev);
636}
637
ab499217 638/**************************************************
884a5228 639 * Radio 0x2056
ab499217 640 **************************************************/
7955de0c 641
d4814e69
RM		 642static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
643 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 644{
d4814e69
RM		 645 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
646 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
647 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
648 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
649 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
650 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
651 e->radio_syn_pll_loopfilter1);
652 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
653 e->radio_syn_pll_loopfilter2);
654 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
655 e->radio_syn_pll_loopfilter3);
656 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
657 e->radio_syn_pll_loopfilter4);
658 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
659 e->radio_syn_pll_loopfilter5);
660 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
661 e->radio_syn_reserved_addr27);
662 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
663 e->radio_syn_reserved_addr28);
664 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
665 e->radio_syn_reserved_addr29);
666 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
667 e->radio_syn_logen_vcobuf1);
668 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
669 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
670 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
671
672 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
673 e->radio_rx0_lnaa_tune);
674 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
675 e->radio_rx0_lnag_tune);
676
677 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
678 e->radio_tx0_intpaa_boost_tune);
679 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
680 e->radio_tx0_intpag_boost_tune);
681 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
682 e->radio_tx0_pada_boost_tune);
683 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
684 e->radio_tx0_padg_boost_tune);
685 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
686 e->radio_tx0_pgaa_boost_tune);
687 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
688 e->radio_tx0_pgag_boost_tune);
689 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
690 e->radio_tx0_mixa_boost_tune);
691 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
692 e->radio_tx0_mixg_boost_tune);
693
694 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
695 e->radio_rx1_lnaa_tune);
696 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
697 e->radio_rx1_lnag_tune);
698
699 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
700 e->radio_tx1_intpaa_boost_tune);
701 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
702 e->radio_tx1_intpag_boost_tune);
703 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
704 e->radio_tx1_pada_boost_tune);
705 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
706 e->radio_tx1_padg_boost_tune);
707 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
708 e->radio_tx1_pgaa_boost_tune);
709 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
710 e->radio_tx1_pgag_boost_tune);
711 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
712 e->radio_tx1_mixa_boost_tune);
713 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
714 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 715}
716
d4814e69
RM		 717/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
718static void b43_radio_2056_setup(struct b43_wldev *dev,
719 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 720{
0581483a 721 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 722 enum ieee80211_band band = b43_current_band(dev->wl);
723 u16 offset;
724 u8 i;
d3d178f0
RM		 725 u16 bias, cbias;
726 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
727 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
036cafe4 728
d4814e69 729 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 730
d4814e69 731 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 732 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
733
734 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
735 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
737 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
738 if (dev->dev->chip_id == 0x4716) {
739 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
740 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
741 } else {
742 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
743 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 744 }
53a6e234 745 }
38646eba
RM		 746 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
747 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
748 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
749 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
750 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
751 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 752 }
53a6e234 753
38646eba
RM		 754 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
755 for (i = 0; i < 2; i++) {
756 offset = i ? B2056_TX1 : B2056_TX0;
757 if (dev->phy.rev >= 5) {
758 b43_radio_write(dev,
759 offset | B2056_TX_PADG_IDAC, 0xcc);
760
761 if (dev->dev->chip_id == 0x4716) {
762 bias = 0x40;
763 cbias = 0x45;
764 pag_boost = 0x5;
765 pgag_boost = 0x33;
766 mixg_boost = 0x55;
767 } else {
768 bias = 0x25;
769 cbias = 0x20;
770 pag_boost = 0x4;
771 pgag_boost = 0x03;
772 mixg_boost = 0x65;
773 }
774 padg_boost = 0x77;
775
776 b43_radio_write(dev,
777 offset | B2056_TX_INTPAG_IMAIN_STAT,
778 bias);
779 b43_radio_write(dev,
780 offset | B2056_TX_INTPAG_IAUX_STAT,
781 bias);
782 b43_radio_write(dev,
783 offset | B2056_TX_INTPAG_CASCBIAS,
784 cbias);
785 b43_radio_write(dev,
786 offset | B2056_TX_INTPAG_BOOST_TUNE,
787 pag_boost);
788 b43_radio_write(dev,
789 offset | B2056_TX_PGAG_BOOST_TUNE,
790 pgag_boost);
791 b43_radio_write(dev,
792 offset | B2056_TX_PADG_BOOST_TUNE,
793 padg_boost);
794 b43_radio_write(dev,
795 offset | B2056_TX_MIXG_BOOST_TUNE,
796 mixg_boost);
797 } else {
798 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
799 b43_radio_write(dev,
800 offset | B2056_TX_INTPAG_IMAIN_STAT,
801 bias);
802 b43_radio_write(dev,
803 offset | B2056_TX_INTPAG_IAUX_STAT,
804 bias);
805 b43_radio_write(dev,
806 offset | B2056_TX_INTPAG_CASCBIAS,
807 0x30);
808 }
809 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
810 }
811 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 812 u16 freq = dev->phy.channel_freq;
813 if (freq < 5100) {
814 paa_boost = 0xA;
815 pada_boost = 0x77;
816 pgaa_boost = 0xF;
817 mixa_boost = 0xF;
818 } else if (freq < 5340) {
819 paa_boost = 0x8;
820 pada_boost = 0x77;
821 pgaa_boost = 0xFB;
822 mixa_boost = 0xF;
823 } else if (freq < 5650) {
824 paa_boost = 0x0;
825 pada_boost = 0x77;
826 pgaa_boost = 0xB;
827 mixa_boost = 0xF;
828 } else {
829 paa_boost = 0x0;
830 pada_boost = 0x77;
831 if (freq != 5825)
832 pgaa_boost = -(freq - 18) / 36 + 168;
833 else
834 pgaa_boost = 6;
835 mixa_boost = 0xF;
836 }
837
838 for (i = 0; i < 2; i++) {
839 offset = i ? B2056_TX1 : B2056_TX0;
840
841 b43_radio_write(dev,
842 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
843 b43_radio_write(dev,
844 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
845 b43_radio_write(dev,
846 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
847 b43_radio_write(dev,
848 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
849 b43_radio_write(dev,
850 offset | B2056_TX_TXSPARE1, 0x30);
851 b43_radio_write(dev,
852 offset | B2056_TX_PA_SPARE2, 0xee);
853 b43_radio_write(dev,
854 offset | B2056_TX_PADA_CASCBIAS, 0x03);
855 b43_radio_write(dev,
856 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
857 b43_radio_write(dev,
858 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
859 b43_radio_write(dev,
860 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
861 }
a2d9bc6f 862 }
38646eba 863
d4814e69
RM		 864 udelay(50);
865 /* VCO calibration */
866 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
867 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
868 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
869 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
870 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
871 udelay(300);
53a6e234
MB		 872}
873
d3d178f0
RM		 874static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
875{
876 struct b43_phy *phy = &dev->phy;
877 u16 mast2, tmp;
878
879 if (phy->rev != 3)
880 return 0;
881
882 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
883 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
884
885 udelay(10);
886 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
887 udelay(10);
888 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
889
890 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
891 1000000)) {
892 b43err(dev->wl, "Radio recalibration timeout\n");
893 return 0;
894 }
895
896 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
897 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
898 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
899
900 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
901
902 return tmp & 0x1f;
903}
904
ea7ee14b
RM		 905static void b43_radio_init2056_pre(struct b43_wldev *dev)
906{
907 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
908 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
909 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
910 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
911 B43_NPHY_RFCTL_CMD_OEPORFORCE);
912 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
913 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
914 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
915 B43_NPHY_RFCTL_CMD_CHIP0PU);
916}
917
918static void b43_radio_init2056_post(struct b43_wldev *dev)
919{
920 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
921 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
922 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
923 msleep(1);
924 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
925 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
926 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 927 if (dev->phy.n->init_por)
928 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 929}
930
d817f4e1
RM		 931/*
932 * Initialize a Broadcom 2056 N-radio
933 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
934 */
935static void b43_radio_init2056(struct b43_wldev *dev)
936{
ea7ee14b
RM		 937 b43_radio_init2056_pre(dev);
938 b2056_upload_inittabs(dev, 0, 0);
939 b43_radio_init2056_post(dev);
d3d178f0
RM		 940
941 dev->phy.n->init_por = false;
d817f4e1
RM		 942}
943
884a5228
RM		 944/**************************************************
945 * Radio 0x2055
946 **************************************************/
947
948static void b43_chantab_radio_upload(struct b43_wldev *dev,
949 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 950{
884a5228
RM		 951 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
952 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
953 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
954 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
955 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 956
884a5228
RM		 957 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
958 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
959 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
960 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
961 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 962
884a5228
RM		 963 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
964 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
965 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
966 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
967 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 968
884a5228
RM		 969 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
970 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
971 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
972 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
973 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 974
884a5228
RM		 975 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
976 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
977 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
978 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
979 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 980
884a5228
RM		 981 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
982 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 983}
984
884a5228
RM		 985/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
986static void b43_radio_2055_setup(struct b43_wldev *dev,
987 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 988{
884a5228 989 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 990
884a5228
RM		 991 b43_chantab_radio_upload(dev, e);
992 udelay(50);
993 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
994 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
995 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
996 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
997 udelay(300);
95b66bad
MB		 998}
999
884a5228 1000static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1001{
884a5228
RM		 1002 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1003 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1004 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1005 B43_NPHY_RFCTL_CMD_CHIP0PU |
1006 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1007 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1008 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1009}
1010
884a5228 1011static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1012{
1013 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1014 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1015 bool workaround = false;
2faa6b83 1016
884a5228
RM		 1017 if (sprom->revision < 4)
1018 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1019 && dev->dev->board_type == 0x46D
1020 && dev->dev->board_rev >= 0x41);
2faa6b83 1021 else
884a5228
RM		 1022 workaround =
1023 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1024
884a5228
RM		 1025 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1026 if (workaround) {
1027 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1028 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1029 }
1030 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1031 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1032 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1033 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1034 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1035 msleep(1);
1036 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1037 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1038 b43err(dev->wl, "radio post init timeout\n");
1039 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1040 b43_switch_channel(dev, dev->phy.channel);
1041 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1042 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1043 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1044 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1045 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1046 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1047 if (!nphy->gain_boost) {
1048 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1049 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1050 } else {
1051 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1052 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1053 }
1054 udelay(2);
2faa6b83
RM		 1055}
1056
884a5228
RM		 1057/*
1058 * Initialize a Broadcom 2055 N-radio
1059 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1060 */
1061static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1062{
884a5228
RM		 1063 b43_radio_init2055_pre(dev);
1064 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1065 /* Follow wl, not specs. Do not force uploading all regs */
1066 b2055_upload_inittab(dev, 0, 0);
a67162ab 1067 } else {
884a5228
RM		 1068 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1069 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1070 }
884a5228 1071 b43_radio_init2055_post(dev);
a67162ab
RM		 1072}
1073
8be89535
RM		 1074/**************************************************
1075 * Samples
1076 **************************************************/
026816fc 1077
8be89535
RM		 1078/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1079static int b43_nphy_load_samples(struct b43_wldev *dev,
1080 struct b43_c32 *samples, u16 len) {
1081 struct b43_phy_n *nphy = dev->phy.n;
1082 u16 i;
1083 u32 *data;
1084
1085 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1086 if (!data) {
1087 b43err(dev->wl, "allocation for samples loading failed\n");
1088 return -ENOMEM;
1089 }
1090 if (nphy->hang_avoid)
1091 b43_nphy_stay_in_carrier_search(dev, 1);
1092
1093 for (i = 0; i < len; i++) {
1094 data[i] = (samples[i].i & 0x3FF << 10);
1095 data[i] |= samples[i].q & 0x3FF;
1096 }
1097 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1098
1099 kfree(data);
1100 if (nphy->hang_avoid)
1101 b43_nphy_stay_in_carrier_search(dev, 0);
1102 return 0;
026816fc
RM		 1103}
1104
8be89535
RM		 1105/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1106static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1107 bool test)
026816fc 1108{
8be89535
RM		 1109 int i;
1110 u16 bw, len, rot, angle;
1111 struct b43_c32 *samples;
026816fc 1112
026816fc 1113
8be89535
RM		 1114 bw = (dev->phy.is_40mhz) ? 40 : 20;
1115 len = bw << 3;
026816fc 1116
8be89535
RM		 1117 if (test) {
1118 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1119 bw = 82;
1120 else
1121 bw = 80;
026816fc 1122
8be89535
RM		 1123 if (dev->phy.is_40mhz)
1124 bw <<= 1;
1125
1126 len = bw << 1;
026816fc
RM		 1127 }
1128
8be89535
RM		 1129 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1130 if (!samples) {
1131 b43err(dev->wl, "allocation for samples generation failed\n");
1132 return 0;
1133 }
1134 rot = (((freq * 36) / bw) << 16) / 100;
1135 angle = 0;
026816fc 1136
8be89535
RM		 1137 for (i = 0; i < len; i++) {
1138 samples[i] = b43_cordic(angle);
1139 angle += rot;
1140 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1141 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1142 }
8be89535
RM		 1143
1144 i = b43_nphy_load_samples(dev, samples, len);
1145 kfree(samples);
1146 return (i < 0) ? 0 : len;
026816fc
RM		 1147}
1148
8be89535
RM		 1149/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1150static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1151 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1152{
8be89535 1153 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1154 int i;
8be89535
RM		 1155 u16 seq_mode;
1156 u32 tmp;
34a56f2c 1157
8be89535
RM		 1158 if (nphy->hang_avoid)
1159 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1160
8be89535
RM		 1161 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1162 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1163 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1164 }
34a56f2c 1165
8be89535
RM		 1166 if (!dev->phy.is_40mhz)
1167 tmp = 0x6464;
1168 else
1169 tmp = 0x4747;
1170 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1171
8be89535
RM		 1172 if (nphy->hang_avoid)
1173 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c 1174
8be89535 1175 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1176
8be89535
RM		 1177 if (loops != 0xFFFF)
1178 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1179 else
1180 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1181
8be89535 1182 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1183
8be89535 1184 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1185
8be89535
RM		 1186 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1187 if (iqmode) {
1188 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1189 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1190 } else {
1191 if (dac_test)
1192 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1193 else
1194 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1195 }
1196 for (i = 0; i < 100; i++) {
2c8ac7eb 1197 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1198 i = 0;
1199 break;
34a56f2c 1200 }
8be89535 1201 udelay(10);
34a56f2c 1202 }
8be89535
RM		 1203 if (i)
1204 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1205
8be89535 1206 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
34a56f2c
RM		 1207}
1208
4d9f46ba
RM		 1209/**************************************************
1210 * RSSI
1211 **************************************************/
1212
1213/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1214static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1215 s8 offset, u8 core,
1216 enum n_rail_type rail,
e5ab1fd7 1217 enum b43_nphy_rssi_type rssi_type)
09146400 1218{
4d9f46ba
RM		 1219 u16 tmp;
1220 bool core1or5 = (core == 1) || (core == 5);
1221 bool core2or5 = (core == 2) || (core == 5);
09146400 1222
4d9f46ba
RM		 1223 offset = clamp_val(offset, -32, 31);
1224 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1225
e5ab1fd7
RM		 1226 switch (rssi_type) {
1227 case B43_NPHY_RSSI_Z:
1228 if (core1or5 && rail == N_RAIL_I)
1229 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1230 if (core1or5 && rail == N_RAIL_Q)
1231 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1232 if (core2or5 && rail == N_RAIL_I)
1233 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1234 if (core2or5 && rail == N_RAIL_Q)
1235 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1236 break;
1237 case B43_NPHY_RSSI_X:
1238 if (core1or5 && rail == N_RAIL_I)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1240 if (core1or5 && rail == N_RAIL_Q)
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1242 if (core2or5 && rail == N_RAIL_I)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1244 if (core2or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1246 break;
1247 case B43_NPHY_RSSI_Y:
1248 if (core1or5 && rail == N_RAIL_I)
1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1250 if (core1or5 && rail == N_RAIL_Q)
1251 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1252 if (core2or5 && rail == N_RAIL_I)
1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1254 if (core2or5 && rail == N_RAIL_Q)
1255 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1256 break;
1257 case B43_NPHY_RSSI_TBD:
1258 if (core1or5 && rail == N_RAIL_I)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1260 if (core1or5 && rail == N_RAIL_Q)
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1262 if (core2or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1264 if (core2or5 && rail == N_RAIL_Q)
1265 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1266 break;
1267 case B43_NPHY_RSSI_PWRDET:
1268 if (core1or5 && rail == N_RAIL_I)
1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1270 if (core1or5 && rail == N_RAIL_Q)
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1272 if (core2or5 && rail == N_RAIL_I)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1274 if (core2or5 && rail == N_RAIL_Q)
1275 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1276 break;
1277 case B43_NPHY_RSSI_TSSI_I:
1278 if (core1or5)
1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1280 if (core2or5)
1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1282 break;
1283 case B43_NPHY_RSSI_TSSI_Q:
1284 if (core1or5)
1285 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1286 if (core2or5)
1287 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1288 break;
1289 }
8987a9e9
RM		 1290}
1291
4d9f46ba 1292static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
bbec398c 1293{
4d9f46ba
RM		 1294 u8 i;
1295 u16 reg, val;
bbec398c 1296
4d9f46ba
RM		 1297 if (code == 0) {
1298 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1299 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1300 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1301 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1302 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1303 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1304 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1305 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1306 } else {
1307 for (i = 0; i < 2; i++) {
1308 if ((code == 1 && i == 1) || (code == 2 && !i))
1309 continue;
bbec398c 1310
4d9f46ba
RM		 1311 reg = (i == 0) ?
1312 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1313 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1314
4d9f46ba
RM		 1315 if (type < 3) {
1316 reg = (i == 0) ?
1317 B43_NPHY_AFECTL_C1 :
1318 B43_NPHY_AFECTL_C2;
1319 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1320
4d9f46ba
RM		 1321 reg = (i == 0) ?
1322 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1323 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1324 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1325
4d9f46ba
RM		 1326 if (type == 0)
1327 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1328 else if (type == 1)
1329 val = 16;
1330 else
1331 val = 32;
1332 b43_phy_set(dev, reg, val);
5c1a140a 1333
4d9f46ba
RM		 1334 reg = (i == 0) ?
1335 B43_NPHY_TXF_40CO_B1S0 :
1336 B43_NPHY_TXF_40CO_B32S1;
1337 b43_phy_set(dev, reg, 0x0020);
1338 } else {
1339 if (type == 6)
1340 val = 0x0100;
1341 else if (type == 3)
1342 val = 0x0200;
1343 else
1344 val = 0x0300;
5c1a140a 1345
4d9f46ba
RM		 1346 reg = (i == 0) ?
1347 B43_NPHY_AFECTL_C1 :
1348 B43_NPHY_AFECTL_C2;
53ae8e8c 1349
4d9f46ba
RM		 1350 b43_phy_maskset(dev, reg, 0xFCFF, val);
1351 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1352
4d9f46ba
RM		 1353 if (type != 3 && type != 6) {
1354 enum ieee80211_band band =
1355 b43_current_band(dev->wl);
53ae8e8c 1356
4d9f46ba
RM		 1357 if (b43_nphy_ipa(dev))
1358 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1359 else
1360 val = 0x11;
1361 reg = (i == 0) ? 0x2000 : 0x3000;
1362 reg |= B2055_PADDRV;
1363 b43_radio_write16(dev, reg, val);
53ae8e8c 1364
4d9f46ba
RM		 1365 reg = (i == 0) ?
1366 B43_NPHY_AFECTL_OVER1 :
1367 B43_NPHY_AFECTL_OVER;
1368 b43_phy_set(dev, reg, 0x0200);
1369 }
1370 }
1371 }
53ae8e8c 1372 }
53ae8e8c
RM		 1373}
1374
4d9f46ba 1375static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
9442e5b5 1376{
4d9f46ba 1377 u16 val;
9442e5b5 1378
4d9f46ba
RM		 1379 if (type < 3)
1380 val = 0;
1381 else if (type == 6)
1382 val = 1;
1383 else if (type == 3)
1384 val = 2;
1385 else
1386 val = 3;
9442e5b5 1387
4d9f46ba
RM		 1388 val = (val << 12) | (val << 14);
1389 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1390 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1391
4d9f46ba
RM		 1392 if (type < 3) {
1393 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1394 (type + 1) << 4);
1395 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1396 (type + 1) << 4);
9442e5b5
RM		 1397 }
1398
4d9f46ba
RM		 1399 if (code == 0) {
1400 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1401 if (type < 3) {
1402 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1403 ~(B43_NPHY_RFCTL_CMD_RXEN |
1404 B43_NPHY_RFCTL_CMD_CORESEL));
1405 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1406 ~(0x1 << 12 |
1407 0x1 << 5 |
1408 0x1 << 1 |
1409 0x1));
1410 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1411 ~B43_NPHY_RFCTL_CMD_START);
1412 udelay(20);
1413 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1414 }
1415 } else {
1416 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1417 if (type < 3) {
1418 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1419 ~(B43_NPHY_RFCTL_CMD_RXEN |
1420 B43_NPHY_RFCTL_CMD_CORESEL),
1421 (B43_NPHY_RFCTL_CMD_RXEN |
1422 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1423 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1424 (0x1 << 12 |
1425 0x1 << 5 |
1426 0x1 << 1 |
1427 0x1));
1428 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1429 B43_NPHY_RFCTL_CMD_START);
1430 udelay(20);
1431 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1432 }
9442e5b5 1433 }
9442e5b5
RM		 1434}
1435
4d9f46ba
RM		 1436/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1437static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
d24019ad 1438{
4d9f46ba
RM		 1439 if (dev->phy.rev >= 3)
1440 b43_nphy_rev3_rssi_select(dev, code, type);
1441 else
1442 b43_nphy_rev2_rssi_select(dev, code, type);
1443}
d24019ad 1444
5ecab603
RM		 1445/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1446static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1447{
1448 int i;
d24019ad 1449 for (i = 0; i < 2; i++) {
5ecab603
RM		 1450 if (type == 2) {
1451 if (i == 0) {
1452 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1453 0xFC, buf[0]);
1454 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1455 0xFC, buf[1]);
1456 } else {
1457 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1458 0xFC, buf[2 * i]);
1459 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1460 0xFC, buf[2 * i + 1]);
1461 }
d24019ad 1462 } else {
5ecab603
RM		 1463 if (i == 0)
1464 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1465 0xF3, buf[0] << 2);
1466 else
1467 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1468 0xF3, buf[2 * i + 1] << 2);
d24019ad 1469 }
d24019ad 1470 }
d24019ad
RM		 1471}
1472
5ecab603
RM		 1473/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1474static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1475 u8 nsamp)
ef5127a4 1476{
5ecab603
RM		 1477 int i;
1478 int out;
1479 u16 save_regs_phy[9];
1480 u16 s[2];
ef5127a4
RM		 1481
1482 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1483 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1484 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1485 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1486 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1487 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1488 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1489 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1490 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1491 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1492 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1493 save_regs_phy[8] = 0;
ef5127a4 1494 } else {
5ecab603
RM		 1495 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1496 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1497 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1498 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1499 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1500 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1501 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1502 save_regs_phy[7] = 0;
1503 save_regs_phy[8] = 0;
1504 }
ef5127a4 1505
5ecab603 1506 b43_nphy_rssi_select(dev, 5, type);
ef5127a4 1507
5ecab603
RM		 1508 if (dev->phy.rev < 2) {
1509 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1510 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1511 }
ef5127a4 1512
5ecab603
RM		 1513 for (i = 0; i < 4; i++)
1514 buf[i] = 0;
1515
1516 for (i = 0; i < nsamp; i++) {
1517 if (dev->phy.rev < 2) {
1518 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1519 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1520 } else {
5ecab603
RM		 1521 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1522 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1523 }
1524
5ecab603
RM		 1525 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1526 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1527 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1528 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1529 }
1530 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1531 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1532
5ecab603
RM		 1533 if (dev->phy.rev < 2)
1534 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1535
5ecab603 1536 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1537 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1538 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1539 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1540 save_regs_phy[2]);
5ecab603 1541 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1542 save_regs_phy[3]);
5ecab603
RM		 1543 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1544 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1545 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1546 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1547 } else {
1548 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1549 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1550 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1551 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1552 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1553 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1554 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1555 }
ef5127a4 1556
5ecab603
RM		 1557 return out;
1558}
ef5127a4 1559
e0c9a021
RM		 1560/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1561static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1562{
1563 struct b43_phy_n *nphy = dev->phy.n;
1564
1565 u16 saved_regs_phy_rfctl[2];
1566 u16 saved_regs_phy[13];
1567 u16 regs_to_store[] = {
1568 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1569 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1570 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1571 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1572 B43_NPHY_RFCTL_CMD,
1573 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1574 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1575 };
1576
1577 u16 class;
1578
1579 u16 clip_state[2];
1580 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1581
1582 u8 vcm_final = 0;
2e1253d6 1583 s32 offset[4];
e0c9a021
RM		 1584 s32 results[8][4] = { };
1585 s32 results_min[4] = { };
1586 s32 poll_results[4] = { };
1587
1588 u16 *rssical_radio_regs = NULL;
1589 u16 *rssical_phy_regs = NULL;
1590
1591 u16 r; /* routing */
1592 u8 rx_core_state;
37859a75 1593 int core, i, j, vcm;
e0c9a021
RM		 1594
1595 class = b43_nphy_classifier(dev, 0, 0);
1596 b43_nphy_classifier(dev, 7, 4);
1597 b43_nphy_read_clip_detection(dev, clip_state);
1598 b43_nphy_write_clip_detection(dev, clip_off);
1599
1600 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1601 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1602 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1603 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1604
1605 b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1606 b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1607 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1608 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1609 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1610 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1611
1612 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1613 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1614 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1615 } else {
1616 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1617 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1618 }
1619
1620 rx_core_state = b43_nphy_get_rx_core_state(dev);
1621 for (core = 0; core < 2; core++) {
1622 if (!(rx_core_state & (1 << core)))
1623 continue;
1624 r = core ? B2056_RX1 : B2056_RX0;
6aa38725
RM		 1625 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, 2);
1626 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, 2);
37859a75
RM		 1627
1628 /* Grab RSSI results for every possible VCM */
1629 for (vcm = 0; vcm < 8; vcm++) {
e0c9a021 1630 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
37859a75
RM		 1631 vcm << 2);
1632 b43_nphy_poll_rssi(dev, 2, results[vcm], 8);
e0c9a021 1633 }
37859a75
RM		 1634
1635 /* Find out which VCM got the best results */
cddec902 1636 for (i = 0; i < 4; i += 2) {
37859a75 1637 s32 currd;
e67dd874 1638 s32 mind = 0x100000;
e0c9a021
RM		 1639 s32 minpoll = 249;
1640 u8 minvcm = 0;
1641 if (2 * core != i)
1642 continue;
37859a75
RM		 1643 for (vcm = 0; vcm < 8; vcm++) {
1644 currd = results[vcm][i] * results[vcm][i] +
1645 results[vcm][i + 1] * results[vcm][i];
1646 if (currd < mind) {
1647 mind = currd;
1648 minvcm = vcm;
e0c9a021 1649 }
37859a75
RM		 1650 if (results[vcm][i] < minpoll)
1651 minpoll = results[vcm][i];
e0c9a021
RM		 1652 }
1653 vcm_final = minvcm;
1654 results_min[i] = minpoll;
1655 }
37859a75
RM		 1656
1657 /* Select the best VCM */
e0c9a021
RM		 1658 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1659 vcm_final << 2);
37859a75 1660
e0c9a021
RM		 1661 for (i = 0; i < 4; i++) {
1662 if (core != i / 2)
1663 continue;
1664 offset[i] = -results[vcm_final][i];
1665 if (offset[i] < 0)
1666 offset[i] = -((abs(offset[i]) + 4) / 8);
1667 else
1668 offset[i] = (offset[i] + 4) / 8;
1669 if (results_min[i] == 248)
1670 offset[i] = -32;
1671 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1672 (i / 2 == 0) ? 1 : 2,
6aa38725 1673 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
e0c9a021
RM		 1674 2);
1675 }
1676 }
37859a75 1677
e0c9a021
RM		 1678 for (core = 0; core < 2; core++) {
1679 if (!(rx_core_state & (1 << core)))
1680 continue;
1681 for (i = 0; i < 2; i++) {
6aa38725
RM		 1682 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1683 N_RAIL_I, i);
1684 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1685 N_RAIL_Q, i);
e0c9a021
RM		 1686 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1687 for (j = 0; j < 4; j++) {
cddec902 1688 if (j / 2 == core) {
e0c9a021 1689 offset[j] = 232 - poll_results[j];
cddec902
RM		 1690 if (offset[j] < 0)
1691 offset[j] = -(abs(offset[j] + 4) / 8);
1692 else
1693 offset[j] = (offset[j] + 4) / 8;
1694 b43_nphy_scale_offset_rssi(dev, 0,
1695 offset[2 * core], core + 1, j % 2, i);
1696 }
e0c9a021
RM		 1697 }
1698 }
1699 }
1700
1701 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1702 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1703
1704 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1705
1706 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1707 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1708 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1709
1710 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1711 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1712 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1713
1714 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1715 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1716
1717 /* Store for future configuration */
1718 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1719 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1720 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1721 } else {
1722 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1723 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1724 }
1725 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1726 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1727 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1728 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1729 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1730 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1731 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1732 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1733 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1734 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1735 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1736 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1737 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1738 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1739
1740 /* Remember for which channel we store configuration */
1741 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1742 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1743 else
1744 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1745
1746 /* End of calibration, restore configuration */
1747 b43_nphy_classifier(dev, 7, class);
1748 b43_nphy_write_clip_detection(dev, clip_state);
1749}
1750
5ecab603
RM		 1751/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1752static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1753{
37859a75 1754 int i, j, vcm;
5ecab603
RM		 1755 u8 state[4];
1756 u8 code, val;
1757 u16 class, override;
1758 u8 regs_save_radio[2];
1759 u16 regs_save_phy[2];
1760
2e1253d6 1761 s32 offset[4];
5ecab603
RM		 1762 u8 core;
1763 u8 rail;
1764
1765 u16 clip_state[2];
1766 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1767 s32 results_min[4] = { };
1768 u8 vcm_final[4] = { };
1769 s32 results[4][4] = { };
1770 s32 miniq[4][2] = { };
1771
1772 if (type == 2) {
1773 code = 0;
1774 val = 6;
1775 } else if (type < 2) {
1776 code = 25;
1777 val = 4;
1778 } else {
1779 B43_WARN_ON(1);
1780 return;
1781 }
1782
1783 class = b43_nphy_classifier(dev, 0, 0);
1784 b43_nphy_classifier(dev, 7, 4);
1785 b43_nphy_read_clip_detection(dev, clip_state);
1786 b43_nphy_write_clip_detection(dev, clip_off);
1787
1788 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1789 override = 0x140;
1790 else
1791 override = 0x110;
1792
1793 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1794 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1795 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1796 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1797
1798 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1799 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1800 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1801 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1802
1803 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1804 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1805 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1806 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1807 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1808 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1809
1810 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1811 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1812 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1813
37859a75 1814 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1815 u8 tmp[4];
1816 for (j = 0; j < 4; j++)
37859a75 1817 tmp[j] = vcm;
5ecab603
RM		 1818 if (type != 1)
1819 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1820 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
5ecab603
RM		 1821 if (type < 2)
1822 for (j = 0; j < 2; j++)
37859a75
RM		 1823 miniq[vcm][j] = min(results[vcm][2 * j],
1824 results[vcm][2 * j + 1]);
5ecab603
RM		 1825 }
1826
1827 for (i = 0; i < 4; i++) {
e67dd874 1828 s32 mind = 0x100000;
5ecab603
RM		 1829 u8 minvcm = 0;
1830 s32 minpoll = 249;
37859a75
RM		 1831 s32 currd;
1832 for (vcm = 0; vcm < 4; vcm++) {
5ecab603 1833 if (type == 2)
37859a75 1834 currd = abs(results[vcm][i]);
5ecab603 1835 else
37859a75 1836 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1837
37859a75
RM		 1838 if (currd < mind) {
1839 mind = currd;
1840 minvcm = vcm;
5ecab603
RM		 1841 }
1842
37859a75
RM		 1843 if (results[vcm][i] < minpoll)
1844 minpoll = results[vcm][i];
8e60b044 1845 }
5ecab603
RM		 1846 results_min[i] = minpoll;
1847 vcm_final[i] = minvcm;
1848 }
ef5127a4 1849
5ecab603
RM		 1850 if (type != 1)
1851 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 1852
5ecab603
RM		 1853 for (i = 0; i < 4; i++) {
1854 offset[i] = (code * 8) - results[vcm_final[i]][i];
1855
1856 if (offset[i] < 0)
1857 offset[i] = -((abs(offset[i]) + 4) / 8);
1858 else
1859 offset[i] = (offset[i] + 4) / 8;
1860
1861 if (results_min[i] == 248)
1862 offset[i] = code - 32;
1863
1864 core = (i / 2) ? 2 : 1;
6aa38725 1865 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 1866
1867 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1868 type);
1869 }
1870
1871 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1872 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1873
1874 switch (state[2]) {
1875 case 1:
1876 b43_nphy_rssi_select(dev, 1, 2);
1877 break;
1878 case 4:
1879 b43_nphy_rssi_select(dev, 1, 0);
1880 break;
1881 case 2:
1882 b43_nphy_rssi_select(dev, 1, 1);
1883 break;
1884 default:
1885 b43_nphy_rssi_select(dev, 1, 1);
1886 break;
1887 }
1888
1889 switch (state[3]) {
1890 case 1:
1891 b43_nphy_rssi_select(dev, 2, 2);
1892 break;
1893 case 4:
1894 b43_nphy_rssi_select(dev, 2, 0);
1895 break;
1896 default:
1897 b43_nphy_rssi_select(dev, 2, 1);
1898 break;
1899 }
1900
1901 b43_nphy_rssi_select(dev, 0, type);
1902
1903 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1904 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1905 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1906 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1907
1908 b43_nphy_classifier(dev, 7, class);
1909 b43_nphy_write_clip_detection(dev, clip_state);
1910 /* Specs don't say about reset here, but it makes wl and b43 dumps
1911 identical, it really seems wl performs this */
1912 b43_nphy_reset_cca(dev);
1913}
1914
5ecab603
RM		 1915/*
1916 * RSSI Calibration
1917 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1918 */
1919static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1920{
1921 if (dev->phy.rev >= 3) {
1922 b43_nphy_rev3_rssi_cal(dev);
1923 } else {
1924 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1925 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1926 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1927 }
1928}
1929
64712095
RM		 1930/**************************************************
1931 * Workarounds
1932 **************************************************/
1933
1934static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1935{
1936 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1937
1938 bool ghz5;
1939 bool ext_lna;
1940 u16 rssi_gain;
1941 struct nphy_gain_ctl_workaround_entry *e;
1942 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1943 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1944
1945 /* Prepare values */
1946 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1947 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 1948 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1949 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 1950 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1951 if (ghz5 && dev->phy.rev >= 5)
1952 rssi_gain = 0x90;
1953 else
1954 rssi_gain = 0x50;
1955
1956 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1957
1958 /* Set Clip 2 detect */
1959 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1960 B43_NPHY_C1_CGAINI_CL2DETECT);
1961 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1962 B43_NPHY_C2_CGAINI_CL2DETECT);
1963
1964 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1965 0x17);
1966 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1967 0x17);
1968 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1969 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1970 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1971 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1972 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1973 rssi_gain);
1974 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1975 rssi_gain);
1976 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1977 0x17);
1978 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1979 0x17);
1980 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1981 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1982
1983 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1984 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1985 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1986 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1987 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1988 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1989 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1990 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1991 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1992 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1993 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1994 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1995
1996 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1997 b43_phy_write(dev, 0x2A7, e->init_gain);
1998 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1999 e->rfseq_init);
64712095
RM		 2000
2001 /* TODO: check defines. Do not match variables names */
2002 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
2003 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
2004 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
2005 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
2006 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
2007 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
2008
2009 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
2010 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
2011 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
2012 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2013 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2014 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2015 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2016 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2017 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2018 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2019}
2020
2021static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2022{
2023 struct b43_phy_n *nphy = dev->phy.n;
2024
2025 u8 i, j;
2026 u8 code;
2027 u16 tmp;
2028 u8 rfseq_events[3] = { 6, 8, 7 };
2029 u8 rfseq_delays[3] = { 10, 30, 1 };
2030
2031 /* Set Clip 2 detect */
2032 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2033 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2034
2035 /* Set narrowband clip threshold */
2036 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2037 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2038
2039 if (!dev->phy.is_40mhz) {
2040 /* Set dwell lengths */
2041 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2042 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2043 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2044 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2045 }
2046
2047 /* Set wideband clip 2 threshold */
2048 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2049 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2050 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2051 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2052
2053 if (!dev->phy.is_40mhz) {
2054 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2055 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2056 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2057 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2058 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2059 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2060 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2061 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2062 }
2063
2064 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2065
2066 if (nphy->gain_boost) {
2067 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2068 dev->phy.is_40mhz)
2069 code = 4;
2070 else
2071 code = 5;
2072 } else {
2073 code = dev->phy.is_40mhz ? 6 : 7;
2074 }
2075
2076 /* Set HPVGA2 index */
2077 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2078 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2079 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2080 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2081
2082 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2083 /* specs say about 2 loops, but wl does 4 */
2084 for (i = 0; i < 4; i++)
2085 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2086
2087 b43_nphy_adjust_lna_gain_table(dev);
2088
2089 if (nphy->elna_gain_config) {
2090 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2091 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2092 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2093 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2094 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2095
2096 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2097 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2098 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2099 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2100 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2101
2102 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2103 /* specs say about 2 loops, but wl does 4 */
2104 for (i = 0; i < 4; i++)
2105 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2106 (code << 8 | 0x74));
2107 }
2108
2109 if (dev->phy.rev == 2) {
2110 for (i = 0; i < 4; i++) {
2111 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2112 (0x0400 * i) + 0x0020);
2113 for (j = 0; j < 21; j++) {
2114 tmp = j * (i < 2 ? 3 : 1);
2115 b43_phy_write(dev,
2116 B43_NPHY_TABLE_DATALO, tmp);
2117 }
2118 }
ef5127a4 2119 }
64712095
RM		 2120
2121 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2122 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2123 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2124 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2125
2126 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2127 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2128}
2129
2130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2131static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2132{
d11d354b
RM		 2133 if (dev->phy.rev >= 7)
2134 ; /* TODO */
2135 else if (dev->phy.rev >= 3)
64712095
RM		 2136 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2137 else
2138 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2139}
2140
d11d354b
RM		 2141/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2142static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2143{
2144 if (!offset)
2145 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2146 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2147}
2148
2149static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2150{
2151 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2152 struct b43_phy *phy = &dev->phy;
2153
2154 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2155 0x1F };
2156 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2157
2158 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2159 u8 ntab7_138_146[] = { 0x11, 0x11 };
2160 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2161
2162 u16 lpf_20, lpf_40, lpf_11b;
2163 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2164 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2165 bool rccal_ovrd = false;
2166
2167 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2168 u16 bias, conv, filt;
2169
2170 u32 tmp32;
2171 u8 core;
2172
2173 if (phy->rev == 7) {
2174 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2175 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2176 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2177 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2178 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2179 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2180 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2181 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2182 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2183 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2184 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2185 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2186 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2187 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2188 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2189 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2190 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2191 }
2192 if (phy->rev <= 8) {
2193 b43_phy_write(dev, 0x23F, 0x1B0);
2194 b43_phy_write(dev, 0x240, 0x1B0);
2195 }
2196 if (phy->rev >= 8)
2197 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2198
2199 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2200 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2201 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2202 tmp32 &= 0xffffff;
2203 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2204 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2205 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2206
2207 if (b43_nphy_ipa(dev))
2208 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2209 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2210
2211 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2212 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2213
2214 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2215 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2216 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2217 if (b43_nphy_ipa(dev)) {
2218 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2219 phy->radio_rev == 7 || phy->radio_rev == 8) {
2220 bcap_val = b43_radio_read(dev, 0x16b);
2221 scap_val = b43_radio_read(dev, 0x16a);
2222 scap_val_11b = scap_val;
2223 bcap_val_11b = bcap_val;
2224 if (phy->radio_rev == 5 && phy->is_40mhz) {
2225 scap_val_11n_20 = scap_val;
2226 bcap_val_11n_20 = bcap_val;
2227 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2228 rccal_ovrd = true;
2229 } else { /* Rev 7/8 */
2230 lpf_20 = 4;
2231 lpf_11b = 1;
2232 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2233 scap_val_11n_20 = 0xc;
2234 bcap_val_11n_20 = 0xc;
2235 scap_val_11n_40 = 0xa;
2236 bcap_val_11n_40 = 0xa;
2237 } else {
2238 scap_val_11n_20 = 0x14;
2239 bcap_val_11n_20 = 0x14;
2240 scap_val_11n_40 = 0xf;
2241 bcap_val_11n_40 = 0xf;
2242 }
2243 rccal_ovrd = true;
2244 }
2245 }
2246 } else {
2247 if (phy->radio_rev == 5) {
2248 lpf_20 = 1;
2249 lpf_40 = 3;
2250 bcap_val = b43_radio_read(dev, 0x16b);
2251 scap_val = b43_radio_read(dev, 0x16a);
2252 scap_val_11b = scap_val;
2253 bcap_val_11b = bcap_val;
2254 scap_val_11n_20 = 0x11;
2255 scap_val_11n_40 = 0x11;
2256 bcap_val_11n_20 = 0x13;
2257 bcap_val_11n_40 = 0x13;
2258 rccal_ovrd = true;
2259 }
2260 }
2261 if (rccal_ovrd) {
2262 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2263 (scap_val_11b << 3) |
2264 lpf_11b;
2265 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2266 (scap_val_11n_20 << 3) |
2267 lpf_20;
2268 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2269 (scap_val_11n_40 << 3) |
2270 lpf_40;
2271 for (core = 0; core < 2; core++) {
2272 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2273 rx2tx_lut_20_11b);
2274 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2275 rx2tx_lut_20_11n);
2276 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2277 rx2tx_lut_20_11n);
2278 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2279 rx2tx_lut_40_11n);
2280 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2281 rx2tx_lut_40_11n);
2282 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2283 rx2tx_lut_40_11n);
2284 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2285 rx2tx_lut_40_11n);
2286 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2287 rx2tx_lut_40_11n);
2288 }
c071b9f6 2289 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2290 }
2291 b43_phy_write(dev, 0x32F, 0x3);
2292 if (phy->radio_rev == 4 || phy->radio_rev == 6)
c071b9f6 2293 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2294
2295 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2296 if (sprom->revision &&
2297 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2298 b43_radio_write(dev, 0x5, 0x05);
2299 b43_radio_write(dev, 0x6, 0x30);
2300 b43_radio_write(dev, 0x7, 0x00);
2301 b43_radio_set(dev, 0x4f, 0x1);
2302 b43_radio_set(dev, 0xd4, 0x1);
2303 bias = 0x1f;
2304 conv = 0x6f;
2305 filt = 0xaa;
2306 } else {
2307 bias = 0x2b;
2308 conv = 0x7f;
2309 filt = 0xee;
2310 }
2311 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2312 for (core = 0; core < 2; core++) {
2313 if (core == 0) {
2314 b43_radio_write(dev, 0x5F, bias);
2315 b43_radio_write(dev, 0x64, conv);
2316 b43_radio_write(dev, 0x66, filt);
2317 } else {
2318 b43_radio_write(dev, 0xE8, bias);
2319 b43_radio_write(dev, 0xE9, conv);
2320 b43_radio_write(dev, 0xEB, filt);
2321 }
2322 }
2323 }
2324 }
2325
2326 if (b43_nphy_ipa(dev)) {
2327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2328 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2329 phy->radio_rev == 6) {
2330 for (core = 0; core < 2; core++) {
2331 if (core == 0)
2332 b43_radio_write(dev, 0x51,
2333 0x7f);
2334 else
2335 b43_radio_write(dev, 0xd6,
2336 0x7f);
2337 }
2338 }
2339 if (phy->radio_rev == 3) {
2340 for (core = 0; core < 2; core++) {
2341 if (core == 0) {
2342 b43_radio_write(dev, 0x64,
2343 0x13);
2344 b43_radio_write(dev, 0x5F,
2345 0x1F);
2346 b43_radio_write(dev, 0x66,
2347 0xEE);
2348 b43_radio_write(dev, 0x59,
2349 0x8A);
2350 b43_radio_write(dev, 0x80,
2351 0x3E);
2352 } else {
2353 b43_radio_write(dev, 0x69,
2354 0x13);
2355 b43_radio_write(dev, 0xE8,
2356 0x1F);
2357 b43_radio_write(dev, 0xEB,
2358 0xEE);
2359 b43_radio_write(dev, 0xDE,
2360 0x8A);
2361 b43_radio_write(dev, 0x105,
2362 0x3E);
2363 }
2364 }
2365 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2366 if (!phy->is_40mhz) {
2367 b43_radio_write(dev, 0x5F, 0x14);
2368 b43_radio_write(dev, 0xE8, 0x12);
2369 } else {
2370 b43_radio_write(dev, 0x5F, 0x16);
2371 b43_radio_write(dev, 0xE8, 0x16);
2372 }
2373 }
2374 } else {
2375 u16 freq = phy->channel_freq;
2376 if ((freq >= 5180 && freq <= 5230) ||
2377 (freq >= 5745 && freq <= 5805)) {
2378 b43_radio_write(dev, 0x7D, 0xFF);
2379 b43_radio_write(dev, 0xFE, 0xFF);
2380 }
2381 }
2382 } else {
2383 if (phy->radio_rev != 5) {
2384 for (core = 0; core < 2; core++) {
2385 if (core == 0) {
2386 b43_radio_write(dev, 0x5c, 0x61);
2387 b43_radio_write(dev, 0x51, 0x70);
2388 } else {
2389 b43_radio_write(dev, 0xe1, 0x61);
2390 b43_radio_write(dev, 0xd6, 0x70);
2391 }
2392 }
2393 }
2394 }
2395
2396 if (phy->radio_rev == 4) {
2397 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2398 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2399 for (core = 0; core < 2; core++) {
2400 if (core == 0) {
2401 b43_radio_write(dev, 0x1a1, 0x00);
2402 b43_radio_write(dev, 0x1a2, 0x3f);
2403 b43_radio_write(dev, 0x1a6, 0x3f);
2404 } else {
2405 b43_radio_write(dev, 0x1a7, 0x00);
2406 b43_radio_write(dev, 0x1ab, 0x3f);
2407 b43_radio_write(dev, 0x1ac, 0x3f);
2408 }
2409 }
2410 } else {
2411 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2412 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2413 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2414 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2415
2416 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2417 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2418 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2419 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2420 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2421 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2422
2423 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2424 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2425 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2426 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2427 }
2428
2429 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2430
2431 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2432 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2433 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2434 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2435 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2436 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2437 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2438
2439 if (!phy->is_40mhz) {
2440 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2441 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2442 } else {
2443 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2444 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2445 }
2446
2447 b43_nphy_gain_ctl_workarounds(dev);
2448
2449 /* TODO
2450 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2451 aux_adc_vmid_rev7_core0);
2452 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2453 aux_adc_vmid_rev7_core1);
2454 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2455 aux_adc_gain_rev7);
2456 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2457 aux_adc_gain_rev7);
2458 */
2459}
2460
73d07a39 2461static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2462{
0eff8fcd 2463 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2464 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2465
0eff8fcd 2466 /* TX to RX */
c56da252
RM		 2467 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2468 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
0eff8fcd
RM		 2469 /* RX to TX */
2470 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2471 0x1F };
2472 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2473 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2474 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2475
ba9a6214
RM		 2476 u16 tmp16;
2477 u32 tmp32;
2478
c56da252
RM		 2479 b43_phy_write(dev, 0x23f, 0x1f8);
2480 b43_phy_write(dev, 0x240, 0x1f8);
2481
73d07a39
RM		 2482 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2483 tmp32 &= 0xffffff;
2484 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2485
73d07a39
RM		 2486 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2487 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2488 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2489 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2490 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2491 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2492
73d07a39
RM		 2493 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2494 b43_phy_write(dev, 0x2AE, 0x000C);
ba9a6214 2495
0eff8fcd 2496 /* TX to RX */
c56da252
RM		 2497 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2498 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2499
2500 /* RX to TX */
2501 if (b43_nphy_ipa(dev))
c56da252
RM		 2502 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2503 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2504 if (nphy->hw_phyrxchain != 3 &&
2505 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2506 if (b43_nphy_ipa(dev)) {
2507 rx2tx_delays[5] = 59;
2508 rx2tx_delays[6] = 1;
2509 rx2tx_events[7] = 0x1F;
2510 }
fa0f2b38 2511 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2512 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2513 }
ba9a6214 2514
73d07a39
RM		 2515 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2516 0x2 : 0x9C40;
2517 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2518
73d07a39 2519 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
ba9a6214 2520
fa0f2b38
RM		 2521 if (!dev->phy.is_40mhz) {
2522 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2523 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2524 } else {
2525 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2526 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2527 }
ba9a6214 2528
3ccd0957 2529 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2530
c56da252
RM		 2531 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2532 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2533
73d07a39 2534 /* TODO */
ba9a6214 2535
73d07a39
RM		 2536 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2537 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2538 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2539 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2540 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2541 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2542 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2543 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2544 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2545 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2546 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2547 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2548
2549 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2550
2551 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2552 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2553 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2554 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2555 tmp32 = 0x00088888;
2556 else
2557 tmp32 = 0x88888888;
2558 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2559 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2560 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2561
2562 if (dev->phy.rev == 4 &&
fa0f2b38 2563 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2564 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2565 0x70);
2566 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2567 0x70);
2568 }
ba9a6214 2569
fa0f2b38 2570 /* Dropped probably-always-true condition */
3c17dd41
RM		 2571 b43_phy_write(dev, 0x224, 0x03eb);
2572 b43_phy_write(dev, 0x225, 0x03eb);
2573 b43_phy_write(dev, 0x226, 0x0341);
2574 b43_phy_write(dev, 0x227, 0x0341);
2575 b43_phy_write(dev, 0x228, 0x042b);
2576 b43_phy_write(dev, 0x229, 0x042b);
2577 b43_phy_write(dev, 0x22a, 0x0381);
2578 b43_phy_write(dev, 0x22b, 0x0381);
2579 b43_phy_write(dev, 0x22c, 0x042b);
2580 b43_phy_write(dev, 0x22d, 0x042b);
2581 b43_phy_write(dev, 0x22e, 0x0381);
2582 b43_phy_write(dev, 0x22f, 0x0381);
fa0f2b38
RM		 2583
2584 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2585 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2586}
ba9a6214 2587
73d07a39
RM		 2588static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2589{
2590 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2591 struct b43_phy *phy = &dev->phy;
2592 struct b43_phy_n *nphy = phy->n;
ba9a6214 2593
73d07a39
RM		 2594 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2595 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2596
73d07a39
RM		 2597 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2598 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2599
fa0f2b38
RM		 2600 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2601 dev->dev->board_type == 0x8B) {
2602 delays1[0] = 0x1;
2603 delays1[5] = 0x14;
2604 }
2605
73d07a39
RM		 2606 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2607 nphy->band5g_pwrgain) {
2608 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2609 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2610 } else {
73d07a39
RM		 2611 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2612 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2613 }
28fd7daa 2614
73d07a39
RM		 2615 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2616 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2617 if (dev->phy.rev < 3) {
2618 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2619 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2620 }
73d07a39
RM		 2621
2622 if (dev->phy.rev < 2) {
2623 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2624 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2625 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2626 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2627 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2628 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2629 }
28fd7daa 2630
73d07a39
RM		 2631 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2632 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2633 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2634 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2635
73d07a39
RM		 2636 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2637 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2638
3ccd0957 2639 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2640
2641 if (dev->phy.rev < 2) {
2642 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2643 b43_hf_write(dev, b43_hf_read(dev) |
2644 B43_HF_MLADVW);
2645 } else if (dev->phy.rev == 2) {
2646 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2647 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2648 }
28fd7daa 2649
73d07a39
RM		 2650 if (dev->phy.rev < 2)
2651 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2652 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2653
2654 /* Set phase track alpha and beta */
2655 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2656 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2657 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2658 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2659 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2660 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2661
fa0f2b38
RM		 2662 if (dev->phy.rev < 3) {
2663 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2664 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2665 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2666 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2667 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2668 }
73d07a39
RM		 2669
2670 if (dev->phy.rev == 2)
2671 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2672 B43_NPHY_FINERX2_CGC_DECGC);
2673}
28fd7daa 2674
73d07a39
RM		 2675/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2676static void b43_nphy_workarounds(struct b43_wldev *dev)
2677{
2678 struct b43_phy *phy = &dev->phy;
2679 struct b43_phy_n *nphy = phy->n;
28fd7daa 2680
73d07a39
RM		 2681 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2682 b43_nphy_classifier(dev, 1, 0);
2683 else
2684 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2685
73d07a39
RM		 2686 if (nphy->hang_avoid)
2687 b43_nphy_stay_in_carrier_search(dev, 1);
2688
2689 b43_phy_set(dev, B43_NPHY_IQFLIP,
2690 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2691
d11d354b
RM		 2692 if (dev->phy.rev >= 7)
2693 b43_nphy_workarounds_rev7plus(dev);
2694 else if (dev->phy.rev >= 3)
73d07a39
RM		 2695 b43_nphy_workarounds_rev3plus(dev);
2696 else
2697 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2698
2699 if (nphy->hang_avoid)
2700 b43_nphy_stay_in_carrier_search(dev, 0);
2701}
2702
9dd4d9b9
RM		 2703/**************************************************
2704 * Tx/Rx common
2705 **************************************************/
2706
2707/*
2708 * Transmits a known value for LO calibration
2709 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2710 */
2711static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2712 bool iqmode, bool dac_test)
2713{
2714 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2715 if (samp == 0)
2716 return -1;
2717 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2718 return 0;
2719}
2720
2721/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2722static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2723{
2724 struct b43_phy_n *nphy = dev->phy.n;
2725
2726 bool override = false;
2727 u16 chain = 0x33;
2728
2729 if (nphy->txrx_chain == 0) {
2730 chain = 0x11;
2731 override = true;
2732 } else if (nphy->txrx_chain == 1) {
2733 chain = 0x22;
2734 override = true;
2735 }
2736
2737 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2738 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2739 chain);
2740
2741 if (override)
2742 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2743 B43_NPHY_RFSEQMODE_CAOVER);
2744 else
2745 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2746 ~B43_NPHY_RFSEQMODE_CAOVER);
2747}
2748
2749/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2750static void b43_nphy_stop_playback(struct b43_wldev *dev)
2751{
2752 struct b43_phy_n *nphy = dev->phy.n;
2753 u16 tmp;
2754
2755 if (nphy->hang_avoid)
2756 b43_nphy_stay_in_carrier_search(dev, 1);
2757
2758 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2759 if (tmp & 0x1)
2760 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2761 else if (tmp & 0x2)
2762 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2763
2764 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2765
2766 if (nphy->bb_mult_save & 0x80000000) {
2767 tmp = nphy->bb_mult_save & 0xFFFF;
2768 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2769 nphy->bb_mult_save = 0;
2770 }
2771
2772 if (nphy->hang_avoid)
2773 b43_nphy_stay_in_carrier_search(dev, 0);
2774}
2775
2776/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2777static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2778 struct nphy_txgains target,
2779 struct nphy_iqcal_params *params)
2780{
2781 int i, j, indx;
2782 u16 gain;
2783
2784 if (dev->phy.rev >= 3) {
2785 params->txgm = target.txgm[core];
2786 params->pga = target.pga[core];
2787 params->pad = target.pad[core];
2788 params->ipa = target.ipa[core];
2789 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2790 (params->pad << 4) | (params->ipa);
2791 for (j = 0; j < 5; j++)
2792 params->ncorr[j] = 0x79;
2793 } else {
2794 gain = (target.pad[core]) | (target.pga[core] << 4) |
2795 (target.txgm[core] << 8);
2796
2797 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2798 1 : 0;
2799 for (i = 0; i < 9; i++)
2800 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2801 break;
2802 i = min(i, 8);
2803
2804 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2805 params->pga = tbl_iqcal_gainparams[indx][i][2];
2806 params->pad = tbl_iqcal_gainparams[indx][i][3];
2807 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2808 (params->pad << 2);
2809 for (j = 0; j < 4; j++)
2810 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2811 }
2812}
2813
884a5228 2814/**************************************************
104cfa88 2815 * Tx and Rx
884a5228 2816 **************************************************/
5f6393ec 2817
884a5228
RM		 2818static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2819{//TODO
2820}
59af099b 2821
884a5228
RM		 2822static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2823 bool ignore_tssi)
2824{//TODO
2825 return B43_TXPWR_RES_DONE;
2826}
59af099b 2827
161d540c
RM		 2828/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2829static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2830{
2831 struct b43_phy_n *nphy = dev->phy.n;
2832 u8 i;
c9c0d9ec
RM		 2833 u16 bmask, val, tmp;
2834 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 2835
161d540c
RM		 2836 if (nphy->hang_avoid)
2837 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 2838
161d540c
RM		 2839 nphy->txpwrctrl = enable;
2840 if (!enable) {
c9c0d9ec
RM		 2841 if (dev->phy.rev >= 3 &&
2842 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2843 (B43_NPHY_TXPCTL_CMD_COEFF |
2844 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2845 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2846 /* We disable enabled TX pwr ctl, save it's state */
2847 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2848 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2849 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2850 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2851 }
59af099b 2852
161d540c
RM		 2853 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2854 for (i = 0; i < 84; i++)
2855 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2856
161d540c
RM		 2857 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2858 for (i = 0; i < 84; i++)
2859 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2860
161d540c
RM		 2861 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2862 if (dev->phy.rev >= 3)
2863 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2864 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 2865
161d540c
RM		 2866 if (dev->phy.rev >= 3) {
2867 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2868 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2869 } else {
2870 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2871 }
10a79873 2872
161d540c
RM		 2873 if (dev->phy.rev == 2)
2874 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2875 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2876 else if (dev->phy.rev < 2)
2877 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2878 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 2879
c9c0d9ec
RM		 2880 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2881 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 2882 } else {
c9c0d9ec
RM		 2883 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2884 nphy->adj_pwr_tbl);
2885 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2886 nphy->adj_pwr_tbl);
10a79873 2887
c9c0d9ec
RM		 2888 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2889 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2890 /* wl does useless check for "enable" param here */
2891 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2892 if (dev->phy.rev >= 3) {
2893 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2894 if (val)
2895 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2896 }
2897 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 2898
c9c0d9ec
RM		 2899 if (band == IEEE80211_BAND_5GHZ) {
2900 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2901 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2902 if (dev->phy.rev > 1)
2903 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2904 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2905 0x64);
2906 }
10a79873 2907
c9c0d9ec
RM		 2908 if (dev->phy.rev >= 3) {
2909 if (nphy->tx_pwr_idx[0] != 128 &&
2910 nphy->tx_pwr_idx[1] != 128) {
2911 /* Recover TX pwr ctl state */
2912 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2913 ~B43_NPHY_TXPCTL_CMD_INIT,
2914 nphy->tx_pwr_idx[0]);
2915 if (dev->phy.rev > 1)
2916 b43_phy_maskset(dev,
2917 B43_NPHY_TXPCTL_INIT,
2918 ~0xff, nphy->tx_pwr_idx[1]);
2919 }
2920 }
10a79873 2921
c9c0d9ec
RM		 2922 if (dev->phy.rev >= 3) {
2923 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2924 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2925 } else {
2926 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2927 }
10a79873 2928
c9c0d9ec
RM		 2929 if (dev->phy.rev == 2)
2930 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2931 else if (dev->phy.rev < 2)
2932 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 2933
c9c0d9ec
RM		 2934 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2935 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 2936
c002831a 2937 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 2938 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2939 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 2940 }
10a79873 2941 }
10a79873 2942
161d540c
RM		 2943 if (nphy->hang_avoid)
2944 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 2945}
2946
161d540c 2947/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 2948static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 2949{
2950 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2951 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 2952
161d540c
RM		 2953 u8 txpi[2], bbmult, i;
2954 u16 tmp, radio_gain, dac_gain;
2955 u16 freq = dev->phy.channel_freq;
2956 u32 txgain;
2957 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 2958
2959 if (nphy->hang_avoid)
161d540c 2960 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 2961
dd5f13b8
RM		 2962 if (dev->phy.rev >= 7) {
2963 txpi[0] = txpi[1] = 30;
2964 } else if (dev->phy.rev >= 3) {
161d540c
RM		 2965 txpi[0] = 40;
2966 txpi[1] = 40;
2967 } else if (sprom->revision < 4) {
2968 txpi[0] = 72;
2969 txpi[1] = 72;
2970 } else {
2971 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2972 txpi[0] = sprom->txpid2g[0];
2973 txpi[1] = sprom->txpid2g[1];
2974 } else if (freq >= 4900 && freq < 5100) {
2975 txpi[0] = sprom->txpid5gl[0];
2976 txpi[1] = sprom->txpid5gl[1];
2977 } else if (freq >= 5100 && freq < 5500) {
2978 txpi[0] = sprom->txpid5g[0];
2979 txpi[1] = sprom->txpid5g[1];
2980 } else if (freq >= 5500) {
2981 txpi[0] = sprom->txpid5gh[0];
2982 txpi[1] = sprom->txpid5gh[1];
2983 } else {
2984 txpi[0] = 91;
2985 txpi[1] = 91;
6dcd9d91
RM		 2986 }
2987 }
dd5f13b8 2988 if (dev->phy.rev < 7 &&
9bd28571 2989 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 2990 txpi[0] = txpi[1] = 91;
6dcd9d91 2991
161d540c
RM		 2992 /*
2993 for (i = 0; i < 2; i++) {
2994 nphy->txpwrindex[i].index_internal = txpi[i];
2995 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 2996 }
161d540c 2997 */
75377b24 2998
161d540c 2999 for (i = 0; i < 2; i++) {
aeab5751
RM		 3000 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3001
3002 if (dev->phy.rev >= 3)
161d540c 3003 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3004 else
161d540c 3005 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3006
dd5f13b8
RM		 3007 if (dev->phy.rev >= 7)
3008 dac_gain = (txgain >> 8) & 0x7;
3009 else
3010 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3011 bbmult = txgain & 0xFF;
75377b24 3012
161d540c
RM		 3013 if (dev->phy.rev >= 3) {
3014 if (i == 0)
3015 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3016 else
3017 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3018 } else {
3019 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3020 }
75377b24 3021
161d540c
RM		 3022 if (i == 0)
3023 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3024 else
3025 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3026
44f4008b 3027 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3028
44f4008b 3029 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3030 if (i == 0)
3031 tmp = (tmp & 0x00FF) | (bbmult << 8);
3032 else
3033 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3034 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3035
0eff8fcd
RM		 3036 if (b43_nphy_ipa(dev)) {
3037 u32 tmp32;
3038 u16 reg = (i == 0) ?
3039 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3040 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3041 576 + txpi[i]));
0eff8fcd
RM		 3042 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3043 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3044 }
3045 }
75377b24 3046
161d540c 3047 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3048
161d540c
RM		 3049 if (nphy->hang_avoid)
3050 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3051}
67cbc3ed 3052
3dda07b6
RM		 3053static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3054{
3055 struct b43_phy *phy = &dev->phy;
3056
3057 u8 core;
3058 u16 r; /* routing */
3059
3060 if (phy->rev >= 7) {
3061 for (core = 0; core < 2; core++) {
3062 r = core ? 0x190 : 0x170;
3063 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3064 b43_radio_write(dev, r + 0x5, 0x5);
3065 b43_radio_write(dev, r + 0x9, 0xE);
3066 if (phy->rev != 5)
3067 b43_radio_write(dev, r + 0xA, 0);
3068 if (phy->rev != 7)
3069 b43_radio_write(dev, r + 0xB, 1);
3070 else
3071 b43_radio_write(dev, r + 0xB, 0x31);
3072 } else {
3073 b43_radio_write(dev, r + 0x5, 0x9);
3074 b43_radio_write(dev, r + 0x9, 0xC);
3075 b43_radio_write(dev, r + 0xB, 0x0);
3076 if (phy->rev != 5)
3077 b43_radio_write(dev, r + 0xA, 1);
3078 else
3079 b43_radio_write(dev, r + 0xA, 0x31);
3080 }
3081 b43_radio_write(dev, r + 0x6, 0);
3082 b43_radio_write(dev, r + 0x7, 0);
3083 b43_radio_write(dev, r + 0x8, 3);
3084 b43_radio_write(dev, r + 0xC, 0);
3085 }
3086 } else {
3087 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3088 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3089 else
3090 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3091 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3092 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3093
3094 for (core = 0; core < 2; core++) {
3095 r = core ? B2056_TX1 : B2056_TX0;
3096
3097 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3098 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3099 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3100 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3101 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3102 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3103 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3104 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3105 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3106 0x5);
3107 if (phy->rev != 5)
3108 b43_radio_write(dev, r | B2056_TX_TSSIA,
3109 0x00);
3110 if (phy->rev >= 5)
3111 b43_radio_write(dev, r | B2056_TX_TSSIG,
3112 0x31);
3113 else
3114 b43_radio_write(dev, r | B2056_TX_TSSIG,
3115 0x11);
3116 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3117 0xE);
3118 } else {
3119 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3120 0x9);
3121 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3122 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3123 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3124 0xC);
3125 }
3126 }
3127 }
3128}
3129
3130/*
3131 * Stop radio and transmit known signal. Then check received signal strength to
3132 * get TSSI (Transmit Signal Strength Indicator).
3133 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3134 */
3135static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3136{
3137 struct b43_phy *phy = &dev->phy;
3138 struct b43_phy_n *nphy = dev->phy.n;
3139
3140 u32 tmp;
3141 s32 rssi[4] = { };
3142
3143 /* TODO: check if we can transmit */
3144
3145 if (b43_nphy_ipa(dev))
3146 b43_nphy_ipa_internal_tssi_setup(dev);
3147
3148 if (phy->rev >= 7)
c071b9f6 3149 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6
RM		 3150 else if (phy->rev >= 3)
3151 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3152
3153 b43_nphy_stop_playback(dev);
3154 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3155 udelay(20);
3156 tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
3157 b43_nphy_stop_playback(dev);
3158 b43_nphy_rssi_select(dev, 0, 0);
3159
3160 if (phy->rev >= 7)
c071b9f6 3161 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6
RM		 3162 else if (phy->rev >= 3)
3163 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3164
3165 if (phy->rev >= 3) {
3166 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3167 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3168 } else {
3169 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3170 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3171 }
3172 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3173 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3174}
3175
d3fd8bf7
RM		 3176/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3177static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3178{
3179 struct b43_phy_n *nphy = dev->phy.n;
3180
3181 u8 idx, delta;
3182 u8 i, stf_mode;
3183
3184 for (i = 0; i < 4; i++)
3185 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3186
3187 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3188 delta = 0;
3189 switch (stf_mode) {
3190 case 0:
3191 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3192 idx = 68;
3193 } else {
3194 delta = 1;
3195 idx = dev->phy.is_40mhz ? 52 : 4;
3196 }
3197 break;
3198 case 1:
3199 idx = dev->phy.is_40mhz ? 76 : 28;
3200 break;
3201 case 2:
3202 idx = dev->phy.is_40mhz ? 84 : 36;
3203 break;
3204 case 3:
3205 idx = dev->phy.is_40mhz ? 92 : 44;
3206 break;
3207 }
3208
3209 for (i = 0; i < 20; i++) {
3210 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3211 nphy->tx_power_offset[idx];
3212 if (i == 0)
3213 idx += delta;
3214 if (i == 14)
3215 idx += 1 - delta;
3216 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3217 i == 13)
3218 idx += 1;
3219 }
3220 }
3221}
3222
3223/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3224static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3225{
3226 struct b43_phy_n *nphy = dev->phy.n;
3227 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3228
3229 s16 a1[2], b0[2], b1[2];
3230 u8 idle[2];
3231 s8 target[2];
3232 s32 num, den, pwr;
3233 u32 regval[64];
3234
3235 u16 freq = dev->phy.channel_freq;
3236 u16 tmp;
3237 u16 r; /* routing */
3238 u8 i, c;
3239
3240 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3241 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3242 b43_read32(dev, B43_MMIO_MACCTL);
3243 udelay(1);
3244 }
3245
3246 if (nphy->hang_avoid)
3247 b43_nphy_stay_in_carrier_search(dev, true);
3248
3249 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3250 if (dev->phy.rev >= 3)
3251 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3252 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3253 else
3254 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3255 B43_NPHY_TXPCTL_CMD_PCTLEN);
3256
3257 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3258 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3259
3260 if (sprom->revision < 4) {
3261 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3262 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3263 target[0] = target[1] = 52;
3264 a1[0] = a1[1] = -424;
3265 b0[0] = b0[1] = 5612;
3266 b1[0] = b1[1] = -1393;
3267 } else {
3268 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3269 for (c = 0; c < 2; c++) {
3270 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3271 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3272 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3273 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3274 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3275 }
3276 } else if (freq >= 4900 && freq < 5100) {
3277 for (c = 0; c < 2; c++) {
3278 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3279 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3280 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3281 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3282 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3283 }
3284 } else if (freq >= 5100 && freq < 5500) {
3285 for (c = 0; c < 2; c++) {
3286 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3287 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3288 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3289 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3290 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3291 }
3292 } else if (freq >= 5500) {
3293 for (c = 0; c < 2; c++) {
3294 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3295 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3296 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3297 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3298 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3299 }
3300 } else {
3301 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3302 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3303 target[0] = target[1] = 52;
3304 a1[0] = a1[1] = -424;
3305 b0[0] = b0[1] = 5612;
3306 b1[0] = b1[1] = -1393;
3307 }
3308 }
3309 /* target[0] = target[1] = nphy->tx_power_max; */
3310
3311 if (dev->phy.rev >= 3) {
3312 if (sprom->fem.ghz2.tssipos)
3313 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3314 if (dev->phy.rev >= 7) {
3315 for (c = 0; c < 2; c++) {
3316 r = c ? 0x190 : 0x170;
3317 if (b43_nphy_ipa(dev))
3318 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3319 }
3320 } else {
3321 if (b43_nphy_ipa(dev)) {
3322 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3323 b43_radio_write(dev,
3324 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3325 b43_radio_write(dev,
3326 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3327 } else {
3328 b43_radio_write(dev,
3329 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3330 b43_radio_write(dev,
3331 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3332 }
3333 }
3334 }
3335
3336 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3337 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3338 b43_read32(dev, B43_MMIO_MACCTL);
3339 udelay(1);
3340 }
3341
3342 if (dev->phy.rev >= 7) {
3343 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3344 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3345 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3346 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3347 } else {
3348 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3349 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3350 if (dev->phy.rev > 1)
3351 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3352 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3353 }
3354
3355 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3356 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3357
3358 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3359 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3360 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3361 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3362 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3363 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3364 B43_NPHY_TXPCTL_ITSSI_BINF);
3365 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3366 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3367 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3368
3369 for (c = 0; c < 2; c++) {
3370 for (i = 0; i < 64; i++) {
3371 num = 8 * (16 * b0[c] + b1[c] * i);
3372 den = 32768 + a1[c] * i;
3373 pwr = max((4 * num + den / 2) / den, -8);
3374 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3375 pwr = max(pwr, target[c] + 1);
3376 regval[i] = pwr;
3377 }
3378 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3379 }
3380
3381 b43_nphy_tx_prepare_adjusted_power_table(dev);
3382 /*
3383 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3384 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3385 */
3386
3387 if (nphy->hang_avoid)
3388 b43_nphy_stay_in_carrier_search(dev, false);
3389}
3390
0eff8fcd
RM		 3391static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3392{
3393 struct b43_phy *phy = &dev->phy;
67cbc3ed 3394
0eff8fcd 3395 const u32 *table = NULL;
0eff8fcd
RM		 3396 u32 rfpwr_offset;
3397 u8 pga_gain;
3398 int i;
0eff8fcd 3399
aeab5751 3400 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3401 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3402 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3403
3404 if (phy->rev >= 3) {
3405#if 0
3406 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3407#endif
0eff8fcd
RM		 3408
3409 for (i = 0; i < 128; i++) {
3410 pga_gain = (table[i] >> 24) & 0xF;
3411 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3412 rfpwr_offset =
3413 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3414 else
34c5cf20
RM		 3415 rfpwr_offset =
3416 0; /* FIXME */
0eff8fcd
RM		 3417 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3418 rfpwr_offset);
3419 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3420 rfpwr_offset);
3421 }
67cbc3ed
RM		 3422 }
3423}
3424
e50cbcf6
RM		 3425/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3426static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3427{
e50cbcf6
RM		 3428 struct b43_phy_n *nphy = dev->phy.n;
3429 enum ieee80211_band band;
3430 u16 tmp;
95b66bad 3431
e50cbcf6
RM		 3432 if (!enable) {
3433 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3434 B43_NPHY_RFCTL_INTC1);
3435 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3436 B43_NPHY_RFCTL_INTC2);
3437 band = b43_current_band(dev->wl);
3438 if (dev->phy.rev >= 3) {
3439 if (band == IEEE80211_BAND_5GHZ)
3440 tmp = 0x600;
3441 else
3442 tmp = 0x480;
3443 } else {
3444 if (band == IEEE80211_BAND_5GHZ)
3445 tmp = 0x180;
3446 else
3447 tmp = 0x120;
3448 }
3449 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3450 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3451 } else {
3452 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3453 nphy->rfctrl_intc1_save);
3454 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3455 nphy->rfctrl_intc2_save);
95b66bad 3456 }
95b66bad
MB		 3457}
3458
fe3e46e8
RM		 3459/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3460static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3461{
3462 u16 tmp;
3c95627d 3463
fe3e46e8 3464 if (dev->phy.rev >= 3) {
c002831a 3465 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3466 tmp = 4;
3467 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3468 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3469 }
76b002bd 3470
fe3e46e8
RM		 3471 tmp = 1;
3472 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3473 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3474 }
3475}
76b002bd 3476
2faa6b83
RM		 3477/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3478static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3479 u16 samps, u8 time, bool wait)
3c95627d 3480{
2faa6b83
RM		 3481 int i;
3482 u16 tmp;
3c95627d 3483
2faa6b83
RM		 3484 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3485 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3486 if (wait)
3487 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3488 else
2faa6b83 3489 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3490
2faa6b83 3491 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3492
2faa6b83
RM		 3493 for (i = 1000; i; i--) {
3494 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3495 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3496 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3497 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3498 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3499 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3500 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3501 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3502
2faa6b83
RM		 3503 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3504 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3505 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3506 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3507 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3508 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3509 return;
3c95627d 3510 }
2faa6b83 3511 udelay(10);
3c95627d 3512 }
2faa6b83 3513 memset(est, 0, sizeof(*est));
3c95627d
RM		 3514}
3515
a67162ab
RM		 3516/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3517static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3518 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3519{
a67162ab
RM		 3520 if (write) {
3521 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3522 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3523 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3524 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3525 } else {
a67162ab
RM		 3526 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3527 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3528 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3529 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3530 }
3531}
6e3b15a9 3532
c7455cf9
RM		 3533#if 0
3534/* Ready but not used anywhere */
026816fc
RM		 3535/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3536static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3537{
3538 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3539
026816fc
RM		 3540 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3541 if (core == 0) {
3542 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3543 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3544 } else {
3545 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3546 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3547 }
3548 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3549 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3550 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3551 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3552 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3553 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3554 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3555 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3556}
6e3b15a9 3557
026816fc
RM		 3558/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3559static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3560{
3561 u8 rxval, txval;
3562 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3563
026816fc
RM		 3564 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3565 if (core == 0) {
3566 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3567 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3568 } else {
3569 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3570 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3571 }
3572 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3573 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3574 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3575 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3576 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3577 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3578 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3579 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3580
026816fc
RM		 3581 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3582 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3583
acd82aa8
LF		 3584 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3585 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3586 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3587 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3588 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3589 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3590 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3591 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3592 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3593
026816fc
RM		 3594 if (core == 0) {
3595 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3596 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3597 } else {
3598 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3599 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3600 }
6e3b15a9 3601
67cbc3ed
RM		 3602 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3603 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 3604 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3605
026816fc
RM		 3606 if (core == 0) {
3607 rxval = 1;
3608 txval = 8;
3609 } else {
3610 rxval = 4;
3611 txval = 2;
6e3b15a9 3612 }
67cbc3ed
RM		 3613 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3614 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
99b82c41 3615}
c7455cf9 3616#endif
99b82c41 3617
34a56f2c
RM		 3618/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3619static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3620{
3621 int i;
34a56f2c
RM		 3622 s32 iq;
3623 u32 ii;
3624 u32 qq;
3625 int iq_nbits, qq_nbits;
3626 int arsh, brsh;
3627 u16 tmp, a, b;
3628
3629 struct nphy_iq_est est;
3630 struct b43_phy_n_iq_comp old;
3631 struct b43_phy_n_iq_comp new = { };
3632 bool error = false;
3633
3634 if (mask == 0)
3635 return;
3636
3637 b43_nphy_rx_iq_coeffs(dev, false, &old);
3638 b43_nphy_rx_iq_coeffs(dev, true, &new);
3639 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3640 new = old;
3641
dfb4aa5d 3642 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3643 if (i == 0 && (mask & 1)) {
3644 iq = est.iq0_prod;
3645 ii = est.i0_pwr;
3646 qq = est.q0_pwr;
3647 } else if (i == 1 && (mask & 2)) {
3648 iq = est.iq1_prod;
3649 ii = est.i1_pwr;
3650 qq = est.q1_pwr;
dfb4aa5d 3651 } else {
34a56f2c 3652 continue;
dfb4aa5d 3653 }
dfb4aa5d 3654
34a56f2c
RM		 3655 if (ii + qq < 2) {
3656 error = true;
3657 break;
3658 }
dfb4aa5d 3659
34a56f2c
RM		 3660 iq_nbits = fls(abs(iq));
3661 qq_nbits = fls(qq);
dfb4aa5d 3662
34a56f2c
RM		 3663 arsh = iq_nbits - 20;
3664 if (arsh >= 0) {
3665 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3666 tmp = ii >> arsh;
3667 } else {
3668 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3669 tmp = ii << -arsh;
3670 }
3671 if (tmp == 0) {
3672 error = true;
3673 break;
3674 }
3675 a /= tmp;
dfb4aa5d 3676
34a56f2c
RM		 3677 brsh = qq_nbits - 11;
3678 if (brsh >= 0) {
3679 b = (qq << (31 - qq_nbits));
3680 tmp = ii >> brsh;
dfb4aa5d 3681 } else {
34a56f2c
RM		 3682 b = (qq << (31 - qq_nbits));
3683 tmp = ii << -brsh;
3684 }
3685 if (tmp == 0) {
3686 error = true;
3687 break;
dfb4aa5d 3688 }
34a56f2c 3689 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3690
34a56f2c
RM		 3691 if (i == 0 && (mask & 0x1)) {
3692 if (dev->phy.rev >= 3) {
3693 new.a0 = a & 0x3FF;
3694 new.b0 = b & 0x3FF;
3695 } else {
3696 new.a0 = b & 0x3FF;
3697 new.b0 = a & 0x3FF;
3698 }
3699 } else if (i == 1 && (mask & 0x2)) {
3700 if (dev->phy.rev >= 3) {
3701 new.a1 = a & 0x3FF;
3702 new.b1 = b & 0x3FF;
3703 } else {
3704 new.a1 = b & 0x3FF;
3705 new.b1 = a & 0x3FF;
3706 }
3707 }
dfb4aa5d 3708 }
dfb4aa5d 3709
34a56f2c
RM		 3710 if (error)
3711 new = old;
dfb4aa5d 3712
34a56f2c
RM		 3713 b43_nphy_rx_iq_coeffs(dev, true, &new);
3714}
dfb4aa5d 3715
09146400
RM		 3716/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3717static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3718{
3719 u16 array[4];
44f4008b 3720 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3721
3722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3723 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3724 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3725 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3726}
3727
9442e5b5
RM		 3728/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3729static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3730{
3731 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3732
204a665b 3733 u8 channel = dev->phy.channel;
9442e5b5
RM		 3734 int tone[2] = { 57, 58 };
3735 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3736
9442e5b5 3737 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3738
9442e5b5
RM		 3739 if (nphy->hang_avoid)
3740 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3741
9442e5b5
RM		 3742 if (nphy->gband_spurwar_en) {
3743 /* TODO: N PHY Adjust Analog Pfbw (7) */
3744 if (channel == 11 && dev->phy.is_40mhz)
3745 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3746 else
3747 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3748 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 3749 }
3750
9442e5b5
RM		 3751 if (nphy->aband_spurwar_en) {
3752 if (channel == 54) {
3753 tone[0] = 0x20;
3754 noise[0] = 0x25F;
3755 } else if (channel == 38 || channel == 102 || channel == 118) {
3756 if (0 /* FIXME */) {
3757 tone[0] = 0x20;
3758 noise[0] = 0x21F;
3759 } else {
3760 tone[0] = 0;
3761 noise[0] = 0;
90b9738d 3762 }
9442e5b5
RM		 3763 } else if (channel == 134) {
3764 tone[0] = 0x20;
3765 noise[0] = 0x21F;
3766 } else if (channel == 151) {
3767 tone[0] = 0x10;
3768 noise[0] = 0x23F;
3769 } else if (channel == 153 || channel == 161) {
3770 tone[0] = 0x30;
3771 noise[0] = 0x23F;
3772 } else {
3773 tone[0] = 0;
3774 noise[0] = 0;
90b9738d 3775 }
90b9738d 3776
9442e5b5
RM		 3777 if (!tone[0] && !noise[0])
3778 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 3779 else
9442e5b5
RM		 3780 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3781 }
90b9738d 3782
9442e5b5
RM		 3783 if (nphy->hang_avoid)
3784 b43_nphy_stay_in_carrier_search(dev, 0);
3785}
90b9738d 3786
5ecab603
RM		 3787/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3788static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3789{
3790 struct b43_phy_n *nphy = dev->phy.n;
3791 int i, j;
3792 u32 tmp;
3793 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 3794
5ecab603 3795 u16 buffer[7];
90b9738d 3796
5ecab603
RM		 3797 if (nphy->hang_avoid)
3798 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 3799
5ecab603 3800 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 3801
5ecab603
RM		 3802 for (i = 0; i < 2; i++) {
3803 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3804 (buffer[i * 2 + 1] & 0x3FF);
3805 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3806 (((i + 26) << 10) | 320));
3807 for (j = 0; j < 128; j++) {
3808 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3809 ((tmp >> 16) & 0xFFFF));
3810 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3811 (tmp & 0xFFFF));
90b9738d 3812 }
90b9738d 3813 }
90b9738d 3814
5ecab603
RM		 3815 for (i = 0; i < 2; i++) {
3816 tmp = buffer[5 + i];
3817 real_part = (tmp >> 8) & 0xFF;
3818 imag_part = (tmp & 0xFF);
3819 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3820 (((i + 26) << 10) | 448));
90b9738d 3821
5ecab603
RM		 3822 if (dev->phy.rev >= 3) {
3823 cur_real = real_part;
3824 cur_imag = imag_part;
3825 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3826 }
4cb99775 3827
5ecab603
RM		 3828 for (j = 0; j < 128; j++) {
3829 if (dev->phy.rev < 3) {
3830 cur_real = (real_part * loscale[j] + 128) >> 8;
3831 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3832 tmp = ((cur_real & 0xFF) << 8) |
3833 (cur_imag & 0xFF);
3834 }
3835 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3836 ((tmp >> 16) & 0xFFFF));
3837 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3838 (tmp & 0xFFFF));
3839 }
90b9738d 3840 }
4cb99775 3841
4cb99775 3842 if (dev->phy.rev >= 3) {
5ecab603
RM		 3843 b43_shm_write16(dev, B43_SHM_SHARED,
3844 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3845 b43_shm_write16(dev, B43_SHM_SHARED,
3846 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 3847 }
90b9738d 3848
5ecab603
RM		 3849 if (nphy->hang_avoid)
3850 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 3851}
3852
42e1547e
RM		 3853/*
3854 * Restore RSSI Calibration
3855 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3856 */
3857static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3858{
3859 struct b43_phy_n *nphy = dev->phy.n;
3860
3861 u16 *rssical_radio_regs = NULL;
3862 u16 *rssical_phy_regs = NULL;
3863
3864 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3865 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 3866 return;
3867 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3868 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3869 } else {
204a665b 3870 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 3871 return;
3872 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3873 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3874 }
3875
3876 /* TODO use some definitions */
3877 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3878 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3879
3880 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3881 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3882 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3883 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3884
3885 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3886 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3887 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3888 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3889
3890 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3891 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3892 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3893 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3894}
3895
c4a92003
RM		 3896/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3897static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3898{
3899 struct b43_phy_n *nphy = dev->phy.n;
3900 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 3901 u16 tmp;
3902 u8 offset, i;
c4a92003
RM		 3903
3904 if (dev->phy.rev >= 3) {
52cb5e97
RM		 3905 for (i = 0; i < 2; i++) {
3906 tmp = (i == 0) ? 0x2000 : 0x3000;
3907 offset = i * 11;
3908
3909 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3910 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3911 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3912 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3913 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3914 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3915 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3916 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3917 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3918 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3919 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3920
3921 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3922 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3923 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3924 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3925 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3926 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3927 if (nphy->ipa5g_on) {
3928 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3929 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3930 } else {
3931 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3932 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3933 }
3934 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3935 } else {
3936 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3937 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3938 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3939 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3940 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3941 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3942 if (nphy->ipa2g_on) {
3943 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3944 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3945 (dev->phy.rev < 5) ? 0x11 : 0x01);
3946 } else {
3947 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3948 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3949 }
3950 }
3951 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3952 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3953 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3954 }
c4a92003
RM		 3955 } else {
3956 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3957 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3958
3959 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3960 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3961
3962 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3963 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3964
3965 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3966 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3967
3968 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3969 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3970
3971 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3972 B43_NPHY_BANDCTL_5GHZ)) {
3973 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3974 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3975 } else {
3976 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3977 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3978 }
3979
3980 if (dev->phy.rev < 2) {
3981 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3982 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3983 } else {
3984 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3985 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3986 }
3987 }
3988}
3989
de7ed0c6
RM		 3990/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3991static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3992{
3993 struct b43_phy_n *nphy = dev->phy.n;
3994 int i;
3995 u16 scale, entry;
3996
3997 u16 tmp = nphy->txcal_bbmult;
3998 if (core == 0)
3999 tmp >>= 8;
4000 tmp &= 0xff;
4001
4002 for (i = 0; i < 18; i++) {
4003 scale = (ladder_lo[i].percent * tmp) / 100;
4004 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4005 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4006
4007 scale = (ladder_iq[i].percent * tmp) / 100;
4008 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4009 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4010 }
4011}
4012
45ca697e
RM		 4013/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4014static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4015{
4016 int i;
4017 for (i = 0; i < 15; i++)
4018 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4019 tbl_tx_filter_coef_rev4[2][i]);
4020}
4021
4022/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4023static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4024{
4025 int i, j;
4026 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4027 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4028
4029 for (i = 0; i < 3; i++)
4030 for (j = 0; j < 15; j++)
4031 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4032 tbl_tx_filter_coef_rev4[i][j]);
4033
4034 if (dev->phy.is_40mhz) {
4035 for (j = 0; j < 15; j++)
4036 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4037 tbl_tx_filter_coef_rev4[3][j]);
4038 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4039 for (j = 0; j < 15; j++)
4040 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4041 tbl_tx_filter_coef_rev4[5][j]);
4042 }
4043
4044 if (dev->phy.channel == 14)
4045 for (j = 0; j < 15; j++)
4046 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4047 tbl_tx_filter_coef_rev4[6][j]);
4048}
4049
b0022e15
RM		 4050/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4051static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4052{
4053 struct b43_phy_n *nphy = dev->phy.n;
4054
4055 u16 curr_gain[2];
4056 struct nphy_txgains target;
4057 const u32 *table = NULL;
4058
161d540c 4059 if (!nphy->txpwrctrl) {
b0022e15
RM		 4060 int i;
4061
4062 if (nphy->hang_avoid)
4063 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4064 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4065 if (nphy->hang_avoid)
4066 b43_nphy_stay_in_carrier_search(dev, false);
4067
4068 for (i = 0; i < 2; ++i) {
4069 if (dev->phy.rev >= 3) {
4070 target.ipa[i] = curr_gain[i] & 0x000F;
4071 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4072 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4073 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4074 } else {
4075 target.ipa[i] = curr_gain[i] & 0x0003;
4076 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4077 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4078 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4079 }
4080 }
4081 } else {
4082 int i;
4083 u16 index[2];
4084 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4085 B43_NPHY_TXPCTL_STAT_BIDX) >>
4086 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4087 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4088 B43_NPHY_TXPCTL_STAT_BIDX) >>
4089 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4090
4091 for (i = 0; i < 2; ++i) {
aeab5751 4092 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4093 if (dev->phy.rev >= 3) {
b0022e15
RM		 4094 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4095 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4096 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4097 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4098 } else {
b0022e15
RM		 4099 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4100 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4101 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4102 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4103 }
4104 }
4105 }
4106
4107 return target;
4108}
4109
e53de674
RM		 4110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4111static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4112{
4113 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4114
4115 if (dev->phy.rev >= 3) {
4116 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4117 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4118 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4119 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4120 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4121 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4122 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4123 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4124 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4125 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4126 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4127 b43_nphy_reset_cca(dev);
4128 } else {
4129 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4130 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4131 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4132 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4133 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4134 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4135 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4136 }
4137}
4138
4139/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4140static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4141{
4142 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4143 u16 tmp;
4144
4145 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4146 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4147 if (dev->phy.rev >= 3) {
4148 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4149 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4150
4151 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4152 regs[2] = tmp;
4153 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4154
4155 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4156 regs[3] = tmp;
4157 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4158
4159 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4160 b43_phy_mask(dev, B43_NPHY_BBCFG,
4161 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4162
c643a66e 4163 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4164 regs[5] = tmp;
d41a3552 4165 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4166
4167 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4168 regs[6] = tmp;
d41a3552 4169 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4170 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4171 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4172
67cbc3ed
RM		 4173 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4174 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4175 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 4176
4177 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4178 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4179 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4180 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4181 } else {
4182 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4183 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4184 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4185 regs[2] = tmp;
4186 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4187 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4188 regs[3] = tmp;
4189 tmp |= 0x2000;
d41a3552 4190 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4191 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4192 regs[4] = tmp;
4193 tmp |= 0x2000;
d41a3552 4194 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4195 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4196 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4197 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4198 tmp = 0x0180;
4199 else
4200 tmp = 0x0120;
4201 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4202 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4203 }
4204}
4205
bbc6dc12
RM		 4206/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4207static void b43_nphy_save_cal(struct b43_wldev *dev)
4208{
4209 struct b43_phy_n *nphy = dev->phy.n;
4210
4211 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4212 u16 *txcal_radio_regs = NULL;
902db91d 4213 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4214 u16 *table = NULL;
4215
4216 if (nphy->hang_avoid)
4217 b43_nphy_stay_in_carrier_search(dev, 1);
4218
4219 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4220 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4221 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4222 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4223 table = nphy->cal_cache.txcal_coeffs_2G;
4224 } else {
4225 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4226 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4227 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4228 table = nphy->cal_cache.txcal_coeffs_5G;
4229 }
4230
4231 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4232 /* TODO use some definitions */
4233 if (dev->phy.rev >= 3) {
4234 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4235 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4236 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4237 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4238 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4239 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4240 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4241 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4242 } else {
4243 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4244 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4245 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4246 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4247 }
204a665b
RM		 4248 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4249 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4250 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4251
4252 if (nphy->hang_avoid)
4253 b43_nphy_stay_in_carrier_search(dev, 0);
4254}
4255
2f258b74
RM		 4256/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4257static void b43_nphy_restore_cal(struct b43_wldev *dev)
4258{
4259 struct b43_phy_n *nphy = dev->phy.n;
4260
4261 u16 coef[4];
4262 u16 *loft = NULL;
4263 u16 *table = NULL;
4264
4265 int i;
4266 u16 *txcal_radio_regs = NULL;
4267 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4268
4269 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4270 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4271 return;
4272 table = nphy->cal_cache.txcal_coeffs_2G;
4273 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4274 } else {
204a665b 4275 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4276 return;
4277 table = nphy->cal_cache.txcal_coeffs_5G;
4278 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4279 }
4280
2581b143 4281 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4282
4283 for (i = 0; i < 4; i++) {
4284 if (dev->phy.rev >= 3)
4285 table[i] = coef[i];
4286 else
4287 coef[i] = 0;
4288 }
4289
2581b143
RM		 4290 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4291 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4292 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4293
4294 if (dev->phy.rev < 2)
4295 b43_nphy_tx_iq_workaround(dev);
4296
4297 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4298 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4299 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4300 } else {
4301 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4302 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4303 }
4304
4305 /* TODO use some definitions */
4306 if (dev->phy.rev >= 3) {
4307 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4308 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4309 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4310 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4311 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4312 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4313 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4314 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4315 } else {
4316 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4317 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4318 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4319 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4320 }
4321 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4322}
4323
fb43b8e2
RM		 4324/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4325static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4326 struct nphy_txgains target,
4327 bool full, bool mphase)
4328{
4329 struct b43_phy_n *nphy = dev->phy.n;
4330 int i;
4331 int error = 0;
4332 int freq;
4333 bool avoid = false;
4334 u8 length;
fb23d863 4335 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4336 const u16 *table;
4337 bool phy6or5x;
4338
4339 u16 buffer[11];
4340 u16 diq_start = 0;
4341 u16 save[2];
4342 u16 gain[2];
4343 struct nphy_iqcal_params params[2];
4344 bool updated[2] = { };
4345
4346 b43_nphy_stay_in_carrier_search(dev, true);
4347
4348 if (dev->phy.rev >= 4) {
4349 avoid = nphy->hang_avoid;
3db1cd5c 4350 nphy->hang_avoid = false;
fb43b8e2
RM		 4351 }
4352
9145834e 4353 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4354
4355 for (i = 0; i < 2; i++) {
4356 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4357 gain[i] = params[i].cal_gain;
4358 }
2581b143
RM		 4359
4360 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4361
4362 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4363 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4364
4365 phy6or5x = dev->phy.rev >= 6 ||
4366 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4367 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4368 if (phy6or5x) {
38bb9029
RM		 4369 if (dev->phy.is_40mhz) {
4370 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4371 tbl_tx_iqlo_cal_loft_ladder_40);
4372 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4373 tbl_tx_iqlo_cal_iqimb_ladder_40);
4374 } else {
4375 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4376 tbl_tx_iqlo_cal_loft_ladder_20);
4377 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4378 tbl_tx_iqlo_cal_iqimb_ladder_20);
4379 }
fb43b8e2
RM		 4380 }
4381
4382 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4383
aa4c7b2a 4384 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4385 freq = 2500;
4386 else
4387 freq = 5000;
4388
4389 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4390 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4391 0xFFFF, 0, true, false);
fb43b8e2 4392 else
59af099b 4393 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4394
4395 if (error == 0) {
4396 if (nphy->mphase_cal_phase_id > 2) {
4397 table = nphy->mphase_txcal_bestcoeffs;
4398 length = 11;
4399 if (dev->phy.rev < 3)
4400 length -= 2;
4401 } else {
4402 if (!full && nphy->txiqlocal_coeffsvalid) {
4403 table = nphy->txiqlocal_bestc;
4404 length = 11;
4405 if (dev->phy.rev < 3)
4406 length -= 2;
4407 } else {
4408 full = true;
4409 if (dev->phy.rev >= 3) {
4410 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4411 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4412 } else {
4413 table = tbl_tx_iqlo_cal_startcoefs;
4414 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4415 }
4416 }
4417 }
4418
2581b143 4419 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4420
4421 if (full) {
4422 if (dev->phy.rev >= 3)
4423 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4424 else
4425 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4426 } else {
4427 if (dev->phy.rev >= 3)
4428 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4429 else
4430 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4431 }
4432
4433 if (mphase) {
4434 count = nphy->mphase_txcal_cmdidx;
4435 numb = min(max,
4436 (u16)(count + nphy->mphase_txcal_numcmds));
4437 } else {
4438 count = 0;
4439 numb = max;
4440 }
4441
4442 for (; count < numb; count++) {
4443 if (full) {
4444 if (dev->phy.rev >= 3)
4445 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4446 else
4447 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4448 } else {
4449 if (dev->phy.rev >= 3)
4450 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4451 else
4452 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4453 }
4454
4455 core = (cmd & 0x3000) >> 12;
4456 type = (cmd & 0x0F00) >> 8;
4457
4458 if (phy6or5x && updated[core] == 0) {
4459 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4460 updated[core] = true;
fb43b8e2
RM		 4461 }
4462
4463 tmp = (params[core].ncorr[type] << 8) | 0x66;
4464 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4465
4466 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4467 buffer[0] = b43_ntab_read(dev,
4468 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4469 diq_start = buffer[0];
4470 buffer[0] = 0;
d41a3552
RM		 4471 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4472 0);
fb43b8e2
RM		 4473 }
4474
4475 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4476 for (i = 0; i < 2000; i++) {
4477 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4478 if (tmp & 0xC000)
4479 break;
4480 udelay(10);
4481 }
4482
9145834e
RM		 4483 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4484 buffer);
2581b143
RM		 4485 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4486 buffer);
fb43b8e2
RM		 4487
4488 if (type == 1 || type == 3 || type == 4)
4489 buffer[0] = diq_start;
4490 }
4491
4492 if (mphase)
4493 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4494
4495 last = (dev->phy.rev < 3) ? 6 : 7;
4496
4497 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4498 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4499 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4500 if (dev->phy.rev < 3) {
4501 buffer[0] = 0;
4502 buffer[1] = 0;
4503 buffer[2] = 0;
4504 buffer[3] = 0;
4505 }
2581b143
RM		 4506 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4507 buffer);
bc53e512 4508 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4509 buffer);
4510 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4511 buffer);
4512 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4513 buffer);
fb43b8e2
RM		 4514 length = 11;
4515 if (dev->phy.rev < 3)
4516 length -= 2;
9145834e
RM		 4517 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4518 nphy->txiqlocal_bestc);
fb43b8e2 4519 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4520 nphy->txiqlocal_chanspec.center_freq =
4521 dev->phy.channel_freq;
4522 nphy->txiqlocal_chanspec.channel_type =
4523 dev->phy.channel_type;
fb43b8e2
RM		 4524 } else {
4525 length = 11;
4526 if (dev->phy.rev < 3)
4527 length -= 2;
9145834e
RM		 4528 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4529 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4530 }
4531
53ae8e8c 4532 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4533 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4534 }
4535
e53de674 4536 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4537 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4538
4539 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4540 b43_nphy_tx_iq_workaround(dev);
4541
4542 if (dev->phy.rev >= 4)
4543 nphy->hang_avoid = avoid;
4544
4545 b43_nphy_stay_in_carrier_search(dev, false);
4546
4547 return error;
4548}
4549
984ff4ff
RM		 4550/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4551static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4552{
4553 struct b43_phy_n *nphy = dev->phy.n;
4554 u8 i;
4555 u16 buffer[7];
4556 bool equal = true;
4557
902db91d 4558 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4559 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4560 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4561 return;
4562
4563 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4564 for (i = 0; i < 4; i++) {
4565 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4566 equal = false;
4567 break;
4568 }
4569 }
4570
4571 if (!equal) {
4572 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4573 nphy->txiqlocal_bestc);
4574 for (i = 0; i < 4; i++)
4575 buffer[i] = 0;
4576 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4577 buffer);
4578 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4579 &nphy->txiqlocal_bestc[5]);
4580 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4581 &nphy->txiqlocal_bestc[5]);
4582 }
4583}
4584
15931e31
RM		 4585/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4586static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4587 struct nphy_txgains target, u8 type, bool debug)
4588{
4589 struct b43_phy_n *nphy = dev->phy.n;
4590 int i, j, index;
4591 u8 rfctl[2];
4592 u8 afectl_core;
4593 u16 tmp[6];
c7455cf9 4594 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4595 u32 real, imag;
4596 enum ieee80211_band band;
4597
4598 u8 use;
4599 u16 cur_hpf;
4600 u16 lna[3] = { 3, 3, 1 };
4601 u16 hpf1[3] = { 7, 2, 0 };
4602 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4603 u32 power[3] = { };
15931e31
RM		 4604 u16 gain_save[2];
4605 u16 cal_gain[2];
4606 struct nphy_iqcal_params cal_params[2];
4607 struct nphy_iq_est est;
4608 int ret = 0;
4609 bool playtone = true;
4610 int desired = 13;
4611
4612 b43_nphy_stay_in_carrier_search(dev, 1);
4613
4614 if (dev->phy.rev < 2)
984ff4ff 4615 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4616 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4617 for (i = 0; i < 2; i++) {
4618 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4619 cal_gain[i] = cal_params[i].cal_gain;
4620 }
2581b143 4621 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4622
4623 for (i = 0; i < 2; i++) {
4624 if (i == 0) {
4625 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4626 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4627 afectl_core = B43_NPHY_AFECTL_C1;
4628 } else {
4629 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4630 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4631 afectl_core = B43_NPHY_AFECTL_C2;
4632 }
4633
4634 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4635 tmp[2] = b43_phy_read(dev, afectl_core);
4636 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4637 tmp[4] = b43_phy_read(dev, rfctl[0]);
4638 tmp[5] = b43_phy_read(dev, rfctl[1]);
4639
4640 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4641 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4642 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4643 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4644 (1 - i));
4645 b43_phy_set(dev, afectl_core, 0x0006);
4646 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4647
4648 band = b43_current_band(dev->wl);
4649
4650 if (nphy->rxcalparams & 0xFF000000) {
4651 if (band == IEEE80211_BAND_5GHZ)
4652 b43_phy_write(dev, rfctl[0], 0x140);
4653 else
4654 b43_phy_write(dev, rfctl[0], 0x110);
4655 } else {
4656 if (band == IEEE80211_BAND_5GHZ)
4657 b43_phy_write(dev, rfctl[0], 0x180);
4658 else
4659 b43_phy_write(dev, rfctl[0], 0x120);
4660 }
4661
4662 if (band == IEEE80211_BAND_5GHZ)
4663 b43_phy_write(dev, rfctl[1], 0x148);
4664 else
4665 b43_phy_write(dev, rfctl[1], 0x114);
4666
4667 if (nphy->rxcalparams & 0x10000) {
4668 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4669 (i + 1));
4670 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4671 (2 - i));
4672 }
4673
30115c22 4674 for (j = 0; j < 4; j++) {
15931e31
RM		 4675 if (j < 3) {
4676 cur_lna = lna[j];
4677 cur_hpf1 = hpf1[j];
4678 cur_hpf2 = hpf2[j];
4679 } else {
4680 if (power[1] > 10000) {
4681 use = 1;
4682 cur_hpf = cur_hpf1;
4683 index = 2;
4684 } else {
4685 if (power[0] > 10000) {
4686 use = 1;
4687 cur_hpf = cur_hpf1;
4688 index = 1;
4689 } else {
4690 index = 0;
4691 use = 2;
4692 cur_hpf = cur_hpf2;
4693 }
4694 }
4695 cur_lna = lna[index];
4696 cur_hpf1 = hpf1[index];
4697 cur_hpf2 = hpf2[index];
4698 cur_hpf += desired - hweight32(power[index]);
4699 cur_hpf = clamp_val(cur_hpf, 0, 10);
4700 if (use == 1)
4701 cur_hpf1 = cur_hpf;
4702 else
4703 cur_hpf2 = cur_hpf;
4704 }
4705
4706 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4707 (cur_lna << 2));
75377b24
RM		 4708 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4709 false);
de9a47f9 4710 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4711 b43_nphy_stop_playback(dev);
15931e31
RM		 4712
4713 if (playtone) {
59af099b
RM		 4714 ret = b43_nphy_tx_tone(dev, 4000,
4715 (nphy->rxcalparams & 0xFFFF),
4716 false, false);
15931e31
RM		 4717 playtone = false;
4718 } else {
10a79873
RM		 4719 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4720 false, false);
15931e31
RM		 4721 }
4722
4723 if (ret == 0) {
4724 if (j < 3) {
4725 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4726 false);
4727 if (i == 0) {
4728 real = est.i0_pwr;
4729 imag = est.q0_pwr;
4730 } else {
4731 real = est.i1_pwr;
4732 imag = est.q1_pwr;
4733 }
4734 power[i] = ((real + imag) / 1024) + 1;
4735 } else {
4736 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4737 }
53ae8e8c 4738 b43_nphy_stop_playback(dev);
15931e31
RM		 4739 }
4740
4741 if (ret != 0)
4742 break;
4743 }
4744
4745 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4746 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4747 b43_phy_write(dev, rfctl[1], tmp[5]);
4748 b43_phy_write(dev, rfctl[0], tmp[4]);
4749 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4750 b43_phy_write(dev, afectl_core, tmp[2]);
4751 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4752
4753 if (ret != 0)
4754 break;
4755 }
4756
75377b24 4757 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 4758 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 4759 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4760
4761 b43_nphy_stay_in_carrier_search(dev, 0);
4762
4763 return ret;
4764}
4765
4766static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4767 struct nphy_txgains target, u8 type, bool debug)
4768{
4769 return -1;
4770}
4771
4772/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4773static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4774 struct nphy_txgains target, u8 type, bool debug)
4775{
4776 if (dev->phy.rev >= 3)
4777 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4778 else
4779 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4780}
4781
4e687b22
GS		 4782/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4783static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4784{
4785 struct b43_phy *phy = &dev->phy;
4786 struct b43_phy_n *nphy = phy->n;
0b81c23d 4787 /* u16 buf[16]; it's rev3+ */
4e687b22 4788
049fbfee
RM		 4789 nphy->phyrxchain = mask;
4790
4e687b22
GS		 4791 if (0 /* FIXME clk */)
4792 return;
4793
4794 b43_mac_suspend(dev);
4795
4796 if (nphy->hang_avoid)
4797 b43_nphy_stay_in_carrier_search(dev, true);
4798
4799 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4800 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4801
049fbfee 4802 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 4803 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4804 if (dev->phy.rev >= 3) {
4805 /* TODO */
4806 }
4807 } else {
4808 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4809 if (dev->phy.rev >= 3) {
4810 /* TODO */
4811 }
4812 }
4813
4814 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4815
4816 if (nphy->hang_avoid)
4817 b43_nphy_stay_in_carrier_search(dev, false);
4818
4819 b43_mac_enable(dev);
4820}
4821
104cfa88
RM		 4822/**************************************************
4823 * N-PHY init
4824 **************************************************/
4825
0988a7a1 4826/*
104cfa88
RM		 4827 * Upload the N-PHY tables.
4828 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
0988a7a1 4829 */
104cfa88
RM		 4830static void b43_nphy_tables_init(struct b43_wldev *dev)
4831{
4832 if (dev->phy.rev < 3)
4833 b43_nphy_rev0_1_2_tables_init(dev);
4834 else
4835 b43_nphy_rev3plus_tables_init(dev);
4836}
4837
4838/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4839static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4840{
4841 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4842
4843 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4844 if (preamble == 1)
4845 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4846 else
4847 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4848
4849 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4850}
4851
4852/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4853static void b43_nphy_bphy_init(struct b43_wldev *dev)
4854{
4855 unsigned int i;
4856 u16 val;
4857
4858 val = 0x1E1F;
4859 for (i = 0; i < 16; i++) {
4860 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4861 val -= 0x202;
4862 }
4863 val = 0x3E3F;
4864 for (i = 0; i < 16; i++) {
4865 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4866 val -= 0x202;
4867 }
4868 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4869}
4870
4871/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4872static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4873{
4874 if (dev->phy.rev >= 3) {
4875 if (!init)
4876 return;
4877 if (0 /* FIXME */) {
4878 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4879 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4880 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4881 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4882 }
4883 } else {
4884 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4885 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4886
4887 switch (dev->dev->bus_type) {
4888#ifdef CONFIG_B43_BCMA
4889 case B43_BUS_BCMA:
4890 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4891 0xFC00, 0xFC00);
4892 break;
4893#endif
4894#ifdef CONFIG_B43_SSB
4895 case B43_BUS_SSB:
4896 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4897 0xFC00, 0xFC00);
4898 break;
4899#endif
4900 }
4901
5056635c
RM		 4902 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4903 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4904 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4905 0);
104cfa88
RM		 4906
4907 if (init) {
4908 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4909 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4910 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4911 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4912 }
4913 }
4914}
4915
4916/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 4917static int b43_phy_initn(struct b43_wldev *dev)
424047e6 4918{
0581483a 4919 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 4920 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 4921 struct b43_phy_n *nphy = phy->n;
4922 u8 tx_pwr_state;
4923 struct nphy_txgains target;
95b66bad 4924 u16 tmp;
0988a7a1
RM		 4925 enum ieee80211_band tmp2;
4926 bool do_rssi_cal;
4927
4928 u16 clip[2];
4929 bool do_cal = false;
95b66bad 4930
0988a7a1 4931 if ((dev->phy.rev >= 3) &&
0581483a 4932 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 4933 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 4934 switch (dev->dev->bus_type) {
42c9a458
RM		 4935#ifdef CONFIG_B43_BCMA
4936 case B43_BUS_BCMA:
4937 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4938 BCMA_CC_CHIPCTL, 0x40);
4939 break;
4940#endif
6cbab0d9
RM		 4941#ifdef CONFIG_B43_SSB
4942 case B43_BUS_SSB:
4943 chipco_set32(&dev->dev->sdev->bus->chipco,
4944 SSB_CHIPCO_CHIPCTL, 0x40);
4945 break;
4946#endif
4947 }
0988a7a1
RM		 4948 }
4949 nphy->deaf_count = 0;
95b66bad 4950 b43_nphy_tables_init(dev);
0988a7a1
RM		 4951 nphy->crsminpwr_adjusted = false;
4952 nphy->noisevars_adjusted = false;
95b66bad
MB		 4953
4954 /* Clear all overrides */
0988a7a1
RM		 4955 if (dev->phy.rev >= 3) {
4956 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4957 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4958 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4959 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4960 } else {
4961 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4962 }
95b66bad
MB		 4963 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4964 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 4965 if (dev->phy.rev < 6) {
4966 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4967 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4968 }
95b66bad
MB		 4969 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4970 ~(B43_NPHY_RFSEQMODE_CAOVER |
4971 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 4972 if (dev->phy.rev >= 3)
4973 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 4974 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4975
0988a7a1
RM		 4976 if (dev->phy.rev <= 2) {
4977 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4978 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4979 ~B43_NPHY_BPHY_CTL3_SCALE,
4980 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4981 }
95b66bad
MB		 4982 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4983 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4984
0eff8fcd 4985 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f
RM		 4986 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4987 dev->dev->board_type == 0x8B))
0988a7a1
RM		 4988 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4989 else
4990 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4991 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4992 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4993 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 4994
ad9716e8 4995 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 4996 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 4997
4998 if (phy->rev < 2) {
4999 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5000 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5001 }
0988a7a1
RM		 5002
5003 tmp2 = b43_current_band(dev->wl);
c002831a 5004 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5005 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5006 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5007 nphy->papd_epsilon_offset[0] << 7);
5008 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5009 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5010 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5011 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5012 } else if (phy->rev >= 5) {
45ca697e 5013 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5014 }
5015
95b66bad 5016 b43_nphy_workarounds(dev);
95b66bad 5017
0988a7a1 5018 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5019 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5020 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5021 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5022 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5023 b43_phy_force_clock(dev, 0);
0988a7a1 5024
858a1652 5025 b43_mac_phy_clock_set(dev, true);
0988a7a1 5026
e50cbcf6 5027 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5028 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5029 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5030 b43_nphy_pa_override(dev, true);
0988a7a1 5031
bbec398c
RM		 5032 b43_nphy_classifier(dev, 0, 0);
5033 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5034 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5035 b43_nphy_bphy_init(dev);
5036
0988a7a1 5037 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5038 b43_nphy_tx_power_ctrl(dev, false);
5039 b43_nphy_tx_power_fix(dev);
3dda07b6 5040 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5041 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5042 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5043
0988a7a1 5044 if (nphy->phyrxchain != 3)
4e687b22 5045 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5046 if (nphy->mphase_cal_phase_id > 0)
5047 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5048
5049 do_rssi_cal = false;
5050 if (phy->rev >= 3) {
5051 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5052 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5053 else
204a665b 5054 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5055
5056 if (do_rssi_cal)
4cb99775 5057 b43_nphy_rssi_cal(dev);
0988a7a1 5058 else
42e1547e 5059 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5060 } else {
4cb99775 5061 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5062 }
5063
5064 if (!((nphy->measure_hold & 0x6) != 0)) {
5065 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5066 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5067 else
204a665b 5068 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5069
5070 if (nphy->mute)
5071 do_cal = false;
5072
5073 if (do_cal) {
b0022e15 5074 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5075
5076 if (nphy->antsel_type == 2)
8987a9e9 5077 b43_nphy_superswitch_init(dev, true);
0988a7a1 5078 if (nphy->perical != 2) {
90b9738d 5079 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5080 if (phy->rev >= 3) {
5081 nphy->cal_orig_pwr_idx[0] =
5082 nphy->txpwrindex[0].index_internal;
5083 nphy->cal_orig_pwr_idx[1] =
5084 nphy->txpwrindex[1].index_internal;
5085 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5086 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5087 }
e7797bf2
RM		 5088 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5089 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5090 b43_nphy_save_cal(dev);
5091 } else if (nphy->mphase_cal_phase_id == 0)
5092 ;/* N PHY Periodic Calibration with arg 3 */
5093 } else {
5094 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5095 }
5096 }
5097
6dcd9d91 5098 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5099 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5100 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5101 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5102 if (phy->rev >= 3 && phy->rev <= 6)
5103 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 5104 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5105 if (phy->rev >= 3)
5106 b43_nphy_spur_workaround(dev);
95b66bad 5107
53a6e234 5108 return 0;
424047e6 5109}
ef1a628d 5110
104cfa88
RM		 5111/**************************************************
5112 * Channel switching ops.
5113 **************************************************/
5114
5115static void b43_chantab_phy_upload(struct b43_wldev *dev,
5116 const struct b43_phy_n_sfo_cfg *e)
5117{
5118 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5119 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5120 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5121 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5122 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5123 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5124}
5125
49d55cef
RM		 5126/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5127static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5128{
d66be829
RM		 5129 switch (dev->dev->bus_type) {
5130#ifdef CONFIG_B43_BCMA
5131 case B43_BUS_BCMA:
9b383672
HM		 5132 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5133 avoid);
d66be829 5134 break;
8b1fdb53 5135#endif
d66be829
RM		 5136#ifdef CONFIG_B43_SSB
5137 case B43_BUS_SSB:
5138 /* FIXME */
5139 break;
5140#endif
5141 }
49d55cef
RM		 5142}
5143
1b69ec7b 5144/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5145static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5146 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5147 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5148{
5149 struct b43_phy *phy = &dev->phy;
5150 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5151 int ch = new_channel->hw_value;
1b69ec7b 5152
087de74a 5153 u16 old_band_5ghz;
1b69ec7b
RM		 5154 u32 tmp32;
5155
087de74a
RM		 5156 old_band_5ghz =
5157 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5158 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 5159 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5160 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5161 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5162 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5163 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5164 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 5165 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5166 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5167 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 5168 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 5169 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5170 }
5171
5172 b43_chantab_phy_upload(dev, e);
5173
a656b6a9 5174 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5175 b43_nphy_classifier(dev, 2, 0);
5176 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5177 } else {
5178 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5179 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5180 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5181 }
5182
161d540c 5183 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5184 b43_nphy_tx_power_fix(dev);
5185
5186 if (dev->phy.rev < 3)
5187 b43_nphy_adjust_lna_gain_table(dev);
5188
5189 b43_nphy_tx_lp_fbw(dev);
5190
49d55cef
RM		 5191 if (dev->phy.rev >= 3 &&
5192 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5193 bool avoid = false;
5194 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5195 avoid = true;
5196 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5197 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5198 avoid = true;
5199 } else { /* 40MHz */
5200 if (nphy->aband_spurwar_en &&
5201 (ch == 38 || ch == 102 || ch == 118))
5202 avoid = dev->dev->chip_id == 0x4716;
5203 }
5204
5205 b43_nphy_pmu_spur_avoid(dev, avoid);
5206
5207 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5208 dev->dev->chip_id == 43225) {
5209 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5210 avoid ? 0x5341 : 0x8889);
5211 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5212 }
5213
5214 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5215 ; /* TODO: reset PLL */
5216
5217 if (avoid)
5218 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5219 else
5220 b43_phy_mask(dev, B43_NPHY_BBCFG,
5221 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5222
5223 b43_nphy_reset_cca(dev);
5224
5225 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5226 }
5227
5228 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5229
5230 if (phy->rev >= 3)
5231 b43_nphy_spur_workaround(dev);
5232}
5233
eff66c51 5234/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5235static int b43_nphy_set_channel(struct b43_wldev *dev,
5236 struct ieee80211_channel *channel,
5237 enum nl80211_channel_type channel_type)
eff66c51 5238{
a656b6a9 5239 struct b43_phy *phy = &dev->phy;
eff66c51 5240
2eeb6fd0
JL		 5241 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5242 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5243
5244 u8 tmp;
eff66c51
RM		 5245
5246 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5247 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5248 channel->center_freq);
f19ebe7d
RM		 5249 if (!tabent_r3)
5250 return -ESRCH;
ffd2d9bd 5251 } else {
a656b6a9
RM		 5252 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5253 channel->hw_value);
f19ebe7d 5254 if (!tabent_r2)
ffd2d9bd 5255 return -ESRCH;
eff66c51
RM		 5256 }
5257
204a665b
RM		 5258 /* Channel is set later in common code, but we need to set it on our
5259 own to let this function's subcalls work properly. */
5260 phy->channel = channel->hw_value;
5261 phy->channel_freq = channel->center_freq;
eff66c51 5262
e5c407f9
RM		 5263 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5264 b43_channel_type_is_40mhz(channel_type))
5265 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5266
a656b6a9
RM		 5267 if (channel_type == NL80211_CHAN_HT40PLUS)
5268 b43_phy_set(dev, B43_NPHY_RXCTL,
5269 B43_NPHY_RXCTL_BSELU20);
5270 else if (channel_type == NL80211_CHAN_HT40MINUS)
5271 b43_phy_mask(dev, B43_NPHY_RXCTL,
5272 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5273
5274 if (dev->phy.rev >= 3) {
a656b6a9 5275 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5276 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5277 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5278 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5279 } else {
a656b6a9 5280 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5281 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5282 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5283 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5284 }
5285
5286 return 0;
5287}
5288
104cfa88
RM		 5289/**************************************************
5290 * Basic PHY ops.
5291 **************************************************/
5292
ef1a628d
MB		 5293static int b43_nphy_op_allocate(struct b43_wldev *dev)
5294{
5295 struct b43_phy_n *nphy;
5296
5297 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5298 if (!nphy)
5299 return -ENOMEM;
5300 dev->phy.n = nphy;
5301
ef1a628d
MB		 5302 return 0;
5303}
5304
fb11137a 5305static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5306{
fb11137a
MB		 5307 struct b43_phy *phy = &dev->phy;
5308 struct b43_phy_n *nphy = phy->n;
c7d64310 5309 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5310
fb11137a 5311 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5312
aca434d3 5313 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5314 nphy->spur_avoid = (phy->rev >= 3) ?
5315 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5316 nphy->init_por = true;
0b81c23d
RM		 5317 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5318 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5319 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5320 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5321 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5322 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5323 nphy->tx_pwr_idx[0] = 128;
5324 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5325
5326 /* Hardware TX power control and 5GHz power gain */
5327 nphy->txpwrctrl = false;
5328 nphy->pwg_gain_5ghz = false;
5329 if (dev->phy.rev >= 3 ||
5330 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5331 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5332 nphy->txpwrctrl = true;
5333 nphy->pwg_gain_5ghz = true;
5334 } else if (sprom->revision >= 4) {
5335 if (dev->phy.rev >= 2 &&
5336 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5337 nphy->txpwrctrl = true;
5338#ifdef CONFIG_B43_SSB
5339 if (dev->dev->bus_type == B43_BUS_SSB &&
5340 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5341 struct pci_dev *pdev =
5342 dev->dev->sdev->bus->host_pci;
5343 if (pdev->device == 0x4328 ||
5344 pdev->device == 0x432a)
5345 nphy->pwg_gain_5ghz = true;
5346 }
5347#endif
5348 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5349 nphy->pwg_gain_5ghz = true;
5350 }
5351 }
5352
5353 if (dev->phy.rev >= 3) {
5354 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5355 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5356 }
572d37a4
RM		 5357
5358 nphy->init_por = true;
ef1a628d
MB		 5359}
5360
fb11137a 5361static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5362{
fb11137a
MB		 5363 struct b43_phy *phy = &dev->phy;
5364 struct b43_phy_n *nphy = phy->n;
ef1a628d 5365
ef1a628d 5366 kfree(nphy);
fb11137a
MB		 5367 phy->n = NULL;
5368}
5369
5370static int b43_nphy_op_init(struct b43_wldev *dev)
5371{
5372 return b43_phy_initn(dev);
ef1a628d
MB		 5373}
5374
5375static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5376{
5377#if B43_DEBUG
5378 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5379 /* OFDM registers are onnly available on A/G-PHYs */
5380 b43err(dev->wl, "Invalid OFDM PHY access at "
5381 "0x%04X on N-PHY\n", offset);
5382 dump_stack();
5383 }
5384 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5385 /* Ext-G registers are only available on G-PHYs */
5386 b43err(dev->wl, "Invalid EXT-G PHY access at "
5387 "0x%04X on N-PHY\n", offset);
5388 dump_stack();
5389 }
5390#endif /* B43_DEBUG */
5391}
5392
5393static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5394{
5395 check_phyreg(dev, reg);
5396 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5397 return b43_read16(dev, B43_MMIO_PHY_DATA);
5398}
5399
5400static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5401{
5402 check_phyreg(dev, reg);
5403 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5404 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5405}
5406
755fd183
RM		 5407static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5408 u16 set)
5409{
5410 check_phyreg(dev, reg);
5411 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5412 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5413}
5414
ef1a628d
MB		 5415static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5416{
5417 /* Register 1 is a 32-bit register. */
5418 B43_WARN_ON(reg == 1);
5419 /* N-PHY needs 0x100 for read access */
5420 reg |= 0x100;
5421
5422 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5423 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5424}
5425
5426static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5427{
5428 /* Register 1 is a 32-bit register. */
5429 B43_WARN_ON(reg == 1);
5430
5431 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5432 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5433}
5434
c2b7aefd 5435/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5436static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5437 bool blocked)
c2b7aefd
RM		 5438{
5439 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5440 b43err(dev->wl, "MAC not suspended\n");
5441
5442 if (blocked) {
5443 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5444 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5445 if (dev->phy.rev >= 7) {
5446 /* TODO */
5447 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5448 b43_radio_mask(dev, 0x09, ~0x2);
5449
5450 b43_radio_write(dev, 0x204D, 0);
5451 b43_radio_write(dev, 0x2053, 0);
5452 b43_radio_write(dev, 0x2058, 0);
5453 b43_radio_write(dev, 0x205E, 0);
5454 b43_radio_mask(dev, 0x2062, ~0xF0);
5455 b43_radio_write(dev, 0x2064, 0);
5456
5457 b43_radio_write(dev, 0x304D, 0);
5458 b43_radio_write(dev, 0x3053, 0);
5459 b43_radio_write(dev, 0x3058, 0);
5460 b43_radio_write(dev, 0x305E, 0);
5461 b43_radio_mask(dev, 0x3062, ~0xF0);
5462 b43_radio_write(dev, 0x3064, 0);
5463 }
5464 } else {
572d37a4
RM		 5465 if (dev->phy.rev >= 7) {
5466 b43_radio_2057_init(dev);
5467 b43_switch_channel(dev, dev->phy.channel);
5468 } else if (dev->phy.rev >= 3) {
d817f4e1 5469 b43_radio_init2056(dev);
78159788 5470 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5471 } else {
5472 b43_radio_init2055(dev);
5473 }
5474 }
ef1a628d
MB		 5475}
5476
0f4091b9 5477/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5478static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5479{
2a870831
RM		 5480 u16 override = on ? 0x0 : 0x7FFF;
5481 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5482
2a870831
RM		 5483 if (dev->phy.rev >= 3) {
5484 if (on) {
5485 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5486 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5487 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5488 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5489 } else {
5490 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5491 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5492 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5493 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5494 }
5495 } else {
5496 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5497 }
cb24f57f
MB		 5498}
5499
ef1a628d
MB		 5500static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5501 unsigned int new_channel)
5502{
675a0b04
KB		 5503 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5504 enum nl80211_channel_type channel_type =
5505 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5506
ef1a628d
MB		 5507 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5508 if ((new_channel < 1) || (new_channel > 14))
5509 return -EINVAL;
5510 } else {
5511 if (new_channel > 200)
5512 return -EINVAL;
5513 }
5514
a656b6a9 5515 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5516}
5517
5518static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5519{
5520 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5521 return 1;
5522 return 36;
5523}
5524
ef1a628d
MB		 5525const struct b43_phy_operations b43_phyops_n = {
5526 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5527 .free = b43_nphy_op_free,
5528 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5529 .init = b43_nphy_op_init,
ef1a628d
MB		 5530 .phy_read = b43_nphy_op_read,
5531 .phy_write = b43_nphy_op_write,
755fd183 5532 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5533 .radio_read = b43_nphy_op_radio_read,
5534 .radio_write = b43_nphy_op_radio_write,
5535 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5536 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5537 .switch_channel = b43_nphy_op_switch_channel,
5538 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5539 .recalc_txpower = b43_nphy_op_recalc_txpower,
5540 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5541};
Linux kernel - Deliverables
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