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b43: silence most sparse warnings
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b 25#include <linux/delay.h>
5a0e3ad6 26#include <linux/slab.h>
819d772b
JL		 27#include <linux/types.h>
28
424047e6 29#include "b43.h"
3d0da751 30#include "phy_n.h"
53a6e234 31#include "tables_nphy.h"
bbec398c 32#include "main.h"
424047e6 33
f8187b5b
RM		 34struct nphy_txgains {
35 u16 txgm[2];
36 u16 pga[2];
37 u16 pad[2];
38 u16 ipa[2];
39};
40
41struct nphy_iqcal_params {
42 u16 txgm;
43 u16 pga;
44 u16 pad;
45 u16 ipa;
46 u16 cal_gain;
47 u16 ncorr[5];
48};
49
50struct nphy_iq_est {
51 s32 iq0_prod;
52 u32 i0_pwr;
53 u32 q0_pwr;
54 s32 iq1_prod;
55 u32 i1_pwr;
56 u32 q1_pwr;
57};
424047e6 58
67c0d6e2
RM		 59enum b43_nphy_rf_sequence {
60 B43_RFSEQ_RX2TX,
61 B43_RFSEQ_TX2RX,
62 B43_RFSEQ_RESET2RX,
63 B43_RFSEQ_UPDATE_GAINH,
64 B43_RFSEQ_UPDATE_GAINL,
65 B43_RFSEQ_UPDATE_GAINU,
66};
67
9501fefe
RM		 68static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
69 u8 *events, u8 *delays, u8 length);
67c0d6e2
RM		 70static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
71 enum b43_nphy_rf_sequence seq);
67cbc3ed
RM		 72static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
73 u16 value, u8 core, bool off);
74static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
75 u16 value, u8 core);
eff66c51 76static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
67c0d6e2 77
902db91d
RM		 78static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
79{
80 return !chanspec->channel && !chanspec->sideband &&
81 !chanspec->b_width && !chanspec->b_freq;
82}
83
84static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1,
85 struct b43_chanspec *chanspec2)
86{
87 return (chanspec1->channel == chanspec2->channel &&
88 chanspec1->sideband == chanspec2->sideband &&
89 chanspec1->b_width == chanspec2->b_width &&
90 chanspec1->b_freq == chanspec2->b_freq);
91}
92
53a6e234
MB		 93void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
94{//TODO
95}
96
18c8adeb 97static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 98{//TODO
99}
100
18c8adeb
MB		 101static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
102 bool ignore_tssi)
103{//TODO
104 return B43_TXPWR_RES_DONE;
105}
106
d1591314 107static void b43_chantab_radio_upload(struct b43_wldev *dev,
f19ebe7d 108 const struct b43_nphy_channeltab_entry_rev2 *e)
d1591314 109{
e5255ccc
RM		 110 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
111 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
112 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
113 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
114 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
115
116 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
117 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
118 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
119 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
120 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
121
122 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
123 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
124 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
125 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
126 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
127
128 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
129 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
130 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
131 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
132 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
133
134 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
135 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
136 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
137 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
138 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
139
140 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
141 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
d1591314
MB		 142}
143
144static void b43_chantab_phy_upload(struct b43_wldev *dev,
b15b3039 145 const struct b43_phy_n_sfo_cfg *e)
d1591314
MB		 146{
147 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
148 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
149 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
150 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
151 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
152 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
153}
154
155static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
156{
157 //TODO
158}
159
7955de0c
RM		 160
161/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
162static void b43_radio_2055_setup(struct b43_wldev *dev,
f19ebe7d 163 const struct b43_nphy_channeltab_entry_rev2 *e)
7955de0c
RM		 164{
165 B43_WARN_ON(dev->phy.rev >= 3);
166
167 b43_chantab_radio_upload(dev, e);
168 udelay(50);
e58b1253
RM		 169 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
170 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
7955de0c 171 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e58b1253 172 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
7955de0c
RM		 173 udelay(300);
174}
175
53a6e234
MB		 176static void b43_radio_init2055_pre(struct b43_wldev *dev)
177{
178 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
179 ~B43_NPHY_RFCTL_CMD_PORFORCE);
180 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
181 B43_NPHY_RFCTL_CMD_CHIP0PU |
182 B43_NPHY_RFCTL_CMD_OEPORFORCE);
183 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
184 B43_NPHY_RFCTL_CMD_PORFORCE);
185}
186
187static void b43_radio_init2055_post(struct b43_wldev *dev)
188{
036cafe4 189 struct b43_phy_n *nphy = dev->phy.n;
53a6e234
MB		 190 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
191 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
192 int i;
193 u16 val;
036cafe4
RM		 194 bool workaround = false;
195
196 if (sprom->revision < 4)
197 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
198 binfo->type != 0x46D ||
199 binfo->rev < 0x41);
200 else
201 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
53a6e234
MB		 202
203 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
036cafe4
RM		 204 if (workaround) {
205 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
206 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
53a6e234 207 }
036cafe4
RM		 208 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
209 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
53a6e234 210 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
53a6e234 211 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
53a6e234
MB		 212 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
213 msleep(1);
214 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
036cafe4
RM		 215 for (i = 0; i < 200; i++) {
216 val = b43_radio_read(dev, B2055_CAL_COUT2);
217 if (val & 0x80) {
218 i = 0;
53a6e234 219 break;
036cafe4 220 }
53a6e234
MB		 221 udelay(10);
222 }
036cafe4
RM		 223 if (i)
224 b43err(dev->wl, "radio post init timeout\n");
53a6e234 225 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
ef1a628d 226 nphy_channel_switch(dev, dev->phy.channel);
036cafe4
RM		 227 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
228 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
229 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
230 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
231 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
232 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
233 if (!nphy->gain_boost) {
234 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
235 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
236 } else {
237 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
238 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
239 }
240 udelay(2);
53a6e234
MB		 241}
242
c2b7aefd
RM		 243/*
244 * Initialize a Broadcom 2055 N-radio
245 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
246 */
53a6e234
MB		 247static void b43_radio_init2055(struct b43_wldev *dev)
248{
249 b43_radio_init2055_pre(dev);
250 if (b43_status(dev) < B43_STAT_INITIALIZED)
251 b2055_upload_inittab(dev, 0, 1);
252 else
253 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
254 b43_radio_init2055_post(dev);
255}
256
d817f4e1
RM		 257/*
258 * Initialize a Broadcom 2056 N-radio
259 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
260 */
261static void b43_radio_init2056(struct b43_wldev *dev)
262{
263 /* TODO */
264}
265
266
4772ae10
RM		 267/*
268 * Upload the N-PHY tables.
269 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
270 */
95b66bad
MB		 271static void b43_nphy_tables_init(struct b43_wldev *dev)
272{
4772ae10
RM		 273 if (dev->phy.rev < 3)
274 b43_nphy_rev0_1_2_tables_init(dev);
275 else
276 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 277}
278
e50cbcf6
RM		 279/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
280static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
281{
282 struct b43_phy_n *nphy = dev->phy.n;
283 enum ieee80211_band band;
284 u16 tmp;
285
286 if (!enable) {
287 nphy->rfctrl_intc1_save = b43_phy_read(dev,
288 B43_NPHY_RFCTL_INTC1);
289 nphy->rfctrl_intc2_save = b43_phy_read(dev,
290 B43_NPHY_RFCTL_INTC2);
291 band = b43_current_band(dev->wl);
292 if (dev->phy.rev >= 3) {
293 if (band == IEEE80211_BAND_5GHZ)
294 tmp = 0x600;
295 else
296 tmp = 0x480;
297 } else {
298 if (band == IEEE80211_BAND_5GHZ)
299 tmp = 0x180;
300 else
301 tmp = 0x120;
302 }
303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
304 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
305 } else {
306 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
307 nphy->rfctrl_intc1_save);
308 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
309 nphy->rfctrl_intc2_save);
310 }
311}
312
fe3e46e8
RM		 313/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
314static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
315{
316 struct b43_phy_n *nphy = dev->phy.n;
317 u16 tmp;
318 enum ieee80211_band band = b43_current_band(dev->wl);
319 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
320 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
321
322 if (dev->phy.rev >= 3) {
323 if (ipa) {
324 tmp = 4;
325 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
326 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
327 }
328
329 tmp = 1;
330 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
331 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
332 }
333}
334
4a933c85
RM		 335/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
336static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
337{
338 u32 tmslow;
339
340 if (dev->phy.type != B43_PHYTYPE_N)
341 return;
342
343 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
344 if (force)
345 tmslow |= SSB_TMSLOW_FGC;
346 else
347 tmslow &= ~SSB_TMSLOW_FGC;
348 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
349}
350
351/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 352static void b43_nphy_reset_cca(struct b43_wldev *dev)
353{
354 u16 bbcfg;
355
4a933c85 356 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 357 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 358 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
359 udelay(1);
360 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
361 b43_nphy_bmac_clock_fgc(dev, 0);
67c0d6e2 362 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 363}
364
ad9716e8
RM		 365/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
366static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
367{
368 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
369
370 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
371 if (preamble == 1)
372 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
373 else
374 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
375
376 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
377}
378
4f4ab6cd
RM		 379/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
380static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
381{
382 struct b43_phy_n *nphy = dev->phy.n;
383
384 bool override = false;
385 u16 chain = 0x33;
386
387 if (nphy->txrx_chain == 0) {
388 chain = 0x11;
389 override = true;
390 } else if (nphy->txrx_chain == 1) {
391 chain = 0x22;
392 override = true;
393 }
394
395 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
396 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
397 chain);
398
399 if (override)
400 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
401 B43_NPHY_RFSEQMODE_CAOVER);
402 else
403 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
404 ~B43_NPHY_RFSEQMODE_CAOVER);
405}
406
2faa6b83
RM		 407/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
408static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
409 u16 samps, u8 time, bool wait)
410{
411 int i;
412 u16 tmp;
413
414 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
415 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
416 if (wait)
417 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
418 else
419 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
420
421 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
422
423 for (i = 1000; i; i--) {
424 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
425 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
426 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
427 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
428 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
429 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
430 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
432
433 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
434 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
435 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
436 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
437 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
438 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
439 return;
440 }
441 udelay(10);
442 }
443 memset(est, 0, sizeof(*est));
444}
445
a67162ab
RM		 446/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
447static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
448 struct b43_phy_n_iq_comp *pcomp)
449{
450 if (write) {
451 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
452 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
453 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
454 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
455 } else {
456 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
457 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
458 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
459 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
460 }
461}
462
026816fc
RM		 463/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
464static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
465{
466 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
467
468 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
469 if (core == 0) {
470 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
471 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
472 } else {
473 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
474 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
475 }
476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
477 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
478 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
479 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
480 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
481 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
482 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
483 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
484}
485
486/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
487static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
488{
489 u8 rxval, txval;
490 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
491
492 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
493 if (core == 0) {
494 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
495 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
496 } else {
497 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
498 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
499 }
500 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
501 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
502 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
503 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
504 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
505 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
506 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
507 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
508
509 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
510 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
511
512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
513 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
514 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
515 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
516 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
517 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
518 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
519 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
520
521 if (core == 0) {
522 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
523 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
524 } else {
525 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
527 }
528
67cbc3ed
RM		 529 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
530 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 531 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 532
533 if (core == 0) {
534 rxval = 1;
535 txval = 8;
536 } else {
537 rxval = 4;
538 txval = 2;
539 }
67cbc3ed
RM		 540 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
541 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc
RM		 542}
543
34a56f2c
RM		 544/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
545static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
546{
547 int i;
548 s32 iq;
549 u32 ii;
550 u32 qq;
551 int iq_nbits, qq_nbits;
552 int arsh, brsh;
553 u16 tmp, a, b;
554
555 struct nphy_iq_est est;
556 struct b43_phy_n_iq_comp old;
557 struct b43_phy_n_iq_comp new = { };
558 bool error = false;
559
560 if (mask == 0)
561 return;
562
563 b43_nphy_rx_iq_coeffs(dev, false, &old);
564 b43_nphy_rx_iq_coeffs(dev, true, &new);
565 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
566 new = old;
567
568 for (i = 0; i < 2; i++) {
569 if (i == 0 && (mask & 1)) {
570 iq = est.iq0_prod;
571 ii = est.i0_pwr;
572 qq = est.q0_pwr;
573 } else if (i == 1 && (mask & 2)) {
574 iq = est.iq1_prod;
575 ii = est.i1_pwr;
576 qq = est.q1_pwr;
577 } else {
578 B43_WARN_ON(1);
579 continue;
580 }
581
582 if (ii + qq < 2) {
583 error = true;
584 break;
585 }
586
587 iq_nbits = fls(abs(iq));
588 qq_nbits = fls(qq);
589
590 arsh = iq_nbits - 20;
591 if (arsh >= 0) {
592 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
593 tmp = ii >> arsh;
594 } else {
595 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
596 tmp = ii << -arsh;
597 }
598 if (tmp == 0) {
599 error = true;
600 break;
601 }
602 a /= tmp;
603
604 brsh = qq_nbits - 11;
605 if (brsh >= 0) {
606 b = (qq << (31 - qq_nbits));
607 tmp = ii >> brsh;
608 } else {
609 b = (qq << (31 - qq_nbits));
610 tmp = ii << -brsh;
611 }
612 if (tmp == 0) {
613 error = true;
614 break;
615 }
616 b = int_sqrt(b / tmp - a * a) - (1 << 10);
617
618 if (i == 0 && (mask & 0x1)) {
619 if (dev->phy.rev >= 3) {
620 new.a0 = a & 0x3FF;
621 new.b0 = b & 0x3FF;
622 } else {
623 new.a0 = b & 0x3FF;
624 new.b0 = a & 0x3FF;
625 }
626 } else if (i == 1 && (mask & 0x2)) {
627 if (dev->phy.rev >= 3) {
628 new.a1 = a & 0x3FF;
629 new.b1 = b & 0x3FF;
630 } else {
631 new.a1 = b & 0x3FF;
632 new.b1 = a & 0x3FF;
633 }
634 }
635 }
636
637 if (error)
638 new = old;
639
640 b43_nphy_rx_iq_coeffs(dev, true, &new);
641}
642
09146400
RM		 643/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
644static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
645{
646 u16 array[4];
647 int i;
648
649 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
650 for (i = 0; i < 4; i++)
651 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
652
653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
656 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
657}
658
bbec398c
RM		 659/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
660static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
661{
662 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
663 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
664}
665
666/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
667static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
668{
669 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
670 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
671}
672
8987a9e9
RM		 673/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
674static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
675{
676 if (dev->phy.rev >= 3) {
677 if (!init)
678 return;
679 if (0 /* FIXME */) {
680 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
681 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
682 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
683 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
684 }
685 } else {
686 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
687 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
688
689 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
690 0xFC00);
691 b43_write32(dev, B43_MMIO_MACCTL,
692 b43_read32(dev, B43_MMIO_MACCTL) &
693 ~B43_MACCTL_GPOUTSMSK);
694 b43_write16(dev, B43_MMIO_GPIO_MASK,
695 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
696 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
697 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
698
699 if (init) {
700 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
701 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
702 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
703 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
704 }
705 }
706}
707
bbec398c
RM		 708/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
709static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
710{
711 u16 tmp;
712
713 if (dev->dev->id.revision == 16)
714 b43_mac_suspend(dev);
715
716 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
717 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
718 B43_NPHY_CLASSCTL_WAITEDEN);
719 tmp &= ~mask;
720 tmp |= (val & mask);
721 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
722
723 if (dev->dev->id.revision == 16)
724 b43_mac_enable(dev);
725
726 return tmp;
727}
728
5c1a140a
RM		 729/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
730static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
731{
732 struct b43_phy *phy = &dev->phy;
733 struct b43_phy_n *nphy = phy->n;
734
735 if (enable) {
736 u16 clip[] = { 0xFFFF, 0xFFFF };
737 if (nphy->deaf_count++ == 0) {
738 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
739 b43_nphy_classifier(dev, 0x7, 0);
740 b43_nphy_read_clip_detection(dev, nphy->clip_state);
741 b43_nphy_write_clip_detection(dev, clip);
742 }
743 b43_nphy_reset_cca(dev);
744 } else {
745 if (--nphy->deaf_count == 0) {
746 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
747 b43_nphy_write_clip_detection(dev, nphy->clip_state);
748 }
749 }
750}
751
53ae8e8c
RM		 752/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
753static void b43_nphy_stop_playback(struct b43_wldev *dev)
754{
755 struct b43_phy_n *nphy = dev->phy.n;
756 u16 tmp;
757
758 if (nphy->hang_avoid)
759 b43_nphy_stay_in_carrier_search(dev, 1);
760
761 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
762 if (tmp & 0x1)
763 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
764 else if (tmp & 0x2)
765 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
766
767 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
768
769 if (nphy->bb_mult_save & 0x80000000) {
770 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 771 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 772 nphy->bb_mult_save = 0;
773 }
774
775 if (nphy->hang_avoid)
776 b43_nphy_stay_in_carrier_search(dev, 0);
777}
778
9442e5b5
RM		 779/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
780static void b43_nphy_spur_workaround(struct b43_wldev *dev)
781{
782 struct b43_phy_n *nphy = dev->phy.n;
783
902db91d 784 u8 channel = nphy->radio_chanspec.channel;
9442e5b5
RM		 785 int tone[2] = { 57, 58 };
786 u32 noise[2] = { 0x3FF, 0x3FF };
787
788 B43_WARN_ON(dev->phy.rev < 3);
789
790 if (nphy->hang_avoid)
791 b43_nphy_stay_in_carrier_search(dev, 1);
792
9442e5b5
RM		 793 if (nphy->gband_spurwar_en) {
794 /* TODO: N PHY Adjust Analog Pfbw (7) */
795 if (channel == 11 && dev->phy.is_40mhz)
796 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
797 else
798 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
799 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
800 }
801
802 if (nphy->aband_spurwar_en) {
803 if (channel == 54) {
804 tone[0] = 0x20;
805 noise[0] = 0x25F;
806 } else if (channel == 38 || channel == 102 || channel == 118) {
807 if (0 /* FIXME */) {
808 tone[0] = 0x20;
809 noise[0] = 0x21F;
810 } else {
811 tone[0] = 0;
812 noise[0] = 0;
813 }
814 } else if (channel == 134) {
815 tone[0] = 0x20;
816 noise[0] = 0x21F;
817 } else if (channel == 151) {
818 tone[0] = 0x10;
819 noise[0] = 0x23F;
820 } else if (channel == 153 || channel == 161) {
821 tone[0] = 0x30;
822 noise[0] = 0x23F;
823 } else {
824 tone[0] = 0;
825 noise[0] = 0;
826 }
827
828 if (!tone[0] && !noise[0])
829 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
830 else
831 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
832 }
833
834 if (nphy->hang_avoid)
835 b43_nphy_stay_in_carrier_search(dev, 0);
836}
837
d24019ad
RM		 838/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
839static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
840{
841 struct b43_phy_n *nphy = dev->phy.n;
842
843 u8 i;
844 s16 tmp;
845 u16 data[4];
846 s16 gain[2];
847 u16 minmax[2];
848 u16 lna_gain[4] = { -2, 10, 19, 25 };
849
850 if (nphy->hang_avoid)
851 b43_nphy_stay_in_carrier_search(dev, 1);
852
853 if (nphy->gain_boost) {
854 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
855 gain[0] = 6;
856 gain[1] = 6;
857 } else {
858 tmp = 40370 - 315 * nphy->radio_chanspec.channel;
859 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
860 tmp = 23242 - 224 * nphy->radio_chanspec.channel;
861 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
862 }
863 } else {
864 gain[0] = 0;
865 gain[1] = 0;
866 }
867
868 for (i = 0; i < 2; i++) {
869 if (nphy->elna_gain_config) {
870 data[0] = 19 + gain[i];
871 data[1] = 25 + gain[i];
872 data[2] = 25 + gain[i];
873 data[3] = 25 + gain[i];
874 } else {
875 data[0] = lna_gain[0] + gain[i];
876 data[1] = lna_gain[1] + gain[i];
877 data[2] = lna_gain[2] + gain[i];
878 data[3] = lna_gain[3] + gain[i];
879 }
880 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
881
882 minmax[i] = 23 + gain[i];
883 }
884
885 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
886 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
887 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
888 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
889
890 if (nphy->hang_avoid)
891 b43_nphy_stay_in_carrier_search(dev, 0);
892}
893
ef5127a4
RM		 894/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
895static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
896{
897 struct b43_phy_n *nphy = dev->phy.n;
898 u8 i, j;
899 u8 code;
900
901 /* TODO: for PHY >= 3
902 s8 *lna1_gain, *lna2_gain;
903 u8 *gain_db, *gain_bits;
904 u16 *rfseq_init;
905 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
906 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
907 */
908
909 u8 rfseq_events[3] = { 6, 8, 7 };
910 u8 rfseq_delays[3] = { 10, 30, 1 };
911
912 if (dev->phy.rev >= 3) {
913 /* TODO */
914 } else {
915 /* Set Clip 2 detect */
916 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
917 B43_NPHY_C1_CGAINI_CL2DETECT);
918 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
919 B43_NPHY_C2_CGAINI_CL2DETECT);
920
921 /* Set narrowband clip threshold */
922 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
923 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
924
925 if (!dev->phy.is_40mhz) {
926 /* Set dwell lengths */
927 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
928 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
929 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
930 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
931 }
932
933 /* Set wideband clip 2 threshold */
934 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
935 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
936 21);
937 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
938 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
939 21);
940
941 if (!dev->phy.is_40mhz) {
942 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
943 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
944 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
945 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
946 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
947 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
948 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
949 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
950 }
951
952 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
953
954 if (nphy->gain_boost) {
955 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
956 dev->phy.is_40mhz)
957 code = 4;
958 else
959 code = 5;
960 } else {
961 code = dev->phy.is_40mhz ? 6 : 7;
962 }
963
964 /* Set HPVGA2 index */
965 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
966 ~B43_NPHY_C1_INITGAIN_HPVGA2,
967 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
968 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
969 ~B43_NPHY_C2_INITGAIN_HPVGA2,
970 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
971
972 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
973 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
974 (code << 8 | 0x7C));
975 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
976 (code << 8 | 0x7C));
977
d24019ad 978 b43_nphy_adjust_lna_gain_table(dev);
ef5127a4
RM		 979
980 if (nphy->elna_gain_config) {
981 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
985 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
986
987 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
988 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
991 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
992
993 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
994 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
995 (code << 8 | 0x74));
996 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
997 (code << 8 | 0x74));
998 }
999
1000 if (dev->phy.rev == 2) {
1001 for (i = 0; i < 4; i++) {
1002 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1003 (0x0400 * i) + 0x0020);
1004 for (j = 0; j < 21; j++)
1005 b43_phy_write(dev,
1006 B43_NPHY_TABLE_DATALO, 3 * j);
1007 }
1008
9501fefe
RM		 1009 b43_nphy_set_rf_sequence(dev, 5,
1010 rfseq_events, rfseq_delays, 3);
ef5127a4
RM		 1011 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1012 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
1013 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1014
1015 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1016 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1017 0xFF80, 4);
1018 }
1019 }
1020}
1021
28fd7daa
RM		 1022/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1023static void b43_nphy_workarounds(struct b43_wldev *dev)
1024{
1025 struct ssb_bus *bus = dev->dev->bus;
1026 struct b43_phy *phy = &dev->phy;
1027 struct b43_phy_n *nphy = phy->n;
1028
1029 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1030 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1031
1032 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1033 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1034
1035 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1036 b43_nphy_classifier(dev, 1, 0);
1037 else
1038 b43_nphy_classifier(dev, 1, 1);
1039
1040 if (nphy->hang_avoid)
1041 b43_nphy_stay_in_carrier_search(dev, 1);
1042
1043 b43_phy_set(dev, B43_NPHY_IQFLIP,
1044 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1045
1046 if (dev->phy.rev >= 3) {
1047 /* TODO */
1048 } else {
1049 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1050 nphy->band5g_pwrgain) {
1051 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1052 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1053 } else {
1054 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1055 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1056 }
1057
1058 /* TODO: convert to b43_ntab_write? */
1059 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1060 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1061 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1062 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1063 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1064 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1065 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1066 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1067
1068 if (dev->phy.rev < 2) {
1069 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1070 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1071 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1072 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1073 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1074 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1075 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1076 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1077 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1078 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1079 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1080 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1081 }
1082
1083 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1084 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1085 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1086 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1087
1088 if (bus->sprom.boardflags2_lo & 0x100 &&
1089 bus->boardinfo.type == 0x8B) {
1090 delays1[0] = 0x1;
1091 delays1[5] = 0x14;
1092 }
9501fefe
RM		 1093 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1094 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
28fd7daa 1095
ef5127a4 1096 b43_nphy_gain_crtl_workarounds(dev);
28fd7daa
RM		 1097
1098 if (dev->phy.rev < 2) {
1099 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1100 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1101 } else if (dev->phy.rev == 2) {
1102 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1103 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1104 }
1105
1106 if (dev->phy.rev < 2)
1107 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1108 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1109
1110 /* Set phase track alpha and beta */
1111 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1112 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1113 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1114 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1115 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1116 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1117
1118 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1119 (u16)~B43_NPHY_PIL_DW_64QAM);
1120 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1121 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1122 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1123
1124 if (dev->phy.rev == 2)
1125 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1126 B43_NPHY_FINERX2_CGC_DECGC);
1127 }
1128
1129 if (nphy->hang_avoid)
1130 b43_nphy_stay_in_carrier_search(dev, 0);
1131}
1132
5f6393ec
RM		 1133/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1134static int b43_nphy_load_samples(struct b43_wldev *dev,
1135 struct b43_c32 *samples, u16 len) {
1136 struct b43_phy_n *nphy = dev->phy.n;
1137 u16 i;
1138 u32 *data;
1139
1140 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1141 if (!data) {
1142 b43err(dev->wl, "allocation for samples loading failed\n");
1143 return -ENOMEM;
1144 }
1145 if (nphy->hang_avoid)
1146 b43_nphy_stay_in_carrier_search(dev, 1);
1147
1148 for (i = 0; i < len; i++) {
1149 data[i] = (samples[i].i & 0x3FF << 10);
1150 data[i] |= samples[i].q & 0x3FF;
1151 }
1152 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1153
1154 kfree(data);
1155 if (nphy->hang_avoid)
1156 b43_nphy_stay_in_carrier_search(dev, 0);
1157 return 0;
1158}
1159
59af099b
RM		 1160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1161static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1162 bool test)
1163{
1164 int i;
f2982181 1165 u16 bw, len, rot, angle;
da860475 1166 struct b43_c32 *samples;
f2982181 1167
59af099b
RM		 1168
1169 bw = (dev->phy.is_40mhz) ? 40 : 20;
1170 len = bw << 3;
1171
1172 if (test) {
1173 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1174 bw = 82;
1175 else
1176 bw = 80;
1177
1178 if (dev->phy.is_40mhz)
1179 bw <<= 1;
1180
1181 len = bw << 1;
1182 }
1183
da860475 1184 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
40bd5203
RM		 1185 if (!samples) {
1186 b43err(dev->wl, "allocation for samples generation failed\n");
1187 return 0;
1188 }
59af099b
RM		 1189 rot = (((freq * 36) / bw) << 16) / 100;
1190 angle = 0;
1191
f2982181
RM		 1192 for (i = 0; i < len; i++) {
1193 samples[i] = b43_cordic(angle);
1194 angle += rot;
1195 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1196 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
59af099b
RM		 1197 }
1198
5f6393ec 1199 i = b43_nphy_load_samples(dev, samples, len);
f2982181 1200 kfree(samples);
5f6393ec 1201 return (i < 0) ? 0 : len;
59af099b
RM		 1202}
1203
10a79873
RM		 1204/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1205static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1206 u16 wait, bool iqmode, bool dac_test)
1207{
1208 struct b43_phy_n *nphy = dev->phy.n;
1209 int i;
1210 u16 seq_mode;
1211 u32 tmp;
1212
1213 if (nphy->hang_avoid)
1214 b43_nphy_stay_in_carrier_search(dev, true);
1215
1216 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1217 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1218 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1219 }
1220
1221 if (!dev->phy.is_40mhz)
1222 tmp = 0x6464;
1223 else
1224 tmp = 0x4747;
1225 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1226
1227 if (nphy->hang_avoid)
1228 b43_nphy_stay_in_carrier_search(dev, false);
1229
1230 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1231
1232 if (loops != 0xFFFF)
1233 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1234 else
1235 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1236
1237 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1238
1239 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1240
1241 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1242 if (iqmode) {
1243 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1244 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1245 } else {
1246 if (dac_test)
1247 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1248 else
1249 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1250 }
1251 for (i = 0; i < 100; i++) {
1252 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1253 i = 0;
1254 break;
1255 }
1256 udelay(10);
1257 }
1258 if (i)
1259 b43err(dev->wl, "run samples timeout\n");
1260
1261 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1262}
1263
59af099b
RM		 1264/*
1265 * Transmits a known value for LO calibration
1266 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1267 */
1268static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1269 bool iqmode, bool dac_test)
1270{
1271 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1272 if (samp == 0)
1273 return -1;
1274 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1275 return 0;
1276}
1277
6dcd9d91
RM		 1278/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1279static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1280{
1281 struct b43_phy_n *nphy = dev->phy.n;
1282 int i, j;
1283 u32 tmp;
1284 u32 cur_real, cur_imag, real_part, imag_part;
1285
1286 u16 buffer[7];
1287
1288 if (nphy->hang_avoid)
1289 b43_nphy_stay_in_carrier_search(dev, true);
1290
9145834e 1291 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 1292
1293 for (i = 0; i < 2; i++) {
1294 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1295 (buffer[i * 2 + 1] & 0x3FF);
1296 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1297 (((i + 26) << 10) | 320));
1298 for (j = 0; j < 128; j++) {
1299 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1300 ((tmp >> 16) & 0xFFFF));
1301 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1302 (tmp & 0xFFFF));
1303 }
1304 }
1305
1306 for (i = 0; i < 2; i++) {
1307 tmp = buffer[5 + i];
1308 real_part = (tmp >> 8) & 0xFF;
1309 imag_part = (tmp & 0xFF);
1310 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1311 (((i + 26) << 10) | 448));
1312
1313 if (dev->phy.rev >= 3) {
1314 cur_real = real_part;
1315 cur_imag = imag_part;
1316 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1317 }
1318
1319 for (j = 0; j < 128; j++) {
1320 if (dev->phy.rev < 3) {
1321 cur_real = (real_part * loscale[j] + 128) >> 8;
1322 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1323 tmp = ((cur_real & 0xFF) << 8) |
1324 (cur_imag & 0xFF);
1325 }
1326 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1327 ((tmp >> 16) & 0xFFFF));
1328 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1329 (tmp & 0xFFFF));
1330 }
1331 }
1332
1333 if (dev->phy.rev >= 3) {
1334 b43_shm_write16(dev, B43_SHM_SHARED,
1335 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1336 b43_shm_write16(dev, B43_SHM_SHARED,
1337 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1338 }
1339
1340 if (nphy->hang_avoid)
1341 b43_nphy_stay_in_carrier_search(dev, false);
1342}
1343
9501fefe
RM		 1344/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1345static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1346 u8 *events, u8 *delays, u8 length)
1347{
1348 struct b43_phy_n *nphy = dev->phy.n;
1349 u8 i;
1350 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1351 u16 offset1 = cmd << 4;
1352 u16 offset2 = offset1 + 0x80;
1353
1354 if (nphy->hang_avoid)
1355 b43_nphy_stay_in_carrier_search(dev, true);
1356
1357 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1358 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1359
1360 for (i = length; i < 16; i++) {
1361 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1362 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1363 }
1364
1365 if (nphy->hang_avoid)
1366 b43_nphy_stay_in_carrier_search(dev, false);
1367}
1368
67c0d6e2 1369/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 1370static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1371 enum b43_nphy_rf_sequence seq)
1372{
1373 static const u16 trigger[] = {
1374 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1375 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1376 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1377 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1378 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1379 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1380 };
1381 int i;
c57199bc 1382 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
95b66bad
MB		 1383
1384 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1385
1386 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1387 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1388 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1389 for (i = 0; i < 200; i++) {
1390 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1391 goto ok;
1392 msleep(1);
1393 }
1394 b43err(dev->wl, "RF sequence status timeout\n");
1395ok:
c57199bc 1396 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
95b66bad
MB		 1397}
1398
75377b24
RM		 1399/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1400static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1401 u16 value, u8 core, bool off)
1402{
1403 int i;
1404 u8 index = fls(field);
1405 u8 addr, en_addr, val_addr;
1406 /* we expect only one bit set */
3ed0fac3 1407 B43_WARN_ON(field & (~(1 << (index - 1))));
75377b24
RM		 1408
1409 if (dev->phy.rev >= 3) {
1410 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1411 for (i = 0; i < 2; i++) {
1412 if (index == 0 || index == 16) {
1413 b43err(dev->wl,
1414 "Unsupported RF Ctrl Override call\n");
1415 return;
1416 }
1417
1418 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1419 en_addr = B43_PHY_N((i == 0) ?
1420 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1421 val_addr = B43_PHY_N((i == 0) ?
1422 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1423
1424 if (off) {
1425 b43_phy_mask(dev, en_addr, ~(field));
1426 b43_phy_mask(dev, val_addr,
1427 ~(rf_ctrl->val_mask));
1428 } else {
1429 if (core == 0 || ((1 << core) & i) != 0) {
1430 b43_phy_set(dev, en_addr, field);
1431 b43_phy_maskset(dev, val_addr,
1432 ~(rf_ctrl->val_mask),
1433 (value << rf_ctrl->val_shift));
1434 }
1435 }
1436 }
1437 } else {
1438 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1439 if (off) {
1440 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1441 value = 0;
1442 } else {
1443 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1444 }
1445
1446 for (i = 0; i < 2; i++) {
1447 if (index <= 1 || index == 16) {
1448 b43err(dev->wl,
1449 "Unsupported RF Ctrl Override call\n");
1450 return;
1451 }
1452
1453 if (index == 2 || index == 10 ||
1454 (index >= 13 && index <= 15)) {
1455 core = 1;
1456 }
1457
1458 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1459 addr = B43_PHY_N((i == 0) ?
1460 rf_ctrl->addr0 : rf_ctrl->addr1);
1461
1462 if ((core & (1 << i)) != 0)
1463 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1464 (value << rf_ctrl->shift));
1465
1466 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1467 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1468 B43_NPHY_RFCTL_CMD_START);
1469 udelay(1);
1470 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1471 }
1472 }
1473}
1474
67cbc3ed
RM		 1475/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1476static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1477 u16 value, u8 core)
1478{
1479 u8 i, j;
1480 u16 reg, tmp, val;
1481
1482 B43_WARN_ON(dev->phy.rev < 3);
1483 B43_WARN_ON(field > 4);
1484
1485 for (i = 0; i < 2; i++) {
1486 if ((core == 1 && i == 1) || (core == 2 && !i))
1487 continue;
1488
1489 reg = (i == 0) ?
1490 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1491 b43_phy_mask(dev, reg, 0xFBFF);
1492
1493 switch (field) {
1494 case 0:
1495 b43_phy_write(dev, reg, 0);
1496 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1497 break;
1498 case 1:
1499 if (!i) {
1500 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1501 0xFC3F, (value << 6));
1502 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1503 0xFFFE, 1);
1504 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1505 B43_NPHY_RFCTL_CMD_START);
1506 for (j = 0; j < 100; j++) {
1507 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1508 j = 0;
1509 break;
1510 }
1511 udelay(10);
1512 }
1513 if (j)
1514 b43err(dev->wl,
1515 "intc override timeout\n");
1516 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1517 0xFFFE);
1518 } else {
1519 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1520 0xFC3F, (value << 6));
1521 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1522 0xFFFE, 1);
1523 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1524 B43_NPHY_RFCTL_CMD_RXTX);
1525 for (j = 0; j < 100; j++) {
1526 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1527 j = 0;
1528 break;
1529 }
1530 udelay(10);
1531 }
1532 if (j)
1533 b43err(dev->wl,
1534 "intc override timeout\n");
1535 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1536 0xFFFE);
1537 }
1538 break;
1539 case 2:
1540 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1541 tmp = 0x0020;
1542 val = value << 5;
1543 } else {
1544 tmp = 0x0010;
1545 val = value << 4;
1546 }
1547 b43_phy_maskset(dev, reg, ~tmp, val);
1548 break;
1549 case 3:
1550 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1551 tmp = 0x0001;
1552 val = value;
1553 } else {
1554 tmp = 0x0004;
1555 val = value << 2;
1556 }
1557 b43_phy_maskset(dev, reg, ~tmp, val);
1558 break;
1559 case 4:
1560 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1561 tmp = 0x0002;
1562 val = value << 1;
1563 } else {
1564 tmp = 0x0008;
1565 val = value << 3;
1566 }
1567 b43_phy_maskset(dev, reg, ~tmp, val);
1568 break;
1569 }
1570 }
1571}
1572
95b66bad
MB		 1573static void b43_nphy_bphy_init(struct b43_wldev *dev)
1574{
1575 unsigned int i;
1576 u16 val;
1577
1578 val = 0x1E1F;
1579 for (i = 0; i < 14; i++) {
1580 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1581 val -= 0x202;
1582 }
1583 val = 0x3E3F;
1584 for (i = 0; i < 16; i++) {
1585 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1586 val -= 0x202;
1587 }
1588 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1589}
1590
3c95627d
RM		 1591/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1592static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1593 s8 offset, u8 core, u8 rail, u8 type)
1594{
1595 u16 tmp;
1596 bool core1or5 = (core == 1) || (core == 5);
1597 bool core2or5 = (core == 2) || (core == 5);
1598
1599 offset = clamp_val(offset, -32, 31);
1600 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1601
1602 if (core1or5 && (rail == 0) && (type == 2))
1603 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1604 if (core1or5 && (rail == 1) && (type == 2))
1605 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1606 if (core2or5 && (rail == 0) && (type == 2))
1607 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1608 if (core2or5 && (rail == 1) && (type == 2))
1609 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1610 if (core1or5 && (rail == 0) && (type == 0))
1611 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1612 if (core1or5 && (rail == 1) && (type == 0))
1613 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1614 if (core2or5 && (rail == 0) && (type == 0))
1615 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1616 if (core2or5 && (rail == 1) && (type == 0))
1617 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1618 if (core1or5 && (rail == 0) && (type == 1))
1619 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1620 if (core1or5 && (rail == 1) && (type == 1))
1621 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1622 if (core2or5 && (rail == 0) && (type == 1))
1623 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1624 if (core2or5 && (rail == 1) && (type == 1))
1625 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1626 if (core1or5 && (rail == 0) && (type == 6))
1627 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1628 if (core1or5 && (rail == 1) && (type == 6))
1629 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1630 if (core2or5 && (rail == 0) && (type == 6))
1631 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1632 if (core2or5 && (rail == 1) && (type == 6))
1633 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1634 if (core1or5 && (rail == 0) && (type == 3))
1635 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1636 if (core1or5 && (rail == 1) && (type == 3))
1637 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1638 if (core2or5 && (rail == 0) && (type == 3))
1639 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1640 if (core2or5 && (rail == 1) && (type == 3))
1641 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1642 if (core1or5 && (type == 4))
1643 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1644 if (core2or5 && (type == 4))
1645 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1646 if (core1or5 && (type == 5))
1647 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1648 if (core2or5 && (type == 5))
1649 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1650}
1651
99b82c41 1652static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
3c95627d
RM		 1653{
1654 u16 val;
1655
99b82c41
RM		 1656 if (type < 3)
1657 val = 0;
1658 else if (type == 6)
1659 val = 1;
1660 else if (type == 3)
1661 val = 2;
1662 else
1663 val = 3;
1664
1665 val = (val << 12) | (val << 14);
1666 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1667 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
3c95627d 1668
99b82c41
RM		 1669 if (type < 3) {
1670 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1671 (type + 1) << 4);
1672 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1673 (type + 1) << 4);
1674 }
3c95627d 1675
99b82c41
RM		 1676 /* TODO use some definitions */
1677 if (code == 0) {
1678 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
3c95627d 1679 if (type < 3) {
99b82c41
RM		 1680 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1681 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1682 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1683 udelay(20);
1684 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
3c95627d 1685 }
99b82c41
RM		 1686 } else {
1687 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1688 0x3000);
1689 if (type < 3) {
1690 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1691 0xFEC7, 0x0180);
1692 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1693 0xEFDC, (code << 1 | 0x1021));
1694 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1695 udelay(20);
1696 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
3c95627d
RM		 1697 }
1698 }
1699}
1700
99b82c41
RM		 1701static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1702{
6e3b15a9
RM		 1703 struct b43_phy_n *nphy = dev->phy.n;
1704 u8 i;
1705 u16 reg, val;
1706
1707 if (code == 0) {
1708 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1709 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1710 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1711 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1712 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1713 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1714 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1715 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1716 } else {
1717 for (i = 0; i < 2; i++) {
1718 if ((code == 1 && i == 1) || (code == 2 && !i))
1719 continue;
1720
1721 reg = (i == 0) ?
1722 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1723 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1724
1725 if (type < 3) {
1726 reg = (i == 0) ?
1727 B43_NPHY_AFECTL_C1 :
1728 B43_NPHY_AFECTL_C2;
1729 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1730
1731 reg = (i == 0) ?
1732 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1733 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1734 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1735
1736 if (type == 0)
1737 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1738 else if (type == 1)
1739 val = 16;
1740 else
1741 val = 32;
1742 b43_phy_set(dev, reg, val);
1743
1744 reg = (i == 0) ?
1745 B43_NPHY_TXF_40CO_B1S0 :
1746 B43_NPHY_TXF_40CO_B32S1;
1747 b43_phy_set(dev, reg, 0x0020);
1748 } else {
1749 if (type == 6)
1750 val = 0x0100;
1751 else if (type == 3)
1752 val = 0x0200;
1753 else
1754 val = 0x0300;
1755
1756 reg = (i == 0) ?
1757 B43_NPHY_AFECTL_C1 :
1758 B43_NPHY_AFECTL_C2;
1759
1760 b43_phy_maskset(dev, reg, 0xFCFF, val);
1761 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1762
1763 if (type != 3 && type != 6) {
1764 enum ieee80211_band band =
1765 b43_current_band(dev->wl);
1766
1767 if ((nphy->ipa2g_on &&
1768 band == IEEE80211_BAND_2GHZ) ||
1769 (nphy->ipa5g_on &&
1770 band == IEEE80211_BAND_5GHZ))
1771 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1772 else
1773 val = 0x11;
1774 reg = (i == 0) ? 0x2000 : 0x3000;
1775 reg |= B2055_PADDRV;
1776 b43_radio_write16(dev, reg, val);
1777
1778 reg = (i == 0) ?
1779 B43_NPHY_AFECTL_OVER1 :
1780 B43_NPHY_AFECTL_OVER;
1781 b43_phy_set(dev, reg, 0x0200);
1782 }
1783 }
1784 }
1785 }
99b82c41
RM		 1786}
1787
1788/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1789static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1790{
1791 if (dev->phy.rev >= 3)
1792 b43_nphy_rev3_rssi_select(dev, code, type);
1793 else
1794 b43_nphy_rev2_rssi_select(dev, code, type);
1795}
1796
dfb4aa5d
RM		 1797/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1798static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1799{
1800 int i;
1801 for (i = 0; i < 2; i++) {
1802 if (type == 2) {
1803 if (i == 0) {
1804 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1805 0xFC, buf[0]);
1806 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1807 0xFC, buf[1]);
1808 } else {
1809 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1810 0xFC, buf[2 * i]);
1811 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1812 0xFC, buf[2 * i + 1]);
1813 }
1814 } else {
1815 if (i == 0)
1816 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1817 0xF3, buf[0] << 2);
1818 else
1819 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1820 0xF3, buf[2 * i + 1] << 2);
1821 }
1822 }
1823}
1824
1825/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1826static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1827 u8 nsamp)
1828{
1829 int i;
1830 int out;
1831 u16 save_regs_phy[9];
1832 u16 s[2];
1833
1834 if (dev->phy.rev >= 3) {
1835 save_regs_phy[0] = b43_phy_read(dev,
1836 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1837 save_regs_phy[1] = b43_phy_read(dev,
1838 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1839 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1840 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1841 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1842 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1843 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1844 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1845 }
1846
1847 b43_nphy_rssi_select(dev, 5, type);
1848
1849 if (dev->phy.rev < 2) {
1850 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1851 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1852 }
1853
1854 for (i = 0; i < 4; i++)
1855 buf[i] = 0;
1856
1857 for (i = 0; i < nsamp; i++) {
1858 if (dev->phy.rev < 2) {
1859 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1860 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1861 } else {
1862 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1863 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1864 }
1865
1866 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1867 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1868 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1869 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1870 }
1871 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1872 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1873
1874 if (dev->phy.rev < 2)
1875 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1876
1877 if (dev->phy.rev >= 3) {
1878 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1879 save_regs_phy[0]);
1880 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1881 save_regs_phy[1]);
1882 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1883 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1884 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1885 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1886 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1887 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1888 }
1889
1890 return out;
1891}
1892
4cb99775
RM		 1893/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1894static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 1895{
90b9738d
RM		 1896 int i, j;
1897 u8 state[4];
1898 u8 code, val;
1899 u16 class, override;
1900 u8 regs_save_radio[2];
1901 u16 regs_save_phy[2];
1902 s8 offset[4];
1903
1904 u16 clip_state[2];
1905 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1906 s32 results_min[4] = { };
1907 u8 vcm_final[4] = { };
1908 s32 results[4][4] = { };
1909 s32 miniq[4][2] = { };
1910
1911 if (type == 2) {
1912 code = 0;
1913 val = 6;
1914 } else if (type < 2) {
1915 code = 25;
1916 val = 4;
1917 } else {
1918 B43_WARN_ON(1);
1919 return;
1920 }
1921
1922 class = b43_nphy_classifier(dev, 0, 0);
1923 b43_nphy_classifier(dev, 7, 4);
1924 b43_nphy_read_clip_detection(dev, clip_state);
1925 b43_nphy_write_clip_detection(dev, clip_off);
1926
1927 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1928 override = 0x140;
1929 else
1930 override = 0x110;
1931
1932 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1933 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1935 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1936
1937 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1938 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1939 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1940 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1941
1942 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1943 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1944 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1945 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1946 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1947 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1948
1949 b43_nphy_rssi_select(dev, 5, type);
1950 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1951 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1952
1953 for (i = 0; i < 4; i++) {
1954 u8 tmp[4];
1955 for (j = 0; j < 4; j++)
1956 tmp[j] = i;
1957 if (type != 1)
1958 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1959 b43_nphy_poll_rssi(dev, type, results[i], 8);
1960 if (type < 2)
1961 for (j = 0; j < 2; j++)
1962 miniq[i][j] = min(results[i][2 * j],
1963 results[i][2 * j + 1]);
1964 }
1965
1966 for (i = 0; i < 4; i++) {
1967 s32 mind = 40;
1968 u8 minvcm = 0;
1969 s32 minpoll = 249;
1970 s32 curr;
1971 for (j = 0; j < 4; j++) {
1972 if (type == 2)
1973 curr = abs(results[j][i]);
1974 else
1975 curr = abs(miniq[j][i / 2] - code * 8);
1976
1977 if (curr < mind) {
1978 mind = curr;
1979 minvcm = j;
1980 }
1981
1982 if (results[j][i] < minpoll)
1983 minpoll = results[j][i];
1984 }
1985 results_min[i] = minpoll;
1986 vcm_final[i] = minvcm;
1987 }
1988
1989 if (type != 1)
1990 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1991
1992 for (i = 0; i < 4; i++) {
1993 offset[i] = (code * 8) - results[vcm_final[i]][i];
1994
1995 if (offset[i] < 0)
1996 offset[i] = -((abs(offset[i]) + 4) / 8);
1997 else
1998 offset[i] = (offset[i] + 4) / 8;
1999
2000 if (results_min[i] == 248)
2001 offset[i] = code - 32;
2002
2003 if (i % 2 == 0)
2004 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2005 type);
2006 else
2007 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2008 type);
2009 }
2010
2011 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2012 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2013
2014 switch (state[2]) {
2015 case 1:
2016 b43_nphy_rssi_select(dev, 1, 2);
2017 break;
2018 case 4:
2019 b43_nphy_rssi_select(dev, 1, 0);
2020 break;
2021 case 2:
2022 b43_nphy_rssi_select(dev, 1, 1);
2023 break;
2024 default:
2025 b43_nphy_rssi_select(dev, 1, 1);
2026 break;
2027 }
2028
2029 switch (state[3]) {
2030 case 1:
2031 b43_nphy_rssi_select(dev, 2, 2);
2032 break;
2033 case 4:
2034 b43_nphy_rssi_select(dev, 2, 0);
2035 break;
2036 default:
2037 b43_nphy_rssi_select(dev, 2, 1);
2038 break;
2039 }
2040
2041 b43_nphy_rssi_select(dev, 0, type);
2042
2043 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2044 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2046 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2047
2048 b43_nphy_classifier(dev, 7, class);
2049 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 2050}
2051
2052/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2053static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2054{
2055 /* TODO */
2056}
2057
2058/*
2059 * RSSI Calibration
2060 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2061 */
2062static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2063{
2064 if (dev->phy.rev >= 3) {
2065 b43_nphy_rev3_rssi_cal(dev);
2066 } else {
2067 b43_nphy_rev2_rssi_cal(dev, 2);
2068 b43_nphy_rev2_rssi_cal(dev, 0);
2069 b43_nphy_rev2_rssi_cal(dev, 1);
2070 }
95b66bad
MB		 2071}
2072
42e1547e
RM		 2073/*
2074 * Restore RSSI Calibration
2075 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2076 */
2077static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2078{
2079 struct b43_phy_n *nphy = dev->phy.n;
2080
2081 u16 *rssical_radio_regs = NULL;
2082 u16 *rssical_phy_regs = NULL;
2083
2084 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
902db91d 2085 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G))
42e1547e
RM		 2086 return;
2087 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2088 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2089 } else {
902db91d 2090 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G))
42e1547e
RM		 2091 return;
2092 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2093 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2094 }
2095
2096 /* TODO use some definitions */
2097 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2098 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2099
2100 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2101 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2102 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2103 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2104
2105 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2106 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2107 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2108 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2109
2110 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2111 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2112 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2113 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2114}
2115
2f258b74
RM		 2116/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2117static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2118{
2119 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2120 if (dev->phy.rev >= 6) {
2121 /* TODO If the chip is 47162
2122 return txpwrctrl_tx_gain_ipa_rev5 */
2123 return txpwrctrl_tx_gain_ipa_rev6;
2124 } else if (dev->phy.rev >= 5) {
2125 return txpwrctrl_tx_gain_ipa_rev5;
2126 } else {
2127 return txpwrctrl_tx_gain_ipa;
2128 }
2129 } else {
2130 return txpwrctrl_tx_gain_ipa_5g;
2131 }
2132}
2133
c4a92003
RM		 2134/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2135static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2136{
2137 struct b43_phy_n *nphy = dev->phy.n;
2138 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2139 u16 tmp;
2140 u8 offset, i;
c4a92003
RM		 2141
2142 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2143 for (i = 0; i < 2; i++) {
2144 tmp = (i == 0) ? 0x2000 : 0x3000;
2145 offset = i * 11;
2146
2147 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2148 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2149 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2150 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2151 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2152 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2153 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2154 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2155 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2156 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2157 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2158
2159 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2160 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2161 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2162 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2163 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2164 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2165 if (nphy->ipa5g_on) {
2166 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2167 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2168 } else {
2169 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2170 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2171 }
2172 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2173 } else {
2174 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2175 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2176 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2177 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2178 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2179 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2180 if (nphy->ipa2g_on) {
2181 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2182 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2183 (dev->phy.rev < 5) ? 0x11 : 0x01);
2184 } else {
2185 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2186 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2187 }
2188 }
2189 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2190 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2191 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2192 }
c4a92003
RM		 2193 } else {
2194 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2195 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2196
2197 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2198 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2199
2200 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2201 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2202
2203 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2204 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2205
2206 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2207 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2208
2209 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2210 B43_NPHY_BANDCTL_5GHZ)) {
2211 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2212 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2213 } else {
2214 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2215 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2216 }
2217
2218 if (dev->phy.rev < 2) {
2219 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2220 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2221 } else {
2222 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2223 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2224 }
2225 }
2226}
2227
e9762492
RM		 2228/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2229static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2230 struct nphy_txgains target,
2231 struct nphy_iqcal_params *params)
2232{
2233 int i, j, indx;
2234 u16 gain;
2235
2236 if (dev->phy.rev >= 3) {
2237 params->txgm = target.txgm[core];
2238 params->pga = target.pga[core];
2239 params->pad = target.pad[core];
2240 params->ipa = target.ipa[core];
2241 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2242 (params->pad << 4) | (params->ipa);
2243 for (j = 0; j < 5; j++)
2244 params->ncorr[j] = 0x79;
2245 } else {
2246 gain = (target.pad[core]) | (target.pga[core] << 4) |
2247 (target.txgm[core] << 8);
2248
2249 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2250 1 : 0;
2251 for (i = 0; i < 9; i++)
2252 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2253 break;
2254 i = min(i, 8);
2255
2256 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2257 params->pga = tbl_iqcal_gainparams[indx][i][2];
2258 params->pad = tbl_iqcal_gainparams[indx][i][3];
2259 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2260 (params->pad << 2);
2261 for (j = 0; j < 4; j++)
2262 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2263 }
2264}
2265
de7ed0c6
RM		 2266/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2267static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2268{
2269 struct b43_phy_n *nphy = dev->phy.n;
2270 int i;
2271 u16 scale, entry;
2272
2273 u16 tmp = nphy->txcal_bbmult;
2274 if (core == 0)
2275 tmp >>= 8;
2276 tmp &= 0xff;
2277
2278 for (i = 0; i < 18; i++) {
2279 scale = (ladder_lo[i].percent * tmp) / 100;
2280 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 2281 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 2282
2283 scale = (ladder_iq[i].percent * tmp) / 100;
2284 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 2285 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 2286 }
2287}
2288
45ca697e
RM		 2289/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2290static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2291{
2292 int i;
2293 for (i = 0; i < 15; i++)
2294 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2295 tbl_tx_filter_coef_rev4[2][i]);
2296}
2297
2298/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2299static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2300{
2301 int i, j;
2302 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2303 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2304
2305 for (i = 0; i < 3; i++)
2306 for (j = 0; j < 15; j++)
2307 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2308 tbl_tx_filter_coef_rev4[i][j]);
2309
2310 if (dev->phy.is_40mhz) {
2311 for (j = 0; j < 15; j++)
2312 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2313 tbl_tx_filter_coef_rev4[3][j]);
2314 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2315 for (j = 0; j < 15; j++)
2316 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2317 tbl_tx_filter_coef_rev4[5][j]);
2318 }
2319
2320 if (dev->phy.channel == 14)
2321 for (j = 0; j < 15; j++)
2322 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2323 tbl_tx_filter_coef_rev4[6][j]);
2324}
2325
b0022e15
RM		 2326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2327static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2328{
2329 struct b43_phy_n *nphy = dev->phy.n;
2330
2331 u16 curr_gain[2];
2332 struct nphy_txgains target;
2333 const u32 *table = NULL;
2334
2335 if (nphy->txpwrctrl == 0) {
2336 int i;
2337
2338 if (nphy->hang_avoid)
2339 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 2340 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 2341 if (nphy->hang_avoid)
2342 b43_nphy_stay_in_carrier_search(dev, false);
2343
2344 for (i = 0; i < 2; ++i) {
2345 if (dev->phy.rev >= 3) {
2346 target.ipa[i] = curr_gain[i] & 0x000F;
2347 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2348 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2349 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2350 } else {
2351 target.ipa[i] = curr_gain[i] & 0x0003;
2352 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2353 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2354 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2355 }
2356 }
2357 } else {
2358 int i;
2359 u16 index[2];
2360 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2361 B43_NPHY_TXPCTL_STAT_BIDX) >>
2362 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2363 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2364 B43_NPHY_TXPCTL_STAT_BIDX) >>
2365 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2366
2367 for (i = 0; i < 2; ++i) {
2368 if (dev->phy.rev >= 3) {
2369 enum ieee80211_band band =
2370 b43_current_band(dev->wl);
2371
2372 if ((nphy->ipa2g_on &&
2373 band == IEEE80211_BAND_2GHZ) ||
2374 (nphy->ipa5g_on &&
2375 band == IEEE80211_BAND_5GHZ)) {
2376 table = b43_nphy_get_ipa_gain_table(dev);
2377 } else {
2378 if (band == IEEE80211_BAND_5GHZ) {
2379 if (dev->phy.rev == 3)
2380 table = b43_ntab_tx_gain_rev3_5ghz;
2381 else if (dev->phy.rev == 4)
2382 table = b43_ntab_tx_gain_rev4_5ghz;
2383 else
2384 table = b43_ntab_tx_gain_rev5plus_5ghz;
2385 } else {
2386 table = b43_ntab_tx_gain_rev3plus_2ghz;
2387 }
2388 }
2389
2390 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2391 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2392 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2393 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2394 } else {
2395 table = b43_ntab_tx_gain_rev0_1_2;
2396
2397 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2398 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2399 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2400 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2401 }
2402 }
2403 }
2404
2405 return target;
2406}
2407
e53de674
RM		 2408/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2409static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2410{
2411 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2412
2413 if (dev->phy.rev >= 3) {
2414 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2415 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2416 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2417 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2418 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 2419 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2420 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 2421 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2422 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2423 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2424 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2425 b43_nphy_reset_cca(dev);
2426 } else {
2427 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2428 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2429 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 2430 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2431 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 2432 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2433 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2434 }
2435}
2436
2437/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2438static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2439{
2440 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2441 u16 tmp;
2442
2443 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2444 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2445 if (dev->phy.rev >= 3) {
2446 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2447 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2448
2449 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2450 regs[2] = tmp;
2451 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2452
2453 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2454 regs[3] = tmp;
2455 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2456
2457 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
de9a47f9 2458 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
e53de674 2459
c643a66e 2460 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 2461 regs[5] = tmp;
d41a3552 2462 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 2463
2464 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 2465 regs[6] = tmp;
d41a3552 2466 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 2467 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2468 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2469
67cbc3ed
RM		 2470 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2471 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2472 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 2473
2474 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2475 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2476 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2477 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2478 } else {
2479 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2480 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2481 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2482 regs[2] = tmp;
2483 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 2484 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 2485 regs[3] = tmp;
2486 tmp |= 0x2000;
d41a3552 2487 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 2488 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 2489 regs[4] = tmp;
2490 tmp |= 0x2000;
d41a3552 2491 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 2492 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2493 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2494 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2495 tmp = 0x0180;
2496 else
2497 tmp = 0x0120;
2498 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2499 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2500 }
2501}
2502
bbc6dc12
RM		 2503/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2504static void b43_nphy_save_cal(struct b43_wldev *dev)
2505{
2506 struct b43_phy_n *nphy = dev->phy.n;
2507
2508 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2509 u16 *txcal_radio_regs = NULL;
902db91d 2510 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 2511 u16 *table = NULL;
2512
2513 if (nphy->hang_avoid)
2514 b43_nphy_stay_in_carrier_search(dev, 1);
2515
2516 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2517 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2518 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2519 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2520 table = nphy->cal_cache.txcal_coeffs_2G;
2521 } else {
2522 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2523 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2524 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2525 table = nphy->cal_cache.txcal_coeffs_5G;
2526 }
2527
2528 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2529 /* TODO use some definitions */
2530 if (dev->phy.rev >= 3) {
2531 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2532 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2533 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2534 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2535 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2536 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2537 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2538 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2539 } else {
2540 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2541 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2542 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2543 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2544 }
2545 *iqcal_chanspec = nphy->radio_chanspec;
2546 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2547
2548 if (nphy->hang_avoid)
2549 b43_nphy_stay_in_carrier_search(dev, 0);
2550}
2551
2f258b74
RM		 2552/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2553static void b43_nphy_restore_cal(struct b43_wldev *dev)
2554{
2555 struct b43_phy_n *nphy = dev->phy.n;
2556
2557 u16 coef[4];
2558 u16 *loft = NULL;
2559 u16 *table = NULL;
2560
2561 int i;
2562 u16 *txcal_radio_regs = NULL;
2563 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2564
2565 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
902db91d 2566 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G))
2f258b74
RM		 2567 return;
2568 table = nphy->cal_cache.txcal_coeffs_2G;
2569 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2570 } else {
902db91d 2571 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G))
2f258b74
RM		 2572 return;
2573 table = nphy->cal_cache.txcal_coeffs_5G;
2574 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2575 }
2576
2581b143 2577 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 2578
2579 for (i = 0; i < 4; i++) {
2580 if (dev->phy.rev >= 3)
2581 table[i] = coef[i];
2582 else
2583 coef[i] = 0;
2584 }
2585
2581b143
RM		 2586 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2587 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2588 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 2589
2590 if (dev->phy.rev < 2)
2591 b43_nphy_tx_iq_workaround(dev);
2592
2593 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2594 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2595 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2596 } else {
2597 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2598 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2599 }
2600
2601 /* TODO use some definitions */
2602 if (dev->phy.rev >= 3) {
2603 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2604 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2605 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2606 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2607 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2608 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2609 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2610 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2611 } else {
2612 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2613 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2614 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2615 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2616 }
2617 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2618}
2619
fb43b8e2
RM		 2620/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2621static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2622 struct nphy_txgains target,
2623 bool full, bool mphase)
2624{
2625 struct b43_phy_n *nphy = dev->phy.n;
2626 int i;
2627 int error = 0;
2628 int freq;
2629 bool avoid = false;
2630 u8 length;
2631 u16 tmp, core, type, count, max, numb, last, cmd;
2632 const u16 *table;
2633 bool phy6or5x;
2634
2635 u16 buffer[11];
2636 u16 diq_start = 0;
2637 u16 save[2];
2638 u16 gain[2];
2639 struct nphy_iqcal_params params[2];
2640 bool updated[2] = { };
2641
2642 b43_nphy_stay_in_carrier_search(dev, true);
2643
2644 if (dev->phy.rev >= 4) {
2645 avoid = nphy->hang_avoid;
2646 nphy->hang_avoid = 0;
2647 }
2648
9145834e 2649 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 2650
2651 for (i = 0; i < 2; i++) {
2652 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2653 gain[i] = params[i].cal_gain;
2654 }
2581b143
RM		 2655
2656 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 2657
2658 b43_nphy_tx_cal_radio_setup(dev);
e53de674 2659 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 2660
2661 phy6or5x = dev->phy.rev >= 6 ||
2662 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2663 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2664 if (phy6or5x) {
38bb9029
RM		 2665 if (dev->phy.is_40mhz) {
2666 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2667 tbl_tx_iqlo_cal_loft_ladder_40);
2668 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2669 tbl_tx_iqlo_cal_iqimb_ladder_40);
2670 } else {
2671 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2672 tbl_tx_iqlo_cal_loft_ladder_20);
2673 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2674 tbl_tx_iqlo_cal_iqimb_ladder_20);
2675 }
fb43b8e2
RM		 2676 }
2677
2678 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2679
aa4c7b2a 2680 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 2681 freq = 2500;
2682 else
2683 freq = 5000;
2684
2685 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 2686 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2687 0xFFFF, 0, true, false);
fb43b8e2 2688 else
59af099b 2689 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 2690
2691 if (error == 0) {
2692 if (nphy->mphase_cal_phase_id > 2) {
2693 table = nphy->mphase_txcal_bestcoeffs;
2694 length = 11;
2695 if (dev->phy.rev < 3)
2696 length -= 2;
2697 } else {
2698 if (!full && nphy->txiqlocal_coeffsvalid) {
2699 table = nphy->txiqlocal_bestc;
2700 length = 11;
2701 if (dev->phy.rev < 3)
2702 length -= 2;
2703 } else {
2704 full = true;
2705 if (dev->phy.rev >= 3) {
2706 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2707 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2708 } else {
2709 table = tbl_tx_iqlo_cal_startcoefs;
2710 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2711 }
2712 }
2713 }
2714
2581b143 2715 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 2716
2717 if (full) {
2718 if (dev->phy.rev >= 3)
2719 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2720 else
2721 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2722 } else {
2723 if (dev->phy.rev >= 3)
2724 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2725 else
2726 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2727 }
2728
2729 if (mphase) {
2730 count = nphy->mphase_txcal_cmdidx;
2731 numb = min(max,
2732 (u16)(count + nphy->mphase_txcal_numcmds));
2733 } else {
2734 count = 0;
2735 numb = max;
2736 }
2737
2738 for (; count < numb; count++) {
2739 if (full) {
2740 if (dev->phy.rev >= 3)
2741 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2742 else
2743 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2744 } else {
2745 if (dev->phy.rev >= 3)
2746 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2747 else
2748 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2749 }
2750
2751 core = (cmd & 0x3000) >> 12;
2752 type = (cmd & 0x0F00) >> 8;
2753
2754 if (phy6or5x && updated[core] == 0) {
2755 b43_nphy_update_tx_cal_ladder(dev, core);
2756 updated[core] = 1;
2757 }
2758
2759 tmp = (params[core].ncorr[type] << 8) | 0x66;
2760 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2761
2762 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 2763 buffer[0] = b43_ntab_read(dev,
2764 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 2765 diq_start = buffer[0];
2766 buffer[0] = 0;
d41a3552
RM		 2767 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2768 0);
fb43b8e2
RM		 2769 }
2770
2771 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2772 for (i = 0; i < 2000; i++) {
2773 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2774 if (tmp & 0xC000)
2775 break;
2776 udelay(10);
2777 }
2778
9145834e
RM		 2779 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2780 buffer);
2581b143
RM		 2781 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2782 buffer);
fb43b8e2
RM		 2783
2784 if (type == 1 || type == 3 || type == 4)
2785 buffer[0] = diq_start;
2786 }
2787
2788 if (mphase)
2789 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2790
2791 last = (dev->phy.rev < 3) ? 6 : 7;
2792
2793 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 2794 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 2795 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 2796 if (dev->phy.rev < 3) {
2797 buffer[0] = 0;
2798 buffer[1] = 0;
2799 buffer[2] = 0;
2800 buffer[3] = 0;
2801 }
2581b143
RM		 2802 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2803 buffer);
bc53e512 2804 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 2805 buffer);
2806 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2807 buffer);
2808 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2809 buffer);
fb43b8e2
RM		 2810 length = 11;
2811 if (dev->phy.rev < 3)
2812 length -= 2;
9145834e
RM		 2813 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2814 nphy->txiqlocal_bestc);
fb43b8e2 2815 nphy->txiqlocal_coeffsvalid = true;
902db91d 2816 nphy->txiqlocal_chanspec = nphy->radio_chanspec;
fb43b8e2
RM		 2817 } else {
2818 length = 11;
2819 if (dev->phy.rev < 3)
2820 length -= 2;
9145834e
RM		 2821 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2822 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 2823 }
2824
53ae8e8c 2825 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 2826 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2827 }
2828
e53de674 2829 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 2830 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 2831
2832 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2833 b43_nphy_tx_iq_workaround(dev);
2834
2835 if (dev->phy.rev >= 4)
2836 nphy->hang_avoid = avoid;
2837
2838 b43_nphy_stay_in_carrier_search(dev, false);
2839
2840 return error;
2841}
2842
984ff4ff
RM		 2843/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2844static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2845{
2846 struct b43_phy_n *nphy = dev->phy.n;
2847 u8 i;
2848 u16 buffer[7];
2849 bool equal = true;
2850
902db91d
RM		 2851 if (!nphy->txiqlocal_coeffsvalid ||
2852 b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec))
984ff4ff
RM		 2853 return;
2854
2855 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2856 for (i = 0; i < 4; i++) {
2857 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2858 equal = false;
2859 break;
2860 }
2861 }
2862
2863 if (!equal) {
2864 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2865 nphy->txiqlocal_bestc);
2866 for (i = 0; i < 4; i++)
2867 buffer[i] = 0;
2868 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2869 buffer);
2870 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2871 &nphy->txiqlocal_bestc[5]);
2872 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2873 &nphy->txiqlocal_bestc[5]);
2874 }
2875}
2876
15931e31
RM		 2877/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2878static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2879 struct nphy_txgains target, u8 type, bool debug)
2880{
2881 struct b43_phy_n *nphy = dev->phy.n;
2882 int i, j, index;
2883 u8 rfctl[2];
2884 u8 afectl_core;
2885 u16 tmp[6];
2886 u16 cur_hpf1, cur_hpf2, cur_lna;
2887 u32 real, imag;
2888 enum ieee80211_band band;
2889
2890 u8 use;
2891 u16 cur_hpf;
2892 u16 lna[3] = { 3, 3, 1 };
2893 u16 hpf1[3] = { 7, 2, 0 };
2894 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 2895 u32 power[3] = { };
15931e31
RM		 2896 u16 gain_save[2];
2897 u16 cal_gain[2];
2898 struct nphy_iqcal_params cal_params[2];
2899 struct nphy_iq_est est;
2900 int ret = 0;
2901 bool playtone = true;
2902 int desired = 13;
2903
2904 b43_nphy_stay_in_carrier_search(dev, 1);
2905
2906 if (dev->phy.rev < 2)
984ff4ff 2907 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 2908 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 2909 for (i = 0; i < 2; i++) {
2910 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2911 cal_gain[i] = cal_params[i].cal_gain;
2912 }
2581b143 2913 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 2914
2915 for (i = 0; i < 2; i++) {
2916 if (i == 0) {
2917 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2918 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2919 afectl_core = B43_NPHY_AFECTL_C1;
2920 } else {
2921 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2922 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2923 afectl_core = B43_NPHY_AFECTL_C2;
2924 }
2925
2926 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2927 tmp[2] = b43_phy_read(dev, afectl_core);
2928 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2929 tmp[4] = b43_phy_read(dev, rfctl[0]);
2930 tmp[5] = b43_phy_read(dev, rfctl[1]);
2931
2932 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2933 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2934 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2935 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2936 (1 - i));
2937 b43_phy_set(dev, afectl_core, 0x0006);
2938 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2939
2940 band = b43_current_band(dev->wl);
2941
2942 if (nphy->rxcalparams & 0xFF000000) {
2943 if (band == IEEE80211_BAND_5GHZ)
2944 b43_phy_write(dev, rfctl[0], 0x140);
2945 else
2946 b43_phy_write(dev, rfctl[0], 0x110);
2947 } else {
2948 if (band == IEEE80211_BAND_5GHZ)
2949 b43_phy_write(dev, rfctl[0], 0x180);
2950 else
2951 b43_phy_write(dev, rfctl[0], 0x120);
2952 }
2953
2954 if (band == IEEE80211_BAND_5GHZ)
2955 b43_phy_write(dev, rfctl[1], 0x148);
2956 else
2957 b43_phy_write(dev, rfctl[1], 0x114);
2958
2959 if (nphy->rxcalparams & 0x10000) {
2960 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2961 (i + 1));
2962 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2963 (2 - i));
2964 }
2965
2966 for (j = 0; i < 4; j++) {
2967 if (j < 3) {
2968 cur_lna = lna[j];
2969 cur_hpf1 = hpf1[j];
2970 cur_hpf2 = hpf2[j];
2971 } else {
2972 if (power[1] > 10000) {
2973 use = 1;
2974 cur_hpf = cur_hpf1;
2975 index = 2;
2976 } else {
2977 if (power[0] > 10000) {
2978 use = 1;
2979 cur_hpf = cur_hpf1;
2980 index = 1;
2981 } else {
2982 index = 0;
2983 use = 2;
2984 cur_hpf = cur_hpf2;
2985 }
2986 }
2987 cur_lna = lna[index];
2988 cur_hpf1 = hpf1[index];
2989 cur_hpf2 = hpf2[index];
2990 cur_hpf += desired - hweight32(power[index]);
2991 cur_hpf = clamp_val(cur_hpf, 0, 10);
2992 if (use == 1)
2993 cur_hpf1 = cur_hpf;
2994 else
2995 cur_hpf2 = cur_hpf;
2996 }
2997
2998 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2999 (cur_lna << 2));
75377b24
RM		 3000 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3001 false);
de9a47f9 3002 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3003 b43_nphy_stop_playback(dev);
15931e31
RM		 3004
3005 if (playtone) {
59af099b
RM		 3006 ret = b43_nphy_tx_tone(dev, 4000,
3007 (nphy->rxcalparams & 0xFFFF),
3008 false, false);
15931e31
RM		 3009 playtone = false;
3010 } else {
10a79873
RM		 3011 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3012 false, false);
15931e31
RM		 3013 }
3014
3015 if (ret == 0) {
3016 if (j < 3) {
3017 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3018 false);
3019 if (i == 0) {
3020 real = est.i0_pwr;
3021 imag = est.q0_pwr;
3022 } else {
3023 real = est.i1_pwr;
3024 imag = est.q1_pwr;
3025 }
3026 power[i] = ((real + imag) / 1024) + 1;
3027 } else {
3028 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3029 }
53ae8e8c 3030 b43_nphy_stop_playback(dev);
15931e31
RM		 3031 }
3032
3033 if (ret != 0)
3034 break;
3035 }
3036
3037 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3038 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3039 b43_phy_write(dev, rfctl[1], tmp[5]);
3040 b43_phy_write(dev, rfctl[0], tmp[4]);
3041 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3042 b43_phy_write(dev, afectl_core, tmp[2]);
3043 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3044
3045 if (ret != 0)
3046 break;
3047 }
3048
75377b24 3049 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3050 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3051 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3052
3053 b43_nphy_stay_in_carrier_search(dev, 0);
3054
3055 return ret;
3056}
3057
3058static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3059 struct nphy_txgains target, u8 type, bool debug)
3060{
3061 return -1;
3062}
3063
3064/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3065static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3066 struct nphy_txgains target, u8 type, bool debug)
3067{
3068 if (dev->phy.rev >= 3)
3069 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3070 else
3071 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3072}
3073
0988a7a1
RM		 3074/*
3075 * Init N-PHY
3076 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3077 */
424047e6
MB		 3078int b43_phy_initn(struct b43_wldev *dev)
3079{
0988a7a1 3080 struct ssb_bus *bus = dev->dev->bus;
95b66bad 3081 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3082 struct b43_phy_n *nphy = phy->n;
3083 u8 tx_pwr_state;
3084 struct nphy_txgains target;
95b66bad 3085 u16 tmp;
0988a7a1
RM		 3086 enum ieee80211_band tmp2;
3087 bool do_rssi_cal;
3088
3089 u16 clip[2];
3090 bool do_cal = false;
95b66bad 3091
0988a7a1
RM		 3092 if ((dev->phy.rev >= 3) &&
3093 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3094 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3095 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3096 }
3097 nphy->deaf_count = 0;
95b66bad 3098 b43_nphy_tables_init(dev);
0988a7a1
RM		 3099 nphy->crsminpwr_adjusted = false;
3100 nphy->noisevars_adjusted = false;
95b66bad
MB		 3101
3102 /* Clear all overrides */
0988a7a1
RM		 3103 if (dev->phy.rev >= 3) {
3104 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3105 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3106 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3107 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3108 } else {
3109 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3110 }
95b66bad
MB		 3111 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3112 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3113 if (dev->phy.rev < 6) {
3114 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3115 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3116 }
95b66bad
MB		 3117 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3118 ~(B43_NPHY_RFSEQMODE_CAOVER |
3119 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3120 if (dev->phy.rev >= 3)
3121 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3122 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3123
0988a7a1
RM		 3124 if (dev->phy.rev <= 2) {
3125 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3126 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3127 ~B43_NPHY_BPHY_CTL3_SCALE,
3128 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3129 }
95b66bad
MB		 3130 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3131 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3132
0988a7a1
RM		 3133 if (bus->sprom.boardflags2_lo & 0x100 ||
3134 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3135 bus->boardinfo.type == 0x8B))
3136 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3137 else
3138 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3139 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3140 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3141 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3142
ad9716e8 3143 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3144 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3145
3146 if (phy->rev < 2) {
3147 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3148 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3149 }
0988a7a1
RM		 3150
3151 tmp2 = b43_current_band(dev->wl);
3152 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3153 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3154 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3155 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3156 nphy->papd_epsilon_offset[0] << 7);
3157 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3158 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3159 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3160 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3161 } else if (phy->rev >= 5) {
45ca697e 3162 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3163 }
3164
95b66bad 3165 b43_nphy_workarounds(dev);
95b66bad 3166
0988a7a1 3167 /* Reset CCA, in init code it differs a little from standard way */
730dd705 3168 b43_nphy_bmac_clock_fgc(dev, 1);
0988a7a1
RM		 3169 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3170 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3171 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
730dd705 3172 b43_nphy_bmac_clock_fgc(dev, 0);
0988a7a1
RM		 3173
3174 /* TODO N PHY MAC PHY Clock Set with argument 1 */
3175
e50cbcf6 3176 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3177 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3178 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3179 b43_nphy_pa_override(dev, true);
0988a7a1 3180
bbec398c
RM		 3181 b43_nphy_classifier(dev, 0, 0);
3182 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 3183 tx_pwr_state = nphy->txpwrctrl;
3184 /* TODO N PHY TX power control with argument 0
3185 (turning off power control) */
3186 /* TODO Fix the TX Power Settings */
3187 /* TODO N PHY TX Power Control Idle TSSI */
3188 /* TODO N PHY TX Power Control Setup */
3189
3190 if (phy->rev >= 3) {
3191 /* TODO */
3192 } else {
2581b143
RM		 3193 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3194 b43_ntab_tx_gain_rev0_1_2);
3195 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3196 b43_ntab_tx_gain_rev0_1_2);
0988a7a1 3197 }
95b66bad 3198
0988a7a1
RM		 3199 if (nphy->phyrxchain != 3)
3200 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3201 if (nphy->mphase_cal_phase_id > 0)
3202 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3203
3204 do_rssi_cal = false;
3205 if (phy->rev >= 3) {
3206 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
902db91d
RM		 3207 do_rssi_cal =
3208 b43_empty_chanspec(&nphy->rssical_chanspec_2G);
0988a7a1 3209 else
902db91d
RM		 3210 do_rssi_cal =
3211 b43_empty_chanspec(&nphy->rssical_chanspec_5G);
0988a7a1
RM		 3212
3213 if (do_rssi_cal)
4cb99775 3214 b43_nphy_rssi_cal(dev);
0988a7a1 3215 else
42e1547e 3216 b43_nphy_restore_rssi_cal(dev);
0988a7a1 3217 } else {
4cb99775 3218 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3219 }
3220
3221 if (!((nphy->measure_hold & 0x6) != 0)) {
3222 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
902db91d 3223 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G);
0988a7a1 3224 else
902db91d 3225 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G);
0988a7a1
RM		 3226
3227 if (nphy->mute)
3228 do_cal = false;
3229
3230 if (do_cal) {
b0022e15 3231 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 3232
3233 if (nphy->antsel_type == 2)
8987a9e9 3234 b43_nphy_superswitch_init(dev, true);
0988a7a1 3235 if (nphy->perical != 2) {
90b9738d 3236 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3237 if (phy->rev >= 3) {
3238 nphy->cal_orig_pwr_idx[0] =
3239 nphy->txpwrindex[0].index_internal;
3240 nphy->cal_orig_pwr_idx[1] =
3241 nphy->txpwrindex[1].index_internal;
3242 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 3243 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 3244 }
3245 }
3246 }
3247 }
3248
0988a7a1
RM		 3249 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3250 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
bbc6dc12 3251 b43_nphy_save_cal(dev);
0988a7a1 3252 else if (nphy->mphase_cal_phase_id == 0)
15931e31 3253 ;/* N PHY Periodic Calibration with argument 3 */
0988a7a1
RM		 3254 } else {
3255 b43_nphy_restore_cal(dev);
3256 }
0988a7a1 3257
6dcd9d91 3258 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
0988a7a1
RM		 3259 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3260 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3261 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3262 if (phy->rev >= 3 && phy->rev <= 6)
3263 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 3264 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 3265 if (phy->rev >= 3)
3266 b43_nphy_spur_workaround(dev);
95b66bad
MB		 3267
3268 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 3269 return 0;
424047e6 3270}
ef1a628d 3271
1b69ec7b
RM		 3272/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3273static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
b15b3039 3274 const struct b43_phy_n_sfo_cfg *e,
1b69ec7b
RM		 3275 struct b43_chanspec chanspec)
3276{
3277 struct b43_phy *phy = &dev->phy;
3278 struct b43_phy_n *nphy = dev->phy.n;
3279
3280 u16 tmp;
3281 u32 tmp32;
3282
3283 tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3284 if (chanspec.b_freq == 1 && tmp == 0) {
3285 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3286 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3287 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3288 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3289 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3290 } else if (chanspec.b_freq == 1) {
3291 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3292 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3293 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3294 b43_phy_mask(dev, B43_PHY_B_BBCFG, (u16)~0xC000);
3295 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3296 }
3297
3298 b43_chantab_phy_upload(dev, e);
3299
3300 tmp = chanspec.channel;
3301 if (chanspec.b_freq == 1)
3302 tmp |= 0x0100;
3303 if (chanspec.b_width == 3)
3304 tmp |= 0x0200;
3305 b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
3306
3307 if (nphy->radio_chanspec.channel == 14) {
3308 b43_nphy_classifier(dev, 2, 0);
3309 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3310 } else {
3311 b43_nphy_classifier(dev, 2, 2);
3312 if (chanspec.b_freq == 2)
3313 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3314 }
3315
3316 if (nphy->txpwrctrl)
3317 b43_nphy_tx_power_fix(dev);
3318
3319 if (dev->phy.rev < 3)
3320 b43_nphy_adjust_lna_gain_table(dev);
3321
3322 b43_nphy_tx_lp_fbw(dev);
3323
3324 if (dev->phy.rev >= 3 && 0) {
3325 /* TODO */
3326 }
3327
3328 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3329
3330 if (phy->rev >= 3)
3331 b43_nphy_spur_workaround(dev);
3332}
3333
eff66c51
RM		 3334/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3335static int b43_nphy_set_chanspec(struct b43_wldev *dev,
3336 struct b43_chanspec chanspec)
3337{
3338 struct b43_phy_n *nphy = dev->phy.n;
3339
f19ebe7d
RM		 3340 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3341 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
eff66c51
RM		 3342
3343 u8 tmp;
3344 u8 channel = chanspec.channel;
3345
3346 if (dev->phy.rev >= 3) {
3347 /* TODO */
f19ebe7d
RM		 3348 tabent_r3 = NULL;
3349 if (!tabent_r3)
3350 return -ESRCH;
ffd2d9bd 3351 } else {
f19ebe7d
RM		 3352 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, channel);
3353 if (!tabent_r2)
ffd2d9bd 3354 return -ESRCH;
eff66c51
RM		 3355 }
3356
3357 nphy->radio_chanspec = chanspec;
3358
3359 if (chanspec.b_width != nphy->b_width)
3360 ; /* TODO: BMAC BW Set (chanspec.b_width) */
3361
3362 /* TODO: use defines */
3363 if (chanspec.b_width == 3) {
3364 if (chanspec.sideband == 2)
3365 b43_phy_set(dev, B43_NPHY_RXCTL,
3366 B43_NPHY_RXCTL_BSELU20);
3367 else
3368 b43_phy_mask(dev, B43_NPHY_RXCTL,
3369 ~B43_NPHY_RXCTL_BSELU20);
3370 }
3371
3372 if (dev->phy.rev >= 3) {
3373 tmp = (chanspec.b_freq == 1) ? 4 : 0;
3374 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
f19ebe7d
RM		 3375 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3376 b43_nphy_chanspec_setup(dev, &(tabent_r3->phy_regs), chanspec);
eff66c51 3377 } else {
eff66c51
RM		 3378 tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050;
3379 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d
RM		 3380 b43_radio_2055_setup(dev, tabent_r2);
3381 b43_nphy_chanspec_setup(dev, &(tabent_r2->phy_regs), chanspec);
eff66c51
RM		 3382 }
3383
3384 return 0;
3385}
3386
3387/* Tune the hardware to a new channel */
3388static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
3389{
3390 struct b43_phy_n *nphy = dev->phy.n;
3391
3392 struct b43_chanspec chanspec;
3393 chanspec = nphy->radio_chanspec;
3394 chanspec.channel = channel;
3395
3396 return b43_nphy_set_chanspec(dev, chanspec);
3397}
3398
ef1a628d
MB		 3399static int b43_nphy_op_allocate(struct b43_wldev *dev)
3400{
3401 struct b43_phy_n *nphy;
3402
3403 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3404 if (!nphy)
3405 return -ENOMEM;
3406 dev->phy.n = nphy;
3407
ef1a628d
MB		 3408 return 0;
3409}
3410
fb11137a 3411static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 3412{
fb11137a
MB		 3413 struct b43_phy *phy = &dev->phy;
3414 struct b43_phy_n *nphy = phy->n;
ef1a628d 3415
fb11137a 3416 memset(nphy, 0, sizeof(*nphy));
ef1a628d 3417
fb11137a 3418 //TODO init struct b43_phy_n
ef1a628d
MB		 3419}
3420
fb11137a 3421static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 3422{
fb11137a
MB		 3423 struct b43_phy *phy = &dev->phy;
3424 struct b43_phy_n *nphy = phy->n;
ef1a628d 3425
ef1a628d 3426 kfree(nphy);
fb11137a
MB		 3427 phy->n = NULL;
3428}
3429
3430static int b43_nphy_op_init(struct b43_wldev *dev)
3431{
3432 return b43_phy_initn(dev);
ef1a628d
MB		 3433}
3434
3435static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3436{
3437#if B43_DEBUG
3438 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3439 /* OFDM registers are onnly available on A/G-PHYs */
3440 b43err(dev->wl, "Invalid OFDM PHY access at "
3441 "0x%04X on N-PHY\n", offset);
3442 dump_stack();
3443 }
3444 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3445 /* Ext-G registers are only available on G-PHYs */
3446 b43err(dev->wl, "Invalid EXT-G PHY access at "
3447 "0x%04X on N-PHY\n", offset);
3448 dump_stack();
3449 }
3450#endif /* B43_DEBUG */
3451}
3452
3453static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3454{
3455 check_phyreg(dev, reg);
3456 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3457 return b43_read16(dev, B43_MMIO_PHY_DATA);
3458}
3459
3460static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3461{
3462 check_phyreg(dev, reg);
3463 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3464 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3465}
3466
3467static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3468{
3469 /* Register 1 is a 32-bit register. */
3470 B43_WARN_ON(reg == 1);
3471 /* N-PHY needs 0x100 for read access */
3472 reg |= 0x100;
3473
3474 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3475 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3476}
3477
3478static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3479{
3480 /* Register 1 is a 32-bit register. */
3481 B43_WARN_ON(reg == 1);
3482
3483 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3484 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3485}
3486
c2b7aefd 3487/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 3488static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 3489 bool blocked)
c2b7aefd 3490{
d817f4e1
RM		 3491 struct b43_phy_n *nphy = dev->phy.n;
3492
c2b7aefd
RM		 3493 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3494 b43err(dev->wl, "MAC not suspended\n");
3495
3496 if (blocked) {
3497 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3498 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3499 if (dev->phy.rev >= 3) {
3500 b43_radio_mask(dev, 0x09, ~0x2);
3501
3502 b43_radio_write(dev, 0x204D, 0);
3503 b43_radio_write(dev, 0x2053, 0);
3504 b43_radio_write(dev, 0x2058, 0);
3505 b43_radio_write(dev, 0x205E, 0);
3506 b43_radio_mask(dev, 0x2062, ~0xF0);
3507 b43_radio_write(dev, 0x2064, 0);
3508
3509 b43_radio_write(dev, 0x304D, 0);
3510 b43_radio_write(dev, 0x3053, 0);
3511 b43_radio_write(dev, 0x3058, 0);
3512 b43_radio_write(dev, 0x305E, 0);
3513 b43_radio_mask(dev, 0x3062, ~0xF0);
3514 b43_radio_write(dev, 0x3064, 0);
3515 }
3516 } else {
3517 if (dev->phy.rev >= 3) {
d817f4e1
RM		 3518 b43_radio_init2056(dev);
3519 b43_nphy_set_chanspec(dev, nphy->radio_chanspec);
c2b7aefd
RM		 3520 } else {
3521 b43_radio_init2055(dev);
3522 }
3523 }
ef1a628d
MB		 3524}
3525
cb24f57f
MB		 3526static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3527{
3528 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3529 on ? 0 : 0x7FFF);
3530}
3531
ef1a628d
MB		 3532static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3533 unsigned int new_channel)
3534{
3535 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3536 if ((new_channel < 1) || (new_channel > 14))
3537 return -EINVAL;
3538 } else {
3539 if (new_channel > 200)
3540 return -EINVAL;
3541 }
3542
3543 return nphy_channel_switch(dev, new_channel);
3544}
3545
3546static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3547{
3548 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3549 return 1;
3550 return 36;
3551}
3552
ef1a628d
MB		 3553const struct b43_phy_operations b43_phyops_n = {
3554 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 3555 .free = b43_nphy_op_free,
3556 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 3557 .init = b43_nphy_op_init,
ef1a628d
MB		 3558 .phy_read = b43_nphy_op_read,
3559 .phy_write = b43_nphy_op_write,
3560 .radio_read = b43_nphy_op_radio_read,
3561 .radio_write = b43_nphy_op_radio_write,
3562 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 3563 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 3564 .switch_channel = b43_nphy_op_switch_channel,
3565 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 3566 .recalc_txpower = b43_nphy_op_recalc_txpower,
3567 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 3568};
Linux kernel - Deliverables
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