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b43: N-PHY: replace some hacks with nice tables ops
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
bbec398c 35#include "main.h"
424047e6 36
f8187b5b
RM		 37struct nphy_txgains {
38 u16 txgm[2];
39 u16 pga[2];
40 u16 pad[2];
41 u16 ipa[2];
42};
43
44struct nphy_iqcal_params {
45 u16 txgm;
46 u16 pga;
47 u16 pad;
48 u16 ipa;
49 u16 cal_gain;
50 u16 ncorr[5];
51};
52
53struct nphy_iq_est {
54 s32 iq0_prod;
55 u32 i0_pwr;
56 u32 q0_pwr;
57 s32 iq1_prod;
58 u32 i1_pwr;
59 u32 q1_pwr;
60};
424047e6 61
67c0d6e2
RM		 62enum b43_nphy_rf_sequence {
63 B43_RFSEQ_RX2TX,
64 B43_RFSEQ_TX2RX,
65 B43_RFSEQ_RESET2RX,
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
69};
70
76b002bd
RM		 71enum b43_nphy_rssi_type {
72 B43_NPHY_RSSI_X = 0,
73 B43_NPHY_RSSI_Y,
74 B43_NPHY_RSSI_Z,
75 B43_NPHY_RSSI_PWRDET,
76 B43_NPHY_RSSI_TSSI_I,
77 B43_NPHY_RSSI_TSSI_Q,
78 B43_NPHY_RSSI_TBD,
79};
80
161d540c
RM		 81static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
82 bool enable);
9501fefe
RM		 83static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
84 u8 *events, u8 *delays, u8 length);
67c0d6e2
RM		 85static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
86 enum b43_nphy_rf_sequence seq);
67cbc3ed
RM		 87static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
88 u16 value, u8 core, bool off);
89static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
90 u16 value, u8 core);
67c0d6e2 91
c002831a
RM		 92static inline bool b43_nphy_ipa(struct b43_wldev *dev)
93{
94 enum ieee80211_band band = b43_current_band(dev->wl);
95 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
96 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
97}
98
53a6e234
MB		 99void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
100{//TODO
101}
102
18c8adeb 103static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 104{//TODO
105}
106
18c8adeb
MB		 107static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
108 bool ignore_tssi)
109{//TODO
110 return B43_TXPWR_RES_DONE;
111}
112
d1591314 113static void b43_chantab_radio_upload(struct b43_wldev *dev,
f19ebe7d 114 const struct b43_nphy_channeltab_entry_rev2 *e)
d1591314 115{
e5255ccc
RM		 116 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
117 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
118 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
119 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
120 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
121
122 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
123 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
124 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
125 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
126 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
127
128 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
129 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
130 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
131 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
132 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
133
134 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
135 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
136 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
137 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
138 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
139
140 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
141 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
142 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
143 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
144 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
145
146 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
147 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
d1591314
MB		 148}
149
d4814e69
RM		 150static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
151 const struct b43_nphy_channeltab_entry_rev3 *e)
152{
153 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
154 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
155 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
156 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
157 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
158 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
159 e->radio_syn_pll_loopfilter1);
160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
161 e->radio_syn_pll_loopfilter2);
162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
163 e->radio_syn_pll_loopfilter3);
164 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
165 e->radio_syn_pll_loopfilter4);
166 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
167 e->radio_syn_pll_loopfilter5);
168 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
169 e->radio_syn_reserved_addr27);
170 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
171 e->radio_syn_reserved_addr28);
172 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
173 e->radio_syn_reserved_addr29);
174 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
175 e->radio_syn_logen_vcobuf1);
176 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
177 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
178 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
179
180 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
181 e->radio_rx0_lnaa_tune);
182 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
183 e->radio_rx0_lnag_tune);
184
185 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
186 e->radio_tx0_intpaa_boost_tune);
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
188 e->radio_tx0_intpag_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
190 e->radio_tx0_pada_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
192 e->radio_tx0_padg_boost_tune);
193 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
194 e->radio_tx0_pgaa_boost_tune);
195 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
196 e->radio_tx0_pgag_boost_tune);
197 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
198 e->radio_tx0_mixa_boost_tune);
199 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
200 e->radio_tx0_mixg_boost_tune);
201
202 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
203 e->radio_rx1_lnaa_tune);
204 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
205 e->radio_rx1_lnag_tune);
206
207 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
208 e->radio_tx1_intpaa_boost_tune);
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
210 e->radio_tx1_intpag_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
212 e->radio_tx1_pada_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
214 e->radio_tx1_padg_boost_tune);
215 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
216 e->radio_tx1_pgaa_boost_tune);
217 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
218 e->radio_tx1_pgag_boost_tune);
219 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
220 e->radio_tx1_mixa_boost_tune);
221 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
222 e->radio_tx1_mixg_boost_tune);
223}
224
225/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
226static void b43_radio_2056_setup(struct b43_wldev *dev,
227 const struct b43_nphy_channeltab_entry_rev3 *e)
228{
229 B43_WARN_ON(dev->phy.rev < 3);
230
231 b43_chantab_radio_2056_upload(dev, e);
232 /* TODO */
233 udelay(50);
234 /* VCO calibration */
235 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
236 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
237 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
238 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
239 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
240 udelay(300);
241}
242
d1591314 243static void b43_chantab_phy_upload(struct b43_wldev *dev,
b15b3039 244 const struct b43_phy_n_sfo_cfg *e)
d1591314
MB		 245{
246 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
247 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
248 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
249 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
250 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
251 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
252}
253
161d540c
RM		 254/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
255static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
256{
257 struct b43_phy_n *nphy = dev->phy.n;
258 u8 i;
c9c0d9ec
RM		 259 u16 bmask, val, tmp;
260 enum ieee80211_band band = b43_current_band(dev->wl);
161d540c
RM		 261
262 if (nphy->hang_avoid)
263 b43_nphy_stay_in_carrier_search(dev, 1);
264
265 nphy->txpwrctrl = enable;
266 if (!enable) {
c9c0d9ec
RM		 267 if (dev->phy.rev >= 3 &&
268 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
269 (B43_NPHY_TXPCTL_CMD_COEFF |
270 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
271 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
272 /* We disable enabled TX pwr ctl, save it's state */
273 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
274 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
275 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
276 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
277 }
161d540c
RM		 278
279 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
280 for (i = 0; i < 84; i++)
281 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
282
283 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
284 for (i = 0; i < 84; i++)
285 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
286
287 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
288 if (dev->phy.rev >= 3)
289 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
290 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
291
292 if (dev->phy.rev >= 3) {
293 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
294 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
295 } else {
296 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
297 }
298
299 if (dev->phy.rev == 2)
300 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
301 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
302 else if (dev->phy.rev < 2)
303 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
304 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
305
c9c0d9ec
RM		 306 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
307 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 308 } else {
c9c0d9ec
RM		 309 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
310 nphy->adj_pwr_tbl);
311 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
312 nphy->adj_pwr_tbl);
313
314 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
315 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
316 /* wl does useless check for "enable" param here */
317 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
318 if (dev->phy.rev >= 3) {
319 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
320 if (val)
321 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
322 }
323 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
324
325 if (band == IEEE80211_BAND_5GHZ) {
326 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
327 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
328 if (dev->phy.rev > 1)
329 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
330 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
331 0x64);
332 }
333
334 if (dev->phy.rev >= 3) {
335 if (nphy->tx_pwr_idx[0] != 128 &&
336 nphy->tx_pwr_idx[1] != 128) {
337 /* Recover TX pwr ctl state */
338 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
339 ~B43_NPHY_TXPCTL_CMD_INIT,
340 nphy->tx_pwr_idx[0]);
341 if (dev->phy.rev > 1)
342 b43_phy_maskset(dev,
343 B43_NPHY_TXPCTL_INIT,
344 ~0xff, nphy->tx_pwr_idx[1]);
345 }
346 }
347
348 if (dev->phy.rev >= 3) {
349 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
350 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
351 } else {
352 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
353 }
354
355 if (dev->phy.rev == 2)
356 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
357 else if (dev->phy.rev < 2)
358 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
359
360 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
361 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
362
c002831a 363 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 364 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
365 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
366 }
161d540c
RM		 367 }
368
369 if (nphy->hang_avoid)
370 b43_nphy_stay_in_carrier_search(dev, 0);
371}
372
373/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314
MB		 374static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
375{
161d540c 376 struct b43_phy_n *nphy = dev->phy.n;
0581483a 377 struct ssb_sprom *sprom = dev->dev->bus_sprom;
161d540c
RM		 378
379 u8 txpi[2], bbmult, i;
380 u16 tmp, radio_gain, dac_gain;
381 u16 freq = dev->phy.channel_freq;
382 u32 txgain;
383 /* u32 gaintbl; rev3+ */
384
385 if (nphy->hang_avoid)
386 b43_nphy_stay_in_carrier_search(dev, 1);
387
388 if (dev->phy.rev >= 3) {
389 txpi[0] = 40;
390 txpi[1] = 40;
391 } else if (sprom->revision < 4) {
392 txpi[0] = 72;
393 txpi[1] = 72;
394 } else {
395 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
396 txpi[0] = sprom->txpid2g[0];
397 txpi[1] = sprom->txpid2g[1];
398 } else if (freq >= 4900 && freq < 5100) {
399 txpi[0] = sprom->txpid5gl[0];
400 txpi[1] = sprom->txpid5gl[1];
401 } else if (freq >= 5100 && freq < 5500) {
402 txpi[0] = sprom->txpid5g[0];
403 txpi[1] = sprom->txpid5g[1];
404 } else if (freq >= 5500) {
405 txpi[0] = sprom->txpid5gh[0];
406 txpi[1] = sprom->txpid5gh[1];
407 } else {
408 txpi[0] = 91;
409 txpi[1] = 91;
410 }
411 }
412
413 /*
414 for (i = 0; i < 2; i++) {
415 nphy->txpwrindex[i].index_internal = txpi[i];
416 nphy->txpwrindex[i].index_internal_save = txpi[i];
417 }
418 */
419
420 for (i = 0; i < 2; i++) {
421 if (dev->phy.rev >= 3) {
c7455cf9
RM		 422 /* FIXME: support 5GHz */
423 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
161d540c
RM		 424 radio_gain = (txgain >> 16) & 0x1FFFF;
425 } else {
426 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
427 radio_gain = (txgain >> 16) & 0x1FFF;
428 }
429
430 dac_gain = (txgain >> 8) & 0x3F;
431 bbmult = txgain & 0xFF;
432
433 if (dev->phy.rev >= 3) {
434 if (i == 0)
435 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
436 else
437 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
438 } else {
439 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
440 }
441
442 if (i == 0)
443 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
444 else
445 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
446
44f4008b 447 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
161d540c 448
44f4008b 449 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 450 if (i == 0)
451 tmp = (tmp & 0x00FF) | (bbmult << 8);
452 else
453 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 454 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c
RM		 455
456 if (0)
457 ; /* TODO */
458 }
459
460 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
461
462 if (nphy->hang_avoid)
463 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 464}
465
7955de0c
RM		 466
467/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
468static void b43_radio_2055_setup(struct b43_wldev *dev,
f19ebe7d 469 const struct b43_nphy_channeltab_entry_rev2 *e)
7955de0c
RM		 470{
471 B43_WARN_ON(dev->phy.rev >= 3);
472
473 b43_chantab_radio_upload(dev, e);
474 udelay(50);
e58b1253
RM		 475 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
476 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
7955de0c 477 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e58b1253 478 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
7955de0c
RM		 479 udelay(300);
480}
481
53a6e234
MB		 482static void b43_radio_init2055_pre(struct b43_wldev *dev)
483{
484 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
485 ~B43_NPHY_RFCTL_CMD_PORFORCE);
486 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
487 B43_NPHY_RFCTL_CMD_CHIP0PU |
488 B43_NPHY_RFCTL_CMD_OEPORFORCE);
489 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
490 B43_NPHY_RFCTL_CMD_PORFORCE);
491}
492
493static void b43_radio_init2055_post(struct b43_wldev *dev)
494{
036cafe4 495 struct b43_phy_n *nphy = dev->phy.n;
0581483a 496 struct ssb_sprom *sprom = dev->dev->bus_sprom;
53a6e234
MB		 497 int i;
498 u16 val;
036cafe4
RM		 499 bool workaround = false;
500
501 if (sprom->revision < 4)
79d2232f
RM		 502 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
503 && dev->dev->board_type == 0x46D
504 && dev->dev->board_rev >= 0x41);
036cafe4 505 else
7a4db8f5
RM		 506 workaround =
507 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
53a6e234
MB		 508
509 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
036cafe4
RM		 510 if (workaround) {
511 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
512 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
53a6e234 513 }
036cafe4
RM		 514 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
515 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
53a6e234 516 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
53a6e234 517 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
53a6e234
MB		 518 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
519 msleep(1);
520 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
036cafe4
RM		 521 for (i = 0; i < 200; i++) {
522 val = b43_radio_read(dev, B2055_CAL_COUT2);
523 if (val & 0x80) {
524 i = 0;
53a6e234 525 break;
036cafe4 526 }
53a6e234
MB		 527 udelay(10);
528 }
036cafe4
RM		 529 if (i)
530 b43err(dev->wl, "radio post init timeout\n");
53a6e234 531 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
78159788 532 b43_switch_channel(dev, dev->phy.channel);
036cafe4
RM		 533 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
534 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
535 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
536 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
537 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
538 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
539 if (!nphy->gain_boost) {
540 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
541 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
542 } else {
543 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
544 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
545 }
546 udelay(2);
53a6e234
MB		 547}
548
c2b7aefd
RM		 549/*
550 * Initialize a Broadcom 2055 N-radio
551 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
552 */
53a6e234
MB		 553static void b43_radio_init2055(struct b43_wldev *dev)
554{
555 b43_radio_init2055_pre(dev);
a2d9bc6f
RM		 556 if (b43_status(dev) < B43_STAT_INITIALIZED) {
557 /* Follow wl, not specs. Do not force uploading all regs */
558 b2055_upload_inittab(dev, 0, 0);
559 } else {
560 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
561 b2055_upload_inittab(dev, ghz5, 0);
562 }
53a6e234
MB		 563 b43_radio_init2055_post(dev);
564}
565
ea7ee14b
RM		 566static void b43_radio_init2056_pre(struct b43_wldev *dev)
567{
568 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
569 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
570 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
571 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
572 B43_NPHY_RFCTL_CMD_OEPORFORCE);
573 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
574 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
575 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
576 B43_NPHY_RFCTL_CMD_CHIP0PU);
577}
578
579static void b43_radio_init2056_post(struct b43_wldev *dev)
580{
581 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
582 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
583 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
584 msleep(1);
585 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
586 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
587 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
588 /*
589 if (nphy->init_por)
590 Call Radio 2056 Recalibrate
591 */
592}
593
d817f4e1
RM		 594/*
595 * Initialize a Broadcom 2056 N-radio
596 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
597 */
598static void b43_radio_init2056(struct b43_wldev *dev)
599{
ea7ee14b
RM		 600 b43_radio_init2056_pre(dev);
601 b2056_upload_inittabs(dev, 0, 0);
602 b43_radio_init2056_post(dev);
d817f4e1
RM		 603}
604
4772ae10
RM		 605/*
606 * Upload the N-PHY tables.
607 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
608 */
95b66bad
MB		 609static void b43_nphy_tables_init(struct b43_wldev *dev)
610{
4772ae10
RM		 611 if (dev->phy.rev < 3)
612 b43_nphy_rev0_1_2_tables_init(dev);
613 else
614 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 615}
616
e50cbcf6
RM		 617/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
618static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
619{
620 struct b43_phy_n *nphy = dev->phy.n;
621 enum ieee80211_band band;
622 u16 tmp;
623
624 if (!enable) {
625 nphy->rfctrl_intc1_save = b43_phy_read(dev,
626 B43_NPHY_RFCTL_INTC1);
627 nphy->rfctrl_intc2_save = b43_phy_read(dev,
628 B43_NPHY_RFCTL_INTC2);
629 band = b43_current_band(dev->wl);
630 if (dev->phy.rev >= 3) {
631 if (band == IEEE80211_BAND_5GHZ)
632 tmp = 0x600;
633 else
634 tmp = 0x480;
635 } else {
636 if (band == IEEE80211_BAND_5GHZ)
637 tmp = 0x180;
638 else
639 tmp = 0x120;
640 }
641 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
642 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
643 } else {
644 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
645 nphy->rfctrl_intc1_save);
646 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
647 nphy->rfctrl_intc2_save);
648 }
649}
650
fe3e46e8
RM		 651/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
652static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
653{
fe3e46e8 654 u16 tmp;
fe3e46e8
RM		 655
656 if (dev->phy.rev >= 3) {
c002831a 657 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 658 tmp = 4;
659 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
660 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
661 }
662
663 tmp = 1;
664 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
665 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
666 }
667}
668
4a933c85 669/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 670static void b43_nphy_reset_cca(struct b43_wldev *dev)
671{
672 u16 bbcfg;
673
f6a3e99d 674 b43_phy_force_clock(dev, 1);
95b66bad 675 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 676 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
677 udelay(1);
678 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 679 b43_phy_force_clock(dev, 0);
67c0d6e2 680 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 681}
682
ad9716e8
RM		 683/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
684static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
685{
686 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
687
688 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
689 if (preamble == 1)
690 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
691 else
692 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
693
694 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
695}
696
4f4ab6cd
RM		 697/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
698static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
699{
700 struct b43_phy_n *nphy = dev->phy.n;
701
702 bool override = false;
703 u16 chain = 0x33;
704
705 if (nphy->txrx_chain == 0) {
706 chain = 0x11;
707 override = true;
708 } else if (nphy->txrx_chain == 1) {
709 chain = 0x22;
710 override = true;
711 }
712
713 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
714 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
715 chain);
716
717 if (override)
718 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
719 B43_NPHY_RFSEQMODE_CAOVER);
720 else
721 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
722 ~B43_NPHY_RFSEQMODE_CAOVER);
723}
724
2faa6b83
RM		 725/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
726static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
727 u16 samps, u8 time, bool wait)
728{
729 int i;
730 u16 tmp;
731
732 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
733 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
734 if (wait)
735 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
736 else
737 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
738
739 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
740
741 for (i = 1000; i; i--) {
742 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
743 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
744 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
745 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
746 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
747 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
748 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
749 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
750
751 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
752 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
753 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
754 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
755 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
756 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
757 return;
758 }
759 udelay(10);
760 }
761 memset(est, 0, sizeof(*est));
762}
763
a67162ab
RM		 764/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
765static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
766 struct b43_phy_n_iq_comp *pcomp)
767{
768 if (write) {
769 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
770 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
771 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
772 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
773 } else {
774 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
775 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
776 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
777 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
778 }
779}
780
c7455cf9
RM		 781#if 0
782/* Ready but not used anywhere */
026816fc
RM		 783/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
784static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
785{
786 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
787
788 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
789 if (core == 0) {
790 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
791 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
792 } else {
793 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
794 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
795 }
796 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
797 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
798 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
799 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
800 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
801 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
802 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
803 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
804}
805
806/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
807static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
808{
809 u8 rxval, txval;
810 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
811
812 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
813 if (core == 0) {
814 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
815 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
816 } else {
817 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
818 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
819 }
820 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
821 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
822 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
823 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
824 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
825 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
826 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
827 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
828
829 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
830 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
831
acd82aa8
LF		 832 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
833 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 834 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
835 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
836 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
837 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
838 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
839 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
840 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
841
842 if (core == 0) {
843 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
844 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
845 } else {
846 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
847 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
848 }
849
67cbc3ed
RM		 850 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
851 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 852 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 853
854 if (core == 0) {
855 rxval = 1;
856 txval = 8;
857 } else {
858 rxval = 4;
859 txval = 2;
860 }
67cbc3ed
RM		 861 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
862 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc 863}
c7455cf9 864#endif
026816fc 865
34a56f2c
RM		 866/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
867static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
868{
869 int i;
870 s32 iq;
871 u32 ii;
872 u32 qq;
873 int iq_nbits, qq_nbits;
874 int arsh, brsh;
875 u16 tmp, a, b;
876
877 struct nphy_iq_est est;
878 struct b43_phy_n_iq_comp old;
879 struct b43_phy_n_iq_comp new = { };
880 bool error = false;
881
882 if (mask == 0)
883 return;
884
885 b43_nphy_rx_iq_coeffs(dev, false, &old);
886 b43_nphy_rx_iq_coeffs(dev, true, &new);
887 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
888 new = old;
889
890 for (i = 0; i < 2; i++) {
891 if (i == 0 && (mask & 1)) {
892 iq = est.iq0_prod;
893 ii = est.i0_pwr;
894 qq = est.q0_pwr;
895 } else if (i == 1 && (mask & 2)) {
896 iq = est.iq1_prod;
897 ii = est.i1_pwr;
898 qq = est.q1_pwr;
899 } else {
34a56f2c
RM		 900 continue;
901 }
902
903 if (ii + qq < 2) {
904 error = true;
905 break;
906 }
907
908 iq_nbits = fls(abs(iq));
909 qq_nbits = fls(qq);
910
911 arsh = iq_nbits - 20;
912 if (arsh >= 0) {
913 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
914 tmp = ii >> arsh;
915 } else {
916 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
917 tmp = ii << -arsh;
918 }
919 if (tmp == 0) {
920 error = true;
921 break;
922 }
923 a /= tmp;
924
925 brsh = qq_nbits - 11;
926 if (brsh >= 0) {
927 b = (qq << (31 - qq_nbits));
928 tmp = ii >> brsh;
929 } else {
930 b = (qq << (31 - qq_nbits));
931 tmp = ii << -brsh;
932 }
933 if (tmp == 0) {
934 error = true;
935 break;
936 }
937 b = int_sqrt(b / tmp - a * a) - (1 << 10);
938
939 if (i == 0 && (mask & 0x1)) {
940 if (dev->phy.rev >= 3) {
941 new.a0 = a & 0x3FF;
942 new.b0 = b & 0x3FF;
943 } else {
944 new.a0 = b & 0x3FF;
945 new.b0 = a & 0x3FF;
946 }
947 } else if (i == 1 && (mask & 0x2)) {
948 if (dev->phy.rev >= 3) {
949 new.a1 = a & 0x3FF;
950 new.b1 = b & 0x3FF;
951 } else {
952 new.a1 = b & 0x3FF;
953 new.b1 = a & 0x3FF;
954 }
955 }
956 }
957
958 if (error)
959 new = old;
960
961 b43_nphy_rx_iq_coeffs(dev, true, &new);
962}
963
09146400
RM		 964/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
965static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
966{
967 u16 array[4];
44f4008b 968 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 969
970 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
971 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
972 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
973 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
974}
975
bbec398c 976/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
20407ed8
JP		 977static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
978 const u16 *clip_st)
bbec398c
RM		 979{
980 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
981 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
982}
983
984/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
985static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
986{
987 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
988 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
989}
990
8987a9e9
RM		 991/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
992static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
993{
994 if (dev->phy.rev >= 3) {
995 if (!init)
996 return;
997 if (0 /* FIXME */) {
998 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
999 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1000 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1001 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1002 }
1003 } else {
1004 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1005 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1006
6cbab0d9 1007 switch (dev->dev->bus_type) {
42c9a458
RM		 1008#ifdef CONFIG_B43_BCMA
1009 case B43_BUS_BCMA:
1010 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1011 0xFC00, 0xFC00);
1012 break;
1013#endif
6cbab0d9
RM		 1014#ifdef CONFIG_B43_SSB
1015 case B43_BUS_SSB:
1016 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1017 0xFC00, 0xFC00);
1018 break;
1019#endif
1020 }
1021
8987a9e9
RM		 1022 b43_write32(dev, B43_MMIO_MACCTL,
1023 b43_read32(dev, B43_MMIO_MACCTL) &
1024 ~B43_MACCTL_GPOUTSMSK);
1025 b43_write16(dev, B43_MMIO_GPIO_MASK,
1026 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1027 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1028 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1029
1030 if (init) {
1031 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1032 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1033 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1034 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1035 }
1036 }
1037}
1038
bbec398c
RM		 1039/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1040static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1041{
1042 u16 tmp;
1043
21d889d4 1044 if (dev->dev->core_rev == 16)
bbec398c
RM		 1045 b43_mac_suspend(dev);
1046
1047 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1048 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1049 B43_NPHY_CLASSCTL_WAITEDEN);
1050 tmp &= ~mask;
1051 tmp |= (val & mask);
1052 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1053
21d889d4 1054 if (dev->dev->core_rev == 16)
bbec398c
RM		 1055 b43_mac_enable(dev);
1056
1057 return tmp;
1058}
1059
5c1a140a
RM		 1060/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1061static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1062{
1063 struct b43_phy *phy = &dev->phy;
1064 struct b43_phy_n *nphy = phy->n;
1065
1066 if (enable) {
20407ed8 1067 static const u16 clip[] = { 0xFFFF, 0xFFFF };
5c1a140a
RM		 1068 if (nphy->deaf_count++ == 0) {
1069 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1070 b43_nphy_classifier(dev, 0x7, 0);
1071 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1072 b43_nphy_write_clip_detection(dev, clip);
1073 }
1074 b43_nphy_reset_cca(dev);
1075 } else {
1076 if (--nphy->deaf_count == 0) {
1077 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1078 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1079 }
1080 }
1081}
1082
53ae8e8c
RM		 1083/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1084static void b43_nphy_stop_playback(struct b43_wldev *dev)
1085{
1086 struct b43_phy_n *nphy = dev->phy.n;
1087 u16 tmp;
1088
1089 if (nphy->hang_avoid)
1090 b43_nphy_stay_in_carrier_search(dev, 1);
1091
1092 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1093 if (tmp & 0x1)
1094 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1095 else if (tmp & 0x2)
acd82aa8 1096 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
53ae8e8c
RM		 1097
1098 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1099
1100 if (nphy->bb_mult_save & 0x80000000) {
1101 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 1102 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 1103 nphy->bb_mult_save = 0;
1104 }
1105
1106 if (nphy->hang_avoid)
1107 b43_nphy_stay_in_carrier_search(dev, 0);
1108}
1109
9442e5b5
RM		 1110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1111static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1112{
1113 struct b43_phy_n *nphy = dev->phy.n;
1114
204a665b 1115 u8 channel = dev->phy.channel;
9442e5b5
RM		 1116 int tone[2] = { 57, 58 };
1117 u32 noise[2] = { 0x3FF, 0x3FF };
1118
1119 B43_WARN_ON(dev->phy.rev < 3);
1120
1121 if (nphy->hang_avoid)
1122 b43_nphy_stay_in_carrier_search(dev, 1);
1123
9442e5b5
RM		 1124 if (nphy->gband_spurwar_en) {
1125 /* TODO: N PHY Adjust Analog Pfbw (7) */
1126 if (channel == 11 && dev->phy.is_40mhz)
1127 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1128 else
1129 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1130 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1131 }
1132
1133 if (nphy->aband_spurwar_en) {
1134 if (channel == 54) {
1135 tone[0] = 0x20;
1136 noise[0] = 0x25F;
1137 } else if (channel == 38 || channel == 102 || channel == 118) {
1138 if (0 /* FIXME */) {
1139 tone[0] = 0x20;
1140 noise[0] = 0x21F;
1141 } else {
1142 tone[0] = 0;
1143 noise[0] = 0;
1144 }
1145 } else if (channel == 134) {
1146 tone[0] = 0x20;
1147 noise[0] = 0x21F;
1148 } else if (channel == 151) {
1149 tone[0] = 0x10;
1150 noise[0] = 0x23F;
1151 } else if (channel == 153 || channel == 161) {
1152 tone[0] = 0x30;
1153 noise[0] = 0x23F;
1154 } else {
1155 tone[0] = 0;
1156 noise[0] = 0;
1157 }
1158
1159 if (!tone[0] && !noise[0])
1160 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1161 else
1162 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1163 }
1164
1165 if (nphy->hang_avoid)
1166 b43_nphy_stay_in_carrier_search(dev, 0);
1167}
1168
d24019ad
RM		 1169/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1170static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1171{
1172 struct b43_phy_n *nphy = dev->phy.n;
1173
1174 u8 i;
1175 s16 tmp;
1176 u16 data[4];
1177 s16 gain[2];
1178 u16 minmax[2];
20407ed8 1179 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
d24019ad
RM		 1180
1181 if (nphy->hang_avoid)
1182 b43_nphy_stay_in_carrier_search(dev, 1);
1183
1184 if (nphy->gain_boost) {
1185 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1186 gain[0] = 6;
1187 gain[1] = 6;
1188 } else {
204a665b 1189 tmp = 40370 - 315 * dev->phy.channel;
d24019ad 1190 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
204a665b 1191 tmp = 23242 - 224 * dev->phy.channel;
d24019ad
RM		 1192 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1193 }
1194 } else {
1195 gain[0] = 0;
1196 gain[1] = 0;
1197 }
1198
1199 for (i = 0; i < 2; i++) {
1200 if (nphy->elna_gain_config) {
1201 data[0] = 19 + gain[i];
1202 data[1] = 25 + gain[i];
1203 data[2] = 25 + gain[i];
1204 data[3] = 25 + gain[i];
1205 } else {
1206 data[0] = lna_gain[0] + gain[i];
1207 data[1] = lna_gain[1] + gain[i];
1208 data[2] = lna_gain[2] + gain[i];
1209 data[3] = lna_gain[3] + gain[i];
1210 }
c0f05b98 1211 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
d24019ad
RM		 1212
1213 minmax[i] = 23 + gain[i];
1214 }
1215
1216 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1217 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1218 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1219 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1220
1221 if (nphy->hang_avoid)
1222 b43_nphy_stay_in_carrier_search(dev, 0);
1223}
1224
ef5127a4 1225/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
e723ef30 1226static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
ef5127a4
RM		 1227{
1228 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1229 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ba9a6214
RM		 1230
1231 /* PHY rev 0, 1, 2 */
ef5127a4
RM		 1232 u8 i, j;
1233 u8 code;
c0f05b98 1234 u16 tmp;
ba9a6214
RM		 1235 u8 rfseq_events[3] = { 6, 8, 7 };
1236 u8 rfseq_delays[3] = { 10, 30, 1 };
ef5127a4 1237
ba9a6214
RM		 1238 /* PHY rev >= 3 */
1239 bool ghz5;
1240 bool ext_lna;
1241 u16 rssi_gain;
1242 struct nphy_gain_ctl_workaround_entry *e;
ef5127a4
RM		 1243 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1244 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
ef5127a4
RM		 1245
1246 if (dev->phy.rev >= 3) {
ba9a6214
RM		 1247 /* Prepare values */
1248 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1249 & B43_NPHY_BANDCTL_5GHZ;
1250 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1251 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1252 if (ghz5 && dev->phy.rev >= 5)
1253 rssi_gain = 0x90;
1254 else
1255 rssi_gain = 0x50;
1256
1257 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1258
1259 /* Set Clip 2 detect */
1260 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1261 B43_NPHY_C1_CGAINI_CL2DETECT);
1262 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1263 B43_NPHY_C2_CGAINI_CL2DETECT);
1264
1265 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1266 0x17);
1267 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1268 0x17);
1269 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1270 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1271 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1272 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1273 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1274 rssi_gain);
1275 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1276 rssi_gain);
1277 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1278 0x17);
1279 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1280 0x17);
1281 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1282 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1283
1284 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1285 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1286 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1287 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1288 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1289 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1290 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1291 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1292 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1293 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1294 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1295 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1296
1297 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1298 b43_phy_write(dev, 0x2A7, e->init_gain);
1299 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1300 e->rfseq_init);
1301 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1302
1303 /* TODO: check defines. Do not match variables names */
1304 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1305 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1306 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1307 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1308 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1309 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1310
1311 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1312 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1313 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1314 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1315 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1316 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1317 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1318 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1319 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1320 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1321 } else {
1322 /* Set Clip 2 detect */
1323 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1324 B43_NPHY_C1_CGAINI_CL2DETECT);
1325 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1326 B43_NPHY_C2_CGAINI_CL2DETECT);
1327
1328 /* Set narrowband clip threshold */
a5d3598d
RM		 1329 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1330 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
ef5127a4
RM		 1331
1332 if (!dev->phy.is_40mhz) {
1333 /* Set dwell lengths */
a5d3598d
RM		 1334 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1335 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1336 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1337 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
ef5127a4
RM		 1338 }
1339
1340 /* Set wideband clip 2 threshold */
1341 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1342 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1343 21);
1344 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1345 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1346 21);
1347
1348 if (!dev->phy.is_40mhz) {
1349 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1350 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1351 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1352 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1353 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1354 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1355 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1356 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1357 }
1358
a5d3598d 1359 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1360
1361 if (nphy->gain_boost) {
1362 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1363 dev->phy.is_40mhz)
1364 code = 4;
1365 else
1366 code = 5;
1367 } else {
1368 code = dev->phy.is_40mhz ? 6 : 7;
1369 }
1370
1371 /* Set HPVGA2 index */
1372 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1373 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1374 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1375 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1376 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1377 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1378
1379 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1380 /* specs say about 2 loops, but wl does 4 */
1381 for (i = 0; i < 4; i++)
1382 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1383 (code << 8 | 0x7C));
ef5127a4 1384
d24019ad 1385 b43_nphy_adjust_lna_gain_table(dev);
ef5127a4
RM		 1386
1387 if (nphy->elna_gain_config) {
1388 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1389 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1390 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1391 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1392 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1393
1394 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1395 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1396 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1397 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1398 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1399
1400 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1401 /* specs say about 2 loops, but wl does 4 */
1402 for (i = 0; i < 4; i++)
1403 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1404 (code << 8 | 0x74));
ef5127a4
RM		 1405 }
1406
1407 if (dev->phy.rev == 2) {
1408 for (i = 0; i < 4; i++) {
1409 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1410 (0x0400 * i) + 0x0020);
c0f05b98
RM		 1411 for (j = 0; j < 21; j++) {
1412 tmp = j * (i < 2 ? 3 : 1);
ef5127a4 1413 b43_phy_write(dev,
c0f05b98
RM		 1414 B43_NPHY_TABLE_DATALO, tmp);
1415 }
ef5127a4 1416 }
8e60b044 1417 }
ef5127a4 1418
8e60b044
RM		 1419 b43_nphy_set_rf_sequence(dev, 5,
1420 rfseq_events, rfseq_delays, 3);
1421 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1422 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1423 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
ef5127a4 1424
8e60b044
RM		 1425 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1426 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1427 0xFF80, 4);
ef5127a4
RM		 1428 }
1429}
1430
28fd7daa
RM		 1431/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1432static void b43_nphy_workarounds(struct b43_wldev *dev)
1433{
0581483a 1434 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa
RM		 1435 struct b43_phy *phy = &dev->phy;
1436 struct b43_phy_n *nphy = phy->n;
1437
1438 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1439 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1440
1441 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1442 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1443
ba9a6214
RM		 1444 u16 tmp16;
1445 u32 tmp32;
1446
a5d3598d 1447 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
28fd7daa
RM		 1448 b43_nphy_classifier(dev, 1, 0);
1449 else
1450 b43_nphy_classifier(dev, 1, 1);
1451
1452 if (nphy->hang_avoid)
1453 b43_nphy_stay_in_carrier_search(dev, 1);
1454
1455 b43_phy_set(dev, B43_NPHY_IQFLIP,
1456 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1457
1458 if (dev->phy.rev >= 3) {
ba9a6214
RM		 1459 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1460 tmp32 &= 0xffffff;
1461 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1462
1463 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1464 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1465 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1466 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1467 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1468 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1469
1470 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1471 b43_phy_write(dev, 0x2AE, 0x000C);
1472
1473 /* TODO */
1474
1475 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1476 0x2 : 0x9C40;
1477 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1478
1479 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1480
1481 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1482 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1483
1484 b43_nphy_gain_ctrl_workarounds(dev);
1485
1486 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1487 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1488
28fd7daa 1489 /* TODO */
ba9a6214
RM		 1490
1491 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1492 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1493 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1494 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1495 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1496 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1497 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1498 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1499 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1500 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1501
1502 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1503
0581483a 1504 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
ba9a6214 1505 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
0581483a 1506 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
ba9a6214
RM		 1507 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1508 tmp32 = 0x00088888;
1509 else
1510 tmp32 = 0x88888888;
1511 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1512 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1513 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1514
1515 if (dev->phy.rev == 4 &&
1516 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1517 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1518 0x70);
1519 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1520 0x70);
1521 }
1522
1523 b43_phy_write(dev, 0x224, 0x039C);
1524 b43_phy_write(dev, 0x225, 0x0357);
1525 b43_phy_write(dev, 0x226, 0x0317);
1526 b43_phy_write(dev, 0x227, 0x02D7);
1527 b43_phy_write(dev, 0x228, 0x039C);
1528 b43_phy_write(dev, 0x229, 0x0357);
1529 b43_phy_write(dev, 0x22A, 0x0317);
1530 b43_phy_write(dev, 0x22B, 0x02D7);
1531 b43_phy_write(dev, 0x22C, 0x039C);
1532 b43_phy_write(dev, 0x22D, 0x0357);
1533 b43_phy_write(dev, 0x22E, 0x0317);
1534 b43_phy_write(dev, 0x22F, 0x02D7);
28fd7daa
RM		 1535 } else {
1536 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1537 nphy->band5g_pwrgain) {
1538 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1539 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1540 } else {
1541 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1542 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1543 }
1544
d242b90a
RM		 1545 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1546 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1547 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1548 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
28fd7daa
RM		 1549
1550 if (dev->phy.rev < 2) {
d242b90a
RM		 1551 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1552 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1553 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1554 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1555 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1556 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
28fd7daa
RM		 1557 }
1558
1559 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1560 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1561 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1562 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1563
0581483a 1564 if (sprom->boardflags2_lo & 0x100 &&
79d2232f 1565 dev->dev->board_type == 0x8B) {
28fd7daa
RM		 1566 delays1[0] = 0x1;
1567 delays1[5] = 0x14;
1568 }
9501fefe
RM		 1569 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1570 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
28fd7daa 1571
e723ef30 1572 b43_nphy_gain_ctrl_workarounds(dev);
28fd7daa
RM		 1573
1574 if (dev->phy.rev < 2) {
1575 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
e7f45d3f
GS		 1576 b43_hf_write(dev, b43_hf_read(dev) |
1577 B43_HF_MLADVW);
28fd7daa
RM		 1578 } else if (dev->phy.rev == 2) {
1579 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1580 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1581 }
1582
1583 if (dev->phy.rev < 2)
1584 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1585 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1586
1587 /* Set phase track alpha and beta */
1588 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1589 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1590 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1591 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1592 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1593 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1594
1595 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
acd82aa8 1596 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
28fd7daa
RM		 1597 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1598 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1599 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1600
1601 if (dev->phy.rev == 2)
1602 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1603 B43_NPHY_FINERX2_CGC_DECGC);
1604 }
1605
1606 if (nphy->hang_avoid)
1607 b43_nphy_stay_in_carrier_search(dev, 0);
1608}
1609
5f6393ec
RM		 1610/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1611static int b43_nphy_load_samples(struct b43_wldev *dev,
1612 struct b43_c32 *samples, u16 len) {
1613 struct b43_phy_n *nphy = dev->phy.n;
1614 u16 i;
1615 u32 *data;
1616
1617 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1618 if (!data) {
1619 b43err(dev->wl, "allocation for samples loading failed\n");
1620 return -ENOMEM;
1621 }
1622 if (nphy->hang_avoid)
1623 b43_nphy_stay_in_carrier_search(dev, 1);
1624
1625 for (i = 0; i < len; i++) {
1626 data[i] = (samples[i].i & 0x3FF << 10);
1627 data[i] |= samples[i].q & 0x3FF;
1628 }
1629 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1630
1631 kfree(data);
1632 if (nphy->hang_avoid)
1633 b43_nphy_stay_in_carrier_search(dev, 0);
1634 return 0;
1635}
1636
59af099b
RM		 1637/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1638static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1639 bool test)
1640{
1641 int i;
f2982181 1642 u16 bw, len, rot, angle;
da860475 1643 struct b43_c32 *samples;
f2982181 1644
59af099b
RM		 1645
1646 bw = (dev->phy.is_40mhz) ? 40 : 20;
1647 len = bw << 3;
1648
1649 if (test) {
1650 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1651 bw = 82;
1652 else
1653 bw = 80;
1654
1655 if (dev->phy.is_40mhz)
1656 bw <<= 1;
1657
1658 len = bw << 1;
1659 }
1660
baeb2ffa 1661 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
40bd5203
RM		 1662 if (!samples) {
1663 b43err(dev->wl, "allocation for samples generation failed\n");
1664 return 0;
1665 }
59af099b
RM		 1666 rot = (((freq * 36) / bw) << 16) / 100;
1667 angle = 0;
1668
f2982181
RM		 1669 for (i = 0; i < len; i++) {
1670 samples[i] = b43_cordic(angle);
1671 angle += rot;
1672 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1673 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
59af099b
RM		 1674 }
1675
5f6393ec 1676 i = b43_nphy_load_samples(dev, samples, len);
f2982181 1677 kfree(samples);
5f6393ec 1678 return (i < 0) ? 0 : len;
59af099b
RM		 1679}
1680
10a79873
RM		 1681/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1682static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1683 u16 wait, bool iqmode, bool dac_test)
1684{
1685 struct b43_phy_n *nphy = dev->phy.n;
1686 int i;
1687 u16 seq_mode;
1688 u32 tmp;
1689
1690 if (nphy->hang_avoid)
1691 b43_nphy_stay_in_carrier_search(dev, true);
1692
1693 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1694 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1695 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1696 }
1697
1698 if (!dev->phy.is_40mhz)
1699 tmp = 0x6464;
1700 else
1701 tmp = 0x4747;
1702 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1703
1704 if (nphy->hang_avoid)
1705 b43_nphy_stay_in_carrier_search(dev, false);
1706
1707 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1708
1709 if (loops != 0xFFFF)
1710 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1711 else
1712 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1713
1714 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1715
1716 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1717
1718 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1719 if (iqmode) {
1720 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1721 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1722 } else {
1723 if (dac_test)
1724 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1725 else
1726 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1727 }
1728 for (i = 0; i < 100; i++) {
1729 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1730 i = 0;
1731 break;
1732 }
1733 udelay(10);
1734 }
1735 if (i)
1736 b43err(dev->wl, "run samples timeout\n");
1737
1738 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1739}
1740
59af099b
RM		 1741/*
1742 * Transmits a known value for LO calibration
1743 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1744 */
1745static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1746 bool iqmode, bool dac_test)
1747{
1748 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1749 if (samp == 0)
1750 return -1;
1751 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1752 return 0;
1753}
1754
6dcd9d91
RM		 1755/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1756static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1757{
1758 struct b43_phy_n *nphy = dev->phy.n;
1759 int i, j;
1760 u32 tmp;
1761 u32 cur_real, cur_imag, real_part, imag_part;
1762
1763 u16 buffer[7];
1764
1765 if (nphy->hang_avoid)
1766 b43_nphy_stay_in_carrier_search(dev, true);
1767
9145834e 1768 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 1769
1770 for (i = 0; i < 2; i++) {
1771 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1772 (buffer[i * 2 + 1] & 0x3FF);
1773 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1774 (((i + 26) << 10) | 320));
1775 for (j = 0; j < 128; j++) {
1776 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1777 ((tmp >> 16) & 0xFFFF));
1778 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1779 (tmp & 0xFFFF));
1780 }
1781 }
1782
1783 for (i = 0; i < 2; i++) {
1784 tmp = buffer[5 + i];
1785 real_part = (tmp >> 8) & 0xFF;
1786 imag_part = (tmp & 0xFF);
1787 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1788 (((i + 26) << 10) | 448));
1789
1790 if (dev->phy.rev >= 3) {
1791 cur_real = real_part;
1792 cur_imag = imag_part;
1793 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1794 }
1795
1796 for (j = 0; j < 128; j++) {
1797 if (dev->phy.rev < 3) {
1798 cur_real = (real_part * loscale[j] + 128) >> 8;
1799 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1800 tmp = ((cur_real & 0xFF) << 8) |
1801 (cur_imag & 0xFF);
1802 }
1803 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1804 ((tmp >> 16) & 0xFFFF));
1805 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1806 (tmp & 0xFFFF));
1807 }
1808 }
1809
1810 if (dev->phy.rev >= 3) {
1811 b43_shm_write16(dev, B43_SHM_SHARED,
1812 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1813 b43_shm_write16(dev, B43_SHM_SHARED,
1814 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1815 }
1816
1817 if (nphy->hang_avoid)
1818 b43_nphy_stay_in_carrier_search(dev, false);
1819}
1820
9501fefe
RM		 1821/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1822static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1823 u8 *events, u8 *delays, u8 length)
1824{
1825 struct b43_phy_n *nphy = dev->phy.n;
1826 u8 i;
1827 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1828 u16 offset1 = cmd << 4;
1829 u16 offset2 = offset1 + 0x80;
1830
1831 if (nphy->hang_avoid)
1832 b43_nphy_stay_in_carrier_search(dev, true);
1833
1834 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1835 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1836
1837 for (i = length; i < 16; i++) {
1838 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1839 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1840 }
1841
1842 if (nphy->hang_avoid)
1843 b43_nphy_stay_in_carrier_search(dev, false);
1844}
1845
67c0d6e2 1846/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 1847static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1848 enum b43_nphy_rf_sequence seq)
1849{
1850 static const u16 trigger[] = {
1851 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1852 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1853 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1854 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1855 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1856 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1857 };
1858 int i;
c57199bc 1859 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
95b66bad
MB		 1860
1861 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1862
1863 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1864 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1865 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1866 for (i = 0; i < 200; i++) {
1867 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1868 goto ok;
1869 msleep(1);
1870 }
1871 b43err(dev->wl, "RF sequence status timeout\n");
1872ok:
c57199bc 1873 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
95b66bad
MB		 1874}
1875
75377b24
RM		 1876/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1877static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1878 u16 value, u8 core, bool off)
1879{
1880 int i;
1881 u8 index = fls(field);
1882 u8 addr, en_addr, val_addr;
1883 /* we expect only one bit set */
3ed0fac3 1884 B43_WARN_ON(field & (~(1 << (index - 1))));
75377b24
RM		 1885
1886 if (dev->phy.rev >= 3) {
1887 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1888 for (i = 0; i < 2; i++) {
1889 if (index == 0 || index == 16) {
1890 b43err(dev->wl,
1891 "Unsupported RF Ctrl Override call\n");
1892 return;
1893 }
1894
1895 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1896 en_addr = B43_PHY_N((i == 0) ?
1897 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1898 val_addr = B43_PHY_N((i == 0) ?
1899 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1900
1901 if (off) {
1902 b43_phy_mask(dev, en_addr, ~(field));
1903 b43_phy_mask(dev, val_addr,
1904 ~(rf_ctrl->val_mask));
1905 } else {
1906 if (core == 0 || ((1 << core) & i) != 0) {
1907 b43_phy_set(dev, en_addr, field);
1908 b43_phy_maskset(dev, val_addr,
1909 ~(rf_ctrl->val_mask),
1910 (value << rf_ctrl->val_shift));
1911 }
1912 }
1913 }
1914 } else {
1915 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1916 if (off) {
1917 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1918 value = 0;
1919 } else {
1920 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1921 }
1922
1923 for (i = 0; i < 2; i++) {
1924 if (index <= 1 || index == 16) {
1925 b43err(dev->wl,
1926 "Unsupported RF Ctrl Override call\n");
1927 return;
1928 }
1929
1930 if (index == 2 || index == 10 ||
1931 (index >= 13 && index <= 15)) {
1932 core = 1;
1933 }
1934
1935 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1936 addr = B43_PHY_N((i == 0) ?
1937 rf_ctrl->addr0 : rf_ctrl->addr1);
1938
1939 if ((core & (1 << i)) != 0)
1940 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1941 (value << rf_ctrl->shift));
1942
1943 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1944 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1945 B43_NPHY_RFCTL_CMD_START);
1946 udelay(1);
1947 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1948 }
1949 }
1950}
1951
67cbc3ed
RM		 1952/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1953static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1954 u16 value, u8 core)
1955{
1956 u8 i, j;
1957 u16 reg, tmp, val;
1958
1959 B43_WARN_ON(dev->phy.rev < 3);
1960 B43_WARN_ON(field > 4);
1961
1962 for (i = 0; i < 2; i++) {
1963 if ((core == 1 && i == 1) || (core == 2 && !i))
1964 continue;
1965
1966 reg = (i == 0) ?
1967 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1968 b43_phy_mask(dev, reg, 0xFBFF);
1969
1970 switch (field) {
1971 case 0:
1972 b43_phy_write(dev, reg, 0);
1973 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1974 break;
1975 case 1:
1976 if (!i) {
1977 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1978 0xFC3F, (value << 6));
1979 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1980 0xFFFE, 1);
1981 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1982 B43_NPHY_RFCTL_CMD_START);
1983 for (j = 0; j < 100; j++) {
1984 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1985 j = 0;
1986 break;
1987 }
1988 udelay(10);
1989 }
1990 if (j)
1991 b43err(dev->wl,
1992 "intc override timeout\n");
1993 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1994 0xFFFE);
1995 } else {
1996 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1997 0xFC3F, (value << 6));
1998 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1999 0xFFFE, 1);
2000 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2001 B43_NPHY_RFCTL_CMD_RXTX);
2002 for (j = 0; j < 100; j++) {
2003 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2004 j = 0;
2005 break;
2006 }
2007 udelay(10);
2008 }
2009 if (j)
2010 b43err(dev->wl,
2011 "intc override timeout\n");
2012 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2013 0xFFFE);
2014 }
2015 break;
2016 case 2:
2017 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2018 tmp = 0x0020;
2019 val = value << 5;
2020 } else {
2021 tmp = 0x0010;
2022 val = value << 4;
2023 }
2024 b43_phy_maskset(dev, reg, ~tmp, val);
2025 break;
2026 case 3:
2027 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2028 tmp = 0x0001;
2029 val = value;
2030 } else {
2031 tmp = 0x0004;
2032 val = value << 2;
2033 }
2034 b43_phy_maskset(dev, reg, ~tmp, val);
2035 break;
2036 case 4:
2037 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2038 tmp = 0x0002;
2039 val = value << 1;
2040 } else {
2041 tmp = 0x0008;
2042 val = value << 3;
2043 }
2044 b43_phy_maskset(dev, reg, ~tmp, val);
2045 break;
2046 }
2047 }
2048}
2049
bec18645 2050/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
95b66bad
MB		 2051static void b43_nphy_bphy_init(struct b43_wldev *dev)
2052{
2053 unsigned int i;
2054 u16 val;
2055
2056 val = 0x1E1F;
fee613b7 2057 for (i = 0; i < 16; i++) {
95b66bad
MB		 2058 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2059 val -= 0x202;
2060 }
2061 val = 0x3E3F;
2062 for (i = 0; i < 16; i++) {
fee613b7 2063 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
95b66bad
MB		 2064 val -= 0x202;
2065 }
2066 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2067}
2068
3c95627d
RM		 2069/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2070static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
76b002bd
RM		 2071 s8 offset, u8 core, u8 rail,
2072 enum b43_nphy_rssi_type type)
3c95627d
RM		 2073{
2074 u16 tmp;
2075 bool core1or5 = (core == 1) || (core == 5);
2076 bool core2or5 = (core == 2) || (core == 5);
2077
2078 offset = clamp_val(offset, -32, 31);
2079 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2080
76b002bd 2081 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2082 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
76b002bd 2083 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2084 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
76b002bd 2085 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2086 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
76b002bd 2087 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2088 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
76b002bd
RM		 2089
2090 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2091 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
76b002bd 2092 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2093 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
76b002bd 2094 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2095 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
76b002bd 2096 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2097 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
76b002bd
RM		 2098
2099 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2100 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
76b002bd 2101 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2102 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
76b002bd 2103 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2104 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
76b002bd 2105 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2106 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
76b002bd
RM		 2107
2108 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2109 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
76b002bd 2110 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2111 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
76b002bd 2112 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2113 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
76b002bd 2114 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2115 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
76b002bd
RM		 2116
2117 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2118 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
76b002bd 2119 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2120 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
76b002bd 2121 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2122 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
76b002bd 2123 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2124 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
76b002bd
RM		 2125
2126 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2127 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
76b002bd 2128 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2129 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
76b002bd
RM		 2130
2131 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d 2132 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
76b002bd 2133 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d
RM		 2134 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2135}
2136
99b82c41 2137static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
3c95627d
RM		 2138{
2139 u16 val;
2140
99b82c41
RM		 2141 if (type < 3)
2142 val = 0;
2143 else if (type == 6)
2144 val = 1;
2145 else if (type == 3)
2146 val = 2;
2147 else
2148 val = 3;
2149
2150 val = (val << 12) | (val << 14);
2151 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2152 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
3c95627d 2153
99b82c41
RM		 2154 if (type < 3) {
2155 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2156 (type + 1) << 4);
2157 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2158 (type + 1) << 4);
2159 }
3c95627d 2160
99b82c41 2161 if (code == 0) {
99f6c2ef 2162 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
3c95627d 2163 if (type < 3) {
99f6c2ef
RM		 2164 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2165 ~(B43_NPHY_RFCTL_CMD_RXEN |
2166 B43_NPHY_RFCTL_CMD_CORESEL));
2167 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2168 ~(0x1 << 12 |
2169 0x1 << 5 |
2170 0x1 << 1 |
2171 0x1));
2172 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2173 ~B43_NPHY_RFCTL_CMD_START);
99b82c41 2174 udelay(20);
99f6c2ef 2175 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d 2176 }
99b82c41 2177 } else {
99f6c2ef 2178 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
99b82c41
RM		 2179 if (type < 3) {
2180 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
99f6c2ef
RM		 2181 ~(B43_NPHY_RFCTL_CMD_RXEN |
2182 B43_NPHY_RFCTL_CMD_CORESEL),
2183 (B43_NPHY_RFCTL_CMD_RXEN |
2184 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2185 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2186 (0x1 << 12 |
2187 0x1 << 5 |
2188 0x1 << 1 |
2189 0x1));
2190 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2191 B43_NPHY_RFCTL_CMD_START);
99b82c41 2192 udelay(20);
99f6c2ef 2193 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d
RM		 2194 }
2195 }
2196}
2197
99b82c41
RM		 2198static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2199{
6e3b15a9
RM		 2200 u8 i;
2201 u16 reg, val;
2202
2203 if (code == 0) {
2204 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2205 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2206 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2207 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2208 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2209 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2210 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2211 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2212 } else {
2213 for (i = 0; i < 2; i++) {
2214 if ((code == 1 && i == 1) || (code == 2 && !i))
2215 continue;
2216
2217 reg = (i == 0) ?
2218 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2219 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2220
2221 if (type < 3) {
2222 reg = (i == 0) ?
2223 B43_NPHY_AFECTL_C1 :
2224 B43_NPHY_AFECTL_C2;
2225 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2226
2227 reg = (i == 0) ?
2228 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2229 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2230 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2231
2232 if (type == 0)
2233 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2234 else if (type == 1)
2235 val = 16;
2236 else
2237 val = 32;
2238 b43_phy_set(dev, reg, val);
2239
2240 reg = (i == 0) ?
2241 B43_NPHY_TXF_40CO_B1S0 :
2242 B43_NPHY_TXF_40CO_B32S1;
2243 b43_phy_set(dev, reg, 0x0020);
2244 } else {
2245 if (type == 6)
2246 val = 0x0100;
2247 else if (type == 3)
2248 val = 0x0200;
2249 else
2250 val = 0x0300;
2251
2252 reg = (i == 0) ?
2253 B43_NPHY_AFECTL_C1 :
2254 B43_NPHY_AFECTL_C2;
2255
2256 b43_phy_maskset(dev, reg, 0xFCFF, val);
2257 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2258
2259 if (type != 3 && type != 6) {
2260 enum ieee80211_band band =
2261 b43_current_band(dev->wl);
2262
c002831a 2263 if (b43_nphy_ipa(dev))
6e3b15a9
RM		 2264 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2265 else
2266 val = 0x11;
2267 reg = (i == 0) ? 0x2000 : 0x3000;
2268 reg |= B2055_PADDRV;
2269 b43_radio_write16(dev, reg, val);
2270
2271 reg = (i == 0) ?
2272 B43_NPHY_AFECTL_OVER1 :
2273 B43_NPHY_AFECTL_OVER;
2274 b43_phy_set(dev, reg, 0x0200);
2275 }
2276 }
2277 }
2278 }
99b82c41
RM		 2279}
2280
2281/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2282static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2283{
2284 if (dev->phy.rev >= 3)
2285 b43_nphy_rev3_rssi_select(dev, code, type);
2286 else
2287 b43_nphy_rev2_rssi_select(dev, code, type);
2288}
2289
dfb4aa5d
RM		 2290/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2291static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2292{
2293 int i;
2294 for (i = 0; i < 2; i++) {
2295 if (type == 2) {
2296 if (i == 0) {
2297 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2298 0xFC, buf[0]);
2299 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2300 0xFC, buf[1]);
2301 } else {
2302 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2303 0xFC, buf[2 * i]);
2304 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2305 0xFC, buf[2 * i + 1]);
2306 }
2307 } else {
2308 if (i == 0)
2309 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2310 0xF3, buf[0] << 2);
2311 else
2312 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2313 0xF3, buf[2 * i + 1] << 2);
2314 }
2315 }
2316}
2317
2318/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2319static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2320 u8 nsamp)
2321{
2322 int i;
2323 int out;
2324 u16 save_regs_phy[9];
2325 u16 s[2];
2326
2327 if (dev->phy.rev >= 3) {
2328 save_regs_phy[0] = b43_phy_read(dev,
2329 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2330 save_regs_phy[1] = b43_phy_read(dev,
2331 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2332 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2333 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2334 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2335 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2336 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2337 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2eeb6fd0 2338 save_regs_phy[8] = 0;
05db8c57 2339 } else {
a529cecd
RM		 2340 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2341 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2342 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2343 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2344 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2345 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2346 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2eeb6fd0
JL		 2347 save_regs_phy[7] = 0;
2348 save_regs_phy[8] = 0;
dfb4aa5d
RM		 2349 }
2350
2351 b43_nphy_rssi_select(dev, 5, type);
2352
2353 if (dev->phy.rev < 2) {
2354 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2355 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2356 }
2357
2358 for (i = 0; i < 4; i++)
2359 buf[i] = 0;
2360
2361 for (i = 0; i < nsamp; i++) {
2362 if (dev->phy.rev < 2) {
2363 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2364 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2365 } else {
2366 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2367 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2368 }
2369
2370 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2371 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2372 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2373 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2374 }
2375 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2376 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2377
2378 if (dev->phy.rev < 2)
2379 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2380
2381 if (dev->phy.rev >= 3) {
2382 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2383 save_regs_phy[0]);
2384 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2385 save_regs_phy[1]);
2386 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2387 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2388 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2389 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2390 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2391 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
05db8c57 2392 } else {
a529cecd
RM		 2393 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2394 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2395 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2396 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2397 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2398 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2399 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
dfb4aa5d
RM		 2400 }
2401
2402 return out;
2403}
2404
4cb99775
RM		 2405/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2406static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 2407{
90b9738d
RM		 2408 int i, j;
2409 u8 state[4];
2410 u8 code, val;
2411 u16 class, override;
2412 u8 regs_save_radio[2];
2413 u16 regs_save_phy[2];
8cbe6e66 2414
90b9738d 2415 s8 offset[4];
8cbe6e66
RM		 2416 u8 core;
2417 u8 rail;
90b9738d
RM		 2418
2419 u16 clip_state[2];
2420 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2421 s32 results_min[4] = { };
2422 u8 vcm_final[4] = { };
2423 s32 results[4][4] = { };
2424 s32 miniq[4][2] = { };
2425
2426 if (type == 2) {
2427 code = 0;
2428 val = 6;
2429 } else if (type < 2) {
2430 code = 25;
2431 val = 4;
2432 } else {
2433 B43_WARN_ON(1);
2434 return;
2435 }
2436
2437 class = b43_nphy_classifier(dev, 0, 0);
2438 b43_nphy_classifier(dev, 7, 4);
2439 b43_nphy_read_clip_detection(dev, clip_state);
2440 b43_nphy_write_clip_detection(dev, clip_off);
2441
2442 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2443 override = 0x140;
2444 else
2445 override = 0x110;
2446
2447 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2448 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2449 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2450 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2451
2452 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2453 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2454 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2455 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2456
2457 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2458 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2459 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2460 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2461 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2462 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2463
2464 b43_nphy_rssi_select(dev, 5, type);
2465 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2466 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2467
2468 for (i = 0; i < 4; i++) {
2469 u8 tmp[4];
2470 for (j = 0; j < 4; j++)
2471 tmp[j] = i;
2472 if (type != 1)
2473 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2474 b43_nphy_poll_rssi(dev, type, results[i], 8);
2475 if (type < 2)
2476 for (j = 0; j < 2; j++)
2477 miniq[i][j] = min(results[i][2 * j],
2478 results[i][2 * j + 1]);
2479 }
2480
2481 for (i = 0; i < 4; i++) {
2482 s32 mind = 40;
2483 u8 minvcm = 0;
2484 s32 minpoll = 249;
2485 s32 curr;
2486 for (j = 0; j < 4; j++) {
2487 if (type == 2)
2488 curr = abs(results[j][i]);
2489 else
2490 curr = abs(miniq[j][i / 2] - code * 8);
2491
2492 if (curr < mind) {
2493 mind = curr;
2494 minvcm = j;
2495 }
2496
2497 if (results[j][i] < minpoll)
2498 minpoll = results[j][i];
2499 }
2500 results_min[i] = minpoll;
2501 vcm_final[i] = minvcm;
2502 }
2503
2504 if (type != 1)
2505 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2506
2507 for (i = 0; i < 4; i++) {
2508 offset[i] = (code * 8) - results[vcm_final[i]][i];
2509
2510 if (offset[i] < 0)
2511 offset[i] = -((abs(offset[i]) + 4) / 8);
2512 else
2513 offset[i] = (offset[i] + 4) / 8;
2514
2515 if (results_min[i] == 248)
2516 offset[i] = code - 32;
2517
8cbe6e66
RM		 2518 core = (i / 2) ? 2 : 1;
2519 rail = (i % 2) ? 1 : 0;
2520
2521 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2522 type);
90b9738d
RM		 2523 }
2524
2525 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
0b81c23d 2526 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
90b9738d
RM		 2527
2528 switch (state[2]) {
2529 case 1:
2530 b43_nphy_rssi_select(dev, 1, 2);
2531 break;
2532 case 4:
2533 b43_nphy_rssi_select(dev, 1, 0);
2534 break;
2535 case 2:
2536 b43_nphy_rssi_select(dev, 1, 1);
2537 break;
2538 default:
2539 b43_nphy_rssi_select(dev, 1, 1);
2540 break;
2541 }
2542
2543 switch (state[3]) {
2544 case 1:
2545 b43_nphy_rssi_select(dev, 2, 2);
2546 break;
2547 case 4:
2548 b43_nphy_rssi_select(dev, 2, 0);
2549 break;
2550 default:
2551 b43_nphy_rssi_select(dev, 2, 1);
2552 break;
2553 }
2554
2555 b43_nphy_rssi_select(dev, 0, type);
2556
2557 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2558 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2559 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2560 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2561
2562 b43_nphy_classifier(dev, 7, class);
2563 b43_nphy_write_clip_detection(dev, clip_state);
8c1d5a7a
RM		 2564 /* Specs don't say about reset here, but it makes wl and b43 dumps
2565 identical, it really seems wl performs this */
2566 b43_nphy_reset_cca(dev);
4cb99775
RM		 2567}
2568
2569/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2570static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2571{
2572 /* TODO */
2573}
2574
2575/*
2576 * RSSI Calibration
2577 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2578 */
2579static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2580{
2581 if (dev->phy.rev >= 3) {
2582 b43_nphy_rev3_rssi_cal(dev);
2583 } else {
76b002bd
RM		 2584 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2585 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2586 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
4cb99775 2587 }
95b66bad
MB		 2588}
2589
42e1547e
RM		 2590/*
2591 * Restore RSSI Calibration
2592 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2593 */
2594static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2595{
2596 struct b43_phy_n *nphy = dev->phy.n;
2597
2598 u16 *rssical_radio_regs = NULL;
2599 u16 *rssical_phy_regs = NULL;
2600
2601 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2602 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 2603 return;
2604 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2605 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2606 } else {
204a665b 2607 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 2608 return;
2609 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2610 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2611 }
2612
2613 /* TODO use some definitions */
2614 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2615 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2616
2617 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2618 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2619 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2620 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2621
2622 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2623 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2624 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2625 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2626
2627 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2628 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2629 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2630 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2631}
2632
2f258b74
RM		 2633/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2634static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2635{
2636 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2637 if (dev->phy.rev >= 6) {
2638 /* TODO If the chip is 47162
2639 return txpwrctrl_tx_gain_ipa_rev5 */
2640 return txpwrctrl_tx_gain_ipa_rev6;
2641 } else if (dev->phy.rev >= 5) {
2642 return txpwrctrl_tx_gain_ipa_rev5;
2643 } else {
2644 return txpwrctrl_tx_gain_ipa;
2645 }
2646 } else {
2647 return txpwrctrl_tx_gain_ipa_5g;
2648 }
2649}
2650
c4a92003
RM		 2651/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2652static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2653{
2654 struct b43_phy_n *nphy = dev->phy.n;
2655 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2656 u16 tmp;
2657 u8 offset, i;
c4a92003
RM		 2658
2659 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2660 for (i = 0; i < 2; i++) {
2661 tmp = (i == 0) ? 0x2000 : 0x3000;
2662 offset = i * 11;
2663
2664 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2665 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2666 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2667 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2668 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2669 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2670 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2671 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2672 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2673 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2674 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2675
2676 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2677 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2678 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2679 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2680 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2681 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2682 if (nphy->ipa5g_on) {
2683 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2684 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2685 } else {
2686 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2687 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2688 }
2689 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2690 } else {
2691 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2692 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2693 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2694 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2695 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2696 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2697 if (nphy->ipa2g_on) {
2698 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2699 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2700 (dev->phy.rev < 5) ? 0x11 : 0x01);
2701 } else {
2702 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2703 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2704 }
2705 }
2706 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2707 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2708 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2709 }
c4a92003
RM		 2710 } else {
2711 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2712 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2713
2714 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2715 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2716
2717 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2718 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2719
2720 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2721 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2722
2723 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2724 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2725
2726 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2727 B43_NPHY_BANDCTL_5GHZ)) {
2728 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2729 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2730 } else {
2731 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2732 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2733 }
2734
2735 if (dev->phy.rev < 2) {
2736 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2737 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2738 } else {
2739 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2740 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2741 }
2742 }
2743}
2744
e9762492
RM		 2745/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2746static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2747 struct nphy_txgains target,
2748 struct nphy_iqcal_params *params)
2749{
2750 int i, j, indx;
2751 u16 gain;
2752
2753 if (dev->phy.rev >= 3) {
2754 params->txgm = target.txgm[core];
2755 params->pga = target.pga[core];
2756 params->pad = target.pad[core];
2757 params->ipa = target.ipa[core];
2758 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2759 (params->pad << 4) | (params->ipa);
2760 for (j = 0; j < 5; j++)
2761 params->ncorr[j] = 0x79;
2762 } else {
2763 gain = (target.pad[core]) | (target.pga[core] << 4) |
2764 (target.txgm[core] << 8);
2765
2766 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2767 1 : 0;
2768 for (i = 0; i < 9; i++)
2769 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2770 break;
2771 i = min(i, 8);
2772
2773 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2774 params->pga = tbl_iqcal_gainparams[indx][i][2];
2775 params->pad = tbl_iqcal_gainparams[indx][i][3];
2776 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2777 (params->pad << 2);
2778 for (j = 0; j < 4; j++)
2779 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2780 }
2781}
2782
de7ed0c6
RM		 2783/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2784static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2785{
2786 struct b43_phy_n *nphy = dev->phy.n;
2787 int i;
2788 u16 scale, entry;
2789
2790 u16 tmp = nphy->txcal_bbmult;
2791 if (core == 0)
2792 tmp >>= 8;
2793 tmp &= 0xff;
2794
2795 for (i = 0; i < 18; i++) {
2796 scale = (ladder_lo[i].percent * tmp) / 100;
2797 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 2798 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 2799
2800 scale = (ladder_iq[i].percent * tmp) / 100;
2801 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 2802 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 2803 }
2804}
2805
45ca697e
RM		 2806/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2807static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2808{
2809 int i;
2810 for (i = 0; i < 15; i++)
2811 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2812 tbl_tx_filter_coef_rev4[2][i]);
2813}
2814
2815/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2816static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2817{
2818 int i, j;
2819 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 2820 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 2821
2822 for (i = 0; i < 3; i++)
2823 for (j = 0; j < 15; j++)
2824 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2825 tbl_tx_filter_coef_rev4[i][j]);
2826
2827 if (dev->phy.is_40mhz) {
2828 for (j = 0; j < 15; j++)
2829 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2830 tbl_tx_filter_coef_rev4[3][j]);
2831 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2832 for (j = 0; j < 15; j++)
2833 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2834 tbl_tx_filter_coef_rev4[5][j]);
2835 }
2836
2837 if (dev->phy.channel == 14)
2838 for (j = 0; j < 15; j++)
2839 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2840 tbl_tx_filter_coef_rev4[6][j]);
2841}
2842
b0022e15
RM		 2843/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2844static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2845{
2846 struct b43_phy_n *nphy = dev->phy.n;
2847
2848 u16 curr_gain[2];
2849 struct nphy_txgains target;
2850 const u32 *table = NULL;
2851
161d540c 2852 if (!nphy->txpwrctrl) {
b0022e15
RM		 2853 int i;
2854
2855 if (nphy->hang_avoid)
2856 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 2857 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 2858 if (nphy->hang_avoid)
2859 b43_nphy_stay_in_carrier_search(dev, false);
2860
2861 for (i = 0; i < 2; ++i) {
2862 if (dev->phy.rev >= 3) {
2863 target.ipa[i] = curr_gain[i] & 0x000F;
2864 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2865 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2866 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2867 } else {
2868 target.ipa[i] = curr_gain[i] & 0x0003;
2869 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2870 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2871 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2872 }
2873 }
2874 } else {
2875 int i;
2876 u16 index[2];
2877 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2878 B43_NPHY_TXPCTL_STAT_BIDX) >>
2879 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2880 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2881 B43_NPHY_TXPCTL_STAT_BIDX) >>
2882 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2883
2884 for (i = 0; i < 2; ++i) {
2885 if (dev->phy.rev >= 3) {
2886 enum ieee80211_band band =
2887 b43_current_band(dev->wl);
2888
c002831a 2889 if (b43_nphy_ipa(dev)) {
b0022e15
RM		 2890 table = b43_nphy_get_ipa_gain_table(dev);
2891 } else {
2892 if (band == IEEE80211_BAND_5GHZ) {
2893 if (dev->phy.rev == 3)
2894 table = b43_ntab_tx_gain_rev3_5ghz;
2895 else if (dev->phy.rev == 4)
2896 table = b43_ntab_tx_gain_rev4_5ghz;
2897 else
2898 table = b43_ntab_tx_gain_rev5plus_5ghz;
2899 } else {
2900 table = b43_ntab_tx_gain_rev3plus_2ghz;
2901 }
2902 }
2903
2904 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2905 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2906 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2907 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2908 } else {
2909 table = b43_ntab_tx_gain_rev0_1_2;
2910
2911 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2912 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2913 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2914 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2915 }
2916 }
2917 }
2918
2919 return target;
2920}
2921
e53de674
RM		 2922/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2923static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2924{
2925 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2926
2927 if (dev->phy.rev >= 3) {
2928 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2929 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2930 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2931 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2932 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 2933 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2934 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 2935 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2937 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2938 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2939 b43_nphy_reset_cca(dev);
2940 } else {
2941 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2942 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2943 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 2944 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2945 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 2946 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2947 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2948 }
2949}
2950
2951/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2952static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2953{
2954 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2955 u16 tmp;
2956
2957 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2958 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2959 if (dev->phy.rev >= 3) {
2960 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2961 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2962
2963 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2964 regs[2] = tmp;
2965 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2966
2967 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2968 regs[3] = tmp;
2969 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2970
2971 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 2972 b43_phy_mask(dev, B43_NPHY_BBCFG,
2973 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 2974
c643a66e 2975 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 2976 regs[5] = tmp;
d41a3552 2977 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 2978
2979 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 2980 regs[6] = tmp;
d41a3552 2981 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 2982 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2983 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2984
67cbc3ed
RM		 2985 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2986 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2987 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 2988
2989 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2990 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2991 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2992 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2993 } else {
2994 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2995 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2996 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2997 regs[2] = tmp;
2998 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 2999 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 3000 regs[3] = tmp;
3001 tmp |= 0x2000;
d41a3552 3002 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 3003 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 3004 regs[4] = tmp;
3005 tmp |= 0x2000;
d41a3552 3006 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 3007 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3008 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3009 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3010 tmp = 0x0180;
3011 else
3012 tmp = 0x0120;
3013 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3014 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3015 }
3016}
3017
bbc6dc12
RM		 3018/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3019static void b43_nphy_save_cal(struct b43_wldev *dev)
3020{
3021 struct b43_phy_n *nphy = dev->phy.n;
3022
3023 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3024 u16 *txcal_radio_regs = NULL;
902db91d 3025 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 3026 u16 *table = NULL;
3027
3028 if (nphy->hang_avoid)
3029 b43_nphy_stay_in_carrier_search(dev, 1);
3030
3031 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3032 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3033 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3034 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3035 table = nphy->cal_cache.txcal_coeffs_2G;
3036 } else {
3037 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3038 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3039 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3040 table = nphy->cal_cache.txcal_coeffs_5G;
3041 }
3042
3043 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3044 /* TODO use some definitions */
3045 if (dev->phy.rev >= 3) {
3046 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3047 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3048 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3049 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3050 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3051 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3052 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3053 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3054 } else {
3055 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3056 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3057 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3058 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3059 }
204a665b
RM		 3060 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3061 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 3062 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 3063
3064 if (nphy->hang_avoid)
3065 b43_nphy_stay_in_carrier_search(dev, 0);
3066}
3067
2f258b74
RM		 3068/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3069static void b43_nphy_restore_cal(struct b43_wldev *dev)
3070{
3071 struct b43_phy_n *nphy = dev->phy.n;
3072
3073 u16 coef[4];
3074 u16 *loft = NULL;
3075 u16 *table = NULL;
3076
3077 int i;
3078 u16 *txcal_radio_regs = NULL;
3079 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3080
3081 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3082 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 3083 return;
3084 table = nphy->cal_cache.txcal_coeffs_2G;
3085 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3086 } else {
204a665b 3087 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 3088 return;
3089 table = nphy->cal_cache.txcal_coeffs_5G;
3090 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3091 }
3092
2581b143 3093 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 3094
3095 for (i = 0; i < 4; i++) {
3096 if (dev->phy.rev >= 3)
3097 table[i] = coef[i];
3098 else
3099 coef[i] = 0;
3100 }
3101
2581b143
RM		 3102 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3103 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3104 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 3105
3106 if (dev->phy.rev < 2)
3107 b43_nphy_tx_iq_workaround(dev);
3108
3109 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3110 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3111 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3112 } else {
3113 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3114 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3115 }
3116
3117 /* TODO use some definitions */
3118 if (dev->phy.rev >= 3) {
3119 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3120 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3121 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3122 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3123 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3124 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3125 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3126 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3127 } else {
3128 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3129 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3130 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3131 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3132 }
3133 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3134}
3135
fb43b8e2
RM		 3136/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3137static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3138 struct nphy_txgains target,
3139 bool full, bool mphase)
3140{
3141 struct b43_phy_n *nphy = dev->phy.n;
3142 int i;
3143 int error = 0;
3144 int freq;
3145 bool avoid = false;
3146 u8 length;
fb23d863 3147 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 3148 const u16 *table;
3149 bool phy6or5x;
3150
3151 u16 buffer[11];
3152 u16 diq_start = 0;
3153 u16 save[2];
3154 u16 gain[2];
3155 struct nphy_iqcal_params params[2];
3156 bool updated[2] = { };
3157
3158 b43_nphy_stay_in_carrier_search(dev, true);
3159
3160 if (dev->phy.rev >= 4) {
3161 avoid = nphy->hang_avoid;
3162 nphy->hang_avoid = 0;
3163 }
3164
9145834e 3165 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3166
3167 for (i = 0; i < 2; i++) {
3168 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3169 gain[i] = params[i].cal_gain;
3170 }
2581b143
RM		 3171
3172 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 3173
3174 b43_nphy_tx_cal_radio_setup(dev);
e53de674 3175 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 3176
3177 phy6or5x = dev->phy.rev >= 6 ||
3178 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3179 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3180 if (phy6or5x) {
38bb9029
RM		 3181 if (dev->phy.is_40mhz) {
3182 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3183 tbl_tx_iqlo_cal_loft_ladder_40);
3184 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3185 tbl_tx_iqlo_cal_iqimb_ladder_40);
3186 } else {
3187 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3188 tbl_tx_iqlo_cal_loft_ladder_20);
3189 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3190 tbl_tx_iqlo_cal_iqimb_ladder_20);
3191 }
fb43b8e2
RM		 3192 }
3193
3194 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3195
aa4c7b2a 3196 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 3197 freq = 2500;
3198 else
3199 freq = 5000;
3200
3201 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 3202 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3203 0xFFFF, 0, true, false);
fb43b8e2 3204 else
59af099b 3205 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 3206
3207 if (error == 0) {
3208 if (nphy->mphase_cal_phase_id > 2) {
3209 table = nphy->mphase_txcal_bestcoeffs;
3210 length = 11;
3211 if (dev->phy.rev < 3)
3212 length -= 2;
3213 } else {
3214 if (!full && nphy->txiqlocal_coeffsvalid) {
3215 table = nphy->txiqlocal_bestc;
3216 length = 11;
3217 if (dev->phy.rev < 3)
3218 length -= 2;
3219 } else {
3220 full = true;
3221 if (dev->phy.rev >= 3) {
3222 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3223 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3224 } else {
3225 table = tbl_tx_iqlo_cal_startcoefs;
3226 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3227 }
3228 }
3229 }
3230
2581b143 3231 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 3232
3233 if (full) {
3234 if (dev->phy.rev >= 3)
3235 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3236 else
3237 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3238 } else {
3239 if (dev->phy.rev >= 3)
3240 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3241 else
3242 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3243 }
3244
3245 if (mphase) {
3246 count = nphy->mphase_txcal_cmdidx;
3247 numb = min(max,
3248 (u16)(count + nphy->mphase_txcal_numcmds));
3249 } else {
3250 count = 0;
3251 numb = max;
3252 }
3253
3254 for (; count < numb; count++) {
3255 if (full) {
3256 if (dev->phy.rev >= 3)
3257 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3258 else
3259 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3260 } else {
3261 if (dev->phy.rev >= 3)
3262 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3263 else
3264 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3265 }
3266
3267 core = (cmd & 0x3000) >> 12;
3268 type = (cmd & 0x0F00) >> 8;
3269
3270 if (phy6or5x && updated[core] == 0) {
3271 b43_nphy_update_tx_cal_ladder(dev, core);
3272 updated[core] = 1;
3273 }
3274
3275 tmp = (params[core].ncorr[type] << 8) | 0x66;
3276 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3277
3278 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 3279 buffer[0] = b43_ntab_read(dev,
3280 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 3281 diq_start = buffer[0];
3282 buffer[0] = 0;
d41a3552
RM		 3283 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3284 0);
fb43b8e2
RM		 3285 }
3286
3287 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3288 for (i = 0; i < 2000; i++) {
3289 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3290 if (tmp & 0xC000)
3291 break;
3292 udelay(10);
3293 }
3294
9145834e
RM		 3295 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3296 buffer);
2581b143
RM		 3297 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3298 buffer);
fb43b8e2
RM		 3299
3300 if (type == 1 || type == 3 || type == 4)
3301 buffer[0] = diq_start;
3302 }
3303
3304 if (mphase)
3305 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3306
3307 last = (dev->phy.rev < 3) ? 6 : 7;
3308
3309 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 3310 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 3311 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 3312 if (dev->phy.rev < 3) {
3313 buffer[0] = 0;
3314 buffer[1] = 0;
3315 buffer[2] = 0;
3316 buffer[3] = 0;
3317 }
2581b143
RM		 3318 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3319 buffer);
bc53e512 3320 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 3321 buffer);
3322 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3323 buffer);
3324 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3325 buffer);
fb43b8e2
RM		 3326 length = 11;
3327 if (dev->phy.rev < 3)
3328 length -= 2;
9145834e
RM		 3329 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3330 nphy->txiqlocal_bestc);
fb43b8e2 3331 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 3332 nphy->txiqlocal_chanspec.center_freq =
3333 dev->phy.channel_freq;
3334 nphy->txiqlocal_chanspec.channel_type =
3335 dev->phy.channel_type;
fb43b8e2
RM		 3336 } else {
3337 length = 11;
3338 if (dev->phy.rev < 3)
3339 length -= 2;
9145834e
RM		 3340 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3341 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 3342 }
3343
53ae8e8c 3344 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 3345 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3346 }
3347
e53de674 3348 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 3349 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3350
3351 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3352 b43_nphy_tx_iq_workaround(dev);
3353
3354 if (dev->phy.rev >= 4)
3355 nphy->hang_avoid = avoid;
3356
3357 b43_nphy_stay_in_carrier_search(dev, false);
3358
3359 return error;
3360}
3361
984ff4ff
RM		 3362/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3363static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3364{
3365 struct b43_phy_n *nphy = dev->phy.n;
3366 u8 i;
3367 u16 buffer[7];
3368 bool equal = true;
3369
902db91d 3370 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 3371 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3372 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 3373 return;
3374
3375 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3376 for (i = 0; i < 4; i++) {
3377 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3378 equal = false;
3379 break;
3380 }
3381 }
3382
3383 if (!equal) {
3384 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3385 nphy->txiqlocal_bestc);
3386 for (i = 0; i < 4; i++)
3387 buffer[i] = 0;
3388 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3389 buffer);
3390 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3391 &nphy->txiqlocal_bestc[5]);
3392 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3393 &nphy->txiqlocal_bestc[5]);
3394 }
3395}
3396
15931e31
RM		 3397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3398static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3399 struct nphy_txgains target, u8 type, bool debug)
3400{
3401 struct b43_phy_n *nphy = dev->phy.n;
3402 int i, j, index;
3403 u8 rfctl[2];
3404 u8 afectl_core;
3405 u16 tmp[6];
c7455cf9 3406 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 3407 u32 real, imag;
3408 enum ieee80211_band band;
3409
3410 u8 use;
3411 u16 cur_hpf;
3412 u16 lna[3] = { 3, 3, 1 };
3413 u16 hpf1[3] = { 7, 2, 0 };
3414 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 3415 u32 power[3] = { };
15931e31
RM		 3416 u16 gain_save[2];
3417 u16 cal_gain[2];
3418 struct nphy_iqcal_params cal_params[2];
3419 struct nphy_iq_est est;
3420 int ret = 0;
3421 bool playtone = true;
3422 int desired = 13;
3423
3424 b43_nphy_stay_in_carrier_search(dev, 1);
3425
3426 if (dev->phy.rev < 2)
984ff4ff 3427 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 3428 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3429 for (i = 0; i < 2; i++) {
3430 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3431 cal_gain[i] = cal_params[i].cal_gain;
3432 }
2581b143 3433 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 3434
3435 for (i = 0; i < 2; i++) {
3436 if (i == 0) {
3437 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3438 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3439 afectl_core = B43_NPHY_AFECTL_C1;
3440 } else {
3441 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3442 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3443 afectl_core = B43_NPHY_AFECTL_C2;
3444 }
3445
3446 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3447 tmp[2] = b43_phy_read(dev, afectl_core);
3448 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3449 tmp[4] = b43_phy_read(dev, rfctl[0]);
3450 tmp[5] = b43_phy_read(dev, rfctl[1]);
3451
3452 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 3453 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 3454 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3455 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3456 (1 - i));
3457 b43_phy_set(dev, afectl_core, 0x0006);
3458 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3459
3460 band = b43_current_band(dev->wl);
3461
3462 if (nphy->rxcalparams & 0xFF000000) {
3463 if (band == IEEE80211_BAND_5GHZ)
3464 b43_phy_write(dev, rfctl[0], 0x140);
3465 else
3466 b43_phy_write(dev, rfctl[0], 0x110);
3467 } else {
3468 if (band == IEEE80211_BAND_5GHZ)
3469 b43_phy_write(dev, rfctl[0], 0x180);
3470 else
3471 b43_phy_write(dev, rfctl[0], 0x120);
3472 }
3473
3474 if (band == IEEE80211_BAND_5GHZ)
3475 b43_phy_write(dev, rfctl[1], 0x148);
3476 else
3477 b43_phy_write(dev, rfctl[1], 0x114);
3478
3479 if (nphy->rxcalparams & 0x10000) {
3480 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3481 (i + 1));
3482 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3483 (2 - i));
3484 }
3485
30115c22 3486 for (j = 0; j < 4; j++) {
15931e31
RM		 3487 if (j < 3) {
3488 cur_lna = lna[j];
3489 cur_hpf1 = hpf1[j];
3490 cur_hpf2 = hpf2[j];
3491 } else {
3492 if (power[1] > 10000) {
3493 use = 1;
3494 cur_hpf = cur_hpf1;
3495 index = 2;
3496 } else {
3497 if (power[0] > 10000) {
3498 use = 1;
3499 cur_hpf = cur_hpf1;
3500 index = 1;
3501 } else {
3502 index = 0;
3503 use = 2;
3504 cur_hpf = cur_hpf2;
3505 }
3506 }
3507 cur_lna = lna[index];
3508 cur_hpf1 = hpf1[index];
3509 cur_hpf2 = hpf2[index];
3510 cur_hpf += desired - hweight32(power[index]);
3511 cur_hpf = clamp_val(cur_hpf, 0, 10);
3512 if (use == 1)
3513 cur_hpf1 = cur_hpf;
3514 else
3515 cur_hpf2 = cur_hpf;
3516 }
3517
3518 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3519 (cur_lna << 2));
75377b24
RM		 3520 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3521 false);
de9a47f9 3522 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3523 b43_nphy_stop_playback(dev);
15931e31
RM		 3524
3525 if (playtone) {
59af099b
RM		 3526 ret = b43_nphy_tx_tone(dev, 4000,
3527 (nphy->rxcalparams & 0xFFFF),
3528 false, false);
15931e31
RM		 3529 playtone = false;
3530 } else {
10a79873
RM		 3531 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3532 false, false);
15931e31
RM		 3533 }
3534
3535 if (ret == 0) {
3536 if (j < 3) {
3537 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3538 false);
3539 if (i == 0) {
3540 real = est.i0_pwr;
3541 imag = est.q0_pwr;
3542 } else {
3543 real = est.i1_pwr;
3544 imag = est.q1_pwr;
3545 }
3546 power[i] = ((real + imag) / 1024) + 1;
3547 } else {
3548 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3549 }
53ae8e8c 3550 b43_nphy_stop_playback(dev);
15931e31
RM		 3551 }
3552
3553 if (ret != 0)
3554 break;
3555 }
3556
3557 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3558 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3559 b43_phy_write(dev, rfctl[1], tmp[5]);
3560 b43_phy_write(dev, rfctl[0], tmp[4]);
3561 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3562 b43_phy_write(dev, afectl_core, tmp[2]);
3563 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3564
3565 if (ret != 0)
3566 break;
3567 }
3568
75377b24 3569 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3570 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3571 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3572
3573 b43_nphy_stay_in_carrier_search(dev, 0);
3574
3575 return ret;
3576}
3577
3578static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3579 struct nphy_txgains target, u8 type, bool debug)
3580{
3581 return -1;
3582}
3583
3584/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3585static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3586 struct nphy_txgains target, u8 type, bool debug)
3587{
3588 if (dev->phy.rev >= 3)
3589 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3590 else
3591 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3592}
3593
4e687b22
GS		 3594/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3595static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3596{
3597 struct b43_phy *phy = &dev->phy;
3598 struct b43_phy_n *nphy = phy->n;
0b81c23d 3599 /* u16 buf[16]; it's rev3+ */
4e687b22 3600
049fbfee
RM		 3601 nphy->phyrxchain = mask;
3602
4e687b22
GS		 3603 if (0 /* FIXME clk */)
3604 return;
3605
3606 b43_mac_suspend(dev);
3607
3608 if (nphy->hang_avoid)
3609 b43_nphy_stay_in_carrier_search(dev, true);
3610
3611 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3612 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3613
049fbfee 3614 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 3615 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3616 if (dev->phy.rev >= 3) {
3617 /* TODO */
3618 }
3619 } else {
3620 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3621 if (dev->phy.rev >= 3) {
3622 /* TODO */
3623 }
3624 }
3625
3626 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3627
3628 if (nphy->hang_avoid)
3629 b43_nphy_stay_in_carrier_search(dev, false);
3630
3631 b43_mac_enable(dev);
3632}
3633
0988a7a1
RM		 3634/*
3635 * Init N-PHY
3636 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3637 */
424047e6
MB		 3638int b43_phy_initn(struct b43_wldev *dev)
3639{
0581483a 3640 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 3641 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3642 struct b43_phy_n *nphy = phy->n;
3643 u8 tx_pwr_state;
3644 struct nphy_txgains target;
95b66bad 3645 u16 tmp;
0988a7a1
RM		 3646 enum ieee80211_band tmp2;
3647 bool do_rssi_cal;
3648
3649 u16 clip[2];
3650 bool do_cal = false;
95b66bad 3651
0988a7a1 3652 if ((dev->phy.rev >= 3) &&
0581483a 3653 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 3654 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 3655 switch (dev->dev->bus_type) {
42c9a458
RM		 3656#ifdef CONFIG_B43_BCMA
3657 case B43_BUS_BCMA:
3658 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3659 BCMA_CC_CHIPCTL, 0x40);
3660 break;
3661#endif
6cbab0d9
RM		 3662#ifdef CONFIG_B43_SSB
3663 case B43_BUS_SSB:
3664 chipco_set32(&dev->dev->sdev->bus->chipco,
3665 SSB_CHIPCO_CHIPCTL, 0x40);
3666 break;
3667#endif
3668 }
0988a7a1
RM		 3669 }
3670 nphy->deaf_count = 0;
95b66bad 3671 b43_nphy_tables_init(dev);
0988a7a1
RM		 3672 nphy->crsminpwr_adjusted = false;
3673 nphy->noisevars_adjusted = false;
95b66bad
MB		 3674
3675 /* Clear all overrides */
0988a7a1
RM		 3676 if (dev->phy.rev >= 3) {
3677 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3678 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3679 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3680 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3681 } else {
3682 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3683 }
95b66bad
MB		 3684 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3685 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3686 if (dev->phy.rev < 6) {
3687 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3688 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3689 }
95b66bad
MB		 3690 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3691 ~(B43_NPHY_RFSEQMODE_CAOVER |
3692 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3693 if (dev->phy.rev >= 3)
3694 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3695 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3696
0988a7a1
RM		 3697 if (dev->phy.rev <= 2) {
3698 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3699 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3700 ~B43_NPHY_BPHY_CTL3_SCALE,
3701 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3702 }
95b66bad
MB		 3703 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3704 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3705
0581483a 3706 if (sprom->boardflags2_lo & 0x100 ||
79d2232f
RM		 3707 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3708 dev->dev->board_type == 0x8B))
0988a7a1
RM		 3709 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3710 else
3711 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3712 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3713 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3714 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3715
ad9716e8 3716 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3717 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3718
3719 if (phy->rev < 2) {
3720 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3721 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3722 }
0988a7a1
RM		 3723
3724 tmp2 = b43_current_band(dev->wl);
c002831a 3725 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 3726 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3727 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3728 nphy->papd_epsilon_offset[0] << 7);
3729 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3730 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3731 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3732 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3733 } else if (phy->rev >= 5) {
45ca697e 3734 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3735 }
3736
95b66bad 3737 b43_nphy_workarounds(dev);
95b66bad 3738
0988a7a1 3739 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 3740 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 3741 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3742 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3743 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 3744 b43_phy_force_clock(dev, 0);
0988a7a1 3745
858a1652 3746 b43_mac_phy_clock_set(dev, true);
0988a7a1 3747
e50cbcf6 3748 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3749 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3750 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3751 b43_nphy_pa_override(dev, true);
0988a7a1 3752
bbec398c
RM		 3753 b43_nphy_classifier(dev, 0, 0);
3754 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 3755 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3756 b43_nphy_bphy_init(dev);
3757
0988a7a1 3758 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 3759 b43_nphy_tx_power_ctrl(dev, false);
3760 b43_nphy_tx_power_fix(dev);
0988a7a1
RM		 3761 /* TODO N PHY TX Power Control Idle TSSI */
3762 /* TODO N PHY TX Power Control Setup */
3763
3764 if (phy->rev >= 3) {
3765 /* TODO */
3766 } else {
2581b143
RM		 3767 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3768 b43_ntab_tx_gain_rev0_1_2);
3769 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3770 b43_ntab_tx_gain_rev0_1_2);
0988a7a1 3771 }
95b66bad 3772
0988a7a1 3773 if (nphy->phyrxchain != 3)
4e687b22 3774 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 3775 if (nphy->mphase_cal_phase_id > 0)
3776 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3777
3778 do_rssi_cal = false;
3779 if (phy->rev >= 3) {
3780 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3781 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 3782 else
204a665b 3783 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 3784
3785 if (do_rssi_cal)
4cb99775 3786 b43_nphy_rssi_cal(dev);
0988a7a1 3787 else
42e1547e 3788 b43_nphy_restore_rssi_cal(dev);
0988a7a1 3789 } else {
4cb99775 3790 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3791 }
3792
3793 if (!((nphy->measure_hold & 0x6) != 0)) {
3794 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3795 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 3796 else
204a665b 3797 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 3798
3799 if (nphy->mute)
3800 do_cal = false;
3801
3802 if (do_cal) {
b0022e15 3803 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 3804
3805 if (nphy->antsel_type == 2)
8987a9e9 3806 b43_nphy_superswitch_init(dev, true);
0988a7a1 3807 if (nphy->perical != 2) {
90b9738d 3808 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3809 if (phy->rev >= 3) {
3810 nphy->cal_orig_pwr_idx[0] =
3811 nphy->txpwrindex[0].index_internal;
3812 nphy->cal_orig_pwr_idx[1] =
3813 nphy->txpwrindex[1].index_internal;
3814 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 3815 target = b43_nphy_get_tx_gains(dev);
0988a7a1 3816 }
e7797bf2
RM		 3817 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3818 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3819 b43_nphy_save_cal(dev);
3820 } else if (nphy->mphase_cal_phase_id == 0)
3821 ;/* N PHY Periodic Calibration with arg 3 */
3822 } else {
3823 b43_nphy_restore_cal(dev);
0988a7a1
RM		 3824 }
3825 }
3826
6dcd9d91 3827 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 3828 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 3829 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3830 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3831 if (phy->rev >= 3 && phy->rev <= 6)
3832 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 3833 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 3834 if (phy->rev >= 3)
3835 b43_nphy_spur_workaround(dev);
95b66bad 3836
53a6e234 3837 return 0;
424047e6 3838}
ef1a628d 3839
1b69ec7b 3840/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 3841static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 3842 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 3843 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 3844{
3845 struct b43_phy *phy = &dev->phy;
3846 struct b43_phy_n *nphy = dev->phy.n;
3847
087de74a 3848 u16 old_band_5ghz;
1b69ec7b
RM		 3849 u32 tmp32;
3850
087de74a
RM		 3851 old_band_5ghz =
3852 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3853 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 3854 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3855 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3856 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3857 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3858 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 3859 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 3860 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3861 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3862 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 3863 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 3864 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3865 }
3866
3867 b43_chantab_phy_upload(dev, e);
3868
a656b6a9 3869 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 3870 b43_nphy_classifier(dev, 2, 0);
3871 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3872 } else {
3873 b43_nphy_classifier(dev, 2, 2);
a656b6a9 3874 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 3875 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3876 }
3877
161d540c 3878 if (!nphy->txpwrctrl)
1b69ec7b
RM		 3879 b43_nphy_tx_power_fix(dev);
3880
3881 if (dev->phy.rev < 3)
3882 b43_nphy_adjust_lna_gain_table(dev);
3883
3884 b43_nphy_tx_lp_fbw(dev);
3885
3886 if (dev->phy.rev >= 3 && 0) {
3887 /* TODO */
3888 }
3889
3890 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3891
3892 if (phy->rev >= 3)
3893 b43_nphy_spur_workaround(dev);
3894}
3895
eff66c51 3896/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 3897static int b43_nphy_set_channel(struct b43_wldev *dev,
3898 struct ieee80211_channel *channel,
3899 enum nl80211_channel_type channel_type)
eff66c51 3900{
a656b6a9 3901 struct b43_phy *phy = &dev->phy;
eff66c51 3902
2eeb6fd0
JL		 3903 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3904 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 3905
3906 u8 tmp;
eff66c51
RM		 3907
3908 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 3909 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3910 channel->center_freq);
f19ebe7d
RM		 3911 if (!tabent_r3)
3912 return -ESRCH;
ffd2d9bd 3913 } else {
a656b6a9
RM		 3914 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3915 channel->hw_value);
f19ebe7d 3916 if (!tabent_r2)
ffd2d9bd 3917 return -ESRCH;
eff66c51
RM		 3918 }
3919
204a665b
RM		 3920 /* Channel is set later in common code, but we need to set it on our
3921 own to let this function's subcalls work properly. */
3922 phy->channel = channel->hw_value;
3923 phy->channel_freq = channel->center_freq;
eff66c51 3924
e5c407f9
RM		 3925 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3926 b43_channel_type_is_40mhz(channel_type))
3927 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 3928
a656b6a9
RM		 3929 if (channel_type == NL80211_CHAN_HT40PLUS)
3930 b43_phy_set(dev, B43_NPHY_RXCTL,
3931 B43_NPHY_RXCTL_BSELU20);
3932 else if (channel_type == NL80211_CHAN_HT40MINUS)
3933 b43_phy_mask(dev, B43_NPHY_RXCTL,
3934 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 3935
3936 if (dev->phy.rev >= 3) {
a656b6a9 3937 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 3938 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 3939 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 3940 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 3941 } else {
a656b6a9 3942 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 3943 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 3944 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 3945 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 3946 }
3947
3948 return 0;
3949}
3950
ef1a628d
MB		 3951static int b43_nphy_op_allocate(struct b43_wldev *dev)
3952{
3953 struct b43_phy_n *nphy;
3954
3955 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3956 if (!nphy)
3957 return -ENOMEM;
3958 dev->phy.n = nphy;
3959
ef1a628d
MB		 3960 return 0;
3961}
3962
fb11137a 3963static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 3964{
fb11137a
MB		 3965 struct b43_phy *phy = &dev->phy;
3966 struct b43_phy_n *nphy = phy->n;
ef1a628d 3967
fb11137a 3968 memset(nphy, 0, sizeof(*nphy));
ef1a628d 3969
aca434d3 3970 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
0b81c23d
RM		 3971 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3972 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3973 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 3974 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 3975 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
3976 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
3977 nphy->tx_pwr_idx[0] = 128;
3978 nphy->tx_pwr_idx[1] = 128;
ef1a628d
MB		 3979}
3980
fb11137a 3981static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 3982{
fb11137a
MB		 3983 struct b43_phy *phy = &dev->phy;
3984 struct b43_phy_n *nphy = phy->n;
ef1a628d 3985
ef1a628d 3986 kfree(nphy);
fb11137a
MB		 3987 phy->n = NULL;
3988}
3989
3990static int b43_nphy_op_init(struct b43_wldev *dev)
3991{
3992 return b43_phy_initn(dev);
ef1a628d
MB		 3993}
3994
3995static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3996{
3997#if B43_DEBUG
3998 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3999 /* OFDM registers are onnly available on A/G-PHYs */
4000 b43err(dev->wl, "Invalid OFDM PHY access at "
4001 "0x%04X on N-PHY\n", offset);
4002 dump_stack();
4003 }
4004 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4005 /* Ext-G registers are only available on G-PHYs */
4006 b43err(dev->wl, "Invalid EXT-G PHY access at "
4007 "0x%04X on N-PHY\n", offset);
4008 dump_stack();
4009 }
4010#endif /* B43_DEBUG */
4011}
4012
4013static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4014{
4015 check_phyreg(dev, reg);
4016 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4017 return b43_read16(dev, B43_MMIO_PHY_DATA);
4018}
4019
4020static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4021{
4022 check_phyreg(dev, reg);
4023 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4024 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4025}
4026
755fd183
RM		 4027static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4028 u16 set)
4029{
4030 check_phyreg(dev, reg);
4031 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4032 b43_write16(dev, B43_MMIO_PHY_DATA,
4033 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4034}
4035
ef1a628d
MB		 4036static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4037{
4038 /* Register 1 is a 32-bit register. */
4039 B43_WARN_ON(reg == 1);
4040 /* N-PHY needs 0x100 for read access */
4041 reg |= 0x100;
4042
4043 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4044 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4045}
4046
4047static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4048{
4049 /* Register 1 is a 32-bit register. */
4050 B43_WARN_ON(reg == 1);
4051
4052 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4053 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4054}
4055
c2b7aefd 4056/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 4057static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 4058 bool blocked)
c2b7aefd
RM		 4059{
4060 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4061 b43err(dev->wl, "MAC not suspended\n");
4062
4063 if (blocked) {
4064 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4065 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4066 if (dev->phy.rev >= 3) {
4067 b43_radio_mask(dev, 0x09, ~0x2);
4068
4069 b43_radio_write(dev, 0x204D, 0);
4070 b43_radio_write(dev, 0x2053, 0);
4071 b43_radio_write(dev, 0x2058, 0);
4072 b43_radio_write(dev, 0x205E, 0);
4073 b43_radio_mask(dev, 0x2062, ~0xF0);
4074 b43_radio_write(dev, 0x2064, 0);
4075
4076 b43_radio_write(dev, 0x304D, 0);
4077 b43_radio_write(dev, 0x3053, 0);
4078 b43_radio_write(dev, 0x3058, 0);
4079 b43_radio_write(dev, 0x305E, 0);
4080 b43_radio_mask(dev, 0x3062, ~0xF0);
4081 b43_radio_write(dev, 0x3064, 0);
4082 }
4083 } else {
4084 if (dev->phy.rev >= 3) {
d817f4e1 4085 b43_radio_init2056(dev);
78159788 4086 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 4087 } else {
4088 b43_radio_init2055(dev);
4089 }
4090 }
ef1a628d
MB		 4091}
4092
0f4091b9 4093/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 4094static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4095{
2a870831
RM		 4096 u16 override = on ? 0x0 : 0x7FFF;
4097 u16 core = on ? 0xD : 0x00FD;
0f4091b9 4098
2a870831
RM		 4099 if (dev->phy.rev >= 3) {
4100 if (on) {
4101 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4102 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4103 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4104 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4105 } else {
4106 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4107 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4108 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4109 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4110 }
4111 } else {
4112 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4113 }
cb24f57f
MB		 4114}
4115
ef1a628d
MB		 4116static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4117 unsigned int new_channel)
4118{
a656b6a9
RM		 4119 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4120 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 4121
ef1a628d
MB		 4122 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4123 if ((new_channel < 1) || (new_channel > 14))
4124 return -EINVAL;
4125 } else {
4126 if (new_channel > 200)
4127 return -EINVAL;
4128 }
4129
a656b6a9 4130 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 4131}
4132
4133static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4134{
4135 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4136 return 1;
4137 return 36;
4138}
4139
ef1a628d
MB		 4140const struct b43_phy_operations b43_phyops_n = {
4141 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 4142 .free = b43_nphy_op_free,
4143 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 4144 .init = b43_nphy_op_init,
ef1a628d
MB		 4145 .phy_read = b43_nphy_op_read,
4146 .phy_write = b43_nphy_op_write,
755fd183 4147 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 4148 .radio_read = b43_nphy_op_radio_read,
4149 .radio_write = b43_nphy_op_radio_write,
4150 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 4151 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 4152 .switch_channel = b43_nphy_op_switch_channel,
4153 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 4154 .recalc_txpower = b43_nphy_op_recalc_txpower,
4155 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 4156};
Linux kernel - Deliverables
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