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ath5k: Fix AR5K_PHY_TXPOWER_RATE_MAX register value setting.
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
4256ba77
RM		 260static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
263{
264 u16 reg, tmp, tmp2, val;
265 int core;
266
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
270 continue;
271
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
273
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
278 break;
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
282
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
286 break;
287 case N_INTC_OVERRIDE_PA:
288 tmp = 0x0030;
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
290 val = value << 5;
291 else
292 val = value << 4;
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
295 break;
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
298 tmp = 0x0001;
299 tmp2 = 0x0004;
300 val = value;
301 } else {
302 tmp = 0x0004;
303 tmp2 = 0x0001;
304 val = value << 2;
305 }
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
308 break;
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
311 tmp = 0x0002;
312 tmp2 = 0x0008;
313 val = value << 1;
314 } else {
315 tmp = 0x0008;
316 tmp2 = 0x0002;
317 val = value << 3;
318 }
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
321 break;
322 }
323 }
324}
325
ab499217 326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 327static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core)
d4814e69 330{
ab499217
RM		 331 u8 i, j;
332 u16 reg, tmp, val;
38646eba 333
4256ba77
RM		 334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
336 core);
337 return;
338 }
339
d4814e69
RM		 340 B43_WARN_ON(dev->phy.rev < 3);
341
ab499217
RM		 342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
344 continue;
38646eba 345
ab499217
RM		 346 reg = (i == 0) ?
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 348 b43_phy_set(dev, reg, 0x400);
38646eba 349
89e43dad
RM		 350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
354 break;
89e43dad 355 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 356 if (!i) {
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
360 0xFFFE, 1);
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
603431e9 364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 365 j = 0;
366 break;
367 }
368 udelay(10);
38646eba 369 }
ab499217
RM		 370 if (j)
371 b43err(dev->wl,
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
374 0xFFFE);
38646eba 375 } else {
ab499217
RM		 376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
379 0xFFFE, 1);
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
603431e9 383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 384 j = 0;
385 break;
386 }
387 udelay(10);
388 }
389 if (j)
390 b43err(dev->wl,
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
393 0xFFFE);
38646eba 394 }
ab499217 395 break;
89e43dad 396 case N_INTC_OVERRIDE_PA:
ab499217
RM		 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
398 tmp = 0x0020;
399 val = value << 5;
400 } else {
401 tmp = 0x0010;
402 val = value << 4;
403 }
404 b43_phy_maskset(dev, reg, ~tmp, val);
405 break;
89e43dad 406 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
408 tmp = 0x0001;
409 val = value;
410 } else {
411 tmp = 0x0004;
412 val = value << 2;
413 }
414 b43_phy_maskset(dev, reg, ~tmp, val);
415 break;
89e43dad 416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
418 tmp = 0x0002;
419 val = value << 1;
420 } else {
421 tmp = 0x0008;
422 val = value << 3;
423 }
424 b43_phy_maskset(dev, reg, ~tmp, val);
425 break;
38646eba 426 }
38646eba 427 }
ab499217 428}
38646eba 429
ab499217
RM		 430/**************************************************
431 * Various PHY ops
432 **************************************************/
433
434/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
436 const u16 *clip_st)
437{
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 440}
441
ab499217
RM		 442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 444{
ab499217
RM		 445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 447}
448
ab499217
RM		 449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 451{
ab499217 452 u16 tmp;
161d540c 453
ab499217
RM		 454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
161d540c 456
ab499217
RM		 457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
460 tmp &= ~mask;
461 tmp |= (val & mask);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 463
ab499217
RM		 464 if (dev->dev->core_rev == 16)
465 b43_mac_enable(dev);
161d540c 466
ab499217
RM		 467 return tmp;
468}
161d540c 469
ab499217
RM		 470/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471static void b43_nphy_reset_cca(struct b43_wldev *dev)
472{
473 u16 bbcfg;
161d540c 474
ab499217
RM		 475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
478 udelay(1);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
482}
161d540c 483
ab499217
RM		 484/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
486{
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
161d540c 489
ab499217
RM		 490 if (enable) {
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
498 }
499 b43_nphy_reset_cca(dev);
161d540c 500 } else {
ab499217
RM		 501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 504 }
161d540c 505 }
161d540c
RM		 506}
507
64712095
RM		 508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 510{
161d540c 511 struct b43_phy_n *nphy = dev->phy.n;
161d540c 512
64712095
RM		 513 u8 i;
514 s16 tmp;
515 u16 data[4];
516 s16 gain[2];
517 u16 minmax[2];
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 519
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
522
64712095 523 if (nphy->gain_boost) {
161d540c 524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 525 gain[0] = 6;
526 gain[1] = 6;
161d540c 527 } else {
64712095
RM		 528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 532 }
64712095
RM		 533 } else {
534 gain[0] = 0;
535 gain[1] = 0;
161d540c 536 }
161d540c
RM		 537
538 for (i = 0; i < 2; i++) {
64712095
RM		 539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
161d540c 544 } else {
64712095
RM		 545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
161d540c 549 }
64712095 550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 551
64712095 552 minmax[i] = 23 + gain[i];
161d540c
RM		 553 }
554
64712095
RM		 555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 559
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 562}
563
ab499217
RM		 564/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
0eff8fcd 567{
ab499217
RM		 568 struct b43_phy_n *nphy = dev->phy.n;
569 u8 i;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
0eff8fcd 573
ab499217
RM		 574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 576
ab499217
RM		 577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 579
ab499217
RM		 580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 583 }
ab499217
RM		 584
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 587}
7955de0c 588
572d37a4
RM		 589/**************************************************
590 * Radio 0x2057
591 **************************************************/
592
593/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
594static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
595{
596 struct b43_phy *phy = &dev->phy;
597 u16 tmp;
598
599 if (phy->radio_rev == 5) {
600 b43_phy_mask(dev, 0x342, ~0x2);
601 udelay(10);
602 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
603 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
604 }
605
606 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
607 udelay(10);
608 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
609 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
610 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
611 return 0;
612 }
613 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
614 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
615 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
616
617 if (phy->radio_rev == 5) {
618 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
619 b43_radio_mask(dev, 0x1ca, ~0x2);
620 }
621 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
622 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
623 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
624 tmp << 2);
625 }
626
627 return tmp & 0x3e;
628}
629
630/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
631static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
632{
633 struct b43_phy *phy = &dev->phy;
634 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
635 phy->radio_rev == 6);
636 u16 tmp;
637
638 if (special) {
639 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
640 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
641 } else {
642 b43_radio_write(dev, 0x1AE, 0x61);
643 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
644 }
645 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
646 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
647 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
648 5000000))
649 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
650 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
651 if (special) {
652 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
653 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
654 } else {
655 b43_radio_write(dev, 0x1AE, 0x69);
656 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
657 }
658 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
659 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
660 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
661 5000000))
6c187236 662 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 663 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
664 if (special) {
665 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
666 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
667 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
668 } else {
669 b43_radio_write(dev, 0x1AE, 0x73);
670 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
671 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
672 }
673 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
674 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
675 5000000)) {
676 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
677 return 0;
678 }
679 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
680 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
681 return tmp;
682}
683
684static void b43_radio_2057_init_pre(struct b43_wldev *dev)
685{
686 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
687 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
688 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
689 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
690 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
691}
692
693static void b43_radio_2057_init_post(struct b43_wldev *dev)
694{
695 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
696
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
698 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
699 mdelay(2);
700 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
701 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
702
703 if (dev->phy.n->init_por) {
704 b43_radio_2057_rcal(dev);
705 b43_radio_2057_rccal(dev);
706 }
707 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
708
709 dev->phy.n->init_por = false;
710}
711
712/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
713static void b43_radio_2057_init(struct b43_wldev *dev)
714{
715 b43_radio_2057_init_pre(dev);
716 r2057_upload_inittabs(dev);
717 b43_radio_2057_init_post(dev);
718}
719
ab499217 720/**************************************************
884a5228 721 * Radio 0x2056
ab499217 722 **************************************************/
7955de0c 723
d4814e69
RM		 724static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
725 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 726{
d4814e69
RM		 727 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
728 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
729 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
730 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
731 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
732 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
733 e->radio_syn_pll_loopfilter1);
734 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
735 e->radio_syn_pll_loopfilter2);
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
737 e->radio_syn_pll_loopfilter3);
738 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
739 e->radio_syn_pll_loopfilter4);
740 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
741 e->radio_syn_pll_loopfilter5);
742 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
743 e->radio_syn_reserved_addr27);
744 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
745 e->radio_syn_reserved_addr28);
746 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
747 e->radio_syn_reserved_addr29);
748 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
749 e->radio_syn_logen_vcobuf1);
750 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
751 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
752 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
753
754 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
755 e->radio_rx0_lnaa_tune);
756 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
757 e->radio_rx0_lnag_tune);
758
759 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
760 e->radio_tx0_intpaa_boost_tune);
761 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
762 e->radio_tx0_intpag_boost_tune);
763 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
764 e->radio_tx0_pada_boost_tune);
765 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
766 e->radio_tx0_padg_boost_tune);
767 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
768 e->radio_tx0_pgaa_boost_tune);
769 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
770 e->radio_tx0_pgag_boost_tune);
771 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
772 e->radio_tx0_mixa_boost_tune);
773 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
774 e->radio_tx0_mixg_boost_tune);
775
776 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
777 e->radio_rx1_lnaa_tune);
778 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
779 e->radio_rx1_lnag_tune);
780
781 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
782 e->radio_tx1_intpaa_boost_tune);
783 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
784 e->radio_tx1_intpag_boost_tune);
785 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
786 e->radio_tx1_pada_boost_tune);
787 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
788 e->radio_tx1_padg_boost_tune);
789 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
790 e->radio_tx1_pgaa_boost_tune);
791 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
792 e->radio_tx1_pgag_boost_tune);
793 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
794 e->radio_tx1_mixa_boost_tune);
795 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
796 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 797}
798
d4814e69
RM		 799/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
800static void b43_radio_2056_setup(struct b43_wldev *dev,
801 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 802{
0581483a 803 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 804 enum ieee80211_band band = b43_current_band(dev->wl);
805 u16 offset;
806 u8 i;
d3d178f0
RM		 807 u16 bias, cbias;
808 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
809 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
036cafe4 810
d4814e69 811 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 812
d4814e69 813 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 814 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
815
816 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
817 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
818 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
819 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
820 if (dev->dev->chip_id == 0x4716) {
821 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
822 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
823 } else {
824 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
825 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 826 }
53a6e234 827 }
38646eba
RM		 828 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
829 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
830 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
831 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
832 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
833 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 834 }
53a6e234 835
38646eba
RM		 836 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
837 for (i = 0; i < 2; i++) {
838 offset = i ? B2056_TX1 : B2056_TX0;
839 if (dev->phy.rev >= 5) {
840 b43_radio_write(dev,
841 offset | B2056_TX_PADG_IDAC, 0xcc);
842
843 if (dev->dev->chip_id == 0x4716) {
844 bias = 0x40;
845 cbias = 0x45;
846 pag_boost = 0x5;
847 pgag_boost = 0x33;
848 mixg_boost = 0x55;
849 } else {
850 bias = 0x25;
851 cbias = 0x20;
852 pag_boost = 0x4;
853 pgag_boost = 0x03;
854 mixg_boost = 0x65;
855 }
856 padg_boost = 0x77;
857
858 b43_radio_write(dev,
859 offset | B2056_TX_INTPAG_IMAIN_STAT,
860 bias);
861 b43_radio_write(dev,
862 offset | B2056_TX_INTPAG_IAUX_STAT,
863 bias);
864 b43_radio_write(dev,
865 offset | B2056_TX_INTPAG_CASCBIAS,
866 cbias);
867 b43_radio_write(dev,
868 offset | B2056_TX_INTPAG_BOOST_TUNE,
869 pag_boost);
870 b43_radio_write(dev,
871 offset | B2056_TX_PGAG_BOOST_TUNE,
872 pgag_boost);
873 b43_radio_write(dev,
874 offset | B2056_TX_PADG_BOOST_TUNE,
875 padg_boost);
876 b43_radio_write(dev,
877 offset | B2056_TX_MIXG_BOOST_TUNE,
878 mixg_boost);
879 } else {
880 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
881 b43_radio_write(dev,
882 offset | B2056_TX_INTPAG_IMAIN_STAT,
883 bias);
884 b43_radio_write(dev,
885 offset | B2056_TX_INTPAG_IAUX_STAT,
886 bias);
887 b43_radio_write(dev,
888 offset | B2056_TX_INTPAG_CASCBIAS,
889 0x30);
890 }
891 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
892 }
893 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 894 u16 freq = dev->phy.channel_freq;
895 if (freq < 5100) {
896 paa_boost = 0xA;
897 pada_boost = 0x77;
898 pgaa_boost = 0xF;
899 mixa_boost = 0xF;
900 } else if (freq < 5340) {
901 paa_boost = 0x8;
902 pada_boost = 0x77;
903 pgaa_boost = 0xFB;
904 mixa_boost = 0xF;
905 } else if (freq < 5650) {
906 paa_boost = 0x0;
907 pada_boost = 0x77;
908 pgaa_boost = 0xB;
909 mixa_boost = 0xF;
910 } else {
911 paa_boost = 0x0;
912 pada_boost = 0x77;
913 if (freq != 5825)
914 pgaa_boost = -(freq - 18) / 36 + 168;
915 else
916 pgaa_boost = 6;
917 mixa_boost = 0xF;
918 }
919
920 for (i = 0; i < 2; i++) {
921 offset = i ? B2056_TX1 : B2056_TX0;
922
923 b43_radio_write(dev,
924 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
925 b43_radio_write(dev,
926 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
927 b43_radio_write(dev,
928 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
929 b43_radio_write(dev,
930 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
931 b43_radio_write(dev,
932 offset | B2056_TX_TXSPARE1, 0x30);
933 b43_radio_write(dev,
934 offset | B2056_TX_PA_SPARE2, 0xee);
935 b43_radio_write(dev,
936 offset | B2056_TX_PADA_CASCBIAS, 0x03);
937 b43_radio_write(dev,
938 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
939 b43_radio_write(dev,
940 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
941 b43_radio_write(dev,
942 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
943 }
a2d9bc6f 944 }
38646eba 945
d4814e69
RM		 946 udelay(50);
947 /* VCO calibration */
948 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
949 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
950 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
951 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
952 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
953 udelay(300);
53a6e234
MB		 954}
955
d3d178f0
RM		 956static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
957{
958 struct b43_phy *phy = &dev->phy;
959 u16 mast2, tmp;
960
961 if (phy->rev != 3)
962 return 0;
963
964 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
965 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
966
967 udelay(10);
968 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
969 udelay(10);
970 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
971
972 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
973 1000000)) {
974 b43err(dev->wl, "Radio recalibration timeout\n");
975 return 0;
976 }
977
978 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
979 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
980 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
981
982 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
983
984 return tmp & 0x1f;
985}
986
ea7ee14b
RM		 987static void b43_radio_init2056_pre(struct b43_wldev *dev)
988{
989 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
990 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
991 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
992 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
993 B43_NPHY_RFCTL_CMD_OEPORFORCE);
994 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
995 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
996 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
997 B43_NPHY_RFCTL_CMD_CHIP0PU);
998}
999
1000static void b43_radio_init2056_post(struct b43_wldev *dev)
1001{
1002 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1003 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1004 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1005 msleep(1);
1006 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1007 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1008 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 1009 if (dev->phy.n->init_por)
1010 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1011}
1012
d817f4e1
RM		 1013/*
1014 * Initialize a Broadcom 2056 N-radio
1015 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1016 */
1017static void b43_radio_init2056(struct b43_wldev *dev)
1018{
ea7ee14b
RM		 1019 b43_radio_init2056_pre(dev);
1020 b2056_upload_inittabs(dev, 0, 0);
1021 b43_radio_init2056_post(dev);
d3d178f0
RM		 1022
1023 dev->phy.n->init_por = false;
d817f4e1
RM		 1024}
1025
884a5228
RM		 1026/**************************************************
1027 * Radio 0x2055
1028 **************************************************/
1029
1030static void b43_chantab_radio_upload(struct b43_wldev *dev,
1031 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1032{
884a5228
RM		 1033 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1034 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1035 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1036 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1037 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1038
884a5228
RM		 1039 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1040 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1041 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1042 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1043 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1044
884a5228
RM		 1045 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1046 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1047 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1048 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1049 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1050
884a5228
RM		 1051 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1052 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1053 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1054 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1055 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1056
884a5228
RM		 1057 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1058 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1059 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1060 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1061 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1062
884a5228
RM		 1063 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1064 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1065}
1066
884a5228
RM		 1067/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1068static void b43_radio_2055_setup(struct b43_wldev *dev,
1069 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1070{
884a5228 1071 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1072
884a5228
RM		 1073 b43_chantab_radio_upload(dev, e);
1074 udelay(50);
1075 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1076 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1077 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1078 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1079 udelay(300);
95b66bad
MB		 1080}
1081
884a5228 1082static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1083{
884a5228
RM		 1084 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1085 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1086 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1087 B43_NPHY_RFCTL_CMD_CHIP0PU |
1088 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1089 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1090 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1091}
1092
884a5228 1093static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1094{
1095 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1096 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1097 bool workaround = false;
2faa6b83 1098
884a5228
RM		 1099 if (sprom->revision < 4)
1100 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1101 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1102 && dev->dev->board_rev >= 0x41);
2faa6b83 1103 else
884a5228
RM		 1104 workaround =
1105 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1106
884a5228
RM		 1107 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1108 if (workaround) {
1109 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1110 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1111 }
1112 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1113 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1114 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1115 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1116 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1117 msleep(1);
1118 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1119 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1120 b43err(dev->wl, "radio post init timeout\n");
1121 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1122 b43_switch_channel(dev, dev->phy.channel);
1123 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1124 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1125 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1126 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1127 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1128 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1129 if (!nphy->gain_boost) {
1130 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1131 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1132 } else {
1133 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1134 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1135 }
1136 udelay(2);
2faa6b83
RM		 1137}
1138
884a5228
RM		 1139/*
1140 * Initialize a Broadcom 2055 N-radio
1141 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1142 */
1143static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1144{
884a5228
RM		 1145 b43_radio_init2055_pre(dev);
1146 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1147 /* Follow wl, not specs. Do not force uploading all regs */
1148 b2055_upload_inittab(dev, 0, 0);
a67162ab 1149 } else {
884a5228
RM		 1150 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1151 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1152 }
884a5228 1153 b43_radio_init2055_post(dev);
a67162ab
RM		 1154}
1155
8be89535
RM		 1156/**************************************************
1157 * Samples
1158 **************************************************/
026816fc 1159
8be89535
RM		 1160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1161static int b43_nphy_load_samples(struct b43_wldev *dev,
1162 struct b43_c32 *samples, u16 len) {
1163 struct b43_phy_n *nphy = dev->phy.n;
1164 u16 i;
1165 u32 *data;
1166
1167 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1168 if (!data) {
1169 b43err(dev->wl, "allocation for samples loading failed\n");
1170 return -ENOMEM;
1171 }
1172 if (nphy->hang_avoid)
1173 b43_nphy_stay_in_carrier_search(dev, 1);
1174
1175 for (i = 0; i < len; i++) {
1176 data[i] = (samples[i].i & 0x3FF << 10);
1177 data[i] |= samples[i].q & 0x3FF;
1178 }
1179 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1180
1181 kfree(data);
1182 if (nphy->hang_avoid)
1183 b43_nphy_stay_in_carrier_search(dev, 0);
1184 return 0;
026816fc
RM		 1185}
1186
8be89535
RM		 1187/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1188static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1189 bool test)
026816fc 1190{
8be89535
RM		 1191 int i;
1192 u16 bw, len, rot, angle;
1193 struct b43_c32 *samples;
026816fc 1194
026816fc 1195
8be89535
RM		 1196 bw = (dev->phy.is_40mhz) ? 40 : 20;
1197 len = bw << 3;
026816fc 1198
8be89535
RM		 1199 if (test) {
1200 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1201 bw = 82;
1202 else
1203 bw = 80;
026816fc 1204
8be89535
RM		 1205 if (dev->phy.is_40mhz)
1206 bw <<= 1;
1207
1208 len = bw << 1;
026816fc
RM		 1209 }
1210
8be89535
RM		 1211 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1212 if (!samples) {
1213 b43err(dev->wl, "allocation for samples generation failed\n");
1214 return 0;
1215 }
1216 rot = (((freq * 36) / bw) << 16) / 100;
1217 angle = 0;
026816fc 1218
8be89535
RM		 1219 for (i = 0; i < len; i++) {
1220 samples[i] = b43_cordic(angle);
1221 angle += rot;
1222 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1223 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1224 }
8be89535
RM		 1225
1226 i = b43_nphy_load_samples(dev, samples, len);
1227 kfree(samples);
1228 return (i < 0) ? 0 : len;
026816fc
RM		 1229}
1230
8be89535
RM		 1231/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1232static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1233 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1234{
8be89535 1235 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1236 int i;
8be89535
RM		 1237 u16 seq_mode;
1238 u32 tmp;
34a56f2c 1239
bc36e994 1240 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1241
8be89535
RM		 1242 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1243 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1244 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1245 }
34a56f2c 1246
bc36e994 1247 /* TODO: add modify_bbmult argument */
8be89535
RM		 1248 if (!dev->phy.is_40mhz)
1249 tmp = 0x6464;
1250 else
1251 tmp = 0x4747;
1252 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1253
8be89535 1254 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1255
8be89535
RM		 1256 if (loops != 0xFFFF)
1257 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1258 else
1259 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1260
8be89535 1261 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1262
8be89535 1263 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1264
8be89535
RM		 1265 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1266 if (iqmode) {
1267 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1268 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1269 } else {
1270 if (dac_test)
1271 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1272 else
1273 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1274 }
1275 for (i = 0; i < 100; i++) {
2c8ac7eb 1276 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1277 i = 0;
1278 break;
34a56f2c 1279 }
8be89535 1280 udelay(10);
34a56f2c 1281 }
8be89535
RM		 1282 if (i)
1283 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1284
8be89535 1285 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1286
1287 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1288}
1289
4d9f46ba
RM		 1290/**************************************************
1291 * RSSI
1292 **************************************************/
1293
1294/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1295static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1296 s8 offset, u8 core,
1297 enum n_rail_type rail,
2a2d0589 1298 enum n_rssi_type rssi_type)
09146400 1299{
4d9f46ba
RM		 1300 u16 tmp;
1301 bool core1or5 = (core == 1) || (core == 5);
1302 bool core2or5 = (core == 2) || (core == 5);
09146400 1303
4d9f46ba
RM		 1304 offset = clamp_val(offset, -32, 31);
1305 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1306
e5ab1fd7 1307 switch (rssi_type) {
2a2d0589 1308 case N_RSSI_NB:
e5ab1fd7
RM		 1309 if (core1or5 && rail == N_RAIL_I)
1310 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1311 if (core1or5 && rail == N_RAIL_Q)
1312 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1313 if (core2or5 && rail == N_RAIL_I)
1314 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1315 if (core2or5 && rail == N_RAIL_Q)
1316 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1317 break;
2a2d0589 1318 case N_RSSI_W1:
e5ab1fd7
RM		 1319 if (core1or5 && rail == N_RAIL_I)
1320 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1321 if (core1or5 && rail == N_RAIL_Q)
1322 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1323 if (core2or5 && rail == N_RAIL_I)
1324 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1325 if (core2or5 && rail == N_RAIL_Q)
1326 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1327 break;
2a2d0589 1328 case N_RSSI_W2:
e5ab1fd7
RM		 1329 if (core1or5 && rail == N_RAIL_I)
1330 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1331 if (core1or5 && rail == N_RAIL_Q)
1332 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1333 if (core2or5 && rail == N_RAIL_I)
1334 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1335 if (core2or5 && rail == N_RAIL_Q)
1336 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1337 break;
2a2d0589 1338 case N_RSSI_TBD:
e5ab1fd7
RM		 1339 if (core1or5 && rail == N_RAIL_I)
1340 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1341 if (core1or5 && rail == N_RAIL_Q)
1342 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1343 if (core2or5 && rail == N_RAIL_I)
1344 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1345 if (core2or5 && rail == N_RAIL_Q)
1346 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1347 break;
2a2d0589 1348 case N_RSSI_IQ:
e5ab1fd7
RM		 1349 if (core1or5 && rail == N_RAIL_I)
1350 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1351 if (core1or5 && rail == N_RAIL_Q)
1352 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1353 if (core2or5 && rail == N_RAIL_I)
1354 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1355 if (core2or5 && rail == N_RAIL_Q)
1356 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1357 break;
2a2d0589 1358 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1359 if (core1or5)
1360 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1361 if (core2or5)
1362 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1363 break;
2a2d0589 1364 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1365 if (core1or5)
1366 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1367 if (core2or5)
1368 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1369 break;
1370 }
8987a9e9
RM		 1371}
1372
a3764ef7
RM		 1373static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1374 enum n_rssi_type rssi_type)
bbec398c 1375{
4d9f46ba
RM		 1376 u8 i;
1377 u16 reg, val;
bbec398c 1378
4d9f46ba
RM		 1379 if (code == 0) {
1380 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1381 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1382 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1383 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1384 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1385 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1386 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1387 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1388 } else {
1389 for (i = 0; i < 2; i++) {
1390 if ((code == 1 && i == 1) || (code == 2 && !i))
1391 continue;
bbec398c 1392
4d9f46ba
RM		 1393 reg = (i == 0) ?
1394 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1395 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1396
a3764ef7
RM		 1397 if (rssi_type == N_RSSI_W1 ||
1398 rssi_type == N_RSSI_W2 ||
1399 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1400 reg = (i == 0) ?
1401 B43_NPHY_AFECTL_C1 :
1402 B43_NPHY_AFECTL_C2;
1403 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1404
4d9f46ba
RM		 1405 reg = (i == 0) ?
1406 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1407 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1408 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1409
a3764ef7 1410 if (rssi_type == N_RSSI_W1)
4d9f46ba 1411 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1412 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1413 val = 16;
1414 else
1415 val = 32;
1416 b43_phy_set(dev, reg, val);
5c1a140a 1417
4d9f46ba
RM		 1418 reg = (i == 0) ?
1419 B43_NPHY_TXF_40CO_B1S0 :
1420 B43_NPHY_TXF_40CO_B32S1;
1421 b43_phy_set(dev, reg, 0x0020);
1422 } else {
a3764ef7 1423 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1424 val = 0x0100;
a3764ef7 1425 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1426 val = 0x0200;
1427 else
1428 val = 0x0300;
5c1a140a 1429
4d9f46ba
RM		 1430 reg = (i == 0) ?
1431 B43_NPHY_AFECTL_C1 :
1432 B43_NPHY_AFECTL_C2;
53ae8e8c 1433
4d9f46ba
RM		 1434 b43_phy_maskset(dev, reg, 0xFCFF, val);
1435 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1436
a3764ef7
RM		 1437 if (rssi_type != N_RSSI_IQ &&
1438 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1439 enum ieee80211_band band =
1440 b43_current_band(dev->wl);
53ae8e8c 1441
4d9f46ba
RM		 1442 if (b43_nphy_ipa(dev))
1443 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1444 else
1445 val = 0x11;
1446 reg = (i == 0) ? 0x2000 : 0x3000;
1447 reg |= B2055_PADDRV;
0c201cfb 1448 b43_radio_write(dev, reg, val);
53ae8e8c 1449
4d9f46ba
RM		 1450 reg = (i == 0) ?
1451 B43_NPHY_AFECTL_OVER1 :
1452 B43_NPHY_AFECTL_OVER;
1453 b43_phy_set(dev, reg, 0x0200);
1454 }
1455 }
1456 }
53ae8e8c 1457 }
53ae8e8c
RM		 1458}
1459
a3764ef7
RM		 1460static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1461 enum n_rssi_type rssi_type)
9442e5b5 1462{
4d9f46ba 1463 u16 val;
a3764ef7 1464 bool rssi_w1_w2_nb = false;
9442e5b5 1465
a3764ef7
RM		 1466 switch (rssi_type) {
1467 case N_RSSI_W1:
1468 case N_RSSI_W2:
1469 case N_RSSI_NB:
4d9f46ba 1470 val = 0;
a3764ef7
RM		 1471 rssi_w1_w2_nb = true;
1472 break;
1473 case N_RSSI_TBD:
4d9f46ba 1474 val = 1;
a3764ef7
RM		 1475 break;
1476 case N_RSSI_IQ:
4d9f46ba 1477 val = 2;
a3764ef7
RM		 1478 break;
1479 default:
4d9f46ba 1480 val = 3;
a3764ef7 1481 }
9442e5b5 1482
4d9f46ba
RM		 1483 val = (val << 12) | (val << 14);
1484 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1485 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1486
a3764ef7 1487 if (rssi_w1_w2_nb) {
4d9f46ba 1488 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1489 (rssi_type + 1) << 4);
4d9f46ba 1490 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1491 (rssi_type + 1) << 4);
9442e5b5
RM		 1492 }
1493
4d9f46ba
RM		 1494 if (code == 0) {
1495 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1496 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1497 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1498 ~(B43_NPHY_RFCTL_CMD_RXEN |
1499 B43_NPHY_RFCTL_CMD_CORESEL));
1500 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1501 ~(0x1 << 12 |
1502 0x1 << 5 |
1503 0x1 << 1 |
1504 0x1));
1505 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1506 ~B43_NPHY_RFCTL_CMD_START);
1507 udelay(20);
1508 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1509 }
1510 } else {
1511 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1512 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1513 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1514 ~(B43_NPHY_RFCTL_CMD_RXEN |
1515 B43_NPHY_RFCTL_CMD_CORESEL),
1516 (B43_NPHY_RFCTL_CMD_RXEN |
1517 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1518 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1519 (0x1 << 12 |
1520 0x1 << 5 |
1521 0x1 << 1 |
1522 0x1));
1523 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1524 B43_NPHY_RFCTL_CMD_START);
1525 udelay(20);
1526 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1527 }
9442e5b5 1528 }
9442e5b5
RM		 1529}
1530
4d9f46ba 1531/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1532static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1533 enum n_rssi_type type)
d24019ad 1534{
4d9f46ba
RM		 1535 if (dev->phy.rev >= 3)
1536 b43_nphy_rev3_rssi_select(dev, code, type);
1537 else
1538 b43_nphy_rev2_rssi_select(dev, code, type);
1539}
d24019ad 1540
5ecab603 1541/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1542static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1543 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1544{
1545 int i;
d24019ad 1546 for (i = 0; i < 2; i++) {
a3764ef7 1547 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1548 if (i == 0) {
1549 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1550 0xFC, buf[0]);
1551 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1552 0xFC, buf[1]);
1553 } else {
1554 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1555 0xFC, buf[2 * i]);
1556 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1557 0xFC, buf[2 * i + 1]);
1558 }
d24019ad 1559 } else {
5ecab603
RM		 1560 if (i == 0)
1561 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1562 0xF3, buf[0] << 2);
1563 else
1564 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1565 0xF3, buf[2 * i + 1] << 2);
d24019ad 1566 }
d24019ad 1567 }
d24019ad
RM		 1568}
1569
5ecab603 1570/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1571static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1572 s32 *buf, u8 nsamp)
ef5127a4 1573{
5ecab603
RM		 1574 int i;
1575 int out;
1576 u16 save_regs_phy[9];
1577 u16 s[2];
ef5127a4
RM		 1578
1579 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1580 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1581 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1582 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1583 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1584 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1585 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1586 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1587 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1588 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1589 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1590 save_regs_phy[8] = 0;
ef5127a4 1591 } else {
5ecab603
RM		 1592 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1593 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1594 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1595 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1596 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1597 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1598 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1599 save_regs_phy[7] = 0;
1600 save_regs_phy[8] = 0;
1601 }
ef5127a4 1602
a3764ef7 1603 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1604
5ecab603
RM		 1605 if (dev->phy.rev < 2) {
1606 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1607 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1608 }
ef5127a4 1609
5ecab603
RM		 1610 for (i = 0; i < 4; i++)
1611 buf[i] = 0;
1612
1613 for (i = 0; i < nsamp; i++) {
1614 if (dev->phy.rev < 2) {
1615 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1616 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1617 } else {
5ecab603
RM		 1618 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1619 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1620 }
1621
5ecab603
RM		 1622 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1623 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1624 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1625 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1626 }
1627 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1628 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1629
5ecab603
RM		 1630 if (dev->phy.rev < 2)
1631 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1632
5ecab603 1633 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1634 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1635 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1636 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1637 save_regs_phy[2]);
5ecab603 1638 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1639 save_regs_phy[3]);
5ecab603
RM		 1640 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1641 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1642 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1643 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1644 } else {
1645 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1646 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1647 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1648 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1649 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1650 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1651 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1652 }
ef5127a4 1653
5ecab603
RM		 1654 return out;
1655}
ef5127a4 1656
e0c9a021
RM		 1657/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1658static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1659{
1660 struct b43_phy_n *nphy = dev->phy.n;
1661
1662 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1663 u16 saved_regs_phy[22];
1664 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1665 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1666 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1667 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1668 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1669 B43_NPHY_RFCTL_CMD,
1670 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1671 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1672 };
97e2a1a1
RM		 1673 u16 regs_to_store_rev7[] = {
1674 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1675 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1676 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1677 0x342, 0x343, 0x346, 0x347,
1678 0x2ff,
1679 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1680 B43_NPHY_RFCTL_CMD,
1681 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1682 0x340, 0x341, 0x344, 0x345,
1683 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1684 };
1685 u16 *regs_to_store;
1686 int regs_amount;
e0c9a021
RM		 1687
1688 u16 class;
1689
1690 u16 clip_state[2];
1691 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1692
1693 u8 vcm_final = 0;
2e1253d6 1694 s32 offset[4];
e0c9a021
RM		 1695 s32 results[8][4] = { };
1696 s32 results_min[4] = { };
1697 s32 poll_results[4] = { };
1698
1699 u16 *rssical_radio_regs = NULL;
1700 u16 *rssical_phy_regs = NULL;
1701
1702 u16 r; /* routing */
1703 u8 rx_core_state;
37859a75 1704 int core, i, j, vcm;
e0c9a021 1705
97e2a1a1
RM		 1706 if (dev->phy.rev >= 7) {
1707 regs_to_store = regs_to_store_rev7;
1708 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1709 } else {
1710 regs_to_store = regs_to_store_rev3;
1711 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1712 }
1713 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1714
e0c9a021
RM		 1715 class = b43_nphy_classifier(dev, 0, 0);
1716 b43_nphy_classifier(dev, 7, 4);
1717 b43_nphy_read_clip_detection(dev, clip_state);
1718 b43_nphy_write_clip_detection(dev, clip_off);
1719
1720 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1721 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1722 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1723 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1724
89e43dad
RM		 1725 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1726 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1727
1728 if (dev->phy.rev >= 7) {
1729 /* TODO */
1730 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1731 } else {
1732 }
e0c9a021 1733 } else {
97e2a1a1
RM		 1734 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1735 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1736 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1737 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1738 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1739 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1740 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1741 } else {
1742 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1743 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1744 }
e0c9a021
RM		 1745 }
1746
1747 rx_core_state = b43_nphy_get_rx_core_state(dev);
1748 for (core = 0; core < 2; core++) {
1749 if (!(rx_core_state & (1 << core)))
1750 continue;
1751 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1752 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1753 N_RSSI_NB);
1754 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1755 N_RSSI_NB);
37859a75
RM		 1756
1757 /* Grab RSSI results for every possible VCM */
1758 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1759 if (dev->phy.rev >= 7)
1760 ;
1761 else
1762 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1763 0xE3, vcm << 2);
a3764ef7 1764 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1765 }
37859a75
RM		 1766
1767 /* Find out which VCM got the best results */
cddec902 1768 for (i = 0; i < 4; i += 2) {
37859a75 1769 s32 currd;
e67dd874 1770 s32 mind = 0x100000;
e0c9a021
RM		 1771 s32 minpoll = 249;
1772 u8 minvcm = 0;
1773 if (2 * core != i)
1774 continue;
37859a75
RM		 1775 for (vcm = 0; vcm < 8; vcm++) {
1776 currd = results[vcm][i] * results[vcm][i] +
1777 results[vcm][i + 1] * results[vcm][i];
1778 if (currd < mind) {
1779 mind = currd;
1780 minvcm = vcm;
e0c9a021 1781 }
37859a75
RM		 1782 if (results[vcm][i] < minpoll)
1783 minpoll = results[vcm][i];
e0c9a021
RM		 1784 }
1785 vcm_final = minvcm;
1786 results_min[i] = minpoll;
1787 }
37859a75
RM		 1788
1789 /* Select the best VCM */
97e2a1a1
RM		 1790 if (dev->phy.rev >= 7)
1791 ;
1792 else
1793 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1794 0xE3, vcm_final << 2);
37859a75 1795
e0c9a021
RM		 1796 for (i = 0; i < 4; i++) {
1797 if (core != i / 2)
1798 continue;
1799 offset[i] = -results[vcm_final][i];
1800 if (offset[i] < 0)
1801 offset[i] = -((abs(offset[i]) + 4) / 8);
1802 else
1803 offset[i] = (offset[i] + 4) / 8;
1804 if (results_min[i] == 248)
1805 offset[i] = -32;
1806 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1807 (i / 2 == 0) ? 1 : 2,
6aa38725 1808 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1809 N_RSSI_NB);
e0c9a021
RM		 1810 }
1811 }
37859a75 1812
e0c9a021
RM		 1813 for (core = 0; core < 2; core++) {
1814 if (!(rx_core_state & (1 << core)))
1815 continue;
1816 for (i = 0; i < 2; i++) {
6aa38725
RM		 1817 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1818 N_RAIL_I, i);
1819 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1820 N_RAIL_Q, i);
e0c9a021
RM		 1821 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1822 for (j = 0; j < 4; j++) {
cddec902 1823 if (j / 2 == core) {
e0c9a021 1824 offset[j] = 232 - poll_results[j];
cddec902
RM		 1825 if (offset[j] < 0)
1826 offset[j] = -(abs(offset[j] + 4) / 8);
1827 else
1828 offset[j] = (offset[j] + 4) / 8;
1829 b43_nphy_scale_offset_rssi(dev, 0,
1830 offset[2 * core], core + 1, j % 2, i);
1831 }
e0c9a021
RM		 1832 }
1833 }
1834 }
1835
1836 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1837 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1838
1839 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1840
1841 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1842 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1843 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1844
1845 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1846 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 1847 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 1848
97e2a1a1 1849 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1850 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1851
1852 /* Store for future configuration */
1853 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1854 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1855 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1856 } else {
1857 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1858 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1859 }
9a98979e
RM		 1860 if (dev->phy.rev >= 7) {
1861 } else {
1862 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1863 B2056_RX_RSSI_MISC);
1864 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1865 B2056_RX_RSSI_MISC);
1866 }
e0c9a021
RM		 1867 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1868 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1869 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1870 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1871 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1872 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1873 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1874 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1875 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1876 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1877 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1878 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1879
1880 /* Remember for which channel we store configuration */
1881 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1882 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1883 else
1884 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1885
1886 /* End of calibration, restore configuration */
1887 b43_nphy_classifier(dev, 7, class);
1888 b43_nphy_write_clip_detection(dev, clip_state);
1889}
1890
5ecab603 1891/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1892static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1893{
37859a75 1894 int i, j, vcm;
5ecab603
RM		 1895 u8 state[4];
1896 u8 code, val;
1897 u16 class, override;
1898 u8 regs_save_radio[2];
1899 u16 regs_save_phy[2];
1900
2e1253d6 1901 s32 offset[4];
5ecab603
RM		 1902 u8 core;
1903 u8 rail;
1904
1905 u16 clip_state[2];
1906 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1907 s32 results_min[4] = { };
1908 u8 vcm_final[4] = { };
1909 s32 results[4][4] = { };
1910 s32 miniq[4][2] = { };
1911
a3764ef7 1912 if (type == N_RSSI_NB) {
5ecab603
RM		 1913 code = 0;
1914 val = 6;
a3764ef7 1915 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1916 code = 25;
1917 val = 4;
1918 } else {
1919 B43_WARN_ON(1);
1920 return;
1921 }
1922
1923 class = b43_nphy_classifier(dev, 0, 0);
1924 b43_nphy_classifier(dev, 7, 4);
1925 b43_nphy_read_clip_detection(dev, clip_state);
1926 b43_nphy_write_clip_detection(dev, clip_off);
1927
1928 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1929 override = 0x140;
1930 else
1931 override = 0x110;
1932
1933 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 1934 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 1935 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 1936 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 1937
1938 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 1939 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 1940 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 1941 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 1942
0c201cfb
RM		 1943 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1944 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 1945 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1946 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 1947 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1948 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 1949
1950 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1951 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1952 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1953
37859a75 1954 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1955 u8 tmp[4];
1956 for (j = 0; j < 4; j++)
37859a75 1957 tmp[j] = vcm;
a3764ef7 1958 if (type != N_RSSI_W2)
5ecab603 1959 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1960 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1961 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1962 for (j = 0; j < 2; j++)
37859a75
RM		 1963 miniq[vcm][j] = min(results[vcm][2 * j],
1964 results[vcm][2 * j + 1]);
5ecab603
RM		 1965 }
1966
1967 for (i = 0; i < 4; i++) {
e67dd874 1968 s32 mind = 0x100000;
5ecab603
RM		 1969 u8 minvcm = 0;
1970 s32 minpoll = 249;
37859a75
RM		 1971 s32 currd;
1972 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1973 if (type == N_RSSI_NB)
542e15f3 1974 currd = abs(results[vcm][i] - code * 8);
5ecab603 1975 else
37859a75 1976 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1977
37859a75
RM		 1978 if (currd < mind) {
1979 mind = currd;
1980 minvcm = vcm;
5ecab603
RM		 1981 }
1982
37859a75
RM		 1983 if (results[vcm][i] < minpoll)
1984 minpoll = results[vcm][i];
8e60b044 1985 }
5ecab603
RM		 1986 results_min[i] = minpoll;
1987 vcm_final[i] = minvcm;
1988 }
ef5127a4 1989
a3764ef7 1990 if (type != N_RSSI_W2)
5ecab603 1991 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 1992
5ecab603
RM		 1993 for (i = 0; i < 4; i++) {
1994 offset[i] = (code * 8) - results[vcm_final[i]][i];
1995
1996 if (offset[i] < 0)
1997 offset[i] = -((abs(offset[i]) + 4) / 8);
1998 else
1999 offset[i] = (offset[i] + 4) / 8;
2000
2001 if (results_min[i] == 248)
2002 offset[i] = code - 32;
2003
2004 core = (i / 2) ? 2 : 1;
6aa38725 2005 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2006
2007 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2008 type);
2009 }
2010
2011 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2012 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2013
2014 switch (state[2]) {
2015 case 1:
a3764ef7 2016 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2017 break;
2018 case 4:
a3764ef7 2019 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2020 break;
2021 case 2:
a3764ef7 2022 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2023 break;
2024 default:
a3764ef7 2025 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2026 break;
2027 }
2028
2029 switch (state[3]) {
2030 case 1:
a3764ef7 2031 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2032 break;
2033 case 4:
a3764ef7 2034 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2035 break;
2036 default:
a3764ef7 2037 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2038 break;
2039 }
2040
2041 b43_nphy_rssi_select(dev, 0, type);
2042
2043 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2044 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2046 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2047
2048 b43_nphy_classifier(dev, 7, class);
2049 b43_nphy_write_clip_detection(dev, clip_state);
2050 /* Specs don't say about reset here, but it makes wl and b43 dumps
2051 identical, it really seems wl performs this */
2052 b43_nphy_reset_cca(dev);
2053}
2054
5ecab603
RM		 2055/*
2056 * RSSI Calibration
2057 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2058 */
2059static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2060{
2061 if (dev->phy.rev >= 3) {
2062 b43_nphy_rev3_rssi_cal(dev);
2063 } else {
2a2d0589
RM		 2064 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2065 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2066 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2067 }
2068}
2069
64712095
RM		 2070/**************************************************
2071 * Workarounds
2072 **************************************************/
2073
2074static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2075{
2076 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2077
2078 bool ghz5;
2079 bool ext_lna;
2080 u16 rssi_gain;
2081 struct nphy_gain_ctl_workaround_entry *e;
2082 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2083 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2084
2085 /* Prepare values */
2086 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2087 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2088 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2089 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2090 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2091 if (ghz5 && dev->phy.rev >= 5)
2092 rssi_gain = 0x90;
2093 else
2094 rssi_gain = 0x50;
2095
2096 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2097
2098 /* Set Clip 2 detect */
04519dc6
RM		 2099 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2100 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2101
2102 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2103 0x17);
2104 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2105 0x17);
2106 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2107 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2108 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2109 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2110 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2111 rssi_gain);
2112 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2113 rssi_gain);
2114 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2115 0x17);
2116 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2117 0x17);
2118 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2119 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2120
2121 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2122 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2123 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2124 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2125 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2126 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2127 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2128 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2129 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2130 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2131 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2132 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2133
04519dc6
RM		 2134 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2135 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2136
64712095
RM		 2137 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2138 e->rfseq_init);
64712095 2139
04519dc6
RM		 2140 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2141 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2142 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2143 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2144 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2145 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2146
2147 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2148 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2149 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2150 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2151 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2152 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2153 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2154 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2155 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2156 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2157}
2158
2159static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2160{
2161 struct b43_phy_n *nphy = dev->phy.n;
2162
2163 u8 i, j;
2164 u8 code;
2165 u16 tmp;
2166 u8 rfseq_events[3] = { 6, 8, 7 };
2167 u8 rfseq_delays[3] = { 10, 30, 1 };
2168
2169 /* Set Clip 2 detect */
2170 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2171 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2172
2173 /* Set narrowband clip threshold */
2174 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2175 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2176
2177 if (!dev->phy.is_40mhz) {
2178 /* Set dwell lengths */
2179 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2180 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2181 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2182 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2183 }
2184
2185 /* Set wideband clip 2 threshold */
2186 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2187 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2188 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2189 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2190
2191 if (!dev->phy.is_40mhz) {
2192 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2193 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2194 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2195 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2196 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2197 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2198 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2199 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2200 }
2201
2202 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2203
2204 if (nphy->gain_boost) {
2205 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2206 dev->phy.is_40mhz)
2207 code = 4;
2208 else
2209 code = 5;
2210 } else {
2211 code = dev->phy.is_40mhz ? 6 : 7;
2212 }
2213
2214 /* Set HPVGA2 index */
2215 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2216 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2217 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2218 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2219
2220 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2221 /* specs say about 2 loops, but wl does 4 */
2222 for (i = 0; i < 4; i++)
2223 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2224
2225 b43_nphy_adjust_lna_gain_table(dev);
2226
2227 if (nphy->elna_gain_config) {
2228 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2229 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2230 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2231 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2232 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2233
2234 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2235 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2236 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2237 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2238 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2239
2240 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2241 /* specs say about 2 loops, but wl does 4 */
2242 for (i = 0; i < 4; i++)
2243 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2244 (code << 8 | 0x74));
2245 }
2246
2247 if (dev->phy.rev == 2) {
2248 for (i = 0; i < 4; i++) {
2249 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2250 (0x0400 * i) + 0x0020);
2251 for (j = 0; j < 21; j++) {
2252 tmp = j * (i < 2 ? 3 : 1);
2253 b43_phy_write(dev,
2254 B43_NPHY_TABLE_DATALO, tmp);
2255 }
2256 }
ef5127a4 2257 }
64712095
RM		 2258
2259 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2260 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2261 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2262 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2263
2264 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2265 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2266}
2267
2268/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2269static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2270{
d11d354b
RM		 2271 if (dev->phy.rev >= 7)
2272 ; /* TODO */
2273 else if (dev->phy.rev >= 3)
64712095
RM		 2274 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2275 else
2276 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2277}
2278
d11d354b
RM		 2279/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2280static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2281{
2282 if (!offset)
2283 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2284 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2285}
2286
2287static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2288{
2289 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2290 struct b43_phy *phy = &dev->phy;
2291
2292 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2293 0x1F };
2294 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2295
2296 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2297 u8 ntab7_138_146[] = { 0x11, 0x11 };
2298 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2299
2300 u16 lpf_20, lpf_40, lpf_11b;
2301 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2302 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2303 bool rccal_ovrd = false;
2304
2305 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2306 u16 bias, conv, filt;
2307
2308 u32 tmp32;
2309 u8 core;
2310
2311 if (phy->rev == 7) {
2312 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2313 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2314 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2315 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2316 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2317 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2318 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2319 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2320 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2321 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2322 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2323 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2324 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2325 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2326 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2327 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2328 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2329 }
2330 if (phy->rev <= 8) {
04519dc6
RM		 2331 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2332 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2333 }
2334 if (phy->rev >= 8)
2335 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2336
2337 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2338 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2339 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2340 tmp32 &= 0xffffff;
2341 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2342 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2343 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2344
2345 if (b43_nphy_ipa(dev))
2346 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2347 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2348
04519dc6
RM		 2349 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2350 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2351
2352 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2353 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2354 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2355 if (b43_nphy_ipa(dev)) {
2356 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2357 phy->radio_rev == 7 || phy->radio_rev == 8) {
2358 bcap_val = b43_radio_read(dev, 0x16b);
2359 scap_val = b43_radio_read(dev, 0x16a);
2360 scap_val_11b = scap_val;
2361 bcap_val_11b = bcap_val;
2362 if (phy->radio_rev == 5 && phy->is_40mhz) {
2363 scap_val_11n_20 = scap_val;
2364 bcap_val_11n_20 = bcap_val;
2365 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2366 rccal_ovrd = true;
2367 } else { /* Rev 7/8 */
2368 lpf_20 = 4;
2369 lpf_11b = 1;
2370 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2371 scap_val_11n_20 = 0xc;
2372 bcap_val_11n_20 = 0xc;
2373 scap_val_11n_40 = 0xa;
2374 bcap_val_11n_40 = 0xa;
2375 } else {
2376 scap_val_11n_20 = 0x14;
2377 bcap_val_11n_20 = 0x14;
2378 scap_val_11n_40 = 0xf;
2379 bcap_val_11n_40 = 0xf;
2380 }
2381 rccal_ovrd = true;
2382 }
2383 }
2384 } else {
2385 if (phy->radio_rev == 5) {
2386 lpf_20 = 1;
2387 lpf_40 = 3;
2388 bcap_val = b43_radio_read(dev, 0x16b);
2389 scap_val = b43_radio_read(dev, 0x16a);
2390 scap_val_11b = scap_val;
2391 bcap_val_11b = bcap_val;
2392 scap_val_11n_20 = 0x11;
2393 scap_val_11n_40 = 0x11;
2394 bcap_val_11n_20 = 0x13;
2395 bcap_val_11n_40 = 0x13;
2396 rccal_ovrd = true;
2397 }
2398 }
2399 if (rccal_ovrd) {
2400 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2401 (scap_val_11b << 3) |
2402 lpf_11b;
2403 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2404 (scap_val_11n_20 << 3) |
2405 lpf_20;
2406 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2407 (scap_val_11n_40 << 3) |
2408 lpf_40;
2409 for (core = 0; core < 2; core++) {
2410 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2411 rx2tx_lut_20_11b);
2412 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2413 rx2tx_lut_20_11n);
2414 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2415 rx2tx_lut_20_11n);
2416 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2417 rx2tx_lut_40_11n);
2418 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2419 rx2tx_lut_40_11n);
2420 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2421 rx2tx_lut_40_11n);
2422 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2423 rx2tx_lut_40_11n);
2424 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2425 rx2tx_lut_40_11n);
2426 }
78ae7532 2427 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2428 }
2429 b43_phy_write(dev, 0x32F, 0x3);
2430 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2431 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2432
2433 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2434 if (sprom->revision &&
2435 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2436 b43_radio_write(dev, 0x5, 0x05);
2437 b43_radio_write(dev, 0x6, 0x30);
2438 b43_radio_write(dev, 0x7, 0x00);
2439 b43_radio_set(dev, 0x4f, 0x1);
2440 b43_radio_set(dev, 0xd4, 0x1);
2441 bias = 0x1f;
2442 conv = 0x6f;
2443 filt = 0xaa;
2444 } else {
2445 bias = 0x2b;
2446 conv = 0x7f;
2447 filt = 0xee;
2448 }
2449 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2450 for (core = 0; core < 2; core++) {
2451 if (core == 0) {
2452 b43_radio_write(dev, 0x5F, bias);
2453 b43_radio_write(dev, 0x64, conv);
2454 b43_radio_write(dev, 0x66, filt);
2455 } else {
2456 b43_radio_write(dev, 0xE8, bias);
2457 b43_radio_write(dev, 0xE9, conv);
2458 b43_radio_write(dev, 0xEB, filt);
2459 }
2460 }
2461 }
2462 }
2463
2464 if (b43_nphy_ipa(dev)) {
2465 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2466 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2467 phy->radio_rev == 6) {
2468 for (core = 0; core < 2; core++) {
2469 if (core == 0)
2470 b43_radio_write(dev, 0x51,
2471 0x7f);
2472 else
2473 b43_radio_write(dev, 0xd6,
2474 0x7f);
2475 }
2476 }
2477 if (phy->radio_rev == 3) {
2478 for (core = 0; core < 2; core++) {
2479 if (core == 0) {
2480 b43_radio_write(dev, 0x64,
2481 0x13);
2482 b43_radio_write(dev, 0x5F,
2483 0x1F);
2484 b43_radio_write(dev, 0x66,
2485 0xEE);
2486 b43_radio_write(dev, 0x59,
2487 0x8A);
2488 b43_radio_write(dev, 0x80,
2489 0x3E);
2490 } else {
2491 b43_radio_write(dev, 0x69,
2492 0x13);
2493 b43_radio_write(dev, 0xE8,
2494 0x1F);
2495 b43_radio_write(dev, 0xEB,
2496 0xEE);
2497 b43_radio_write(dev, 0xDE,
2498 0x8A);
2499 b43_radio_write(dev, 0x105,
2500 0x3E);
2501 }
2502 }
2503 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2504 if (!phy->is_40mhz) {
2505 b43_radio_write(dev, 0x5F, 0x14);
2506 b43_radio_write(dev, 0xE8, 0x12);
2507 } else {
2508 b43_radio_write(dev, 0x5F, 0x16);
2509 b43_radio_write(dev, 0xE8, 0x16);
2510 }
2511 }
2512 } else {
2513 u16 freq = phy->channel_freq;
2514 if ((freq >= 5180 && freq <= 5230) ||
2515 (freq >= 5745 && freq <= 5805)) {
2516 b43_radio_write(dev, 0x7D, 0xFF);
2517 b43_radio_write(dev, 0xFE, 0xFF);
2518 }
2519 }
2520 } else {
2521 if (phy->radio_rev != 5) {
2522 for (core = 0; core < 2; core++) {
2523 if (core == 0) {
2524 b43_radio_write(dev, 0x5c, 0x61);
2525 b43_radio_write(dev, 0x51, 0x70);
2526 } else {
2527 b43_radio_write(dev, 0xe1, 0x61);
2528 b43_radio_write(dev, 0xd6, 0x70);
2529 }
2530 }
2531 }
2532 }
2533
2534 if (phy->radio_rev == 4) {
2535 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2536 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2537 for (core = 0; core < 2; core++) {
2538 if (core == 0) {
2539 b43_radio_write(dev, 0x1a1, 0x00);
2540 b43_radio_write(dev, 0x1a2, 0x3f);
2541 b43_radio_write(dev, 0x1a6, 0x3f);
2542 } else {
2543 b43_radio_write(dev, 0x1a7, 0x00);
2544 b43_radio_write(dev, 0x1ab, 0x3f);
2545 b43_radio_write(dev, 0x1ac, 0x3f);
2546 }
2547 }
2548 } else {
2549 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2550 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2551 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2552 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2553
2554 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2555 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2556 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2557 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2558 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2559 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2560
2561 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2562 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2563 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2564 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2565 }
2566
2567 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2568
2569 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2570 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2571 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2572 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2573 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2574 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2575 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2576
2577 if (!phy->is_40mhz) {
2578 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2579 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2580 } else {
2581 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2582 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2583 }
2584
2585 b43_nphy_gain_ctl_workarounds(dev);
2586
2587 /* TODO
2588 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2589 aux_adc_vmid_rev7_core0);
2590 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2591 aux_adc_vmid_rev7_core1);
2592 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2593 aux_adc_gain_rev7);
2594 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2595 aux_adc_gain_rev7);
2596 */
2597}
2598
73d07a39 2599static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2600{
0eff8fcd 2601 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2602 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2603
0eff8fcd 2604 /* TX to RX */
c378bb97
RM		 2605 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2606 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2607 /* RX to TX */
2608 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2609 0x1F };
2610 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2611 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2612 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2613
c378bb97
RM		 2614 u16 vmids[5][4] = {
2615 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2616 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2617 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2618 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2619 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2620 };
2621 u16 gains[5][4] = {
2622 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2623 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2624 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2625 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2626 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2627 };
2628 u16 *vmid, *gain;
2629
2630 u8 pdet_range;
ba9a6214
RM		 2631 u16 tmp16;
2632 u32 tmp32;
2633
04519dc6
RM		 2634 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2635 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2636
73d07a39
RM		 2637 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2638 tmp32 &= 0xffffff;
2639 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2640
73d07a39
RM		 2641 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2642 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2643 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2644 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2645 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2646 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2647
04519dc6
RM		 2648 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2649 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2650
0eff8fcd 2651 /* TX to RX */
c56da252
RM		 2652 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2653 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2654
2655 /* RX to TX */
2656 if (b43_nphy_ipa(dev))
c56da252
RM		 2657 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2658 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2659 if (nphy->hw_phyrxchain != 3 &&
2660 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2661 if (b43_nphy_ipa(dev)) {
2662 rx2tx_delays[5] = 59;
2663 rx2tx_delays[6] = 1;
2664 rx2tx_events[7] = 0x1F;
2665 }
fa0f2b38 2666 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2667 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2668 }
ba9a6214 2669
73d07a39
RM		 2670 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2671 0x2 : 0x9C40;
2672 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2673
04519dc6 2674 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2675
fa0f2b38
RM		 2676 if (!dev->phy.is_40mhz) {
2677 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2678 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2679 } else {
2680 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2681 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2682 }
ba9a6214 2683
3ccd0957 2684 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2685
c56da252
RM		 2686 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2687 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2688
c378bb97
RM		 2689 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2690 pdet_range = sprom->fem.ghz2.pdet_range;
2691 else
2692 pdet_range = sprom->fem.ghz5.pdet_range;
2693 vmid = vmids[min_t(u16, pdet_range, 4)];
2694 gain = gains[min_t(u16, pdet_range, 4)];
2695 switch (pdet_range) {
2696 case 3:
2697 if (!(dev->phy.rev >= 4 &&
2698 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2699 break;
2700 /* FALL THROUGH */
2701 case 0:
2702 case 1:
2703 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2704 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2705 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2706 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2707 break;
2708 case 2:
2709 if (dev->phy.rev >= 6) {
2710 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2711 vmid[3] = 0x94;
2712 else
2713 vmid[3] = 0x8e;
2714 gain[3] = 3;
2715 } else if (dev->phy.rev == 5) {
2716 vmid[3] = 0x84;
2717 gain[3] = 2;
2718 }
2719 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2720 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2721 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2722 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2723 break;
2724 case 4:
2725 case 5:
2726 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2727 if (pdet_range == 4) {
2728 vmid[3] = 0x8e;
2729 tmp16 = 0x96;
2730 gain[3] = 0x2;
2731 } else {
2732 vmid[3] = 0x89;
2733 tmp16 = 0x89;
2734 gain[3] = 0;
2735 }
2736 } else {
2737 if (pdet_range == 4) {
2738 vmid[3] = 0x89;
2739 tmp16 = 0x8b;
2740 gain[3] = 0x2;
2741 } else {
2742 vmid[3] = 0x74;
2743 tmp16 = 0x70;
2744 gain[3] = 0;
2745 }
2746 }
2747 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2748 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2749 vmid[3] = tmp16;
2750 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2751 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2752 break;
2753 }
ba9a6214 2754
73d07a39
RM		 2755 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2756 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2757 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2758 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2759 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2760 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2761 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2762 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2763 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2764 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2765 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2766 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2767
2768 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2769
2770 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2771 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2772 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2773 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2774 tmp32 = 0x00088888;
2775 else
2776 tmp32 = 0x88888888;
2777 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2778 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2779 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2780
2781 if (dev->phy.rev == 4 &&
fa0f2b38 2782 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2783 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2784 0x70);
2785 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2786 0x70);
2787 }
ba9a6214 2788
fa0f2b38 2789 /* Dropped probably-always-true condition */
04519dc6
RM		 2790 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2791 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2792 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2793 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2794 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2795 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2796 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2797 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2798 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2799 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2800 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2801 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2802
2803 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2804 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2805}
ba9a6214 2806
73d07a39
RM		 2807static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2808{
2809 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2810 struct b43_phy *phy = &dev->phy;
2811 struct b43_phy_n *nphy = phy->n;
ba9a6214 2812
73d07a39
RM		 2813 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2814 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2815
73d07a39
RM		 2816 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2817 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2818
fa0f2b38 2819 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2820 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2821 delays1[0] = 0x1;
2822 delays1[5] = 0x14;
2823 }
2824
73d07a39
RM		 2825 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2826 nphy->band5g_pwrgain) {
2827 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2828 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2829 } else {
73d07a39
RM		 2830 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2831 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2832 }
28fd7daa 2833
73d07a39
RM		 2834 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2835 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2836 if (dev->phy.rev < 3) {
2837 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2838 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2839 }
73d07a39
RM		 2840
2841 if (dev->phy.rev < 2) {
2842 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2843 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2844 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2845 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2846 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2847 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2848 }
28fd7daa 2849
73d07a39
RM		 2850 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2851 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2852 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2853 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2854
73d07a39
RM		 2855 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2856 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2857
3ccd0957 2858 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2859
2860 if (dev->phy.rev < 2) {
2861 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2862 b43_hf_write(dev, b43_hf_read(dev) |
2863 B43_HF_MLADVW);
2864 } else if (dev->phy.rev == 2) {
2865 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2866 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2867 }
28fd7daa 2868
73d07a39
RM		 2869 if (dev->phy.rev < 2)
2870 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2871 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2872
2873 /* Set phase track alpha and beta */
2874 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2875 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2876 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2877 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2878 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2879 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2880
fa0f2b38
RM		 2881 if (dev->phy.rev < 3) {
2882 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2883 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2884 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2885 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2886 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2887 }
73d07a39
RM		 2888
2889 if (dev->phy.rev == 2)
2890 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2891 B43_NPHY_FINERX2_CGC_DECGC);
2892}
28fd7daa 2893
73d07a39
RM		 2894/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2895static void b43_nphy_workarounds(struct b43_wldev *dev)
2896{
2897 struct b43_phy *phy = &dev->phy;
2898 struct b43_phy_n *nphy = phy->n;
28fd7daa 2899
73d07a39
RM		 2900 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2901 b43_nphy_classifier(dev, 1, 0);
2902 else
2903 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2904
73d07a39
RM		 2905 if (nphy->hang_avoid)
2906 b43_nphy_stay_in_carrier_search(dev, 1);
2907
2908 b43_phy_set(dev, B43_NPHY_IQFLIP,
2909 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2910
d11d354b
RM		 2911 if (dev->phy.rev >= 7)
2912 b43_nphy_workarounds_rev7plus(dev);
2913 else if (dev->phy.rev >= 3)
73d07a39
RM		 2914 b43_nphy_workarounds_rev3plus(dev);
2915 else
2916 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2917
2918 if (nphy->hang_avoid)
2919 b43_nphy_stay_in_carrier_search(dev, 0);
2920}
2921
9dd4d9b9
RM		 2922/**************************************************
2923 * Tx/Rx common
2924 **************************************************/
2925
2926/*
2927 * Transmits a known value for LO calibration
2928 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2929 */
2930static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2931 bool iqmode, bool dac_test)
2932{
2933 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2934 if (samp == 0)
2935 return -1;
2936 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2937 return 0;
2938}
2939
2940/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2941static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2942{
2943 struct b43_phy_n *nphy = dev->phy.n;
2944
2945 bool override = false;
2946 u16 chain = 0x33;
2947
2948 if (nphy->txrx_chain == 0) {
2949 chain = 0x11;
2950 override = true;
2951 } else if (nphy->txrx_chain == 1) {
2952 chain = 0x22;
2953 override = true;
2954 }
2955
2956 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2957 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2958 chain);
2959
2960 if (override)
2961 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2962 B43_NPHY_RFSEQMODE_CAOVER);
2963 else
2964 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2965 ~B43_NPHY_RFSEQMODE_CAOVER);
2966}
2967
2968/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2969static void b43_nphy_stop_playback(struct b43_wldev *dev)
2970{
2971 struct b43_phy_n *nphy = dev->phy.n;
2972 u16 tmp;
2973
2974 if (nphy->hang_avoid)
2975 b43_nphy_stay_in_carrier_search(dev, 1);
2976
2977 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2978 if (tmp & 0x1)
2979 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2980 else if (tmp & 0x2)
2981 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2982
2983 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2984
2985 if (nphy->bb_mult_save & 0x80000000) {
2986 tmp = nphy->bb_mult_save & 0xFFFF;
2987 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2988 nphy->bb_mult_save = 0;
2989 }
2990
2991 if (nphy->hang_avoid)
2992 b43_nphy_stay_in_carrier_search(dev, 0);
2993}
2994
2995/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2996static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2997 struct nphy_txgains target,
2998 struct nphy_iqcal_params *params)
2999{
3000 int i, j, indx;
3001 u16 gain;
3002
3003 if (dev->phy.rev >= 3) {
3004 params->txgm = target.txgm[core];
3005 params->pga = target.pga[core];
3006 params->pad = target.pad[core];
3007 params->ipa = target.ipa[core];
3008 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3009 (params->pad << 4) | (params->ipa);
3010 for (j = 0; j < 5; j++)
3011 params->ncorr[j] = 0x79;
3012 } else {
3013 gain = (target.pad[core]) | (target.pga[core] << 4) |
3014 (target.txgm[core] << 8);
3015
3016 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3017 1 : 0;
3018 for (i = 0; i < 9; i++)
3019 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3020 break;
3021 i = min(i, 8);
3022
3023 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3024 params->pga = tbl_iqcal_gainparams[indx][i][2];
3025 params->pad = tbl_iqcal_gainparams[indx][i][3];
3026 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3027 (params->pad << 2);
3028 for (j = 0; j < 4; j++)
3029 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3030 }
3031}
3032
884a5228 3033/**************************************************
104cfa88 3034 * Tx and Rx
884a5228 3035 **************************************************/
5f6393ec 3036
884a5228
RM		 3037static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3038{//TODO
3039}
59af099b 3040
884a5228
RM		 3041static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3042 bool ignore_tssi)
3043{//TODO
3044 return B43_TXPWR_RES_DONE;
3045}
59af099b 3046
161d540c
RM		 3047/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3048static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3049{
3050 struct b43_phy_n *nphy = dev->phy.n;
3051 u8 i;
c9c0d9ec
RM		 3052 u16 bmask, val, tmp;
3053 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3054
161d540c
RM		 3055 if (nphy->hang_avoid)
3056 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3057
161d540c
RM		 3058 nphy->txpwrctrl = enable;
3059 if (!enable) {
c9c0d9ec
RM		 3060 if (dev->phy.rev >= 3 &&
3061 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3062 (B43_NPHY_TXPCTL_CMD_COEFF |
3063 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3064 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3065 /* We disable enabled TX pwr ctl, save it's state */
3066 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3067 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3068 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3069 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3070 }
59af099b 3071
161d540c
RM		 3072 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3073 for (i = 0; i < 84; i++)
3074 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3075
161d540c
RM		 3076 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3077 for (i = 0; i < 84; i++)
3078 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3079
161d540c
RM		 3080 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3081 if (dev->phy.rev >= 3)
3082 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3083 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3084
161d540c
RM		 3085 if (dev->phy.rev >= 3) {
3086 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3087 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3088 } else {
3089 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3090 }
10a79873 3091
161d540c
RM		 3092 if (dev->phy.rev == 2)
3093 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3094 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3095 else if (dev->phy.rev < 2)
3096 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3097 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3098
c9c0d9ec
RM		 3099 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3100 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3101 } else {
c9c0d9ec
RM		 3102 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3103 nphy->adj_pwr_tbl);
3104 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3105 nphy->adj_pwr_tbl);
10a79873 3106
c9c0d9ec
RM		 3107 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3108 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3109 /* wl does useless check for "enable" param here */
3110 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3111 if (dev->phy.rev >= 3) {
3112 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3113 if (val)
3114 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3115 }
3116 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3117
c9c0d9ec
RM		 3118 if (band == IEEE80211_BAND_5GHZ) {
3119 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3120 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3121 if (dev->phy.rev > 1)
3122 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3123 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3124 0x64);
3125 }
10a79873 3126
c9c0d9ec
RM		 3127 if (dev->phy.rev >= 3) {
3128 if (nphy->tx_pwr_idx[0] != 128 &&
3129 nphy->tx_pwr_idx[1] != 128) {
3130 /* Recover TX pwr ctl state */
3131 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3132 ~B43_NPHY_TXPCTL_CMD_INIT,
3133 nphy->tx_pwr_idx[0]);
3134 if (dev->phy.rev > 1)
3135 b43_phy_maskset(dev,
3136 B43_NPHY_TXPCTL_INIT,
3137 ~0xff, nphy->tx_pwr_idx[1]);
3138 }
3139 }
10a79873 3140
c9c0d9ec
RM		 3141 if (dev->phy.rev >= 3) {
3142 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3143 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3144 } else {
3145 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3146 }
10a79873 3147
c9c0d9ec
RM		 3148 if (dev->phy.rev == 2)
3149 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3150 else if (dev->phy.rev < 2)
3151 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3152
c9c0d9ec
RM		 3153 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3154 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3155
c002831a 3156 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3157 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3158 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3159 }
10a79873 3160 }
10a79873 3161
161d540c
RM		 3162 if (nphy->hang_avoid)
3163 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3164}
3165
161d540c 3166/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3167static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 3168{
3169 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3170 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3171
161d540c
RM		 3172 u8 txpi[2], bbmult, i;
3173 u16 tmp, radio_gain, dac_gain;
3174 u16 freq = dev->phy.channel_freq;
3175 u32 txgain;
3176 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3177
3178 if (nphy->hang_avoid)
161d540c 3179 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3180
dd5f13b8
RM		 3181 if (dev->phy.rev >= 7) {
3182 txpi[0] = txpi[1] = 30;
3183 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3184 txpi[0] = 40;
3185 txpi[1] = 40;
3186 } else if (sprom->revision < 4) {
3187 txpi[0] = 72;
3188 txpi[1] = 72;
3189 } else {
3190 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3191 txpi[0] = sprom->txpid2g[0];
3192 txpi[1] = sprom->txpid2g[1];
3193 } else if (freq >= 4900 && freq < 5100) {
3194 txpi[0] = sprom->txpid5gl[0];
3195 txpi[1] = sprom->txpid5gl[1];
3196 } else if (freq >= 5100 && freq < 5500) {
3197 txpi[0] = sprom->txpid5g[0];
3198 txpi[1] = sprom->txpid5g[1];
3199 } else if (freq >= 5500) {
3200 txpi[0] = sprom->txpid5gh[0];
3201 txpi[1] = sprom->txpid5gh[1];
3202 } else {
3203 txpi[0] = 91;
3204 txpi[1] = 91;
6dcd9d91
RM		 3205 }
3206 }
dd5f13b8 3207 if (dev->phy.rev < 7 &&
9bd28571 3208 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3209 txpi[0] = txpi[1] = 91;
6dcd9d91 3210
161d540c
RM		 3211 /*
3212 for (i = 0; i < 2; i++) {
3213 nphy->txpwrindex[i].index_internal = txpi[i];
3214 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3215 }
161d540c 3216 */
75377b24 3217
161d540c 3218 for (i = 0; i < 2; i++) {
aeab5751
RM		 3219 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3220
3221 if (dev->phy.rev >= 3)
161d540c 3222 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3223 else
161d540c 3224 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3225
dd5f13b8
RM		 3226 if (dev->phy.rev >= 7)
3227 dac_gain = (txgain >> 8) & 0x7;
3228 else
3229 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3230 bbmult = txgain & 0xFF;
75377b24 3231
161d540c
RM		 3232 if (dev->phy.rev >= 3) {
3233 if (i == 0)
3234 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3235 else
3236 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3237 } else {
3238 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3239 }
75377b24 3240
161d540c
RM		 3241 if (i == 0)
3242 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3243 else
3244 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3245
44f4008b 3246 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3247
44f4008b 3248 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3249 if (i == 0)
3250 tmp = (tmp & 0x00FF) | (bbmult << 8);
3251 else
3252 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3253 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3254
0eff8fcd
RM		 3255 if (b43_nphy_ipa(dev)) {
3256 u32 tmp32;
3257 u16 reg = (i == 0) ?
3258 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3259 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3260 576 + txpi[i]));
0eff8fcd
RM		 3261 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3262 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3263 }
3264 }
75377b24 3265
161d540c 3266 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3267
161d540c
RM		 3268 if (nphy->hang_avoid)
3269 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3270}
67cbc3ed 3271
3dda07b6
RM		 3272static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3273{
3274 struct b43_phy *phy = &dev->phy;
3275
3276 u8 core;
3277 u16 r; /* routing */
3278
3279 if (phy->rev >= 7) {
3280 for (core = 0; core < 2; core++) {
3281 r = core ? 0x190 : 0x170;
3282 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3283 b43_radio_write(dev, r + 0x5, 0x5);
3284 b43_radio_write(dev, r + 0x9, 0xE);
3285 if (phy->rev != 5)
3286 b43_radio_write(dev, r + 0xA, 0);
3287 if (phy->rev != 7)
3288 b43_radio_write(dev, r + 0xB, 1);
3289 else
3290 b43_radio_write(dev, r + 0xB, 0x31);
3291 } else {
3292 b43_radio_write(dev, r + 0x5, 0x9);
3293 b43_radio_write(dev, r + 0x9, 0xC);
3294 b43_radio_write(dev, r + 0xB, 0x0);
3295 if (phy->rev != 5)
3296 b43_radio_write(dev, r + 0xA, 1);
3297 else
3298 b43_radio_write(dev, r + 0xA, 0x31);
3299 }
3300 b43_radio_write(dev, r + 0x6, 0);
3301 b43_radio_write(dev, r + 0x7, 0);
3302 b43_radio_write(dev, r + 0x8, 3);
3303 b43_radio_write(dev, r + 0xC, 0);
3304 }
3305 } else {
3306 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3307 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3308 else
3309 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3310 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3311 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3312
3313 for (core = 0; core < 2; core++) {
3314 r = core ? B2056_TX1 : B2056_TX0;
3315
3316 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3317 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3318 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3319 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3320 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3321 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3322 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3323 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3324 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3325 0x5);
3326 if (phy->rev != 5)
3327 b43_radio_write(dev, r | B2056_TX_TSSIA,
3328 0x00);
3329 if (phy->rev >= 5)
3330 b43_radio_write(dev, r | B2056_TX_TSSIG,
3331 0x31);
3332 else
3333 b43_radio_write(dev, r | B2056_TX_TSSIG,
3334 0x11);
3335 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3336 0xE);
3337 } else {
3338 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3339 0x9);
3340 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3341 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3342 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3343 0xC);
3344 }
3345 }
3346 }
3347}
3348
3349/*
3350 * Stop radio and transmit known signal. Then check received signal strength to
3351 * get TSSI (Transmit Signal Strength Indicator).
3352 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3353 */
3354static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3355{
3356 struct b43_phy *phy = &dev->phy;
3357 struct b43_phy_n *nphy = dev->phy.n;
3358
3359 u32 tmp;
3360 s32 rssi[4] = { };
3361
3362 /* TODO: check if we can transmit */
3363
3364 if (b43_nphy_ipa(dev))
3365 b43_nphy_ipa_internal_tssi_setup(dev);
3366
3367 if (phy->rev >= 7)
78ae7532 3368 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3369 else if (phy->rev >= 3)
78ae7532 3370 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3371
3372 b43_nphy_stop_playback(dev);
3373 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3374 udelay(20);
a3764ef7 3375 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3376 b43_nphy_stop_playback(dev);
a3764ef7 3377 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3378
3379 if (phy->rev >= 7)
78ae7532 3380 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3381 else if (phy->rev >= 3)
78ae7532 3382 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3383
3384 if (phy->rev >= 3) {
3385 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3386 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3387 } else {
3388 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3389 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3390 }
3391 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3392 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3393}
3394
d3fd8bf7
RM		 3395/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3396static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3397{
3398 struct b43_phy_n *nphy = dev->phy.n;
3399
3400 u8 idx, delta;
3401 u8 i, stf_mode;
3402
55757927
RM		 3403 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3404 * 21 groups, each containing 4 entries.
3405 *
3406 * First group has entries for CCK modulation.
3407 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3408 *
3409 * Group 0 is for CCK
3410 * Groups 1..4 use BPSK (group per coding rate)
3411 * Groups 5..8 use QPSK (group per coding rate)
3412 * Groups 9..12 use 16-QAM (group per coding rate)
3413 * Groups 13..16 use 64-QAM (group per coding rate)
3414 * Groups 17..20 are unknown
3415 */
3416
d3fd8bf7
RM		 3417 for (i = 0; i < 4; i++)
3418 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3419
3420 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3421 delta = 0;
3422 switch (stf_mode) {
3423 case 0:
3424 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3425 idx = 68;
3426 } else {
3427 delta = 1;
3428 idx = dev->phy.is_40mhz ? 52 : 4;
3429 }
3430 break;
3431 case 1:
3432 idx = dev->phy.is_40mhz ? 76 : 28;
3433 break;
3434 case 2:
3435 idx = dev->phy.is_40mhz ? 84 : 36;
3436 break;
3437 case 3:
3438 idx = dev->phy.is_40mhz ? 92 : 44;
3439 break;
3440 }
3441
3442 for (i = 0; i < 20; i++) {
3443 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3444 nphy->tx_power_offset[idx];
3445 if (i == 0)
3446 idx += delta;
3447 if (i == 14)
3448 idx += 1 - delta;
3449 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3450 i == 13)
3451 idx += 1;
3452 }
3453 }
3454}
3455
3456/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3457static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3458{
3459 struct b43_phy_n *nphy = dev->phy.n;
3460 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3461
3462 s16 a1[2], b0[2], b1[2];
3463 u8 idle[2];
3464 s8 target[2];
3465 s32 num, den, pwr;
3466 u32 regval[64];
3467
3468 u16 freq = dev->phy.channel_freq;
3469 u16 tmp;
3470 u16 r; /* routing */
3471 u8 i, c;
3472
3473 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3474 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3475 b43_read32(dev, B43_MMIO_MACCTL);
3476 udelay(1);
3477 }
3478
3479 if (nphy->hang_avoid)
3480 b43_nphy_stay_in_carrier_search(dev, true);
3481
3482 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3483 if (dev->phy.rev >= 3)
3484 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3485 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3486 else
3487 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3488 B43_NPHY_TXPCTL_CMD_PCTLEN);
3489
3490 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3491 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3492
3493 if (sprom->revision < 4) {
3494 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3495 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3496 target[0] = target[1] = 52;
3497 a1[0] = a1[1] = -424;
3498 b0[0] = b0[1] = 5612;
3499 b1[0] = b1[1] = -1393;
3500 } else {
3501 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3502 for (c = 0; c < 2; c++) {
3503 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3504 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3505 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3506 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3507 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3508 }
3509 } else if (freq >= 4900 && freq < 5100) {
3510 for (c = 0; c < 2; c++) {
3511 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3512 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3513 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3514 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3515 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3516 }
3517 } else if (freq >= 5100 && freq < 5500) {
3518 for (c = 0; c < 2; c++) {
3519 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3520 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3521 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3522 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3523 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3524 }
3525 } else if (freq >= 5500) {
3526 for (c = 0; c < 2; c++) {
3527 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3528 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3529 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3530 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3531 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3532 }
3533 } else {
3534 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3535 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3536 target[0] = target[1] = 52;
3537 a1[0] = a1[1] = -424;
3538 b0[0] = b0[1] = 5612;
3539 b1[0] = b1[1] = -1393;
3540 }
3541 }
3542 /* target[0] = target[1] = nphy->tx_power_max; */
3543
3544 if (dev->phy.rev >= 3) {
3545 if (sprom->fem.ghz2.tssipos)
3546 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3547 if (dev->phy.rev >= 7) {
3548 for (c = 0; c < 2; c++) {
3549 r = c ? 0x190 : 0x170;
3550 if (b43_nphy_ipa(dev))
3551 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3552 }
3553 } else {
3554 if (b43_nphy_ipa(dev)) {
3555 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3556 b43_radio_write(dev,
3557 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3558 b43_radio_write(dev,
3559 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3560 } else {
3561 b43_radio_write(dev,
3562 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3563 b43_radio_write(dev,
3564 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3565 }
3566 }
3567 }
3568
3569 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3570 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3571 b43_read32(dev, B43_MMIO_MACCTL);
3572 udelay(1);
3573 }
3574
3575 if (dev->phy.rev >= 7) {
3576 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3577 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3578 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3579 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3580 } else {
3581 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3582 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3583 if (dev->phy.rev > 1)
3584 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3585 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3586 }
3587
3588 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3589 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3590
3591 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3592 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3593 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3594 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3595 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3596 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3597 B43_NPHY_TXPCTL_ITSSI_BINF);
3598 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3599 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3600 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3601
3602 for (c = 0; c < 2; c++) {
3603 for (i = 0; i < 64; i++) {
3604 num = 8 * (16 * b0[c] + b1[c] * i);
3605 den = 32768 + a1[c] * i;
3606 pwr = max((4 * num + den / 2) / den, -8);
3607 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3608 pwr = max(pwr, target[c] + 1);
3609 regval[i] = pwr;
3610 }
3611 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3612 }
3613
3614 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3615 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3616 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3617
3618 if (nphy->hang_avoid)
3619 b43_nphy_stay_in_carrier_search(dev, false);
3620}
3621
0eff8fcd
RM		 3622static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3623{
3624 struct b43_phy *phy = &dev->phy;
67cbc3ed 3625
0eff8fcd 3626 const u32 *table = NULL;
0eff8fcd
RM		 3627 u32 rfpwr_offset;
3628 u8 pga_gain;
3629 int i;
0eff8fcd 3630
aeab5751 3631 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3632 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3633 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3634
3635 if (phy->rev >= 3) {
3636#if 0
3637 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3638#endif
0eff8fcd
RM		 3639
3640 for (i = 0; i < 128; i++) {
3641 pga_gain = (table[i] >> 24) & 0xF;
3642 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3643 rfpwr_offset =
3644 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3645 else
34c5cf20
RM		 3646 rfpwr_offset =
3647 0; /* FIXME */
0eff8fcd
RM		 3648 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3649 rfpwr_offset);
3650 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3651 rfpwr_offset);
3652 }
67cbc3ed
RM		 3653 }
3654}
3655
e50cbcf6
RM		 3656/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3657static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3658{
e50cbcf6
RM		 3659 struct b43_phy_n *nphy = dev->phy.n;
3660 enum ieee80211_band band;
3661 u16 tmp;
95b66bad 3662
e50cbcf6
RM		 3663 if (!enable) {
3664 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3665 B43_NPHY_RFCTL_INTC1);
3666 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3667 B43_NPHY_RFCTL_INTC2);
3668 band = b43_current_band(dev->wl);
3669 if (dev->phy.rev >= 3) {
3670 if (band == IEEE80211_BAND_5GHZ)
3671 tmp = 0x600;
3672 else
3673 tmp = 0x480;
3674 } else {
3675 if (band == IEEE80211_BAND_5GHZ)
3676 tmp = 0x180;
3677 else
3678 tmp = 0x120;
3679 }
3680 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3681 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3682 } else {
3683 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3684 nphy->rfctrl_intc1_save);
3685 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3686 nphy->rfctrl_intc2_save);
95b66bad 3687 }
95b66bad
MB		 3688}
3689
fe3e46e8
RM		 3690/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3691static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3692{
3693 u16 tmp;
3c95627d 3694
fe3e46e8 3695 if (dev->phy.rev >= 3) {
c002831a 3696 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3697 tmp = 4;
3698 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3699 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3700 }
76b002bd 3701
fe3e46e8
RM		 3702 tmp = 1;
3703 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3704 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3705 }
3706}
76b002bd 3707
2faa6b83
RM		 3708/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3709static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3710 u16 samps, u8 time, bool wait)
3c95627d 3711{
2faa6b83
RM		 3712 int i;
3713 u16 tmp;
3c95627d 3714
2faa6b83
RM		 3715 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3716 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3717 if (wait)
3718 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3719 else
2faa6b83 3720 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3721
2faa6b83 3722 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3723
2faa6b83
RM		 3724 for (i = 1000; i; i--) {
3725 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3726 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3727 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3728 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3729 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3730 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3731 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3732 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3733
2faa6b83
RM		 3734 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3735 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3736 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3737 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3738 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3739 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3740 return;
3c95627d 3741 }
2faa6b83 3742 udelay(10);
3c95627d 3743 }
2faa6b83 3744 memset(est, 0, sizeof(*est));
3c95627d
RM		 3745}
3746
a67162ab
RM		 3747/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3748static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3749 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3750{
a67162ab
RM		 3751 if (write) {
3752 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3753 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3754 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3755 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3756 } else {
a67162ab
RM		 3757 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3758 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3759 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3760 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3761 }
3762}
6e3b15a9 3763
c7455cf9
RM		 3764#if 0
3765/* Ready but not used anywhere */
026816fc
RM		 3766/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3767static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3768{
3769 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3770
026816fc
RM		 3771 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3772 if (core == 0) {
3773 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3774 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3775 } else {
3776 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3777 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3778 }
3779 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3780 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3781 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3782 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3783 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3784 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3785 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3786 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3787}
6e3b15a9 3788
026816fc
RM		 3789/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3790static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3791{
3792 u8 rxval, txval;
3793 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3794
026816fc
RM		 3795 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3796 if (core == 0) {
3797 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3798 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3799 } else {
3800 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3801 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3802 }
3803 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3804 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3805 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3806 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3807 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3808 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3809 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3810 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3811
026816fc
RM		 3812 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3813 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3814
acd82aa8
LF		 3815 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3816 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3817 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3818 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3819 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3820 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3821 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3822 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3823 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3824
026816fc
RM		 3825 if (core == 0) {
3826 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3827 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3828 } else {
3829 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3830 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3831 }
6e3b15a9 3832
89e43dad 3833 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3834 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3835 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3836
026816fc
RM		 3837 if (core == 0) {
3838 rxval = 1;
3839 txval = 8;
3840 } else {
3841 rxval = 4;
3842 txval = 2;
6e3b15a9 3843 }
89e43dad
RM		 3844 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3845 core + 1);
3846 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3847 2 - core);
99b82c41 3848}
c7455cf9 3849#endif
99b82c41 3850
34a56f2c
RM		 3851/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3852static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3853{
3854 int i;
34a56f2c
RM		 3855 s32 iq;
3856 u32 ii;
3857 u32 qq;
3858 int iq_nbits, qq_nbits;
3859 int arsh, brsh;
3860 u16 tmp, a, b;
3861
3862 struct nphy_iq_est est;
3863 struct b43_phy_n_iq_comp old;
3864 struct b43_phy_n_iq_comp new = { };
3865 bool error = false;
3866
3867 if (mask == 0)
3868 return;
3869
3870 b43_nphy_rx_iq_coeffs(dev, false, &old);
3871 b43_nphy_rx_iq_coeffs(dev, true, &new);
3872 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3873 new = old;
3874
dfb4aa5d 3875 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3876 if (i == 0 && (mask & 1)) {
3877 iq = est.iq0_prod;
3878 ii = est.i0_pwr;
3879 qq = est.q0_pwr;
3880 } else if (i == 1 && (mask & 2)) {
3881 iq = est.iq1_prod;
3882 ii = est.i1_pwr;
3883 qq = est.q1_pwr;
dfb4aa5d 3884 } else {
34a56f2c 3885 continue;
dfb4aa5d 3886 }
dfb4aa5d 3887
34a56f2c
RM		 3888 if (ii + qq < 2) {
3889 error = true;
3890 break;
3891 }
dfb4aa5d 3892
34a56f2c
RM		 3893 iq_nbits = fls(abs(iq));
3894 qq_nbits = fls(qq);
dfb4aa5d 3895
34a56f2c
RM		 3896 arsh = iq_nbits - 20;
3897 if (arsh >= 0) {
3898 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3899 tmp = ii >> arsh;
3900 } else {
3901 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3902 tmp = ii << -arsh;
3903 }
3904 if (tmp == 0) {
3905 error = true;
3906 break;
3907 }
3908 a /= tmp;
dfb4aa5d 3909
34a56f2c
RM		 3910 brsh = qq_nbits - 11;
3911 if (brsh >= 0) {
3912 b = (qq << (31 - qq_nbits));
3913 tmp = ii >> brsh;
dfb4aa5d 3914 } else {
34a56f2c
RM		 3915 b = (qq << (31 - qq_nbits));
3916 tmp = ii << -brsh;
3917 }
3918 if (tmp == 0) {
3919 error = true;
3920 break;
dfb4aa5d 3921 }
34a56f2c 3922 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3923
34a56f2c
RM		 3924 if (i == 0 && (mask & 0x1)) {
3925 if (dev->phy.rev >= 3) {
3926 new.a0 = a & 0x3FF;
3927 new.b0 = b & 0x3FF;
3928 } else {
3929 new.a0 = b & 0x3FF;
3930 new.b0 = a & 0x3FF;
3931 }
3932 } else if (i == 1 && (mask & 0x2)) {
3933 if (dev->phy.rev >= 3) {
3934 new.a1 = a & 0x3FF;
3935 new.b1 = b & 0x3FF;
3936 } else {
3937 new.a1 = b & 0x3FF;
3938 new.b1 = a & 0x3FF;
3939 }
3940 }
dfb4aa5d 3941 }
dfb4aa5d 3942
34a56f2c
RM		 3943 if (error)
3944 new = old;
dfb4aa5d 3945
34a56f2c
RM		 3946 b43_nphy_rx_iq_coeffs(dev, true, &new);
3947}
dfb4aa5d 3948
09146400
RM		 3949/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3950static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3951{
3952 u16 array[4];
44f4008b 3953 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3954
3955 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3956 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3957 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3958 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3959}
3960
9442e5b5
RM		 3961/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3962static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3963{
3964 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3965
204a665b 3966 u8 channel = dev->phy.channel;
9442e5b5
RM		 3967 int tone[2] = { 57, 58 };
3968 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3969
9442e5b5 3970 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3971
9442e5b5
RM		 3972 if (nphy->hang_avoid)
3973 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3974
9442e5b5
RM		 3975 if (nphy->gband_spurwar_en) {
3976 /* TODO: N PHY Adjust Analog Pfbw (7) */
3977 if (channel == 11 && dev->phy.is_40mhz)
3978 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3979 else
3980 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3981 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 3982 }
3983
9442e5b5
RM		 3984 if (nphy->aband_spurwar_en) {
3985 if (channel == 54) {
3986 tone[0] = 0x20;
3987 noise[0] = 0x25F;
3988 } else if (channel == 38 || channel == 102 || channel == 118) {
3989 if (0 /* FIXME */) {
3990 tone[0] = 0x20;
3991 noise[0] = 0x21F;
3992 } else {
3993 tone[0] = 0;
3994 noise[0] = 0;
90b9738d 3995 }
9442e5b5
RM		 3996 } else if (channel == 134) {
3997 tone[0] = 0x20;
3998 noise[0] = 0x21F;
3999 } else if (channel == 151) {
4000 tone[0] = 0x10;
4001 noise[0] = 0x23F;
4002 } else if (channel == 153 || channel == 161) {
4003 tone[0] = 0x30;
4004 noise[0] = 0x23F;
4005 } else {
4006 tone[0] = 0;
4007 noise[0] = 0;
90b9738d 4008 }
90b9738d 4009
9442e5b5
RM		 4010 if (!tone[0] && !noise[0])
4011 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4012 else
9442e5b5
RM		 4013 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4014 }
90b9738d 4015
9442e5b5
RM		 4016 if (nphy->hang_avoid)
4017 b43_nphy_stay_in_carrier_search(dev, 0);
4018}
90b9738d 4019
5ecab603
RM		 4020/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4021static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4022{
4023 struct b43_phy_n *nphy = dev->phy.n;
4024 int i, j;
4025 u32 tmp;
4026 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4027
5ecab603 4028 u16 buffer[7];
90b9738d 4029
5ecab603
RM		 4030 if (nphy->hang_avoid)
4031 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4032
5ecab603 4033 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4034
5ecab603
RM		 4035 for (i = 0; i < 2; i++) {
4036 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4037 (buffer[i * 2 + 1] & 0x3FF);
4038 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4039 (((i + 26) << 10) | 320));
4040 for (j = 0; j < 128; j++) {
4041 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4042 ((tmp >> 16) & 0xFFFF));
4043 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4044 (tmp & 0xFFFF));
90b9738d 4045 }
90b9738d 4046 }
90b9738d 4047
5ecab603
RM		 4048 for (i = 0; i < 2; i++) {
4049 tmp = buffer[5 + i];
4050 real_part = (tmp >> 8) & 0xFF;
4051 imag_part = (tmp & 0xFF);
4052 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4053 (((i + 26) << 10) | 448));
90b9738d 4054
5ecab603
RM		 4055 if (dev->phy.rev >= 3) {
4056 cur_real = real_part;
4057 cur_imag = imag_part;
4058 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4059 }
4cb99775 4060
5ecab603
RM		 4061 for (j = 0; j < 128; j++) {
4062 if (dev->phy.rev < 3) {
4063 cur_real = (real_part * loscale[j] + 128) >> 8;
4064 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4065 tmp = ((cur_real & 0xFF) << 8) |
4066 (cur_imag & 0xFF);
4067 }
4068 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4069 ((tmp >> 16) & 0xFFFF));
4070 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4071 (tmp & 0xFFFF));
4072 }
90b9738d 4073 }
4cb99775 4074
4cb99775 4075 if (dev->phy.rev >= 3) {
5ecab603
RM		 4076 b43_shm_write16(dev, B43_SHM_SHARED,
4077 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4078 b43_shm_write16(dev, B43_SHM_SHARED,
4079 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4080 }
90b9738d 4081
5ecab603
RM		 4082 if (nphy->hang_avoid)
4083 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4084}
4085
42e1547e
RM		 4086/*
4087 * Restore RSSI Calibration
4088 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4089 */
4090static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4091{
4092 struct b43_phy_n *nphy = dev->phy.n;
4093
4094 u16 *rssical_radio_regs = NULL;
4095 u16 *rssical_phy_regs = NULL;
4096
4097 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4098 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4099 return;
4100 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4101 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4102 } else {
204a665b 4103 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4104 return;
4105 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4106 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4107 }
4108
9a98979e
RM		 4109 if (dev->phy.rev >= 7) {
4110 } else {
4111 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4112 rssical_radio_regs[0]);
4113 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4114 rssical_radio_regs[1]);
4115 }
42e1547e
RM		 4116
4117 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4118 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4119 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4120 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4121
4122 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4123 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4124 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4125 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4126
4127 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4128 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4129 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4130 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4131}
4132
c4a92003
RM		 4133/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4134static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4135{
4136 struct b43_phy_n *nphy = dev->phy.n;
4137 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4138 u16 tmp;
4139 u8 offset, i;
c4a92003
RM		 4140
4141 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4142 for (i = 0; i < 2; i++) {
4143 tmp = (i == 0) ? 0x2000 : 0x3000;
4144 offset = i * 11;
4145
0c201cfb
RM		 4146 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4147 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4148 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4149 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4150 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4151 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4152 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4153 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4154 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4155 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4156 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4157
4158 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4159 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4160 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4161 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4162 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4163 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4164 if (nphy->ipa5g_on) {
0c201cfb
RM		 4165 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4166 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4167 } else {
0c201cfb
RM		 4168 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4169 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4170 }
0c201cfb 4171 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4172 } else {
0c201cfb
RM		 4173 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4174 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4175 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4176 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4177 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4178 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4179 if (nphy->ipa2g_on) {
0c201cfb
RM		 4180 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4181 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4182 (dev->phy.rev < 5) ? 0x11 : 0x01);
4183 } else {
0c201cfb
RM		 4184 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4185 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4186 }
4187 }
0c201cfb
RM		 4188 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4189 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4190 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4191 }
c4a92003 4192 } else {
0c201cfb
RM		 4193 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4194 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4195
0c201cfb
RM		 4196 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4197 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4198
0c201cfb
RM		 4199 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4200 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4201
0c201cfb
RM		 4202 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4203 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4204
0c201cfb
RM		 4205 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4206 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4207
4208 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4209 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4210 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4211 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4212 } else {
0c201cfb
RM		 4213 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4214 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4215 }
4216
4217 if (dev->phy.rev < 2) {
4218 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4219 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4220 } else {
4221 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4222 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4223 }
4224 }
4225}
4226
de7ed0c6
RM		 4227/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4228static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4229{
4230 struct b43_phy_n *nphy = dev->phy.n;
4231 int i;
4232 u16 scale, entry;
4233
4234 u16 tmp = nphy->txcal_bbmult;
4235 if (core == 0)
4236 tmp >>= 8;
4237 tmp &= 0xff;
4238
4239 for (i = 0; i < 18; i++) {
4240 scale = (ladder_lo[i].percent * tmp) / 100;
4241 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4242 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4243
4244 scale = (ladder_iq[i].percent * tmp) / 100;
4245 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4246 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4247 }
4248}
4249
45ca697e
RM		 4250/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4251static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4252{
4253 int i;
4254 for (i = 0; i < 15; i++)
4255 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4256 tbl_tx_filter_coef_rev4[2][i]);
4257}
4258
4259/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4260static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4261{
4262 int i, j;
4263 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4264 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4265
4266 for (i = 0; i < 3; i++)
4267 for (j = 0; j < 15; j++)
4268 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4269 tbl_tx_filter_coef_rev4[i][j]);
4270
4271 if (dev->phy.is_40mhz) {
4272 for (j = 0; j < 15; j++)
4273 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4274 tbl_tx_filter_coef_rev4[3][j]);
4275 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4276 for (j = 0; j < 15; j++)
4277 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4278 tbl_tx_filter_coef_rev4[5][j]);
4279 }
4280
4281 if (dev->phy.channel == 14)
4282 for (j = 0; j < 15; j++)
4283 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4284 tbl_tx_filter_coef_rev4[6][j]);
4285}
4286
b0022e15
RM		 4287/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4288static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4289{
4290 struct b43_phy_n *nphy = dev->phy.n;
4291
4292 u16 curr_gain[2];
4293 struct nphy_txgains target;
4294 const u32 *table = NULL;
4295
161d540c 4296 if (!nphy->txpwrctrl) {
b0022e15
RM		 4297 int i;
4298
4299 if (nphy->hang_avoid)
4300 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4301 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4302 if (nphy->hang_avoid)
4303 b43_nphy_stay_in_carrier_search(dev, false);
4304
4305 for (i = 0; i < 2; ++i) {
4306 if (dev->phy.rev >= 3) {
4307 target.ipa[i] = curr_gain[i] & 0x000F;
4308 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4309 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4310 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4311 } else {
4312 target.ipa[i] = curr_gain[i] & 0x0003;
4313 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4314 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4315 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4316 }
4317 }
4318 } else {
4319 int i;
4320 u16 index[2];
4321 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4322 B43_NPHY_TXPCTL_STAT_BIDX) >>
4323 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4324 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4325 B43_NPHY_TXPCTL_STAT_BIDX) >>
4326 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4327
4328 for (i = 0; i < 2; ++i) {
aeab5751 4329 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4330 if (dev->phy.rev >= 3) {
b0022e15
RM		 4331 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4332 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4333 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4334 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4335 } else {
b0022e15
RM		 4336 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4337 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4338 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4339 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4340 }
4341 }
4342 }
4343
4344 return target;
4345}
4346
e53de674
RM		 4347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4348static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4349{
4350 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4351
4352 if (dev->phy.rev >= 3) {
4353 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4354 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4355 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4356 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4357 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4358 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4359 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4360 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4361 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4362 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4363 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4364 b43_nphy_reset_cca(dev);
4365 } else {
4366 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4367 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4368 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4369 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4370 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4371 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4372 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4373 }
4374}
4375
4376/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4377static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4378{
4379 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4380 u16 tmp;
4381
4382 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4383 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4384 if (dev->phy.rev >= 3) {
4385 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4386 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4387
4388 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4389 regs[2] = tmp;
4390 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4391
4392 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4393 regs[3] = tmp;
4394 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4395
4396 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4397 b43_phy_mask(dev, B43_NPHY_BBCFG,
4398 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4399
c643a66e 4400 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4401 regs[5] = tmp;
d41a3552 4402 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4403
4404 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4405 regs[6] = tmp;
d41a3552 4406 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4407 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4408 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4409
89e43dad
RM		 4410 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4411 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4412 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4413
4414 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4415 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4416 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4417 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4418 } else {
4419 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4420 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4421 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4422 regs[2] = tmp;
4423 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4424 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4425 regs[3] = tmp;
4426 tmp |= 0x2000;
d41a3552 4427 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4428 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4429 regs[4] = tmp;
4430 tmp |= 0x2000;
d41a3552 4431 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4432 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4433 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4434 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4435 tmp = 0x0180;
4436 else
4437 tmp = 0x0120;
4438 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4439 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4440 }
4441}
4442
bbc6dc12
RM		 4443/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4444static void b43_nphy_save_cal(struct b43_wldev *dev)
4445{
4446 struct b43_phy_n *nphy = dev->phy.n;
4447
4448 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4449 u16 *txcal_radio_regs = NULL;
902db91d 4450 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4451 u16 *table = NULL;
4452
4453 if (nphy->hang_avoid)
4454 b43_nphy_stay_in_carrier_search(dev, 1);
4455
4456 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4457 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4458 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4459 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4460 table = nphy->cal_cache.txcal_coeffs_2G;
4461 } else {
4462 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4463 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4464 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4465 table = nphy->cal_cache.txcal_coeffs_5G;
4466 }
4467
4468 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4469 /* TODO use some definitions */
4470 if (dev->phy.rev >= 3) {
4471 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4472 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4473 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4474 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4475 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4476 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4477 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4478 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4479 } else {
4480 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4481 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4482 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4483 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4484 }
204a665b
RM		 4485 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4486 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4487 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4488
4489 if (nphy->hang_avoid)
4490 b43_nphy_stay_in_carrier_search(dev, 0);
4491}
4492
2f258b74
RM		 4493/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4494static void b43_nphy_restore_cal(struct b43_wldev *dev)
4495{
4496 struct b43_phy_n *nphy = dev->phy.n;
4497
4498 u16 coef[4];
4499 u16 *loft = NULL;
4500 u16 *table = NULL;
4501
4502 int i;
4503 u16 *txcal_radio_regs = NULL;
4504 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4505
4506 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4507 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4508 return;
4509 table = nphy->cal_cache.txcal_coeffs_2G;
4510 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4511 } else {
204a665b 4512 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4513 return;
4514 table = nphy->cal_cache.txcal_coeffs_5G;
4515 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4516 }
4517
2581b143 4518 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4519
4520 for (i = 0; i < 4; i++) {
4521 if (dev->phy.rev >= 3)
4522 table[i] = coef[i];
4523 else
4524 coef[i] = 0;
4525 }
4526
2581b143
RM		 4527 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4528 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4529 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4530
4531 if (dev->phy.rev < 2)
4532 b43_nphy_tx_iq_workaround(dev);
4533
4534 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4535 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4536 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4537 } else {
4538 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4539 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4540 }
4541
4542 /* TODO use some definitions */
4543 if (dev->phy.rev >= 3) {
4544 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4545 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4546 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4547 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4548 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4549 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4550 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4551 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4552 } else {
4553 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4554 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4555 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4556 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4557 }
4558 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4559}
4560
fb43b8e2
RM		 4561/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4562static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4563 struct nphy_txgains target,
4564 bool full, bool mphase)
4565{
4566 struct b43_phy_n *nphy = dev->phy.n;
4567 int i;
4568 int error = 0;
4569 int freq;
4570 bool avoid = false;
4571 u8 length;
fb23d863 4572 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4573 const u16 *table;
4574 bool phy6or5x;
4575
4576 u16 buffer[11];
4577 u16 diq_start = 0;
4578 u16 save[2];
4579 u16 gain[2];
4580 struct nphy_iqcal_params params[2];
4581 bool updated[2] = { };
4582
4583 b43_nphy_stay_in_carrier_search(dev, true);
4584
4585 if (dev->phy.rev >= 4) {
4586 avoid = nphy->hang_avoid;
3db1cd5c 4587 nphy->hang_avoid = false;
fb43b8e2
RM		 4588 }
4589
9145834e 4590 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4591
4592 for (i = 0; i < 2; i++) {
4593 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4594 gain[i] = params[i].cal_gain;
4595 }
2581b143
RM		 4596
4597 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4598
4599 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4600 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4601
4602 phy6or5x = dev->phy.rev >= 6 ||
4603 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4604 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4605 if (phy6or5x) {
38bb9029
RM		 4606 if (dev->phy.is_40mhz) {
4607 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4608 tbl_tx_iqlo_cal_loft_ladder_40);
4609 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4610 tbl_tx_iqlo_cal_iqimb_ladder_40);
4611 } else {
4612 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4613 tbl_tx_iqlo_cal_loft_ladder_20);
4614 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4615 tbl_tx_iqlo_cal_iqimb_ladder_20);
4616 }
fb43b8e2
RM		 4617 }
4618
4619 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4620
aa4c7b2a 4621 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4622 freq = 2500;
4623 else
4624 freq = 5000;
4625
4626 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4627 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4628 0xFFFF, 0, true, false);
fb43b8e2 4629 else
59af099b 4630 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4631
4632 if (error == 0) {
4633 if (nphy->mphase_cal_phase_id > 2) {
4634 table = nphy->mphase_txcal_bestcoeffs;
4635 length = 11;
4636 if (dev->phy.rev < 3)
4637 length -= 2;
4638 } else {
4639 if (!full && nphy->txiqlocal_coeffsvalid) {
4640 table = nphy->txiqlocal_bestc;
4641 length = 11;
4642 if (dev->phy.rev < 3)
4643 length -= 2;
4644 } else {
4645 full = true;
4646 if (dev->phy.rev >= 3) {
4647 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4648 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4649 } else {
4650 table = tbl_tx_iqlo_cal_startcoefs;
4651 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4652 }
4653 }
4654 }
4655
2581b143 4656 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4657
4658 if (full) {
4659 if (dev->phy.rev >= 3)
4660 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4661 else
4662 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4663 } else {
4664 if (dev->phy.rev >= 3)
4665 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4666 else
4667 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4668 }
4669
4670 if (mphase) {
4671 count = nphy->mphase_txcal_cmdidx;
4672 numb = min(max,
4673 (u16)(count + nphy->mphase_txcal_numcmds));
4674 } else {
4675 count = 0;
4676 numb = max;
4677 }
4678
4679 for (; count < numb; count++) {
4680 if (full) {
4681 if (dev->phy.rev >= 3)
4682 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4683 else
4684 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4685 } else {
4686 if (dev->phy.rev >= 3)
4687 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4688 else
4689 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4690 }
4691
4692 core = (cmd & 0x3000) >> 12;
4693 type = (cmd & 0x0F00) >> 8;
4694
4695 if (phy6or5x && updated[core] == 0) {
4696 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4697 updated[core] = true;
fb43b8e2
RM		 4698 }
4699
4700 tmp = (params[core].ncorr[type] << 8) | 0x66;
4701 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4702
4703 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4704 buffer[0] = b43_ntab_read(dev,
4705 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4706 diq_start = buffer[0];
4707 buffer[0] = 0;
d41a3552
RM		 4708 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4709 0);
fb43b8e2
RM		 4710 }
4711
4712 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4713 for (i = 0; i < 2000; i++) {
4714 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4715 if (tmp & 0xC000)
4716 break;
4717 udelay(10);
4718 }
4719
9145834e
RM		 4720 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4721 buffer);
2581b143
RM		 4722 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4723 buffer);
fb43b8e2
RM		 4724
4725 if (type == 1 || type == 3 || type == 4)
4726 buffer[0] = diq_start;
4727 }
4728
4729 if (mphase)
4730 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4731
4732 last = (dev->phy.rev < 3) ? 6 : 7;
4733
4734 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4735 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4736 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4737 if (dev->phy.rev < 3) {
4738 buffer[0] = 0;
4739 buffer[1] = 0;
4740 buffer[2] = 0;
4741 buffer[3] = 0;
4742 }
2581b143
RM		 4743 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4744 buffer);
bc53e512 4745 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4746 buffer);
4747 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4748 buffer);
4749 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4750 buffer);
fb43b8e2
RM		 4751 length = 11;
4752 if (dev->phy.rev < 3)
4753 length -= 2;
9145834e
RM		 4754 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4755 nphy->txiqlocal_bestc);
fb43b8e2 4756 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4757 nphy->txiqlocal_chanspec.center_freq =
4758 dev->phy.channel_freq;
4759 nphy->txiqlocal_chanspec.channel_type =
4760 dev->phy.channel_type;
fb43b8e2
RM		 4761 } else {
4762 length = 11;
4763 if (dev->phy.rev < 3)
4764 length -= 2;
9145834e
RM		 4765 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4766 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4767 }
4768
53ae8e8c 4769 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4770 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4771 }
4772
e53de674 4773 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4774 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4775
4776 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4777 b43_nphy_tx_iq_workaround(dev);
4778
4779 if (dev->phy.rev >= 4)
4780 nphy->hang_avoid = avoid;
4781
4782 b43_nphy_stay_in_carrier_search(dev, false);
4783
4784 return error;
4785}
4786
984ff4ff
RM		 4787/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4788static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4789{
4790 struct b43_phy_n *nphy = dev->phy.n;
4791 u8 i;
4792 u16 buffer[7];
4793 bool equal = true;
4794
902db91d 4795 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4796 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4797 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4798 return;
4799
4800 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4801 for (i = 0; i < 4; i++) {
4802 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4803 equal = false;
4804 break;
4805 }
4806 }
4807
4808 if (!equal) {
4809 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4810 nphy->txiqlocal_bestc);
4811 for (i = 0; i < 4; i++)
4812 buffer[i] = 0;
4813 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4814 buffer);
4815 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4816 &nphy->txiqlocal_bestc[5]);
4817 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4818 &nphy->txiqlocal_bestc[5]);
4819 }
4820}
4821
15931e31
RM		 4822/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4823static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4824 struct nphy_txgains target, u8 type, bool debug)
4825{
4826 struct b43_phy_n *nphy = dev->phy.n;
4827 int i, j, index;
4828 u8 rfctl[2];
4829 u8 afectl_core;
4830 u16 tmp[6];
c7455cf9 4831 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4832 u32 real, imag;
4833 enum ieee80211_band band;
4834
4835 u8 use;
4836 u16 cur_hpf;
4837 u16 lna[3] = { 3, 3, 1 };
4838 u16 hpf1[3] = { 7, 2, 0 };
4839 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4840 u32 power[3] = { };
15931e31
RM		 4841 u16 gain_save[2];
4842 u16 cal_gain[2];
4843 struct nphy_iqcal_params cal_params[2];
4844 struct nphy_iq_est est;
4845 int ret = 0;
4846 bool playtone = true;
4847 int desired = 13;
4848
4849 b43_nphy_stay_in_carrier_search(dev, 1);
4850
4851 if (dev->phy.rev < 2)
984ff4ff 4852 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4853 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4854 for (i = 0; i < 2; i++) {
4855 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4856 cal_gain[i] = cal_params[i].cal_gain;
4857 }
2581b143 4858 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4859
4860 for (i = 0; i < 2; i++) {
4861 if (i == 0) {
4862 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4863 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4864 afectl_core = B43_NPHY_AFECTL_C1;
4865 } else {
4866 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4867 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4868 afectl_core = B43_NPHY_AFECTL_C2;
4869 }
4870
4871 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4872 tmp[2] = b43_phy_read(dev, afectl_core);
4873 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4874 tmp[4] = b43_phy_read(dev, rfctl[0]);
4875 tmp[5] = b43_phy_read(dev, rfctl[1]);
4876
4877 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4878 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4879 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4880 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4881 (1 - i));
4882 b43_phy_set(dev, afectl_core, 0x0006);
4883 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4884
4885 band = b43_current_band(dev->wl);
4886
4887 if (nphy->rxcalparams & 0xFF000000) {
4888 if (band == IEEE80211_BAND_5GHZ)
4889 b43_phy_write(dev, rfctl[0], 0x140);
4890 else
4891 b43_phy_write(dev, rfctl[0], 0x110);
4892 } else {
4893 if (band == IEEE80211_BAND_5GHZ)
4894 b43_phy_write(dev, rfctl[0], 0x180);
4895 else
4896 b43_phy_write(dev, rfctl[0], 0x120);
4897 }
4898
4899 if (band == IEEE80211_BAND_5GHZ)
4900 b43_phy_write(dev, rfctl[1], 0x148);
4901 else
4902 b43_phy_write(dev, rfctl[1], 0x114);
4903
4904 if (nphy->rxcalparams & 0x10000) {
4905 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4906 (i + 1));
4907 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4908 (2 - i));
4909 }
4910
30115c22 4911 for (j = 0; j < 4; j++) {
15931e31
RM		 4912 if (j < 3) {
4913 cur_lna = lna[j];
4914 cur_hpf1 = hpf1[j];
4915 cur_hpf2 = hpf2[j];
4916 } else {
4917 if (power[1] > 10000) {
4918 use = 1;
4919 cur_hpf = cur_hpf1;
4920 index = 2;
4921 } else {
4922 if (power[0] > 10000) {
4923 use = 1;
4924 cur_hpf = cur_hpf1;
4925 index = 1;
4926 } else {
4927 index = 0;
4928 use = 2;
4929 cur_hpf = cur_hpf2;
4930 }
4931 }
4932 cur_lna = lna[index];
4933 cur_hpf1 = hpf1[index];
4934 cur_hpf2 = hpf2[index];
4935 cur_hpf += desired - hweight32(power[index]);
4936 cur_hpf = clamp_val(cur_hpf, 0, 10);
4937 if (use == 1)
4938 cur_hpf1 = cur_hpf;
4939 else
4940 cur_hpf2 = cur_hpf;
4941 }
4942
4943 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4944 (cur_lna << 2));
78ae7532 4945 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 4946 false);
de9a47f9 4947 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4948 b43_nphy_stop_playback(dev);
15931e31
RM		 4949
4950 if (playtone) {
59af099b
RM		 4951 ret = b43_nphy_tx_tone(dev, 4000,
4952 (nphy->rxcalparams & 0xFFFF),
4953 false, false);
15931e31
RM		 4954 playtone = false;
4955 } else {
10a79873
RM		 4956 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4957 false, false);
15931e31
RM		 4958 }
4959
4960 if (ret == 0) {
4961 if (j < 3) {
4962 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4963 false);
4964 if (i == 0) {
4965 real = est.i0_pwr;
4966 imag = est.q0_pwr;
4967 } else {
4968 real = est.i1_pwr;
4969 imag = est.q1_pwr;
4970 }
4971 power[i] = ((real + imag) / 1024) + 1;
4972 } else {
4973 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4974 }
53ae8e8c 4975 b43_nphy_stop_playback(dev);
15931e31
RM		 4976 }
4977
4978 if (ret != 0)
4979 break;
4980 }
4981
4982 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4983 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4984 b43_phy_write(dev, rfctl[1], tmp[5]);
4985 b43_phy_write(dev, rfctl[0], tmp[4]);
4986 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4987 b43_phy_write(dev, afectl_core, tmp[2]);
4988 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4989
4990 if (ret != 0)
4991 break;
4992 }
4993
78ae7532 4994 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 4995 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 4996 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4997
4998 b43_nphy_stay_in_carrier_search(dev, 0);
4999
5000 return ret;
5001}
5002
5003static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5004 struct nphy_txgains target, u8 type, bool debug)
5005{
5006 return -1;
5007}
5008
5009/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5010static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5011 struct nphy_txgains target, u8 type, bool debug)
5012{
5013 if (dev->phy.rev >= 3)
5014 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5015 else
5016 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5017}
5018
4e687b22
GS		 5019/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5020static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5021{
5022 struct b43_phy *phy = &dev->phy;
5023 struct b43_phy_n *nphy = phy->n;
0b81c23d 5024 /* u16 buf[16]; it's rev3+ */
4e687b22 5025
049fbfee
RM		 5026 nphy->phyrxchain = mask;
5027
4e687b22
GS		 5028 if (0 /* FIXME clk */)
5029 return;
5030
5031 b43_mac_suspend(dev);
5032
5033 if (nphy->hang_avoid)
5034 b43_nphy_stay_in_carrier_search(dev, true);
5035
5036 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5037 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5038
049fbfee 5039 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5040 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5041 if (dev->phy.rev >= 3) {
5042 /* TODO */
5043 }
5044 } else {
5045 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5046 if (dev->phy.rev >= 3) {
5047 /* TODO */
5048 }
5049 }
5050
5051 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5052
5053 if (nphy->hang_avoid)
5054 b43_nphy_stay_in_carrier_search(dev, false);
5055
5056 b43_mac_enable(dev);
5057}
5058
104cfa88
RM		 5059/**************************************************
5060 * N-PHY init
5061 **************************************************/
5062
104cfa88
RM		 5063/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5064static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5065{
5066 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5067
5068 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5069 if (preamble == 1)
5070 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5071 else
5072 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5073
5074 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5075}
5076
5077/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5078static void b43_nphy_bphy_init(struct b43_wldev *dev)
5079{
5080 unsigned int i;
5081 u16 val;
5082
5083 val = 0x1E1F;
5084 for (i = 0; i < 16; i++) {
5085 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5086 val -= 0x202;
5087 }
5088 val = 0x3E3F;
5089 for (i = 0; i < 16; i++) {
5090 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5091 val -= 0x202;
5092 }
5093 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5094}
5095
5096/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5097static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5098{
5099 if (dev->phy.rev >= 3) {
5100 if (!init)
5101 return;
5102 if (0 /* FIXME */) {
5103 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5104 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5105 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5106 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5107 }
5108 } else {
5109 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5110 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5111
5112 switch (dev->dev->bus_type) {
5113#ifdef CONFIG_B43_BCMA
5114 case B43_BUS_BCMA:
5115 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5116 0xFC00, 0xFC00);
5117 break;
5118#endif
5119#ifdef CONFIG_B43_SSB
5120 case B43_BUS_SSB:
5121 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5122 0xFC00, 0xFC00);
5123 break;
5124#endif
5125 }
5126
5056635c
RM		 5127 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5128 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5129 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5130 0);
104cfa88
RM		 5131
5132 if (init) {
5133 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5134 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5135 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5136 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5137 }
5138 }
5139}
5140
5141/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5142static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5143{
0581483a 5144 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5145 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5146 struct b43_phy_n *nphy = phy->n;
5147 u8 tx_pwr_state;
5148 struct nphy_txgains target;
95b66bad 5149 u16 tmp;
0988a7a1
RM		 5150 enum ieee80211_band tmp2;
5151 bool do_rssi_cal;
5152
5153 u16 clip[2];
5154 bool do_cal = false;
95b66bad 5155
0988a7a1 5156 if ((dev->phy.rev >= 3) &&
0581483a 5157 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5158 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5159 switch (dev->dev->bus_type) {
42c9a458
RM		 5160#ifdef CONFIG_B43_BCMA
5161 case B43_BUS_BCMA:
5162 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5163 BCMA_CC_CHIPCTL, 0x40);
5164 break;
5165#endif
6cbab0d9
RM		 5166#ifdef CONFIG_B43_SSB
5167 case B43_BUS_SSB:
5168 chipco_set32(&dev->dev->sdev->bus->chipco,
5169 SSB_CHIPCO_CHIPCTL, 0x40);
5170 break;
5171#endif
5172 }
0988a7a1
RM		 5173 }
5174 nphy->deaf_count = 0;
95b66bad 5175 b43_nphy_tables_init(dev);
0988a7a1
RM		 5176 nphy->crsminpwr_adjusted = false;
5177 nphy->noisevars_adjusted = false;
95b66bad
MB		 5178
5179 /* Clear all overrides */
0988a7a1
RM		 5180 if (dev->phy.rev >= 3) {
5181 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5182 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5183 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5184 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5185 } else {
5186 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5187 }
95b66bad
MB		 5188 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5189 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5190 if (dev->phy.rev < 6) {
5191 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5192 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5193 }
95b66bad
MB		 5194 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5195 ~(B43_NPHY_RFSEQMODE_CAOVER |
5196 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5197 if (dev->phy.rev >= 3)
5198 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5199 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5200
0988a7a1
RM		 5201 if (dev->phy.rev <= 2) {
5202 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5203 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5204 ~B43_NPHY_BPHY_CTL3_SCALE,
5205 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5206 }
95b66bad
MB		 5207 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5208 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5209
0eff8fcd 5210 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5211 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5212 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5213 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5214 else
5215 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5216 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5217 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5218 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5219
ad9716e8 5220 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5221 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5222
5223 if (phy->rev < 2) {
5224 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5225 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5226 }
0988a7a1
RM		 5227
5228 tmp2 = b43_current_band(dev->wl);
c002831a 5229 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5230 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5231 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5232 nphy->papd_epsilon_offset[0] << 7);
5233 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5234 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5235 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5236 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5237 } else if (phy->rev >= 5) {
45ca697e 5238 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5239 }
5240
95b66bad 5241 b43_nphy_workarounds(dev);
95b66bad 5242
0988a7a1 5243 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5244 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5245 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5246 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5247 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5248 b43_phy_force_clock(dev, 0);
0988a7a1 5249
858a1652 5250 b43_mac_phy_clock_set(dev, true);
0988a7a1 5251
e50cbcf6 5252 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5253 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5254 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5255 b43_nphy_pa_override(dev, true);
0988a7a1 5256
bbec398c
RM		 5257 b43_nphy_classifier(dev, 0, 0);
5258 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5259 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5260 b43_nphy_bphy_init(dev);
5261
0988a7a1 5262 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5263 b43_nphy_tx_power_ctrl(dev, false);
5264 b43_nphy_tx_power_fix(dev);
3dda07b6 5265 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5266 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5267 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5268
0988a7a1 5269 if (nphy->phyrxchain != 3)
4e687b22 5270 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5271 if (nphy->mphase_cal_phase_id > 0)
5272 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5273
5274 do_rssi_cal = false;
5275 if (phy->rev >= 3) {
5276 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5277 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5278 else
204a665b 5279 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5280
5281 if (do_rssi_cal)
4cb99775 5282 b43_nphy_rssi_cal(dev);
0988a7a1 5283 else
42e1547e 5284 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5285 } else {
4cb99775 5286 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5287 }
5288
5289 if (!((nphy->measure_hold & 0x6) != 0)) {
5290 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5291 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5292 else
204a665b 5293 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5294
5295 if (nphy->mute)
5296 do_cal = false;
5297
5298 if (do_cal) {
b0022e15 5299 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5300
5301 if (nphy->antsel_type == 2)
8987a9e9 5302 b43_nphy_superswitch_init(dev, true);
0988a7a1 5303 if (nphy->perical != 2) {
90b9738d 5304 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5305 if (phy->rev >= 3) {
5306 nphy->cal_orig_pwr_idx[0] =
5307 nphy->txpwrindex[0].index_internal;
5308 nphy->cal_orig_pwr_idx[1] =
5309 nphy->txpwrindex[1].index_internal;
5310 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5311 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5312 }
e7797bf2
RM		 5313 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5314 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5315 b43_nphy_save_cal(dev);
5316 } else if (nphy->mphase_cal_phase_id == 0)
5317 ;/* N PHY Periodic Calibration with arg 3 */
5318 } else {
5319 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5320 }
5321 }
5322
6dcd9d91 5323 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5324 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5325 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5326 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5327 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5328 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
fe3e46e8 5329 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5330 if (phy->rev >= 3)
5331 b43_nphy_spur_workaround(dev);
95b66bad 5332
53a6e234 5333 return 0;
424047e6 5334}
ef1a628d 5335
104cfa88
RM		 5336/**************************************************
5337 * Channel switching ops.
5338 **************************************************/
5339
5340static void b43_chantab_phy_upload(struct b43_wldev *dev,
5341 const struct b43_phy_n_sfo_cfg *e)
5342{
5343 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5344 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5345 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5346 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5347 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5348 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5349}
5350
49d55cef
RM		 5351/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5352static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5353{
d66be829
RM		 5354 switch (dev->dev->bus_type) {
5355#ifdef CONFIG_B43_BCMA
5356 case B43_BUS_BCMA:
9b383672
HM		 5357 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5358 avoid);
d66be829 5359 break;
8b1fdb53 5360#endif
d66be829
RM		 5361#ifdef CONFIG_B43_SSB
5362 case B43_BUS_SSB:
46fc4c90
RM		 5363 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5364 avoid);
d66be829
RM		 5365 break;
5366#endif
5367 }
49d55cef
RM		 5368}
5369
1b69ec7b 5370/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5371static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5372 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5373 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5374{
5375 struct b43_phy *phy = &dev->phy;
5376 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5377 int ch = new_channel->hw_value;
1b69ec7b 5378
087de74a 5379 u16 old_band_5ghz;
12cd43c6 5380 u16 tmp16;
1b69ec7b 5381
087de74a
RM		 5382 old_band_5ghz =
5383 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5384 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5385 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5386 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5387 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5388 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5389 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5390 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5391 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5392 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5393 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5394 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5395 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5396 }
5397
5398 b43_chantab_phy_upload(dev, e);
5399
a656b6a9 5400 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5401 b43_nphy_classifier(dev, 2, 0);
5402 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5403 } else {
5404 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5405 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5406 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5407 }
5408
161d540c 5409 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5410 b43_nphy_tx_power_fix(dev);
5411
5412 if (dev->phy.rev < 3)
5413 b43_nphy_adjust_lna_gain_table(dev);
5414
5415 b43_nphy_tx_lp_fbw(dev);
5416
49d55cef
RM		 5417 if (dev->phy.rev >= 3 &&
5418 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5419 bool avoid = false;
5420 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5421 avoid = true;
5422 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5423 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5424 avoid = true;
5425 } else { /* 40MHz */
5426 if (nphy->aband_spurwar_en &&
5427 (ch == 38 || ch == 102 || ch == 118))
5428 avoid = dev->dev->chip_id == 0x4716;
5429 }
5430
5431 b43_nphy_pmu_spur_avoid(dev, avoid);
5432
5433 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5434 dev->dev->chip_id == 43225) {
5435 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5436 avoid ? 0x5341 : 0x8889);
5437 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5438 }
5439
5440 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5441 ; /* TODO: reset PLL */
5442
5443 if (avoid)
5444 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5445 else
5446 b43_phy_mask(dev, B43_NPHY_BBCFG,
5447 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5448
5449 b43_nphy_reset_cca(dev);
5450
5451 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5452 }
5453
5454 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5455
5456 if (phy->rev >= 3)
5457 b43_nphy_spur_workaround(dev);
5458}
5459
eff66c51 5460/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5461static int b43_nphy_set_channel(struct b43_wldev *dev,
5462 struct ieee80211_channel *channel,
5463 enum nl80211_channel_type channel_type)
eff66c51 5464{
a656b6a9 5465 struct b43_phy *phy = &dev->phy;
eff66c51 5466
2eeb6fd0
JL		 5467 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5468 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5469
5470 u8 tmp;
eff66c51
RM		 5471
5472 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5473 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5474 channel->center_freq);
f19ebe7d
RM		 5475 if (!tabent_r3)
5476 return -ESRCH;
ffd2d9bd 5477 } else {
a656b6a9
RM		 5478 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5479 channel->hw_value);
f19ebe7d 5480 if (!tabent_r2)
ffd2d9bd 5481 return -ESRCH;
eff66c51
RM		 5482 }
5483
204a665b
RM		 5484 /* Channel is set later in common code, but we need to set it on our
5485 own to let this function's subcalls work properly. */
5486 phy->channel = channel->hw_value;
5487 phy->channel_freq = channel->center_freq;
eff66c51 5488
e5c407f9
RM		 5489 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5490 b43_channel_type_is_40mhz(channel_type))
5491 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5492
a656b6a9
RM		 5493 if (channel_type == NL80211_CHAN_HT40PLUS)
5494 b43_phy_set(dev, B43_NPHY_RXCTL,
5495 B43_NPHY_RXCTL_BSELU20);
5496 else if (channel_type == NL80211_CHAN_HT40MINUS)
5497 b43_phy_mask(dev, B43_NPHY_RXCTL,
5498 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5499
5500 if (dev->phy.rev >= 3) {
a656b6a9 5501 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5502 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5503 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5504 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5505 } else {
a656b6a9 5506 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5507 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5508 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5509 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5510 }
5511
5512 return 0;
5513}
5514
104cfa88
RM		 5515/**************************************************
5516 * Basic PHY ops.
5517 **************************************************/
5518
ef1a628d
MB		 5519static int b43_nphy_op_allocate(struct b43_wldev *dev)
5520{
5521 struct b43_phy_n *nphy;
5522
5523 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5524 if (!nphy)
5525 return -ENOMEM;
5526 dev->phy.n = nphy;
5527
ef1a628d
MB		 5528 return 0;
5529}
5530
fb11137a 5531static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5532{
fb11137a
MB		 5533 struct b43_phy *phy = &dev->phy;
5534 struct b43_phy_n *nphy = phy->n;
c7d64310 5535 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5536
fb11137a 5537 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5538
aca434d3 5539 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5540 nphy->spur_avoid = (phy->rev >= 3) ?
5541 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5542 nphy->init_por = true;
0b81c23d
RM		 5543 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5544 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5545 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5546 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5547 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5548 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5549 nphy->tx_pwr_idx[0] = 128;
5550 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5551
5552 /* Hardware TX power control and 5GHz power gain */
5553 nphy->txpwrctrl = false;
5554 nphy->pwg_gain_5ghz = false;
5555 if (dev->phy.rev >= 3 ||
5556 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5557 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5558 nphy->txpwrctrl = true;
5559 nphy->pwg_gain_5ghz = true;
5560 } else if (sprom->revision >= 4) {
5561 if (dev->phy.rev >= 2 &&
5562 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5563 nphy->txpwrctrl = true;
5564#ifdef CONFIG_B43_SSB
5565 if (dev->dev->bus_type == B43_BUS_SSB &&
5566 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5567 struct pci_dev *pdev =
5568 dev->dev->sdev->bus->host_pci;
5569 if (pdev->device == 0x4328 ||
5570 pdev->device == 0x432a)
5571 nphy->pwg_gain_5ghz = true;
5572 }
5573#endif
5574 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5575 nphy->pwg_gain_5ghz = true;
5576 }
5577 }
5578
5579 if (dev->phy.rev >= 3) {
5580 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5581 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5582 }
572d37a4
RM		 5583
5584 nphy->init_por = true;
ef1a628d
MB		 5585}
5586
fb11137a 5587static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5588{
fb11137a
MB		 5589 struct b43_phy *phy = &dev->phy;
5590 struct b43_phy_n *nphy = phy->n;
ef1a628d 5591
ef1a628d 5592 kfree(nphy);
fb11137a
MB		 5593 phy->n = NULL;
5594}
5595
5596static int b43_nphy_op_init(struct b43_wldev *dev)
5597{
5598 return b43_phy_initn(dev);
ef1a628d
MB		 5599}
5600
5601static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5602{
5603#if B43_DEBUG
5604 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5605 /* OFDM registers are onnly available on A/G-PHYs */
5606 b43err(dev->wl, "Invalid OFDM PHY access at "
5607 "0x%04X on N-PHY\n", offset);
5608 dump_stack();
5609 }
5610 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5611 /* Ext-G registers are only available on G-PHYs */
5612 b43err(dev->wl, "Invalid EXT-G PHY access at "
5613 "0x%04X on N-PHY\n", offset);
5614 dump_stack();
5615 }
5616#endif /* B43_DEBUG */
5617}
5618
5619static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5620{
5621 check_phyreg(dev, reg);
5622 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5623 return b43_read16(dev, B43_MMIO_PHY_DATA);
5624}
5625
5626static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5627{
5628 check_phyreg(dev, reg);
5629 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5630 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5631}
5632
755fd183
RM		 5633static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5634 u16 set)
5635{
5636 check_phyreg(dev, reg);
5637 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5638 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5639}
5640
ef1a628d
MB		 5641static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5642{
5643 /* Register 1 is a 32-bit register. */
5644 B43_WARN_ON(reg == 1);
a6aa05d6
RM		 5645
5646 if (dev->phy.rev >= 7)
5647 reg |= 0x200; /* Radio 0x2057 */
5648 else
5649 reg |= 0x100;
ef1a628d
MB		 5650
5651 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5652 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5653}
5654
5655static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5656{
5657 /* Register 1 is a 32-bit register. */
5658 B43_WARN_ON(reg == 1);
5659
5660 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5661 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5662}
5663
c2b7aefd 5664/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5665static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5666 bool blocked)
c2b7aefd
RM		 5667{
5668 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5669 b43err(dev->wl, "MAC not suspended\n");
5670
5671 if (blocked) {
5672 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5673 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5674 if (dev->phy.rev >= 7) {
5675 /* TODO */
5676 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5677 b43_radio_mask(dev, 0x09, ~0x2);
5678
5679 b43_radio_write(dev, 0x204D, 0);
5680 b43_radio_write(dev, 0x2053, 0);
5681 b43_radio_write(dev, 0x2058, 0);
5682 b43_radio_write(dev, 0x205E, 0);
5683 b43_radio_mask(dev, 0x2062, ~0xF0);
5684 b43_radio_write(dev, 0x2064, 0);
5685
5686 b43_radio_write(dev, 0x304D, 0);
5687 b43_radio_write(dev, 0x3053, 0);
5688 b43_radio_write(dev, 0x3058, 0);
5689 b43_radio_write(dev, 0x305E, 0);
5690 b43_radio_mask(dev, 0x3062, ~0xF0);
5691 b43_radio_write(dev, 0x3064, 0);
5692 }
5693 } else {
572d37a4
RM		 5694 if (dev->phy.rev >= 7) {
5695 b43_radio_2057_init(dev);
5696 b43_switch_channel(dev, dev->phy.channel);
5697 } else if (dev->phy.rev >= 3) {
d817f4e1 5698 b43_radio_init2056(dev);
78159788 5699 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5700 } else {
5701 b43_radio_init2055(dev);
5702 }
5703 }
ef1a628d
MB		 5704}
5705
0f4091b9 5706/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5707static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5708{
2a870831
RM		 5709 u16 override = on ? 0x0 : 0x7FFF;
5710 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5711
2a870831
RM		 5712 if (dev->phy.rev >= 3) {
5713 if (on) {
5714 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5715 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5716 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5717 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5718 } else {
5719 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5720 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5721 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5722 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5723 }
5724 } else {
5725 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5726 }
cb24f57f
MB		 5727}
5728
ef1a628d
MB		 5729static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5730 unsigned int new_channel)
5731{
675a0b04
KB		 5732 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5733 enum nl80211_channel_type channel_type =
5734 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5735
ef1a628d
MB		 5736 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5737 if ((new_channel < 1) || (new_channel > 14))
5738 return -EINVAL;
5739 } else {
5740 if (new_channel > 200)
5741 return -EINVAL;
5742 }
5743
a656b6a9 5744 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5745}
5746
5747static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5748{
5749 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5750 return 1;
5751 return 36;
5752}
5753
ef1a628d
MB		 5754const struct b43_phy_operations b43_phyops_n = {
5755 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5756 .free = b43_nphy_op_free,
5757 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5758 .init = b43_nphy_op_init,
ef1a628d
MB		 5759 .phy_read = b43_nphy_op_read,
5760 .phy_write = b43_nphy_op_write,
755fd183 5761 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5762 .radio_read = b43_nphy_op_radio_read,
5763 .radio_write = b43_nphy_op_radio_write,
5764 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5765 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5766 .switch_channel = b43_nphy_op_switch_channel,
5767 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5768 .recalc_txpower = b43_nphy_op_recalc_txpower,
5769 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5770};
Linux kernel - Deliverables
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