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b43: N-PHY: reorder functions: collect samples ones
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
bbec398c 35#include "main.h"
424047e6 36
f8187b5b
RM		 37struct nphy_txgains {
38 u16 txgm[2];
39 u16 pga[2];
40 u16 pad[2];
41 u16 ipa[2];
42};
43
44struct nphy_iqcal_params {
45 u16 txgm;
46 u16 pga;
47 u16 pad;
48 u16 ipa;
49 u16 cal_gain;
50 u16 ncorr[5];
51};
52
53struct nphy_iq_est {
54 s32 iq0_prod;
55 u32 i0_pwr;
56 u32 q0_pwr;
57 s32 iq1_prod;
58 u32 i1_pwr;
59 u32 q1_pwr;
60};
424047e6 61
67c0d6e2
RM		 62enum b43_nphy_rf_sequence {
63 B43_RFSEQ_RX2TX,
64 B43_RFSEQ_TX2RX,
65 B43_RFSEQ_RESET2RX,
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
69};
70
76b002bd
RM		 71enum b43_nphy_rssi_type {
72 B43_NPHY_RSSI_X = 0,
73 B43_NPHY_RSSI_Y,
74 B43_NPHY_RSSI_Z,
75 B43_NPHY_RSSI_PWRDET,
76 B43_NPHY_RSSI_TSSI_I,
77 B43_NPHY_RSSI_TSSI_Q,
78 B43_NPHY_RSSI_TBD,
79};
80
c002831a
RM		 81static inline bool b43_nphy_ipa(struct b43_wldev *dev)
82{
83 enum ieee80211_band band = b43_current_band(dev->wl);
84 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
85 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
86}
87
ab499217
RM		 88/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
89static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
90{
91 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
92 if (dev->phy.rev >= 6) {
93 if (dev->dev->chip_id == 47162)
94 return txpwrctrl_tx_gain_ipa_rev5;
95 return txpwrctrl_tx_gain_ipa_rev6;
96 } else if (dev->phy.rev >= 5) {
97 return txpwrctrl_tx_gain_ipa_rev5;
98 } else {
99 return txpwrctrl_tx_gain_ipa;
100 }
101 } else {
102 return txpwrctrl_tx_gain_ipa_5g;
103 }
104}
105
106/**************************************************
107 * RF (just without b43_nphy_rf_control_intc_override)
108 **************************************************/
109
110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
111static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
112 enum b43_nphy_rf_sequence seq)
113{
114 static const u16 trigger[] = {
115 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
116 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
117 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
118 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
119 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
120 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
121 };
122 int i;
123 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
124
125 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
126
127 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
128 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
129 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
130 for (i = 0; i < 200; i++) {
131 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
132 goto ok;
133 msleep(1);
134 }
135 b43err(dev->wl, "RF sequence status timeout\n");
136ok:
137 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
138}
139
140/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
141static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
142 u16 value, u8 core, bool off)
143{
144 int i;
145 u8 index = fls(field);
146 u8 addr, en_addr, val_addr;
147 /* we expect only one bit set */
148 B43_WARN_ON(field & (~(1 << (index - 1))));
149
150 if (dev->phy.rev >= 3) {
151 const struct nphy_rf_control_override_rev3 *rf_ctrl;
152 for (i = 0; i < 2; i++) {
153 if (index == 0 || index == 16) {
154 b43err(dev->wl,
155 "Unsupported RF Ctrl Override call\n");
156 return;
157 }
158
159 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
160 en_addr = B43_PHY_N((i == 0) ?
161 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
162 val_addr = B43_PHY_N((i == 0) ?
163 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
164
165 if (off) {
166 b43_phy_mask(dev, en_addr, ~(field));
167 b43_phy_mask(dev, val_addr,
168 ~(rf_ctrl->val_mask));
169 } else {
170 if (core == 0 || ((1 << core) & i) != 0) {
171 b43_phy_set(dev, en_addr, field);
172 b43_phy_maskset(dev, val_addr,
173 ~(rf_ctrl->val_mask),
174 (value << rf_ctrl->val_shift));
175 }
176 }
177 }
178 } else {
179 const struct nphy_rf_control_override_rev2 *rf_ctrl;
180 if (off) {
181 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
182 value = 0;
183 } else {
184 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
185 }
186
187 for (i = 0; i < 2; i++) {
188 if (index <= 1 || index == 16) {
189 b43err(dev->wl,
190 "Unsupported RF Ctrl Override call\n");
191 return;
192 }
193
194 if (index == 2 || index == 10 ||
195 (index >= 13 && index <= 15)) {
196 core = 1;
197 }
198
199 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
200 addr = B43_PHY_N((i == 0) ?
201 rf_ctrl->addr0 : rf_ctrl->addr1);
202
203 if ((core & (1 << i)) != 0)
204 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
205 (value << rf_ctrl->shift));
206
207 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
208 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
209 B43_NPHY_RFCTL_CMD_START);
210 udelay(1);
211 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
212 }
213 }
214}
215
216/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
217static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
218 u16 value, u8 core)
219{
220 u8 i, j;
221 u16 reg, tmp, val;
222
223 B43_WARN_ON(dev->phy.rev < 3);
224 B43_WARN_ON(field > 4);
225
226 for (i = 0; i < 2; i++) {
227 if ((core == 1 && i == 1) || (core == 2 && !i))
228 continue;
229
230 reg = (i == 0) ?
231 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
232 b43_phy_mask(dev, reg, 0xFBFF);
233
234 switch (field) {
235 case 0:
236 b43_phy_write(dev, reg, 0);
237 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
238 break;
239 case 1:
240 if (!i) {
241 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
242 0xFC3F, (value << 6));
243 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
244 0xFFFE, 1);
245 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
246 B43_NPHY_RFCTL_CMD_START);
247 for (j = 0; j < 100; j++) {
248 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
249 j = 0;
250 break;
251 }
252 udelay(10);
253 }
254 if (j)
255 b43err(dev->wl,
256 "intc override timeout\n");
257 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
258 0xFFFE);
259 } else {
260 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
261 0xFC3F, (value << 6));
262 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
263 0xFFFE, 1);
264 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
265 B43_NPHY_RFCTL_CMD_RXTX);
266 for (j = 0; j < 100; j++) {
267 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
268 j = 0;
269 break;
270 }
271 udelay(10);
272 }
273 if (j)
274 b43err(dev->wl,
275 "intc override timeout\n");
276 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
277 0xFFFE);
278 }
279 break;
280 case 2:
281 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
282 tmp = 0x0020;
283 val = value << 5;
284 } else {
285 tmp = 0x0010;
286 val = value << 4;
287 }
288 b43_phy_maskset(dev, reg, ~tmp, val);
289 break;
290 case 3:
291 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
292 tmp = 0x0001;
293 val = value;
294 } else {
295 tmp = 0x0004;
296 val = value << 2;
297 }
298 b43_phy_maskset(dev, reg, ~tmp, val);
299 break;
300 case 4:
301 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
302 tmp = 0x0002;
303 val = value << 1;
304 } else {
305 tmp = 0x0008;
306 val = value << 3;
307 }
308 b43_phy_maskset(dev, reg, ~tmp, val);
309 break;
310 }
311 }
312}
313
314/**************************************************
315 * Various PHY ops
316 **************************************************/
317
318/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
319static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
320 const u16 *clip_st)
321{
322 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
323 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
324}
325
326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
327static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
328{
329 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
330 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
331}
332
333/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
334static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
335{
336 u16 tmp;
337
338 if (dev->dev->core_rev == 16)
339 b43_mac_suspend(dev);
340
341 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
342 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
343 B43_NPHY_CLASSCTL_WAITEDEN);
344 tmp &= ~mask;
345 tmp |= (val & mask);
346 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
347
348 if (dev->dev->core_rev == 16)
349 b43_mac_enable(dev);
350
351 return tmp;
352}
353
354/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
355static void b43_nphy_reset_cca(struct b43_wldev *dev)
356{
357 u16 bbcfg;
358
359 b43_phy_force_clock(dev, 1);
360 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
361 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
362 udelay(1);
363 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
364 b43_phy_force_clock(dev, 0);
365 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
366}
367
368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
369static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
370{
371 struct b43_phy *phy = &dev->phy;
372 struct b43_phy_n *nphy = phy->n;
373
374 if (enable) {
375 static const u16 clip[] = { 0xFFFF, 0xFFFF };
376 if (nphy->deaf_count++ == 0) {
377 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
378 b43_nphy_classifier(dev, 0x7, 0);
379 b43_nphy_read_clip_detection(dev, nphy->clip_state);
380 b43_nphy_write_clip_detection(dev, clip);
381 }
382 b43_nphy_reset_cca(dev);
383 } else {
384 if (--nphy->deaf_count == 0) {
385 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
386 b43_nphy_write_clip_detection(dev, nphy->clip_state);
387 }
388 }
389}
390
391/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
392static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
393 u8 *events, u8 *delays, u8 length)
394{
395 struct b43_phy_n *nphy = dev->phy.n;
396 u8 i;
397 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
398 u16 offset1 = cmd << 4;
399 u16 offset2 = offset1 + 0x80;
400
401 if (nphy->hang_avoid)
402 b43_nphy_stay_in_carrier_search(dev, true);
403
404 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
405 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
406
407 for (i = length; i < 16; i++) {
408 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
409 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
410 }
411
412 if (nphy->hang_avoid)
413 b43_nphy_stay_in_carrier_search(dev, false);
414}
415
416/**************************************************
884a5228 417 * Radio 0x2056
ab499217
RM		 418 **************************************************/
419
d4814e69
RM		 420static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
421 const struct b43_nphy_channeltab_entry_rev3 *e)
422{
423 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
424 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
425 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
426 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
427 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
428 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
429 e->radio_syn_pll_loopfilter1);
430 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
431 e->radio_syn_pll_loopfilter2);
432 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
433 e->radio_syn_pll_loopfilter3);
434 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
435 e->radio_syn_pll_loopfilter4);
436 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
437 e->radio_syn_pll_loopfilter5);
438 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
439 e->radio_syn_reserved_addr27);
440 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
441 e->radio_syn_reserved_addr28);
442 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
443 e->radio_syn_reserved_addr29);
444 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
445 e->radio_syn_logen_vcobuf1);
446 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
447 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
448 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
449
450 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
451 e->radio_rx0_lnaa_tune);
452 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
453 e->radio_rx0_lnag_tune);
454
455 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
456 e->radio_tx0_intpaa_boost_tune);
457 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
458 e->radio_tx0_intpag_boost_tune);
459 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
460 e->radio_tx0_pada_boost_tune);
461 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
462 e->radio_tx0_padg_boost_tune);
463 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
464 e->radio_tx0_pgaa_boost_tune);
465 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
466 e->radio_tx0_pgag_boost_tune);
467 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
468 e->radio_tx0_mixa_boost_tune);
469 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
470 e->radio_tx0_mixg_boost_tune);
471
472 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
473 e->radio_rx1_lnaa_tune);
474 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
475 e->radio_rx1_lnag_tune);
476
477 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
478 e->radio_tx1_intpaa_boost_tune);
479 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
480 e->radio_tx1_intpag_boost_tune);
481 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
482 e->radio_tx1_pada_boost_tune);
483 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
484 e->radio_tx1_padg_boost_tune);
485 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
486 e->radio_tx1_pgaa_boost_tune);
487 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
488 e->radio_tx1_pgag_boost_tune);
489 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
490 e->radio_tx1_mixa_boost_tune);
491 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
492 e->radio_tx1_mixg_boost_tune);
493}
494
495/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
496static void b43_radio_2056_setup(struct b43_wldev *dev,
497 const struct b43_nphy_channeltab_entry_rev3 *e)
498{
38646eba
RM		 499 struct ssb_sprom *sprom = dev->dev->bus_sprom;
500 enum ieee80211_band band = b43_current_band(dev->wl);
501 u16 offset;
502 u8 i;
503 u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
504
d4814e69
RM		 505 B43_WARN_ON(dev->phy.rev < 3);
506
507 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 508 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
509
510 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
511 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
512 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
513 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
514 if (dev->dev->chip_id == 0x4716) {
515 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
516 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
517 } else {
518 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
519 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
520 }
521 }
522 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
523 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
524 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
525 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
526 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
527 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
528 }
529
530 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
531 for (i = 0; i < 2; i++) {
532 offset = i ? B2056_TX1 : B2056_TX0;
533 if (dev->phy.rev >= 5) {
534 b43_radio_write(dev,
535 offset | B2056_TX_PADG_IDAC, 0xcc);
536
537 if (dev->dev->chip_id == 0x4716) {
538 bias = 0x40;
539 cbias = 0x45;
540 pag_boost = 0x5;
541 pgag_boost = 0x33;
542 mixg_boost = 0x55;
543 } else {
544 bias = 0x25;
545 cbias = 0x20;
546 pag_boost = 0x4;
547 pgag_boost = 0x03;
548 mixg_boost = 0x65;
549 }
550 padg_boost = 0x77;
551
552 b43_radio_write(dev,
553 offset | B2056_TX_INTPAG_IMAIN_STAT,
554 bias);
555 b43_radio_write(dev,
556 offset | B2056_TX_INTPAG_IAUX_STAT,
557 bias);
558 b43_radio_write(dev,
559 offset | B2056_TX_INTPAG_CASCBIAS,
560 cbias);
561 b43_radio_write(dev,
562 offset | B2056_TX_INTPAG_BOOST_TUNE,
563 pag_boost);
564 b43_radio_write(dev,
565 offset | B2056_TX_PGAG_BOOST_TUNE,
566 pgag_boost);
567 b43_radio_write(dev,
568 offset | B2056_TX_PADG_BOOST_TUNE,
569 padg_boost);
570 b43_radio_write(dev,
571 offset | B2056_TX_MIXG_BOOST_TUNE,
572 mixg_boost);
573 } else {
574 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
575 b43_radio_write(dev,
576 offset | B2056_TX_INTPAG_IMAIN_STAT,
577 bias);
578 b43_radio_write(dev,
579 offset | B2056_TX_INTPAG_IAUX_STAT,
580 bias);
581 b43_radio_write(dev,
582 offset | B2056_TX_INTPAG_CASCBIAS,
583 0x30);
584 }
585 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
586 }
587 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
588 /* TODO */
589 }
590
d4814e69
RM		 591 udelay(50);
592 /* VCO calibration */
593 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
594 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
595 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
596 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
597 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
598 udelay(300);
599}
600
884a5228
RM		 601static void b43_radio_init2056_pre(struct b43_wldev *dev)
602{
603 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
604 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
605 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
606 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
607 B43_NPHY_RFCTL_CMD_OEPORFORCE);
608 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
609 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
610 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
611 B43_NPHY_RFCTL_CMD_CHIP0PU);
612}
613
614static void b43_radio_init2056_post(struct b43_wldev *dev)
615{
616 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
617 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
618 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
619 msleep(1);
620 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
621 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
622 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
623 /*
624 if (nphy->init_por)
625 Call Radio 2056 Recalibrate
626 */
627}
628
629/*
630 * Initialize a Broadcom 2056 N-radio
631 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
632 */
633static void b43_radio_init2056(struct b43_wldev *dev)
634{
635 b43_radio_init2056_pre(dev);
636 b2056_upload_inittabs(dev, 0, 0);
637 b43_radio_init2056_post(dev);
638}
639
640/**************************************************
641 * Radio 0x2055
642 **************************************************/
643
644static void b43_chantab_radio_upload(struct b43_wldev *dev,
645 const struct b43_nphy_channeltab_entry_rev2 *e)
646{
647 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
648 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
649 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
650 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
651 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
652
653 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
654 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
655 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
656 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
657 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
658
659 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
660 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
661 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
662 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
663 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
664
665 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
666 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
667 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
668 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
669 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
670
671 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
672 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
673 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
674 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
675 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
676
677 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
678 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
679}
680
681/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
682static void b43_radio_2055_setup(struct b43_wldev *dev,
683 const struct b43_nphy_channeltab_entry_rev2 *e)
684{
685 B43_WARN_ON(dev->phy.rev >= 3);
686
687 b43_chantab_radio_upload(dev, e);
688 udelay(50);
689 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
690 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
691 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
692 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
693 udelay(300);
694}
695
696static void b43_radio_init2055_pre(struct b43_wldev *dev)
697{
698 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
699 ~B43_NPHY_RFCTL_CMD_PORFORCE);
700 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
701 B43_NPHY_RFCTL_CMD_CHIP0PU |
702 B43_NPHY_RFCTL_CMD_OEPORFORCE);
703 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
704 B43_NPHY_RFCTL_CMD_PORFORCE);
705}
706
707static void b43_radio_init2055_post(struct b43_wldev *dev)
708{
709 struct b43_phy_n *nphy = dev->phy.n;
710 struct ssb_sprom *sprom = dev->dev->bus_sprom;
711 int i;
712 u16 val;
713 bool workaround = false;
714
715 if (sprom->revision < 4)
716 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
717 && dev->dev->board_type == 0x46D
718 && dev->dev->board_rev >= 0x41);
719 else
720 workaround =
721 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
722
723 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
724 if (workaround) {
725 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
726 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
727 }
728 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
729 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
730 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
731 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
732 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
733 msleep(1);
734 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
735 for (i = 0; i < 200; i++) {
736 val = b43_radio_read(dev, B2055_CAL_COUT2);
737 if (val & 0x80) {
738 i = 0;
739 break;
740 }
741 udelay(10);
742 }
743 if (i)
744 b43err(dev->wl, "radio post init timeout\n");
745 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
746 b43_switch_channel(dev, dev->phy.channel);
747 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
748 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
749 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
750 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
751 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
752 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
753 if (!nphy->gain_boost) {
754 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
755 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
756 } else {
757 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
758 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
759 }
760 udelay(2);
761}
762
763/*
764 * Initialize a Broadcom 2055 N-radio
765 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
766 */
767static void b43_radio_init2055(struct b43_wldev *dev)
768{
769 b43_radio_init2055_pre(dev);
770 if (b43_status(dev) < B43_STAT_INITIALIZED) {
771 /* Follow wl, not specs. Do not force uploading all regs */
772 b2055_upload_inittab(dev, 0, 0);
773 } else {
774 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
775 b2055_upload_inittab(dev, ghz5, 0);
776 }
777 b43_radio_init2055_post(dev);
778}
779
8be89535
RM		 780/**************************************************
781 * Samples
782 **************************************************/
783
784/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
785static int b43_nphy_load_samples(struct b43_wldev *dev,
786 struct b43_c32 *samples, u16 len) {
787 struct b43_phy_n *nphy = dev->phy.n;
788 u16 i;
789 u32 *data;
790
791 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
792 if (!data) {
793 b43err(dev->wl, "allocation for samples loading failed\n");
794 return -ENOMEM;
795 }
796 if (nphy->hang_avoid)
797 b43_nphy_stay_in_carrier_search(dev, 1);
798
799 for (i = 0; i < len; i++) {
800 data[i] = (samples[i].i & 0x3FF << 10);
801 data[i] |= samples[i].q & 0x3FF;
802 }
803 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
804
805 kfree(data);
806 if (nphy->hang_avoid)
807 b43_nphy_stay_in_carrier_search(dev, 0);
808 return 0;
809}
810
811/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
812static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
813 bool test)
814{
815 int i;
816 u16 bw, len, rot, angle;
817 struct b43_c32 *samples;
818
819
820 bw = (dev->phy.is_40mhz) ? 40 : 20;
821 len = bw << 3;
822
823 if (test) {
824 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
825 bw = 82;
826 else
827 bw = 80;
828
829 if (dev->phy.is_40mhz)
830 bw <<= 1;
831
832 len = bw << 1;
833 }
834
835 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
836 if (!samples) {
837 b43err(dev->wl, "allocation for samples generation failed\n");
838 return 0;
839 }
840 rot = (((freq * 36) / bw) << 16) / 100;
841 angle = 0;
842
843 for (i = 0; i < len; i++) {
844 samples[i] = b43_cordic(angle);
845 angle += rot;
846 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
847 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
848 }
849
850 i = b43_nphy_load_samples(dev, samples, len);
851 kfree(samples);
852 return (i < 0) ? 0 : len;
853}
854
855/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
856static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
857 u16 wait, bool iqmode, bool dac_test)
858{
859 struct b43_phy_n *nphy = dev->phy.n;
860 int i;
861 u16 seq_mode;
862 u32 tmp;
863
864 if (nphy->hang_avoid)
865 b43_nphy_stay_in_carrier_search(dev, true);
866
867 if ((nphy->bb_mult_save & 0x80000000) == 0) {
868 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
869 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
870 }
871
872 if (!dev->phy.is_40mhz)
873 tmp = 0x6464;
874 else
875 tmp = 0x4747;
876 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
877
878 if (nphy->hang_avoid)
879 b43_nphy_stay_in_carrier_search(dev, false);
880
881 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
882
883 if (loops != 0xFFFF)
884 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
885 else
886 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
887
888 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
889
890 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
891
892 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
893 if (iqmode) {
894 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
895 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
896 } else {
897 if (dac_test)
898 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
899 else
900 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
901 }
902 for (i = 0; i < 100; i++) {
903 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
904 i = 0;
905 break;
906 }
907 udelay(10);
908 }
909 if (i)
910 b43err(dev->wl, "run samples timeout\n");
911
912 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
913}
914
884a5228
RM		 915/**************************************************
916 * Others
917 **************************************************/
918
919void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
920{//TODO
921}
922
923static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
924{//TODO
925}
926
927static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
928 bool ignore_tssi)
929{//TODO
930 return B43_TXPWR_RES_DONE;
931}
932
d1591314 933static void b43_chantab_phy_upload(struct b43_wldev *dev,
b15b3039 934 const struct b43_phy_n_sfo_cfg *e)
d1591314
MB		 935{
936 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
937 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
938 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
939 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
940 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
941 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
942}
943
161d540c
RM		 944/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
945static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
946{
947 struct b43_phy_n *nphy = dev->phy.n;
948 u8 i;
c9c0d9ec
RM		 949 u16 bmask, val, tmp;
950 enum ieee80211_band band = b43_current_band(dev->wl);
161d540c
RM		 951
952 if (nphy->hang_avoid)
953 b43_nphy_stay_in_carrier_search(dev, 1);
954
955 nphy->txpwrctrl = enable;
956 if (!enable) {
c9c0d9ec
RM		 957 if (dev->phy.rev >= 3 &&
958 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
959 (B43_NPHY_TXPCTL_CMD_COEFF |
960 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
961 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
962 /* We disable enabled TX pwr ctl, save it's state */
963 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
964 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
965 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
966 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
967 }
161d540c
RM		 968
969 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
970 for (i = 0; i < 84; i++)
971 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
972
973 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
974 for (i = 0; i < 84; i++)
975 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
976
977 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
978 if (dev->phy.rev >= 3)
979 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
980 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
981
982 if (dev->phy.rev >= 3) {
983 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
984 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
985 } else {
986 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
987 }
988
989 if (dev->phy.rev == 2)
990 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
991 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
992 else if (dev->phy.rev < 2)
993 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
994 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
995
c9c0d9ec
RM		 996 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
997 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 998 } else {
c9c0d9ec
RM		 999 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
1000 nphy->adj_pwr_tbl);
1001 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
1002 nphy->adj_pwr_tbl);
1003
1004 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
1005 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1006 /* wl does useless check for "enable" param here */
1007 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1008 if (dev->phy.rev >= 3) {
1009 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1010 if (val)
1011 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1012 }
1013 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
1014
1015 if (band == IEEE80211_BAND_5GHZ) {
1016 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
1017 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
1018 if (dev->phy.rev > 1)
1019 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
1020 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
1021 0x64);
1022 }
1023
1024 if (dev->phy.rev >= 3) {
1025 if (nphy->tx_pwr_idx[0] != 128 &&
1026 nphy->tx_pwr_idx[1] != 128) {
1027 /* Recover TX pwr ctl state */
1028 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
1029 ~B43_NPHY_TXPCTL_CMD_INIT,
1030 nphy->tx_pwr_idx[0]);
1031 if (dev->phy.rev > 1)
1032 b43_phy_maskset(dev,
1033 B43_NPHY_TXPCTL_INIT,
1034 ~0xff, nphy->tx_pwr_idx[1]);
1035 }
1036 }
1037
1038 if (dev->phy.rev >= 3) {
1039 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
1040 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
1041 } else {
1042 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
1043 }
1044
1045 if (dev->phy.rev == 2)
1046 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
1047 else if (dev->phy.rev < 2)
1048 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
1049
1050 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
1051 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
1052
c002831a 1053 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 1054 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
1055 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
1056 }
161d540c
RM		 1057 }
1058
1059 if (nphy->hang_avoid)
1060 b43_nphy_stay_in_carrier_search(dev, 0);
1061}
1062
1063/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314
MB		 1064static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
1065{
161d540c 1066 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1067 struct ssb_sprom *sprom = dev->dev->bus_sprom;
161d540c
RM		 1068
1069 u8 txpi[2], bbmult, i;
1070 u16 tmp, radio_gain, dac_gain;
1071 u16 freq = dev->phy.channel_freq;
1072 u32 txgain;
1073 /* u32 gaintbl; rev3+ */
1074
1075 if (nphy->hang_avoid)
1076 b43_nphy_stay_in_carrier_search(dev, 1);
1077
dd5f13b8
RM		 1078 if (dev->phy.rev >= 7) {
1079 txpi[0] = txpi[1] = 30;
1080 } else if (dev->phy.rev >= 3) {
161d540c
RM		 1081 txpi[0] = 40;
1082 txpi[1] = 40;
1083 } else if (sprom->revision < 4) {
1084 txpi[0] = 72;
1085 txpi[1] = 72;
1086 } else {
1087 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1088 txpi[0] = sprom->txpid2g[0];
1089 txpi[1] = sprom->txpid2g[1];
1090 } else if (freq >= 4900 && freq < 5100) {
1091 txpi[0] = sprom->txpid5gl[0];
1092 txpi[1] = sprom->txpid5gl[1];
1093 } else if (freq >= 5100 && freq < 5500) {
1094 txpi[0] = sprom->txpid5g[0];
1095 txpi[1] = sprom->txpid5g[1];
1096 } else if (freq >= 5500) {
1097 txpi[0] = sprom->txpid5gh[0];
1098 txpi[1] = sprom->txpid5gh[1];
1099 } else {
1100 txpi[0] = 91;
1101 txpi[1] = 91;
1102 }
1103 }
dd5f13b8
RM		 1104 if (dev->phy.rev < 7 &&
1105 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
1106 txpi[0] = txpi[1] = 91;
161d540c
RM		 1107
1108 /*
1109 for (i = 0; i < 2; i++) {
1110 nphy->txpwrindex[i].index_internal = txpi[i];
1111 nphy->txpwrindex[i].index_internal_save = txpi[i];
1112 }
1113 */
1114
1115 for (i = 0; i < 2; i++) {
1116 if (dev->phy.rev >= 3) {
dd5f13b8
RM		 1117 if (b43_nphy_ipa(dev)) {
1118 txgain = *(b43_nphy_get_ipa_gain_table(dev) +
1119 txpi[i]);
1120 } else if (b43_current_band(dev->wl) ==
1121 IEEE80211_BAND_5GHZ) {
1122 /* FIXME: use 5GHz tables */
1123 txgain =
1124 b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
1125 } else {
1126 if (dev->phy.rev >= 5 &&
1127 sprom->fem.ghz5.extpa_gain == 3)
1128 ; /* FIXME: 5GHz_txgain_HiPwrEPA */
1129 txgain =
1130 b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
1131 }
161d540c
RM		 1132 radio_gain = (txgain >> 16) & 0x1FFFF;
1133 } else {
1134 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
1135 radio_gain = (txgain >> 16) & 0x1FFF;
1136 }
1137
dd5f13b8
RM		 1138 if (dev->phy.rev >= 7)
1139 dac_gain = (txgain >> 8) & 0x7;
1140 else
1141 dac_gain = (txgain >> 8) & 0x3F;
161d540c
RM		 1142 bbmult = txgain & 0xFF;
1143
1144 if (dev->phy.rev >= 3) {
1145 if (i == 0)
1146 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
1147 else
1148 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
1149 } else {
1150 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
1151 }
1152
1153 if (i == 0)
1154 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
1155 else
1156 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
1157
44f4008b 1158 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
161d540c 1159
44f4008b 1160 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 1161 if (i == 0)
1162 tmp = (tmp & 0x00FF) | (bbmult << 8);
1163 else
1164 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 1165 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 1166
0eff8fcd
RM		 1167 if (b43_nphy_ipa(dev)) {
1168 u32 tmp32;
1169 u16 reg = (i == 0) ?
1170 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 1171 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
1172 576 + txpi[i]));
0eff8fcd
RM		 1173 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
1174 b43_phy_set(dev, reg, 0x4);
1175 }
161d540c
RM		 1176 }
1177
1178 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
1179
1180 if (nphy->hang_avoid)
1181 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 1182}
1183
0eff8fcd
RM		 1184static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
1185{
1186 struct b43_phy *phy = &dev->phy;
1187
1188 const u32 *table = NULL;
1189#if 0
1190 TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
1191 u32 rfpwr_offset;
1192 u8 pga_gain;
1193 int i;
1194#endif
1195
1196 if (phy->rev >= 3) {
1197 if (b43_nphy_ipa(dev)) {
1198 table = b43_nphy_get_ipa_gain_table(dev);
1199 } else {
1200 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1201 if (phy->rev == 3)
1202 table = b43_ntab_tx_gain_rev3_5ghz;
1203 if (phy->rev == 4)
1204 table = b43_ntab_tx_gain_rev4_5ghz;
1205 else
1206 table = b43_ntab_tx_gain_rev5plus_5ghz;
1207 } else {
1208 table = b43_ntab_tx_gain_rev3plus_2ghz;
1209 }
1210 }
1211 } else {
1212 table = b43_ntab_tx_gain_rev0_1_2;
1213 }
1214 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
1215 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
1216
1217 if (phy->rev >= 3) {
1218#if 0
1219 nphy->gmval = (table[0] >> 16) & 0x7000;
1220
1221 for (i = 0; i < 128; i++) {
1222 pga_gain = (table[i] >> 24) & 0xF;
1223 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1224 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
1225 else
1226 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
1227 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
1228 rfpwr_offset);
1229 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
1230 rfpwr_offset);
1231 }
1232#endif
1233 }
1234}
7955de0c 1235
4772ae10
RM		 1236/*
1237 * Upload the N-PHY tables.
1238 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
1239 */
95b66bad
MB		 1240static void b43_nphy_tables_init(struct b43_wldev *dev)
1241{
4772ae10
RM		 1242 if (dev->phy.rev < 3)
1243 b43_nphy_rev0_1_2_tables_init(dev);
1244 else
1245 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 1246}
1247
e50cbcf6
RM		 1248/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
1249static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
1250{
1251 struct b43_phy_n *nphy = dev->phy.n;
1252 enum ieee80211_band band;
1253 u16 tmp;
1254
1255 if (!enable) {
1256 nphy->rfctrl_intc1_save = b43_phy_read(dev,
1257 B43_NPHY_RFCTL_INTC1);
1258 nphy->rfctrl_intc2_save = b43_phy_read(dev,
1259 B43_NPHY_RFCTL_INTC2);
1260 band = b43_current_band(dev->wl);
1261 if (dev->phy.rev >= 3) {
1262 if (band == IEEE80211_BAND_5GHZ)
1263 tmp = 0x600;
1264 else
1265 tmp = 0x480;
1266 } else {
1267 if (band == IEEE80211_BAND_5GHZ)
1268 tmp = 0x180;
1269 else
1270 tmp = 0x120;
1271 }
1272 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1273 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1274 } else {
1275 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
1276 nphy->rfctrl_intc1_save);
1277 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
1278 nphy->rfctrl_intc2_save);
1279 }
1280}
1281
fe3e46e8
RM		 1282/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
1283static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
1284{
fe3e46e8 1285 u16 tmp;
fe3e46e8
RM		 1286
1287 if (dev->phy.rev >= 3) {
c002831a 1288 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 1289 tmp = 4;
1290 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
1291 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
1292 }
1293
1294 tmp = 1;
1295 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
1296 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
1297 }
1298}
1299
ad9716e8
RM		 1300/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
1301static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
1302{
1303 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
1304
1305 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
1306 if (preamble == 1)
1307 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
1308 else
1309 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
1310
1311 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
1312}
1313
4f4ab6cd
RM		 1314/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
1315static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
1316{
1317 struct b43_phy_n *nphy = dev->phy.n;
1318
1319 bool override = false;
1320 u16 chain = 0x33;
1321
1322 if (nphy->txrx_chain == 0) {
1323 chain = 0x11;
1324 override = true;
1325 } else if (nphy->txrx_chain == 1) {
1326 chain = 0x22;
1327 override = true;
1328 }
1329
1330 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1331 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
1332 chain);
1333
1334 if (override)
1335 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1336 B43_NPHY_RFSEQMODE_CAOVER);
1337 else
1338 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1339 ~B43_NPHY_RFSEQMODE_CAOVER);
1340}
1341
2faa6b83
RM		 1342/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
1343static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
1344 u16 samps, u8 time, bool wait)
1345{
1346 int i;
1347 u16 tmp;
1348
1349 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
1350 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
1351 if (wait)
1352 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
1353 else
1354 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
1355
1356 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
1357
1358 for (i = 1000; i; i--) {
1359 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
1360 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
1361 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
1362 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
1363 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
1364 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
1365 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
1366 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
1367
1368 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
1369 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
1370 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
1371 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
1372 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
1373 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
1374 return;
1375 }
1376 udelay(10);
1377 }
1378 memset(est, 0, sizeof(*est));
1379}
1380
a67162ab
RM		 1381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
1382static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
1383 struct b43_phy_n_iq_comp *pcomp)
1384{
1385 if (write) {
1386 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
1387 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
1388 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
1389 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
1390 } else {
1391 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
1392 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
1393 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
1394 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
1395 }
1396}
1397
c7455cf9
RM		 1398#if 0
1399/* Ready but not used anywhere */
026816fc
RM		 1400/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
1401static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
1402{
1403 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1404
1405 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
1406 if (core == 0) {
1407 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
1408 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1409 } else {
1410 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1411 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1412 }
1413 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
1414 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
1415 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
1416 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
1417 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
1418 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
1419 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1420 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1421}
1422
1423/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
1424static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
1425{
1426 u8 rxval, txval;
1427 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1428
1429 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
1430 if (core == 0) {
1431 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1432 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1433 } else {
1434 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1435 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1436 }
1437 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1438 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1439 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1440 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1441 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
1442 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1443 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1444 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1445
1446 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1447 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1448
acd82aa8
LF		 1449 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1450 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 1451 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
1452 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
1453 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
1454 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
1455 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
1456 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
1457 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
1458
1459 if (core == 0) {
1460 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
1461 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
1462 } else {
1463 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
1464 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
1465 }
1466
67cbc3ed
RM		 1467 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
1468 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 1469 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 1470
1471 if (core == 0) {
1472 rxval = 1;
1473 txval = 8;
1474 } else {
1475 rxval = 4;
1476 txval = 2;
1477 }
67cbc3ed
RM		 1478 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
1479 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc 1480}
c7455cf9 1481#endif
026816fc 1482
34a56f2c
RM		 1483/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
1484static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
1485{
1486 int i;
1487 s32 iq;
1488 u32 ii;
1489 u32 qq;
1490 int iq_nbits, qq_nbits;
1491 int arsh, brsh;
1492 u16 tmp, a, b;
1493
1494 struct nphy_iq_est est;
1495 struct b43_phy_n_iq_comp old;
1496 struct b43_phy_n_iq_comp new = { };
1497 bool error = false;
1498
1499 if (mask == 0)
1500 return;
1501
1502 b43_nphy_rx_iq_coeffs(dev, false, &old);
1503 b43_nphy_rx_iq_coeffs(dev, true, &new);
1504 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
1505 new = old;
1506
1507 for (i = 0; i < 2; i++) {
1508 if (i == 0 && (mask & 1)) {
1509 iq = est.iq0_prod;
1510 ii = est.i0_pwr;
1511 qq = est.q0_pwr;
1512 } else if (i == 1 && (mask & 2)) {
1513 iq = est.iq1_prod;
1514 ii = est.i1_pwr;
1515 qq = est.q1_pwr;
1516 } else {
34a56f2c
RM		 1517 continue;
1518 }
1519
1520 if (ii + qq < 2) {
1521 error = true;
1522 break;
1523 }
1524
1525 iq_nbits = fls(abs(iq));
1526 qq_nbits = fls(qq);
1527
1528 arsh = iq_nbits - 20;
1529 if (arsh >= 0) {
1530 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
1531 tmp = ii >> arsh;
1532 } else {
1533 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
1534 tmp = ii << -arsh;
1535 }
1536 if (tmp == 0) {
1537 error = true;
1538 break;
1539 }
1540 a /= tmp;
1541
1542 brsh = qq_nbits - 11;
1543 if (brsh >= 0) {
1544 b = (qq << (31 - qq_nbits));
1545 tmp = ii >> brsh;
1546 } else {
1547 b = (qq << (31 - qq_nbits));
1548 tmp = ii << -brsh;
1549 }
1550 if (tmp == 0) {
1551 error = true;
1552 break;
1553 }
1554 b = int_sqrt(b / tmp - a * a) - (1 << 10);
1555
1556 if (i == 0 && (mask & 0x1)) {
1557 if (dev->phy.rev >= 3) {
1558 new.a0 = a & 0x3FF;
1559 new.b0 = b & 0x3FF;
1560 } else {
1561 new.a0 = b & 0x3FF;
1562 new.b0 = a & 0x3FF;
1563 }
1564 } else if (i == 1 && (mask & 0x2)) {
1565 if (dev->phy.rev >= 3) {
1566 new.a1 = a & 0x3FF;
1567 new.b1 = b & 0x3FF;
1568 } else {
1569 new.a1 = b & 0x3FF;
1570 new.b1 = a & 0x3FF;
1571 }
1572 }
1573 }
1574
1575 if (error)
1576 new = old;
1577
1578 b43_nphy_rx_iq_coeffs(dev, true, &new);
1579}
1580
09146400
RM		 1581/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1582static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1583{
1584 u16 array[4];
44f4008b 1585 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 1586
1587 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1588 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1589 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1590 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1591}
1592
8987a9e9
RM		 1593/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1594static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1595{
1596 if (dev->phy.rev >= 3) {
1597 if (!init)
1598 return;
1599 if (0 /* FIXME */) {
1600 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1601 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1602 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1603 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1604 }
1605 } else {
1606 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1607 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1608
6cbab0d9 1609 switch (dev->dev->bus_type) {
42c9a458
RM		 1610#ifdef CONFIG_B43_BCMA
1611 case B43_BUS_BCMA:
1612 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1613 0xFC00, 0xFC00);
1614 break;
1615#endif
6cbab0d9
RM		 1616#ifdef CONFIG_B43_SSB
1617 case B43_BUS_SSB:
1618 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1619 0xFC00, 0xFC00);
1620 break;
1621#endif
1622 }
1623
8987a9e9
RM		 1624 b43_write32(dev, B43_MMIO_MACCTL,
1625 b43_read32(dev, B43_MMIO_MACCTL) &
1626 ~B43_MACCTL_GPOUTSMSK);
1627 b43_write16(dev, B43_MMIO_GPIO_MASK,
ab499217
RM		 1628 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1629 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1630 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1631
1632 if (init) {
1633 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1634 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1635 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1636 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5c1a140a
RM		 1637 }
1638 }
1639}
1640
53ae8e8c
RM		 1641/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1642static void b43_nphy_stop_playback(struct b43_wldev *dev)
1643{
1644 struct b43_phy_n *nphy = dev->phy.n;
1645 u16 tmp;
1646
1647 if (nphy->hang_avoid)
1648 b43_nphy_stay_in_carrier_search(dev, 1);
1649
1650 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1651 if (tmp & 0x1)
1652 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1653 else if (tmp & 0x2)
acd82aa8 1654 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
53ae8e8c
RM		 1655
1656 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1657
1658 if (nphy->bb_mult_save & 0x80000000) {
1659 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 1660 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 1661 nphy->bb_mult_save = 0;
1662 }
1663
1664 if (nphy->hang_avoid)
1665 b43_nphy_stay_in_carrier_search(dev, 0);
1666}
1667
9442e5b5
RM		 1668/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1669static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1670{
1671 struct b43_phy_n *nphy = dev->phy.n;
1672
204a665b 1673 u8 channel = dev->phy.channel;
9442e5b5
RM		 1674 int tone[2] = { 57, 58 };
1675 u32 noise[2] = { 0x3FF, 0x3FF };
1676
1677 B43_WARN_ON(dev->phy.rev < 3);
1678
1679 if (nphy->hang_avoid)
1680 b43_nphy_stay_in_carrier_search(dev, 1);
1681
9442e5b5
RM		 1682 if (nphy->gband_spurwar_en) {
1683 /* TODO: N PHY Adjust Analog Pfbw (7) */
1684 if (channel == 11 && dev->phy.is_40mhz)
1685 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1686 else
1687 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1688 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1689 }
1690
1691 if (nphy->aband_spurwar_en) {
1692 if (channel == 54) {
1693 tone[0] = 0x20;
1694 noise[0] = 0x25F;
1695 } else if (channel == 38 || channel == 102 || channel == 118) {
1696 if (0 /* FIXME */) {
1697 tone[0] = 0x20;
1698 noise[0] = 0x21F;
1699 } else {
1700 tone[0] = 0;
1701 noise[0] = 0;
1702 }
1703 } else if (channel == 134) {
1704 tone[0] = 0x20;
1705 noise[0] = 0x21F;
1706 } else if (channel == 151) {
1707 tone[0] = 0x10;
1708 noise[0] = 0x23F;
1709 } else if (channel == 153 || channel == 161) {
1710 tone[0] = 0x30;
1711 noise[0] = 0x23F;
1712 } else {
1713 tone[0] = 0;
1714 noise[0] = 0;
1715 }
1716
1717 if (!tone[0] && !noise[0])
1718 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1719 else
1720 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1721 }
1722
1723 if (nphy->hang_avoid)
1724 b43_nphy_stay_in_carrier_search(dev, 0);
1725}
1726
d24019ad
RM		 1727/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1728static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1729{
1730 struct b43_phy_n *nphy = dev->phy.n;
1731
1732 u8 i;
1733 s16 tmp;
1734 u16 data[4];
1735 s16 gain[2];
1736 u16 minmax[2];
20407ed8 1737 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
d24019ad
RM		 1738
1739 if (nphy->hang_avoid)
1740 b43_nphy_stay_in_carrier_search(dev, 1);
1741
1742 if (nphy->gain_boost) {
1743 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1744 gain[0] = 6;
1745 gain[1] = 6;
1746 } else {
204a665b 1747 tmp = 40370 - 315 * dev->phy.channel;
d24019ad 1748 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
204a665b 1749 tmp = 23242 - 224 * dev->phy.channel;
d24019ad
RM		 1750 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1751 }
1752 } else {
1753 gain[0] = 0;
1754 gain[1] = 0;
1755 }
1756
1757 for (i = 0; i < 2; i++) {
1758 if (nphy->elna_gain_config) {
1759 data[0] = 19 + gain[i];
1760 data[1] = 25 + gain[i];
1761 data[2] = 25 + gain[i];
1762 data[3] = 25 + gain[i];
1763 } else {
1764 data[0] = lna_gain[0] + gain[i];
1765 data[1] = lna_gain[1] + gain[i];
1766 data[2] = lna_gain[2] + gain[i];
1767 data[3] = lna_gain[3] + gain[i];
1768 }
c0f05b98 1769 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
d24019ad
RM		 1770
1771 minmax[i] = 23 + gain[i];
1772 }
1773
1774 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1775 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1776 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1777 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1778
1779 if (nphy->hang_avoid)
1780 b43_nphy_stay_in_carrier_search(dev, 0);
1781}
1782
ef5127a4 1783/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
e723ef30 1784static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
ef5127a4
RM		 1785{
1786 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1787 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ba9a6214
RM		 1788
1789 /* PHY rev 0, 1, 2 */
ef5127a4
RM		 1790 u8 i, j;
1791 u8 code;
c0f05b98 1792 u16 tmp;
ba9a6214
RM		 1793 u8 rfseq_events[3] = { 6, 8, 7 };
1794 u8 rfseq_delays[3] = { 10, 30, 1 };
ef5127a4 1795
ba9a6214
RM		 1796 /* PHY rev >= 3 */
1797 bool ghz5;
1798 bool ext_lna;
1799 u16 rssi_gain;
1800 struct nphy_gain_ctl_workaround_entry *e;
ef5127a4
RM		 1801 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1802 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
ef5127a4
RM		 1803
1804 if (dev->phy.rev >= 3) {
ba9a6214
RM		 1805 /* Prepare values */
1806 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1807 & B43_NPHY_BANDCTL_5GHZ;
1808 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1809 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1810 if (ghz5 && dev->phy.rev >= 5)
1811 rssi_gain = 0x90;
1812 else
1813 rssi_gain = 0x50;
1814
1815 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1816
1817 /* Set Clip 2 detect */
1818 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1819 B43_NPHY_C1_CGAINI_CL2DETECT);
1820 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1821 B43_NPHY_C2_CGAINI_CL2DETECT);
1822
1823 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1824 0x17);
1825 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1826 0x17);
1827 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1828 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1829 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1830 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1831 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1832 rssi_gain);
1833 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1834 rssi_gain);
1835 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1836 0x17);
1837 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1838 0x17);
1839 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1840 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1841
1842 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1843 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1844 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1845 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1846 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1847 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1848 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1849 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1850 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1851 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1852 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1853 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1854
1855 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1856 b43_phy_write(dev, 0x2A7, e->init_gain);
1857 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1858 e->rfseq_init);
1859 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1860
1861 /* TODO: check defines. Do not match variables names */
1862 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1863 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1864 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1865 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1866 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1867 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1868
1869 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1870 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1871 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1872 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1873 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1874 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1875 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1876 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1877 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1878 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1879 } else {
1880 /* Set Clip 2 detect */
1881 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1882 B43_NPHY_C1_CGAINI_CL2DETECT);
1883 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1884 B43_NPHY_C2_CGAINI_CL2DETECT);
1885
1886 /* Set narrowband clip threshold */
a5d3598d
RM		 1887 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1888 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
ef5127a4
RM		 1889
1890 if (!dev->phy.is_40mhz) {
1891 /* Set dwell lengths */
a5d3598d
RM		 1892 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1893 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1894 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1895 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
ef5127a4
RM		 1896 }
1897
1898 /* Set wideband clip 2 threshold */
1899 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1900 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1901 21);
1902 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1903 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1904 21);
1905
1906 if (!dev->phy.is_40mhz) {
1907 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1908 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1909 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1910 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1911 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1912 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1913 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1914 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1915 }
1916
a5d3598d 1917 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1918
1919 if (nphy->gain_boost) {
1920 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1921 dev->phy.is_40mhz)
1922 code = 4;
1923 else
1924 code = 5;
1925 } else {
1926 code = dev->phy.is_40mhz ? 6 : 7;
1927 }
1928
1929 /* Set HPVGA2 index */
1930 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1931 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1932 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1933 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1934 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1935 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1936
1937 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1938 /* specs say about 2 loops, but wl does 4 */
1939 for (i = 0; i < 4; i++)
1940 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1941 (code << 8 | 0x7C));
ef5127a4 1942
d24019ad 1943 b43_nphy_adjust_lna_gain_table(dev);
ef5127a4
RM		 1944
1945 if (nphy->elna_gain_config) {
1946 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1947 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1948 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1949 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1950 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1951
1952 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1953 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1954 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1955 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1956 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1957
1958 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1959 /* specs say about 2 loops, but wl does 4 */
1960 for (i = 0; i < 4; i++)
1961 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1962 (code << 8 | 0x74));
ef5127a4
RM		 1963 }
1964
1965 if (dev->phy.rev == 2) {
1966 for (i = 0; i < 4; i++) {
1967 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1968 (0x0400 * i) + 0x0020);
c0f05b98
RM		 1969 for (j = 0; j < 21; j++) {
1970 tmp = j * (i < 2 ? 3 : 1);
ef5127a4 1971 b43_phy_write(dev,
c0f05b98
RM		 1972 B43_NPHY_TABLE_DATALO, tmp);
1973 }
ef5127a4 1974 }
8e60b044 1975 }
ef5127a4 1976
8e60b044
RM		 1977 b43_nphy_set_rf_sequence(dev, 5,
1978 rfseq_events, rfseq_delays, 3);
1979 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1980 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1981 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
ef5127a4 1982
8e60b044
RM		 1983 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1984 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1985 0xFF80, 4);
ef5127a4
RM		 1986 }
1987}
1988
73d07a39 1989static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 1990{
0eff8fcd 1991 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1992 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 1993
0eff8fcd 1994 /* TX to RX */
c56da252
RM		 1995 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1996 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
0eff8fcd
RM		 1997 /* RX to TX */
1998 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1999 0x1F };
2000 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2001 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2002 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2003
ba9a6214
RM		 2004 u16 tmp16;
2005 u32 tmp32;
2006
c56da252
RM		 2007 b43_phy_write(dev, 0x23f, 0x1f8);
2008 b43_phy_write(dev, 0x240, 0x1f8);
2009
73d07a39
RM		 2010 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2011 tmp32 &= 0xffffff;
2012 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2013
73d07a39
RM		 2014 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2015 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2016 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2017 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2018 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2019 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2020
73d07a39
RM		 2021 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2022 b43_phy_write(dev, 0x2AE, 0x000C);
ba9a6214 2023
0eff8fcd 2024 /* TX to RX */
c56da252
RM		 2025 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2026 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2027
2028 /* RX to TX */
2029 if (b43_nphy_ipa(dev))
c56da252
RM		 2030 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2031 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2032 if (nphy->hw_phyrxchain != 3 &&
2033 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2034 if (b43_nphy_ipa(dev)) {
2035 rx2tx_delays[5] = 59;
2036 rx2tx_delays[6] = 1;
2037 rx2tx_events[7] = 0x1F;
2038 }
c56da252
RM		 2039 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
2040 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2041 }
ba9a6214 2042
73d07a39
RM		 2043 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2044 0x2 : 0x9C40;
2045 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2046
73d07a39 2047 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
ba9a6214 2048
73d07a39
RM		 2049 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2050 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
ba9a6214 2051
73d07a39 2052 b43_nphy_gain_ctrl_workarounds(dev);
ba9a6214 2053
c56da252
RM		 2054 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2055 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2056
73d07a39 2057 /* TODO */
ba9a6214 2058
73d07a39
RM		 2059 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2060 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2061 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2062 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2063 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2064 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2065 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2066 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2067 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2068 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2069 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2070 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2071
2072 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2073
2074 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2075 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2076 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2077 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2078 tmp32 = 0x00088888;
2079 else
2080 tmp32 = 0x88888888;
2081 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2082 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2083 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2084
2085 if (dev->phy.rev == 4 &&
2086 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2087 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2088 0x70);
2089 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2090 0x70);
2091 }
ba9a6214 2092
3c17dd41
RM		 2093 b43_phy_write(dev, 0x224, 0x03eb);
2094 b43_phy_write(dev, 0x225, 0x03eb);
2095 b43_phy_write(dev, 0x226, 0x0341);
2096 b43_phy_write(dev, 0x227, 0x0341);
2097 b43_phy_write(dev, 0x228, 0x042b);
2098 b43_phy_write(dev, 0x229, 0x042b);
2099 b43_phy_write(dev, 0x22a, 0x0381);
2100 b43_phy_write(dev, 0x22b, 0x0381);
2101 b43_phy_write(dev, 0x22c, 0x042b);
2102 b43_phy_write(dev, 0x22d, 0x042b);
2103 b43_phy_write(dev, 0x22e, 0x0381);
2104 b43_phy_write(dev, 0x22f, 0x0381);
73d07a39 2105}
ba9a6214 2106
73d07a39
RM		 2107static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2108{
2109 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2110 struct b43_phy *phy = &dev->phy;
2111 struct b43_phy_n *nphy = phy->n;
ba9a6214 2112
73d07a39
RM		 2113 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2114 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2115
73d07a39
RM		 2116 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2117 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2118
73d07a39
RM		 2119 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2120 nphy->band5g_pwrgain) {
2121 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2122 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2123 } else {
73d07a39
RM		 2124 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2125 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2126 }
28fd7daa 2127
73d07a39
RM		 2128 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2129 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2130 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2131 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2132
2133 if (dev->phy.rev < 2) {
2134 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2135 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2136 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2137 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2138 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2139 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2140 }
28fd7daa 2141
73d07a39
RM		 2142 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2143 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2144 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2145 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2146
0eff8fcd
RM		 2147 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
2148 dev->dev->board_type == 0x8B) {
73d07a39
RM		 2149 delays1[0] = 0x1;
2150 delays1[5] = 0x14;
2151 }
2152 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2153 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2154
2155 b43_nphy_gain_ctrl_workarounds(dev);
2156
2157 if (dev->phy.rev < 2) {
2158 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2159 b43_hf_write(dev, b43_hf_read(dev) |
2160 B43_HF_MLADVW);
2161 } else if (dev->phy.rev == 2) {
2162 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2163 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2164 }
28fd7daa 2165
73d07a39
RM		 2166 if (dev->phy.rev < 2)
2167 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2168 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2169
2170 /* Set phase track alpha and beta */
2171 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2172 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2173 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2174 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2175 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2176 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2177
2178 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2179 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2180 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2181 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2182 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2183
2184 if (dev->phy.rev == 2)
2185 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2186 B43_NPHY_FINERX2_CGC_DECGC);
2187}
28fd7daa 2188
73d07a39
RM		 2189/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2190static void b43_nphy_workarounds(struct b43_wldev *dev)
2191{
2192 struct b43_phy *phy = &dev->phy;
2193 struct b43_phy_n *nphy = phy->n;
28fd7daa 2194
73d07a39
RM		 2195 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2196 b43_nphy_classifier(dev, 1, 0);
2197 else
2198 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2199
73d07a39
RM		 2200 if (nphy->hang_avoid)
2201 b43_nphy_stay_in_carrier_search(dev, 1);
2202
2203 b43_phy_set(dev, B43_NPHY_IQFLIP,
2204 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2205
2206 if (dev->phy.rev >= 3)
2207 b43_nphy_workarounds_rev3plus(dev);
2208 else
2209 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2210
2211 if (nphy->hang_avoid)
2212 b43_nphy_stay_in_carrier_search(dev, 0);
2213}
2214
59af099b
RM		 2215/*
2216 * Transmits a known value for LO calibration
2217 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2218 */
2219static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2220 bool iqmode, bool dac_test)
2221{
2222 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2223 if (samp == 0)
2224 return -1;
2225 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2226 return 0;
2227}
2228
6dcd9d91
RM		 2229/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
2230static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
2231{
2232 struct b43_phy_n *nphy = dev->phy.n;
2233 int i, j;
2234 u32 tmp;
2235 u32 cur_real, cur_imag, real_part, imag_part;
2236
2237 u16 buffer[7];
2238
2239 if (nphy->hang_avoid)
2240 b43_nphy_stay_in_carrier_search(dev, true);
2241
9145834e 2242 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 2243
2244 for (i = 0; i < 2; i++) {
2245 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
2246 (buffer[i * 2 + 1] & 0x3FF);
2247 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2248 (((i + 26) << 10) | 320));
2249 for (j = 0; j < 128; j++) {
2250 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2251 ((tmp >> 16) & 0xFFFF));
2252 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2253 (tmp & 0xFFFF));
2254 }
2255 }
2256
2257 for (i = 0; i < 2; i++) {
2258 tmp = buffer[5 + i];
2259 real_part = (tmp >> 8) & 0xFF;
2260 imag_part = (tmp & 0xFF);
2261 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2262 (((i + 26) << 10) | 448));
2263
2264 if (dev->phy.rev >= 3) {
2265 cur_real = real_part;
2266 cur_imag = imag_part;
2267 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
2268 }
2269
2270 for (j = 0; j < 128; j++) {
2271 if (dev->phy.rev < 3) {
2272 cur_real = (real_part * loscale[j] + 128) >> 8;
2273 cur_imag = (imag_part * loscale[j] + 128) >> 8;
2274 tmp = ((cur_real & 0xFF) << 8) |
2275 (cur_imag & 0xFF);
2276 }
2277 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2278 ((tmp >> 16) & 0xFFFF));
2279 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2280 (tmp & 0xFFFF));
2281 }
2282 }
2283
2284 if (dev->phy.rev >= 3) {
2285 b43_shm_write16(dev, B43_SHM_SHARED,
2286 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2287 b43_shm_write16(dev, B43_SHM_SHARED,
2288 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
2289 }
2290
2291 if (nphy->hang_avoid)
2292 b43_nphy_stay_in_carrier_search(dev, false);
2293}
2294
bec18645 2295/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
95b66bad
MB		 2296static void b43_nphy_bphy_init(struct b43_wldev *dev)
2297{
2298 unsigned int i;
2299 u16 val;
2300
2301 val = 0x1E1F;
fee613b7 2302 for (i = 0; i < 16; i++) {
95b66bad
MB		 2303 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2304 val -= 0x202;
2305 }
2306 val = 0x3E3F;
2307 for (i = 0; i < 16; i++) {
fee613b7 2308 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
95b66bad
MB		 2309 val -= 0x202;
2310 }
2311 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2312}
2313
3c95627d
RM		 2314/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2315static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
76b002bd
RM		 2316 s8 offset, u8 core, u8 rail,
2317 enum b43_nphy_rssi_type type)
3c95627d
RM		 2318{
2319 u16 tmp;
2320 bool core1or5 = (core == 1) || (core == 5);
2321 bool core2or5 = (core == 2) || (core == 5);
2322
2323 offset = clamp_val(offset, -32, 31);
2324 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2325
76b002bd 2326 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2327 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
76b002bd 2328 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2329 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
76b002bd 2330 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2331 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
76b002bd 2332 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2333 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
76b002bd
RM		 2334
2335 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2336 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
76b002bd 2337 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2338 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
76b002bd 2339 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2340 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
76b002bd 2341 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2342 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
76b002bd
RM		 2343
2344 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2345 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
76b002bd 2346 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2347 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
76b002bd 2348 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2349 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
76b002bd 2350 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2351 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
76b002bd
RM		 2352
2353 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2354 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
76b002bd 2355 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2356 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
76b002bd 2357 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2358 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
76b002bd 2359 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2360 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
76b002bd
RM		 2361
2362 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2363 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
76b002bd 2364 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2365 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
76b002bd 2366 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2367 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
76b002bd 2368 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2369 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
76b002bd
RM		 2370
2371 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2372 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
76b002bd 2373 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2374 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
76b002bd
RM		 2375
2376 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d 2377 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
76b002bd 2378 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d
RM		 2379 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2380}
2381
99b82c41 2382static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
3c95627d
RM		 2383{
2384 u16 val;
2385
99b82c41
RM		 2386 if (type < 3)
2387 val = 0;
2388 else if (type == 6)
2389 val = 1;
2390 else if (type == 3)
2391 val = 2;
2392 else
2393 val = 3;
2394
2395 val = (val << 12) | (val << 14);
2396 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2397 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
3c95627d 2398
99b82c41
RM		 2399 if (type < 3) {
2400 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2401 (type + 1) << 4);
2402 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2403 (type + 1) << 4);
2404 }
3c95627d 2405
99b82c41 2406 if (code == 0) {
99f6c2ef 2407 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
3c95627d 2408 if (type < 3) {
99f6c2ef
RM		 2409 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2410 ~(B43_NPHY_RFCTL_CMD_RXEN |
2411 B43_NPHY_RFCTL_CMD_CORESEL));
2412 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2413 ~(0x1 << 12 |
2414 0x1 << 5 |
2415 0x1 << 1 |
2416 0x1));
2417 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2418 ~B43_NPHY_RFCTL_CMD_START);
99b82c41 2419 udelay(20);
99f6c2ef 2420 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d 2421 }
99b82c41 2422 } else {
99f6c2ef 2423 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
99b82c41
RM		 2424 if (type < 3) {
2425 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
99f6c2ef
RM		 2426 ~(B43_NPHY_RFCTL_CMD_RXEN |
2427 B43_NPHY_RFCTL_CMD_CORESEL),
2428 (B43_NPHY_RFCTL_CMD_RXEN |
2429 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2430 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2431 (0x1 << 12 |
2432 0x1 << 5 |
2433 0x1 << 1 |
2434 0x1));
2435 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2436 B43_NPHY_RFCTL_CMD_START);
99b82c41 2437 udelay(20);
99f6c2ef 2438 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d
RM		 2439 }
2440 }
2441}
2442
99b82c41
RM		 2443static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2444{
6e3b15a9
RM		 2445 u8 i;
2446 u16 reg, val;
2447
2448 if (code == 0) {
2449 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2450 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2451 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2452 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2453 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2454 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2455 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2456 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2457 } else {
2458 for (i = 0; i < 2; i++) {
2459 if ((code == 1 && i == 1) || (code == 2 && !i))
2460 continue;
2461
2462 reg = (i == 0) ?
2463 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2464 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2465
2466 if (type < 3) {
2467 reg = (i == 0) ?
2468 B43_NPHY_AFECTL_C1 :
2469 B43_NPHY_AFECTL_C2;
2470 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2471
2472 reg = (i == 0) ?
2473 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2474 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2475 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2476
2477 if (type == 0)
2478 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2479 else if (type == 1)
2480 val = 16;
2481 else
2482 val = 32;
2483 b43_phy_set(dev, reg, val);
2484
2485 reg = (i == 0) ?
2486 B43_NPHY_TXF_40CO_B1S0 :
2487 B43_NPHY_TXF_40CO_B32S1;
2488 b43_phy_set(dev, reg, 0x0020);
2489 } else {
2490 if (type == 6)
2491 val = 0x0100;
2492 else if (type == 3)
2493 val = 0x0200;
2494 else
2495 val = 0x0300;
2496
2497 reg = (i == 0) ?
2498 B43_NPHY_AFECTL_C1 :
2499 B43_NPHY_AFECTL_C2;
2500
2501 b43_phy_maskset(dev, reg, 0xFCFF, val);
2502 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2503
2504 if (type != 3 && type != 6) {
2505 enum ieee80211_band band =
2506 b43_current_band(dev->wl);
2507
c002831a 2508 if (b43_nphy_ipa(dev))
6e3b15a9
RM		 2509 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2510 else
2511 val = 0x11;
2512 reg = (i == 0) ? 0x2000 : 0x3000;
2513 reg |= B2055_PADDRV;
2514 b43_radio_write16(dev, reg, val);
2515
2516 reg = (i == 0) ?
2517 B43_NPHY_AFECTL_OVER1 :
2518 B43_NPHY_AFECTL_OVER;
2519 b43_phy_set(dev, reg, 0x0200);
2520 }
2521 }
2522 }
2523 }
99b82c41
RM		 2524}
2525
2526/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2527static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2528{
2529 if (dev->phy.rev >= 3)
2530 b43_nphy_rev3_rssi_select(dev, code, type);
2531 else
2532 b43_nphy_rev2_rssi_select(dev, code, type);
2533}
2534
dfb4aa5d
RM		 2535/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2536static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2537{
2538 int i;
2539 for (i = 0; i < 2; i++) {
2540 if (type == 2) {
2541 if (i == 0) {
2542 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2543 0xFC, buf[0]);
2544 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2545 0xFC, buf[1]);
2546 } else {
2547 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2548 0xFC, buf[2 * i]);
2549 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2550 0xFC, buf[2 * i + 1]);
2551 }
2552 } else {
2553 if (i == 0)
2554 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2555 0xF3, buf[0] << 2);
2556 else
2557 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2558 0xF3, buf[2 * i + 1] << 2);
2559 }
2560 }
2561}
2562
2563/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2564static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2565 u8 nsamp)
2566{
2567 int i;
2568 int out;
2569 u16 save_regs_phy[9];
2570 u16 s[2];
2571
2572 if (dev->phy.rev >= 3) {
2573 save_regs_phy[0] = b43_phy_read(dev,
2574 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2575 save_regs_phy[1] = b43_phy_read(dev,
2576 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2577 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2578 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2579 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2580 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2581 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2582 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2eeb6fd0 2583 save_regs_phy[8] = 0;
05db8c57 2584 } else {
a529cecd
RM		 2585 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2586 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2587 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2588 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2589 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2590 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2591 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2eeb6fd0
JL		 2592 save_regs_phy[7] = 0;
2593 save_regs_phy[8] = 0;
dfb4aa5d
RM		 2594 }
2595
2596 b43_nphy_rssi_select(dev, 5, type);
2597
2598 if (dev->phy.rev < 2) {
2599 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2600 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2601 }
2602
2603 for (i = 0; i < 4; i++)
2604 buf[i] = 0;
2605
2606 for (i = 0; i < nsamp; i++) {
2607 if (dev->phy.rev < 2) {
2608 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2609 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2610 } else {
2611 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2612 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2613 }
2614
2615 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2616 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2617 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2618 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2619 }
2620 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2621 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2622
2623 if (dev->phy.rev < 2)
2624 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2625
2626 if (dev->phy.rev >= 3) {
2627 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2628 save_regs_phy[0]);
2629 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2630 save_regs_phy[1]);
2631 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2632 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2633 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2634 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2635 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2636 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
05db8c57 2637 } else {
a529cecd
RM		 2638 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2639 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2640 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2641 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2642 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2643 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2644 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
dfb4aa5d
RM		 2645 }
2646
2647 return out;
2648}
2649
4cb99775
RM		 2650/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2651static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 2652{
90b9738d
RM		 2653 int i, j;
2654 u8 state[4];
2655 u8 code, val;
2656 u16 class, override;
2657 u8 regs_save_radio[2];
2658 u16 regs_save_phy[2];
8cbe6e66 2659
90b9738d 2660 s8 offset[4];
8cbe6e66
RM		 2661 u8 core;
2662 u8 rail;
90b9738d
RM		 2663
2664 u16 clip_state[2];
2665 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2666 s32 results_min[4] = { };
2667 u8 vcm_final[4] = { };
2668 s32 results[4][4] = { };
2669 s32 miniq[4][2] = { };
2670
2671 if (type == 2) {
2672 code = 0;
2673 val = 6;
2674 } else if (type < 2) {
2675 code = 25;
2676 val = 4;
2677 } else {
2678 B43_WARN_ON(1);
2679 return;
2680 }
2681
2682 class = b43_nphy_classifier(dev, 0, 0);
2683 b43_nphy_classifier(dev, 7, 4);
2684 b43_nphy_read_clip_detection(dev, clip_state);
2685 b43_nphy_write_clip_detection(dev, clip_off);
2686
2687 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2688 override = 0x140;
2689 else
2690 override = 0x110;
2691
2692 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2693 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2694 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2695 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2696
2697 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2698 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2699 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2700 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2701
2702 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2703 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2704 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2705 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2706 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2707 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2708
2709 b43_nphy_rssi_select(dev, 5, type);
2710 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2711 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2712
2713 for (i = 0; i < 4; i++) {
2714 u8 tmp[4];
2715 for (j = 0; j < 4; j++)
2716 tmp[j] = i;
2717 if (type != 1)
2718 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2719 b43_nphy_poll_rssi(dev, type, results[i], 8);
2720 if (type < 2)
2721 for (j = 0; j < 2; j++)
2722 miniq[i][j] = min(results[i][2 * j],
2723 results[i][2 * j + 1]);
2724 }
2725
2726 for (i = 0; i < 4; i++) {
2727 s32 mind = 40;
2728 u8 minvcm = 0;
2729 s32 minpoll = 249;
2730 s32 curr;
2731 for (j = 0; j < 4; j++) {
2732 if (type == 2)
2733 curr = abs(results[j][i]);
2734 else
2735 curr = abs(miniq[j][i / 2] - code * 8);
2736
2737 if (curr < mind) {
2738 mind = curr;
2739 minvcm = j;
2740 }
2741
2742 if (results[j][i] < minpoll)
2743 minpoll = results[j][i];
2744 }
2745 results_min[i] = minpoll;
2746 vcm_final[i] = minvcm;
2747 }
2748
2749 if (type != 1)
2750 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2751
2752 for (i = 0; i < 4; i++) {
2753 offset[i] = (code * 8) - results[vcm_final[i]][i];
2754
2755 if (offset[i] < 0)
2756 offset[i] = -((abs(offset[i]) + 4) / 8);
2757 else
2758 offset[i] = (offset[i] + 4) / 8;
2759
2760 if (results_min[i] == 248)
2761 offset[i] = code - 32;
2762
8cbe6e66
RM		 2763 core = (i / 2) ? 2 : 1;
2764 rail = (i % 2) ? 1 : 0;
2765
2766 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2767 type);
90b9738d
RM		 2768 }
2769
2770 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
0b81c23d 2771 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
90b9738d
RM		 2772
2773 switch (state[2]) {
2774 case 1:
2775 b43_nphy_rssi_select(dev, 1, 2);
2776 break;
2777 case 4:
2778 b43_nphy_rssi_select(dev, 1, 0);
2779 break;
2780 case 2:
2781 b43_nphy_rssi_select(dev, 1, 1);
2782 break;
2783 default:
2784 b43_nphy_rssi_select(dev, 1, 1);
2785 break;
2786 }
2787
2788 switch (state[3]) {
2789 case 1:
2790 b43_nphy_rssi_select(dev, 2, 2);
2791 break;
2792 case 4:
2793 b43_nphy_rssi_select(dev, 2, 0);
2794 break;
2795 default:
2796 b43_nphy_rssi_select(dev, 2, 1);
2797 break;
2798 }
2799
2800 b43_nphy_rssi_select(dev, 0, type);
2801
2802 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2803 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2804 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2805 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2806
2807 b43_nphy_classifier(dev, 7, class);
2808 b43_nphy_write_clip_detection(dev, clip_state);
8c1d5a7a
RM		 2809 /* Specs don't say about reset here, but it makes wl and b43 dumps
2810 identical, it really seems wl performs this */
2811 b43_nphy_reset_cca(dev);
4cb99775
RM		 2812}
2813
2814/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2815static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2816{
2817 /* TODO */
2818}
2819
2820/*
2821 * RSSI Calibration
2822 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2823 */
2824static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2825{
2826 if (dev->phy.rev >= 3) {
2827 b43_nphy_rev3_rssi_cal(dev);
2828 } else {
76b002bd
RM		 2829 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2830 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2831 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
4cb99775 2832 }
95b66bad
MB		 2833}
2834
42e1547e
RM		 2835/*
2836 * Restore RSSI Calibration
2837 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2838 */
2839static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2840{
2841 struct b43_phy_n *nphy = dev->phy.n;
2842
2843 u16 *rssical_radio_regs = NULL;
2844 u16 *rssical_phy_regs = NULL;
2845
2846 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2847 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 2848 return;
2849 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2850 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2851 } else {
204a665b 2852 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 2853 return;
2854 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2855 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2856 }
2857
2858 /* TODO use some definitions */
2859 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2860 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2861
2862 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2863 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2864 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2865 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2866
2867 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2868 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2869 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2870 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2871
2872 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2873 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2874 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2875 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2876}
2877
c4a92003
RM		 2878/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2879static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2880{
2881 struct b43_phy_n *nphy = dev->phy.n;
2882 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2883 u16 tmp;
2884 u8 offset, i;
c4a92003
RM		 2885
2886 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2887 for (i = 0; i < 2; i++) {
2888 tmp = (i == 0) ? 0x2000 : 0x3000;
2889 offset = i * 11;
2890
2891 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2892 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2893 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2894 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2895 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2896 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2897 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2898 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2899 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2900 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2901 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2902
2903 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2904 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2905 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2906 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2907 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2908 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2909 if (nphy->ipa5g_on) {
2910 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2911 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2912 } else {
2913 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2914 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2915 }
2916 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2917 } else {
2918 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2919 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2920 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2921 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2922 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2923 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2924 if (nphy->ipa2g_on) {
2925 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2926 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2927 (dev->phy.rev < 5) ? 0x11 : 0x01);
2928 } else {
2929 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2930 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2931 }
2932 }
2933 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2934 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2935 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2936 }
c4a92003
RM		 2937 } else {
2938 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2939 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2940
2941 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2942 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2943
2944 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2945 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2946
2947 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2948 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2949
2950 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2951 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2952
2953 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2954 B43_NPHY_BANDCTL_5GHZ)) {
2955 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2956 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2957 } else {
2958 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2959 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2960 }
2961
2962 if (dev->phy.rev < 2) {
2963 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2964 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2965 } else {
2966 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2967 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2968 }
2969 }
2970}
2971
e9762492
RM		 2972/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2973static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2974 struct nphy_txgains target,
2975 struct nphy_iqcal_params *params)
2976{
2977 int i, j, indx;
2978 u16 gain;
2979
2980 if (dev->phy.rev >= 3) {
2981 params->txgm = target.txgm[core];
2982 params->pga = target.pga[core];
2983 params->pad = target.pad[core];
2984 params->ipa = target.ipa[core];
2985 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2986 (params->pad << 4) | (params->ipa);
2987 for (j = 0; j < 5; j++)
2988 params->ncorr[j] = 0x79;
2989 } else {
2990 gain = (target.pad[core]) | (target.pga[core] << 4) |
2991 (target.txgm[core] << 8);
2992
2993 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2994 1 : 0;
2995 for (i = 0; i < 9; i++)
2996 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2997 break;
2998 i = min(i, 8);
2999
3000 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3001 params->pga = tbl_iqcal_gainparams[indx][i][2];
3002 params->pad = tbl_iqcal_gainparams[indx][i][3];
3003 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3004 (params->pad << 2);
3005 for (j = 0; j < 4; j++)
3006 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3007 }
3008}
3009
de7ed0c6
RM		 3010/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3011static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3012{
3013 struct b43_phy_n *nphy = dev->phy.n;
3014 int i;
3015 u16 scale, entry;
3016
3017 u16 tmp = nphy->txcal_bbmult;
3018 if (core == 0)
3019 tmp >>= 8;
3020 tmp &= 0xff;
3021
3022 for (i = 0; i < 18; i++) {
3023 scale = (ladder_lo[i].percent * tmp) / 100;
3024 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 3025 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 3026
3027 scale = (ladder_iq[i].percent * tmp) / 100;
3028 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 3029 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 3030 }
3031}
3032
45ca697e
RM		 3033/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3034static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3035{
3036 int i;
3037 for (i = 0; i < 15; i++)
3038 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3039 tbl_tx_filter_coef_rev4[2][i]);
3040}
3041
3042/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3043static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3044{
3045 int i, j;
3046 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 3047 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 3048
3049 for (i = 0; i < 3; i++)
3050 for (j = 0; j < 15; j++)
3051 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3052 tbl_tx_filter_coef_rev4[i][j]);
3053
3054 if (dev->phy.is_40mhz) {
3055 for (j = 0; j < 15; j++)
3056 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3057 tbl_tx_filter_coef_rev4[3][j]);
3058 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3059 for (j = 0; j < 15; j++)
3060 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3061 tbl_tx_filter_coef_rev4[5][j]);
3062 }
3063
3064 if (dev->phy.channel == 14)
3065 for (j = 0; j < 15; j++)
3066 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3067 tbl_tx_filter_coef_rev4[6][j]);
3068}
3069
b0022e15
RM		 3070/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3071static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3072{
3073 struct b43_phy_n *nphy = dev->phy.n;
3074
3075 u16 curr_gain[2];
3076 struct nphy_txgains target;
3077 const u32 *table = NULL;
3078
161d540c 3079 if (!nphy->txpwrctrl) {
b0022e15
RM		 3080 int i;
3081
3082 if (nphy->hang_avoid)
3083 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 3084 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 3085 if (nphy->hang_avoid)
3086 b43_nphy_stay_in_carrier_search(dev, false);
3087
3088 for (i = 0; i < 2; ++i) {
3089 if (dev->phy.rev >= 3) {
3090 target.ipa[i] = curr_gain[i] & 0x000F;
3091 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3092 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3093 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3094 } else {
3095 target.ipa[i] = curr_gain[i] & 0x0003;
3096 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3097 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3098 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3099 }
3100 }
3101 } else {
3102 int i;
3103 u16 index[2];
3104 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3105 B43_NPHY_TXPCTL_STAT_BIDX) >>
3106 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3107 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3108 B43_NPHY_TXPCTL_STAT_BIDX) >>
3109 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3110
3111 for (i = 0; i < 2; ++i) {
3112 if (dev->phy.rev >= 3) {
3113 enum ieee80211_band band =
3114 b43_current_band(dev->wl);
3115
c002831a 3116 if (b43_nphy_ipa(dev)) {
b0022e15
RM		 3117 table = b43_nphy_get_ipa_gain_table(dev);
3118 } else {
3119 if (band == IEEE80211_BAND_5GHZ) {
3120 if (dev->phy.rev == 3)
3121 table = b43_ntab_tx_gain_rev3_5ghz;
3122 else if (dev->phy.rev == 4)
3123 table = b43_ntab_tx_gain_rev4_5ghz;
3124 else
3125 table = b43_ntab_tx_gain_rev5plus_5ghz;
3126 } else {
3127 table = b43_ntab_tx_gain_rev3plus_2ghz;
3128 }
3129 }
3130
3131 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3132 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3133 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3134 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3135 } else {
3136 table = b43_ntab_tx_gain_rev0_1_2;
3137
3138 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3139 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3140 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3141 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3142 }
3143 }
3144 }
3145
3146 return target;
3147}
3148
e53de674
RM		 3149/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3150static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3151{
3152 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3153
3154 if (dev->phy.rev >= 3) {
3155 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3156 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3157 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3158 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3159 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 3160 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3161 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 3162 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3163 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3164 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3165 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3166 b43_nphy_reset_cca(dev);
3167 } else {
3168 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3169 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3170 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 3171 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3172 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 3173 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3174 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3175 }
3176}
3177
3178/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3179static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3180{
3181 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3182 u16 tmp;
3183
3184 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3185 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3186 if (dev->phy.rev >= 3) {
3187 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3188 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3189
3190 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3191 regs[2] = tmp;
3192 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3193
3194 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3195 regs[3] = tmp;
3196 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3197
3198 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 3199 b43_phy_mask(dev, B43_NPHY_BBCFG,
3200 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 3201
c643a66e 3202 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 3203 regs[5] = tmp;
d41a3552 3204 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 3205
3206 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 3207 regs[6] = tmp;
d41a3552 3208 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 3209 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3210 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3211
67cbc3ed
RM		 3212 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3213 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3214 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 3215
3216 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3217 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3218 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3219 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3220 } else {
3221 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3222 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3223 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3224 regs[2] = tmp;
3225 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 3226 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 3227 regs[3] = tmp;
3228 tmp |= 0x2000;
d41a3552 3229 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 3230 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 3231 regs[4] = tmp;
3232 tmp |= 0x2000;
d41a3552 3233 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 3234 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3235 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3236 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3237 tmp = 0x0180;
3238 else
3239 tmp = 0x0120;
3240 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3241 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3242 }
3243}
3244
bbc6dc12
RM		 3245/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3246static void b43_nphy_save_cal(struct b43_wldev *dev)
3247{
3248 struct b43_phy_n *nphy = dev->phy.n;
3249
3250 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3251 u16 *txcal_radio_regs = NULL;
902db91d 3252 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 3253 u16 *table = NULL;
3254
3255 if (nphy->hang_avoid)
3256 b43_nphy_stay_in_carrier_search(dev, 1);
3257
3258 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3259 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3260 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3261 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3262 table = nphy->cal_cache.txcal_coeffs_2G;
3263 } else {
3264 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3265 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3266 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3267 table = nphy->cal_cache.txcal_coeffs_5G;
3268 }
3269
3270 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3271 /* TODO use some definitions */
3272 if (dev->phy.rev >= 3) {
3273 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3274 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3275 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3276 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3277 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3278 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3279 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3280 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3281 } else {
3282 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3283 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3284 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3285 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3286 }
204a665b
RM		 3287 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3288 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 3289 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 3290
3291 if (nphy->hang_avoid)
3292 b43_nphy_stay_in_carrier_search(dev, 0);
3293}
3294
2f258b74
RM		 3295/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3296static void b43_nphy_restore_cal(struct b43_wldev *dev)
3297{
3298 struct b43_phy_n *nphy = dev->phy.n;
3299
3300 u16 coef[4];
3301 u16 *loft = NULL;
3302 u16 *table = NULL;
3303
3304 int i;
3305 u16 *txcal_radio_regs = NULL;
3306 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3307
3308 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3309 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 3310 return;
3311 table = nphy->cal_cache.txcal_coeffs_2G;
3312 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3313 } else {
204a665b 3314 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 3315 return;
3316 table = nphy->cal_cache.txcal_coeffs_5G;
3317 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3318 }
3319
2581b143 3320 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 3321
3322 for (i = 0; i < 4; i++) {
3323 if (dev->phy.rev >= 3)
3324 table[i] = coef[i];
3325 else
3326 coef[i] = 0;
3327 }
3328
2581b143
RM		 3329 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3331 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 3332
3333 if (dev->phy.rev < 2)
3334 b43_nphy_tx_iq_workaround(dev);
3335
3336 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3337 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3338 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3339 } else {
3340 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3341 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3342 }
3343
3344 /* TODO use some definitions */
3345 if (dev->phy.rev >= 3) {
3346 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3347 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3348 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3349 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3350 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3351 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3352 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3353 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3354 } else {
3355 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3356 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3357 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3358 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3359 }
3360 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3361}
3362
fb43b8e2
RM		 3363/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3364static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3365 struct nphy_txgains target,
3366 bool full, bool mphase)
3367{
3368 struct b43_phy_n *nphy = dev->phy.n;
3369 int i;
3370 int error = 0;
3371 int freq;
3372 bool avoid = false;
3373 u8 length;
fb23d863 3374 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 3375 const u16 *table;
3376 bool phy6or5x;
3377
3378 u16 buffer[11];
3379 u16 diq_start = 0;
3380 u16 save[2];
3381 u16 gain[2];
3382 struct nphy_iqcal_params params[2];
3383 bool updated[2] = { };
3384
3385 b43_nphy_stay_in_carrier_search(dev, true);
3386
3387 if (dev->phy.rev >= 4) {
3388 avoid = nphy->hang_avoid;
3389 nphy->hang_avoid = 0;
3390 }
3391
9145834e 3392 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3393
3394 for (i = 0; i < 2; i++) {
3395 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3396 gain[i] = params[i].cal_gain;
3397 }
2581b143
RM		 3398
3399 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 3400
3401 b43_nphy_tx_cal_radio_setup(dev);
e53de674 3402 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 3403
3404 phy6or5x = dev->phy.rev >= 6 ||
3405 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3406 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3407 if (phy6or5x) {
38bb9029
RM		 3408 if (dev->phy.is_40mhz) {
3409 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3410 tbl_tx_iqlo_cal_loft_ladder_40);
3411 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3412 tbl_tx_iqlo_cal_iqimb_ladder_40);
3413 } else {
3414 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3415 tbl_tx_iqlo_cal_loft_ladder_20);
3416 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3417 tbl_tx_iqlo_cal_iqimb_ladder_20);
3418 }
fb43b8e2
RM		 3419 }
3420
3421 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3422
aa4c7b2a 3423 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 3424 freq = 2500;
3425 else
3426 freq = 5000;
3427
3428 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 3429 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3430 0xFFFF, 0, true, false);
fb43b8e2 3431 else
59af099b 3432 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 3433
3434 if (error == 0) {
3435 if (nphy->mphase_cal_phase_id > 2) {
3436 table = nphy->mphase_txcal_bestcoeffs;
3437 length = 11;
3438 if (dev->phy.rev < 3)
3439 length -= 2;
3440 } else {
3441 if (!full && nphy->txiqlocal_coeffsvalid) {
3442 table = nphy->txiqlocal_bestc;
3443 length = 11;
3444 if (dev->phy.rev < 3)
3445 length -= 2;
3446 } else {
3447 full = true;
3448 if (dev->phy.rev >= 3) {
3449 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3450 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3451 } else {
3452 table = tbl_tx_iqlo_cal_startcoefs;
3453 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3454 }
3455 }
3456 }
3457
2581b143 3458 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 3459
3460 if (full) {
3461 if (dev->phy.rev >= 3)
3462 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3463 else
3464 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3465 } else {
3466 if (dev->phy.rev >= 3)
3467 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3468 else
3469 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3470 }
3471
3472 if (mphase) {
3473 count = nphy->mphase_txcal_cmdidx;
3474 numb = min(max,
3475 (u16)(count + nphy->mphase_txcal_numcmds));
3476 } else {
3477 count = 0;
3478 numb = max;
3479 }
3480
3481 for (; count < numb; count++) {
3482 if (full) {
3483 if (dev->phy.rev >= 3)
3484 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3485 else
3486 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3487 } else {
3488 if (dev->phy.rev >= 3)
3489 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3490 else
3491 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3492 }
3493
3494 core = (cmd & 0x3000) >> 12;
3495 type = (cmd & 0x0F00) >> 8;
3496
3497 if (phy6or5x && updated[core] == 0) {
3498 b43_nphy_update_tx_cal_ladder(dev, core);
3499 updated[core] = 1;
3500 }
3501
3502 tmp = (params[core].ncorr[type] << 8) | 0x66;
3503 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3504
3505 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 3506 buffer[0] = b43_ntab_read(dev,
3507 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 3508 diq_start = buffer[0];
3509 buffer[0] = 0;
d41a3552
RM		 3510 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3511 0);
fb43b8e2
RM		 3512 }
3513
3514 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3515 for (i = 0; i < 2000; i++) {
3516 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3517 if (tmp & 0xC000)
3518 break;
3519 udelay(10);
3520 }
3521
9145834e
RM		 3522 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3523 buffer);
2581b143
RM		 3524 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3525 buffer);
fb43b8e2
RM		 3526
3527 if (type == 1 || type == 3 || type == 4)
3528 buffer[0] = diq_start;
3529 }
3530
3531 if (mphase)
3532 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3533
3534 last = (dev->phy.rev < 3) ? 6 : 7;
3535
3536 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 3537 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 3538 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 3539 if (dev->phy.rev < 3) {
3540 buffer[0] = 0;
3541 buffer[1] = 0;
3542 buffer[2] = 0;
3543 buffer[3] = 0;
3544 }
2581b143
RM		 3545 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3546 buffer);
bc53e512 3547 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 3548 buffer);
3549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3550 buffer);
3551 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3552 buffer);
fb43b8e2
RM		 3553 length = 11;
3554 if (dev->phy.rev < 3)
3555 length -= 2;
9145834e
RM		 3556 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3557 nphy->txiqlocal_bestc);
fb43b8e2 3558 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 3559 nphy->txiqlocal_chanspec.center_freq =
3560 dev->phy.channel_freq;
3561 nphy->txiqlocal_chanspec.channel_type =
3562 dev->phy.channel_type;
fb43b8e2
RM		 3563 } else {
3564 length = 11;
3565 if (dev->phy.rev < 3)
3566 length -= 2;
9145834e
RM		 3567 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3568 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 3569 }
3570
53ae8e8c 3571 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 3572 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3573 }
3574
e53de674 3575 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 3576 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3577
3578 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3579 b43_nphy_tx_iq_workaround(dev);
3580
3581 if (dev->phy.rev >= 4)
3582 nphy->hang_avoid = avoid;
3583
3584 b43_nphy_stay_in_carrier_search(dev, false);
3585
3586 return error;
3587}
3588
984ff4ff
RM		 3589/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3590static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3591{
3592 struct b43_phy_n *nphy = dev->phy.n;
3593 u8 i;
3594 u16 buffer[7];
3595 bool equal = true;
3596
902db91d 3597 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 3598 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3599 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 3600 return;
3601
3602 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3603 for (i = 0; i < 4; i++) {
3604 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3605 equal = false;
3606 break;
3607 }
3608 }
3609
3610 if (!equal) {
3611 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3612 nphy->txiqlocal_bestc);
3613 for (i = 0; i < 4; i++)
3614 buffer[i] = 0;
3615 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3616 buffer);
3617 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3618 &nphy->txiqlocal_bestc[5]);
3619 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3620 &nphy->txiqlocal_bestc[5]);
3621 }
3622}
3623
15931e31
RM		 3624/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3625static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3626 struct nphy_txgains target, u8 type, bool debug)
3627{
3628 struct b43_phy_n *nphy = dev->phy.n;
3629 int i, j, index;
3630 u8 rfctl[2];
3631 u8 afectl_core;
3632 u16 tmp[6];
c7455cf9 3633 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 3634 u32 real, imag;
3635 enum ieee80211_band band;
3636
3637 u8 use;
3638 u16 cur_hpf;
3639 u16 lna[3] = { 3, 3, 1 };
3640 u16 hpf1[3] = { 7, 2, 0 };
3641 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 3642 u32 power[3] = { };
15931e31
RM		 3643 u16 gain_save[2];
3644 u16 cal_gain[2];
3645 struct nphy_iqcal_params cal_params[2];
3646 struct nphy_iq_est est;
3647 int ret = 0;
3648 bool playtone = true;
3649 int desired = 13;
3650
3651 b43_nphy_stay_in_carrier_search(dev, 1);
3652
3653 if (dev->phy.rev < 2)
984ff4ff 3654 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 3655 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3656 for (i = 0; i < 2; i++) {
3657 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3658 cal_gain[i] = cal_params[i].cal_gain;
3659 }
2581b143 3660 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 3661
3662 for (i = 0; i < 2; i++) {
3663 if (i == 0) {
3664 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3665 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3666 afectl_core = B43_NPHY_AFECTL_C1;
3667 } else {
3668 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3669 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3670 afectl_core = B43_NPHY_AFECTL_C2;
3671 }
3672
3673 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3674 tmp[2] = b43_phy_read(dev, afectl_core);
3675 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3676 tmp[4] = b43_phy_read(dev, rfctl[0]);
3677 tmp[5] = b43_phy_read(dev, rfctl[1]);
3678
3679 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 3680 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 3681 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3682 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3683 (1 - i));
3684 b43_phy_set(dev, afectl_core, 0x0006);
3685 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3686
3687 band = b43_current_band(dev->wl);
3688
3689 if (nphy->rxcalparams & 0xFF000000) {
3690 if (band == IEEE80211_BAND_5GHZ)
3691 b43_phy_write(dev, rfctl[0], 0x140);
3692 else
3693 b43_phy_write(dev, rfctl[0], 0x110);
3694 } else {
3695 if (band == IEEE80211_BAND_5GHZ)
3696 b43_phy_write(dev, rfctl[0], 0x180);
3697 else
3698 b43_phy_write(dev, rfctl[0], 0x120);
3699 }
3700
3701 if (band == IEEE80211_BAND_5GHZ)
3702 b43_phy_write(dev, rfctl[1], 0x148);
3703 else
3704 b43_phy_write(dev, rfctl[1], 0x114);
3705
3706 if (nphy->rxcalparams & 0x10000) {
3707 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3708 (i + 1));
3709 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3710 (2 - i));
3711 }
3712
30115c22 3713 for (j = 0; j < 4; j++) {
15931e31
RM		 3714 if (j < 3) {
3715 cur_lna = lna[j];
3716 cur_hpf1 = hpf1[j];
3717 cur_hpf2 = hpf2[j];
3718 } else {
3719 if (power[1] > 10000) {
3720 use = 1;
3721 cur_hpf = cur_hpf1;
3722 index = 2;
3723 } else {
3724 if (power[0] > 10000) {
3725 use = 1;
3726 cur_hpf = cur_hpf1;
3727 index = 1;
3728 } else {
3729 index = 0;
3730 use = 2;
3731 cur_hpf = cur_hpf2;
3732 }
3733 }
3734 cur_lna = lna[index];
3735 cur_hpf1 = hpf1[index];
3736 cur_hpf2 = hpf2[index];
3737 cur_hpf += desired - hweight32(power[index]);
3738 cur_hpf = clamp_val(cur_hpf, 0, 10);
3739 if (use == 1)
3740 cur_hpf1 = cur_hpf;
3741 else
3742 cur_hpf2 = cur_hpf;
3743 }
3744
3745 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3746 (cur_lna << 2));
75377b24
RM		 3747 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3748 false);
de9a47f9 3749 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3750 b43_nphy_stop_playback(dev);
15931e31
RM		 3751
3752 if (playtone) {
59af099b
RM		 3753 ret = b43_nphy_tx_tone(dev, 4000,
3754 (nphy->rxcalparams & 0xFFFF),
3755 false, false);
15931e31
RM		 3756 playtone = false;
3757 } else {
10a79873
RM		 3758 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3759 false, false);
15931e31
RM		 3760 }
3761
3762 if (ret == 0) {
3763 if (j < 3) {
3764 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3765 false);
3766 if (i == 0) {
3767 real = est.i0_pwr;
3768 imag = est.q0_pwr;
3769 } else {
3770 real = est.i1_pwr;
3771 imag = est.q1_pwr;
3772 }
3773 power[i] = ((real + imag) / 1024) + 1;
3774 } else {
3775 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3776 }
53ae8e8c 3777 b43_nphy_stop_playback(dev);
15931e31
RM		 3778 }
3779
3780 if (ret != 0)
3781 break;
3782 }
3783
3784 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3785 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3786 b43_phy_write(dev, rfctl[1], tmp[5]);
3787 b43_phy_write(dev, rfctl[0], tmp[4]);
3788 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3789 b43_phy_write(dev, afectl_core, tmp[2]);
3790 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3791
3792 if (ret != 0)
3793 break;
3794 }
3795
75377b24 3796 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3797 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3798 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3799
3800 b43_nphy_stay_in_carrier_search(dev, 0);
3801
3802 return ret;
3803}
3804
3805static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3806 struct nphy_txgains target, u8 type, bool debug)
3807{
3808 return -1;
3809}
3810
3811/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3812static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3813 struct nphy_txgains target, u8 type, bool debug)
3814{
3815 if (dev->phy.rev >= 3)
3816 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3817 else
3818 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3819}
3820
4e687b22
GS		 3821/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3822static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3823{
3824 struct b43_phy *phy = &dev->phy;
3825 struct b43_phy_n *nphy = phy->n;
0b81c23d 3826 /* u16 buf[16]; it's rev3+ */
4e687b22 3827
049fbfee
RM		 3828 nphy->phyrxchain = mask;
3829
4e687b22
GS		 3830 if (0 /* FIXME clk */)
3831 return;
3832
3833 b43_mac_suspend(dev);
3834
3835 if (nphy->hang_avoid)
3836 b43_nphy_stay_in_carrier_search(dev, true);
3837
3838 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3839 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3840
049fbfee 3841 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 3842 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3843 if (dev->phy.rev >= 3) {
3844 /* TODO */
3845 }
3846 } else {
3847 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3848 if (dev->phy.rev >= 3) {
3849 /* TODO */
3850 }
3851 }
3852
3853 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3854
3855 if (nphy->hang_avoid)
3856 b43_nphy_stay_in_carrier_search(dev, false);
3857
3858 b43_mac_enable(dev);
3859}
3860
0988a7a1
RM		 3861/*
3862 * Init N-PHY
3863 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3864 */
424047e6
MB		 3865int b43_phy_initn(struct b43_wldev *dev)
3866{
0581483a 3867 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 3868 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3869 struct b43_phy_n *nphy = phy->n;
3870 u8 tx_pwr_state;
3871 struct nphy_txgains target;
95b66bad 3872 u16 tmp;
0988a7a1
RM		 3873 enum ieee80211_band tmp2;
3874 bool do_rssi_cal;
3875
3876 u16 clip[2];
3877 bool do_cal = false;
95b66bad 3878
0988a7a1 3879 if ((dev->phy.rev >= 3) &&
0581483a 3880 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 3881 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 3882 switch (dev->dev->bus_type) {
42c9a458
RM		 3883#ifdef CONFIG_B43_BCMA
3884 case B43_BUS_BCMA:
3885 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3886 BCMA_CC_CHIPCTL, 0x40);
3887 break;
3888#endif
6cbab0d9
RM		 3889#ifdef CONFIG_B43_SSB
3890 case B43_BUS_SSB:
3891 chipco_set32(&dev->dev->sdev->bus->chipco,
3892 SSB_CHIPCO_CHIPCTL, 0x40);
3893 break;
3894#endif
3895 }
0988a7a1
RM		 3896 }
3897 nphy->deaf_count = 0;
95b66bad 3898 b43_nphy_tables_init(dev);
0988a7a1
RM		 3899 nphy->crsminpwr_adjusted = false;
3900 nphy->noisevars_adjusted = false;
95b66bad
MB		 3901
3902 /* Clear all overrides */
0988a7a1
RM		 3903 if (dev->phy.rev >= 3) {
3904 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3905 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3906 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3907 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3908 } else {
3909 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3910 }
95b66bad
MB		 3911 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3912 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3913 if (dev->phy.rev < 6) {
3914 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3915 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3916 }
95b66bad
MB		 3917 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3918 ~(B43_NPHY_RFSEQMODE_CAOVER |
3919 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3920 if (dev->phy.rev >= 3)
3921 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3922 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3923
0988a7a1
RM		 3924 if (dev->phy.rev <= 2) {
3925 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3926 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3927 ~B43_NPHY_BPHY_CTL3_SCALE,
3928 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3929 }
95b66bad
MB		 3930 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3931 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3932
0eff8fcd 3933 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f
RM		 3934 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3935 dev->dev->board_type == 0x8B))
0988a7a1
RM		 3936 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3937 else
3938 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3939 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3940 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3941 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3942
ad9716e8 3943 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3944 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3945
3946 if (phy->rev < 2) {
3947 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3948 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3949 }
0988a7a1
RM		 3950
3951 tmp2 = b43_current_band(dev->wl);
c002831a 3952 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 3953 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3954 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3955 nphy->papd_epsilon_offset[0] << 7);
3956 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3957 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3958 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3959 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3960 } else if (phy->rev >= 5) {
45ca697e 3961 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3962 }
3963
95b66bad 3964 b43_nphy_workarounds(dev);
95b66bad 3965
0988a7a1 3966 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 3967 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 3968 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3969 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3970 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 3971 b43_phy_force_clock(dev, 0);
0988a7a1 3972
858a1652 3973 b43_mac_phy_clock_set(dev, true);
0988a7a1 3974
e50cbcf6 3975 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3976 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3977 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3978 b43_nphy_pa_override(dev, true);
0988a7a1 3979
bbec398c
RM		 3980 b43_nphy_classifier(dev, 0, 0);
3981 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 3982 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3983 b43_nphy_bphy_init(dev);
3984
0988a7a1 3985 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 3986 b43_nphy_tx_power_ctrl(dev, false);
3987 b43_nphy_tx_power_fix(dev);
0988a7a1
RM		 3988 /* TODO N PHY TX Power Control Idle TSSI */
3989 /* TODO N PHY TX Power Control Setup */
0eff8fcd 3990 b43_nphy_tx_gain_table_upload(dev);
95b66bad 3991
0988a7a1 3992 if (nphy->phyrxchain != 3)
4e687b22 3993 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 3994 if (nphy->mphase_cal_phase_id > 0)
3995 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3996
3997 do_rssi_cal = false;
3998 if (phy->rev >= 3) {
3999 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 4000 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 4001 else
204a665b 4002 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 4003
4004 if (do_rssi_cal)
4cb99775 4005 b43_nphy_rssi_cal(dev);
0988a7a1 4006 else
42e1547e 4007 b43_nphy_restore_rssi_cal(dev);
0988a7a1 4008 } else {
4cb99775 4009 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 4010 }
4011
4012 if (!((nphy->measure_hold & 0x6) != 0)) {
4013 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 4014 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 4015 else
204a665b 4016 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 4017
4018 if (nphy->mute)
4019 do_cal = false;
4020
4021 if (do_cal) {
b0022e15 4022 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 4023
4024 if (nphy->antsel_type == 2)
8987a9e9 4025 b43_nphy_superswitch_init(dev, true);
0988a7a1 4026 if (nphy->perical != 2) {
90b9738d 4027 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 4028 if (phy->rev >= 3) {
4029 nphy->cal_orig_pwr_idx[0] =
4030 nphy->txpwrindex[0].index_internal;
4031 nphy->cal_orig_pwr_idx[1] =
4032 nphy->txpwrindex[1].index_internal;
4033 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 4034 target = b43_nphy_get_tx_gains(dev);
0988a7a1 4035 }
e7797bf2
RM		 4036 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4037 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4038 b43_nphy_save_cal(dev);
4039 } else if (nphy->mphase_cal_phase_id == 0)
4040 ;/* N PHY Periodic Calibration with arg 3 */
4041 } else {
4042 b43_nphy_restore_cal(dev);
0988a7a1
RM		 4043 }
4044 }
4045
6dcd9d91 4046 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 4047 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 4048 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4049 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4050 if (phy->rev >= 3 && phy->rev <= 6)
4051 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 4052 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 4053 if (phy->rev >= 3)
4054 b43_nphy_spur_workaround(dev);
95b66bad 4055
53a6e234 4056 return 0;
424047e6 4057}
ef1a628d 4058
49d55cef
RM		 4059/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4060static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4061{
9b682c78
JL		 4062 struct bcma_drv_cc __maybe_unused *cc;
4063 u32 __maybe_unused pmu_ctl;
d66be829
RM		 4064
4065 switch (dev->dev->bus_type) {
4066#ifdef CONFIG_B43_BCMA
4067 case B43_BUS_BCMA:
4068 cc = &dev->dev->bdev->bus->drv_cc;
4069 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4070 if (avoid) {
4071 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4072 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4073 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4074 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4075 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4076 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4077 } else {
4078 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4079 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4080 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4081 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4082 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4083 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4084 }
4085 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4086 } else if (dev->dev->chip_id == 0x4716) {
4087 if (avoid) {
4088 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4089 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4090 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4091 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4092 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4093 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4094 } else {
4095 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4096 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4097 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4098 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4099 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4100 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4101 }
4102 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4103 BCMA_CC_PMU_CTL_NOILPONW;
4104 } else if (dev->dev->chip_id == 0x4322 ||
4105 dev->dev->chip_id == 0x4340 ||
4106 dev->dev->chip_id == 0x4341) {
4107 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4108 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4109 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4110 if (avoid)
4111 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4112 else
4113 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4114 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
49d55cef 4115 } else {
d66be829 4116 return;
49d55cef 4117 }
d66be829
RM		 4118 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4119 break;
8b1fdb53 4120#endif
d66be829
RM		 4121#ifdef CONFIG_B43_SSB
4122 case B43_BUS_SSB:
4123 /* FIXME */
4124 break;
4125#endif
4126 }
49d55cef
RM		 4127}
4128
1b69ec7b 4129/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 4130static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 4131 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 4132 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 4133{
4134 struct b43_phy *phy = &dev->phy;
4135 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 4136 int ch = new_channel->hw_value;
1b69ec7b 4137
087de74a 4138 u16 old_band_5ghz;
1b69ec7b
RM		 4139 u32 tmp32;
4140
087de74a
RM		 4141 old_band_5ghz =
4142 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4143 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 4144 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4145 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4146 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4147 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4148 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 4149 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 4150 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4151 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4152 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 4153 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 4154 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4155 }
4156
4157 b43_chantab_phy_upload(dev, e);
4158
a656b6a9 4159 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 4160 b43_nphy_classifier(dev, 2, 0);
4161 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4162 } else {
4163 b43_nphy_classifier(dev, 2, 2);
a656b6a9 4164 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 4165 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4166 }
4167
161d540c 4168 if (!nphy->txpwrctrl)
1b69ec7b
RM		 4169 b43_nphy_tx_power_fix(dev);
4170
4171 if (dev->phy.rev < 3)
4172 b43_nphy_adjust_lna_gain_table(dev);
4173
4174 b43_nphy_tx_lp_fbw(dev);
4175
49d55cef
RM		 4176 if (dev->phy.rev >= 3 &&
4177 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4178 bool avoid = false;
4179 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4180 avoid = true;
4181 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4182 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4183 avoid = true;
4184 } else { /* 40MHz */
4185 if (nphy->aband_spurwar_en &&
4186 (ch == 38 || ch == 102 || ch == 118))
4187 avoid = dev->dev->chip_id == 0x4716;
4188 }
4189
4190 b43_nphy_pmu_spur_avoid(dev, avoid);
4191
4192 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4193 dev->dev->chip_id == 43225) {
4194 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4195 avoid ? 0x5341 : 0x8889);
4196 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4197 }
4198
4199 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4200 ; /* TODO: reset PLL */
4201
4202 if (avoid)
4203 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4204 else
4205 b43_phy_mask(dev, B43_NPHY_BBCFG,
4206 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4207
4208 b43_nphy_reset_cca(dev);
4209
4210 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 4211 }
4212
4213 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4214
4215 if (phy->rev >= 3)
4216 b43_nphy_spur_workaround(dev);
4217}
4218
eff66c51 4219/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 4220static int b43_nphy_set_channel(struct b43_wldev *dev,
4221 struct ieee80211_channel *channel,
4222 enum nl80211_channel_type channel_type)
eff66c51 4223{
a656b6a9 4224 struct b43_phy *phy = &dev->phy;
eff66c51 4225
2eeb6fd0
JL		 4226 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4227 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 4228
4229 u8 tmp;
eff66c51
RM		 4230
4231 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 4232 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4233 channel->center_freq);
f19ebe7d
RM		 4234 if (!tabent_r3)
4235 return -ESRCH;
ffd2d9bd 4236 } else {
a656b6a9
RM		 4237 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4238 channel->hw_value);
f19ebe7d 4239 if (!tabent_r2)
ffd2d9bd 4240 return -ESRCH;
eff66c51
RM		 4241 }
4242
204a665b
RM		 4243 /* Channel is set later in common code, but we need to set it on our
4244 own to let this function's subcalls work properly. */
4245 phy->channel = channel->hw_value;
4246 phy->channel_freq = channel->center_freq;
eff66c51 4247
e5c407f9
RM		 4248 if (b43_channel_type_is_40mhz(phy->channel_type) !=
4249 b43_channel_type_is_40mhz(channel_type))
4250 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 4251
a656b6a9
RM		 4252 if (channel_type == NL80211_CHAN_HT40PLUS)
4253 b43_phy_set(dev, B43_NPHY_RXCTL,
4254 B43_NPHY_RXCTL_BSELU20);
4255 else if (channel_type == NL80211_CHAN_HT40MINUS)
4256 b43_phy_mask(dev, B43_NPHY_RXCTL,
4257 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 4258
4259 if (dev->phy.rev >= 3) {
a656b6a9 4260 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 4261 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 4262 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 4263 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 4264 } else {
a656b6a9 4265 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 4266 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 4267 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 4268 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 4269 }
4270
4271 return 0;
4272}
4273
ef1a628d
MB		 4274static int b43_nphy_op_allocate(struct b43_wldev *dev)
4275{
4276 struct b43_phy_n *nphy;
4277
4278 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4279 if (!nphy)
4280 return -ENOMEM;
4281 dev->phy.n = nphy;
4282
ef1a628d
MB		 4283 return 0;
4284}
4285
fb11137a 4286static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 4287{
fb11137a
MB		 4288 struct b43_phy *phy = &dev->phy;
4289 struct b43_phy_n *nphy = phy->n;
c7d64310 4290 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 4291
fb11137a 4292 memset(nphy, 0, sizeof(*nphy));
ef1a628d 4293
aca434d3 4294 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 4295 nphy->spur_avoid = (phy->rev >= 3) ?
4296 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 4297 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4298 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4299 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 4300 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 4301 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4302 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4303 nphy->tx_pwr_idx[0] = 128;
4304 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 4305
4306 /* Hardware TX power control and 5GHz power gain */
4307 nphy->txpwrctrl = false;
4308 nphy->pwg_gain_5ghz = false;
4309 if (dev->phy.rev >= 3 ||
4310 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4311 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4312 nphy->txpwrctrl = true;
4313 nphy->pwg_gain_5ghz = true;
4314 } else if (sprom->revision >= 4) {
4315 if (dev->phy.rev >= 2 &&
4316 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4317 nphy->txpwrctrl = true;
4318#ifdef CONFIG_B43_SSB
4319 if (dev->dev->bus_type == B43_BUS_SSB &&
4320 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4321 struct pci_dev *pdev =
4322 dev->dev->sdev->bus->host_pci;
4323 if (pdev->device == 0x4328 ||
4324 pdev->device == 0x432a)
4325 nphy->pwg_gain_5ghz = true;
4326 }
4327#endif
4328 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4329 nphy->pwg_gain_5ghz = true;
4330 }
4331 }
4332
4333 if (dev->phy.rev >= 3) {
4334 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4335 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4336 }
ef1a628d
MB		 4337}
4338
fb11137a 4339static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 4340{
fb11137a
MB		 4341 struct b43_phy *phy = &dev->phy;
4342 struct b43_phy_n *nphy = phy->n;
ef1a628d 4343
ef1a628d 4344 kfree(nphy);
fb11137a
MB		 4345 phy->n = NULL;
4346}
4347
4348static int b43_nphy_op_init(struct b43_wldev *dev)
4349{
4350 return b43_phy_initn(dev);
ef1a628d
MB		 4351}
4352
4353static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4354{
4355#if B43_DEBUG
4356 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4357 /* OFDM registers are onnly available on A/G-PHYs */
4358 b43err(dev->wl, "Invalid OFDM PHY access at "
4359 "0x%04X on N-PHY\n", offset);
4360 dump_stack();
4361 }
4362 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4363 /* Ext-G registers are only available on G-PHYs */
4364 b43err(dev->wl, "Invalid EXT-G PHY access at "
4365 "0x%04X on N-PHY\n", offset);
4366 dump_stack();
4367 }
4368#endif /* B43_DEBUG */
4369}
4370
4371static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4372{
4373 check_phyreg(dev, reg);
4374 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4375 return b43_read16(dev, B43_MMIO_PHY_DATA);
4376}
4377
4378static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4379{
4380 check_phyreg(dev, reg);
4381 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4382 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4383}
4384
755fd183
RM		 4385static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4386 u16 set)
4387{
4388 check_phyreg(dev, reg);
4389 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4390 b43_write16(dev, B43_MMIO_PHY_DATA,
4391 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4392}
4393
ef1a628d
MB		 4394static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4395{
4396 /* Register 1 is a 32-bit register. */
4397 B43_WARN_ON(reg == 1);
4398 /* N-PHY needs 0x100 for read access */
4399 reg |= 0x100;
4400
4401 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4402 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4403}
4404
4405static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4406{
4407 /* Register 1 is a 32-bit register. */
4408 B43_WARN_ON(reg == 1);
4409
4410 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4411 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4412}
4413
c2b7aefd 4414/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 4415static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 4416 bool blocked)
c2b7aefd
RM		 4417{
4418 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4419 b43err(dev->wl, "MAC not suspended\n");
4420
4421 if (blocked) {
4422 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4423 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4424 if (dev->phy.rev >= 3) {
4425 b43_radio_mask(dev, 0x09, ~0x2);
4426
4427 b43_radio_write(dev, 0x204D, 0);
4428 b43_radio_write(dev, 0x2053, 0);
4429 b43_radio_write(dev, 0x2058, 0);
4430 b43_radio_write(dev, 0x205E, 0);
4431 b43_radio_mask(dev, 0x2062, ~0xF0);
4432 b43_radio_write(dev, 0x2064, 0);
4433
4434 b43_radio_write(dev, 0x304D, 0);
4435 b43_radio_write(dev, 0x3053, 0);
4436 b43_radio_write(dev, 0x3058, 0);
4437 b43_radio_write(dev, 0x305E, 0);
4438 b43_radio_mask(dev, 0x3062, ~0xF0);
4439 b43_radio_write(dev, 0x3064, 0);
4440 }
4441 } else {
4442 if (dev->phy.rev >= 3) {
d817f4e1 4443 b43_radio_init2056(dev);
78159788 4444 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 4445 } else {
4446 b43_radio_init2055(dev);
4447 }
4448 }
ef1a628d
MB		 4449}
4450
0f4091b9 4451/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 4452static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4453{
2a870831
RM		 4454 u16 override = on ? 0x0 : 0x7FFF;
4455 u16 core = on ? 0xD : 0x00FD;
0f4091b9 4456
2a870831
RM		 4457 if (dev->phy.rev >= 3) {
4458 if (on) {
4459 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4460 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4461 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4462 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4463 } else {
4464 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4465 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4466 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4467 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4468 }
4469 } else {
4470 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4471 }
cb24f57f
MB		 4472}
4473
ef1a628d
MB		 4474static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4475 unsigned int new_channel)
4476{
a656b6a9
RM		 4477 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4478 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 4479
ef1a628d
MB		 4480 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4481 if ((new_channel < 1) || (new_channel > 14))
4482 return -EINVAL;
4483 } else {
4484 if (new_channel > 200)
4485 return -EINVAL;
4486 }
4487
a656b6a9 4488 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 4489}
4490
4491static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4492{
4493 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4494 return 1;
4495 return 36;
4496}
4497
ef1a628d
MB		 4498const struct b43_phy_operations b43_phyops_n = {
4499 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 4500 .free = b43_nphy_op_free,
4501 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 4502 .init = b43_nphy_op_init,
ef1a628d
MB		 4503 .phy_read = b43_nphy_op_read,
4504 .phy_write = b43_nphy_op_write,
755fd183 4505 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 4506 .radio_read = b43_nphy_op_radio_read,
4507 .radio_write = b43_nphy_op_radio_write,
4508 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 4509 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 4510 .switch_channel = b43_nphy_op_switch_channel,
4511 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 4512 .recalc_txpower = b43_nphy_op_recalc_txpower,
4513 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 4514};
Linux kernel - Deliverables
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