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b43: N-PHY: add init tables for 2056 radio
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b 25#include <linux/delay.h>
5a0e3ad6 26#include <linux/slab.h>
819d772b
JL		 27#include <linux/types.h>
28
424047e6 29#include "b43.h"
3d0da751 30#include "phy_n.h"
53a6e234 31#include "tables_nphy.h"
6db507ff 32#include "radio_2055.h"
5161bec5 33#include "radio_2056.h"
bbec398c 34#include "main.h"
424047e6 35
f8187b5b
RM		 36struct nphy_txgains {
37 u16 txgm[2];
38 u16 pga[2];
39 u16 pad[2];
40 u16 ipa[2];
41};
42
43struct nphy_iqcal_params {
44 u16 txgm;
45 u16 pga;
46 u16 pad;
47 u16 ipa;
48 u16 cal_gain;
49 u16 ncorr[5];
50};
51
52struct nphy_iq_est {
53 s32 iq0_prod;
54 u32 i0_pwr;
55 u32 q0_pwr;
56 s32 iq1_prod;
57 u32 i1_pwr;
58 u32 q1_pwr;
59};
424047e6 60
67c0d6e2
RM		 61enum b43_nphy_rf_sequence {
62 B43_RFSEQ_RX2TX,
63 B43_RFSEQ_TX2RX,
64 B43_RFSEQ_RESET2RX,
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
68};
69
76b002bd
RM		 70enum b43_nphy_rssi_type {
71 B43_NPHY_RSSI_X = 0,
72 B43_NPHY_RSSI_Y,
73 B43_NPHY_RSSI_Z,
74 B43_NPHY_RSSI_PWRDET,
75 B43_NPHY_RSSI_TSSI_I,
76 B43_NPHY_RSSI_TSSI_Q,
77 B43_NPHY_RSSI_TBD,
78};
79
161d540c
RM		 80static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
81 bool enable);
9501fefe
RM		 82static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83 u8 *events, u8 *delays, u8 length);
67c0d6e2
RM		 84static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85 enum b43_nphy_rf_sequence seq);
67cbc3ed
RM		 86static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87 u16 value, u8 core, bool off);
88static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
89 u16 value, u8 core);
67c0d6e2 90
53a6e234
MB		 91void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
92{//TODO
93}
94
18c8adeb 95static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 96{//TODO
97}
98
18c8adeb
MB		 99static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
100 bool ignore_tssi)
101{//TODO
102 return B43_TXPWR_RES_DONE;
103}
104
d1591314 105static void b43_chantab_radio_upload(struct b43_wldev *dev,
f19ebe7d 106 const struct b43_nphy_channeltab_entry_rev2 *e)
d1591314 107{
e5255ccc
RM		 108 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
113
114 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
119
120 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
125
126 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
131
132 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
137
138 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
d1591314
MB		 140}
141
142static void b43_chantab_phy_upload(struct b43_wldev *dev,
b15b3039 143 const struct b43_phy_n_sfo_cfg *e)
d1591314
MB		 144{
145 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
146 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
147 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
148 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
149 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
150 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
151}
152
161d540c
RM		 153/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
154static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
155{
156 struct b43_phy_n *nphy = dev->phy.n;
157 u8 i;
158 u16 tmp;
159
160 if (nphy->hang_avoid)
161 b43_nphy_stay_in_carrier_search(dev, 1);
162
163 nphy->txpwrctrl = enable;
164 if (!enable) {
165 if (dev->phy.rev >= 3)
166 ; /* TODO */
167
168 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
169 for (i = 0; i < 84; i++)
170 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
171
172 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
173 for (i = 0; i < 84; i++)
174 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
175
176 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
177 if (dev->phy.rev >= 3)
178 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
179 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
180
181 if (dev->phy.rev >= 3) {
182 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
183 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
184 } else {
185 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
186 }
187
188 if (dev->phy.rev == 2)
189 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
190 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
191 else if (dev->phy.rev < 2)
192 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
193 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
194
195 if (dev->phy.rev < 2 && 0)
196 ; /* TODO */
197 } else {
198 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
199 }
200
201 if (nphy->hang_avoid)
202 b43_nphy_stay_in_carrier_search(dev, 0);
203}
204
205/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314
MB		 206static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
207{
161d540c
RM		 208 struct b43_phy_n *nphy = dev->phy.n;
209 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
210
211 u8 txpi[2], bbmult, i;
212 u16 tmp, radio_gain, dac_gain;
213 u16 freq = dev->phy.channel_freq;
214 u32 txgain;
215 /* u32 gaintbl; rev3+ */
216
217 if (nphy->hang_avoid)
218 b43_nphy_stay_in_carrier_search(dev, 1);
219
220 if (dev->phy.rev >= 3) {
221 txpi[0] = 40;
222 txpi[1] = 40;
223 } else if (sprom->revision < 4) {
224 txpi[0] = 72;
225 txpi[1] = 72;
226 } else {
227 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
228 txpi[0] = sprom->txpid2g[0];
229 txpi[1] = sprom->txpid2g[1];
230 } else if (freq >= 4900 && freq < 5100) {
231 txpi[0] = sprom->txpid5gl[0];
232 txpi[1] = sprom->txpid5gl[1];
233 } else if (freq >= 5100 && freq < 5500) {
234 txpi[0] = sprom->txpid5g[0];
235 txpi[1] = sprom->txpid5g[1];
236 } else if (freq >= 5500) {
237 txpi[0] = sprom->txpid5gh[0];
238 txpi[1] = sprom->txpid5gh[1];
239 } else {
240 txpi[0] = 91;
241 txpi[1] = 91;
242 }
243 }
244
245 /*
246 for (i = 0; i < 2; i++) {
247 nphy->txpwrindex[i].index_internal = txpi[i];
248 nphy->txpwrindex[i].index_internal_save = txpi[i];
249 }
250 */
251
252 for (i = 0; i < 2; i++) {
253 if (dev->phy.rev >= 3) {
c7455cf9
RM		 254 /* FIXME: support 5GHz */
255 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
161d540c
RM		 256 radio_gain = (txgain >> 16) & 0x1FFFF;
257 } else {
258 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
259 radio_gain = (txgain >> 16) & 0x1FFF;
260 }
261
262 dac_gain = (txgain >> 8) & 0x3F;
263 bbmult = txgain & 0xFF;
264
265 if (dev->phy.rev >= 3) {
266 if (i == 0)
267 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
268 else
269 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
270 } else {
271 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
272 }
273
274 if (i == 0)
275 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
276 else
277 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
278
279 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
280 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
281
282 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
283 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
284
285 if (i == 0)
286 tmp = (tmp & 0x00FF) | (bbmult << 8);
287 else
288 tmp = (tmp & 0xFF00) | bbmult;
289
290 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
291 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
292
293 if (0)
294 ; /* TODO */
295 }
296
297 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
298
299 if (nphy->hang_avoid)
300 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 301}
302
7955de0c
RM		 303
304/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
305static void b43_radio_2055_setup(struct b43_wldev *dev,
f19ebe7d 306 const struct b43_nphy_channeltab_entry_rev2 *e)
7955de0c
RM		 307{
308 B43_WARN_ON(dev->phy.rev >= 3);
309
310 b43_chantab_radio_upload(dev, e);
311 udelay(50);
e58b1253
RM		 312 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
313 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
7955de0c 314 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e58b1253 315 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
7955de0c
RM		 316 udelay(300);
317}
318
53a6e234
MB		 319static void b43_radio_init2055_pre(struct b43_wldev *dev)
320{
321 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
322 ~B43_NPHY_RFCTL_CMD_PORFORCE);
323 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
324 B43_NPHY_RFCTL_CMD_CHIP0PU |
325 B43_NPHY_RFCTL_CMD_OEPORFORCE);
326 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
327 B43_NPHY_RFCTL_CMD_PORFORCE);
328}
329
330static void b43_radio_init2055_post(struct b43_wldev *dev)
331{
036cafe4 332 struct b43_phy_n *nphy = dev->phy.n;
53a6e234
MB		 333 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
334 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
335 int i;
336 u16 val;
036cafe4
RM		 337 bool workaround = false;
338
339 if (sprom->revision < 4)
340 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
341 binfo->type != 0x46D ||
342 binfo->rev < 0x41);
343 else
7a4db8f5
RM		 344 workaround =
345 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
53a6e234
MB		 346
347 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
036cafe4
RM		 348 if (workaround) {
349 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
350 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
53a6e234 351 }
036cafe4
RM		 352 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
353 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
53a6e234 354 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
53a6e234 355 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
53a6e234
MB		 356 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
357 msleep(1);
358 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
036cafe4
RM		 359 for (i = 0; i < 200; i++) {
360 val = b43_radio_read(dev, B2055_CAL_COUT2);
361 if (val & 0x80) {
362 i = 0;
53a6e234 363 break;
036cafe4 364 }
53a6e234
MB		 365 udelay(10);
366 }
036cafe4
RM		 367 if (i)
368 b43err(dev->wl, "radio post init timeout\n");
53a6e234 369 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
78159788 370 b43_switch_channel(dev, dev->phy.channel);
036cafe4
RM		 371 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
372 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
373 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
374 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
375 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
376 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
377 if (!nphy->gain_boost) {
378 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
379 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
380 } else {
381 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
382 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
383 }
384 udelay(2);
53a6e234
MB		 385}
386
c2b7aefd
RM		 387/*
388 * Initialize a Broadcom 2055 N-radio
389 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
390 */
53a6e234
MB		 391static void b43_radio_init2055(struct b43_wldev *dev)
392{
393 b43_radio_init2055_pre(dev);
a2d9bc6f
RM		 394 if (b43_status(dev) < B43_STAT_INITIALIZED) {
395 /* Follow wl, not specs. Do not force uploading all regs */
396 b2055_upload_inittab(dev, 0, 0);
397 } else {
398 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
399 b2055_upload_inittab(dev, ghz5, 0);
400 }
53a6e234
MB		 401 b43_radio_init2055_post(dev);
402}
403
ea7ee14b
RM		 404static void b43_radio_init2056_pre(struct b43_wldev *dev)
405{
406 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
407 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
408 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
409 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
410 B43_NPHY_RFCTL_CMD_OEPORFORCE);
411 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
412 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
413 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
414 B43_NPHY_RFCTL_CMD_CHIP0PU);
415}
416
417static void b43_radio_init2056_post(struct b43_wldev *dev)
418{
419 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
420 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
421 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
422 msleep(1);
423 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
424 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
425 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
426 /*
427 if (nphy->init_por)
428 Call Radio 2056 Recalibrate
429 */
430}
431
d817f4e1
RM		 432/*
433 * Initialize a Broadcom 2056 N-radio
434 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
435 */
436static void b43_radio_init2056(struct b43_wldev *dev)
437{
ea7ee14b
RM		 438 b43_radio_init2056_pre(dev);
439 b2056_upload_inittabs(dev, 0, 0);
440 b43_radio_init2056_post(dev);
d817f4e1
RM		 441}
442
4772ae10
RM		 443/*
444 * Upload the N-PHY tables.
445 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
446 */
95b66bad
MB		 447static void b43_nphy_tables_init(struct b43_wldev *dev)
448{
4772ae10
RM		 449 if (dev->phy.rev < 3)
450 b43_nphy_rev0_1_2_tables_init(dev);
451 else
452 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 453}
454
e50cbcf6
RM		 455/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
456static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
457{
458 struct b43_phy_n *nphy = dev->phy.n;
459 enum ieee80211_band band;
460 u16 tmp;
461
462 if (!enable) {
463 nphy->rfctrl_intc1_save = b43_phy_read(dev,
464 B43_NPHY_RFCTL_INTC1);
465 nphy->rfctrl_intc2_save = b43_phy_read(dev,
466 B43_NPHY_RFCTL_INTC2);
467 band = b43_current_band(dev->wl);
468 if (dev->phy.rev >= 3) {
469 if (band == IEEE80211_BAND_5GHZ)
470 tmp = 0x600;
471 else
472 tmp = 0x480;
473 } else {
474 if (band == IEEE80211_BAND_5GHZ)
475 tmp = 0x180;
476 else
477 tmp = 0x120;
478 }
479 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
480 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
481 } else {
482 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
483 nphy->rfctrl_intc1_save);
484 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
485 nphy->rfctrl_intc2_save);
486 }
487}
488
fe3e46e8
RM		 489/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
490static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
491{
492 struct b43_phy_n *nphy = dev->phy.n;
493 u16 tmp;
494 enum ieee80211_band band = b43_current_band(dev->wl);
495 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
496 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
497
498 if (dev->phy.rev >= 3) {
499 if (ipa) {
500 tmp = 4;
501 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
502 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
503 }
504
505 tmp = 1;
506 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
507 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
508 }
509}
510
4a933c85
RM		 511/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
512static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
513{
514 u32 tmslow;
515
516 if (dev->phy.type != B43_PHYTYPE_N)
517 return;
518
519 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
520 if (force)
521 tmslow |= SSB_TMSLOW_FGC;
522 else
523 tmslow &= ~SSB_TMSLOW_FGC;
524 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
525}
526
527/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 528static void b43_nphy_reset_cca(struct b43_wldev *dev)
529{
530 u16 bbcfg;
531
4a933c85 532 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 533 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 534 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
535 udelay(1);
536 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
537 b43_nphy_bmac_clock_fgc(dev, 0);
67c0d6e2 538 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 539}
540
ad9716e8
RM		 541/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
542static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
543{
544 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
545
546 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
547 if (preamble == 1)
548 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
549 else
550 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
551
552 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
553}
554
4f4ab6cd
RM		 555/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
556static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
557{
558 struct b43_phy_n *nphy = dev->phy.n;
559
560 bool override = false;
561 u16 chain = 0x33;
562
563 if (nphy->txrx_chain == 0) {
564 chain = 0x11;
565 override = true;
566 } else if (nphy->txrx_chain == 1) {
567 chain = 0x22;
568 override = true;
569 }
570
571 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
572 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
573 chain);
574
575 if (override)
576 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
577 B43_NPHY_RFSEQMODE_CAOVER);
578 else
579 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
580 ~B43_NPHY_RFSEQMODE_CAOVER);
581}
582
2faa6b83
RM		 583/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
584static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
585 u16 samps, u8 time, bool wait)
586{
587 int i;
588 u16 tmp;
589
590 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
591 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
592 if (wait)
593 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
594 else
595 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
596
597 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
598
599 for (i = 1000; i; i--) {
600 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
601 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
602 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
603 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
604 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
605 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
606 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
607 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
608
609 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
610 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
611 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
612 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
613 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
614 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
615 return;
616 }
617 udelay(10);
618 }
619 memset(est, 0, sizeof(*est));
620}
621
a67162ab
RM		 622/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
623static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
624 struct b43_phy_n_iq_comp *pcomp)
625{
626 if (write) {
627 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
628 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
629 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
630 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
631 } else {
632 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
633 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
634 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
635 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
636 }
637}
638
c7455cf9
RM		 639#if 0
640/* Ready but not used anywhere */
026816fc
RM		 641/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
642static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
643{
644 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
645
646 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
647 if (core == 0) {
648 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
649 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
650 } else {
651 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
652 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
653 }
654 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
655 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
656 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
657 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
658 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
659 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
660 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
661 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
662}
663
664/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
665static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
666{
667 u8 rxval, txval;
668 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
669
670 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
671 if (core == 0) {
672 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
673 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
674 } else {
675 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
676 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
677 }
678 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
679 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
680 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
681 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
682 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
683 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
684 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
685 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
686
687 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
688 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
689
acd82aa8
LF		 690 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
691 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 692 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
693 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
694 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
695 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
696 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
697 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
698 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
699
700 if (core == 0) {
701 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
702 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
703 } else {
704 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
705 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
706 }
707
67cbc3ed
RM		 708 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
709 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 710 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 711
712 if (core == 0) {
713 rxval = 1;
714 txval = 8;
715 } else {
716 rxval = 4;
717 txval = 2;
718 }
67cbc3ed
RM		 719 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
720 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc 721}
c7455cf9 722#endif
026816fc 723
34a56f2c
RM		 724/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
725static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
726{
727 int i;
728 s32 iq;
729 u32 ii;
730 u32 qq;
731 int iq_nbits, qq_nbits;
732 int arsh, brsh;
733 u16 tmp, a, b;
734
735 struct nphy_iq_est est;
736 struct b43_phy_n_iq_comp old;
737 struct b43_phy_n_iq_comp new = { };
738 bool error = false;
739
740 if (mask == 0)
741 return;
742
743 b43_nphy_rx_iq_coeffs(dev, false, &old);
744 b43_nphy_rx_iq_coeffs(dev, true, &new);
745 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
746 new = old;
747
748 for (i = 0; i < 2; i++) {
749 if (i == 0 && (mask & 1)) {
750 iq = est.iq0_prod;
751 ii = est.i0_pwr;
752 qq = est.q0_pwr;
753 } else if (i == 1 && (mask & 2)) {
754 iq = est.iq1_prod;
755 ii = est.i1_pwr;
756 qq = est.q1_pwr;
757 } else {
34a56f2c
RM		 758 continue;
759 }
760
761 if (ii + qq < 2) {
762 error = true;
763 break;
764 }
765
766 iq_nbits = fls(abs(iq));
767 qq_nbits = fls(qq);
768
769 arsh = iq_nbits - 20;
770 if (arsh >= 0) {
771 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
772 tmp = ii >> arsh;
773 } else {
774 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
775 tmp = ii << -arsh;
776 }
777 if (tmp == 0) {
778 error = true;
779 break;
780 }
781 a /= tmp;
782
783 brsh = qq_nbits - 11;
784 if (brsh >= 0) {
785 b = (qq << (31 - qq_nbits));
786 tmp = ii >> brsh;
787 } else {
788 b = (qq << (31 - qq_nbits));
789 tmp = ii << -brsh;
790 }
791 if (tmp == 0) {
792 error = true;
793 break;
794 }
795 b = int_sqrt(b / tmp - a * a) - (1 << 10);
796
797 if (i == 0 && (mask & 0x1)) {
798 if (dev->phy.rev >= 3) {
799 new.a0 = a & 0x3FF;
800 new.b0 = b & 0x3FF;
801 } else {
802 new.a0 = b & 0x3FF;
803 new.b0 = a & 0x3FF;
804 }
805 } else if (i == 1 && (mask & 0x2)) {
806 if (dev->phy.rev >= 3) {
807 new.a1 = a & 0x3FF;
808 new.b1 = b & 0x3FF;
809 } else {
810 new.a1 = b & 0x3FF;
811 new.b1 = a & 0x3FF;
812 }
813 }
814 }
815
816 if (error)
817 new = old;
818
819 b43_nphy_rx_iq_coeffs(dev, true, &new);
820}
821
09146400
RM		 822/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
823static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
824{
825 u16 array[4];
826 int i;
827
828 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
829 for (i = 0; i < 4; i++)
830 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
831
832 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
833 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
834 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
835 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
836}
837
bbec398c 838/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
20407ed8
JP		 839static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
840 const u16 *clip_st)
bbec398c
RM		 841{
842 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
843 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
844}
845
846/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
847static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
848{
849 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
850 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
851}
852
8987a9e9
RM		 853/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
854static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
855{
856 if (dev->phy.rev >= 3) {
857 if (!init)
858 return;
859 if (0 /* FIXME */) {
860 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
861 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
862 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
863 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
864 }
865 } else {
866 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
867 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
868
869 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
870 0xFC00);
871 b43_write32(dev, B43_MMIO_MACCTL,
872 b43_read32(dev, B43_MMIO_MACCTL) &
873 ~B43_MACCTL_GPOUTSMSK);
874 b43_write16(dev, B43_MMIO_GPIO_MASK,
875 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
876 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
877 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
878
879 if (init) {
880 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
881 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
882 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
883 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
884 }
885 }
886}
887
bbec398c
RM		 888/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
889static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
890{
891 u16 tmp;
892
893 if (dev->dev->id.revision == 16)
894 b43_mac_suspend(dev);
895
896 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
897 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
898 B43_NPHY_CLASSCTL_WAITEDEN);
899 tmp &= ~mask;
900 tmp |= (val & mask);
901 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
902
903 if (dev->dev->id.revision == 16)
904 b43_mac_enable(dev);
905
906 return tmp;
907}
908
5c1a140a
RM		 909/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
910static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
911{
912 struct b43_phy *phy = &dev->phy;
913 struct b43_phy_n *nphy = phy->n;
914
915 if (enable) {
20407ed8 916 static const u16 clip[] = { 0xFFFF, 0xFFFF };
5c1a140a
RM		 917 if (nphy->deaf_count++ == 0) {
918 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
919 b43_nphy_classifier(dev, 0x7, 0);
920 b43_nphy_read_clip_detection(dev, nphy->clip_state);
921 b43_nphy_write_clip_detection(dev, clip);
922 }
923 b43_nphy_reset_cca(dev);
924 } else {
925 if (--nphy->deaf_count == 0) {
926 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
927 b43_nphy_write_clip_detection(dev, nphy->clip_state);
928 }
929 }
930}
931
53ae8e8c
RM		 932/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
933static void b43_nphy_stop_playback(struct b43_wldev *dev)
934{
935 struct b43_phy_n *nphy = dev->phy.n;
936 u16 tmp;
937
938 if (nphy->hang_avoid)
939 b43_nphy_stay_in_carrier_search(dev, 1);
940
941 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
942 if (tmp & 0x1)
943 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
944 else if (tmp & 0x2)
acd82aa8 945 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
53ae8e8c
RM		 946
947 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
948
949 if (nphy->bb_mult_save & 0x80000000) {
950 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 951 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 952 nphy->bb_mult_save = 0;
953 }
954
955 if (nphy->hang_avoid)
956 b43_nphy_stay_in_carrier_search(dev, 0);
957}
958
9442e5b5
RM		 959/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
960static void b43_nphy_spur_workaround(struct b43_wldev *dev)
961{
962 struct b43_phy_n *nphy = dev->phy.n;
963
204a665b 964 u8 channel = dev->phy.channel;
9442e5b5
RM		 965 int tone[2] = { 57, 58 };
966 u32 noise[2] = { 0x3FF, 0x3FF };
967
968 B43_WARN_ON(dev->phy.rev < 3);
969
970 if (nphy->hang_avoid)
971 b43_nphy_stay_in_carrier_search(dev, 1);
972
9442e5b5
RM		 973 if (nphy->gband_spurwar_en) {
974 /* TODO: N PHY Adjust Analog Pfbw (7) */
975 if (channel == 11 && dev->phy.is_40mhz)
976 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
977 else
978 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
979 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
980 }
981
982 if (nphy->aband_spurwar_en) {
983 if (channel == 54) {
984 tone[0] = 0x20;
985 noise[0] = 0x25F;
986 } else if (channel == 38 || channel == 102 || channel == 118) {
987 if (0 /* FIXME */) {
988 tone[0] = 0x20;
989 noise[0] = 0x21F;
990 } else {
991 tone[0] = 0;
992 noise[0] = 0;
993 }
994 } else if (channel == 134) {
995 tone[0] = 0x20;
996 noise[0] = 0x21F;
997 } else if (channel == 151) {
998 tone[0] = 0x10;
999 noise[0] = 0x23F;
1000 } else if (channel == 153 || channel == 161) {
1001 tone[0] = 0x30;
1002 noise[0] = 0x23F;
1003 } else {
1004 tone[0] = 0;
1005 noise[0] = 0;
1006 }
1007
1008 if (!tone[0] && !noise[0])
1009 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1010 else
1011 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1012 }
1013
1014 if (nphy->hang_avoid)
1015 b43_nphy_stay_in_carrier_search(dev, 0);
1016}
1017
d24019ad
RM		 1018/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1019static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1020{
1021 struct b43_phy_n *nphy = dev->phy.n;
1022
1023 u8 i;
1024 s16 tmp;
1025 u16 data[4];
1026 s16 gain[2];
1027 u16 minmax[2];
20407ed8 1028 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
d24019ad
RM		 1029
1030 if (nphy->hang_avoid)
1031 b43_nphy_stay_in_carrier_search(dev, 1);
1032
1033 if (nphy->gain_boost) {
1034 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1035 gain[0] = 6;
1036 gain[1] = 6;
1037 } else {
204a665b 1038 tmp = 40370 - 315 * dev->phy.channel;
d24019ad 1039 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
204a665b 1040 tmp = 23242 - 224 * dev->phy.channel;
d24019ad
RM		 1041 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1042 }
1043 } else {
1044 gain[0] = 0;
1045 gain[1] = 0;
1046 }
1047
1048 for (i = 0; i < 2; i++) {
1049 if (nphy->elna_gain_config) {
1050 data[0] = 19 + gain[i];
1051 data[1] = 25 + gain[i];
1052 data[2] = 25 + gain[i];
1053 data[3] = 25 + gain[i];
1054 } else {
1055 data[0] = lna_gain[0] + gain[i];
1056 data[1] = lna_gain[1] + gain[i];
1057 data[2] = lna_gain[2] + gain[i];
1058 data[3] = lna_gain[3] + gain[i];
1059 }
c0f05b98 1060 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
d24019ad
RM		 1061
1062 minmax[i] = 23 + gain[i];
1063 }
1064
1065 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1066 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1067 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1068 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1069
1070 if (nphy->hang_avoid)
1071 b43_nphy_stay_in_carrier_search(dev, 0);
1072}
1073
ef5127a4 1074/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
e723ef30 1075static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
ef5127a4
RM		 1076{
1077 struct b43_phy_n *nphy = dev->phy.n;
1078 u8 i, j;
1079 u8 code;
c0f05b98 1080 u16 tmp;
ef5127a4
RM		 1081
1082 /* TODO: for PHY >= 3
1083 s8 *lna1_gain, *lna2_gain;
1084 u8 *gain_db, *gain_bits;
1085 u16 *rfseq_init;
1086 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1087 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1088 */
1089
1090 u8 rfseq_events[3] = { 6, 8, 7 };
1091 u8 rfseq_delays[3] = { 10, 30, 1 };
1092
1093 if (dev->phy.rev >= 3) {
1094 /* TODO */
1095 } else {
1096 /* Set Clip 2 detect */
1097 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1098 B43_NPHY_C1_CGAINI_CL2DETECT);
1099 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1100 B43_NPHY_C2_CGAINI_CL2DETECT);
1101
1102 /* Set narrowband clip threshold */
a5d3598d
RM		 1103 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1104 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
ef5127a4
RM		 1105
1106 if (!dev->phy.is_40mhz) {
1107 /* Set dwell lengths */
a5d3598d
RM		 1108 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1109 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1110 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1111 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
ef5127a4
RM		 1112 }
1113
1114 /* Set wideband clip 2 threshold */
1115 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1116 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1117 21);
1118 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1119 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1120 21);
1121
1122 if (!dev->phy.is_40mhz) {
1123 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1124 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1125 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1126 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1127 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1128 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1129 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1130 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1131 }
1132
a5d3598d 1133 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1134
1135 if (nphy->gain_boost) {
1136 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1137 dev->phy.is_40mhz)
1138 code = 4;
1139 else
1140 code = 5;
1141 } else {
1142 code = dev->phy.is_40mhz ? 6 : 7;
1143 }
1144
1145 /* Set HPVGA2 index */
1146 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1147 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1148 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1149 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1150 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1151 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1152
1153 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1154 /* specs say about 2 loops, but wl does 4 */
1155 for (i = 0; i < 4; i++)
1156 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1157 (code << 8 | 0x7C));
ef5127a4 1158
d24019ad 1159 b43_nphy_adjust_lna_gain_table(dev);
ef5127a4
RM		 1160
1161 if (nphy->elna_gain_config) {
1162 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1163 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1164 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1165 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1166 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1167
1168 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1169 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1170 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1171 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1172 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1173
1174 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1175 /* specs say about 2 loops, but wl does 4 */
1176 for (i = 0; i < 4; i++)
1177 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1178 (code << 8 | 0x74));
ef5127a4
RM		 1179 }
1180
1181 if (dev->phy.rev == 2) {
1182 for (i = 0; i < 4; i++) {
1183 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1184 (0x0400 * i) + 0x0020);
c0f05b98
RM		 1185 for (j = 0; j < 21; j++) {
1186 tmp = j * (i < 2 ? 3 : 1);
ef5127a4 1187 b43_phy_write(dev,
c0f05b98
RM		 1188 B43_NPHY_TABLE_DATALO, tmp);
1189 }
ef5127a4
RM		 1190 }
1191
9501fefe
RM		 1192 b43_nphy_set_rf_sequence(dev, 5,
1193 rfseq_events, rfseq_delays, 3);
ef5127a4 1194 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
acd82aa8 1195 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
ef5127a4
RM		 1196 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1197
1198 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1199 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1200 0xFF80, 4);
1201 }
1202 }
1203}
1204
28fd7daa
RM		 1205/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1206static void b43_nphy_workarounds(struct b43_wldev *dev)
1207{
1208 struct ssb_bus *bus = dev->dev->bus;
1209 struct b43_phy *phy = &dev->phy;
1210 struct b43_phy_n *nphy = phy->n;
1211
1212 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1213 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1214
1215 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1216 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1217
a5d3598d 1218 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
28fd7daa
RM		 1219 b43_nphy_classifier(dev, 1, 0);
1220 else
1221 b43_nphy_classifier(dev, 1, 1);
1222
1223 if (nphy->hang_avoid)
1224 b43_nphy_stay_in_carrier_search(dev, 1);
1225
1226 b43_phy_set(dev, B43_NPHY_IQFLIP,
1227 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1228
1229 if (dev->phy.rev >= 3) {
1230 /* TODO */
1231 } else {
1232 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1233 nphy->band5g_pwrgain) {
1234 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1235 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1236 } else {
1237 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1238 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1239 }
1240
d242b90a
RM		 1241 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1242 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1243 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1244 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
28fd7daa
RM		 1245
1246 if (dev->phy.rev < 2) {
d242b90a
RM		 1247 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1248 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1249 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1250 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1251 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1252 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
28fd7daa
RM		 1253 }
1254
1255 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1256 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1257 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1258 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1259
1260 if (bus->sprom.boardflags2_lo & 0x100 &&
1261 bus->boardinfo.type == 0x8B) {
1262 delays1[0] = 0x1;
1263 delays1[5] = 0x14;
1264 }
9501fefe
RM		 1265 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1266 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
28fd7daa 1267
e723ef30 1268 b43_nphy_gain_ctrl_workarounds(dev);
28fd7daa
RM		 1269
1270 if (dev->phy.rev < 2) {
1271 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
e7f45d3f
GS		 1272 b43_hf_write(dev, b43_hf_read(dev) |
1273 B43_HF_MLADVW);
28fd7daa
RM		 1274 } else if (dev->phy.rev == 2) {
1275 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1276 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1277 }
1278
1279 if (dev->phy.rev < 2)
1280 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1281 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1282
1283 /* Set phase track alpha and beta */
1284 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1285 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1286 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1287 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1288 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1289 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1290
1291 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
acd82aa8 1292 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
28fd7daa
RM		 1293 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1294 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1295 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1296
1297 if (dev->phy.rev == 2)
1298 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1299 B43_NPHY_FINERX2_CGC_DECGC);
1300 }
1301
1302 if (nphy->hang_avoid)
1303 b43_nphy_stay_in_carrier_search(dev, 0);
1304}
1305
5f6393ec
RM		 1306/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1307static int b43_nphy_load_samples(struct b43_wldev *dev,
1308 struct b43_c32 *samples, u16 len) {
1309 struct b43_phy_n *nphy = dev->phy.n;
1310 u16 i;
1311 u32 *data;
1312
1313 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1314 if (!data) {
1315 b43err(dev->wl, "allocation for samples loading failed\n");
1316 return -ENOMEM;
1317 }
1318 if (nphy->hang_avoid)
1319 b43_nphy_stay_in_carrier_search(dev, 1);
1320
1321 for (i = 0; i < len; i++) {
1322 data[i] = (samples[i].i & 0x3FF << 10);
1323 data[i] |= samples[i].q & 0x3FF;
1324 }
1325 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1326
1327 kfree(data);
1328 if (nphy->hang_avoid)
1329 b43_nphy_stay_in_carrier_search(dev, 0);
1330 return 0;
1331}
1332
59af099b
RM		 1333/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1334static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1335 bool test)
1336{
1337 int i;
f2982181 1338 u16 bw, len, rot, angle;
da860475 1339 struct b43_c32 *samples;
f2982181 1340
59af099b
RM		 1341
1342 bw = (dev->phy.is_40mhz) ? 40 : 20;
1343 len = bw << 3;
1344
1345 if (test) {
1346 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1347 bw = 82;
1348 else
1349 bw = 80;
1350
1351 if (dev->phy.is_40mhz)
1352 bw <<= 1;
1353
1354 len = bw << 1;
1355 }
1356
baeb2ffa 1357 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
40bd5203
RM		 1358 if (!samples) {
1359 b43err(dev->wl, "allocation for samples generation failed\n");
1360 return 0;
1361 }
59af099b
RM		 1362 rot = (((freq * 36) / bw) << 16) / 100;
1363 angle = 0;
1364
f2982181
RM		 1365 for (i = 0; i < len; i++) {
1366 samples[i] = b43_cordic(angle);
1367 angle += rot;
1368 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1369 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
59af099b
RM		 1370 }
1371
5f6393ec 1372 i = b43_nphy_load_samples(dev, samples, len);
f2982181 1373 kfree(samples);
5f6393ec 1374 return (i < 0) ? 0 : len;
59af099b
RM		 1375}
1376
10a79873
RM		 1377/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1378static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1379 u16 wait, bool iqmode, bool dac_test)
1380{
1381 struct b43_phy_n *nphy = dev->phy.n;
1382 int i;
1383 u16 seq_mode;
1384 u32 tmp;
1385
1386 if (nphy->hang_avoid)
1387 b43_nphy_stay_in_carrier_search(dev, true);
1388
1389 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1390 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1391 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1392 }
1393
1394 if (!dev->phy.is_40mhz)
1395 tmp = 0x6464;
1396 else
1397 tmp = 0x4747;
1398 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1399
1400 if (nphy->hang_avoid)
1401 b43_nphy_stay_in_carrier_search(dev, false);
1402
1403 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1404
1405 if (loops != 0xFFFF)
1406 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1407 else
1408 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1409
1410 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1411
1412 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1413
1414 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1415 if (iqmode) {
1416 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1417 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1418 } else {
1419 if (dac_test)
1420 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1421 else
1422 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1423 }
1424 for (i = 0; i < 100; i++) {
1425 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1426 i = 0;
1427 break;
1428 }
1429 udelay(10);
1430 }
1431 if (i)
1432 b43err(dev->wl, "run samples timeout\n");
1433
1434 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1435}
1436
59af099b
RM		 1437/*
1438 * Transmits a known value for LO calibration
1439 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1440 */
1441static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1442 bool iqmode, bool dac_test)
1443{
1444 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1445 if (samp == 0)
1446 return -1;
1447 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1448 return 0;
1449}
1450
6dcd9d91
RM		 1451/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1452static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1453{
1454 struct b43_phy_n *nphy = dev->phy.n;
1455 int i, j;
1456 u32 tmp;
1457 u32 cur_real, cur_imag, real_part, imag_part;
1458
1459 u16 buffer[7];
1460
1461 if (nphy->hang_avoid)
1462 b43_nphy_stay_in_carrier_search(dev, true);
1463
9145834e 1464 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 1465
1466 for (i = 0; i < 2; i++) {
1467 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1468 (buffer[i * 2 + 1] & 0x3FF);
1469 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1470 (((i + 26) << 10) | 320));
1471 for (j = 0; j < 128; j++) {
1472 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1473 ((tmp >> 16) & 0xFFFF));
1474 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1475 (tmp & 0xFFFF));
1476 }
1477 }
1478
1479 for (i = 0; i < 2; i++) {
1480 tmp = buffer[5 + i];
1481 real_part = (tmp >> 8) & 0xFF;
1482 imag_part = (tmp & 0xFF);
1483 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1484 (((i + 26) << 10) | 448));
1485
1486 if (dev->phy.rev >= 3) {
1487 cur_real = real_part;
1488 cur_imag = imag_part;
1489 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1490 }
1491
1492 for (j = 0; j < 128; j++) {
1493 if (dev->phy.rev < 3) {
1494 cur_real = (real_part * loscale[j] + 128) >> 8;
1495 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1496 tmp = ((cur_real & 0xFF) << 8) |
1497 (cur_imag & 0xFF);
1498 }
1499 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1500 ((tmp >> 16) & 0xFFFF));
1501 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1502 (tmp & 0xFFFF));
1503 }
1504 }
1505
1506 if (dev->phy.rev >= 3) {
1507 b43_shm_write16(dev, B43_SHM_SHARED,
1508 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1509 b43_shm_write16(dev, B43_SHM_SHARED,
1510 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1511 }
1512
1513 if (nphy->hang_avoid)
1514 b43_nphy_stay_in_carrier_search(dev, false);
1515}
1516
9501fefe
RM		 1517/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1518static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1519 u8 *events, u8 *delays, u8 length)
1520{
1521 struct b43_phy_n *nphy = dev->phy.n;
1522 u8 i;
1523 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1524 u16 offset1 = cmd << 4;
1525 u16 offset2 = offset1 + 0x80;
1526
1527 if (nphy->hang_avoid)
1528 b43_nphy_stay_in_carrier_search(dev, true);
1529
1530 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1531 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1532
1533 for (i = length; i < 16; i++) {
1534 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1535 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1536 }
1537
1538 if (nphy->hang_avoid)
1539 b43_nphy_stay_in_carrier_search(dev, false);
1540}
1541
67c0d6e2 1542/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 1543static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1544 enum b43_nphy_rf_sequence seq)
1545{
1546 static const u16 trigger[] = {
1547 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1548 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1549 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1550 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1551 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1552 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1553 };
1554 int i;
c57199bc 1555 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
95b66bad
MB		 1556
1557 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1558
1559 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1560 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1561 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1562 for (i = 0; i < 200; i++) {
1563 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1564 goto ok;
1565 msleep(1);
1566 }
1567 b43err(dev->wl, "RF sequence status timeout\n");
1568ok:
c57199bc 1569 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
95b66bad
MB		 1570}
1571
75377b24
RM		 1572/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1573static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1574 u16 value, u8 core, bool off)
1575{
1576 int i;
1577 u8 index = fls(field);
1578 u8 addr, en_addr, val_addr;
1579 /* we expect only one bit set */
3ed0fac3 1580 B43_WARN_ON(field & (~(1 << (index - 1))));
75377b24
RM		 1581
1582 if (dev->phy.rev >= 3) {
1583 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1584 for (i = 0; i < 2; i++) {
1585 if (index == 0 || index == 16) {
1586 b43err(dev->wl,
1587 "Unsupported RF Ctrl Override call\n");
1588 return;
1589 }
1590
1591 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1592 en_addr = B43_PHY_N((i == 0) ?
1593 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1594 val_addr = B43_PHY_N((i == 0) ?
1595 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1596
1597 if (off) {
1598 b43_phy_mask(dev, en_addr, ~(field));
1599 b43_phy_mask(dev, val_addr,
1600 ~(rf_ctrl->val_mask));
1601 } else {
1602 if (core == 0 || ((1 << core) & i) != 0) {
1603 b43_phy_set(dev, en_addr, field);
1604 b43_phy_maskset(dev, val_addr,
1605 ~(rf_ctrl->val_mask),
1606 (value << rf_ctrl->val_shift));
1607 }
1608 }
1609 }
1610 } else {
1611 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1612 if (off) {
1613 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1614 value = 0;
1615 } else {
1616 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1617 }
1618
1619 for (i = 0; i < 2; i++) {
1620 if (index <= 1 || index == 16) {
1621 b43err(dev->wl,
1622 "Unsupported RF Ctrl Override call\n");
1623 return;
1624 }
1625
1626 if (index == 2 || index == 10 ||
1627 (index >= 13 && index <= 15)) {
1628 core = 1;
1629 }
1630
1631 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1632 addr = B43_PHY_N((i == 0) ?
1633 rf_ctrl->addr0 : rf_ctrl->addr1);
1634
1635 if ((core & (1 << i)) != 0)
1636 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1637 (value << rf_ctrl->shift));
1638
1639 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1640 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1641 B43_NPHY_RFCTL_CMD_START);
1642 udelay(1);
1643 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1644 }
1645 }
1646}
1647
67cbc3ed
RM		 1648/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1649static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1650 u16 value, u8 core)
1651{
1652 u8 i, j;
1653 u16 reg, tmp, val;
1654
1655 B43_WARN_ON(dev->phy.rev < 3);
1656 B43_WARN_ON(field > 4);
1657
1658 for (i = 0; i < 2; i++) {
1659 if ((core == 1 && i == 1) || (core == 2 && !i))
1660 continue;
1661
1662 reg = (i == 0) ?
1663 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1664 b43_phy_mask(dev, reg, 0xFBFF);
1665
1666 switch (field) {
1667 case 0:
1668 b43_phy_write(dev, reg, 0);
1669 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1670 break;
1671 case 1:
1672 if (!i) {
1673 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1674 0xFC3F, (value << 6));
1675 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1676 0xFFFE, 1);
1677 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1678 B43_NPHY_RFCTL_CMD_START);
1679 for (j = 0; j < 100; j++) {
1680 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1681 j = 0;
1682 break;
1683 }
1684 udelay(10);
1685 }
1686 if (j)
1687 b43err(dev->wl,
1688 "intc override timeout\n");
1689 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1690 0xFFFE);
1691 } else {
1692 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1693 0xFC3F, (value << 6));
1694 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1695 0xFFFE, 1);
1696 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1697 B43_NPHY_RFCTL_CMD_RXTX);
1698 for (j = 0; j < 100; j++) {
1699 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1700 j = 0;
1701 break;
1702 }
1703 udelay(10);
1704 }
1705 if (j)
1706 b43err(dev->wl,
1707 "intc override timeout\n");
1708 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1709 0xFFFE);
1710 }
1711 break;
1712 case 2:
1713 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1714 tmp = 0x0020;
1715 val = value << 5;
1716 } else {
1717 tmp = 0x0010;
1718 val = value << 4;
1719 }
1720 b43_phy_maskset(dev, reg, ~tmp, val);
1721 break;
1722 case 3:
1723 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1724 tmp = 0x0001;
1725 val = value;
1726 } else {
1727 tmp = 0x0004;
1728 val = value << 2;
1729 }
1730 b43_phy_maskset(dev, reg, ~tmp, val);
1731 break;
1732 case 4:
1733 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1734 tmp = 0x0002;
1735 val = value << 1;
1736 } else {
1737 tmp = 0x0008;
1738 val = value << 3;
1739 }
1740 b43_phy_maskset(dev, reg, ~tmp, val);
1741 break;
1742 }
1743 }
1744}
1745
bec18645 1746/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
95b66bad
MB		 1747static void b43_nphy_bphy_init(struct b43_wldev *dev)
1748{
1749 unsigned int i;
1750 u16 val;
1751
1752 val = 0x1E1F;
fee613b7 1753 for (i = 0; i < 16; i++) {
95b66bad
MB		 1754 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1755 val -= 0x202;
1756 }
1757 val = 0x3E3F;
1758 for (i = 0; i < 16; i++) {
fee613b7 1759 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
95b66bad
MB		 1760 val -= 0x202;
1761 }
1762 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1763}
1764
3c95627d
RM		 1765/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1766static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
76b002bd
RM		 1767 s8 offset, u8 core, u8 rail,
1768 enum b43_nphy_rssi_type type)
3c95627d
RM		 1769{
1770 u16 tmp;
1771 bool core1or5 = (core == 1) || (core == 5);
1772 bool core2or5 = (core == 2) || (core == 5);
1773
1774 offset = clamp_val(offset, -32, 31);
1775 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1776
76b002bd 1777 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 1778 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
76b002bd 1779 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 1780 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
76b002bd 1781 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 1782 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
76b002bd 1783 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 1784 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
76b002bd
RM		 1785
1786 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 1787 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
76b002bd 1788 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 1789 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
76b002bd 1790 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 1791 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
76b002bd 1792 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 1793 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
76b002bd
RM		 1794
1795 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 1796 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
76b002bd 1797 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 1798 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
76b002bd 1799 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 1800 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
76b002bd 1801 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 1802 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
76b002bd
RM		 1803
1804 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 1805 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
76b002bd 1806 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 1807 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
76b002bd 1808 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 1809 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
76b002bd 1810 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 1811 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
76b002bd
RM		 1812
1813 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 1814 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
76b002bd 1815 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 1816 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
76b002bd 1817 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 1818 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
76b002bd 1819 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 1820 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
76b002bd
RM		 1821
1822 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 1823 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
76b002bd 1824 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 1825 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
76b002bd
RM		 1826
1827 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d 1828 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
76b002bd 1829 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d
RM		 1830 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1831}
1832
99b82c41 1833static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
3c95627d
RM		 1834{
1835 u16 val;
1836
99b82c41
RM		 1837 if (type < 3)
1838 val = 0;
1839 else if (type == 6)
1840 val = 1;
1841 else if (type == 3)
1842 val = 2;
1843 else
1844 val = 3;
1845
1846 val = (val << 12) | (val << 14);
1847 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1848 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
3c95627d 1849
99b82c41
RM		 1850 if (type < 3) {
1851 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1852 (type + 1) << 4);
1853 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1854 (type + 1) << 4);
1855 }
3c95627d 1856
99b82c41 1857 if (code == 0) {
99f6c2ef 1858 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
3c95627d 1859 if (type < 3) {
99f6c2ef
RM		 1860 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1861 ~(B43_NPHY_RFCTL_CMD_RXEN |
1862 B43_NPHY_RFCTL_CMD_CORESEL));
1863 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1864 ~(0x1 << 12 |
1865 0x1 << 5 |
1866 0x1 << 1 |
1867 0x1));
1868 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1869 ~B43_NPHY_RFCTL_CMD_START);
99b82c41 1870 udelay(20);
99f6c2ef 1871 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d 1872 }
99b82c41 1873 } else {
99f6c2ef 1874 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
99b82c41
RM		 1875 if (type < 3) {
1876 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
99f6c2ef
RM		 1877 ~(B43_NPHY_RFCTL_CMD_RXEN |
1878 B43_NPHY_RFCTL_CMD_CORESEL),
1879 (B43_NPHY_RFCTL_CMD_RXEN |
1880 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1881 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1882 (0x1 << 12 |
1883 0x1 << 5 |
1884 0x1 << 1 |
1885 0x1));
1886 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1887 B43_NPHY_RFCTL_CMD_START);
99b82c41 1888 udelay(20);
99f6c2ef 1889 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d
RM		 1890 }
1891 }
1892}
1893
99b82c41
RM		 1894static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1895{
6e3b15a9
RM		 1896 struct b43_phy_n *nphy = dev->phy.n;
1897 u8 i;
1898 u16 reg, val;
1899
1900 if (code == 0) {
1901 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1902 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1903 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1904 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1905 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1906 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1907 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1908 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1909 } else {
1910 for (i = 0; i < 2; i++) {
1911 if ((code == 1 && i == 1) || (code == 2 && !i))
1912 continue;
1913
1914 reg = (i == 0) ?
1915 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1916 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1917
1918 if (type < 3) {
1919 reg = (i == 0) ?
1920 B43_NPHY_AFECTL_C1 :
1921 B43_NPHY_AFECTL_C2;
1922 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1923
1924 reg = (i == 0) ?
1925 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1926 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1927 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1928
1929 if (type == 0)
1930 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1931 else if (type == 1)
1932 val = 16;
1933 else
1934 val = 32;
1935 b43_phy_set(dev, reg, val);
1936
1937 reg = (i == 0) ?
1938 B43_NPHY_TXF_40CO_B1S0 :
1939 B43_NPHY_TXF_40CO_B32S1;
1940 b43_phy_set(dev, reg, 0x0020);
1941 } else {
1942 if (type == 6)
1943 val = 0x0100;
1944 else if (type == 3)
1945 val = 0x0200;
1946 else
1947 val = 0x0300;
1948
1949 reg = (i == 0) ?
1950 B43_NPHY_AFECTL_C1 :
1951 B43_NPHY_AFECTL_C2;
1952
1953 b43_phy_maskset(dev, reg, 0xFCFF, val);
1954 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1955
1956 if (type != 3 && type != 6) {
1957 enum ieee80211_band band =
1958 b43_current_band(dev->wl);
1959
1960 if ((nphy->ipa2g_on &&
1961 band == IEEE80211_BAND_2GHZ) ||
1962 (nphy->ipa5g_on &&
1963 band == IEEE80211_BAND_5GHZ))
1964 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1965 else
1966 val = 0x11;
1967 reg = (i == 0) ? 0x2000 : 0x3000;
1968 reg |= B2055_PADDRV;
1969 b43_radio_write16(dev, reg, val);
1970
1971 reg = (i == 0) ?
1972 B43_NPHY_AFECTL_OVER1 :
1973 B43_NPHY_AFECTL_OVER;
1974 b43_phy_set(dev, reg, 0x0200);
1975 }
1976 }
1977 }
1978 }
99b82c41
RM		 1979}
1980
1981/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1982static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1983{
1984 if (dev->phy.rev >= 3)
1985 b43_nphy_rev3_rssi_select(dev, code, type);
1986 else
1987 b43_nphy_rev2_rssi_select(dev, code, type);
1988}
1989
dfb4aa5d
RM		 1990/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1991static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1992{
1993 int i;
1994 for (i = 0; i < 2; i++) {
1995 if (type == 2) {
1996 if (i == 0) {
1997 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1998 0xFC, buf[0]);
1999 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2000 0xFC, buf[1]);
2001 } else {
2002 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2003 0xFC, buf[2 * i]);
2004 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2005 0xFC, buf[2 * i + 1]);
2006 }
2007 } else {
2008 if (i == 0)
2009 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2010 0xF3, buf[0] << 2);
2011 else
2012 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2013 0xF3, buf[2 * i + 1] << 2);
2014 }
2015 }
2016}
2017
2018/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2019static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2020 u8 nsamp)
2021{
2022 int i;
2023 int out;
2024 u16 save_regs_phy[9];
2025 u16 s[2];
2026
2027 if (dev->phy.rev >= 3) {
2028 save_regs_phy[0] = b43_phy_read(dev,
2029 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2030 save_regs_phy[1] = b43_phy_read(dev,
2031 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2032 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2033 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2034 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2035 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2036 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2037 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
a529cecd
RM		 2038 } else if (dev->phy.rev == 2) {
2039 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2040 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2041 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2042 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2043 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2044 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2045 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
dfb4aa5d
RM		 2046 }
2047
2048 b43_nphy_rssi_select(dev, 5, type);
2049
2050 if (dev->phy.rev < 2) {
2051 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2052 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2053 }
2054
2055 for (i = 0; i < 4; i++)
2056 buf[i] = 0;
2057
2058 for (i = 0; i < nsamp; i++) {
2059 if (dev->phy.rev < 2) {
2060 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2061 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2062 } else {
2063 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2064 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2065 }
2066
2067 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2068 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2069 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2070 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2071 }
2072 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2073 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2074
2075 if (dev->phy.rev < 2)
2076 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2077
2078 if (dev->phy.rev >= 3) {
2079 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2080 save_regs_phy[0]);
2081 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2082 save_regs_phy[1]);
2083 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2084 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2085 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2086 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2087 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2088 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
a529cecd
RM		 2089 } else if (dev->phy.rev == 2) {
2090 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2091 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2092 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2093 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2094 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2095 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2096 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
dfb4aa5d
RM		 2097 }
2098
2099 return out;
2100}
2101
4cb99775
RM		 2102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2103static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 2104{
90b9738d
RM		 2105 int i, j;
2106 u8 state[4];
2107 u8 code, val;
2108 u16 class, override;
2109 u8 regs_save_radio[2];
2110 u16 regs_save_phy[2];
8cbe6e66 2111
90b9738d 2112 s8 offset[4];
8cbe6e66
RM		 2113 u8 core;
2114 u8 rail;
90b9738d
RM		 2115
2116 u16 clip_state[2];
2117 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2118 s32 results_min[4] = { };
2119 u8 vcm_final[4] = { };
2120 s32 results[4][4] = { };
2121 s32 miniq[4][2] = { };
2122
2123 if (type == 2) {
2124 code = 0;
2125 val = 6;
2126 } else if (type < 2) {
2127 code = 25;
2128 val = 4;
2129 } else {
2130 B43_WARN_ON(1);
2131 return;
2132 }
2133
2134 class = b43_nphy_classifier(dev, 0, 0);
2135 b43_nphy_classifier(dev, 7, 4);
2136 b43_nphy_read_clip_detection(dev, clip_state);
2137 b43_nphy_write_clip_detection(dev, clip_off);
2138
2139 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2140 override = 0x140;
2141 else
2142 override = 0x110;
2143
2144 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2145 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2146 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2147 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2148
2149 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2150 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2151 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2152 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2153
2154 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2155 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2156 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2157 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2158 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2159 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2160
2161 b43_nphy_rssi_select(dev, 5, type);
2162 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2163 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2164
2165 for (i = 0; i < 4; i++) {
2166 u8 tmp[4];
2167 for (j = 0; j < 4; j++)
2168 tmp[j] = i;
2169 if (type != 1)
2170 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2171 b43_nphy_poll_rssi(dev, type, results[i], 8);
2172 if (type < 2)
2173 for (j = 0; j < 2; j++)
2174 miniq[i][j] = min(results[i][2 * j],
2175 results[i][2 * j + 1]);
2176 }
2177
2178 for (i = 0; i < 4; i++) {
2179 s32 mind = 40;
2180 u8 minvcm = 0;
2181 s32 minpoll = 249;
2182 s32 curr;
2183 for (j = 0; j < 4; j++) {
2184 if (type == 2)
2185 curr = abs(results[j][i]);
2186 else
2187 curr = abs(miniq[j][i / 2] - code * 8);
2188
2189 if (curr < mind) {
2190 mind = curr;
2191 minvcm = j;
2192 }
2193
2194 if (results[j][i] < minpoll)
2195 minpoll = results[j][i];
2196 }
2197 results_min[i] = minpoll;
2198 vcm_final[i] = minvcm;
2199 }
2200
2201 if (type != 1)
2202 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2203
2204 for (i = 0; i < 4; i++) {
2205 offset[i] = (code * 8) - results[vcm_final[i]][i];
2206
2207 if (offset[i] < 0)
2208 offset[i] = -((abs(offset[i]) + 4) / 8);
2209 else
2210 offset[i] = (offset[i] + 4) / 8;
2211
2212 if (results_min[i] == 248)
2213 offset[i] = code - 32;
2214
8cbe6e66
RM		 2215 core = (i / 2) ? 2 : 1;
2216 rail = (i % 2) ? 1 : 0;
2217
2218 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2219 type);
90b9738d
RM		 2220 }
2221
2222 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
0b81c23d 2223 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
90b9738d
RM		 2224
2225 switch (state[2]) {
2226 case 1:
2227 b43_nphy_rssi_select(dev, 1, 2);
2228 break;
2229 case 4:
2230 b43_nphy_rssi_select(dev, 1, 0);
2231 break;
2232 case 2:
2233 b43_nphy_rssi_select(dev, 1, 1);
2234 break;
2235 default:
2236 b43_nphy_rssi_select(dev, 1, 1);
2237 break;
2238 }
2239
2240 switch (state[3]) {
2241 case 1:
2242 b43_nphy_rssi_select(dev, 2, 2);
2243 break;
2244 case 4:
2245 b43_nphy_rssi_select(dev, 2, 0);
2246 break;
2247 default:
2248 b43_nphy_rssi_select(dev, 2, 1);
2249 break;
2250 }
2251
2252 b43_nphy_rssi_select(dev, 0, type);
2253
2254 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2255 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2256 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2257 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2258
2259 b43_nphy_classifier(dev, 7, class);
2260 b43_nphy_write_clip_detection(dev, clip_state);
8c1d5a7a
RM		 2261 /* Specs don't say about reset here, but it makes wl and b43 dumps
2262 identical, it really seems wl performs this */
2263 b43_nphy_reset_cca(dev);
4cb99775
RM		 2264}
2265
2266/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2267static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2268{
2269 /* TODO */
2270}
2271
2272/*
2273 * RSSI Calibration
2274 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2275 */
2276static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2277{
2278 if (dev->phy.rev >= 3) {
2279 b43_nphy_rev3_rssi_cal(dev);
2280 } else {
76b002bd
RM		 2281 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2282 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2283 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
4cb99775 2284 }
95b66bad
MB		 2285}
2286
42e1547e
RM		 2287/*
2288 * Restore RSSI Calibration
2289 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2290 */
2291static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2292{
2293 struct b43_phy_n *nphy = dev->phy.n;
2294
2295 u16 *rssical_radio_regs = NULL;
2296 u16 *rssical_phy_regs = NULL;
2297
2298 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2299 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 2300 return;
2301 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2302 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2303 } else {
204a665b 2304 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 2305 return;
2306 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2307 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2308 }
2309
2310 /* TODO use some definitions */
2311 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2312 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2313
2314 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2315 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2316 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2317 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2318
2319 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2320 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2321 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2322 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2323
2324 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2325 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2326 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2327 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2328}
2329
2f258b74
RM		 2330/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2331static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2332{
2333 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2334 if (dev->phy.rev >= 6) {
2335 /* TODO If the chip is 47162
2336 return txpwrctrl_tx_gain_ipa_rev5 */
2337 return txpwrctrl_tx_gain_ipa_rev6;
2338 } else if (dev->phy.rev >= 5) {
2339 return txpwrctrl_tx_gain_ipa_rev5;
2340 } else {
2341 return txpwrctrl_tx_gain_ipa;
2342 }
2343 } else {
2344 return txpwrctrl_tx_gain_ipa_5g;
2345 }
2346}
2347
c4a92003
RM		 2348/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2349static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2350{
2351 struct b43_phy_n *nphy = dev->phy.n;
2352 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2353 u16 tmp;
2354 u8 offset, i;
c4a92003
RM		 2355
2356 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2357 for (i = 0; i < 2; i++) {
2358 tmp = (i == 0) ? 0x2000 : 0x3000;
2359 offset = i * 11;
2360
2361 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2362 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2363 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2364 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2365 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2366 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2367 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2368 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2369 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2370 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2371 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2372
2373 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2374 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2375 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2376 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2377 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2378 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2379 if (nphy->ipa5g_on) {
2380 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2381 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2382 } else {
2383 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2384 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2385 }
2386 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2387 } else {
2388 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2389 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2390 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2391 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2392 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2393 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2394 if (nphy->ipa2g_on) {
2395 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2396 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2397 (dev->phy.rev < 5) ? 0x11 : 0x01);
2398 } else {
2399 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2400 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2401 }
2402 }
2403 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2404 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2405 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2406 }
c4a92003
RM		 2407 } else {
2408 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2409 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2410
2411 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2412 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2413
2414 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2415 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2416
2417 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2418 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2419
2420 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2421 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2422
2423 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2424 B43_NPHY_BANDCTL_5GHZ)) {
2425 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2426 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2427 } else {
2428 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2429 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2430 }
2431
2432 if (dev->phy.rev < 2) {
2433 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2434 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2435 } else {
2436 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2437 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2438 }
2439 }
2440}
2441
e9762492
RM		 2442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2443static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2444 struct nphy_txgains target,
2445 struct nphy_iqcal_params *params)
2446{
2447 int i, j, indx;
2448 u16 gain;
2449
2450 if (dev->phy.rev >= 3) {
2451 params->txgm = target.txgm[core];
2452 params->pga = target.pga[core];
2453 params->pad = target.pad[core];
2454 params->ipa = target.ipa[core];
2455 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2456 (params->pad << 4) | (params->ipa);
2457 for (j = 0; j < 5; j++)
2458 params->ncorr[j] = 0x79;
2459 } else {
2460 gain = (target.pad[core]) | (target.pga[core] << 4) |
2461 (target.txgm[core] << 8);
2462
2463 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2464 1 : 0;
2465 for (i = 0; i < 9; i++)
2466 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2467 break;
2468 i = min(i, 8);
2469
2470 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2471 params->pga = tbl_iqcal_gainparams[indx][i][2];
2472 params->pad = tbl_iqcal_gainparams[indx][i][3];
2473 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2474 (params->pad << 2);
2475 for (j = 0; j < 4; j++)
2476 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2477 }
2478}
2479
de7ed0c6
RM		 2480/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2481static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2482{
2483 struct b43_phy_n *nphy = dev->phy.n;
2484 int i;
2485 u16 scale, entry;
2486
2487 u16 tmp = nphy->txcal_bbmult;
2488 if (core == 0)
2489 tmp >>= 8;
2490 tmp &= 0xff;
2491
2492 for (i = 0; i < 18; i++) {
2493 scale = (ladder_lo[i].percent * tmp) / 100;
2494 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 2495 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 2496
2497 scale = (ladder_iq[i].percent * tmp) / 100;
2498 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 2499 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 2500 }
2501}
2502
45ca697e
RM		 2503/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2504static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2505{
2506 int i;
2507 for (i = 0; i < 15; i++)
2508 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2509 tbl_tx_filter_coef_rev4[2][i]);
2510}
2511
2512/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2513static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2514{
2515 int i, j;
2516 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 2517 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 2518
2519 for (i = 0; i < 3; i++)
2520 for (j = 0; j < 15; j++)
2521 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2522 tbl_tx_filter_coef_rev4[i][j]);
2523
2524 if (dev->phy.is_40mhz) {
2525 for (j = 0; j < 15; j++)
2526 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2527 tbl_tx_filter_coef_rev4[3][j]);
2528 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2529 for (j = 0; j < 15; j++)
2530 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2531 tbl_tx_filter_coef_rev4[5][j]);
2532 }
2533
2534 if (dev->phy.channel == 14)
2535 for (j = 0; j < 15; j++)
2536 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2537 tbl_tx_filter_coef_rev4[6][j]);
2538}
2539
b0022e15
RM		 2540/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2541static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2542{
2543 struct b43_phy_n *nphy = dev->phy.n;
2544
2545 u16 curr_gain[2];
2546 struct nphy_txgains target;
2547 const u32 *table = NULL;
2548
161d540c 2549 if (!nphy->txpwrctrl) {
b0022e15
RM		 2550 int i;
2551
2552 if (nphy->hang_avoid)
2553 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 2554 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 2555 if (nphy->hang_avoid)
2556 b43_nphy_stay_in_carrier_search(dev, false);
2557
2558 for (i = 0; i < 2; ++i) {
2559 if (dev->phy.rev >= 3) {
2560 target.ipa[i] = curr_gain[i] & 0x000F;
2561 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2562 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2563 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2564 } else {
2565 target.ipa[i] = curr_gain[i] & 0x0003;
2566 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2567 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2568 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2569 }
2570 }
2571 } else {
2572 int i;
2573 u16 index[2];
2574 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2575 B43_NPHY_TXPCTL_STAT_BIDX) >>
2576 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2577 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2578 B43_NPHY_TXPCTL_STAT_BIDX) >>
2579 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2580
2581 for (i = 0; i < 2; ++i) {
2582 if (dev->phy.rev >= 3) {
2583 enum ieee80211_band band =
2584 b43_current_band(dev->wl);
2585
2586 if ((nphy->ipa2g_on &&
2587 band == IEEE80211_BAND_2GHZ) ||
2588 (nphy->ipa5g_on &&
2589 band == IEEE80211_BAND_5GHZ)) {
2590 table = b43_nphy_get_ipa_gain_table(dev);
2591 } else {
2592 if (band == IEEE80211_BAND_5GHZ) {
2593 if (dev->phy.rev == 3)
2594 table = b43_ntab_tx_gain_rev3_5ghz;
2595 else if (dev->phy.rev == 4)
2596 table = b43_ntab_tx_gain_rev4_5ghz;
2597 else
2598 table = b43_ntab_tx_gain_rev5plus_5ghz;
2599 } else {
2600 table = b43_ntab_tx_gain_rev3plus_2ghz;
2601 }
2602 }
2603
2604 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2605 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2606 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2607 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2608 } else {
2609 table = b43_ntab_tx_gain_rev0_1_2;
2610
2611 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2612 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2613 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2614 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2615 }
2616 }
2617 }
2618
2619 return target;
2620}
2621
e53de674
RM		 2622/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2623static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2624{
2625 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2626
2627 if (dev->phy.rev >= 3) {
2628 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2629 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2630 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2631 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2632 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 2633 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2634 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 2635 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2636 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2637 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2638 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2639 b43_nphy_reset_cca(dev);
2640 } else {
2641 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2642 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2643 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 2644 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2645 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 2646 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2647 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2648 }
2649}
2650
2651/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2652static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2653{
2654 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2655 u16 tmp;
2656
2657 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2658 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2659 if (dev->phy.rev >= 3) {
2660 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2661 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2662
2663 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2664 regs[2] = tmp;
2665 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2666
2667 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2668 regs[3] = tmp;
2669 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2670
2671 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 2672 b43_phy_mask(dev, B43_NPHY_BBCFG,
2673 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 2674
c643a66e 2675 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 2676 regs[5] = tmp;
d41a3552 2677 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 2678
2679 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 2680 regs[6] = tmp;
d41a3552 2681 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 2682 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2683 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2684
67cbc3ed
RM		 2685 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2686 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2687 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 2688
2689 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2690 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2691 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2692 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2693 } else {
2694 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2695 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2696 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2697 regs[2] = tmp;
2698 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 2699 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 2700 regs[3] = tmp;
2701 tmp |= 0x2000;
d41a3552 2702 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 2703 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 2704 regs[4] = tmp;
2705 tmp |= 0x2000;
d41a3552 2706 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 2707 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2708 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2709 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2710 tmp = 0x0180;
2711 else
2712 tmp = 0x0120;
2713 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2714 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2715 }
2716}
2717
bbc6dc12
RM		 2718/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2719static void b43_nphy_save_cal(struct b43_wldev *dev)
2720{
2721 struct b43_phy_n *nphy = dev->phy.n;
2722
2723 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2724 u16 *txcal_radio_regs = NULL;
902db91d 2725 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 2726 u16 *table = NULL;
2727
2728 if (nphy->hang_avoid)
2729 b43_nphy_stay_in_carrier_search(dev, 1);
2730
2731 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2732 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2733 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2734 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2735 table = nphy->cal_cache.txcal_coeffs_2G;
2736 } else {
2737 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2738 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2739 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2740 table = nphy->cal_cache.txcal_coeffs_5G;
2741 }
2742
2743 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2744 /* TODO use some definitions */
2745 if (dev->phy.rev >= 3) {
2746 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2747 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2748 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2749 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2750 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2751 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2752 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2753 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2754 } else {
2755 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2756 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2757 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2758 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2759 }
204a665b
RM		 2760 iqcal_chanspec->center_freq = dev->phy.channel_freq;
2761 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 2762 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 2763
2764 if (nphy->hang_avoid)
2765 b43_nphy_stay_in_carrier_search(dev, 0);
2766}
2767
2f258b74
RM		 2768/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2769static void b43_nphy_restore_cal(struct b43_wldev *dev)
2770{
2771 struct b43_phy_n *nphy = dev->phy.n;
2772
2773 u16 coef[4];
2774 u16 *loft = NULL;
2775 u16 *table = NULL;
2776
2777 int i;
2778 u16 *txcal_radio_regs = NULL;
2779 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2780
2781 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2782 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 2783 return;
2784 table = nphy->cal_cache.txcal_coeffs_2G;
2785 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2786 } else {
204a665b 2787 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 2788 return;
2789 table = nphy->cal_cache.txcal_coeffs_5G;
2790 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2791 }
2792
2581b143 2793 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 2794
2795 for (i = 0; i < 4; i++) {
2796 if (dev->phy.rev >= 3)
2797 table[i] = coef[i];
2798 else
2799 coef[i] = 0;
2800 }
2801
2581b143
RM		 2802 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2803 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2804 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 2805
2806 if (dev->phy.rev < 2)
2807 b43_nphy_tx_iq_workaround(dev);
2808
2809 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2810 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2811 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2812 } else {
2813 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2814 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2815 }
2816
2817 /* TODO use some definitions */
2818 if (dev->phy.rev >= 3) {
2819 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2820 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2821 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2822 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2823 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2824 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2825 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2826 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2827 } else {
2828 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2829 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2830 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2831 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2832 }
2833 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2834}
2835
fb43b8e2
RM		 2836/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2837static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2838 struct nphy_txgains target,
2839 bool full, bool mphase)
2840{
2841 struct b43_phy_n *nphy = dev->phy.n;
2842 int i;
2843 int error = 0;
2844 int freq;
2845 bool avoid = false;
2846 u8 length;
2847 u16 tmp, core, type, count, max, numb, last, cmd;
2848 const u16 *table;
2849 bool phy6or5x;
2850
2851 u16 buffer[11];
2852 u16 diq_start = 0;
2853 u16 save[2];
2854 u16 gain[2];
2855 struct nphy_iqcal_params params[2];
2856 bool updated[2] = { };
2857
2858 b43_nphy_stay_in_carrier_search(dev, true);
2859
2860 if (dev->phy.rev >= 4) {
2861 avoid = nphy->hang_avoid;
2862 nphy->hang_avoid = 0;
2863 }
2864
9145834e 2865 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 2866
2867 for (i = 0; i < 2; i++) {
2868 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2869 gain[i] = params[i].cal_gain;
2870 }
2581b143
RM		 2871
2872 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 2873
2874 b43_nphy_tx_cal_radio_setup(dev);
e53de674 2875 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 2876
2877 phy6or5x = dev->phy.rev >= 6 ||
2878 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2879 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2880 if (phy6or5x) {
38bb9029
RM		 2881 if (dev->phy.is_40mhz) {
2882 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2883 tbl_tx_iqlo_cal_loft_ladder_40);
2884 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2885 tbl_tx_iqlo_cal_iqimb_ladder_40);
2886 } else {
2887 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2888 tbl_tx_iqlo_cal_loft_ladder_20);
2889 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2890 tbl_tx_iqlo_cal_iqimb_ladder_20);
2891 }
fb43b8e2
RM		 2892 }
2893
2894 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2895
aa4c7b2a 2896 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 2897 freq = 2500;
2898 else
2899 freq = 5000;
2900
2901 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 2902 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2903 0xFFFF, 0, true, false);
fb43b8e2 2904 else
59af099b 2905 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 2906
2907 if (error == 0) {
2908 if (nphy->mphase_cal_phase_id > 2) {
2909 table = nphy->mphase_txcal_bestcoeffs;
2910 length = 11;
2911 if (dev->phy.rev < 3)
2912 length -= 2;
2913 } else {
2914 if (!full && nphy->txiqlocal_coeffsvalid) {
2915 table = nphy->txiqlocal_bestc;
2916 length = 11;
2917 if (dev->phy.rev < 3)
2918 length -= 2;
2919 } else {
2920 full = true;
2921 if (dev->phy.rev >= 3) {
2922 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2923 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2924 } else {
2925 table = tbl_tx_iqlo_cal_startcoefs;
2926 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2927 }
2928 }
2929 }
2930
2581b143 2931 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 2932
2933 if (full) {
2934 if (dev->phy.rev >= 3)
2935 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2936 else
2937 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2938 } else {
2939 if (dev->phy.rev >= 3)
2940 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2941 else
2942 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2943 }
2944
2945 if (mphase) {
2946 count = nphy->mphase_txcal_cmdidx;
2947 numb = min(max,
2948 (u16)(count + nphy->mphase_txcal_numcmds));
2949 } else {
2950 count = 0;
2951 numb = max;
2952 }
2953
2954 for (; count < numb; count++) {
2955 if (full) {
2956 if (dev->phy.rev >= 3)
2957 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2958 else
2959 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2960 } else {
2961 if (dev->phy.rev >= 3)
2962 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2963 else
2964 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2965 }
2966
2967 core = (cmd & 0x3000) >> 12;
2968 type = (cmd & 0x0F00) >> 8;
2969
2970 if (phy6or5x && updated[core] == 0) {
2971 b43_nphy_update_tx_cal_ladder(dev, core);
2972 updated[core] = 1;
2973 }
2974
2975 tmp = (params[core].ncorr[type] << 8) | 0x66;
2976 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2977
2978 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 2979 buffer[0] = b43_ntab_read(dev,
2980 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 2981 diq_start = buffer[0];
2982 buffer[0] = 0;
d41a3552
RM		 2983 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2984 0);
fb43b8e2
RM		 2985 }
2986
2987 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2988 for (i = 0; i < 2000; i++) {
2989 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2990 if (tmp & 0xC000)
2991 break;
2992 udelay(10);
2993 }
2994
9145834e
RM		 2995 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2996 buffer);
2581b143
RM		 2997 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2998 buffer);
fb43b8e2
RM		 2999
3000 if (type == 1 || type == 3 || type == 4)
3001 buffer[0] = diq_start;
3002 }
3003
3004 if (mphase)
3005 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3006
3007 last = (dev->phy.rev < 3) ? 6 : 7;
3008
3009 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 3010 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 3011 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 3012 if (dev->phy.rev < 3) {
3013 buffer[0] = 0;
3014 buffer[1] = 0;
3015 buffer[2] = 0;
3016 buffer[3] = 0;
3017 }
2581b143
RM		 3018 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3019 buffer);
bc53e512 3020 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 3021 buffer);
3022 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3023 buffer);
3024 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3025 buffer);
fb43b8e2
RM		 3026 length = 11;
3027 if (dev->phy.rev < 3)
3028 length -= 2;
9145834e
RM		 3029 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3030 nphy->txiqlocal_bestc);
fb43b8e2 3031 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 3032 nphy->txiqlocal_chanspec.center_freq =
3033 dev->phy.channel_freq;
3034 nphy->txiqlocal_chanspec.channel_type =
3035 dev->phy.channel_type;
fb43b8e2
RM		 3036 } else {
3037 length = 11;
3038 if (dev->phy.rev < 3)
3039 length -= 2;
9145834e
RM		 3040 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3041 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 3042 }
3043
53ae8e8c 3044 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 3045 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3046 }
3047
e53de674 3048 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 3049 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3050
3051 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3052 b43_nphy_tx_iq_workaround(dev);
3053
3054 if (dev->phy.rev >= 4)
3055 nphy->hang_avoid = avoid;
3056
3057 b43_nphy_stay_in_carrier_search(dev, false);
3058
3059 return error;
3060}
3061
984ff4ff
RM		 3062/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3063static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3064{
3065 struct b43_phy_n *nphy = dev->phy.n;
3066 u8 i;
3067 u16 buffer[7];
3068 bool equal = true;
3069
902db91d 3070 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 3071 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3072 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 3073 return;
3074
3075 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3076 for (i = 0; i < 4; i++) {
3077 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3078 equal = false;
3079 break;
3080 }
3081 }
3082
3083 if (!equal) {
3084 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3085 nphy->txiqlocal_bestc);
3086 for (i = 0; i < 4; i++)
3087 buffer[i] = 0;
3088 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3089 buffer);
3090 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3091 &nphy->txiqlocal_bestc[5]);
3092 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3093 &nphy->txiqlocal_bestc[5]);
3094 }
3095}
3096
15931e31
RM		 3097/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3098static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3099 struct nphy_txgains target, u8 type, bool debug)
3100{
3101 struct b43_phy_n *nphy = dev->phy.n;
3102 int i, j, index;
3103 u8 rfctl[2];
3104 u8 afectl_core;
3105 u16 tmp[6];
c7455cf9 3106 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 3107 u32 real, imag;
3108 enum ieee80211_band band;
3109
3110 u8 use;
3111 u16 cur_hpf;
3112 u16 lna[3] = { 3, 3, 1 };
3113 u16 hpf1[3] = { 7, 2, 0 };
3114 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 3115 u32 power[3] = { };
15931e31
RM		 3116 u16 gain_save[2];
3117 u16 cal_gain[2];
3118 struct nphy_iqcal_params cal_params[2];
3119 struct nphy_iq_est est;
3120 int ret = 0;
3121 bool playtone = true;
3122 int desired = 13;
3123
3124 b43_nphy_stay_in_carrier_search(dev, 1);
3125
3126 if (dev->phy.rev < 2)
984ff4ff 3127 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 3128 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3129 for (i = 0; i < 2; i++) {
3130 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3131 cal_gain[i] = cal_params[i].cal_gain;
3132 }
2581b143 3133 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 3134
3135 for (i = 0; i < 2; i++) {
3136 if (i == 0) {
3137 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3138 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3139 afectl_core = B43_NPHY_AFECTL_C1;
3140 } else {
3141 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3142 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3143 afectl_core = B43_NPHY_AFECTL_C2;
3144 }
3145
3146 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3147 tmp[2] = b43_phy_read(dev, afectl_core);
3148 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3149 tmp[4] = b43_phy_read(dev, rfctl[0]);
3150 tmp[5] = b43_phy_read(dev, rfctl[1]);
3151
3152 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 3153 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 3154 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3155 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3156 (1 - i));
3157 b43_phy_set(dev, afectl_core, 0x0006);
3158 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3159
3160 band = b43_current_band(dev->wl);
3161
3162 if (nphy->rxcalparams & 0xFF000000) {
3163 if (band == IEEE80211_BAND_5GHZ)
3164 b43_phy_write(dev, rfctl[0], 0x140);
3165 else
3166 b43_phy_write(dev, rfctl[0], 0x110);
3167 } else {
3168 if (band == IEEE80211_BAND_5GHZ)
3169 b43_phy_write(dev, rfctl[0], 0x180);
3170 else
3171 b43_phy_write(dev, rfctl[0], 0x120);
3172 }
3173
3174 if (band == IEEE80211_BAND_5GHZ)
3175 b43_phy_write(dev, rfctl[1], 0x148);
3176 else
3177 b43_phy_write(dev, rfctl[1], 0x114);
3178
3179 if (nphy->rxcalparams & 0x10000) {
3180 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3181 (i + 1));
3182 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3183 (2 - i));
3184 }
3185
30115c22 3186 for (j = 0; j < 4; j++) {
15931e31
RM		 3187 if (j < 3) {
3188 cur_lna = lna[j];
3189 cur_hpf1 = hpf1[j];
3190 cur_hpf2 = hpf2[j];
3191 } else {
3192 if (power[1] > 10000) {
3193 use = 1;
3194 cur_hpf = cur_hpf1;
3195 index = 2;
3196 } else {
3197 if (power[0] > 10000) {
3198 use = 1;
3199 cur_hpf = cur_hpf1;
3200 index = 1;
3201 } else {
3202 index = 0;
3203 use = 2;
3204 cur_hpf = cur_hpf2;
3205 }
3206 }
3207 cur_lna = lna[index];
3208 cur_hpf1 = hpf1[index];
3209 cur_hpf2 = hpf2[index];
3210 cur_hpf += desired - hweight32(power[index]);
3211 cur_hpf = clamp_val(cur_hpf, 0, 10);
3212 if (use == 1)
3213 cur_hpf1 = cur_hpf;
3214 else
3215 cur_hpf2 = cur_hpf;
3216 }
3217
3218 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3219 (cur_lna << 2));
75377b24
RM		 3220 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3221 false);
de9a47f9 3222 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3223 b43_nphy_stop_playback(dev);
15931e31
RM		 3224
3225 if (playtone) {
59af099b
RM		 3226 ret = b43_nphy_tx_tone(dev, 4000,
3227 (nphy->rxcalparams & 0xFFFF),
3228 false, false);
15931e31
RM		 3229 playtone = false;
3230 } else {
10a79873
RM		 3231 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3232 false, false);
15931e31
RM		 3233 }
3234
3235 if (ret == 0) {
3236 if (j < 3) {
3237 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3238 false);
3239 if (i == 0) {
3240 real = est.i0_pwr;
3241 imag = est.q0_pwr;
3242 } else {
3243 real = est.i1_pwr;
3244 imag = est.q1_pwr;
3245 }
3246 power[i] = ((real + imag) / 1024) + 1;
3247 } else {
3248 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3249 }
53ae8e8c 3250 b43_nphy_stop_playback(dev);
15931e31
RM		 3251 }
3252
3253 if (ret != 0)
3254 break;
3255 }
3256
3257 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3258 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3259 b43_phy_write(dev, rfctl[1], tmp[5]);
3260 b43_phy_write(dev, rfctl[0], tmp[4]);
3261 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3262 b43_phy_write(dev, afectl_core, tmp[2]);
3263 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3264
3265 if (ret != 0)
3266 break;
3267 }
3268
75377b24 3269 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3270 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3271 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3272
3273 b43_nphy_stay_in_carrier_search(dev, 0);
3274
3275 return ret;
3276}
3277
3278static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3279 struct nphy_txgains target, u8 type, bool debug)
3280{
3281 return -1;
3282}
3283
3284/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3285static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3286 struct nphy_txgains target, u8 type, bool debug)
3287{
3288 if (dev->phy.rev >= 3)
3289 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3290 else
3291 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3292}
3293
d2730b2a
GS		 3294/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3295static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3296{
3297 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3298 if (on)
f61afc29 3299 tmslow |= B43_TMSLOW_MACPHYCLKEN;
d2730b2a 3300 else
f61afc29 3301 tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
d2730b2a
GS		 3302 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3303}
3304
4e687b22
GS		 3305/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3306static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3307{
3308 struct b43_phy *phy = &dev->phy;
3309 struct b43_phy_n *nphy = phy->n;
0b81c23d 3310 /* u16 buf[16]; it's rev3+ */
4e687b22 3311
049fbfee
RM		 3312 nphy->phyrxchain = mask;
3313
4e687b22
GS		 3314 if (0 /* FIXME clk */)
3315 return;
3316
3317 b43_mac_suspend(dev);
3318
3319 if (nphy->hang_avoid)
3320 b43_nphy_stay_in_carrier_search(dev, true);
3321
3322 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3323 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3324
049fbfee 3325 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 3326 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3327 if (dev->phy.rev >= 3) {
3328 /* TODO */
3329 }
3330 } else {
3331 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3332 if (dev->phy.rev >= 3) {
3333 /* TODO */
3334 }
3335 }
3336
3337 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3338
3339 if (nphy->hang_avoid)
3340 b43_nphy_stay_in_carrier_search(dev, false);
3341
3342 b43_mac_enable(dev);
3343}
3344
0988a7a1
RM		 3345/*
3346 * Init N-PHY
3347 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3348 */
424047e6
MB		 3349int b43_phy_initn(struct b43_wldev *dev)
3350{
0988a7a1 3351 struct ssb_bus *bus = dev->dev->bus;
95b66bad 3352 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3353 struct b43_phy_n *nphy = phy->n;
3354 u8 tx_pwr_state;
3355 struct nphy_txgains target;
95b66bad 3356 u16 tmp;
0988a7a1
RM		 3357 enum ieee80211_band tmp2;
3358 bool do_rssi_cal;
3359
3360 u16 clip[2];
3361 bool do_cal = false;
95b66bad 3362
0988a7a1
RM		 3363 if ((dev->phy.rev >= 3) &&
3364 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3365 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3366 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3367 }
3368 nphy->deaf_count = 0;
95b66bad 3369 b43_nphy_tables_init(dev);
0988a7a1
RM		 3370 nphy->crsminpwr_adjusted = false;
3371 nphy->noisevars_adjusted = false;
95b66bad
MB		 3372
3373 /* Clear all overrides */
0988a7a1
RM		 3374 if (dev->phy.rev >= 3) {
3375 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3376 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3377 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3378 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3379 } else {
3380 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3381 }
95b66bad
MB		 3382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3383 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3384 if (dev->phy.rev < 6) {
3385 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3386 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3387 }
95b66bad
MB		 3388 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3389 ~(B43_NPHY_RFSEQMODE_CAOVER |
3390 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3391 if (dev->phy.rev >= 3)
3392 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3393 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3394
0988a7a1
RM		 3395 if (dev->phy.rev <= 2) {
3396 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3397 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3398 ~B43_NPHY_BPHY_CTL3_SCALE,
3399 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3400 }
95b66bad
MB		 3401 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3402 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3403
0988a7a1
RM		 3404 if (bus->sprom.boardflags2_lo & 0x100 ||
3405 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3406 bus->boardinfo.type == 0x8B))
3407 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3408 else
3409 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3410 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3411 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3412 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3413
ad9716e8 3414 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3415 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3416
3417 if (phy->rev < 2) {
3418 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3419 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3420 }
0988a7a1
RM		 3421
3422 tmp2 = b43_current_band(dev->wl);
3423 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3424 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3425 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3426 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3427 nphy->papd_epsilon_offset[0] << 7);
3428 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3429 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3430 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3431 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3432 } else if (phy->rev >= 5) {
45ca697e 3433 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3434 }
3435
95b66bad 3436 b43_nphy_workarounds(dev);
95b66bad 3437
0988a7a1 3438 /* Reset CCA, in init code it differs a little from standard way */
730dd705 3439 b43_nphy_bmac_clock_fgc(dev, 1);
0988a7a1
RM		 3440 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3441 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3442 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
730dd705 3443 b43_nphy_bmac_clock_fgc(dev, 0);
0988a7a1 3444
d2730b2a 3445 b43_nphy_mac_phy_clock_set(dev, true);
0988a7a1 3446
e50cbcf6 3447 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3448 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3449 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3450 b43_nphy_pa_override(dev, true);
0988a7a1 3451
bbec398c
RM		 3452 b43_nphy_classifier(dev, 0, 0);
3453 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 3454 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3455 b43_nphy_bphy_init(dev);
3456
0988a7a1 3457 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 3458 b43_nphy_tx_power_ctrl(dev, false);
3459 b43_nphy_tx_power_fix(dev);
0988a7a1
RM		 3460 /* TODO N PHY TX Power Control Idle TSSI */
3461 /* TODO N PHY TX Power Control Setup */
3462
3463 if (phy->rev >= 3) {
3464 /* TODO */
3465 } else {
2581b143
RM		 3466 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3467 b43_ntab_tx_gain_rev0_1_2);
3468 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3469 b43_ntab_tx_gain_rev0_1_2);
0988a7a1 3470 }
95b66bad 3471
0988a7a1 3472 if (nphy->phyrxchain != 3)
4e687b22 3473 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 3474 if (nphy->mphase_cal_phase_id > 0)
3475 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3476
3477 do_rssi_cal = false;
3478 if (phy->rev >= 3) {
3479 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3480 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 3481 else
204a665b 3482 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 3483
3484 if (do_rssi_cal)
4cb99775 3485 b43_nphy_rssi_cal(dev);
0988a7a1 3486 else
42e1547e 3487 b43_nphy_restore_rssi_cal(dev);
0988a7a1 3488 } else {
4cb99775 3489 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3490 }
3491
3492 if (!((nphy->measure_hold & 0x6) != 0)) {
3493 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3494 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 3495 else
204a665b 3496 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 3497
3498 if (nphy->mute)
3499 do_cal = false;
3500
3501 if (do_cal) {
b0022e15 3502 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 3503
3504 if (nphy->antsel_type == 2)
8987a9e9 3505 b43_nphy_superswitch_init(dev, true);
0988a7a1 3506 if (nphy->perical != 2) {
90b9738d 3507 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3508 if (phy->rev >= 3) {
3509 nphy->cal_orig_pwr_idx[0] =
3510 nphy->txpwrindex[0].index_internal;
3511 nphy->cal_orig_pwr_idx[1] =
3512 nphy->txpwrindex[1].index_internal;
3513 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 3514 target = b43_nphy_get_tx_gains(dev);
0988a7a1 3515 }
e7797bf2
RM		 3516 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3517 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3518 b43_nphy_save_cal(dev);
3519 } else if (nphy->mphase_cal_phase_id == 0)
3520 ;/* N PHY Periodic Calibration with arg 3 */
3521 } else {
3522 b43_nphy_restore_cal(dev);
0988a7a1
RM		 3523 }
3524 }
3525
6dcd9d91 3526 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 3527 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 3528 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3529 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3530 if (phy->rev >= 3 && phy->rev <= 6)
3531 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 3532 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 3533 if (phy->rev >= 3)
3534 b43_nphy_spur_workaround(dev);
95b66bad 3535
53a6e234 3536 return 0;
424047e6 3537}
ef1a628d 3538
1b69ec7b 3539/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 3540static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 3541 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 3542 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 3543{
3544 struct b43_phy *phy = &dev->phy;
3545 struct b43_phy_n *nphy = dev->phy.n;
3546
087de74a 3547 u16 old_band_5ghz;
1b69ec7b
RM		 3548 u32 tmp32;
3549
087de74a
RM		 3550 old_band_5ghz =
3551 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3552 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 3553 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3554 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3555 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3556 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3557 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 3558 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 3559 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3560 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3561 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 3562 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 3563 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3564 }
3565
3566 b43_chantab_phy_upload(dev, e);
3567
a656b6a9 3568 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 3569 b43_nphy_classifier(dev, 2, 0);
3570 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3571 } else {
3572 b43_nphy_classifier(dev, 2, 2);
a656b6a9 3573 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 3574 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3575 }
3576
161d540c 3577 if (!nphy->txpwrctrl)
1b69ec7b
RM		 3578 b43_nphy_tx_power_fix(dev);
3579
3580 if (dev->phy.rev < 3)
3581 b43_nphy_adjust_lna_gain_table(dev);
3582
3583 b43_nphy_tx_lp_fbw(dev);
3584
3585 if (dev->phy.rev >= 3 && 0) {
3586 /* TODO */
3587 }
3588
3589 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3590
3591 if (phy->rev >= 3)
3592 b43_nphy_spur_workaround(dev);
3593}
3594
eff66c51 3595/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 3596static int b43_nphy_set_channel(struct b43_wldev *dev,
3597 struct ieee80211_channel *channel,
3598 enum nl80211_channel_type channel_type)
eff66c51 3599{
a656b6a9 3600 struct b43_phy *phy = &dev->phy;
eff66c51 3601
f19ebe7d
RM		 3602 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3603 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
eff66c51
RM		 3604
3605 u8 tmp;
eff66c51
RM		 3606
3607 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 3608 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3609 channel->center_freq);
f19ebe7d
RM		 3610 tabent_r3 = NULL;
3611 if (!tabent_r3)
3612 return -ESRCH;
ffd2d9bd 3613 } else {
a656b6a9
RM		 3614 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3615 channel->hw_value);
f19ebe7d 3616 if (!tabent_r2)
ffd2d9bd 3617 return -ESRCH;
eff66c51
RM		 3618 }
3619
204a665b
RM		 3620 /* Channel is set later in common code, but we need to set it on our
3621 own to let this function's subcalls work properly. */
3622 phy->channel = channel->hw_value;
3623 phy->channel_freq = channel->center_freq;
eff66c51 3624
e5c407f9
RM		 3625 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3626 b43_channel_type_is_40mhz(channel_type))
3627 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 3628
a656b6a9
RM		 3629 if (channel_type == NL80211_CHAN_HT40PLUS)
3630 b43_phy_set(dev, B43_NPHY_RXCTL,
3631 B43_NPHY_RXCTL_BSELU20);
3632 else if (channel_type == NL80211_CHAN_HT40MINUS)
3633 b43_phy_mask(dev, B43_NPHY_RXCTL,
3634 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 3635
3636 if (dev->phy.rev >= 3) {
a656b6a9 3637 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 3638 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
f19ebe7d 3639 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
a656b6a9 3640 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 3641 } else {
a656b6a9 3642 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 3643 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 3644 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 3645 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 3646 }
3647
3648 return 0;
3649}
3650
ef1a628d
MB		 3651static int b43_nphy_op_allocate(struct b43_wldev *dev)
3652{
3653 struct b43_phy_n *nphy;
3654
3655 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3656 if (!nphy)
3657 return -ENOMEM;
3658 dev->phy.n = nphy;
3659
ef1a628d
MB		 3660 return 0;
3661}
3662
fb11137a 3663static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 3664{
fb11137a
MB		 3665 struct b43_phy *phy = &dev->phy;
3666 struct b43_phy_n *nphy = phy->n;
ef1a628d 3667
fb11137a 3668 memset(nphy, 0, sizeof(*nphy));
ef1a628d 3669
0b81c23d
RM		 3670 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3671 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3672 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 3673 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
ef1a628d
MB		 3674}
3675
fb11137a 3676static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 3677{
fb11137a
MB		 3678 struct b43_phy *phy = &dev->phy;
3679 struct b43_phy_n *nphy = phy->n;
ef1a628d 3680
ef1a628d 3681 kfree(nphy);
fb11137a
MB		 3682 phy->n = NULL;
3683}
3684
3685static int b43_nphy_op_init(struct b43_wldev *dev)
3686{
3687 return b43_phy_initn(dev);
ef1a628d
MB		 3688}
3689
3690static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3691{
3692#if B43_DEBUG
3693 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3694 /* OFDM registers are onnly available on A/G-PHYs */
3695 b43err(dev->wl, "Invalid OFDM PHY access at "
3696 "0x%04X on N-PHY\n", offset);
3697 dump_stack();
3698 }
3699 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3700 /* Ext-G registers are only available on G-PHYs */
3701 b43err(dev->wl, "Invalid EXT-G PHY access at "
3702 "0x%04X on N-PHY\n", offset);
3703 dump_stack();
3704 }
3705#endif /* B43_DEBUG */
3706}
3707
3708static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3709{
3710 check_phyreg(dev, reg);
3711 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3712 return b43_read16(dev, B43_MMIO_PHY_DATA);
3713}
3714
3715static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3716{
3717 check_phyreg(dev, reg);
3718 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3719 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3720}
3721
755fd183
RM		 3722static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3723 u16 set)
3724{
3725 check_phyreg(dev, reg);
3726 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3727 b43_write16(dev, B43_MMIO_PHY_DATA,
3728 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3729}
3730
ef1a628d
MB		 3731static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3732{
3733 /* Register 1 is a 32-bit register. */
3734 B43_WARN_ON(reg == 1);
3735 /* N-PHY needs 0x100 for read access */
3736 reg |= 0x100;
3737
3738 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3739 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3740}
3741
3742static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3743{
3744 /* Register 1 is a 32-bit register. */
3745 B43_WARN_ON(reg == 1);
3746
3747 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3748 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3749}
3750
c2b7aefd 3751/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 3752static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 3753 bool blocked)
c2b7aefd
RM		 3754{
3755 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3756 b43err(dev->wl, "MAC not suspended\n");
3757
3758 if (blocked) {
3759 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3760 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3761 if (dev->phy.rev >= 3) {
3762 b43_radio_mask(dev, 0x09, ~0x2);
3763
3764 b43_radio_write(dev, 0x204D, 0);
3765 b43_radio_write(dev, 0x2053, 0);
3766 b43_radio_write(dev, 0x2058, 0);
3767 b43_radio_write(dev, 0x205E, 0);
3768 b43_radio_mask(dev, 0x2062, ~0xF0);
3769 b43_radio_write(dev, 0x2064, 0);
3770
3771 b43_radio_write(dev, 0x304D, 0);
3772 b43_radio_write(dev, 0x3053, 0);
3773 b43_radio_write(dev, 0x3058, 0);
3774 b43_radio_write(dev, 0x305E, 0);
3775 b43_radio_mask(dev, 0x3062, ~0xF0);
3776 b43_radio_write(dev, 0x3064, 0);
3777 }
3778 } else {
3779 if (dev->phy.rev >= 3) {
d817f4e1 3780 b43_radio_init2056(dev);
78159788 3781 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 3782 } else {
3783 b43_radio_init2055(dev);
3784 }
3785 }
ef1a628d
MB		 3786}
3787
cb24f57f
MB		 3788static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3789{
3790 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3791 on ? 0 : 0x7FFF);
3792}
3793
ef1a628d
MB		 3794static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3795 unsigned int new_channel)
3796{
a656b6a9
RM		 3797 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3798 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 3799
ef1a628d
MB		 3800 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3801 if ((new_channel < 1) || (new_channel > 14))
3802 return -EINVAL;
3803 } else {
3804 if (new_channel > 200)
3805 return -EINVAL;
3806 }
3807
a656b6a9 3808 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 3809}
3810
3811static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3812{
3813 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3814 return 1;
3815 return 36;
3816}
3817
ef1a628d
MB		 3818const struct b43_phy_operations b43_phyops_n = {
3819 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 3820 .free = b43_nphy_op_free,
3821 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 3822 .init = b43_nphy_op_init,
ef1a628d
MB		 3823 .phy_read = b43_nphy_op_read,
3824 .phy_write = b43_nphy_op_write,
755fd183 3825 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 3826 .radio_read = b43_nphy_op_radio_read,
3827 .radio_write = b43_nphy_op_radio_write,
3828 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 3829 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 3830 .switch_channel = b43_nphy_op_switch_channel,
3831 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 3832 .recalc_txpower = b43_nphy_op_recalc_txpower,
3833 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 3834};
Linux kernel - Deliverables
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