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b43: N-PHY: implement RX IQ coeffs
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
53a6e234
MB		 58void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
59{//TODO
60}
61
18c8adeb 62static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 63{//TODO
64}
65
18c8adeb
MB		 66static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
67 bool ignore_tssi)
68{//TODO
69 return B43_TXPWR_RES_DONE;
70}
71
d1591314
MB		 72static void b43_chantab_radio_upload(struct b43_wldev *dev,
73 const struct b43_nphy_channeltab_entry *e)
74{
75 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
76 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
77 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
78 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
79 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
80 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
81 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
82 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
83 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
84 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
85 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
86 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
87 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
88 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
89 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
90 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
91 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
92 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
93 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
94 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
95 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
96 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
97}
98
99static void b43_chantab_phy_upload(struct b43_wldev *dev,
100 const struct b43_nphy_channeltab_entry *e)
101{
102 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
103 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
104 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
105 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
106 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
107 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
108}
109
110static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
111{
112 //TODO
113}
114
ef1a628d
MB		 115/* Tune the hardware to a new channel. */
116static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 117{
d1591314
MB		 118 const struct b43_nphy_channeltab_entry *tabent;
119
120 tabent = b43_nphy_get_chantabent(dev, channel);
121 if (!tabent)
122 return -ESRCH;
123
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
127 else
128 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev, tabent);
130 udelay(50);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
133 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
134 udelay(300);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
137 else
138 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
139 b43_chantab_phy_upload(dev, tabent);
140 b43_nphy_tx_power_fix(dev);
53a6e234 141
d1591314 142 return 0;
53a6e234
MB		 143}
144
145static void b43_radio_init2055_pre(struct b43_wldev *dev)
146{
147 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE);
149 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
150 B43_NPHY_RFCTL_CMD_CHIP0PU |
151 B43_NPHY_RFCTL_CMD_OEPORFORCE);
152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
153 B43_NPHY_RFCTL_CMD_PORFORCE);
154}
155
156static void b43_radio_init2055_post(struct b43_wldev *dev)
157{
158 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
159 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
160 int i;
161 u16 val;
162
163 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
164 msleep(1);
738f0f43
GS		 165 if ((sprom->revision != 4) ||
166 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 167 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
168 (binfo->type != 0x46D) ||
169 (binfo->rev < 0x41)) {
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
172 msleep(1);
173 }
174 }
175 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
176 msleep(1);
177 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
178 msleep(1);
179 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
180 msleep(1);
181 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
182 msleep(1);
183 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
184 msleep(1);
185 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
186 msleep(1);
187 for (i = 0; i < 100; i++) {
188 val = b43_radio_read16(dev, B2055_CAL_COUT2);
189 if (val & 0x80)
190 break;
191 udelay(10);
192 }
193 msleep(1);
194 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
195 msleep(1);
ef1a628d 196 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 197 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
199 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
200 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
201}
202
203/* Initialize a Broadcom 2055 N-radio */
204static void b43_radio_init2055(struct b43_wldev *dev)
205{
206 b43_radio_init2055_pre(dev);
207 if (b43_status(dev) < B43_STAT_INITIALIZED)
208 b2055_upload_inittab(dev, 0, 1);
209 else
210 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev);
212}
213
214void b43_nphy_radio_turn_on(struct b43_wldev *dev)
215{
216 b43_radio_init2055(dev);
217}
218
219void b43_nphy_radio_turn_off(struct b43_wldev *dev)
220{
221 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
222 ~B43_NPHY_RFCTL_CMD_EN);
223}
224
95b66bad
MB		 225#define ntab_upload(dev, offset, data) do { \
226 unsigned int i; \
227 for (i = 0; i < (offset##_SIZE); i++) \
228 b43_ntab_write(dev, (offset) + i, (data)[i]); \
229 } while (0)
230
4772ae10
RM		 231/*
232 * Upload the N-PHY tables.
233 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
234 */
95b66bad
MB		 235static void b43_nphy_tables_init(struct b43_wldev *dev)
236{
4772ae10
RM		 237 if (dev->phy.rev < 3)
238 b43_nphy_rev0_1_2_tables_init(dev);
239 else
240 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 241}
242
243static void b43_nphy_workarounds(struct b43_wldev *dev)
244{
245 struct b43_phy *phy = &dev->phy;
246 unsigned int i;
247
248 b43_phy_set(dev, B43_NPHY_IQFLIP,
249 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 250 if (1 /* FIXME band is 2.4GHz */) {
251 b43_phy_set(dev, B43_NPHY_CLASSCTL,
252 B43_NPHY_CLASSCTL_CCKEN);
253 } else {
254 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
255 ~B43_NPHY_CLASSCTL_CCKEN);
256 }
257 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
258 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
259
260 /* Fixup some tables */
261 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
271
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
275 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
276
277 //TODO set RF sequence
278
279 /* Set narrowband clip threshold */
280 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
281 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
282
283 /* Set wideband clip 2 threshold */
284 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
285 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
287 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
288 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
289 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
290
291 /* Set Clip 2 detect */
292 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
293 B43_NPHY_C1_CGAINI_CL2DETECT);
294 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
295 B43_NPHY_C2_CGAINI_CL2DETECT);
296
297 if (0 /*FIXME*/) {
298 /* Set dwell lengths */
299 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
301 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
302 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
303
304 /* Set gain backoff */
305 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
306 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
308 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
309 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
310 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
311
312 /* Set HPVGA2 index */
313 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
314 ~B43_NPHY_C1_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
316 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
317 ~B43_NPHY_C2_INITGAIN_HPVGA2,
318 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
319
320 //FIXME verify that the specs really mean to use autoinc here.
321 for (i = 0; i < 3; i++)
322 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
323 }
324
325 /* Set minimum gain value */
326 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
327 ~B43_NPHY_C1_MINGAIN,
328 23 << B43_NPHY_C1_MINGAIN_SHIFT);
329 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
330 ~B43_NPHY_C2_MINGAIN,
331 23 << B43_NPHY_C2_MINGAIN_SHIFT);
332
333 if (phy->rev < 2) {
334 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
335 ~B43_NPHY_SCRAM_SIGCTL_SCM);
336 }
337
338 /* Set phase track alpha and beta */
339 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
341 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
344 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
345}
346
e50cbcf6
RM		 347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
348static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
349{
350 struct b43_phy_n *nphy = dev->phy.n;
351 enum ieee80211_band band;
352 u16 tmp;
353
354 if (!enable) {
355 nphy->rfctrl_intc1_save = b43_phy_read(dev,
356 B43_NPHY_RFCTL_INTC1);
357 nphy->rfctrl_intc2_save = b43_phy_read(dev,
358 B43_NPHY_RFCTL_INTC2);
359 band = b43_current_band(dev->wl);
360 if (dev->phy.rev >= 3) {
361 if (band == IEEE80211_BAND_5GHZ)
362 tmp = 0x600;
363 else
364 tmp = 0x480;
365 } else {
366 if (band == IEEE80211_BAND_5GHZ)
367 tmp = 0x180;
368 else
369 tmp = 0x120;
370 }
371 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
372 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
373 } else {
374 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
375 nphy->rfctrl_intc1_save);
376 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
377 nphy->rfctrl_intc2_save);
378 }
379}
380
4a933c85
RM		 381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
382static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
383{
384 u32 tmslow;
385
386 if (dev->phy.type != B43_PHYTYPE_N)
387 return;
388
389 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
390 if (force)
391 tmslow |= SSB_TMSLOW_FGC;
392 else
393 tmslow &= ~SSB_TMSLOW_FGC;
394 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
395}
396
397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 398static void b43_nphy_reset_cca(struct b43_wldev *dev)
399{
400 u16 bbcfg;
401
4a933c85 402 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 403 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 404 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
405 udelay(1);
406 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
407 b43_nphy_bmac_clock_fgc(dev, 0);
408 /* TODO: N PHY Force RF Seq with argument 2 */
95b66bad
MB		 409}
410
a67162ab
RM		 411/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
412static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
413 struct b43_phy_n_iq_comp *pcomp)
414{
415 if (write) {
416 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
417 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
418 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
419 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
420 } else {
421 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
422 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
423 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
424 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
425 }
426}
427
bbec398c
RM		 428/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
429static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
430{
431 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
432 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
433}
434
435/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
436static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
437{
438 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
439 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
440}
441
442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
443static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
444{
445 u16 tmp;
446
447 if (dev->dev->id.revision == 16)
448 b43_mac_suspend(dev);
449
450 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
451 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
452 B43_NPHY_CLASSCTL_WAITEDEN);
453 tmp &= ~mask;
454 tmp |= (val & mask);
455 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
456
457 if (dev->dev->id.revision == 16)
458 b43_mac_enable(dev);
459
460 return tmp;
461}
462
5c1a140a
RM		 463/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
464static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
465{
466 struct b43_phy *phy = &dev->phy;
467 struct b43_phy_n *nphy = phy->n;
468
469 if (enable) {
470 u16 clip[] = { 0xFFFF, 0xFFFF };
471 if (nphy->deaf_count++ == 0) {
472 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
473 b43_nphy_classifier(dev, 0x7, 0);
474 b43_nphy_read_clip_detection(dev, nphy->clip_state);
475 b43_nphy_write_clip_detection(dev, clip);
476 }
477 b43_nphy_reset_cca(dev);
478 } else {
479 if (--nphy->deaf_count == 0) {
480 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
481 b43_nphy_write_clip_detection(dev, nphy->clip_state);
482 }
483 }
484}
485
95b66bad
MB		 486enum b43_nphy_rf_sequence {
487 B43_RFSEQ_RX2TX,
488 B43_RFSEQ_TX2RX,
489 B43_RFSEQ_RESET2RX,
490 B43_RFSEQ_UPDATE_GAINH,
491 B43_RFSEQ_UPDATE_GAINL,
492 B43_RFSEQ_UPDATE_GAINU,
493};
494
495static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
496 enum b43_nphy_rf_sequence seq)
497{
498 static const u16 trigger[] = {
499 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
500 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
501 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
502 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
503 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
504 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
505 };
506 int i;
507
508 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
509
510 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
511 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
512 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
513 for (i = 0; i < 200; i++) {
514 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
515 goto ok;
516 msleep(1);
517 }
518 b43err(dev->wl, "RF sequence status timeout\n");
519ok:
520 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
521 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
522}
523
524static void b43_nphy_bphy_init(struct b43_wldev *dev)
525{
526 unsigned int i;
527 u16 val;
528
529 val = 0x1E1F;
530 for (i = 0; i < 14; i++) {
531 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
532 val -= 0x202;
533 }
534 val = 0x3E3F;
535 for (i = 0; i < 16; i++) {
536 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
537 val -= 0x202;
538 }
539 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
540}
541
3c95627d
RM		 542/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
543static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
544 s8 offset, u8 core, u8 rail, u8 type)
545{
546 u16 tmp;
547 bool core1or5 = (core == 1) || (core == 5);
548 bool core2or5 = (core == 2) || (core == 5);
549
550 offset = clamp_val(offset, -32, 31);
551 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
552
553 if (core1or5 && (rail == 0) && (type == 2))
554 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
555 if (core1or5 && (rail == 1) && (type == 2))
556 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
557 if (core2or5 && (rail == 0) && (type == 2))
558 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
559 if (core2or5 && (rail == 1) && (type == 2))
560 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
561 if (core1or5 && (rail == 0) && (type == 0))
562 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
563 if (core1or5 && (rail == 1) && (type == 0))
564 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
565 if (core2or5 && (rail == 0) && (type == 0))
566 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
567 if (core2or5 && (rail == 1) && (type == 0))
568 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
569 if (core1or5 && (rail == 0) && (type == 1))
570 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
571 if (core1or5 && (rail == 1) && (type == 1))
572 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
573 if (core2or5 && (rail == 0) && (type == 1))
574 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
575 if (core2or5 && (rail == 1) && (type == 1))
576 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
577 if (core1or5 && (rail == 0) && (type == 6))
578 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
579 if (core1or5 && (rail == 1) && (type == 6))
580 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
581 if (core2or5 && (rail == 0) && (type == 6))
582 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
583 if (core2or5 && (rail == 1) && (type == 6))
584 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
585 if (core1or5 && (rail == 0) && (type == 3))
586 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
587 if (core1or5 && (rail == 1) && (type == 3))
588 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
589 if (core2or5 && (rail == 0) && (type == 3))
590 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
591 if (core2or5 && (rail == 1) && (type == 3))
592 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
593 if (core1or5 && (type == 4))
594 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
595 if (core2or5 && (type == 4))
596 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
597 if (core1or5 && (type == 5))
598 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
599 if (core2or5 && (type == 5))
600 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
601}
602
603/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
604static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
605{
606 u16 val;
607
608 if (dev->phy.rev >= 3) {
609 /* TODO */
610 } else {
611 if (type < 3)
612 val = 0;
613 else if (type == 6)
614 val = 1;
615 else if (type == 3)
616 val = 2;
617 else
618 val = 3;
619
620 val = (val << 12) | (val << 14);
621 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
622 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
623
624 if (type < 3) {
625 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
626 (type + 1) << 4);
627 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
628 (type + 1) << 4);
629 }
630
631 /* TODO use some definitions */
632 if (code == 0) {
633 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
634 if (type < 3) {
635 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
636 0xFEC7, 0);
637 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
638 0xEFDC, 0);
639 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
640 0xFFFE, 0);
641 udelay(20);
642 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
643 0xFFFE, 0);
644 }
645 } else {
646 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
647 0x3000);
648 if (type < 3) {
649 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
650 0xFEC7, 0x0180);
651 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
652 0xEFDC, (code << 1 | 0x1021));
653 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
654 0xFFFE, 0x0001);
655 udelay(20);
656 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
657 0xFFFE, 0);
658 }
659 }
660 }
661}
662
dfb4aa5d
RM		 663/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
664static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
665{
666 int i;
667 for (i = 0; i < 2; i++) {
668 if (type == 2) {
669 if (i == 0) {
670 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
671 0xFC, buf[0]);
672 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
673 0xFC, buf[1]);
674 } else {
675 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
676 0xFC, buf[2 * i]);
677 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
678 0xFC, buf[2 * i + 1]);
679 }
680 } else {
681 if (i == 0)
682 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
683 0xF3, buf[0] << 2);
684 else
685 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
686 0xF3, buf[2 * i + 1] << 2);
687 }
688 }
689}
690
691/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
692static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
693 u8 nsamp)
694{
695 int i;
696 int out;
697 u16 save_regs_phy[9];
698 u16 s[2];
699
700 if (dev->phy.rev >= 3) {
701 save_regs_phy[0] = b43_phy_read(dev,
702 B43_NPHY_RFCTL_LUT_TRSW_UP1);
703 save_regs_phy[1] = b43_phy_read(dev,
704 B43_NPHY_RFCTL_LUT_TRSW_UP2);
705 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
706 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
707 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
708 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
709 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
710 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
711 }
712
713 b43_nphy_rssi_select(dev, 5, type);
714
715 if (dev->phy.rev < 2) {
716 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
717 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
718 }
719
720 for (i = 0; i < 4; i++)
721 buf[i] = 0;
722
723 for (i = 0; i < nsamp; i++) {
724 if (dev->phy.rev < 2) {
725 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
726 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
727 } else {
728 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
729 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
730 }
731
732 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
733 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
734 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
735 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
736 }
737 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
738 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
739
740 if (dev->phy.rev < 2)
741 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
742
743 if (dev->phy.rev >= 3) {
744 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
745 save_regs_phy[0]);
746 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
747 save_regs_phy[1]);
748 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
749 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
750 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
751 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
752 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
753 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
754 }
755
756 return out;
757}
758
4cb99775
RM		 759/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
760static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 761{
90b9738d
RM		 762 int i, j;
763 u8 state[4];
764 u8 code, val;
765 u16 class, override;
766 u8 regs_save_radio[2];
767 u16 regs_save_phy[2];
768 s8 offset[4];
769
770 u16 clip_state[2];
771 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
772 s32 results_min[4] = { };
773 u8 vcm_final[4] = { };
774 s32 results[4][4] = { };
775 s32 miniq[4][2] = { };
776
777 if (type == 2) {
778 code = 0;
779 val = 6;
780 } else if (type < 2) {
781 code = 25;
782 val = 4;
783 } else {
784 B43_WARN_ON(1);
785 return;
786 }
787
788 class = b43_nphy_classifier(dev, 0, 0);
789 b43_nphy_classifier(dev, 7, 4);
790 b43_nphy_read_clip_detection(dev, clip_state);
791 b43_nphy_write_clip_detection(dev, clip_off);
792
793 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
794 override = 0x140;
795 else
796 override = 0x110;
797
798 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
799 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
800 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
801 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
802
803 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
804 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
805 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
806 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
807
808 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
809 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
810 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
811 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
812 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
813 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
814
815 b43_nphy_rssi_select(dev, 5, type);
816 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
817 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
818
819 for (i = 0; i < 4; i++) {
820 u8 tmp[4];
821 for (j = 0; j < 4; j++)
822 tmp[j] = i;
823 if (type != 1)
824 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
825 b43_nphy_poll_rssi(dev, type, results[i], 8);
826 if (type < 2)
827 for (j = 0; j < 2; j++)
828 miniq[i][j] = min(results[i][2 * j],
829 results[i][2 * j + 1]);
830 }
831
832 for (i = 0; i < 4; i++) {
833 s32 mind = 40;
834 u8 minvcm = 0;
835 s32 minpoll = 249;
836 s32 curr;
837 for (j = 0; j < 4; j++) {
838 if (type == 2)
839 curr = abs(results[j][i]);
840 else
841 curr = abs(miniq[j][i / 2] - code * 8);
842
843 if (curr < mind) {
844 mind = curr;
845 minvcm = j;
846 }
847
848 if (results[j][i] < minpoll)
849 minpoll = results[j][i];
850 }
851 results_min[i] = minpoll;
852 vcm_final[i] = minvcm;
853 }
854
855 if (type != 1)
856 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
857
858 for (i = 0; i < 4; i++) {
859 offset[i] = (code * 8) - results[vcm_final[i]][i];
860
861 if (offset[i] < 0)
862 offset[i] = -((abs(offset[i]) + 4) / 8);
863 else
864 offset[i] = (offset[i] + 4) / 8;
865
866 if (results_min[i] == 248)
867 offset[i] = code - 32;
868
869 if (i % 2 == 0)
870 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
871 type);
872 else
873 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
874 type);
875 }
876
877 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
878 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
879
880 switch (state[2]) {
881 case 1:
882 b43_nphy_rssi_select(dev, 1, 2);
883 break;
884 case 4:
885 b43_nphy_rssi_select(dev, 1, 0);
886 break;
887 case 2:
888 b43_nphy_rssi_select(dev, 1, 1);
889 break;
890 default:
891 b43_nphy_rssi_select(dev, 1, 1);
892 break;
893 }
894
895 switch (state[3]) {
896 case 1:
897 b43_nphy_rssi_select(dev, 2, 2);
898 break;
899 case 4:
900 b43_nphy_rssi_select(dev, 2, 0);
901 break;
902 default:
903 b43_nphy_rssi_select(dev, 2, 1);
904 break;
905 }
906
907 b43_nphy_rssi_select(dev, 0, type);
908
909 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
910 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
911 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
912 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
913
914 b43_nphy_classifier(dev, 7, class);
915 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 916}
917
918/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
919static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
920{
921 /* TODO */
922}
923
924/*
925 * RSSI Calibration
926 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
927 */
928static void b43_nphy_rssi_cal(struct b43_wldev *dev)
929{
930 if (dev->phy.rev >= 3) {
931 b43_nphy_rev3_rssi_cal(dev);
932 } else {
933 b43_nphy_rev2_rssi_cal(dev, 2);
934 b43_nphy_rev2_rssi_cal(dev, 0);
935 b43_nphy_rev2_rssi_cal(dev, 1);
936 }
95b66bad
MB		 937}
938
42e1547e
RM		 939/*
940 * Restore RSSI Calibration
941 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
942 */
943static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
944{
945 struct b43_phy_n *nphy = dev->phy.n;
946
947 u16 *rssical_radio_regs = NULL;
948 u16 *rssical_phy_regs = NULL;
949
950 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
951 if (!nphy->rssical_chanspec_2G)
952 return;
953 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
954 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
955 } else {
956 if (!nphy->rssical_chanspec_5G)
957 return;
958 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
959 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
960 }
961
962 /* TODO use some definitions */
963 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
964 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
965
966 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
967 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
968 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
969 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
970
971 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
972 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
973 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
974 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
975
976 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
977 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
978 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
979 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
980}
981
0988a7a1
RM		 982/*
983 * Init N-PHY
984 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
985 */
424047e6
MB		 986int b43_phy_initn(struct b43_wldev *dev)
987{
0988a7a1 988 struct ssb_bus *bus = dev->dev->bus;
95b66bad 989 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 990 struct b43_phy_n *nphy = phy->n;
991 u8 tx_pwr_state;
992 struct nphy_txgains target;
95b66bad 993 u16 tmp;
0988a7a1
RM		 994 enum ieee80211_band tmp2;
995 bool do_rssi_cal;
996
997 u16 clip[2];
998 bool do_cal = false;
95b66bad 999
0988a7a1
RM		 1000 if ((dev->phy.rev >= 3) &&
1001 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
1002 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1003 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1004 }
1005 nphy->deaf_count = 0;
95b66bad 1006 b43_nphy_tables_init(dev);
0988a7a1
RM		 1007 nphy->crsminpwr_adjusted = false;
1008 nphy->noisevars_adjusted = false;
95b66bad
MB		 1009
1010 /* Clear all overrides */
0988a7a1
RM		 1011 if (dev->phy.rev >= 3) {
1012 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
1013 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1014 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
1015 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
1016 } else {
1017 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1018 }
95b66bad
MB		 1019 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
1020 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 1021 if (dev->phy.rev < 6) {
1022 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
1023 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
1024 }
95b66bad
MB		 1025 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1026 ~(B43_NPHY_RFSEQMODE_CAOVER |
1027 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 1028 if (dev->phy.rev >= 3)
1029 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 1030 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
1031
0988a7a1
RM		 1032 if (dev->phy.rev <= 2) {
1033 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
1034 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1035 ~B43_NPHY_BPHY_CTL3_SCALE,
1036 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
1037 }
95b66bad
MB		 1038 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
1039 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
1040
0988a7a1
RM		 1041 if (bus->sprom.boardflags2_lo & 0x100 ||
1042 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
1043 bus->boardinfo.type == 0x8B))
1044 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
1045 else
1046 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
1047 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
1048 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
1049 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 1050
0988a7a1
RM		 1051 /* TODO MIMO-Config */
1052 /* TODO Update TX/RX chain */
95b66bad
MB		 1053
1054 if (phy->rev < 2) {
1055 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
1056 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
1057 }
0988a7a1
RM		 1058
1059 tmp2 = b43_current_band(dev->wl);
1060 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
1061 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
1062 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
1063 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
1064 nphy->papd_epsilon_offset[0] << 7);
1065 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
1066 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
1067 nphy->papd_epsilon_offset[1] << 7);
1068 /* TODO N PHY IPA Set TX Dig Filters */
1069 } else if (phy->rev >= 5) {
1070 /* TODO N PHY Ext PA Set TX Dig Filters */
1071 }
1072
95b66bad 1073 b43_nphy_workarounds(dev);
95b66bad 1074
0988a7a1
RM		 1075 /* Reset CCA, in init code it differs a little from standard way */
1076 /* b43_nphy_bmac_clock_fgc(dev, 1); */
1077 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
1078 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
1079 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
1080 /* b43_nphy_bmac_clock_fgc(dev, 0); */
1081
1082 /* TODO N PHY MAC PHY Clock Set with argument 1 */
1083
e50cbcf6 1084 b43_nphy_pa_override(dev, false);
95b66bad
MB		 1085 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1086 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 1087 b43_nphy_pa_override(dev, true);
0988a7a1 1088
bbec398c
RM		 1089 b43_nphy_classifier(dev, 0, 0);
1090 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 1091 tx_pwr_state = nphy->txpwrctrl;
1092 /* TODO N PHY TX power control with argument 0
1093 (turning off power control) */
1094 /* TODO Fix the TX Power Settings */
1095 /* TODO N PHY TX Power Control Idle TSSI */
1096 /* TODO N PHY TX Power Control Setup */
1097
1098 if (phy->rev >= 3) {
1099 /* TODO */
1100 } else {
1101 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1102 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1103 }
95b66bad 1104
0988a7a1
RM		 1105 if (nphy->phyrxchain != 3)
1106 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1107 if (nphy->mphase_cal_phase_id > 0)
1108 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1109
1110 do_rssi_cal = false;
1111 if (phy->rev >= 3) {
1112 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1113 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1114 else
1115 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1116
1117 if (do_rssi_cal)
4cb99775 1118 b43_nphy_rssi_cal(dev);
0988a7a1 1119 else
42e1547e 1120 b43_nphy_restore_rssi_cal(dev);
0988a7a1 1121 } else {
4cb99775 1122 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1123 }
1124
1125 if (!((nphy->measure_hold & 0x6) != 0)) {
1126 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1127 do_cal = (nphy->iqcal_chanspec_2G == 0);
1128 else
1129 do_cal = (nphy->iqcal_chanspec_5G == 0);
1130
1131 if (nphy->mute)
1132 do_cal = false;
1133
1134 if (do_cal) {
1135 /* target = b43_nphy_get_tx_gains(dev); */
1136
1137 if (nphy->antsel_type == 2)
1138 ;/*TODO NPHY Superswitch Init with argument 1*/
1139 if (nphy->perical != 2) {
90b9738d 1140 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1141 if (phy->rev >= 3) {
1142 nphy->cal_orig_pwr_idx[0] =
1143 nphy->txpwrindex[0].index_internal;
1144 nphy->cal_orig_pwr_idx[1] =
1145 nphy->txpwrindex[1].index_internal;
1146 /* TODO N PHY Pre Calibrate TX Gain */
1147 /*target = b43_nphy_get_tx_gains(dev)*/
1148 }
1149 }
1150 }
1151 }
1152
1153 /*
1154 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1155 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1156 Call N PHY Save Cal
1157 else if (nphy->mphase_cal_phase_id == 0)
1158 N PHY Periodic Calibration with argument 3
1159 } else {
1160 b43_nphy_restore_cal(dev);
1161 }
1162 */
1163
1164 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1165 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1166 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1167 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1168 if (phy->rev >= 3 && phy->rev <= 6)
1169 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1170 /* b43_nphy_tx_lp_fbw(dev); */
1171 /* TODO N PHY Spur Workaround */
95b66bad
MB		 1172
1173 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 1174 return 0;
424047e6 1175}
ef1a628d
MB		 1176
1177static int b43_nphy_op_allocate(struct b43_wldev *dev)
1178{
1179 struct b43_phy_n *nphy;
1180
1181 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1182 if (!nphy)
1183 return -ENOMEM;
1184 dev->phy.n = nphy;
1185
ef1a628d
MB		 1186 return 0;
1187}
1188
fb11137a 1189static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 1190{
fb11137a
MB		 1191 struct b43_phy *phy = &dev->phy;
1192 struct b43_phy_n *nphy = phy->n;
ef1a628d 1193
fb11137a 1194 memset(nphy, 0, sizeof(*nphy));
ef1a628d 1195
fb11137a 1196 //TODO init struct b43_phy_n
ef1a628d
MB		 1197}
1198
fb11137a 1199static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 1200{
fb11137a
MB		 1201 struct b43_phy *phy = &dev->phy;
1202 struct b43_phy_n *nphy = phy->n;
ef1a628d 1203
ef1a628d 1204 kfree(nphy);
fb11137a
MB		 1205 phy->n = NULL;
1206}
1207
1208static int b43_nphy_op_init(struct b43_wldev *dev)
1209{
1210 return b43_phy_initn(dev);
ef1a628d
MB		 1211}
1212
1213static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1214{
1215#if B43_DEBUG
1216 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1217 /* OFDM registers are onnly available on A/G-PHYs */
1218 b43err(dev->wl, "Invalid OFDM PHY access at "
1219 "0x%04X on N-PHY\n", offset);
1220 dump_stack();
1221 }
1222 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1223 /* Ext-G registers are only available on G-PHYs */
1224 b43err(dev->wl, "Invalid EXT-G PHY access at "
1225 "0x%04X on N-PHY\n", offset);
1226 dump_stack();
1227 }
1228#endif /* B43_DEBUG */
1229}
1230
1231static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1232{
1233 check_phyreg(dev, reg);
1234 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1235 return b43_read16(dev, B43_MMIO_PHY_DATA);
1236}
1237
1238static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1239{
1240 check_phyreg(dev, reg);
1241 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1242 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1243}
1244
1245static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1246{
1247 /* Register 1 is a 32-bit register. */
1248 B43_WARN_ON(reg == 1);
1249 /* N-PHY needs 0x100 for read access */
1250 reg |= 0x100;
1251
1252 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1253 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1254}
1255
1256static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1257{
1258 /* Register 1 is a 32-bit register. */
1259 B43_WARN_ON(reg == 1);
1260
1261 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1262 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1263}
1264
1265static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1266 bool blocked)
ef1a628d
MB		 1267{//TODO
1268}
1269
cb24f57f
MB		 1270static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1271{
1272 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1273 on ? 0 : 0x7FFF);
1274}
1275
ef1a628d
MB		 1276static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1277 unsigned int new_channel)
1278{
1279 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1280 if ((new_channel < 1) || (new_channel > 14))
1281 return -EINVAL;
1282 } else {
1283 if (new_channel > 200)
1284 return -EINVAL;
1285 }
1286
1287 return nphy_channel_switch(dev, new_channel);
1288}
1289
1290static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1291{
1292 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1293 return 1;
1294 return 36;
1295}
1296
ef1a628d
MB		 1297const struct b43_phy_operations b43_phyops_n = {
1298 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 1299 .free = b43_nphy_op_free,
1300 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 1301 .init = b43_nphy_op_init,
ef1a628d
MB		 1302 .phy_read = b43_nphy_op_read,
1303 .phy_write = b43_nphy_op_write,
1304 .radio_read = b43_nphy_op_radio_read,
1305 .radio_write = b43_nphy_op_radio_write,
1306 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 1307 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 1308 .switch_channel = b43_nphy_op_switch_channel,
1309 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 1310 .recalc_txpower = b43_nphy_op_recalc_txpower,
1311 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 1312};
Linux kernel - Deliverables
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