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b43: PHY: drop is_40mhz (get width info from chandef)
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
4256ba77
RM		 260static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
263{
264 u16 reg, tmp, tmp2, val;
265 int core;
266
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
270 continue;
271
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
273
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
278 break;
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
282
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
286 break;
287 case N_INTC_OVERRIDE_PA:
288 tmp = 0x0030;
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
290 val = value << 5;
291 else
292 val = value << 4;
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
295 break;
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
298 tmp = 0x0001;
299 tmp2 = 0x0004;
300 val = value;
301 } else {
302 tmp = 0x0004;
303 tmp2 = 0x0001;
304 val = value << 2;
305 }
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
308 break;
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
311 tmp = 0x0002;
312 tmp2 = 0x0008;
313 val = value << 1;
314 } else {
315 tmp = 0x0008;
316 tmp2 = 0x0002;
317 val = value << 3;
318 }
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
321 break;
322 }
323 }
324}
325
ab499217 326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 327static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core)
d4814e69 330{
ab499217
RM		 331 u8 i, j;
332 u16 reg, tmp, val;
38646eba 333
4256ba77
RM		 334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
336 core);
337 return;
338 }
339
d4814e69
RM		 340 B43_WARN_ON(dev->phy.rev < 3);
341
ab499217
RM		 342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
344 continue;
38646eba 345
ab499217
RM		 346 reg = (i == 0) ?
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 348 b43_phy_set(dev, reg, 0x400);
38646eba 349
89e43dad
RM		 350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
354 break;
89e43dad 355 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 356 if (!i) {
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
360 0xFFFE, 1);
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
603431e9 364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 365 j = 0;
366 break;
367 }
368 udelay(10);
38646eba 369 }
ab499217
RM		 370 if (j)
371 b43err(dev->wl,
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
374 0xFFFE);
38646eba 375 } else {
ab499217
RM		 376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
379 0xFFFE, 1);
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
603431e9 383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 384 j = 0;
385 break;
386 }
387 udelay(10);
388 }
389 if (j)
390 b43err(dev->wl,
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
393 0xFFFE);
38646eba 394 }
ab499217 395 break;
89e43dad 396 case N_INTC_OVERRIDE_PA:
ab499217
RM		 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
398 tmp = 0x0020;
399 val = value << 5;
400 } else {
401 tmp = 0x0010;
402 val = value << 4;
403 }
404 b43_phy_maskset(dev, reg, ~tmp, val);
405 break;
89e43dad 406 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
408 tmp = 0x0001;
409 val = value;
410 } else {
411 tmp = 0x0004;
412 val = value << 2;
413 }
414 b43_phy_maskset(dev, reg, ~tmp, val);
415 break;
89e43dad 416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
418 tmp = 0x0002;
419 val = value << 1;
420 } else {
421 tmp = 0x0008;
422 val = value << 3;
423 }
424 b43_phy_maskset(dev, reg, ~tmp, val);
425 break;
38646eba 426 }
38646eba 427 }
ab499217 428}
38646eba 429
ab499217
RM		 430/**************************************************
431 * Various PHY ops
432 **************************************************/
433
434/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
436 const u16 *clip_st)
437{
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 440}
441
ab499217
RM		 442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 444{
ab499217
RM		 445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 447}
448
ab499217
RM		 449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 451{
ab499217 452 u16 tmp;
161d540c 453
ab499217
RM		 454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
161d540c 456
ab499217
RM		 457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
460 tmp &= ~mask;
461 tmp |= (val & mask);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 463
ab499217
RM		 464 if (dev->dev->core_rev == 16)
465 b43_mac_enable(dev);
161d540c 466
ab499217
RM		 467 return tmp;
468}
161d540c 469
ab499217
RM		 470/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471static void b43_nphy_reset_cca(struct b43_wldev *dev)
472{
473 u16 bbcfg;
161d540c 474
ab499217
RM		 475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
478 udelay(1);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
482}
161d540c 483
ab499217
RM		 484/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
486{
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
161d540c 489
ab499217
RM		 490 if (enable) {
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
498 }
499 b43_nphy_reset_cca(dev);
161d540c 500 } else {
ab499217
RM		 501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 504 }
161d540c 505 }
161d540c
RM		 506}
507
64712095
RM		 508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 510{
161d540c 511 struct b43_phy_n *nphy = dev->phy.n;
161d540c 512
64712095
RM		 513 u8 i;
514 s16 tmp;
515 u16 data[4];
516 s16 gain[2];
517 u16 minmax[2];
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 519
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
522
64712095 523 if (nphy->gain_boost) {
161d540c 524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 525 gain[0] = 6;
526 gain[1] = 6;
161d540c 527 } else {
64712095
RM		 528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 532 }
64712095
RM		 533 } else {
534 gain[0] = 0;
535 gain[1] = 0;
161d540c 536 }
161d540c
RM		 537
538 for (i = 0; i < 2; i++) {
64712095
RM		 539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
161d540c 544 } else {
64712095
RM		 545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
161d540c 549 }
64712095 550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 551
64712095 552 minmax[i] = 23 + gain[i];
161d540c
RM		 553 }
554
64712095
RM		 555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 559
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 562}
563
ab499217
RM		 564/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
0eff8fcd 567{
ab499217
RM		 568 struct b43_phy_n *nphy = dev->phy.n;
569 u8 i;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
0eff8fcd 573
ab499217
RM		 574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 576
ab499217
RM		 577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 579
ab499217
RM		 580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 583 }
ab499217
RM		 584
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 587}
7955de0c 588
572d37a4
RM		 589/**************************************************
590 * Radio 0x2057
591 **************************************************/
592
593/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
594static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
595{
596 struct b43_phy *phy = &dev->phy;
597 u16 tmp;
598
599 if (phy->radio_rev == 5) {
600 b43_phy_mask(dev, 0x342, ~0x2);
601 udelay(10);
602 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
603 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
604 }
605
606 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
607 udelay(10);
608 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
609 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
610 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
611 return 0;
612 }
613 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
614 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
615 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
616
617 if (phy->radio_rev == 5) {
618 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
619 b43_radio_mask(dev, 0x1ca, ~0x2);
620 }
621 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
622 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
623 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
624 tmp << 2);
625 }
626
627 return tmp & 0x3e;
628}
629
630/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
631static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
632{
633 struct b43_phy *phy = &dev->phy;
634 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
635 phy->radio_rev == 6);
636 u16 tmp;
637
638 if (special) {
639 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
640 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
641 } else {
642 b43_radio_write(dev, 0x1AE, 0x61);
643 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
644 }
645 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
646 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
647 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
648 5000000))
649 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
650 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
651 if (special) {
652 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
653 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
654 } else {
655 b43_radio_write(dev, 0x1AE, 0x69);
656 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
657 }
658 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
659 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
660 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
661 5000000))
6c187236 662 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 663 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
664 if (special) {
665 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
666 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
667 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
668 } else {
669 b43_radio_write(dev, 0x1AE, 0x73);
670 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
671 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
672 }
673 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
674 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
675 5000000)) {
676 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
677 return 0;
678 }
679 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
680 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
681 return tmp;
682}
683
684static void b43_radio_2057_init_pre(struct b43_wldev *dev)
685{
686 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
687 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
688 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
689 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
690 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
691}
692
693static void b43_radio_2057_init_post(struct b43_wldev *dev)
694{
695 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
696
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
698 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
699 mdelay(2);
700 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
701 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
702
90e569d1 703 if (dev->phy.do_full_init) {
572d37a4
RM		 704 b43_radio_2057_rcal(dev);
705 b43_radio_2057_rccal(dev);
706 }
707 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
572d37a4
RM		 708}
709
710/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
711static void b43_radio_2057_init(struct b43_wldev *dev)
712{
713 b43_radio_2057_init_pre(dev);
714 r2057_upload_inittabs(dev);
715 b43_radio_2057_init_post(dev);
716}
717
ab499217 718/**************************************************
884a5228 719 * Radio 0x2056
ab499217 720 **************************************************/
7955de0c 721
d4814e69
RM		 722static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
723 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 724{
d4814e69
RM		 725 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
726 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
727 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
728 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
729 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
730 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
731 e->radio_syn_pll_loopfilter1);
732 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
733 e->radio_syn_pll_loopfilter2);
734 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
735 e->radio_syn_pll_loopfilter3);
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
737 e->radio_syn_pll_loopfilter4);
738 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
739 e->radio_syn_pll_loopfilter5);
740 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
741 e->radio_syn_reserved_addr27);
742 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
743 e->radio_syn_reserved_addr28);
744 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
745 e->radio_syn_reserved_addr29);
746 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
747 e->radio_syn_logen_vcobuf1);
748 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
749 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
750 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
751
752 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
753 e->radio_rx0_lnaa_tune);
754 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
755 e->radio_rx0_lnag_tune);
756
757 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
758 e->radio_tx0_intpaa_boost_tune);
759 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
760 e->radio_tx0_intpag_boost_tune);
761 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
762 e->radio_tx0_pada_boost_tune);
763 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
764 e->radio_tx0_padg_boost_tune);
765 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
766 e->radio_tx0_pgaa_boost_tune);
767 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
768 e->radio_tx0_pgag_boost_tune);
769 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
770 e->radio_tx0_mixa_boost_tune);
771 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
772 e->radio_tx0_mixg_boost_tune);
773
774 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
775 e->radio_rx1_lnaa_tune);
776 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
777 e->radio_rx1_lnag_tune);
778
779 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
780 e->radio_tx1_intpaa_boost_tune);
781 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
782 e->radio_tx1_intpag_boost_tune);
783 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
784 e->radio_tx1_pada_boost_tune);
785 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
786 e->radio_tx1_padg_boost_tune);
787 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
788 e->radio_tx1_pgaa_boost_tune);
789 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
790 e->radio_tx1_pgag_boost_tune);
791 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
792 e->radio_tx1_mixa_boost_tune);
793 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
794 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 795}
796
d4814e69
RM		 797/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
798static void b43_radio_2056_setup(struct b43_wldev *dev,
799 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 800{
39e971ef 801 struct b43_phy *phy = &dev->phy;
0581483a 802 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 803 enum ieee80211_band band = b43_current_band(dev->wl);
804 u16 offset;
805 u8 i;
d3d178f0
RM		 806 u16 bias, cbias;
807 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
808 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 809 bool is_pkg_fab_smic;
036cafe4 810
d4814e69 811 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 812
b88cdde9
RM		 813 is_pkg_fab_smic =
814 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
815 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
816 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
817 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
818
d4814e69 819 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 820 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
821
822 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
823 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
824 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
825 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 826 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
827 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 828 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
829 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
830 } else {
831 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
832 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 833 }
53a6e234 834 }
b88cdde9
RM		 835 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
836 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
837 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
838 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
839 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
840 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
841 }
38646eba
RM		 842 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
843 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
844 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
845 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
846 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
847 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 848 }
53a6e234 849
38646eba
RM		 850 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
851 for (i = 0; i < 2; i++) {
852 offset = i ? B2056_TX1 : B2056_TX0;
853 if (dev->phy.rev >= 5) {
854 b43_radio_write(dev,
855 offset | B2056_TX_PADG_IDAC, 0xcc);
856
b88cdde9
RM		 857 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
858 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 859 bias = 0x40;
860 cbias = 0x45;
861 pag_boost = 0x5;
862 pgag_boost = 0x33;
863 mixg_boost = 0x55;
864 } else {
865 bias = 0x25;
866 cbias = 0x20;
b88cdde9
RM		 867 if (is_pkg_fab_smic) {
868 bias = 0x2a;
869 cbias = 0x38;
870 }
38646eba
RM		 871 pag_boost = 0x4;
872 pgag_boost = 0x03;
873 mixg_boost = 0x65;
874 }
875 padg_boost = 0x77;
876
877 b43_radio_write(dev,
878 offset | B2056_TX_INTPAG_IMAIN_STAT,
879 bias);
880 b43_radio_write(dev,
881 offset | B2056_TX_INTPAG_IAUX_STAT,
882 bias);
883 b43_radio_write(dev,
884 offset | B2056_TX_INTPAG_CASCBIAS,
885 cbias);
886 b43_radio_write(dev,
887 offset | B2056_TX_INTPAG_BOOST_TUNE,
888 pag_boost);
889 b43_radio_write(dev,
890 offset | B2056_TX_PGAG_BOOST_TUNE,
891 pgag_boost);
892 b43_radio_write(dev,
893 offset | B2056_TX_PADG_BOOST_TUNE,
894 padg_boost);
895 b43_radio_write(dev,
896 offset | B2056_TX_MIXG_BOOST_TUNE,
897 mixg_boost);
898 } else {
bee6d4b2 899 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
38646eba
RM		 900 b43_radio_write(dev,
901 offset | B2056_TX_INTPAG_IMAIN_STAT,
902 bias);
903 b43_radio_write(dev,
904 offset | B2056_TX_INTPAG_IAUX_STAT,
905 bias);
906 b43_radio_write(dev,
907 offset | B2056_TX_INTPAG_CASCBIAS,
908 0x30);
909 }
910 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
911 }
912 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
39e971ef 913 u16 freq = phy->chandef->chan->center_freq;
d3d178f0
RM		 914 if (freq < 5100) {
915 paa_boost = 0xA;
916 pada_boost = 0x77;
917 pgaa_boost = 0xF;
918 mixa_boost = 0xF;
919 } else if (freq < 5340) {
920 paa_boost = 0x8;
921 pada_boost = 0x77;
922 pgaa_boost = 0xFB;
923 mixa_boost = 0xF;
924 } else if (freq < 5650) {
925 paa_boost = 0x0;
926 pada_boost = 0x77;
927 pgaa_boost = 0xB;
928 mixa_boost = 0xF;
929 } else {
930 paa_boost = 0x0;
931 pada_boost = 0x77;
932 if (freq != 5825)
933 pgaa_boost = -(freq - 18) / 36 + 168;
934 else
935 pgaa_boost = 6;
936 mixa_boost = 0xF;
937 }
938
b88cdde9
RM		 939 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
940
d3d178f0
RM		 941 for (i = 0; i < 2; i++) {
942 offset = i ? B2056_TX1 : B2056_TX0;
943
944 b43_radio_write(dev,
945 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
946 b43_radio_write(dev,
947 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
948 b43_radio_write(dev,
949 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
950 b43_radio_write(dev,
951 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
952 b43_radio_write(dev,
953 offset | B2056_TX_TXSPARE1, 0x30);
954 b43_radio_write(dev,
955 offset | B2056_TX_PA_SPARE2, 0xee);
956 b43_radio_write(dev,
957 offset | B2056_TX_PADA_CASCBIAS, 0x03);
958 b43_radio_write(dev,
b88cdde9 959 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 960 b43_radio_write(dev,
b88cdde9 961 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 962 b43_radio_write(dev,
b88cdde9 963 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 964 }
a2d9bc6f 965 }
38646eba 966
d4814e69
RM		 967 udelay(50);
968 /* VCO calibration */
969 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
970 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
971 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
972 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
973 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
974 udelay(300);
53a6e234
MB		 975}
976
d3d178f0
RM		 977static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
978{
979 struct b43_phy *phy = &dev->phy;
980 u16 mast2, tmp;
981
982 if (phy->rev != 3)
983 return 0;
984
985 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
986 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
987
988 udelay(10);
989 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
990 udelay(10);
991 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
992
993 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
994 1000000)) {
995 b43err(dev->wl, "Radio recalibration timeout\n");
996 return 0;
997 }
998
999 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1000 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1001 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1002
1003 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1004
1005 return tmp & 0x1f;
1006}
1007
ea7ee14b
RM		 1008static void b43_radio_init2056_pre(struct b43_wldev *dev)
1009{
1010 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1011 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1012 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1013 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1014 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1015 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1016 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1017 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1018 B43_NPHY_RFCTL_CMD_CHIP0PU);
1019}
1020
1021static void b43_radio_init2056_post(struct b43_wldev *dev)
1022{
1023 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1024 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1025 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1026 msleep(1);
1027 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1028 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1029 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
90e569d1 1030 if (dev->phy.do_full_init)
d3d178f0 1031 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1032}
1033
d817f4e1
RM		 1034/*
1035 * Initialize a Broadcom 2056 N-radio
1036 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1037 */
1038static void b43_radio_init2056(struct b43_wldev *dev)
1039{
ea7ee14b
RM		 1040 b43_radio_init2056_pre(dev);
1041 b2056_upload_inittabs(dev, 0, 0);
1042 b43_radio_init2056_post(dev);
d817f4e1
RM		 1043}
1044
884a5228
RM		 1045/**************************************************
1046 * Radio 0x2055
1047 **************************************************/
1048
1049static void b43_chantab_radio_upload(struct b43_wldev *dev,
1050 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1051{
884a5228
RM		 1052 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1053 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1054 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1055 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1056 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1057
884a5228
RM		 1058 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1059 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1060 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1061 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1062 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1063
884a5228
RM		 1064 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1065 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1066 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1067 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1068 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1069
884a5228
RM		 1070 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1071 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1072 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1073 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1074 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1075
884a5228
RM		 1076 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1077 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1078 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1079 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1080 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1081
884a5228
RM		 1082 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1083 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1084}
1085
884a5228
RM		 1086/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1087static void b43_radio_2055_setup(struct b43_wldev *dev,
1088 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1089{
884a5228 1090 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1091
884a5228
RM		 1092 b43_chantab_radio_upload(dev, e);
1093 udelay(50);
1094 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1095 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1096 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1097 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1098 udelay(300);
95b66bad
MB		 1099}
1100
884a5228 1101static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1102{
884a5228
RM		 1103 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1104 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1105 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1106 B43_NPHY_RFCTL_CMD_CHIP0PU |
1107 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1108 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1109 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1110}
1111
884a5228 1112static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1113{
1114 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1115 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1116 bool workaround = false;
2faa6b83 1117
884a5228
RM		 1118 if (sprom->revision < 4)
1119 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1120 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1121 && dev->dev->board_rev >= 0x41);
2faa6b83 1122 else
884a5228
RM		 1123 workaround =
1124 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1125
884a5228
RM		 1126 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1127 if (workaround) {
1128 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1129 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1130 }
1131 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1132 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1133 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1134 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1135 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1136 msleep(1);
1137 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1138 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1139 b43err(dev->wl, "radio post init timeout\n");
1140 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1141 b43_switch_channel(dev, dev->phy.channel);
1142 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1143 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1144 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1145 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1146 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1147 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1148 if (!nphy->gain_boost) {
1149 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1150 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1151 } else {
1152 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1153 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1154 }
1155 udelay(2);
2faa6b83
RM		 1156}
1157
884a5228
RM		 1158/*
1159 * Initialize a Broadcom 2055 N-radio
1160 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1161 */
1162static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1163{
884a5228
RM		 1164 b43_radio_init2055_pre(dev);
1165 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1166 /* Follow wl, not specs. Do not force uploading all regs */
1167 b2055_upload_inittab(dev, 0, 0);
a67162ab 1168 } else {
884a5228
RM		 1169 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1170 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1171 }
884a5228 1172 b43_radio_init2055_post(dev);
a67162ab
RM		 1173}
1174
8be89535
RM		 1175/**************************************************
1176 * Samples
1177 **************************************************/
026816fc 1178
8be89535
RM		 1179/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1180static int b43_nphy_load_samples(struct b43_wldev *dev,
1181 struct b43_c32 *samples, u16 len) {
1182 struct b43_phy_n *nphy = dev->phy.n;
1183 u16 i;
1184 u32 *data;
1185
1186 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1187 if (!data) {
1188 b43err(dev->wl, "allocation for samples loading failed\n");
1189 return -ENOMEM;
1190 }
1191 if (nphy->hang_avoid)
1192 b43_nphy_stay_in_carrier_search(dev, 1);
1193
1194 for (i = 0; i < len; i++) {
1195 data[i] = (samples[i].i & 0x3FF << 10);
1196 data[i] |= samples[i].q & 0x3FF;
1197 }
1198 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1199
1200 kfree(data);
1201 if (nphy->hang_avoid)
1202 b43_nphy_stay_in_carrier_search(dev, 0);
1203 return 0;
026816fc
RM		 1204}
1205
8be89535
RM		 1206/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1207static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1208 bool test)
026816fc 1209{
8be89535
RM		 1210 int i;
1211 u16 bw, len, rot, angle;
1212 struct b43_c32 *samples;
026816fc 1213
bee6d4b2 1214 bw = b43_is_40mhz(dev) ? 40 : 20;
8be89535 1215 len = bw << 3;
026816fc 1216
8be89535
RM		 1217 if (test) {
1218 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1219 bw = 82;
1220 else
1221 bw = 80;
026816fc 1222
bee6d4b2 1223 if (b43_is_40mhz(dev))
8be89535
RM		 1224 bw <<= 1;
1225
1226 len = bw << 1;
026816fc
RM		 1227 }
1228
8be89535
RM		 1229 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1230 if (!samples) {
1231 b43err(dev->wl, "allocation for samples generation failed\n");
1232 return 0;
1233 }
1234 rot = (((freq * 36) / bw) << 16) / 100;
1235 angle = 0;
026816fc 1236
8be89535
RM		 1237 for (i = 0; i < len; i++) {
1238 samples[i] = b43_cordic(angle);
1239 angle += rot;
1240 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1241 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1242 }
8be89535
RM		 1243
1244 i = b43_nphy_load_samples(dev, samples, len);
1245 kfree(samples);
1246 return (i < 0) ? 0 : len;
026816fc
RM		 1247}
1248
8be89535
RM		 1249/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1250static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1251 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1252{
8be89535 1253 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1254 int i;
8be89535
RM		 1255 u16 seq_mode;
1256 u32 tmp;
34a56f2c 1257
bc36e994 1258 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1259
8be89535
RM		 1260 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1261 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1262 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1263 }
34a56f2c 1264
bc36e994 1265 /* TODO: add modify_bbmult argument */
bee6d4b2 1266 if (!b43_is_40mhz(dev))
8be89535
RM		 1267 tmp = 0x6464;
1268 else
1269 tmp = 0x4747;
1270 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1271
8be89535 1272 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1273
8be89535
RM		 1274 if (loops != 0xFFFF)
1275 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1276 else
1277 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1278
8be89535 1279 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1280
8be89535 1281 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1282
8be89535
RM		 1283 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1284 if (iqmode) {
1285 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1286 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1287 } else {
1288 if (dac_test)
1289 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1290 else
1291 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1292 }
1293 for (i = 0; i < 100; i++) {
2c8ac7eb 1294 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1295 i = 0;
1296 break;
34a56f2c 1297 }
8be89535 1298 udelay(10);
34a56f2c 1299 }
8be89535
RM		 1300 if (i)
1301 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1302
8be89535 1303 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1304
1305 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1306}
1307
4d9f46ba
RM		 1308/**************************************************
1309 * RSSI
1310 **************************************************/
1311
1312/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1313static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1314 s8 offset, u8 core,
1315 enum n_rail_type rail,
2a2d0589 1316 enum n_rssi_type rssi_type)
09146400 1317{
4d9f46ba
RM		 1318 u16 tmp;
1319 bool core1or5 = (core == 1) || (core == 5);
1320 bool core2or5 = (core == 2) || (core == 5);
09146400 1321
4d9f46ba
RM		 1322 offset = clamp_val(offset, -32, 31);
1323 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1324
e5ab1fd7 1325 switch (rssi_type) {
2a2d0589 1326 case N_RSSI_NB:
e5ab1fd7
RM		 1327 if (core1or5 && rail == N_RAIL_I)
1328 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1329 if (core1or5 && rail == N_RAIL_Q)
1330 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1331 if (core2or5 && rail == N_RAIL_I)
1332 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1333 if (core2or5 && rail == N_RAIL_Q)
1334 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1335 break;
2a2d0589 1336 case N_RSSI_W1:
e5ab1fd7
RM		 1337 if (core1or5 && rail == N_RAIL_I)
1338 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1339 if (core1or5 && rail == N_RAIL_Q)
1340 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1341 if (core2or5 && rail == N_RAIL_I)
1342 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1343 if (core2or5 && rail == N_RAIL_Q)
1344 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1345 break;
2a2d0589 1346 case N_RSSI_W2:
e5ab1fd7
RM		 1347 if (core1or5 && rail == N_RAIL_I)
1348 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1349 if (core1or5 && rail == N_RAIL_Q)
1350 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1351 if (core2or5 && rail == N_RAIL_I)
1352 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1353 if (core2or5 && rail == N_RAIL_Q)
1354 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1355 break;
2a2d0589 1356 case N_RSSI_TBD:
e5ab1fd7
RM		 1357 if (core1or5 && rail == N_RAIL_I)
1358 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1359 if (core1or5 && rail == N_RAIL_Q)
1360 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1361 if (core2or5 && rail == N_RAIL_I)
1362 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1363 if (core2or5 && rail == N_RAIL_Q)
1364 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1365 break;
2a2d0589 1366 case N_RSSI_IQ:
e5ab1fd7
RM		 1367 if (core1or5 && rail == N_RAIL_I)
1368 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1369 if (core1or5 && rail == N_RAIL_Q)
1370 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1371 if (core2or5 && rail == N_RAIL_I)
1372 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1373 if (core2or5 && rail == N_RAIL_Q)
1374 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1375 break;
2a2d0589 1376 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1377 if (core1or5)
1378 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1379 if (core2or5)
1380 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1381 break;
2a2d0589 1382 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1383 if (core1or5)
1384 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1385 if (core2or5)
1386 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1387 break;
1388 }
8987a9e9
RM		 1389}
1390
a3764ef7
RM		 1391static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1392 enum n_rssi_type rssi_type)
bbec398c 1393{
4d9f46ba
RM		 1394 u8 i;
1395 u16 reg, val;
bbec398c 1396
4d9f46ba
RM		 1397 if (code == 0) {
1398 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1399 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1400 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1401 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1402 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1403 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1404 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1405 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1406 } else {
1407 for (i = 0; i < 2; i++) {
1408 if ((code == 1 && i == 1) || (code == 2 && !i))
1409 continue;
bbec398c 1410
4d9f46ba
RM		 1411 reg = (i == 0) ?
1412 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1413 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1414
a3764ef7
RM		 1415 if (rssi_type == N_RSSI_W1 ||
1416 rssi_type == N_RSSI_W2 ||
1417 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1418 reg = (i == 0) ?
1419 B43_NPHY_AFECTL_C1 :
1420 B43_NPHY_AFECTL_C2;
1421 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1422
4d9f46ba
RM		 1423 reg = (i == 0) ?
1424 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1425 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1426 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1427
a3764ef7 1428 if (rssi_type == N_RSSI_W1)
4d9f46ba 1429 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1430 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1431 val = 16;
1432 else
1433 val = 32;
1434 b43_phy_set(dev, reg, val);
5c1a140a 1435
4d9f46ba
RM		 1436 reg = (i == 0) ?
1437 B43_NPHY_TXF_40CO_B1S0 :
1438 B43_NPHY_TXF_40CO_B32S1;
1439 b43_phy_set(dev, reg, 0x0020);
1440 } else {
a3764ef7 1441 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1442 val = 0x0100;
a3764ef7 1443 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1444 val = 0x0200;
1445 else
1446 val = 0x0300;
5c1a140a 1447
4d9f46ba
RM		 1448 reg = (i == 0) ?
1449 B43_NPHY_AFECTL_C1 :
1450 B43_NPHY_AFECTL_C2;
53ae8e8c 1451
4d9f46ba
RM		 1452 b43_phy_maskset(dev, reg, 0xFCFF, val);
1453 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1454
a3764ef7
RM		 1455 if (rssi_type != N_RSSI_IQ &&
1456 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1457 enum ieee80211_band band =
1458 b43_current_band(dev->wl);
53ae8e8c 1459
4d9f46ba
RM		 1460 if (b43_nphy_ipa(dev))
1461 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1462 else
1463 val = 0x11;
1464 reg = (i == 0) ? 0x2000 : 0x3000;
1465 reg |= B2055_PADDRV;
0c201cfb 1466 b43_radio_write(dev, reg, val);
53ae8e8c 1467
4d9f46ba
RM		 1468 reg = (i == 0) ?
1469 B43_NPHY_AFECTL_OVER1 :
1470 B43_NPHY_AFECTL_OVER;
1471 b43_phy_set(dev, reg, 0x0200);
1472 }
1473 }
1474 }
53ae8e8c 1475 }
53ae8e8c
RM		 1476}
1477
a3764ef7
RM		 1478static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1479 enum n_rssi_type rssi_type)
9442e5b5 1480{
4d9f46ba 1481 u16 val;
a3764ef7 1482 bool rssi_w1_w2_nb = false;
9442e5b5 1483
a3764ef7
RM		 1484 switch (rssi_type) {
1485 case N_RSSI_W1:
1486 case N_RSSI_W2:
1487 case N_RSSI_NB:
4d9f46ba 1488 val = 0;
a3764ef7
RM		 1489 rssi_w1_w2_nb = true;
1490 break;
1491 case N_RSSI_TBD:
4d9f46ba 1492 val = 1;
a3764ef7
RM		 1493 break;
1494 case N_RSSI_IQ:
4d9f46ba 1495 val = 2;
a3764ef7
RM		 1496 break;
1497 default:
4d9f46ba 1498 val = 3;
a3764ef7 1499 }
9442e5b5 1500
4d9f46ba
RM		 1501 val = (val << 12) | (val << 14);
1502 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1503 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1504
a3764ef7 1505 if (rssi_w1_w2_nb) {
4d9f46ba 1506 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1507 (rssi_type + 1) << 4);
4d9f46ba 1508 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1509 (rssi_type + 1) << 4);
9442e5b5
RM		 1510 }
1511
4d9f46ba
RM		 1512 if (code == 0) {
1513 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1514 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1515 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1516 ~(B43_NPHY_RFCTL_CMD_RXEN |
1517 B43_NPHY_RFCTL_CMD_CORESEL));
1518 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1519 ~(0x1 << 12 |
1520 0x1 << 5 |
1521 0x1 << 1 |
1522 0x1));
1523 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1524 ~B43_NPHY_RFCTL_CMD_START);
1525 udelay(20);
1526 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1527 }
1528 } else {
1529 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1530 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1531 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1532 ~(B43_NPHY_RFCTL_CMD_RXEN |
1533 B43_NPHY_RFCTL_CMD_CORESEL),
1534 (B43_NPHY_RFCTL_CMD_RXEN |
1535 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1536 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1537 (0x1 << 12 |
1538 0x1 << 5 |
1539 0x1 << 1 |
1540 0x1));
1541 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1542 B43_NPHY_RFCTL_CMD_START);
1543 udelay(20);
1544 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1545 }
9442e5b5 1546 }
9442e5b5
RM		 1547}
1548
4d9f46ba 1549/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1550static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1551 enum n_rssi_type type)
d24019ad 1552{
4d9f46ba
RM		 1553 if (dev->phy.rev >= 3)
1554 b43_nphy_rev3_rssi_select(dev, code, type);
1555 else
1556 b43_nphy_rev2_rssi_select(dev, code, type);
1557}
d24019ad 1558
5ecab603 1559/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1560static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1561 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1562{
1563 int i;
d24019ad 1564 for (i = 0; i < 2; i++) {
a3764ef7 1565 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1566 if (i == 0) {
1567 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1568 0xFC, buf[0]);
1569 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1570 0xFC, buf[1]);
1571 } else {
1572 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1573 0xFC, buf[2 * i]);
1574 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1575 0xFC, buf[2 * i + 1]);
1576 }
d24019ad 1577 } else {
5ecab603
RM		 1578 if (i == 0)
1579 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1580 0xF3, buf[0] << 2);
1581 else
1582 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1583 0xF3, buf[2 * i + 1] << 2);
d24019ad 1584 }
d24019ad 1585 }
d24019ad
RM		 1586}
1587
5ecab603 1588/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1589static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1590 s32 *buf, u8 nsamp)
ef5127a4 1591{
5ecab603
RM		 1592 int i;
1593 int out;
1594 u16 save_regs_phy[9];
1595 u16 s[2];
ef5127a4
RM		 1596
1597 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1598 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1599 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1600 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1601 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1602 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1603 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1604 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1605 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1606 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1607 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1608 save_regs_phy[8] = 0;
ef5127a4 1609 } else {
5ecab603
RM		 1610 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1611 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1612 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1613 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1614 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1615 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1616 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1617 save_regs_phy[7] = 0;
1618 save_regs_phy[8] = 0;
1619 }
ef5127a4 1620
a3764ef7 1621 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1622
5ecab603
RM		 1623 if (dev->phy.rev < 2) {
1624 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1625 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1626 }
ef5127a4 1627
5ecab603
RM		 1628 for (i = 0; i < 4; i++)
1629 buf[i] = 0;
1630
1631 for (i = 0; i < nsamp; i++) {
1632 if (dev->phy.rev < 2) {
1633 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1634 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1635 } else {
5ecab603
RM		 1636 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1637 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1638 }
1639
5ecab603
RM		 1640 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1641 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1642 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1643 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1644 }
1645 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1646 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1647
5ecab603
RM		 1648 if (dev->phy.rev < 2)
1649 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1650
5ecab603 1651 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1652 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1653 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1654 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1655 save_regs_phy[2]);
5ecab603 1656 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1657 save_regs_phy[3]);
5ecab603
RM		 1658 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1659 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1660 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1661 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1662 } else {
1663 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1664 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1665 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1666 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1667 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1668 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1669 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1670 }
ef5127a4 1671
5ecab603
RM		 1672 return out;
1673}
ef5127a4 1674
e0c9a021
RM		 1675/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1676static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1677{
39e971ef 1678 struct b43_phy *phy = &dev->phy;
e0c9a021
RM		 1679 struct b43_phy_n *nphy = dev->phy.n;
1680
1681 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1682 u16 saved_regs_phy[22];
1683 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1684 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1685 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1686 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1687 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1688 B43_NPHY_RFCTL_CMD,
1689 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1690 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1691 };
97e2a1a1
RM		 1692 u16 regs_to_store_rev7[] = {
1693 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1694 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1695 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1696 0x342, 0x343, 0x346, 0x347,
1697 0x2ff,
1698 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1699 B43_NPHY_RFCTL_CMD,
1700 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1701 0x340, 0x341, 0x344, 0x345,
1702 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1703 };
1704 u16 *regs_to_store;
1705 int regs_amount;
e0c9a021
RM		 1706
1707 u16 class;
1708
1709 u16 clip_state[2];
1710 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1711
1712 u8 vcm_final = 0;
2e1253d6 1713 s32 offset[4];
e0c9a021
RM		 1714 s32 results[8][4] = { };
1715 s32 results_min[4] = { };
1716 s32 poll_results[4] = { };
1717
1718 u16 *rssical_radio_regs = NULL;
1719 u16 *rssical_phy_regs = NULL;
1720
1721 u16 r; /* routing */
1722 u8 rx_core_state;
37859a75 1723 int core, i, j, vcm;
e0c9a021 1724
97e2a1a1
RM		 1725 if (dev->phy.rev >= 7) {
1726 regs_to_store = regs_to_store_rev7;
1727 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1728 } else {
1729 regs_to_store = regs_to_store_rev3;
1730 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1731 }
1732 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1733
e0c9a021
RM		 1734 class = b43_nphy_classifier(dev, 0, 0);
1735 b43_nphy_classifier(dev, 7, 4);
1736 b43_nphy_read_clip_detection(dev, clip_state);
1737 b43_nphy_write_clip_detection(dev, clip_off);
1738
1739 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1740 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1741 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1742 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1743
89e43dad
RM		 1744 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1745 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1746
1747 if (dev->phy.rev >= 7) {
1748 /* TODO */
1749 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1750 } else {
1751 }
e0c9a021 1752 } else {
97e2a1a1
RM		 1753 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1754 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1755 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1756 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1757 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1758 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1759 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1760 } else {
1761 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1762 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1763 }
e0c9a021
RM		 1764 }
1765
1766 rx_core_state = b43_nphy_get_rx_core_state(dev);
1767 for (core = 0; core < 2; core++) {
1768 if (!(rx_core_state & (1 << core)))
1769 continue;
1770 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1771 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1772 N_RSSI_NB);
1773 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1774 N_RSSI_NB);
37859a75
RM		 1775
1776 /* Grab RSSI results for every possible VCM */
1777 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1778 if (dev->phy.rev >= 7)
1779 ;
1780 else
1781 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1782 0xE3, vcm << 2);
a3764ef7 1783 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1784 }
37859a75
RM		 1785
1786 /* Find out which VCM got the best results */
cddec902 1787 for (i = 0; i < 4; i += 2) {
37859a75 1788 s32 currd;
e67dd874 1789 s32 mind = 0x100000;
e0c9a021
RM		 1790 s32 minpoll = 249;
1791 u8 minvcm = 0;
1792 if (2 * core != i)
1793 continue;
37859a75
RM		 1794 for (vcm = 0; vcm < 8; vcm++) {
1795 currd = results[vcm][i] * results[vcm][i] +
1796 results[vcm][i + 1] * results[vcm][i];
1797 if (currd < mind) {
1798 mind = currd;
1799 minvcm = vcm;
e0c9a021 1800 }
37859a75
RM		 1801 if (results[vcm][i] < minpoll)
1802 minpoll = results[vcm][i];
e0c9a021
RM		 1803 }
1804 vcm_final = minvcm;
1805 results_min[i] = minpoll;
1806 }
37859a75
RM		 1807
1808 /* Select the best VCM */
97e2a1a1
RM		 1809 if (dev->phy.rev >= 7)
1810 ;
1811 else
1812 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1813 0xE3, vcm_final << 2);
37859a75 1814
e0c9a021
RM		 1815 for (i = 0; i < 4; i++) {
1816 if (core != i / 2)
1817 continue;
1818 offset[i] = -results[vcm_final][i];
1819 if (offset[i] < 0)
1820 offset[i] = -((abs(offset[i]) + 4) / 8);
1821 else
1822 offset[i] = (offset[i] + 4) / 8;
1823 if (results_min[i] == 248)
1824 offset[i] = -32;
1825 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1826 (i / 2 == 0) ? 1 : 2,
6aa38725 1827 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1828 N_RSSI_NB);
e0c9a021
RM		 1829 }
1830 }
37859a75 1831
e0c9a021
RM		 1832 for (core = 0; core < 2; core++) {
1833 if (!(rx_core_state & (1 << core)))
1834 continue;
1835 for (i = 0; i < 2; i++) {
6aa38725
RM		 1836 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1837 N_RAIL_I, i);
1838 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1839 N_RAIL_Q, i);
e0c9a021
RM		 1840 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1841 for (j = 0; j < 4; j++) {
cddec902 1842 if (j / 2 == core) {
e0c9a021 1843 offset[j] = 232 - poll_results[j];
cddec902
RM		 1844 if (offset[j] < 0)
1845 offset[j] = -(abs(offset[j] + 4) / 8);
1846 else
1847 offset[j] = (offset[j] + 4) / 8;
1848 b43_nphy_scale_offset_rssi(dev, 0,
1849 offset[2 * core], core + 1, j % 2, i);
1850 }
e0c9a021
RM		 1851 }
1852 }
1853 }
1854
1855 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1856 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1857
1858 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1859
1860 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1861 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1862 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1863
1864 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1865 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 1866 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 1867
97e2a1a1 1868 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1869 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1870
1871 /* Store for future configuration */
1872 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1873 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1874 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1875 } else {
1876 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1877 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1878 }
9a98979e
RM		 1879 if (dev->phy.rev >= 7) {
1880 } else {
1881 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1882 B2056_RX_RSSI_MISC);
1883 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1884 B2056_RX_RSSI_MISC);
1885 }
e0c9a021
RM		 1886 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1887 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1888 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1889 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1890 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1891 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1892 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1893 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1894 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1895 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1896 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1897 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1898
1899 /* Remember for which channel we store configuration */
1900 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
39e971ef 1901 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq;
e0c9a021 1902 else
39e971ef 1903 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq;
e0c9a021
RM		 1904
1905 /* End of calibration, restore configuration */
1906 b43_nphy_classifier(dev, 7, class);
1907 b43_nphy_write_clip_detection(dev, clip_state);
1908}
1909
5ecab603 1910/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1911static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1912{
37859a75 1913 int i, j, vcm;
5ecab603
RM		 1914 u8 state[4];
1915 u8 code, val;
1916 u16 class, override;
1917 u8 regs_save_radio[2];
1918 u16 regs_save_phy[2];
1919
2e1253d6 1920 s32 offset[4];
5ecab603
RM		 1921 u8 core;
1922 u8 rail;
1923
1924 u16 clip_state[2];
1925 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1926 s32 results_min[4] = { };
1927 u8 vcm_final[4] = { };
1928 s32 results[4][4] = { };
1929 s32 miniq[4][2] = { };
1930
a3764ef7 1931 if (type == N_RSSI_NB) {
5ecab603
RM		 1932 code = 0;
1933 val = 6;
a3764ef7 1934 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1935 code = 25;
1936 val = 4;
1937 } else {
1938 B43_WARN_ON(1);
1939 return;
1940 }
1941
1942 class = b43_nphy_classifier(dev, 0, 0);
1943 b43_nphy_classifier(dev, 7, 4);
1944 b43_nphy_read_clip_detection(dev, clip_state);
1945 b43_nphy_write_clip_detection(dev, clip_off);
1946
1947 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1948 override = 0x140;
1949 else
1950 override = 0x110;
1951
1952 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 1953 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 1954 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 1955 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 1956
1957 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 1958 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 1959 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 1960 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 1961
0c201cfb
RM		 1962 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1963 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 1964 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1965 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 1966 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1967 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 1968
1969 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1970 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1971 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1972
37859a75 1973 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1974 u8 tmp[4];
1975 for (j = 0; j < 4; j++)
37859a75 1976 tmp[j] = vcm;
a3764ef7 1977 if (type != N_RSSI_W2)
5ecab603 1978 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1979 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1980 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1981 for (j = 0; j < 2; j++)
37859a75
RM		 1982 miniq[vcm][j] = min(results[vcm][2 * j],
1983 results[vcm][2 * j + 1]);
5ecab603
RM		 1984 }
1985
1986 for (i = 0; i < 4; i++) {
e67dd874 1987 s32 mind = 0x100000;
5ecab603
RM		 1988 u8 minvcm = 0;
1989 s32 minpoll = 249;
37859a75
RM		 1990 s32 currd;
1991 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1992 if (type == N_RSSI_NB)
542e15f3 1993 currd = abs(results[vcm][i] - code * 8);
5ecab603 1994 else
37859a75 1995 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1996
37859a75
RM		 1997 if (currd < mind) {
1998 mind = currd;
1999 minvcm = vcm;
5ecab603
RM		 2000 }
2001
37859a75
RM		 2002 if (results[vcm][i] < minpoll)
2003 minpoll = results[vcm][i];
8e60b044 2004 }
5ecab603
RM		 2005 results_min[i] = minpoll;
2006 vcm_final[i] = minvcm;
2007 }
ef5127a4 2008
a3764ef7 2009 if (type != N_RSSI_W2)
5ecab603 2010 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2011
5ecab603
RM		 2012 for (i = 0; i < 4; i++) {
2013 offset[i] = (code * 8) - results[vcm_final[i]][i];
2014
2015 if (offset[i] < 0)
2016 offset[i] = -((abs(offset[i]) + 4) / 8);
2017 else
2018 offset[i] = (offset[i] + 4) / 8;
2019
2020 if (results_min[i] == 248)
2021 offset[i] = code - 32;
2022
2023 core = (i / 2) ? 2 : 1;
6aa38725 2024 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2025
2026 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2027 type);
2028 }
2029
2030 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2031 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2032
2033 switch (state[2]) {
2034 case 1:
a3764ef7 2035 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2036 break;
2037 case 4:
a3764ef7 2038 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2039 break;
2040 case 2:
a3764ef7 2041 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2042 break;
2043 default:
a3764ef7 2044 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2045 break;
2046 }
2047
2048 switch (state[3]) {
2049 case 1:
a3764ef7 2050 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2051 break;
2052 case 4:
a3764ef7 2053 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2054 break;
2055 default:
a3764ef7 2056 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2057 break;
2058 }
2059
2060 b43_nphy_rssi_select(dev, 0, type);
2061
2062 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2063 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2064 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2065 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2066
2067 b43_nphy_classifier(dev, 7, class);
2068 b43_nphy_write_clip_detection(dev, clip_state);
2069 /* Specs don't say about reset here, but it makes wl and b43 dumps
2070 identical, it really seems wl performs this */
2071 b43_nphy_reset_cca(dev);
2072}
2073
5ecab603
RM		 2074/*
2075 * RSSI Calibration
2076 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2077 */
2078static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2079{
2080 if (dev->phy.rev >= 3) {
2081 b43_nphy_rev3_rssi_cal(dev);
2082 } else {
2a2d0589
RM		 2083 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2084 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2085 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2086 }
2087}
2088
64712095
RM		 2089/**************************************************
2090 * Workarounds
2091 **************************************************/
2092
2093static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2094{
2095 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2096
2097 bool ghz5;
2098 bool ext_lna;
2099 u16 rssi_gain;
2100 struct nphy_gain_ctl_workaround_entry *e;
2101 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2102 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2103
2104 /* Prepare values */
2105 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2106 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2107 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2108 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2109 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2110 if (ghz5 && dev->phy.rev >= 5)
2111 rssi_gain = 0x90;
2112 else
2113 rssi_gain = 0x50;
2114
2115 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2116
2117 /* Set Clip 2 detect */
04519dc6
RM		 2118 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2119 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2120
2121 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2122 0x17);
2123 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2124 0x17);
2125 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2126 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2127 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2128 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2129 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2130 rssi_gain);
2131 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2132 rssi_gain);
2133 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2134 0x17);
2135 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2136 0x17);
2137 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2138 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2139
2140 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2141 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2142 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2143 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2144 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2145 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2146 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2147 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2148 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2149 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2150 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2151 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2152
04519dc6
RM		 2153 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2154 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2155
64712095
RM		 2156 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2157 e->rfseq_init);
64712095 2158
04519dc6
RM		 2159 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2160 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2161 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2162 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2163 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2164 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2165
2166 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2167 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2168 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2169 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2170 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2171 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2172 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2173 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2174 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2175 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2176}
2177
2178static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2179{
2180 struct b43_phy_n *nphy = dev->phy.n;
2181
2182 u8 i, j;
2183 u8 code;
2184 u16 tmp;
2185 u8 rfseq_events[3] = { 6, 8, 7 };
2186 u8 rfseq_delays[3] = { 10, 30, 1 };
2187
2188 /* Set Clip 2 detect */
2189 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2190 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2191
2192 /* Set narrowband clip threshold */
2193 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2194 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2195
bee6d4b2 2196 if (!b43_is_40mhz(dev)) {
64712095
RM		 2197 /* Set dwell lengths */
2198 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2199 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2200 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2201 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2202 }
2203
2204 /* Set wideband clip 2 threshold */
2205 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2206 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2207 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2208 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2209
bee6d4b2 2210 if (!b43_is_40mhz(dev)) {
64712095
RM		 2211 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2212 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2213 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2214 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2215 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2216 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2217 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2218 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2219 }
2220
2221 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2222
2223 if (nphy->gain_boost) {
2224 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
bee6d4b2 2225 b43_is_40mhz(dev))
64712095
RM		 2226 code = 4;
2227 else
2228 code = 5;
2229 } else {
bee6d4b2 2230 code = b43_is_40mhz(dev) ? 6 : 7;
64712095
RM		 2231 }
2232
2233 /* Set HPVGA2 index */
2234 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2235 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2236 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2237 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2238
2239 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2240 /* specs say about 2 loops, but wl does 4 */
2241 for (i = 0; i < 4; i++)
2242 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2243
2244 b43_nphy_adjust_lna_gain_table(dev);
2245
2246 if (nphy->elna_gain_config) {
2247 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2248 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2249 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2250 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2251 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2252
2253 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2254 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2255 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2256 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2257 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2258
2259 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2260 /* specs say about 2 loops, but wl does 4 */
2261 for (i = 0; i < 4; i++)
2262 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2263 (code << 8 | 0x74));
2264 }
2265
2266 if (dev->phy.rev == 2) {
2267 for (i = 0; i < 4; i++) {
2268 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2269 (0x0400 * i) + 0x0020);
2270 for (j = 0; j < 21; j++) {
2271 tmp = j * (i < 2 ? 3 : 1);
2272 b43_phy_write(dev,
2273 B43_NPHY_TABLE_DATALO, tmp);
2274 }
2275 }
ef5127a4 2276 }
64712095
RM		 2277
2278 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2279 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2280 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2281 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2282
2283 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2284 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2285}
2286
2287/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2288static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2289{
d11d354b
RM		 2290 if (dev->phy.rev >= 7)
2291 ; /* TODO */
2292 else if (dev->phy.rev >= 3)
64712095
RM		 2293 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2294 else
2295 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2296}
2297
d11d354b
RM		 2298/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2299static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2300{
2301 if (!offset)
bee6d4b2 2302 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
d11d354b
RM		 2303 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2304}
2305
2306static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2307{
2308 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2309 struct b43_phy *phy = &dev->phy;
2310
2311 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2312 0x1F };
2313 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2314
2315 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2316 u8 ntab7_138_146[] = { 0x11, 0x11 };
2317 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2318
2319 u16 lpf_20, lpf_40, lpf_11b;
2320 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2321 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2322 bool rccal_ovrd = false;
2323
2324 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2325 u16 bias, conv, filt;
2326
2327 u32 tmp32;
2328 u8 core;
2329
2330 if (phy->rev == 7) {
2331 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2332 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2333 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2334 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2335 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2336 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2337 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2338 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2339 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2340 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2341 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2342 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2343 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2344 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2345 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2346 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2347 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2348 }
2349 if (phy->rev <= 8) {
04519dc6
RM		 2350 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2351 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2352 }
2353 if (phy->rev >= 8)
2354 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2355
2356 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2357 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2358 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2359 tmp32 &= 0xffffff;
2360 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2361 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2362 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2363
2364 if (b43_nphy_ipa(dev))
2365 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2366 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2367
04519dc6
RM		 2368 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2369 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2370
2371 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2372 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2373 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2374 if (b43_nphy_ipa(dev)) {
bee6d4b2 2375 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
d11d354b
RM		 2376 phy->radio_rev == 7 || phy->radio_rev == 8) {
2377 bcap_val = b43_radio_read(dev, 0x16b);
2378 scap_val = b43_radio_read(dev, 0x16a);
2379 scap_val_11b = scap_val;
2380 bcap_val_11b = bcap_val;
bee6d4b2 2381 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
d11d354b
RM		 2382 scap_val_11n_20 = scap_val;
2383 bcap_val_11n_20 = bcap_val;
2384 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2385 rccal_ovrd = true;
2386 } else { /* Rev 7/8 */
2387 lpf_20 = 4;
2388 lpf_11b = 1;
2389 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2390 scap_val_11n_20 = 0xc;
2391 bcap_val_11n_20 = 0xc;
2392 scap_val_11n_40 = 0xa;
2393 bcap_val_11n_40 = 0xa;
2394 } else {
2395 scap_val_11n_20 = 0x14;
2396 bcap_val_11n_20 = 0x14;
2397 scap_val_11n_40 = 0xf;
2398 bcap_val_11n_40 = 0xf;
2399 }
2400 rccal_ovrd = true;
2401 }
2402 }
2403 } else {
2404 if (phy->radio_rev == 5) {
2405 lpf_20 = 1;
2406 lpf_40 = 3;
2407 bcap_val = b43_radio_read(dev, 0x16b);
2408 scap_val = b43_radio_read(dev, 0x16a);
2409 scap_val_11b = scap_val;
2410 bcap_val_11b = bcap_val;
2411 scap_val_11n_20 = 0x11;
2412 scap_val_11n_40 = 0x11;
2413 bcap_val_11n_20 = 0x13;
2414 bcap_val_11n_40 = 0x13;
2415 rccal_ovrd = true;
2416 }
2417 }
2418 if (rccal_ovrd) {
2419 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2420 (scap_val_11b << 3) |
2421 lpf_11b;
2422 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2423 (scap_val_11n_20 << 3) |
2424 lpf_20;
2425 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2426 (scap_val_11n_40 << 3) |
2427 lpf_40;
2428 for (core = 0; core < 2; core++) {
2429 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2430 rx2tx_lut_20_11b);
2431 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2432 rx2tx_lut_20_11n);
2433 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2434 rx2tx_lut_20_11n);
2435 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2436 rx2tx_lut_40_11n);
2437 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2438 rx2tx_lut_40_11n);
2439 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2440 rx2tx_lut_40_11n);
2441 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2442 rx2tx_lut_40_11n);
2443 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2444 rx2tx_lut_40_11n);
2445 }
78ae7532 2446 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2447 }
2448 b43_phy_write(dev, 0x32F, 0x3);
2449 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2450 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2451
2452 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2453 if (sprom->revision &&
2454 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2455 b43_radio_write(dev, 0x5, 0x05);
2456 b43_radio_write(dev, 0x6, 0x30);
2457 b43_radio_write(dev, 0x7, 0x00);
2458 b43_radio_set(dev, 0x4f, 0x1);
2459 b43_radio_set(dev, 0xd4, 0x1);
2460 bias = 0x1f;
2461 conv = 0x6f;
2462 filt = 0xaa;
2463 } else {
2464 bias = 0x2b;
2465 conv = 0x7f;
2466 filt = 0xee;
2467 }
2468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2469 for (core = 0; core < 2; core++) {
2470 if (core == 0) {
2471 b43_radio_write(dev, 0x5F, bias);
2472 b43_radio_write(dev, 0x64, conv);
2473 b43_radio_write(dev, 0x66, filt);
2474 } else {
2475 b43_radio_write(dev, 0xE8, bias);
2476 b43_radio_write(dev, 0xE9, conv);
2477 b43_radio_write(dev, 0xEB, filt);
2478 }
2479 }
2480 }
2481 }
2482
2483 if (b43_nphy_ipa(dev)) {
2484 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2485 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2486 phy->radio_rev == 6) {
2487 for (core = 0; core < 2; core++) {
2488 if (core == 0)
2489 b43_radio_write(dev, 0x51,
2490 0x7f);
2491 else
2492 b43_radio_write(dev, 0xd6,
2493 0x7f);
2494 }
2495 }
2496 if (phy->radio_rev == 3) {
2497 for (core = 0; core < 2; core++) {
2498 if (core == 0) {
2499 b43_radio_write(dev, 0x64,
2500 0x13);
2501 b43_radio_write(dev, 0x5F,
2502 0x1F);
2503 b43_radio_write(dev, 0x66,
2504 0xEE);
2505 b43_radio_write(dev, 0x59,
2506 0x8A);
2507 b43_radio_write(dev, 0x80,
2508 0x3E);
2509 } else {
2510 b43_radio_write(dev, 0x69,
2511 0x13);
2512 b43_radio_write(dev, 0xE8,
2513 0x1F);
2514 b43_radio_write(dev, 0xEB,
2515 0xEE);
2516 b43_radio_write(dev, 0xDE,
2517 0x8A);
2518 b43_radio_write(dev, 0x105,
2519 0x3E);
2520 }
2521 }
2522 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
bee6d4b2 2523 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2524 b43_radio_write(dev, 0x5F, 0x14);
2525 b43_radio_write(dev, 0xE8, 0x12);
2526 } else {
2527 b43_radio_write(dev, 0x5F, 0x16);
2528 b43_radio_write(dev, 0xE8, 0x16);
2529 }
2530 }
2531 } else {
39e971ef 2532 u16 freq = phy->chandef->chan->center_freq;
d11d354b
RM		 2533 if ((freq >= 5180 && freq <= 5230) ||
2534 (freq >= 5745 && freq <= 5805)) {
2535 b43_radio_write(dev, 0x7D, 0xFF);
2536 b43_radio_write(dev, 0xFE, 0xFF);
2537 }
2538 }
2539 } else {
2540 if (phy->radio_rev != 5) {
2541 for (core = 0; core < 2; core++) {
2542 if (core == 0) {
2543 b43_radio_write(dev, 0x5c, 0x61);
2544 b43_radio_write(dev, 0x51, 0x70);
2545 } else {
2546 b43_radio_write(dev, 0xe1, 0x61);
2547 b43_radio_write(dev, 0xd6, 0x70);
2548 }
2549 }
2550 }
2551 }
2552
2553 if (phy->radio_rev == 4) {
2554 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2555 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2556 for (core = 0; core < 2; core++) {
2557 if (core == 0) {
2558 b43_radio_write(dev, 0x1a1, 0x00);
2559 b43_radio_write(dev, 0x1a2, 0x3f);
2560 b43_radio_write(dev, 0x1a6, 0x3f);
2561 } else {
2562 b43_radio_write(dev, 0x1a7, 0x00);
2563 b43_radio_write(dev, 0x1ab, 0x3f);
2564 b43_radio_write(dev, 0x1ac, 0x3f);
2565 }
2566 }
2567 } else {
2568 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2569 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2570 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2571 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2572
2573 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2574 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2575 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2576 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2577 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2578 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2579
2580 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2581 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2582 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2583 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2584 }
2585
2586 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2587
2588 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2589 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2590 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2591 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2592 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2593 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2594 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2595
bee6d4b2 2596 if (!b43_is_40mhz(dev)) {
d11d354b
RM		 2597 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2598 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2599 } else {
2600 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2601 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2602 }
2603
2604 b43_nphy_gain_ctl_workarounds(dev);
2605
2606 /* TODO
2607 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2608 aux_adc_vmid_rev7_core0);
2609 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2610 aux_adc_vmid_rev7_core1);
2611 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2612 aux_adc_gain_rev7);
2613 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2614 aux_adc_gain_rev7);
2615 */
2616}
2617
73d07a39 2618static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2619{
0eff8fcd 2620 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2621 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2622
0eff8fcd 2623 /* TX to RX */
c378bb97
RM		 2624 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2625 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2626 /* RX to TX */
2627 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2628 0x1F };
2629 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2630 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2631 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2632
c378bb97
RM		 2633 u16 vmids[5][4] = {
2634 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2635 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2636 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2637 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2638 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2639 };
2640 u16 gains[5][4] = {
2641 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2642 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2643 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2644 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2645 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2646 };
2647 u16 *vmid, *gain;
2648
2649 u8 pdet_range;
ba9a6214
RM		 2650 u16 tmp16;
2651 u32 tmp32;
2652
04519dc6
RM		 2653 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2654 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2655
73d07a39
RM		 2656 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2657 tmp32 &= 0xffffff;
2658 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2659
73d07a39
RM		 2660 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2661 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2662 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2663 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2664 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2665 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2666
04519dc6
RM		 2667 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2668 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2669
0eff8fcd 2670 /* TX to RX */
c56da252
RM		 2671 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2672 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2673
2674 /* RX to TX */
2675 if (b43_nphy_ipa(dev))
c56da252
RM		 2676 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2677 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2678 if (nphy->hw_phyrxchain != 3 &&
2679 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2680 if (b43_nphy_ipa(dev)) {
2681 rx2tx_delays[5] = 59;
2682 rx2tx_delays[6] = 1;
2683 rx2tx_events[7] = 0x1F;
2684 }
fa0f2b38 2685 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2686 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2687 }
ba9a6214 2688
73d07a39
RM		 2689 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2690 0x2 : 0x9C40;
2691 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2692
04519dc6 2693 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2694
bee6d4b2 2695 if (!b43_is_40mhz(dev)) {
fa0f2b38
RM		 2696 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2697 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2698 } else {
2699 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2700 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2701 }
ba9a6214 2702
3ccd0957 2703 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2704
c56da252
RM		 2705 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2706 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2707
c378bb97
RM		 2708 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2709 pdet_range = sprom->fem.ghz2.pdet_range;
2710 else
2711 pdet_range = sprom->fem.ghz5.pdet_range;
2712 vmid = vmids[min_t(u16, pdet_range, 4)];
2713 gain = gains[min_t(u16, pdet_range, 4)];
2714 switch (pdet_range) {
2715 case 3:
2716 if (!(dev->phy.rev >= 4 &&
2717 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2718 break;
2719 /* FALL THROUGH */
2720 case 0:
2721 case 1:
2722 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2723 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2724 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2725 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2726 break;
2727 case 2:
2728 if (dev->phy.rev >= 6) {
2729 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2730 vmid[3] = 0x94;
2731 else
2732 vmid[3] = 0x8e;
2733 gain[3] = 3;
2734 } else if (dev->phy.rev == 5) {
2735 vmid[3] = 0x84;
2736 gain[3] = 2;
2737 }
2738 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2739 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2740 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2741 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2742 break;
2743 case 4:
2744 case 5:
2745 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2746 if (pdet_range == 4) {
2747 vmid[3] = 0x8e;
2748 tmp16 = 0x96;
2749 gain[3] = 0x2;
2750 } else {
2751 vmid[3] = 0x89;
2752 tmp16 = 0x89;
2753 gain[3] = 0;
2754 }
2755 } else {
2756 if (pdet_range == 4) {
2757 vmid[3] = 0x89;
2758 tmp16 = 0x8b;
2759 gain[3] = 0x2;
2760 } else {
2761 vmid[3] = 0x74;
2762 tmp16 = 0x70;
2763 gain[3] = 0;
2764 }
2765 }
2766 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2767 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2768 vmid[3] = tmp16;
2769 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2770 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2771 break;
2772 }
ba9a6214 2773
73d07a39
RM		 2774 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2775 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2776 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2777 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2778 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2779 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2780 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2781 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2782 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2783 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2784 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2785 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2786
2787 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2788
2789 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2790 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2791 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2792 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2793 tmp32 = 0x00088888;
2794 else
2795 tmp32 = 0x88888888;
2796 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2797 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2798 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2799
2800 if (dev->phy.rev == 4 &&
fa0f2b38 2801 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2802 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2803 0x70);
2804 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2805 0x70);
2806 }
ba9a6214 2807
fa0f2b38 2808 /* Dropped probably-always-true condition */
04519dc6
RM		 2809 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2810 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2811 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2812 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2813 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2814 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2815 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2816 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2817 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2818 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2819 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2820 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2821
2822 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2823 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2824}
ba9a6214 2825
73d07a39
RM		 2826static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2827{
2828 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2829 struct b43_phy *phy = &dev->phy;
2830 struct b43_phy_n *nphy = phy->n;
ba9a6214 2831
73d07a39
RM		 2832 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2833 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2834
73d07a39
RM		 2835 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2836 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2837
fa0f2b38 2838 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2839 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2840 delays1[0] = 0x1;
2841 delays1[5] = 0x14;
2842 }
2843
73d07a39
RM		 2844 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2845 nphy->band5g_pwrgain) {
2846 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2847 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2848 } else {
73d07a39
RM		 2849 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2850 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2851 }
28fd7daa 2852
73d07a39
RM		 2853 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2854 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2855 if (dev->phy.rev < 3) {
2856 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2857 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2858 }
73d07a39
RM		 2859
2860 if (dev->phy.rev < 2) {
2861 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2862 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2863 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2864 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2865 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2866 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2867 }
28fd7daa 2868
73d07a39
RM		 2869 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2870 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2871 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2872 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2873
73d07a39
RM		 2874 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2875 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2876
3ccd0957 2877 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2878
2879 if (dev->phy.rev < 2) {
2880 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2881 b43_hf_write(dev, b43_hf_read(dev) |
2882 B43_HF_MLADVW);
2883 } else if (dev->phy.rev == 2) {
2884 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2885 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2886 }
28fd7daa 2887
73d07a39
RM		 2888 if (dev->phy.rev < 2)
2889 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2890 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2891
2892 /* Set phase track alpha and beta */
2893 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2894 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2895 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2896 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2897 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2898 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2899
fa0f2b38
RM		 2900 if (dev->phy.rev < 3) {
2901 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2902 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2903 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2904 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2905 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2906 }
73d07a39
RM		 2907
2908 if (dev->phy.rev == 2)
2909 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2910 B43_NPHY_FINERX2_CGC_DECGC);
2911}
28fd7daa 2912
73d07a39
RM		 2913/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2914static void b43_nphy_workarounds(struct b43_wldev *dev)
2915{
2916 struct b43_phy *phy = &dev->phy;
2917 struct b43_phy_n *nphy = phy->n;
28fd7daa 2918
73d07a39
RM		 2919 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2920 b43_nphy_classifier(dev, 1, 0);
2921 else
2922 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2923
73d07a39
RM		 2924 if (nphy->hang_avoid)
2925 b43_nphy_stay_in_carrier_search(dev, 1);
2926
2927 b43_phy_set(dev, B43_NPHY_IQFLIP,
2928 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2929
d11d354b
RM		 2930 if (dev->phy.rev >= 7)
2931 b43_nphy_workarounds_rev7plus(dev);
2932 else if (dev->phy.rev >= 3)
73d07a39
RM		 2933 b43_nphy_workarounds_rev3plus(dev);
2934 else
2935 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2936
2937 if (nphy->hang_avoid)
2938 b43_nphy_stay_in_carrier_search(dev, 0);
2939}
2940
9dd4d9b9
RM		 2941/**************************************************
2942 * Tx/Rx common
2943 **************************************************/
2944
2945/*
2946 * Transmits a known value for LO calibration
2947 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2948 */
2949static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2950 bool iqmode, bool dac_test)
2951{
2952 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2953 if (samp == 0)
2954 return -1;
2955 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2956 return 0;
2957}
2958
2959/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2960static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2961{
2962 struct b43_phy_n *nphy = dev->phy.n;
2963
2964 bool override = false;
2965 u16 chain = 0x33;
2966
2967 if (nphy->txrx_chain == 0) {
2968 chain = 0x11;
2969 override = true;
2970 } else if (nphy->txrx_chain == 1) {
2971 chain = 0x22;
2972 override = true;
2973 }
2974
2975 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2976 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2977 chain);
2978
2979 if (override)
2980 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2981 B43_NPHY_RFSEQMODE_CAOVER);
2982 else
2983 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2984 ~B43_NPHY_RFSEQMODE_CAOVER);
2985}
2986
2987/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2988static void b43_nphy_stop_playback(struct b43_wldev *dev)
2989{
2990 struct b43_phy_n *nphy = dev->phy.n;
2991 u16 tmp;
2992
2993 if (nphy->hang_avoid)
2994 b43_nphy_stay_in_carrier_search(dev, 1);
2995
2996 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2997 if (tmp & 0x1)
2998 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2999 else if (tmp & 0x2)
3000 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3001
3002 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3003
3004 if (nphy->bb_mult_save & 0x80000000) {
3005 tmp = nphy->bb_mult_save & 0xFFFF;
3006 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3007 nphy->bb_mult_save = 0;
3008 }
3009
3010 if (nphy->hang_avoid)
3011 b43_nphy_stay_in_carrier_search(dev, 0);
3012}
3013
3014/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3015static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3016 struct nphy_txgains target,
3017 struct nphy_iqcal_params *params)
3018{
3019 int i, j, indx;
3020 u16 gain;
3021
3022 if (dev->phy.rev >= 3) {
3023 params->txgm = target.txgm[core];
3024 params->pga = target.pga[core];
3025 params->pad = target.pad[core];
3026 params->ipa = target.ipa[core];
3027 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3028 (params->pad << 4) | (params->ipa);
3029 for (j = 0; j < 5; j++)
3030 params->ncorr[j] = 0x79;
3031 } else {
3032 gain = (target.pad[core]) | (target.pga[core] << 4) |
3033 (target.txgm[core] << 8);
3034
3035 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3036 1 : 0;
3037 for (i = 0; i < 9; i++)
3038 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3039 break;
3040 i = min(i, 8);
3041
3042 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3043 params->pga = tbl_iqcal_gainparams[indx][i][2];
3044 params->pad = tbl_iqcal_gainparams[indx][i][3];
3045 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3046 (params->pad << 2);
3047 for (j = 0; j < 4; j++)
3048 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3049 }
3050}
3051
884a5228 3052/**************************************************
104cfa88 3053 * Tx and Rx
884a5228 3054 **************************************************/
5f6393ec 3055
884a5228
RM		 3056static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3057{//TODO
3058}
59af099b 3059
884a5228
RM		 3060static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3061 bool ignore_tssi)
3062{//TODO
3063 return B43_TXPWR_RES_DONE;
3064}
59af099b 3065
161d540c
RM		 3066/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3067static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3068{
3069 struct b43_phy_n *nphy = dev->phy.n;
3070 u8 i;
c9c0d9ec
RM		 3071 u16 bmask, val, tmp;
3072 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3073
161d540c
RM		 3074 if (nphy->hang_avoid)
3075 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3076
161d540c
RM		 3077 nphy->txpwrctrl = enable;
3078 if (!enable) {
c9c0d9ec
RM		 3079 if (dev->phy.rev >= 3 &&
3080 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3081 (B43_NPHY_TXPCTL_CMD_COEFF |
3082 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3083 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3084 /* We disable enabled TX pwr ctl, save it's state */
3085 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3086 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3087 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3088 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3089 }
59af099b 3090
161d540c
RM		 3091 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3092 for (i = 0; i < 84; i++)
3093 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3094
161d540c
RM		 3095 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3096 for (i = 0; i < 84; i++)
3097 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3098
161d540c
RM		 3099 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3100 if (dev->phy.rev >= 3)
3101 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3102 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3103
161d540c
RM		 3104 if (dev->phy.rev >= 3) {
3105 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3106 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3107 } else {
3108 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3109 }
10a79873 3110
161d540c
RM		 3111 if (dev->phy.rev == 2)
3112 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3113 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3114 else if (dev->phy.rev < 2)
3115 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3116 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3117
bee6d4b2 3118 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3119 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3120 } else {
c9c0d9ec
RM		 3121 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3122 nphy->adj_pwr_tbl);
3123 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3124 nphy->adj_pwr_tbl);
10a79873 3125
c9c0d9ec
RM		 3126 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3127 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3128 /* wl does useless check for "enable" param here */
3129 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3130 if (dev->phy.rev >= 3) {
3131 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3132 if (val)
3133 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3134 }
3135 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3136
c9c0d9ec
RM		 3137 if (band == IEEE80211_BAND_5GHZ) {
3138 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3139 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3140 if (dev->phy.rev > 1)
3141 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3142 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3143 0x64);
3144 }
10a79873 3145
c9c0d9ec
RM		 3146 if (dev->phy.rev >= 3) {
3147 if (nphy->tx_pwr_idx[0] != 128 &&
3148 nphy->tx_pwr_idx[1] != 128) {
3149 /* Recover TX pwr ctl state */
3150 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3151 ~B43_NPHY_TXPCTL_CMD_INIT,
3152 nphy->tx_pwr_idx[0]);
3153 if (dev->phy.rev > 1)
3154 b43_phy_maskset(dev,
3155 B43_NPHY_TXPCTL_INIT,
3156 ~0xff, nphy->tx_pwr_idx[1]);
3157 }
3158 }
10a79873 3159
c9c0d9ec
RM		 3160 if (dev->phy.rev >= 3) {
3161 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3162 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3163 } else {
3164 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3165 }
10a79873 3166
c9c0d9ec
RM		 3167 if (dev->phy.rev == 2)
3168 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3169 else if (dev->phy.rev < 2)
3170 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3171
bee6d4b2 3172 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
c9c0d9ec 3173 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3174
c002831a 3175 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3176 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3177 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3178 }
10a79873 3179 }
10a79873 3180
161d540c
RM		 3181 if (nphy->hang_avoid)
3182 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3183}
3184
161d540c 3185/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3186static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91 3187{
39e971ef 3188 struct b43_phy *phy = &dev->phy;
6dcd9d91 3189 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3190 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3191
161d540c
RM		 3192 u8 txpi[2], bbmult, i;
3193 u16 tmp, radio_gain, dac_gain;
39e971ef 3194 u16 freq = phy->chandef->chan->center_freq;
161d540c
RM		 3195 u32 txgain;
3196 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3197
3198 if (nphy->hang_avoid)
161d540c 3199 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3200
dd5f13b8
RM		 3201 if (dev->phy.rev >= 7) {
3202 txpi[0] = txpi[1] = 30;
3203 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3204 txpi[0] = 40;
3205 txpi[1] = 40;
3206 } else if (sprom->revision < 4) {
3207 txpi[0] = 72;
3208 txpi[1] = 72;
3209 } else {
3210 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3211 txpi[0] = sprom->txpid2g[0];
3212 txpi[1] = sprom->txpid2g[1];
3213 } else if (freq >= 4900 && freq < 5100) {
3214 txpi[0] = sprom->txpid5gl[0];
3215 txpi[1] = sprom->txpid5gl[1];
3216 } else if (freq >= 5100 && freq < 5500) {
3217 txpi[0] = sprom->txpid5g[0];
3218 txpi[1] = sprom->txpid5g[1];
3219 } else if (freq >= 5500) {
3220 txpi[0] = sprom->txpid5gh[0];
3221 txpi[1] = sprom->txpid5gh[1];
3222 } else {
3223 txpi[0] = 91;
3224 txpi[1] = 91;
6dcd9d91
RM		 3225 }
3226 }
dd5f13b8 3227 if (dev->phy.rev < 7 &&
9bd28571 3228 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3229 txpi[0] = txpi[1] = 91;
6dcd9d91 3230
161d540c
RM		 3231 /*
3232 for (i = 0; i < 2; i++) {
3233 nphy->txpwrindex[i].index_internal = txpi[i];
3234 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3235 }
161d540c 3236 */
75377b24 3237
161d540c 3238 for (i = 0; i < 2; i++) {
aeab5751
RM		 3239 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3240
3241 if (dev->phy.rev >= 3)
161d540c 3242 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3243 else
161d540c 3244 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3245
dd5f13b8
RM		 3246 if (dev->phy.rev >= 7)
3247 dac_gain = (txgain >> 8) & 0x7;
3248 else
3249 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3250 bbmult = txgain & 0xFF;
75377b24 3251
161d540c
RM		 3252 if (dev->phy.rev >= 3) {
3253 if (i == 0)
3254 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3255 else
3256 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3257 } else {
3258 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3259 }
75377b24 3260
161d540c
RM		 3261 if (i == 0)
3262 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3263 else
3264 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3265
44f4008b 3266 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3267
44f4008b 3268 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3269 if (i == 0)
3270 tmp = (tmp & 0x00FF) | (bbmult << 8);
3271 else
3272 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3273 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3274
0eff8fcd
RM		 3275 if (b43_nphy_ipa(dev)) {
3276 u32 tmp32;
3277 u16 reg = (i == 0) ?
3278 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3279 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3280 576 + txpi[i]));
0eff8fcd
RM		 3281 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3282 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3283 }
3284 }
75377b24 3285
161d540c 3286 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3287
161d540c
RM		 3288 if (nphy->hang_avoid)
3289 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3290}
67cbc3ed 3291
3dda07b6
RM		 3292static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3293{
3294 struct b43_phy *phy = &dev->phy;
3295
3296 u8 core;
3297 u16 r; /* routing */
3298
3299 if (phy->rev >= 7) {
3300 for (core = 0; core < 2; core++) {
3301 r = core ? 0x190 : 0x170;
3302 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3303 b43_radio_write(dev, r + 0x5, 0x5);
3304 b43_radio_write(dev, r + 0x9, 0xE);
3305 if (phy->rev != 5)
3306 b43_radio_write(dev, r + 0xA, 0);
3307 if (phy->rev != 7)
3308 b43_radio_write(dev, r + 0xB, 1);
3309 else
3310 b43_radio_write(dev, r + 0xB, 0x31);
3311 } else {
3312 b43_radio_write(dev, r + 0x5, 0x9);
3313 b43_radio_write(dev, r + 0x9, 0xC);
3314 b43_radio_write(dev, r + 0xB, 0x0);
3315 if (phy->rev != 5)
3316 b43_radio_write(dev, r + 0xA, 1);
3317 else
3318 b43_radio_write(dev, r + 0xA, 0x31);
3319 }
3320 b43_radio_write(dev, r + 0x6, 0);
3321 b43_radio_write(dev, r + 0x7, 0);
3322 b43_radio_write(dev, r + 0x8, 3);
3323 b43_radio_write(dev, r + 0xC, 0);
3324 }
3325 } else {
3326 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3327 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3328 else
3329 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3330 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3331 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3332
3333 for (core = 0; core < 2; core++) {
3334 r = core ? B2056_TX1 : B2056_TX0;
3335
3336 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3337 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3338 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3339 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3340 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3341 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3342 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3343 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3344 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3345 0x5);
3346 if (phy->rev != 5)
3347 b43_radio_write(dev, r | B2056_TX_TSSIA,
3348 0x00);
3349 if (phy->rev >= 5)
3350 b43_radio_write(dev, r | B2056_TX_TSSIG,
3351 0x31);
3352 else
3353 b43_radio_write(dev, r | B2056_TX_TSSIG,
3354 0x11);
3355 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3356 0xE);
3357 } else {
3358 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3359 0x9);
3360 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3361 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3362 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3363 0xC);
3364 }
3365 }
3366 }
3367}
3368
3369/*
3370 * Stop radio and transmit known signal. Then check received signal strength to
3371 * get TSSI (Transmit Signal Strength Indicator).
3372 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3373 */
3374static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3375{
3376 struct b43_phy *phy = &dev->phy;
3377 struct b43_phy_n *nphy = dev->phy.n;
3378
3379 u32 tmp;
3380 s32 rssi[4] = { };
3381
3382 /* TODO: check if we can transmit */
3383
3384 if (b43_nphy_ipa(dev))
3385 b43_nphy_ipa_internal_tssi_setup(dev);
3386
3387 if (phy->rev >= 7)
78ae7532 3388 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3389 else if (phy->rev >= 3)
78ae7532 3390 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3391
3392 b43_nphy_stop_playback(dev);
3393 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3394 udelay(20);
a3764ef7 3395 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3396 b43_nphy_stop_playback(dev);
a3764ef7 3397 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3398
3399 if (phy->rev >= 7)
78ae7532 3400 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3401 else if (phy->rev >= 3)
78ae7532 3402 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3403
3404 if (phy->rev >= 3) {
3405 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3406 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3407 } else {
3408 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3409 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3410 }
3411 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3412 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3413}
3414
d3fd8bf7
RM		 3415/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3416static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3417{
3418 struct b43_phy_n *nphy = dev->phy.n;
3419
3420 u8 idx, delta;
3421 u8 i, stf_mode;
3422
55757927
RM		 3423 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3424 * 21 groups, each containing 4 entries.
3425 *
3426 * First group has entries for CCK modulation.
3427 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3428 *
3429 * Group 0 is for CCK
3430 * Groups 1..4 use BPSK (group per coding rate)
3431 * Groups 5..8 use QPSK (group per coding rate)
3432 * Groups 9..12 use 16-QAM (group per coding rate)
3433 * Groups 13..16 use 64-QAM (group per coding rate)
3434 * Groups 17..20 are unknown
3435 */
3436
d3fd8bf7
RM		 3437 for (i = 0; i < 4; i++)
3438 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3439
3440 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3441 delta = 0;
3442 switch (stf_mode) {
3443 case 0:
bee6d4b2 3444 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
d3fd8bf7
RM		 3445 idx = 68;
3446 } else {
3447 delta = 1;
bee6d4b2 3448 idx = b43_is_40mhz(dev) ? 52 : 4;
d3fd8bf7
RM		 3449 }
3450 break;
3451 case 1:
bee6d4b2 3452 idx = b43_is_40mhz(dev) ? 76 : 28;
d3fd8bf7
RM		 3453 break;
3454 case 2:
bee6d4b2 3455 idx = b43_is_40mhz(dev) ? 84 : 36;
d3fd8bf7
RM		 3456 break;
3457 case 3:
bee6d4b2 3458 idx = b43_is_40mhz(dev) ? 92 : 44;
d3fd8bf7
RM		 3459 break;
3460 }
3461
3462 for (i = 0; i < 20; i++) {
3463 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3464 nphy->tx_power_offset[idx];
3465 if (i == 0)
3466 idx += delta;
3467 if (i == 14)
3468 idx += 1 - delta;
3469 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3470 i == 13)
3471 idx += 1;
3472 }
3473 }
3474}
3475
3476/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3477static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3478{
39e971ef 3479 struct b43_phy *phy = &dev->phy;
d3fd8bf7
RM		 3480 struct b43_phy_n *nphy = dev->phy.n;
3481 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3482
3483 s16 a1[2], b0[2], b1[2];
3484 u8 idle[2];
3485 s8 target[2];
3486 s32 num, den, pwr;
3487 u32 regval[64];
3488
39e971ef 3489 u16 freq = phy->chandef->chan->center_freq;
d3fd8bf7
RM		 3490 u16 tmp;
3491 u16 r; /* routing */
3492 u8 i, c;
3493
3494 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3495 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3496 b43_read32(dev, B43_MMIO_MACCTL);
3497 udelay(1);
3498 }
3499
3500 if (nphy->hang_avoid)
3501 b43_nphy_stay_in_carrier_search(dev, true);
3502
3503 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3504 if (dev->phy.rev >= 3)
3505 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3506 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3507 else
3508 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3509 B43_NPHY_TXPCTL_CMD_PCTLEN);
3510
3511 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3512 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3513
3514 if (sprom->revision < 4) {
3515 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3516 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3517 target[0] = target[1] = 52;
3518 a1[0] = a1[1] = -424;
3519 b0[0] = b0[1] = 5612;
3520 b1[0] = b1[1] = -1393;
3521 } else {
3522 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3523 for (c = 0; c < 2; c++) {
3524 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3525 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3526 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3527 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3528 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3529 }
3530 } else if (freq >= 4900 && freq < 5100) {
3531 for (c = 0; c < 2; c++) {
3532 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3533 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3534 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3535 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3536 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3537 }
3538 } else if (freq >= 5100 && freq < 5500) {
3539 for (c = 0; c < 2; c++) {
3540 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3541 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3542 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3543 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3544 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3545 }
3546 } else if (freq >= 5500) {
3547 for (c = 0; c < 2; c++) {
3548 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3549 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3550 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3551 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3552 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3553 }
3554 } else {
3555 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3556 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3557 target[0] = target[1] = 52;
3558 a1[0] = a1[1] = -424;
3559 b0[0] = b0[1] = 5612;
3560 b1[0] = b1[1] = -1393;
3561 }
3562 }
3563 /* target[0] = target[1] = nphy->tx_power_max; */
3564
3565 if (dev->phy.rev >= 3) {
3566 if (sprom->fem.ghz2.tssipos)
3567 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3568 if (dev->phy.rev >= 7) {
3569 for (c = 0; c < 2; c++) {
3570 r = c ? 0x190 : 0x170;
3571 if (b43_nphy_ipa(dev))
3572 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3573 }
3574 } else {
3575 if (b43_nphy_ipa(dev)) {
3576 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3577 b43_radio_write(dev,
3578 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3579 b43_radio_write(dev,
3580 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3581 } else {
3582 b43_radio_write(dev,
3583 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3584 b43_radio_write(dev,
3585 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3586 }
3587 }
3588 }
3589
3590 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3591 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3592 b43_read32(dev, B43_MMIO_MACCTL);
3593 udelay(1);
3594 }
3595
3596 if (dev->phy.rev >= 7) {
3597 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3598 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3599 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3600 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3601 } else {
3602 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3603 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3604 if (dev->phy.rev > 1)
3605 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3606 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3607 }
3608
3609 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3610 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3611
3612 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3613 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3614 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3615 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3616 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3617 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3618 B43_NPHY_TXPCTL_ITSSI_BINF);
3619 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3620 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3621 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3622
3623 for (c = 0; c < 2; c++) {
3624 for (i = 0; i < 64; i++) {
3625 num = 8 * (16 * b0[c] + b1[c] * i);
3626 den = 32768 + a1[c] * i;
3627 pwr = max((4 * num + den / 2) / den, -8);
3628 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3629 pwr = max(pwr, target[c] + 1);
3630 regval[i] = pwr;
3631 }
3632 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3633 }
3634
3635 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3636 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3637 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3638
3639 if (nphy->hang_avoid)
3640 b43_nphy_stay_in_carrier_search(dev, false);
3641}
3642
0eff8fcd
RM		 3643static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3644{
3645 struct b43_phy *phy = &dev->phy;
67cbc3ed 3646
0eff8fcd 3647 const u32 *table = NULL;
0eff8fcd
RM		 3648 u32 rfpwr_offset;
3649 u8 pga_gain;
3650 int i;
0eff8fcd 3651
aeab5751 3652 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3653 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3654 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3655
3656 if (phy->rev >= 3) {
3657#if 0
3658 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3659#endif
0eff8fcd
RM		 3660
3661 for (i = 0; i < 128; i++) {
3662 pga_gain = (table[i] >> 24) & 0xF;
3663 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3664 rfpwr_offset =
3665 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3666 else
34c5cf20
RM		 3667 rfpwr_offset =
3668 0; /* FIXME */
0eff8fcd
RM		 3669 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3670 rfpwr_offset);
3671 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3672 rfpwr_offset);
3673 }
67cbc3ed
RM		 3674 }
3675}
3676
e50cbcf6
RM		 3677/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3678static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3679{
e50cbcf6
RM		 3680 struct b43_phy_n *nphy = dev->phy.n;
3681 enum ieee80211_band band;
3682 u16 tmp;
95b66bad 3683
e50cbcf6
RM		 3684 if (!enable) {
3685 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3686 B43_NPHY_RFCTL_INTC1);
3687 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3688 B43_NPHY_RFCTL_INTC2);
3689 band = b43_current_band(dev->wl);
3690 if (dev->phy.rev >= 3) {
3691 if (band == IEEE80211_BAND_5GHZ)
3692 tmp = 0x600;
3693 else
3694 tmp = 0x480;
3695 } else {
3696 if (band == IEEE80211_BAND_5GHZ)
3697 tmp = 0x180;
3698 else
3699 tmp = 0x120;
3700 }
3701 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3702 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3703 } else {
3704 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3705 nphy->rfctrl_intc1_save);
3706 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3707 nphy->rfctrl_intc2_save);
95b66bad 3708 }
95b66bad
MB		 3709}
3710
fe3e46e8
RM		 3711/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3712static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3713{
3714 u16 tmp;
3c95627d 3715
fe3e46e8 3716 if (dev->phy.rev >= 3) {
c002831a 3717 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3718 tmp = 4;
3719 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3720 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3721 }
76b002bd 3722
fe3e46e8
RM		 3723 tmp = 1;
3724 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3725 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3726 }
3727}
76b002bd 3728
2faa6b83
RM		 3729/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3730static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3731 u16 samps, u8 time, bool wait)
3c95627d 3732{
2faa6b83
RM		 3733 int i;
3734 u16 tmp;
3c95627d 3735
2faa6b83
RM		 3736 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3737 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3738 if (wait)
3739 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3740 else
2faa6b83 3741 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3742
2faa6b83 3743 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3744
2faa6b83
RM		 3745 for (i = 1000; i; i--) {
3746 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3747 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3748 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3749 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3750 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3751 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3752 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3753 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3754
2faa6b83
RM		 3755 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3756 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3757 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3758 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3759 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3760 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3761 return;
3c95627d 3762 }
2faa6b83 3763 udelay(10);
3c95627d 3764 }
2faa6b83 3765 memset(est, 0, sizeof(*est));
3c95627d
RM		 3766}
3767
a67162ab
RM		 3768/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3769static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3770 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3771{
a67162ab
RM		 3772 if (write) {
3773 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3774 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3775 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3776 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3777 } else {
a67162ab
RM		 3778 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3779 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3780 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3781 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3782 }
3783}
6e3b15a9 3784
c7455cf9
RM		 3785#if 0
3786/* Ready but not used anywhere */
026816fc
RM		 3787/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3788static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3789{
3790 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3791
026816fc
RM		 3792 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3793 if (core == 0) {
3794 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3795 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3796 } else {
3797 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3798 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3799 }
3800 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3801 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3802 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3803 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3804 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3805 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3806 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3807 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3808}
6e3b15a9 3809
026816fc
RM		 3810/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3811static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3812{
3813 u8 rxval, txval;
3814 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3815
026816fc
RM		 3816 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3817 if (core == 0) {
3818 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3819 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3820 } else {
3821 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3822 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3823 }
3824 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3825 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3826 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3827 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3828 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3829 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3830 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3831 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3832
026816fc
RM		 3833 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3834 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3835
acd82aa8
LF		 3836 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3837 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3838 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3839 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3840 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3841 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3842 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3843 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3844 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3845
026816fc
RM		 3846 if (core == 0) {
3847 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3848 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3849 } else {
3850 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3851 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3852 }
6e3b15a9 3853
89e43dad 3854 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3855 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3856 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3857
026816fc
RM		 3858 if (core == 0) {
3859 rxval = 1;
3860 txval = 8;
3861 } else {
3862 rxval = 4;
3863 txval = 2;
6e3b15a9 3864 }
89e43dad
RM		 3865 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3866 core + 1);
3867 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3868 2 - core);
99b82c41 3869}
c7455cf9 3870#endif
99b82c41 3871
34a56f2c
RM		 3872/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3873static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3874{
3875 int i;
34a56f2c
RM		 3876 s32 iq;
3877 u32 ii;
3878 u32 qq;
3879 int iq_nbits, qq_nbits;
3880 int arsh, brsh;
3881 u16 tmp, a, b;
3882
3883 struct nphy_iq_est est;
3884 struct b43_phy_n_iq_comp old;
3885 struct b43_phy_n_iq_comp new = { };
3886 bool error = false;
3887
3888 if (mask == 0)
3889 return;
3890
3891 b43_nphy_rx_iq_coeffs(dev, false, &old);
3892 b43_nphy_rx_iq_coeffs(dev, true, &new);
3893 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3894 new = old;
3895
dfb4aa5d 3896 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3897 if (i == 0 && (mask & 1)) {
3898 iq = est.iq0_prod;
3899 ii = est.i0_pwr;
3900 qq = est.q0_pwr;
3901 } else if (i == 1 && (mask & 2)) {
3902 iq = est.iq1_prod;
3903 ii = est.i1_pwr;
3904 qq = est.q1_pwr;
dfb4aa5d 3905 } else {
34a56f2c 3906 continue;
dfb4aa5d 3907 }
dfb4aa5d 3908
34a56f2c
RM		 3909 if (ii + qq < 2) {
3910 error = true;
3911 break;
3912 }
dfb4aa5d 3913
34a56f2c
RM		 3914 iq_nbits = fls(abs(iq));
3915 qq_nbits = fls(qq);
dfb4aa5d 3916
34a56f2c
RM		 3917 arsh = iq_nbits - 20;
3918 if (arsh >= 0) {
3919 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3920 tmp = ii >> arsh;
3921 } else {
3922 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3923 tmp = ii << -arsh;
3924 }
3925 if (tmp == 0) {
3926 error = true;
3927 break;
3928 }
3929 a /= tmp;
dfb4aa5d 3930
34a56f2c
RM		 3931 brsh = qq_nbits - 11;
3932 if (brsh >= 0) {
3933 b = (qq << (31 - qq_nbits));
3934 tmp = ii >> brsh;
dfb4aa5d 3935 } else {
34a56f2c
RM		 3936 b = (qq << (31 - qq_nbits));
3937 tmp = ii << -brsh;
3938 }
3939 if (tmp == 0) {
3940 error = true;
3941 break;
dfb4aa5d 3942 }
34a56f2c 3943 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3944
34a56f2c
RM		 3945 if (i == 0 && (mask & 0x1)) {
3946 if (dev->phy.rev >= 3) {
3947 new.a0 = a & 0x3FF;
3948 new.b0 = b & 0x3FF;
3949 } else {
3950 new.a0 = b & 0x3FF;
3951 new.b0 = a & 0x3FF;
3952 }
3953 } else if (i == 1 && (mask & 0x2)) {
3954 if (dev->phy.rev >= 3) {
3955 new.a1 = a & 0x3FF;
3956 new.b1 = b & 0x3FF;
3957 } else {
3958 new.a1 = b & 0x3FF;
3959 new.b1 = a & 0x3FF;
3960 }
3961 }
dfb4aa5d 3962 }
dfb4aa5d 3963
34a56f2c
RM		 3964 if (error)
3965 new = old;
dfb4aa5d 3966
34a56f2c
RM		 3967 b43_nphy_rx_iq_coeffs(dev, true, &new);
3968}
dfb4aa5d 3969
09146400
RM		 3970/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3971static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3972{
3973 u16 array[4];
44f4008b 3974 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3975
3976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3978 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3979 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3980}
3981
9442e5b5
RM		 3982/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3983static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3984{
3985 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3986
204a665b 3987 u8 channel = dev->phy.channel;
9442e5b5
RM		 3988 int tone[2] = { 57, 58 };
3989 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3990
9442e5b5 3991 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3992
9442e5b5
RM		 3993 if (nphy->hang_avoid)
3994 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3995
9442e5b5
RM		 3996 if (nphy->gband_spurwar_en) {
3997 /* TODO: N PHY Adjust Analog Pfbw (7) */
bee6d4b2 3998 if (channel == 11 && b43_is_40mhz(dev))
9442e5b5
RM		 3999 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4000 else
4001 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4002 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4003 }
4004
9442e5b5
RM		 4005 if (nphy->aband_spurwar_en) {
4006 if (channel == 54) {
4007 tone[0] = 0x20;
4008 noise[0] = 0x25F;
4009 } else if (channel == 38 || channel == 102 || channel == 118) {
4010 if (0 /* FIXME */) {
4011 tone[0] = 0x20;
4012 noise[0] = 0x21F;
4013 } else {
4014 tone[0] = 0;
4015 noise[0] = 0;
90b9738d 4016 }
9442e5b5
RM		 4017 } else if (channel == 134) {
4018 tone[0] = 0x20;
4019 noise[0] = 0x21F;
4020 } else if (channel == 151) {
4021 tone[0] = 0x10;
4022 noise[0] = 0x23F;
4023 } else if (channel == 153 || channel == 161) {
4024 tone[0] = 0x30;
4025 noise[0] = 0x23F;
4026 } else {
4027 tone[0] = 0;
4028 noise[0] = 0;
90b9738d 4029 }
90b9738d 4030
9442e5b5
RM		 4031 if (!tone[0] && !noise[0])
4032 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4033 else
9442e5b5
RM		 4034 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4035 }
90b9738d 4036
9442e5b5
RM		 4037 if (nphy->hang_avoid)
4038 b43_nphy_stay_in_carrier_search(dev, 0);
4039}
90b9738d 4040
5ecab603
RM		 4041/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4042static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4043{
4044 struct b43_phy_n *nphy = dev->phy.n;
4045 int i, j;
4046 u32 tmp;
4047 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4048
5ecab603 4049 u16 buffer[7];
90b9738d 4050
5ecab603
RM		 4051 if (nphy->hang_avoid)
4052 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4053
5ecab603 4054 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4055
5ecab603
RM		 4056 for (i = 0; i < 2; i++) {
4057 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4058 (buffer[i * 2 + 1] & 0x3FF);
4059 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4060 (((i + 26) << 10) | 320));
4061 for (j = 0; j < 128; j++) {
4062 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4063 ((tmp >> 16) & 0xFFFF));
4064 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4065 (tmp & 0xFFFF));
90b9738d 4066 }
90b9738d 4067 }
90b9738d 4068
5ecab603
RM		 4069 for (i = 0; i < 2; i++) {
4070 tmp = buffer[5 + i];
4071 real_part = (tmp >> 8) & 0xFF;
4072 imag_part = (tmp & 0xFF);
4073 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4074 (((i + 26) << 10) | 448));
90b9738d 4075
5ecab603
RM		 4076 if (dev->phy.rev >= 3) {
4077 cur_real = real_part;
4078 cur_imag = imag_part;
4079 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4080 }
4cb99775 4081
5ecab603
RM		 4082 for (j = 0; j < 128; j++) {
4083 if (dev->phy.rev < 3) {
4084 cur_real = (real_part * loscale[j] + 128) >> 8;
4085 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4086 tmp = ((cur_real & 0xFF) << 8) |
4087 (cur_imag & 0xFF);
4088 }
4089 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4090 ((tmp >> 16) & 0xFFFF));
4091 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4092 (tmp & 0xFFFF));
4093 }
90b9738d 4094 }
4cb99775 4095
4cb99775 4096 if (dev->phy.rev >= 3) {
5ecab603
RM		 4097 b43_shm_write16(dev, B43_SHM_SHARED,
4098 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4099 b43_shm_write16(dev, B43_SHM_SHARED,
4100 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4101 }
90b9738d 4102
5ecab603
RM		 4103 if (nphy->hang_avoid)
4104 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4105}
4106
42e1547e
RM		 4107/*
4108 * Restore RSSI Calibration
4109 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4110 */
4111static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4112{
4113 struct b43_phy_n *nphy = dev->phy.n;
4114
4115 u16 *rssical_radio_regs = NULL;
4116 u16 *rssical_phy_regs = NULL;
4117
4118 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4119 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4120 return;
4121 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4122 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4123 } else {
204a665b 4124 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4125 return;
4126 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4127 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4128 }
4129
9a98979e
RM		 4130 if (dev->phy.rev >= 7) {
4131 } else {
4132 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4133 rssical_radio_regs[0]);
4134 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4135 rssical_radio_regs[1]);
4136 }
42e1547e
RM		 4137
4138 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4139 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4140 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4141 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4142
4143 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4144 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4145 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4146 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4147
4148 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4149 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4150 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4151 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4152}
4153
c4a92003
RM		 4154/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4155static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4156{
4157 struct b43_phy_n *nphy = dev->phy.n;
4158 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4159 u16 tmp;
4160 u8 offset, i;
c4a92003
RM		 4161
4162 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4163 for (i = 0; i < 2; i++) {
4164 tmp = (i == 0) ? 0x2000 : 0x3000;
4165 offset = i * 11;
4166
0c201cfb
RM		 4167 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4168 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4169 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4170 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4171 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4172 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4173 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4174 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4175 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4176 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4177 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4178
4179 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4180 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4181 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4182 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4183 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4184 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4185 if (nphy->ipa5g_on) {
0c201cfb
RM		 4186 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4187 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4188 } else {
0c201cfb
RM		 4189 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4190 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4191 }
0c201cfb 4192 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4193 } else {
0c201cfb
RM		 4194 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4195 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4196 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4197 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4198 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4199 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4200 if (nphy->ipa2g_on) {
0c201cfb
RM		 4201 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4202 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4203 (dev->phy.rev < 5) ? 0x11 : 0x01);
4204 } else {
0c201cfb
RM		 4205 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4206 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4207 }
4208 }
0c201cfb
RM		 4209 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4210 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4211 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4212 }
c4a92003 4213 } else {
0c201cfb
RM		 4214 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4215 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4216
0c201cfb
RM		 4217 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4218 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4219
0c201cfb
RM		 4220 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4221 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4222
0c201cfb
RM		 4223 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4224 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4225
0c201cfb
RM		 4226 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4227 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4228
4229 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4230 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4231 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4232 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4233 } else {
0c201cfb
RM		 4234 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4235 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4236 }
4237
4238 if (dev->phy.rev < 2) {
4239 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4240 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4241 } else {
4242 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4243 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4244 }
4245 }
4246}
4247
de7ed0c6
RM		 4248/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4249static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4250{
4251 struct b43_phy_n *nphy = dev->phy.n;
4252 int i;
4253 u16 scale, entry;
4254
4255 u16 tmp = nphy->txcal_bbmult;
4256 if (core == 0)
4257 tmp >>= 8;
4258 tmp &= 0xff;
4259
4260 for (i = 0; i < 18; i++) {
4261 scale = (ladder_lo[i].percent * tmp) / 100;
4262 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4263 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4264
4265 scale = (ladder_iq[i].percent * tmp) / 100;
4266 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4267 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4268 }
4269}
4270
45ca697e
RM		 4271/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4272static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4273{
4274 int i;
4275 for (i = 0; i < 15; i++)
4276 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4277 tbl_tx_filter_coef_rev4[2][i]);
4278}
4279
4280/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4281static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4282{
4283 int i, j;
4284 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4285 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4286
4287 for (i = 0; i < 3; i++)
4288 for (j = 0; j < 15; j++)
4289 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4290 tbl_tx_filter_coef_rev4[i][j]);
4291
bee6d4b2 4292 if (b43_is_40mhz(dev)) {
45ca697e
RM		 4293 for (j = 0; j < 15; j++)
4294 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4295 tbl_tx_filter_coef_rev4[3][j]);
4296 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4297 for (j = 0; j < 15; j++)
4298 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4299 tbl_tx_filter_coef_rev4[5][j]);
4300 }
4301
4302 if (dev->phy.channel == 14)
4303 for (j = 0; j < 15; j++)
4304 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4305 tbl_tx_filter_coef_rev4[6][j]);
4306}
4307
b0022e15
RM		 4308/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4309static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4310{
4311 struct b43_phy_n *nphy = dev->phy.n;
4312
4313 u16 curr_gain[2];
4314 struct nphy_txgains target;
4315 const u32 *table = NULL;
4316
161d540c 4317 if (!nphy->txpwrctrl) {
b0022e15
RM		 4318 int i;
4319
4320 if (nphy->hang_avoid)
4321 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4322 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4323 if (nphy->hang_avoid)
4324 b43_nphy_stay_in_carrier_search(dev, false);
4325
4326 for (i = 0; i < 2; ++i) {
4327 if (dev->phy.rev >= 3) {
4328 target.ipa[i] = curr_gain[i] & 0x000F;
4329 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4330 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4331 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4332 } else {
4333 target.ipa[i] = curr_gain[i] & 0x0003;
4334 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4335 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4336 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4337 }
4338 }
4339 } else {
4340 int i;
4341 u16 index[2];
4342 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4343 B43_NPHY_TXPCTL_STAT_BIDX) >>
4344 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4345 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4346 B43_NPHY_TXPCTL_STAT_BIDX) >>
4347 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4348
4349 for (i = 0; i < 2; ++i) {
aeab5751 4350 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4351 if (dev->phy.rev >= 3) {
b0022e15
RM		 4352 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4353 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4354 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4355 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4356 } else {
b0022e15
RM		 4357 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4358 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4359 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4360 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4361 }
4362 }
4363 }
4364
4365 return target;
4366}
4367
e53de674
RM		 4368/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4369static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4370{
4371 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4372
4373 if (dev->phy.rev >= 3) {
4374 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4375 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4376 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4377 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4378 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4379 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4380 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4381 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4383 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4384 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4385 b43_nphy_reset_cca(dev);
4386 } else {
4387 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4388 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4389 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4390 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4391 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4392 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4393 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4394 }
4395}
4396
4397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4398static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4399{
4400 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4401 u16 tmp;
4402
4403 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4404 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4405 if (dev->phy.rev >= 3) {
4406 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4407 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4408
4409 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4410 regs[2] = tmp;
4411 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4412
4413 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4414 regs[3] = tmp;
4415 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4416
4417 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4418 b43_phy_mask(dev, B43_NPHY_BBCFG,
4419 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4420
c643a66e 4421 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4422 regs[5] = tmp;
d41a3552 4423 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4424
4425 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4426 regs[6] = tmp;
d41a3552 4427 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4428 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4429 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4430
89e43dad
RM		 4431 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4432 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4433 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4434
4435 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4436 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4437 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4438 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4439 } else {
4440 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4441 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4442 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4443 regs[2] = tmp;
4444 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4445 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4446 regs[3] = tmp;
4447 tmp |= 0x2000;
d41a3552 4448 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4449 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4450 regs[4] = tmp;
4451 tmp |= 0x2000;
d41a3552 4452 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4453 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4454 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4455 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4456 tmp = 0x0180;
4457 else
4458 tmp = 0x0120;
4459 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4460 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4461 }
4462}
4463
bbc6dc12
RM		 4464/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4465static void b43_nphy_save_cal(struct b43_wldev *dev)
4466{
4467 struct b43_phy_n *nphy = dev->phy.n;
4468
4469 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4470 u16 *txcal_radio_regs = NULL;
902db91d 4471 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4472 u16 *table = NULL;
4473
4474 if (nphy->hang_avoid)
4475 b43_nphy_stay_in_carrier_search(dev, 1);
4476
4477 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4478 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4479 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4480 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4481 table = nphy->cal_cache.txcal_coeffs_2G;
4482 } else {
4483 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4484 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4485 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4486 table = nphy->cal_cache.txcal_coeffs_5G;
4487 }
4488
4489 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4490 /* TODO use some definitions */
4491 if (dev->phy.rev >= 3) {
4492 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4493 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4494 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4495 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4496 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4497 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4498 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4499 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4500 } else {
4501 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4502 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4503 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4504 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4505 }
39e971ef 4506 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq;
204a665b 4507 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4508 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4509
4510 if (nphy->hang_avoid)
4511 b43_nphy_stay_in_carrier_search(dev, 0);
4512}
4513
2f258b74
RM		 4514/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4515static void b43_nphy_restore_cal(struct b43_wldev *dev)
4516{
4517 struct b43_phy_n *nphy = dev->phy.n;
4518
4519 u16 coef[4];
4520 u16 *loft = NULL;
4521 u16 *table = NULL;
4522
4523 int i;
4524 u16 *txcal_radio_regs = NULL;
4525 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4526
4527 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4528 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4529 return;
4530 table = nphy->cal_cache.txcal_coeffs_2G;
4531 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4532 } else {
204a665b 4533 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4534 return;
4535 table = nphy->cal_cache.txcal_coeffs_5G;
4536 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4537 }
4538
2581b143 4539 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4540
4541 for (i = 0; i < 4; i++) {
4542 if (dev->phy.rev >= 3)
4543 table[i] = coef[i];
4544 else
4545 coef[i] = 0;
4546 }
4547
2581b143
RM		 4548 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4550 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4551
4552 if (dev->phy.rev < 2)
4553 b43_nphy_tx_iq_workaround(dev);
4554
4555 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4556 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4557 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4558 } else {
4559 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4560 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4561 }
4562
4563 /* TODO use some definitions */
4564 if (dev->phy.rev >= 3) {
4565 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4566 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4567 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4568 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4569 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4570 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4571 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4572 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4573 } else {
4574 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4575 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4576 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4577 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4578 }
4579 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4580}
4581
fb43b8e2
RM		 4582/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4583static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4584 struct nphy_txgains target,
4585 bool full, bool mphase)
4586{
39e971ef 4587 struct b43_phy *phy = &dev->phy;
fb43b8e2
RM		 4588 struct b43_phy_n *nphy = dev->phy.n;
4589 int i;
4590 int error = 0;
4591 int freq;
4592 bool avoid = false;
4593 u8 length;
fb23d863 4594 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4595 const u16 *table;
4596 bool phy6or5x;
4597
4598 u16 buffer[11];
4599 u16 diq_start = 0;
4600 u16 save[2];
4601 u16 gain[2];
4602 struct nphy_iqcal_params params[2];
4603 bool updated[2] = { };
4604
4605 b43_nphy_stay_in_carrier_search(dev, true);
4606
4607 if (dev->phy.rev >= 4) {
4608 avoid = nphy->hang_avoid;
3db1cd5c 4609 nphy->hang_avoid = false;
fb43b8e2
RM		 4610 }
4611
9145834e 4612 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4613
4614 for (i = 0; i < 2; i++) {
4615 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4616 gain[i] = params[i].cal_gain;
4617 }
2581b143
RM		 4618
4619 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4620
4621 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4622 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4623
4624 phy6or5x = dev->phy.rev >= 6 ||
4625 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4626 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4627 if (phy6or5x) {
bee6d4b2 4628 if (b43_is_40mhz(dev)) {
38bb9029
RM		 4629 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4630 tbl_tx_iqlo_cal_loft_ladder_40);
4631 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4632 tbl_tx_iqlo_cal_iqimb_ladder_40);
4633 } else {
4634 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4635 tbl_tx_iqlo_cal_loft_ladder_20);
4636 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4637 tbl_tx_iqlo_cal_iqimb_ladder_20);
4638 }
fb43b8e2
RM		 4639 }
4640
4641 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4642
bee6d4b2 4643 if (!b43_is_40mhz(dev))
fb43b8e2
RM		 4644 freq = 2500;
4645 else
4646 freq = 5000;
4647
4648 if (nphy->mphase_cal_phase_id > 2)
bee6d4b2 4649 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
10a79873 4650 0xFFFF, 0, true, false);
fb43b8e2 4651 else
59af099b 4652 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4653
4654 if (error == 0) {
4655 if (nphy->mphase_cal_phase_id > 2) {
4656 table = nphy->mphase_txcal_bestcoeffs;
4657 length = 11;
4658 if (dev->phy.rev < 3)
4659 length -= 2;
4660 } else {
4661 if (!full && nphy->txiqlocal_coeffsvalid) {
4662 table = nphy->txiqlocal_bestc;
4663 length = 11;
4664 if (dev->phy.rev < 3)
4665 length -= 2;
4666 } else {
4667 full = true;
4668 if (dev->phy.rev >= 3) {
4669 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4670 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4671 } else {
4672 table = tbl_tx_iqlo_cal_startcoefs;
4673 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4674 }
4675 }
4676 }
4677
2581b143 4678 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4679
4680 if (full) {
4681 if (dev->phy.rev >= 3)
4682 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4683 else
4684 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4685 } else {
4686 if (dev->phy.rev >= 3)
4687 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4688 else
4689 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4690 }
4691
4692 if (mphase) {
4693 count = nphy->mphase_txcal_cmdidx;
4694 numb = min(max,
4695 (u16)(count + nphy->mphase_txcal_numcmds));
4696 } else {
4697 count = 0;
4698 numb = max;
4699 }
4700
4701 for (; count < numb; count++) {
4702 if (full) {
4703 if (dev->phy.rev >= 3)
4704 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4705 else
4706 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4707 } else {
4708 if (dev->phy.rev >= 3)
4709 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4710 else
4711 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4712 }
4713
4714 core = (cmd & 0x3000) >> 12;
4715 type = (cmd & 0x0F00) >> 8;
4716
4717 if (phy6or5x && updated[core] == 0) {
4718 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4719 updated[core] = true;
fb43b8e2
RM		 4720 }
4721
4722 tmp = (params[core].ncorr[type] << 8) | 0x66;
4723 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4724
4725 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4726 buffer[0] = b43_ntab_read(dev,
4727 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4728 diq_start = buffer[0];
4729 buffer[0] = 0;
d41a3552
RM		 4730 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4731 0);
fb43b8e2
RM		 4732 }
4733
4734 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4735 for (i = 0; i < 2000; i++) {
4736 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4737 if (tmp & 0xC000)
4738 break;
4739 udelay(10);
4740 }
4741
9145834e
RM		 4742 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4743 buffer);
2581b143
RM		 4744 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4745 buffer);
fb43b8e2
RM		 4746
4747 if (type == 1 || type == 3 || type == 4)
4748 buffer[0] = diq_start;
4749 }
4750
4751 if (mphase)
4752 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4753
4754 last = (dev->phy.rev < 3) ? 6 : 7;
4755
4756 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4757 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4758 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4759 if (dev->phy.rev < 3) {
4760 buffer[0] = 0;
4761 buffer[1] = 0;
4762 buffer[2] = 0;
4763 buffer[3] = 0;
4764 }
2581b143
RM		 4765 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4766 buffer);
bc53e512 4767 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4768 buffer);
4769 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4770 buffer);
4771 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4772 buffer);
fb43b8e2
RM		 4773 length = 11;
4774 if (dev->phy.rev < 3)
4775 length -= 2;
9145834e
RM		 4776 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4777 nphy->txiqlocal_bestc);
fb43b8e2 4778 nphy->txiqlocal_coeffsvalid = true;
204a665b 4779 nphy->txiqlocal_chanspec.center_freq =
39e971ef 4780 phy->chandef->chan->center_freq;
204a665b
RM		 4781 nphy->txiqlocal_chanspec.channel_type =
4782 dev->phy.channel_type;
fb43b8e2
RM		 4783 } else {
4784 length = 11;
4785 if (dev->phy.rev < 3)
4786 length -= 2;
9145834e
RM		 4787 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4788 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4789 }
4790
53ae8e8c 4791 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4792 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4793 }
4794
e53de674 4795 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4796 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4797
4798 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4799 b43_nphy_tx_iq_workaround(dev);
4800
4801 if (dev->phy.rev >= 4)
4802 nphy->hang_avoid = avoid;
4803
4804 b43_nphy_stay_in_carrier_search(dev, false);
4805
4806 return error;
4807}
4808
984ff4ff
RM		 4809/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4810static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4811{
4812 struct b43_phy_n *nphy = dev->phy.n;
4813 u8 i;
4814 u16 buffer[7];
4815 bool equal = true;
4816
902db91d 4817 if (!nphy->txiqlocal_coeffsvalid ||
39e971ef 4818 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq ||
204a665b 4819 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4820 return;
4821
4822 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4823 for (i = 0; i < 4; i++) {
4824 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4825 equal = false;
4826 break;
4827 }
4828 }
4829
4830 if (!equal) {
4831 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4832 nphy->txiqlocal_bestc);
4833 for (i = 0; i < 4; i++)
4834 buffer[i] = 0;
4835 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4836 buffer);
4837 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4838 &nphy->txiqlocal_bestc[5]);
4839 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4840 &nphy->txiqlocal_bestc[5]);
4841 }
4842}
4843
15931e31
RM		 4844/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4845static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4846 struct nphy_txgains target, u8 type, bool debug)
4847{
4848 struct b43_phy_n *nphy = dev->phy.n;
4849 int i, j, index;
4850 u8 rfctl[2];
4851 u8 afectl_core;
4852 u16 tmp[6];
c7455cf9 4853 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4854 u32 real, imag;
4855 enum ieee80211_band band;
4856
4857 u8 use;
4858 u16 cur_hpf;
4859 u16 lna[3] = { 3, 3, 1 };
4860 u16 hpf1[3] = { 7, 2, 0 };
4861 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4862 u32 power[3] = { };
15931e31
RM		 4863 u16 gain_save[2];
4864 u16 cal_gain[2];
4865 struct nphy_iqcal_params cal_params[2];
4866 struct nphy_iq_est est;
4867 int ret = 0;
4868 bool playtone = true;
4869 int desired = 13;
4870
4871 b43_nphy_stay_in_carrier_search(dev, 1);
4872
4873 if (dev->phy.rev < 2)
984ff4ff 4874 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4875 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4876 for (i = 0; i < 2; i++) {
4877 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4878 cal_gain[i] = cal_params[i].cal_gain;
4879 }
2581b143 4880 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4881
4882 for (i = 0; i < 2; i++) {
4883 if (i == 0) {
4884 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4885 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4886 afectl_core = B43_NPHY_AFECTL_C1;
4887 } else {
4888 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4889 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4890 afectl_core = B43_NPHY_AFECTL_C2;
4891 }
4892
4893 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4894 tmp[2] = b43_phy_read(dev, afectl_core);
4895 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4896 tmp[4] = b43_phy_read(dev, rfctl[0]);
4897 tmp[5] = b43_phy_read(dev, rfctl[1]);
4898
4899 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4900 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4901 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4902 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4903 (1 - i));
4904 b43_phy_set(dev, afectl_core, 0x0006);
4905 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4906
4907 band = b43_current_band(dev->wl);
4908
4909 if (nphy->rxcalparams & 0xFF000000) {
4910 if (band == IEEE80211_BAND_5GHZ)
4911 b43_phy_write(dev, rfctl[0], 0x140);
4912 else
4913 b43_phy_write(dev, rfctl[0], 0x110);
4914 } else {
4915 if (band == IEEE80211_BAND_5GHZ)
4916 b43_phy_write(dev, rfctl[0], 0x180);
4917 else
4918 b43_phy_write(dev, rfctl[0], 0x120);
4919 }
4920
4921 if (band == IEEE80211_BAND_5GHZ)
4922 b43_phy_write(dev, rfctl[1], 0x148);
4923 else
4924 b43_phy_write(dev, rfctl[1], 0x114);
4925
4926 if (nphy->rxcalparams & 0x10000) {
4927 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4928 (i + 1));
4929 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4930 (2 - i));
4931 }
4932
30115c22 4933 for (j = 0; j < 4; j++) {
15931e31
RM		 4934 if (j < 3) {
4935 cur_lna = lna[j];
4936 cur_hpf1 = hpf1[j];
4937 cur_hpf2 = hpf2[j];
4938 } else {
4939 if (power[1] > 10000) {
4940 use = 1;
4941 cur_hpf = cur_hpf1;
4942 index = 2;
4943 } else {
4944 if (power[0] > 10000) {
4945 use = 1;
4946 cur_hpf = cur_hpf1;
4947 index = 1;
4948 } else {
4949 index = 0;
4950 use = 2;
4951 cur_hpf = cur_hpf2;
4952 }
4953 }
4954 cur_lna = lna[index];
4955 cur_hpf1 = hpf1[index];
4956 cur_hpf2 = hpf2[index];
4957 cur_hpf += desired - hweight32(power[index]);
4958 cur_hpf = clamp_val(cur_hpf, 0, 10);
4959 if (use == 1)
4960 cur_hpf1 = cur_hpf;
4961 else
4962 cur_hpf2 = cur_hpf;
4963 }
4964
4965 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4966 (cur_lna << 2));
78ae7532 4967 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 4968 false);
de9a47f9 4969 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4970 b43_nphy_stop_playback(dev);
15931e31
RM		 4971
4972 if (playtone) {
59af099b
RM		 4973 ret = b43_nphy_tx_tone(dev, 4000,
4974 (nphy->rxcalparams & 0xFFFF),
4975 false, false);
15931e31
RM		 4976 playtone = false;
4977 } else {
10a79873
RM		 4978 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4979 false, false);
15931e31
RM		 4980 }
4981
4982 if (ret == 0) {
4983 if (j < 3) {
4984 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4985 false);
4986 if (i == 0) {
4987 real = est.i0_pwr;
4988 imag = est.q0_pwr;
4989 } else {
4990 real = est.i1_pwr;
4991 imag = est.q1_pwr;
4992 }
4993 power[i] = ((real + imag) / 1024) + 1;
4994 } else {
4995 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4996 }
53ae8e8c 4997 b43_nphy_stop_playback(dev);
15931e31
RM		 4998 }
4999
5000 if (ret != 0)
5001 break;
5002 }
5003
5004 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5005 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5006 b43_phy_write(dev, rfctl[1], tmp[5]);
5007 b43_phy_write(dev, rfctl[0], tmp[4]);
5008 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5009 b43_phy_write(dev, afectl_core, tmp[2]);
5010 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5011
5012 if (ret != 0)
5013 break;
5014 }
5015
78ae7532 5016 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5017 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5018 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5019
5020 b43_nphy_stay_in_carrier_search(dev, 0);
5021
5022 return ret;
5023}
5024
5025static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5026 struct nphy_txgains target, u8 type, bool debug)
5027{
5028 return -1;
5029}
5030
5031/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5032static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5033 struct nphy_txgains target, u8 type, bool debug)
5034{
5035 if (dev->phy.rev >= 3)
5036 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5037 else
5038 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5039}
5040
4e687b22
GS		 5041/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5042static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5043{
5044 struct b43_phy *phy = &dev->phy;
5045 struct b43_phy_n *nphy = phy->n;
0b81c23d 5046 /* u16 buf[16]; it's rev3+ */
4e687b22 5047
049fbfee
RM		 5048 nphy->phyrxchain = mask;
5049
4e687b22
GS		 5050 if (0 /* FIXME clk */)
5051 return;
5052
5053 b43_mac_suspend(dev);
5054
5055 if (nphy->hang_avoid)
5056 b43_nphy_stay_in_carrier_search(dev, true);
5057
5058 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5059 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5060
049fbfee 5061 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5062 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5063 if (dev->phy.rev >= 3) {
5064 /* TODO */
5065 }
5066 } else {
5067 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5068 if (dev->phy.rev >= 3) {
5069 /* TODO */
5070 }
5071 }
5072
5073 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5074
5075 if (nphy->hang_avoid)
5076 b43_nphy_stay_in_carrier_search(dev, false);
5077
5078 b43_mac_enable(dev);
5079}
5080
104cfa88
RM		 5081/**************************************************
5082 * N-PHY init
5083 **************************************************/
5084
104cfa88
RM		 5085/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5086static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5087{
5088 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5089
5090 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5091 if (preamble == 1)
5092 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5093 else
5094 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5095
5096 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5097}
5098
5099/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5100static void b43_nphy_bphy_init(struct b43_wldev *dev)
5101{
5102 unsigned int i;
5103 u16 val;
5104
5105 val = 0x1E1F;
5106 for (i = 0; i < 16; i++) {
5107 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5108 val -= 0x202;
5109 }
5110 val = 0x3E3F;
5111 for (i = 0; i < 16; i++) {
5112 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5113 val -= 0x202;
5114 }
5115 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5116}
5117
5118/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5119static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5120{
5121 if (dev->phy.rev >= 3) {
5122 if (!init)
5123 return;
5124 if (0 /* FIXME */) {
5125 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5126 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5127 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5128 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5129 }
5130 } else {
5131 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5132 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5133
5134 switch (dev->dev->bus_type) {
5135#ifdef CONFIG_B43_BCMA
5136 case B43_BUS_BCMA:
5137 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5138 0xFC00, 0xFC00);
5139 break;
5140#endif
5141#ifdef CONFIG_B43_SSB
5142 case B43_BUS_SSB:
5143 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5144 0xFC00, 0xFC00);
5145 break;
5146#endif
5147 }
5148
5056635c
RM		 5149 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5150 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5151 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5152 0);
104cfa88
RM		 5153
5154 if (init) {
5155 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5156 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5157 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5158 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5159 }
5160 }
5161}
5162
5163/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5164static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5165{
0581483a 5166 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5167 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5168 struct b43_phy_n *nphy = phy->n;
5169 u8 tx_pwr_state;
5170 struct nphy_txgains target;
95b66bad 5171 u16 tmp;
0988a7a1
RM		 5172 enum ieee80211_band tmp2;
5173 bool do_rssi_cal;
5174
5175 u16 clip[2];
5176 bool do_cal = false;
95b66bad 5177
0988a7a1 5178 if ((dev->phy.rev >= 3) &&
0581483a 5179 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5180 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5181 switch (dev->dev->bus_type) {
42c9a458
RM		 5182#ifdef CONFIG_B43_BCMA
5183 case B43_BUS_BCMA:
5184 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5185 BCMA_CC_CHIPCTL, 0x40);
5186 break;
5187#endif
6cbab0d9
RM		 5188#ifdef CONFIG_B43_SSB
5189 case B43_BUS_SSB:
5190 chipco_set32(&dev->dev->sdev->bus->chipco,
5191 SSB_CHIPCO_CHIPCTL, 0x40);
5192 break;
5193#endif
5194 }
0988a7a1
RM		 5195 }
5196 nphy->deaf_count = 0;
95b66bad 5197 b43_nphy_tables_init(dev);
0988a7a1
RM		 5198 nphy->crsminpwr_adjusted = false;
5199 nphy->noisevars_adjusted = false;
95b66bad
MB		 5200
5201 /* Clear all overrides */
0988a7a1
RM		 5202 if (dev->phy.rev >= 3) {
5203 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5204 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5205 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5206 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5207 } else {
5208 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5209 }
95b66bad
MB		 5210 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5211 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5212 if (dev->phy.rev < 6) {
5213 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5214 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5215 }
95b66bad
MB		 5216 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5217 ~(B43_NPHY_RFSEQMODE_CAOVER |
5218 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5219 if (dev->phy.rev >= 3)
5220 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5221 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5222
0988a7a1
RM		 5223 if (dev->phy.rev <= 2) {
5224 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5225 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5226 ~B43_NPHY_BPHY_CTL3_SCALE,
5227 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5228 }
95b66bad
MB		 5229 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5230 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5231
0eff8fcd 5232 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5233 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5234 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5235 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5236 else
5237 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5238 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5239 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5240 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5241
ad9716e8 5242 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5243 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5244
5245 if (phy->rev < 2) {
5246 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5247 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5248 }
0988a7a1
RM		 5249
5250 tmp2 = b43_current_band(dev->wl);
c002831a 5251 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5252 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5253 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5254 nphy->papd_epsilon_offset[0] << 7);
5255 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5256 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5257 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5258 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5259 } else if (phy->rev >= 5) {
45ca697e 5260 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5261 }
5262
95b66bad 5263 b43_nphy_workarounds(dev);
95b66bad 5264
0988a7a1 5265 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5266 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5267 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5268 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5269 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5270 b43_phy_force_clock(dev, 0);
0988a7a1 5271
858a1652 5272 b43_mac_phy_clock_set(dev, true);
0988a7a1 5273
e50cbcf6 5274 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5275 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5276 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5277 b43_nphy_pa_override(dev, true);
0988a7a1 5278
bbec398c
RM		 5279 b43_nphy_classifier(dev, 0, 0);
5280 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5281 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5282 b43_nphy_bphy_init(dev);
5283
0988a7a1 5284 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5285 b43_nphy_tx_power_ctrl(dev, false);
5286 b43_nphy_tx_power_fix(dev);
3dda07b6 5287 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5288 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5289 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5290
0988a7a1 5291 if (nphy->phyrxchain != 3)
4e687b22 5292 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5293 if (nphy->mphase_cal_phase_id > 0)
5294 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5295
5296 do_rssi_cal = false;
5297 if (phy->rev >= 3) {
5298 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5299 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5300 else
204a665b 5301 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5302
5303 if (do_rssi_cal)
4cb99775 5304 b43_nphy_rssi_cal(dev);
0988a7a1 5305 else
42e1547e 5306 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5307 } else {
4cb99775 5308 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5309 }
5310
5311 if (!((nphy->measure_hold & 0x6) != 0)) {
5312 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5313 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5314 else
204a665b 5315 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5316
5317 if (nphy->mute)
5318 do_cal = false;
5319
5320 if (do_cal) {
b0022e15 5321 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5322
5323 if (nphy->antsel_type == 2)
8987a9e9 5324 b43_nphy_superswitch_init(dev, true);
0988a7a1 5325 if (nphy->perical != 2) {
90b9738d 5326 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5327 if (phy->rev >= 3) {
5328 nphy->cal_orig_pwr_idx[0] =
5329 nphy->txpwrindex[0].index_internal;
5330 nphy->cal_orig_pwr_idx[1] =
5331 nphy->txpwrindex[1].index_internal;
5332 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5333 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5334 }
e7797bf2
RM		 5335 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5336 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5337 b43_nphy_save_cal(dev);
5338 } else if (nphy->mphase_cal_phase_id == 0)
5339 ;/* N PHY Periodic Calibration with arg 3 */
5340 } else {
5341 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5342 }
5343 }
5344
6dcd9d91 5345 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5346 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5347 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5348 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5349 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5350 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
fe3e46e8 5351 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5352 if (phy->rev >= 3)
5353 b43_nphy_spur_workaround(dev);
95b66bad 5354
53a6e234 5355 return 0;
424047e6 5356}
ef1a628d 5357
104cfa88
RM		 5358/**************************************************
5359 * Channel switching ops.
5360 **************************************************/
5361
5362static void b43_chantab_phy_upload(struct b43_wldev *dev,
5363 const struct b43_phy_n_sfo_cfg *e)
5364{
5365 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5366 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5367 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5368 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5369 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5370 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5371}
5372
49d55cef
RM		 5373/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5374static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5375{
d66be829
RM		 5376 switch (dev->dev->bus_type) {
5377#ifdef CONFIG_B43_BCMA
5378 case B43_BUS_BCMA:
9b383672
HM		 5379 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5380 avoid);
d66be829 5381 break;
8b1fdb53 5382#endif
d66be829
RM		 5383#ifdef CONFIG_B43_SSB
5384 case B43_BUS_SSB:
46fc4c90
RM		 5385 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5386 avoid);
d66be829
RM		 5387 break;
5388#endif
5389 }
49d55cef
RM		 5390}
5391
1b69ec7b 5392/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5393static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5394 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5395 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5396{
5397 struct b43_phy *phy = &dev->phy;
5398 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5399 int ch = new_channel->hw_value;
1b69ec7b 5400
087de74a 5401 u16 old_band_5ghz;
12cd43c6 5402 u16 tmp16;
1b69ec7b 5403
087de74a
RM		 5404 old_band_5ghz =
5405 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5406 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5407 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5408 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5409 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5410 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5411 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5412 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5413 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5414 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5415 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5416 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5417 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5418 }
5419
5420 b43_chantab_phy_upload(dev, e);
5421
a656b6a9 5422 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5423 b43_nphy_classifier(dev, 2, 0);
5424 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5425 } else {
5426 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5427 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5428 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5429 }
5430
161d540c 5431 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5432 b43_nphy_tx_power_fix(dev);
5433
5434 if (dev->phy.rev < 3)
5435 b43_nphy_adjust_lna_gain_table(dev);
5436
5437 b43_nphy_tx_lp_fbw(dev);
5438
49d55cef
RM		 5439 if (dev->phy.rev >= 3 &&
5440 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5441 bool avoid = false;
5442 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5443 avoid = true;
5444 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5445 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5446 avoid = true;
5447 } else { /* 40MHz */
5448 if (nphy->aband_spurwar_en &&
5449 (ch == 38 || ch == 102 || ch == 118))
5450 avoid = dev->dev->chip_id == 0x4716;
5451 }
5452
5453 b43_nphy_pmu_spur_avoid(dev, avoid);
5454
5455 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5456 dev->dev->chip_id == 43225) {
5457 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5458 avoid ? 0x5341 : 0x8889);
5459 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5460 }
5461
5462 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5463 ; /* TODO: reset PLL */
5464
5465 if (avoid)
5466 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5467 else
5468 b43_phy_mask(dev, B43_NPHY_BBCFG,
5469 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5470
5471 b43_nphy_reset_cca(dev);
5472
5473 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5474 }
5475
5476 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5477
5478 if (phy->rev >= 3)
5479 b43_nphy_spur_workaround(dev);
5480}
5481
eff66c51 5482/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5483static int b43_nphy_set_channel(struct b43_wldev *dev,
5484 struct ieee80211_channel *channel,
5485 enum nl80211_channel_type channel_type)
eff66c51 5486{
a656b6a9 5487 struct b43_phy *phy = &dev->phy;
eff66c51 5488
2eeb6fd0
JL		 5489 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5490 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5491
5492 u8 tmp;
eff66c51
RM		 5493
5494 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5495 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5496 channel->center_freq);
f19ebe7d
RM		 5497 if (!tabent_r3)
5498 return -ESRCH;
ffd2d9bd 5499 } else {
a656b6a9
RM		 5500 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5501 channel->hw_value);
f19ebe7d 5502 if (!tabent_r2)
ffd2d9bd 5503 return -ESRCH;
eff66c51
RM		 5504 }
5505
204a665b
RM		 5506 /* Channel is set later in common code, but we need to set it on our
5507 own to let this function's subcalls work properly. */
5508 phy->channel = channel->hw_value;
eff66c51 5509
e5c407f9
RM		 5510 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5511 b43_channel_type_is_40mhz(channel_type))
5512 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5513
a656b6a9
RM		 5514 if (channel_type == NL80211_CHAN_HT40PLUS)
5515 b43_phy_set(dev, B43_NPHY_RXCTL,
5516 B43_NPHY_RXCTL_BSELU20);
5517 else if (channel_type == NL80211_CHAN_HT40MINUS)
5518 b43_phy_mask(dev, B43_NPHY_RXCTL,
5519 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5520
5521 if (dev->phy.rev >= 3) {
a656b6a9 5522 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5523 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5524 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5525 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5526 } else {
a656b6a9 5527 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5528 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5529 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5530 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5531 }
5532
5533 return 0;
5534}
5535
104cfa88
RM		 5536/**************************************************
5537 * Basic PHY ops.
5538 **************************************************/
5539
ef1a628d
MB		 5540static int b43_nphy_op_allocate(struct b43_wldev *dev)
5541{
5542 struct b43_phy_n *nphy;
5543
5544 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5545 if (!nphy)
5546 return -ENOMEM;
5547 dev->phy.n = nphy;
5548
ef1a628d
MB		 5549 return 0;
5550}
5551
fb11137a 5552static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5553{
fb11137a
MB		 5554 struct b43_phy *phy = &dev->phy;
5555 struct b43_phy_n *nphy = phy->n;
c7d64310 5556 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5557
fb11137a 5558 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5559
aca434d3 5560 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5561 nphy->spur_avoid = (phy->rev >= 3) ?
5562 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
0b81c23d
RM		 5563 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5564 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5565 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5566 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5567 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5568 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5569 nphy->tx_pwr_idx[0] = 128;
5570 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5571
5572 /* Hardware TX power control and 5GHz power gain */
5573 nphy->txpwrctrl = false;
5574 nphy->pwg_gain_5ghz = false;
5575 if (dev->phy.rev >= 3 ||
5576 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5577 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5578 nphy->txpwrctrl = true;
5579 nphy->pwg_gain_5ghz = true;
5580 } else if (sprom->revision >= 4) {
5581 if (dev->phy.rev >= 2 &&
5582 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5583 nphy->txpwrctrl = true;
5584#ifdef CONFIG_B43_SSB
5585 if (dev->dev->bus_type == B43_BUS_SSB &&
5586 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5587 struct pci_dev *pdev =
5588 dev->dev->sdev->bus->host_pci;
5589 if (pdev->device == 0x4328 ||
5590 pdev->device == 0x432a)
5591 nphy->pwg_gain_5ghz = true;
5592 }
5593#endif
5594 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5595 nphy->pwg_gain_5ghz = true;
5596 }
5597 }
5598
5599 if (dev->phy.rev >= 3) {
5600 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5601 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5602 }
ef1a628d
MB		 5603}
5604
fb11137a 5605static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5606{
fb11137a
MB		 5607 struct b43_phy *phy = &dev->phy;
5608 struct b43_phy_n *nphy = phy->n;
ef1a628d 5609
ef1a628d 5610 kfree(nphy);
fb11137a
MB		 5611 phy->n = NULL;
5612}
5613
5614static int b43_nphy_op_init(struct b43_wldev *dev)
5615{
5616 return b43_phy_initn(dev);
ef1a628d
MB		 5617}
5618
5619static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5620{
5621#if B43_DEBUG
5622 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5623 /* OFDM registers are onnly available on A/G-PHYs */
5624 b43err(dev->wl, "Invalid OFDM PHY access at "
5625 "0x%04X on N-PHY\n", offset);
5626 dump_stack();
5627 }
5628 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5629 /* Ext-G registers are only available on G-PHYs */
5630 b43err(dev->wl, "Invalid EXT-G PHY access at "
5631 "0x%04X on N-PHY\n", offset);
5632 dump_stack();
5633 }
5634#endif /* B43_DEBUG */
5635}
5636
5637static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5638{
5639 check_phyreg(dev, reg);
5640 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5641 return b43_read16(dev, B43_MMIO_PHY_DATA);
5642}
5643
5644static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5645{
5646 check_phyreg(dev, reg);
5647 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5648 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5649}
5650
755fd183
RM		 5651static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5652 u16 set)
5653{
5654 check_phyreg(dev, reg);
5655 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5656 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5657}
5658
ef1a628d
MB		 5659static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5660{
5661 /* Register 1 is a 32-bit register. */
5662 B43_WARN_ON(reg == 1);
a6aa05d6
RM		 5663
5664 if (dev->phy.rev >= 7)
5665 reg |= 0x200; /* Radio 0x2057 */
5666 else
5667 reg |= 0x100;
ef1a628d
MB		 5668
5669 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5670 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5671}
5672
5673static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5674{
5675 /* Register 1 is a 32-bit register. */
5676 B43_WARN_ON(reg == 1);
5677
5678 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5679 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5680}
5681
c2b7aefd 5682/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5683static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5684 bool blocked)
c2b7aefd
RM		 5685{
5686 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5687 b43err(dev->wl, "MAC not suspended\n");
5688
5689 if (blocked) {
5690 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5691 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5692 if (dev->phy.rev >= 7) {
5693 /* TODO */
5694 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5695 b43_radio_mask(dev, 0x09, ~0x2);
5696
5697 b43_radio_write(dev, 0x204D, 0);
5698 b43_radio_write(dev, 0x2053, 0);
5699 b43_radio_write(dev, 0x2058, 0);
5700 b43_radio_write(dev, 0x205E, 0);
5701 b43_radio_mask(dev, 0x2062, ~0xF0);
5702 b43_radio_write(dev, 0x2064, 0);
5703
5704 b43_radio_write(dev, 0x304D, 0);
5705 b43_radio_write(dev, 0x3053, 0);
5706 b43_radio_write(dev, 0x3058, 0);
5707 b43_radio_write(dev, 0x305E, 0);
5708 b43_radio_mask(dev, 0x3062, ~0xF0);
5709 b43_radio_write(dev, 0x3064, 0);
5710 }
5711 } else {
572d37a4 5712 if (dev->phy.rev >= 7) {
6fe55143
RM		 5713 if (!dev->phy.radio_on)
5714 b43_radio_2057_init(dev);
572d37a4
RM		 5715 b43_switch_channel(dev, dev->phy.channel);
5716 } else if (dev->phy.rev >= 3) {
6fe55143
RM		 5717 if (!dev->phy.radio_on)
5718 b43_radio_init2056(dev);
78159788 5719 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5720 } else {
5721 b43_radio_init2055(dev);
5722 }
5723 }
ef1a628d
MB		 5724}
5725
0f4091b9 5726/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5727static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5728{
2a870831
RM		 5729 u16 override = on ? 0x0 : 0x7FFF;
5730 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5731
2a870831
RM		 5732 if (dev->phy.rev >= 3) {
5733 if (on) {
5734 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5735 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5736 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5737 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5738 } else {
5739 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5740 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5741 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5742 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5743 }
5744 } else {
5745 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5746 }
cb24f57f
MB		 5747}
5748
ef1a628d
MB		 5749static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5750 unsigned int new_channel)
5751{
675a0b04
KB		 5752 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5753 enum nl80211_channel_type channel_type =
5754 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5755
ef1a628d
MB		 5756 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5757 if ((new_channel < 1) || (new_channel > 14))
5758 return -EINVAL;
5759 } else {
5760 if (new_channel > 200)
5761 return -EINVAL;
5762 }
5763
a656b6a9 5764 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5765}
5766
5767static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5768{
5769 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5770 return 1;
5771 return 36;
5772}
5773
ef1a628d
MB		 5774const struct b43_phy_operations b43_phyops_n = {
5775 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5776 .free = b43_nphy_op_free,
5777 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5778 .init = b43_nphy_op_init,
ef1a628d
MB		 5779 .phy_read = b43_nphy_op_read,
5780 .phy_write = b43_nphy_op_write,
755fd183 5781 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5782 .radio_read = b43_nphy_op_radio_read,
5783 .radio_write = b43_nphy_op_radio_write,
5784 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5785 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5786 .switch_channel = b43_nphy_op_switch_channel,
5787 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5788 .recalc_txpower = b43_nphy_op_recalc_txpower,
5789 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5790};
Linux kernel - Deliverables
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