projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k: make two mci related functions static
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
bbec398c 35#include "main.h"
424047e6 36
f8187b5b
RM		 37struct nphy_txgains {
38 u16 txgm[2];
39 u16 pga[2];
40 u16 pad[2];
41 u16 ipa[2];
42};
43
44struct nphy_iqcal_params {
45 u16 txgm;
46 u16 pga;
47 u16 pad;
48 u16 ipa;
49 u16 cal_gain;
50 u16 ncorr[5];
51};
52
53struct nphy_iq_est {
54 s32 iq0_prod;
55 u32 i0_pwr;
56 u32 q0_pwr;
57 s32 iq1_prod;
58 u32 i1_pwr;
59 u32 q1_pwr;
60};
424047e6 61
67c0d6e2
RM		 62enum b43_nphy_rf_sequence {
63 B43_RFSEQ_RX2TX,
64 B43_RFSEQ_TX2RX,
65 B43_RFSEQ_RESET2RX,
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
69};
70
76b002bd
RM		 71enum b43_nphy_rssi_type {
72 B43_NPHY_RSSI_X = 0,
73 B43_NPHY_RSSI_Y,
74 B43_NPHY_RSSI_Z,
75 B43_NPHY_RSSI_PWRDET,
76 B43_NPHY_RSSI_TSSI_I,
77 B43_NPHY_RSSI_TSSI_Q,
78 B43_NPHY_RSSI_TBD,
79};
80
0eff8fcd 81/* TODO: reorder functions */
161d540c
RM		 82static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
83 bool enable);
9501fefe
RM		 84static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
85 u8 *events, u8 *delays, u8 length);
67c0d6e2
RM		 86static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
87 enum b43_nphy_rf_sequence seq);
67cbc3ed
RM		 88static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
89 u16 value, u8 core, bool off);
90static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
91 u16 value, u8 core);
0eff8fcd 92static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
67c0d6e2 93
c002831a
RM		 94static inline bool b43_nphy_ipa(struct b43_wldev *dev)
95{
96 enum ieee80211_band band = b43_current_band(dev->wl);
97 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
98 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
99}
100
53a6e234
MB		 101void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
102{//TODO
103}
104
18c8adeb 105static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 106{//TODO
107}
108
18c8adeb
MB		 109static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
110 bool ignore_tssi)
111{//TODO
112 return B43_TXPWR_RES_DONE;
113}
114
d1591314 115static void b43_chantab_radio_upload(struct b43_wldev *dev,
f19ebe7d 116 const struct b43_nphy_channeltab_entry_rev2 *e)
d1591314 117{
e5255ccc
RM		 118 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
119 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
120 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
121 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
122 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
123
124 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
125 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
126 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
127 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
128 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
129
130 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
131 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
132 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
133 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
134 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
135
136 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
137 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
138 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
139 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
140 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
141
142 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
143 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
144 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
145 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
146 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
147
148 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
149 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
d1591314
MB		 150}
151
d4814e69
RM		 152static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
153 const struct b43_nphy_channeltab_entry_rev3 *e)
154{
155 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
156 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
157 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
158 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
159 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
161 e->radio_syn_pll_loopfilter1);
162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
163 e->radio_syn_pll_loopfilter2);
164 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
165 e->radio_syn_pll_loopfilter3);
166 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
167 e->radio_syn_pll_loopfilter4);
168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
169 e->radio_syn_pll_loopfilter5);
170 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
171 e->radio_syn_reserved_addr27);
172 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
173 e->radio_syn_reserved_addr28);
174 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
175 e->radio_syn_reserved_addr29);
176 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
177 e->radio_syn_logen_vcobuf1);
178 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
179 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
180 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
181
182 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
183 e->radio_rx0_lnaa_tune);
184 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
185 e->radio_rx0_lnag_tune);
186
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
188 e->radio_tx0_intpaa_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
190 e->radio_tx0_intpag_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
192 e->radio_tx0_pada_boost_tune);
193 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
194 e->radio_tx0_padg_boost_tune);
195 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
196 e->radio_tx0_pgaa_boost_tune);
197 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
198 e->radio_tx0_pgag_boost_tune);
199 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
200 e->radio_tx0_mixa_boost_tune);
201 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
202 e->radio_tx0_mixg_boost_tune);
203
204 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
205 e->radio_rx1_lnaa_tune);
206 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
207 e->radio_rx1_lnag_tune);
208
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
210 e->radio_tx1_intpaa_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
212 e->radio_tx1_intpag_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
214 e->radio_tx1_pada_boost_tune);
215 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
216 e->radio_tx1_padg_boost_tune);
217 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
218 e->radio_tx1_pgaa_boost_tune);
219 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
220 e->radio_tx1_pgag_boost_tune);
221 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
222 e->radio_tx1_mixa_boost_tune);
223 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
224 e->radio_tx1_mixg_boost_tune);
225}
226
227/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
228static void b43_radio_2056_setup(struct b43_wldev *dev,
229 const struct b43_nphy_channeltab_entry_rev3 *e)
230{
231 B43_WARN_ON(dev->phy.rev < 3);
232
233 b43_chantab_radio_2056_upload(dev, e);
234 /* TODO */
235 udelay(50);
236 /* VCO calibration */
237 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
238 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
239 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
240 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
241 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
242 udelay(300);
243}
244
d1591314 245static void b43_chantab_phy_upload(struct b43_wldev *dev,
b15b3039 246 const struct b43_phy_n_sfo_cfg *e)
d1591314
MB		 247{
248 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
249 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
250 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
251 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
252 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
253 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
254}
255
161d540c
RM		 256/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
257static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
258{
259 struct b43_phy_n *nphy = dev->phy.n;
260 u8 i;
c9c0d9ec
RM		 261 u16 bmask, val, tmp;
262 enum ieee80211_band band = b43_current_band(dev->wl);
161d540c
RM		 263
264 if (nphy->hang_avoid)
265 b43_nphy_stay_in_carrier_search(dev, 1);
266
267 nphy->txpwrctrl = enable;
268 if (!enable) {
c9c0d9ec
RM		 269 if (dev->phy.rev >= 3 &&
270 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
271 (B43_NPHY_TXPCTL_CMD_COEFF |
272 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
273 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
274 /* We disable enabled TX pwr ctl, save it's state */
275 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
276 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
277 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
278 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
279 }
161d540c
RM		 280
281 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
282 for (i = 0; i < 84; i++)
283 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
284
285 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
286 for (i = 0; i < 84; i++)
287 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
288
289 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
290 if (dev->phy.rev >= 3)
291 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
292 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
293
294 if (dev->phy.rev >= 3) {
295 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
296 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
297 } else {
298 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
299 }
300
301 if (dev->phy.rev == 2)
302 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
303 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
304 else if (dev->phy.rev < 2)
305 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
306 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
307
c9c0d9ec
RM		 308 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
309 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 310 } else {
c9c0d9ec
RM		 311 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
312 nphy->adj_pwr_tbl);
313 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
314 nphy->adj_pwr_tbl);
315
316 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
317 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
318 /* wl does useless check for "enable" param here */
319 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
320 if (dev->phy.rev >= 3) {
321 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
322 if (val)
323 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
324 }
325 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
326
327 if (band == IEEE80211_BAND_5GHZ) {
328 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
329 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
330 if (dev->phy.rev > 1)
331 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
332 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
333 0x64);
334 }
335
336 if (dev->phy.rev >= 3) {
337 if (nphy->tx_pwr_idx[0] != 128 &&
338 nphy->tx_pwr_idx[1] != 128) {
339 /* Recover TX pwr ctl state */
340 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
341 ~B43_NPHY_TXPCTL_CMD_INIT,
342 nphy->tx_pwr_idx[0]);
343 if (dev->phy.rev > 1)
344 b43_phy_maskset(dev,
345 B43_NPHY_TXPCTL_INIT,
346 ~0xff, nphy->tx_pwr_idx[1]);
347 }
348 }
349
350 if (dev->phy.rev >= 3) {
351 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
352 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
353 } else {
354 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
355 }
356
357 if (dev->phy.rev == 2)
358 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
359 else if (dev->phy.rev < 2)
360 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
361
362 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
363 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
364
c002831a 365 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 366 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
367 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
368 }
161d540c
RM		 369 }
370
371 if (nphy->hang_avoid)
372 b43_nphy_stay_in_carrier_search(dev, 0);
373}
374
375/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314
MB		 376static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
377{
161d540c 378 struct b43_phy_n *nphy = dev->phy.n;
0581483a 379 struct ssb_sprom *sprom = dev->dev->bus_sprom;
161d540c
RM		 380
381 u8 txpi[2], bbmult, i;
382 u16 tmp, radio_gain, dac_gain;
383 u16 freq = dev->phy.channel_freq;
384 u32 txgain;
385 /* u32 gaintbl; rev3+ */
386
387 if (nphy->hang_avoid)
388 b43_nphy_stay_in_carrier_search(dev, 1);
389
390 if (dev->phy.rev >= 3) {
391 txpi[0] = 40;
392 txpi[1] = 40;
393 } else if (sprom->revision < 4) {
394 txpi[0] = 72;
395 txpi[1] = 72;
396 } else {
397 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
398 txpi[0] = sprom->txpid2g[0];
399 txpi[1] = sprom->txpid2g[1];
400 } else if (freq >= 4900 && freq < 5100) {
401 txpi[0] = sprom->txpid5gl[0];
402 txpi[1] = sprom->txpid5gl[1];
403 } else if (freq >= 5100 && freq < 5500) {
404 txpi[0] = sprom->txpid5g[0];
405 txpi[1] = sprom->txpid5g[1];
406 } else if (freq >= 5500) {
407 txpi[0] = sprom->txpid5gh[0];
408 txpi[1] = sprom->txpid5gh[1];
409 } else {
410 txpi[0] = 91;
411 txpi[1] = 91;
412 }
413 }
414
415 /*
416 for (i = 0; i < 2; i++) {
417 nphy->txpwrindex[i].index_internal = txpi[i];
418 nphy->txpwrindex[i].index_internal_save = txpi[i];
419 }
420 */
421
422 for (i = 0; i < 2; i++) {
423 if (dev->phy.rev >= 3) {
c7455cf9
RM		 424 /* FIXME: support 5GHz */
425 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
161d540c
RM		 426 radio_gain = (txgain >> 16) & 0x1FFFF;
427 } else {
428 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
429 radio_gain = (txgain >> 16) & 0x1FFF;
430 }
431
432 dac_gain = (txgain >> 8) & 0x3F;
433 bbmult = txgain & 0xFF;
434
435 if (dev->phy.rev >= 3) {
436 if (i == 0)
437 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
438 else
439 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
440 } else {
441 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
442 }
443
444 if (i == 0)
445 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
446 else
447 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
448
44f4008b 449 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
161d540c 450
44f4008b 451 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 452 if (i == 0)
453 tmp = (tmp & 0x00FF) | (bbmult << 8);
454 else
455 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 456 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 457
0eff8fcd
RM		 458 if (b43_nphy_ipa(dev)) {
459 u32 tmp32;
460 u16 reg = (i == 0) ?
461 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
462 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i]));
463 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
464 b43_phy_set(dev, reg, 0x4);
465 }
161d540c
RM		 466 }
467
468 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
469
470 if (nphy->hang_avoid)
471 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 472}
473
0eff8fcd
RM		 474static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
475{
476 struct b43_phy *phy = &dev->phy;
477
478 const u32 *table = NULL;
479#if 0
480 TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
481 u32 rfpwr_offset;
482 u8 pga_gain;
483 int i;
484#endif
485
486 if (phy->rev >= 3) {
487 if (b43_nphy_ipa(dev)) {
488 table = b43_nphy_get_ipa_gain_table(dev);
489 } else {
490 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
491 if (phy->rev == 3)
492 table = b43_ntab_tx_gain_rev3_5ghz;
493 if (phy->rev == 4)
494 table = b43_ntab_tx_gain_rev4_5ghz;
495 else
496 table = b43_ntab_tx_gain_rev5plus_5ghz;
497 } else {
498 table = b43_ntab_tx_gain_rev3plus_2ghz;
499 }
500 }
501 } else {
502 table = b43_ntab_tx_gain_rev0_1_2;
503 }
504 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
505 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
506
507 if (phy->rev >= 3) {
508#if 0
509 nphy->gmval = (table[0] >> 16) & 0x7000;
510
511 for (i = 0; i < 128; i++) {
512 pga_gain = (table[i] >> 24) & 0xF;
513 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
514 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
515 else
516 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
517 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
518 rfpwr_offset);
519 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
520 rfpwr_offset);
521 }
522#endif
523 }
524}
7955de0c
RM		 525
526/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
527static void b43_radio_2055_setup(struct b43_wldev *dev,
f19ebe7d 528 const struct b43_nphy_channeltab_entry_rev2 *e)
7955de0c
RM		 529{
530 B43_WARN_ON(dev->phy.rev >= 3);
531
532 b43_chantab_radio_upload(dev, e);
533 udelay(50);
e58b1253
RM		 534 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
535 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
7955de0c 536 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e58b1253 537 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
7955de0c
RM		 538 udelay(300);
539}
540
53a6e234
MB		 541static void b43_radio_init2055_pre(struct b43_wldev *dev)
542{
543 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
544 ~B43_NPHY_RFCTL_CMD_PORFORCE);
545 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
546 B43_NPHY_RFCTL_CMD_CHIP0PU |
547 B43_NPHY_RFCTL_CMD_OEPORFORCE);
548 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
549 B43_NPHY_RFCTL_CMD_PORFORCE);
550}
551
552static void b43_radio_init2055_post(struct b43_wldev *dev)
553{
036cafe4 554 struct b43_phy_n *nphy = dev->phy.n;
0581483a 555 struct ssb_sprom *sprom = dev->dev->bus_sprom;
53a6e234
MB		 556 int i;
557 u16 val;
036cafe4
RM		 558 bool workaround = false;
559
560 if (sprom->revision < 4)
79d2232f
RM		 561 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
562 && dev->dev->board_type == 0x46D
563 && dev->dev->board_rev >= 0x41);
036cafe4 564 else
7a4db8f5
RM		 565 workaround =
566 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
53a6e234
MB		 567
568 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
036cafe4
RM		 569 if (workaround) {
570 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
571 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
53a6e234 572 }
036cafe4
RM		 573 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
574 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
53a6e234 575 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
53a6e234 576 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
53a6e234
MB		 577 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
578 msleep(1);
579 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
036cafe4
RM		 580 for (i = 0; i < 200; i++) {
581 val = b43_radio_read(dev, B2055_CAL_COUT2);
582 if (val & 0x80) {
583 i = 0;
53a6e234 584 break;
036cafe4 585 }
53a6e234
MB		 586 udelay(10);
587 }
036cafe4
RM		 588 if (i)
589 b43err(dev->wl, "radio post init timeout\n");
53a6e234 590 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
78159788 591 b43_switch_channel(dev, dev->phy.channel);
036cafe4
RM		 592 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
593 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
594 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
595 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
596 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
597 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
598 if (!nphy->gain_boost) {
599 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
600 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
601 } else {
602 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
603 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
604 }
605 udelay(2);
53a6e234
MB		 606}
607
c2b7aefd
RM		 608/*
609 * Initialize a Broadcom 2055 N-radio
610 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
611 */
53a6e234
MB		 612static void b43_radio_init2055(struct b43_wldev *dev)
613{
614 b43_radio_init2055_pre(dev);
a2d9bc6f
RM		 615 if (b43_status(dev) < B43_STAT_INITIALIZED) {
616 /* Follow wl, not specs. Do not force uploading all regs */
617 b2055_upload_inittab(dev, 0, 0);
618 } else {
619 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
620 b2055_upload_inittab(dev, ghz5, 0);
621 }
53a6e234
MB		 622 b43_radio_init2055_post(dev);
623}
624
ea7ee14b
RM		 625static void b43_radio_init2056_pre(struct b43_wldev *dev)
626{
627 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
628 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
629 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
630 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
631 B43_NPHY_RFCTL_CMD_OEPORFORCE);
632 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
633 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
634 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
635 B43_NPHY_RFCTL_CMD_CHIP0PU);
636}
637
638static void b43_radio_init2056_post(struct b43_wldev *dev)
639{
640 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
641 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
642 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
643 msleep(1);
644 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
645 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
646 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
647 /*
648 if (nphy->init_por)
649 Call Radio 2056 Recalibrate
650 */
651}
652
d817f4e1
RM		 653/*
654 * Initialize a Broadcom 2056 N-radio
655 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
656 */
657static void b43_radio_init2056(struct b43_wldev *dev)
658{
ea7ee14b
RM		 659 b43_radio_init2056_pre(dev);
660 b2056_upload_inittabs(dev, 0, 0);
661 b43_radio_init2056_post(dev);
d817f4e1
RM		 662}
663
4772ae10
RM		 664/*
665 * Upload the N-PHY tables.
666 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
667 */
95b66bad
MB		 668static void b43_nphy_tables_init(struct b43_wldev *dev)
669{
4772ae10
RM		 670 if (dev->phy.rev < 3)
671 b43_nphy_rev0_1_2_tables_init(dev);
672 else
673 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 674}
675
e50cbcf6
RM		 676/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
677static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
678{
679 struct b43_phy_n *nphy = dev->phy.n;
680 enum ieee80211_band band;
681 u16 tmp;
682
683 if (!enable) {
684 nphy->rfctrl_intc1_save = b43_phy_read(dev,
685 B43_NPHY_RFCTL_INTC1);
686 nphy->rfctrl_intc2_save = b43_phy_read(dev,
687 B43_NPHY_RFCTL_INTC2);
688 band = b43_current_band(dev->wl);
689 if (dev->phy.rev >= 3) {
690 if (band == IEEE80211_BAND_5GHZ)
691 tmp = 0x600;
692 else
693 tmp = 0x480;
694 } else {
695 if (band == IEEE80211_BAND_5GHZ)
696 tmp = 0x180;
697 else
698 tmp = 0x120;
699 }
700 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
701 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
702 } else {
703 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
704 nphy->rfctrl_intc1_save);
705 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
706 nphy->rfctrl_intc2_save);
707 }
708}
709
fe3e46e8
RM		 710/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
711static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
712{
fe3e46e8 713 u16 tmp;
fe3e46e8
RM		 714
715 if (dev->phy.rev >= 3) {
c002831a 716 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 717 tmp = 4;
718 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
719 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
720 }
721
722 tmp = 1;
723 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
724 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
725 }
726}
727
4a933c85 728/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 729static void b43_nphy_reset_cca(struct b43_wldev *dev)
730{
731 u16 bbcfg;
732
f6a3e99d 733 b43_phy_force_clock(dev, 1);
95b66bad 734 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 735 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
736 udelay(1);
737 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 738 b43_phy_force_clock(dev, 0);
67c0d6e2 739 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 740}
741
ad9716e8
RM		 742/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
743static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
744{
745 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
746
747 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
748 if (preamble == 1)
749 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
750 else
751 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
752
753 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
754}
755
4f4ab6cd
RM		 756/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
757static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
758{
759 struct b43_phy_n *nphy = dev->phy.n;
760
761 bool override = false;
762 u16 chain = 0x33;
763
764 if (nphy->txrx_chain == 0) {
765 chain = 0x11;
766 override = true;
767 } else if (nphy->txrx_chain == 1) {
768 chain = 0x22;
769 override = true;
770 }
771
772 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
773 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
774 chain);
775
776 if (override)
777 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
778 B43_NPHY_RFSEQMODE_CAOVER);
779 else
780 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
781 ~B43_NPHY_RFSEQMODE_CAOVER);
782}
783
2faa6b83
RM		 784/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
785static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
786 u16 samps, u8 time, bool wait)
787{
788 int i;
789 u16 tmp;
790
791 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
792 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
793 if (wait)
794 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
795 else
796 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
797
798 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
799
800 for (i = 1000; i; i--) {
801 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
802 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
803 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
804 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
805 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
806 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
807 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
808 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
809
810 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
811 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
812 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
813 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
814 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
815 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
816 return;
817 }
818 udelay(10);
819 }
820 memset(est, 0, sizeof(*est));
821}
822
a67162ab
RM		 823/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
824static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
825 struct b43_phy_n_iq_comp *pcomp)
826{
827 if (write) {
828 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
829 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
830 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
831 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
832 } else {
833 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
834 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
835 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
836 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
837 }
838}
839
c7455cf9
RM		 840#if 0
841/* Ready but not used anywhere */
026816fc
RM		 842/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
843static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
844{
845 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
846
847 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
848 if (core == 0) {
849 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
850 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
851 } else {
852 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
853 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
854 }
855 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
856 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
857 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
858 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
859 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
860 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
861 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
862 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
863}
864
865/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
866static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
867{
868 u8 rxval, txval;
869 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
870
871 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
872 if (core == 0) {
873 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
874 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
875 } else {
876 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
877 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
878 }
879 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
880 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
881 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
882 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
883 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
884 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
885 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
886 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
887
888 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
889 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
890
acd82aa8
LF		 891 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
892 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 893 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
894 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
895 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
896 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
897 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
898 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
899 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
900
901 if (core == 0) {
902 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
903 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
904 } else {
905 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
906 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
907 }
908
67cbc3ed
RM		 909 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
910 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
67c0d6e2 911 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 912
913 if (core == 0) {
914 rxval = 1;
915 txval = 8;
916 } else {
917 rxval = 4;
918 txval = 2;
919 }
67cbc3ed
RM		 920 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
921 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
026816fc 922}
c7455cf9 923#endif
026816fc 924
34a56f2c
RM		 925/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
926static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
927{
928 int i;
929 s32 iq;
930 u32 ii;
931 u32 qq;
932 int iq_nbits, qq_nbits;
933 int arsh, brsh;
934 u16 tmp, a, b;
935
936 struct nphy_iq_est est;
937 struct b43_phy_n_iq_comp old;
938 struct b43_phy_n_iq_comp new = { };
939 bool error = false;
940
941 if (mask == 0)
942 return;
943
944 b43_nphy_rx_iq_coeffs(dev, false, &old);
945 b43_nphy_rx_iq_coeffs(dev, true, &new);
946 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
947 new = old;
948
949 for (i = 0; i < 2; i++) {
950 if (i == 0 && (mask & 1)) {
951 iq = est.iq0_prod;
952 ii = est.i0_pwr;
953 qq = est.q0_pwr;
954 } else if (i == 1 && (mask & 2)) {
955 iq = est.iq1_prod;
956 ii = est.i1_pwr;
957 qq = est.q1_pwr;
958 } else {
34a56f2c
RM		 959 continue;
960 }
961
962 if (ii + qq < 2) {
963 error = true;
964 break;
965 }
966
967 iq_nbits = fls(abs(iq));
968 qq_nbits = fls(qq);
969
970 arsh = iq_nbits - 20;
971 if (arsh >= 0) {
972 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
973 tmp = ii >> arsh;
974 } else {
975 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
976 tmp = ii << -arsh;
977 }
978 if (tmp == 0) {
979 error = true;
980 break;
981 }
982 a /= tmp;
983
984 brsh = qq_nbits - 11;
985 if (brsh >= 0) {
986 b = (qq << (31 - qq_nbits));
987 tmp = ii >> brsh;
988 } else {
989 b = (qq << (31 - qq_nbits));
990 tmp = ii << -brsh;
991 }
992 if (tmp == 0) {
993 error = true;
994 break;
995 }
996 b = int_sqrt(b / tmp - a * a) - (1 << 10);
997
998 if (i == 0 && (mask & 0x1)) {
999 if (dev->phy.rev >= 3) {
1000 new.a0 = a & 0x3FF;
1001 new.b0 = b & 0x3FF;
1002 } else {
1003 new.a0 = b & 0x3FF;
1004 new.b0 = a & 0x3FF;
1005 }
1006 } else if (i == 1 && (mask & 0x2)) {
1007 if (dev->phy.rev >= 3) {
1008 new.a1 = a & 0x3FF;
1009 new.b1 = b & 0x3FF;
1010 } else {
1011 new.a1 = b & 0x3FF;
1012 new.b1 = a & 0x3FF;
1013 }
1014 }
1015 }
1016
1017 if (error)
1018 new = old;
1019
1020 b43_nphy_rx_iq_coeffs(dev, true, &new);
1021}
1022
09146400
RM		 1023/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1024static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1025{
1026 u16 array[4];
44f4008b 1027 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 1028
1029 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1030 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1031 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1032 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1033}
1034
bbec398c 1035/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
20407ed8
JP		 1036static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
1037 const u16 *clip_st)
bbec398c
RM		 1038{
1039 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
1040 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
1041}
1042
1043/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1044static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
1045{
1046 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
1047 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
1048}
1049
8987a9e9
RM		 1050/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1051static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1052{
1053 if (dev->phy.rev >= 3) {
1054 if (!init)
1055 return;
1056 if (0 /* FIXME */) {
1057 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1058 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1059 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1060 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1061 }
1062 } else {
1063 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1064 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1065
6cbab0d9 1066 switch (dev->dev->bus_type) {
42c9a458
RM		 1067#ifdef CONFIG_B43_BCMA
1068 case B43_BUS_BCMA:
1069 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1070 0xFC00, 0xFC00);
1071 break;
1072#endif
6cbab0d9
RM		 1073#ifdef CONFIG_B43_SSB
1074 case B43_BUS_SSB:
1075 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1076 0xFC00, 0xFC00);
1077 break;
1078#endif
1079 }
1080
8987a9e9
RM		 1081 b43_write32(dev, B43_MMIO_MACCTL,
1082 b43_read32(dev, B43_MMIO_MACCTL) &
1083 ~B43_MACCTL_GPOUTSMSK);
1084 b43_write16(dev, B43_MMIO_GPIO_MASK,
1085 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1086 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1087 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1088
1089 if (init) {
1090 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1091 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1092 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1093 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1094 }
1095 }
1096}
1097
bbec398c
RM		 1098/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1099static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1100{
1101 u16 tmp;
1102
21d889d4 1103 if (dev->dev->core_rev == 16)
bbec398c
RM		 1104 b43_mac_suspend(dev);
1105
1106 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1107 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1108 B43_NPHY_CLASSCTL_WAITEDEN);
1109 tmp &= ~mask;
1110 tmp |= (val & mask);
1111 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1112
21d889d4 1113 if (dev->dev->core_rev == 16)
bbec398c
RM		 1114 b43_mac_enable(dev);
1115
1116 return tmp;
1117}
1118
5c1a140a
RM		 1119/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1120static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1121{
1122 struct b43_phy *phy = &dev->phy;
1123 struct b43_phy_n *nphy = phy->n;
1124
1125 if (enable) {
20407ed8 1126 static const u16 clip[] = { 0xFFFF, 0xFFFF };
5c1a140a
RM		 1127 if (nphy->deaf_count++ == 0) {
1128 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1129 b43_nphy_classifier(dev, 0x7, 0);
1130 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1131 b43_nphy_write_clip_detection(dev, clip);
1132 }
1133 b43_nphy_reset_cca(dev);
1134 } else {
1135 if (--nphy->deaf_count == 0) {
1136 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1137 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1138 }
1139 }
1140}
1141
53ae8e8c
RM		 1142/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1143static void b43_nphy_stop_playback(struct b43_wldev *dev)
1144{
1145 struct b43_phy_n *nphy = dev->phy.n;
1146 u16 tmp;
1147
1148 if (nphy->hang_avoid)
1149 b43_nphy_stay_in_carrier_search(dev, 1);
1150
1151 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1152 if (tmp & 0x1)
1153 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1154 else if (tmp & 0x2)
acd82aa8 1155 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
53ae8e8c
RM		 1156
1157 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1158
1159 if (nphy->bb_mult_save & 0x80000000) {
1160 tmp = nphy->bb_mult_save & 0xFFFF;
d41a3552 1161 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
53ae8e8c
RM		 1162 nphy->bb_mult_save = 0;
1163 }
1164
1165 if (nphy->hang_avoid)
1166 b43_nphy_stay_in_carrier_search(dev, 0);
1167}
1168
9442e5b5
RM		 1169/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1170static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1171{
1172 struct b43_phy_n *nphy = dev->phy.n;
1173
204a665b 1174 u8 channel = dev->phy.channel;
9442e5b5
RM		 1175 int tone[2] = { 57, 58 };
1176 u32 noise[2] = { 0x3FF, 0x3FF };
1177
1178 B43_WARN_ON(dev->phy.rev < 3);
1179
1180 if (nphy->hang_avoid)
1181 b43_nphy_stay_in_carrier_search(dev, 1);
1182
9442e5b5
RM		 1183 if (nphy->gband_spurwar_en) {
1184 /* TODO: N PHY Adjust Analog Pfbw (7) */
1185 if (channel == 11 && dev->phy.is_40mhz)
1186 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1187 else
1188 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1189 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1190 }
1191
1192 if (nphy->aband_spurwar_en) {
1193 if (channel == 54) {
1194 tone[0] = 0x20;
1195 noise[0] = 0x25F;
1196 } else if (channel == 38 || channel == 102 || channel == 118) {
1197 if (0 /* FIXME */) {
1198 tone[0] = 0x20;
1199 noise[0] = 0x21F;
1200 } else {
1201 tone[0] = 0;
1202 noise[0] = 0;
1203 }
1204 } else if (channel == 134) {
1205 tone[0] = 0x20;
1206 noise[0] = 0x21F;
1207 } else if (channel == 151) {
1208 tone[0] = 0x10;
1209 noise[0] = 0x23F;
1210 } else if (channel == 153 || channel == 161) {
1211 tone[0] = 0x30;
1212 noise[0] = 0x23F;
1213 } else {
1214 tone[0] = 0;
1215 noise[0] = 0;
1216 }
1217
1218 if (!tone[0] && !noise[0])
1219 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1220 else
1221 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1222 }
1223
1224 if (nphy->hang_avoid)
1225 b43_nphy_stay_in_carrier_search(dev, 0);
1226}
1227
d24019ad
RM		 1228/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1229static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1230{
1231 struct b43_phy_n *nphy = dev->phy.n;
1232
1233 u8 i;
1234 s16 tmp;
1235 u16 data[4];
1236 s16 gain[2];
1237 u16 minmax[2];
20407ed8 1238 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
d24019ad
RM		 1239
1240 if (nphy->hang_avoid)
1241 b43_nphy_stay_in_carrier_search(dev, 1);
1242
1243 if (nphy->gain_boost) {
1244 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1245 gain[0] = 6;
1246 gain[1] = 6;
1247 } else {
204a665b 1248 tmp = 40370 - 315 * dev->phy.channel;
d24019ad 1249 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
204a665b 1250 tmp = 23242 - 224 * dev->phy.channel;
d24019ad
RM		 1251 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1252 }
1253 } else {
1254 gain[0] = 0;
1255 gain[1] = 0;
1256 }
1257
1258 for (i = 0; i < 2; i++) {
1259 if (nphy->elna_gain_config) {
1260 data[0] = 19 + gain[i];
1261 data[1] = 25 + gain[i];
1262 data[2] = 25 + gain[i];
1263 data[3] = 25 + gain[i];
1264 } else {
1265 data[0] = lna_gain[0] + gain[i];
1266 data[1] = lna_gain[1] + gain[i];
1267 data[2] = lna_gain[2] + gain[i];
1268 data[3] = lna_gain[3] + gain[i];
1269 }
c0f05b98 1270 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
d24019ad
RM		 1271
1272 minmax[i] = 23 + gain[i];
1273 }
1274
1275 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1276 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1277 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1278 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1279
1280 if (nphy->hang_avoid)
1281 b43_nphy_stay_in_carrier_search(dev, 0);
1282}
1283
ef5127a4 1284/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
e723ef30 1285static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
ef5127a4
RM		 1286{
1287 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1288 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ba9a6214
RM		 1289
1290 /* PHY rev 0, 1, 2 */
ef5127a4
RM		 1291 u8 i, j;
1292 u8 code;
c0f05b98 1293 u16 tmp;
ba9a6214
RM		 1294 u8 rfseq_events[3] = { 6, 8, 7 };
1295 u8 rfseq_delays[3] = { 10, 30, 1 };
ef5127a4 1296
ba9a6214
RM		 1297 /* PHY rev >= 3 */
1298 bool ghz5;
1299 bool ext_lna;
1300 u16 rssi_gain;
1301 struct nphy_gain_ctl_workaround_entry *e;
ef5127a4
RM		 1302 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1303 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
ef5127a4
RM		 1304
1305 if (dev->phy.rev >= 3) {
ba9a6214
RM		 1306 /* Prepare values */
1307 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1308 & B43_NPHY_BANDCTL_5GHZ;
1309 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1310 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1311 if (ghz5 && dev->phy.rev >= 5)
1312 rssi_gain = 0x90;
1313 else
1314 rssi_gain = 0x50;
1315
1316 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1317
1318 /* Set Clip 2 detect */
1319 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1320 B43_NPHY_C1_CGAINI_CL2DETECT);
1321 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1322 B43_NPHY_C2_CGAINI_CL2DETECT);
1323
1324 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1325 0x17);
1326 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1327 0x17);
1328 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1329 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1330 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1331 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1332 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1333 rssi_gain);
1334 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1335 rssi_gain);
1336 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1337 0x17);
1338 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1339 0x17);
1340 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1341 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1342
1343 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1344 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1345 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1346 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1347 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1348 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1349 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1350 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1351 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1352 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1353 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1354 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1355
1356 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1357 b43_phy_write(dev, 0x2A7, e->init_gain);
1358 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1359 e->rfseq_init);
1360 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1361
1362 /* TODO: check defines. Do not match variables names */
1363 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1364 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1365 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1366 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1367 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1368 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1369
1370 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1371 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1372 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1373 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1374 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1375 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1376 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1377 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1378 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1379 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1380 } else {
1381 /* Set Clip 2 detect */
1382 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1383 B43_NPHY_C1_CGAINI_CL2DETECT);
1384 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1385 B43_NPHY_C2_CGAINI_CL2DETECT);
1386
1387 /* Set narrowband clip threshold */
a5d3598d
RM		 1388 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1389 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
ef5127a4
RM		 1390
1391 if (!dev->phy.is_40mhz) {
1392 /* Set dwell lengths */
a5d3598d
RM		 1393 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1394 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1395 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1396 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
ef5127a4
RM		 1397 }
1398
1399 /* Set wideband clip 2 threshold */
1400 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1401 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1402 21);
1403 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1404 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1405 21);
1406
1407 if (!dev->phy.is_40mhz) {
1408 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1409 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1410 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1411 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1412 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1413 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1414 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1415 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1416 }
1417
a5d3598d 1418 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
ef5127a4
RM		 1419
1420 if (nphy->gain_boost) {
1421 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1422 dev->phy.is_40mhz)
1423 code = 4;
1424 else
1425 code = 5;
1426 } else {
1427 code = dev->phy.is_40mhz ? 6 : 7;
1428 }
1429
1430 /* Set HPVGA2 index */
1431 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1432 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1433 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1434 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1435 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1436 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1437
1438 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1439 /* specs say about 2 loops, but wl does 4 */
1440 for (i = 0; i < 4; i++)
1441 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1442 (code << 8 | 0x7C));
ef5127a4 1443
d24019ad 1444 b43_nphy_adjust_lna_gain_table(dev);
ef5127a4
RM		 1445
1446 if (nphy->elna_gain_config) {
1447 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1448 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1449 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1450 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1451 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1452
1453 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1454 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1455 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1456 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1457 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1458
1459 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
a5d3598d
RM		 1460 /* specs say about 2 loops, but wl does 4 */
1461 for (i = 0; i < 4; i++)
1462 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1463 (code << 8 | 0x74));
ef5127a4
RM		 1464 }
1465
1466 if (dev->phy.rev == 2) {
1467 for (i = 0; i < 4; i++) {
1468 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1469 (0x0400 * i) + 0x0020);
c0f05b98
RM		 1470 for (j = 0; j < 21; j++) {
1471 tmp = j * (i < 2 ? 3 : 1);
ef5127a4 1472 b43_phy_write(dev,
c0f05b98
RM		 1473 B43_NPHY_TABLE_DATALO, tmp);
1474 }
ef5127a4 1475 }
8e60b044 1476 }
ef5127a4 1477
8e60b044
RM		 1478 b43_nphy_set_rf_sequence(dev, 5,
1479 rfseq_events, rfseq_delays, 3);
1480 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1481 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1482 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
ef5127a4 1483
8e60b044
RM		 1484 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1485 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1486 0xFF80, 4);
ef5127a4
RM		 1487 }
1488}
1489
73d07a39 1490static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 1491{
0eff8fcd 1492 struct b43_phy_n *nphy = dev->phy.n;
0581483a 1493 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 1494
0eff8fcd
RM		 1495 /* TX to RX */
1496 u8 tx2rx_events[9] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1497 u8 tx2rx_delays[9] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1498 /* RX to TX */
1499 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1500 0x1F };
1501 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1502 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1503 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1504
ba9a6214
RM		 1505 u16 tmp16;
1506 u32 tmp32;
1507
73d07a39
RM		 1508 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1509 tmp32 &= 0xffffff;
1510 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 1511
73d07a39
RM		 1512 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1513 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1514 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1515 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1516 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1517 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 1518
73d07a39
RM		 1519 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1520 b43_phy_write(dev, 0x2AE, 0x000C);
ba9a6214 1521
0eff8fcd
RM		 1522 /* TX to RX */
1523 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 9);
1524
1525 /* RX to TX */
1526 if (b43_nphy_ipa(dev))
1527 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events_ipa,
1528 rx2tx_delays_ipa, 9);
1529 if (nphy->hw_phyrxchain != 3 &&
1530 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1531 if (b43_nphy_ipa(dev)) {
1532 rx2tx_delays[5] = 59;
1533 rx2tx_delays[6] = 1;
1534 rx2tx_events[7] = 0x1F;
1535 }
1536 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays, 9);
1537 }
ba9a6214 1538
73d07a39
RM		 1539 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1540 0x2 : 0x9C40;
1541 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 1542
73d07a39 1543 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
ba9a6214 1544
73d07a39
RM		 1545 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1546 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
ba9a6214 1547
73d07a39 1548 b43_nphy_gain_ctrl_workarounds(dev);
ba9a6214 1549
73d07a39
RM		 1550 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1551 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
ba9a6214 1552
73d07a39 1553 /* TODO */
ba9a6214 1554
73d07a39
RM		 1555 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1556 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1557 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1558 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1559 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1560 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1561 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1562 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1563 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1564 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1565
1566 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1567
1568 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1569 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1570 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1571 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1572 tmp32 = 0x00088888;
1573 else
1574 tmp32 = 0x88888888;
1575 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1576 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1577 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1578
1579 if (dev->phy.rev == 4 &&
1580 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1581 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1582 0x70);
1583 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1584 0x70);
1585 }
ba9a6214 1586
73d07a39
RM		 1587 b43_phy_write(dev, 0x224, 0x039C);
1588 b43_phy_write(dev, 0x225, 0x0357);
1589 b43_phy_write(dev, 0x226, 0x0317);
1590 b43_phy_write(dev, 0x227, 0x02D7);
1591 b43_phy_write(dev, 0x228, 0x039C);
1592 b43_phy_write(dev, 0x229, 0x0357);
1593 b43_phy_write(dev, 0x22A, 0x0317);
1594 b43_phy_write(dev, 0x22B, 0x02D7);
1595 b43_phy_write(dev, 0x22C, 0x039C);
1596 b43_phy_write(dev, 0x22D, 0x0357);
1597 b43_phy_write(dev, 0x22E, 0x0317);
1598 b43_phy_write(dev, 0x22F, 0x02D7);
1599}
ba9a6214 1600
73d07a39
RM		 1601static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1602{
1603 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1604 struct b43_phy *phy = &dev->phy;
1605 struct b43_phy_n *nphy = phy->n;
ba9a6214 1606
73d07a39
RM		 1607 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1608 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 1609
73d07a39
RM		 1610 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1611 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 1612
73d07a39
RM		 1613 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1614 nphy->band5g_pwrgain) {
1615 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1616 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 1617 } else {
73d07a39
RM		 1618 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1619 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1620 }
28fd7daa 1621
73d07a39
RM		 1622 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1623 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1624 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1625 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1626
1627 if (dev->phy.rev < 2) {
1628 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1629 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1630 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1631 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1632 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1633 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1634 }
28fd7daa 1635
73d07a39
RM		 1636 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1637 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1638 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1639 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 1640
0eff8fcd
RM		 1641 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1642 dev->dev->board_type == 0x8B) {
73d07a39
RM		 1643 delays1[0] = 0x1;
1644 delays1[5] = 0x14;
1645 }
1646 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1647 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1648
1649 b43_nphy_gain_ctrl_workarounds(dev);
1650
1651 if (dev->phy.rev < 2) {
1652 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1653 b43_hf_write(dev, b43_hf_read(dev) |
1654 B43_HF_MLADVW);
1655 } else if (dev->phy.rev == 2) {
1656 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1657 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1658 }
28fd7daa 1659
73d07a39
RM		 1660 if (dev->phy.rev < 2)
1661 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1662 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1663
1664 /* Set phase track alpha and beta */
1665 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1666 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1667 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1668 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1669 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1670 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1671
1672 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1673 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1674 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1675 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1676 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1677
1678 if (dev->phy.rev == 2)
1679 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1680 B43_NPHY_FINERX2_CGC_DECGC);
1681}
28fd7daa 1682
73d07a39
RM		 1683/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1684static void b43_nphy_workarounds(struct b43_wldev *dev)
1685{
1686 struct b43_phy *phy = &dev->phy;
1687 struct b43_phy_n *nphy = phy->n;
28fd7daa 1688
73d07a39
RM		 1689 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1690 b43_nphy_classifier(dev, 1, 0);
1691 else
1692 b43_nphy_classifier(dev, 1, 1);
28fd7daa 1693
73d07a39
RM		 1694 if (nphy->hang_avoid)
1695 b43_nphy_stay_in_carrier_search(dev, 1);
1696
1697 b43_phy_set(dev, B43_NPHY_IQFLIP,
1698 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1699
1700 if (dev->phy.rev >= 3)
1701 b43_nphy_workarounds_rev3plus(dev);
1702 else
1703 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 1704
1705 if (nphy->hang_avoid)
1706 b43_nphy_stay_in_carrier_search(dev, 0);
1707}
1708
5f6393ec
RM		 1709/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1710static int b43_nphy_load_samples(struct b43_wldev *dev,
1711 struct b43_c32 *samples, u16 len) {
1712 struct b43_phy_n *nphy = dev->phy.n;
1713 u16 i;
1714 u32 *data;
1715
1716 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1717 if (!data) {
1718 b43err(dev->wl, "allocation for samples loading failed\n");
1719 return -ENOMEM;
1720 }
1721 if (nphy->hang_avoid)
1722 b43_nphy_stay_in_carrier_search(dev, 1);
1723
1724 for (i = 0; i < len; i++) {
1725 data[i] = (samples[i].i & 0x3FF << 10);
1726 data[i] |= samples[i].q & 0x3FF;
1727 }
1728 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1729
1730 kfree(data);
1731 if (nphy->hang_avoid)
1732 b43_nphy_stay_in_carrier_search(dev, 0);
1733 return 0;
1734}
1735
59af099b
RM		 1736/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1737static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1738 bool test)
1739{
1740 int i;
f2982181 1741 u16 bw, len, rot, angle;
da860475 1742 struct b43_c32 *samples;
f2982181 1743
59af099b
RM		 1744
1745 bw = (dev->phy.is_40mhz) ? 40 : 20;
1746 len = bw << 3;
1747
1748 if (test) {
1749 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1750 bw = 82;
1751 else
1752 bw = 80;
1753
1754 if (dev->phy.is_40mhz)
1755 bw <<= 1;
1756
1757 len = bw << 1;
1758 }
1759
baeb2ffa 1760 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
40bd5203
RM		 1761 if (!samples) {
1762 b43err(dev->wl, "allocation for samples generation failed\n");
1763 return 0;
1764 }
59af099b
RM		 1765 rot = (((freq * 36) / bw) << 16) / 100;
1766 angle = 0;
1767
f2982181
RM		 1768 for (i = 0; i < len; i++) {
1769 samples[i] = b43_cordic(angle);
1770 angle += rot;
1771 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1772 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
59af099b
RM		 1773 }
1774
5f6393ec 1775 i = b43_nphy_load_samples(dev, samples, len);
f2982181 1776 kfree(samples);
5f6393ec 1777 return (i < 0) ? 0 : len;
59af099b
RM		 1778}
1779
10a79873
RM		 1780/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1781static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1782 u16 wait, bool iqmode, bool dac_test)
1783{
1784 struct b43_phy_n *nphy = dev->phy.n;
1785 int i;
1786 u16 seq_mode;
1787 u32 tmp;
1788
1789 if (nphy->hang_avoid)
1790 b43_nphy_stay_in_carrier_search(dev, true);
1791
1792 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1793 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1794 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1795 }
1796
1797 if (!dev->phy.is_40mhz)
1798 tmp = 0x6464;
1799 else
1800 tmp = 0x4747;
1801 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1802
1803 if (nphy->hang_avoid)
1804 b43_nphy_stay_in_carrier_search(dev, false);
1805
1806 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1807
1808 if (loops != 0xFFFF)
1809 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1810 else
1811 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1812
1813 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1814
1815 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1816
1817 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1818 if (iqmode) {
1819 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1820 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1821 } else {
1822 if (dac_test)
1823 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1824 else
1825 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1826 }
1827 for (i = 0; i < 100; i++) {
1828 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1829 i = 0;
1830 break;
1831 }
1832 udelay(10);
1833 }
1834 if (i)
1835 b43err(dev->wl, "run samples timeout\n");
1836
1837 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1838}
1839
59af099b
RM		 1840/*
1841 * Transmits a known value for LO calibration
1842 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1843 */
1844static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1845 bool iqmode, bool dac_test)
1846{
1847 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1848 if (samp == 0)
1849 return -1;
1850 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1851 return 0;
1852}
1853
6dcd9d91
RM		 1854/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1855static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1856{
1857 struct b43_phy_n *nphy = dev->phy.n;
1858 int i, j;
1859 u32 tmp;
1860 u32 cur_real, cur_imag, real_part, imag_part;
1861
1862 u16 buffer[7];
1863
1864 if (nphy->hang_avoid)
1865 b43_nphy_stay_in_carrier_search(dev, true);
1866
9145834e 1867 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
6dcd9d91
RM		 1868
1869 for (i = 0; i < 2; i++) {
1870 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1871 (buffer[i * 2 + 1] & 0x3FF);
1872 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1873 (((i + 26) << 10) | 320));
1874 for (j = 0; j < 128; j++) {
1875 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1876 ((tmp >> 16) & 0xFFFF));
1877 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1878 (tmp & 0xFFFF));
1879 }
1880 }
1881
1882 for (i = 0; i < 2; i++) {
1883 tmp = buffer[5 + i];
1884 real_part = (tmp >> 8) & 0xFF;
1885 imag_part = (tmp & 0xFF);
1886 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1887 (((i + 26) << 10) | 448));
1888
1889 if (dev->phy.rev >= 3) {
1890 cur_real = real_part;
1891 cur_imag = imag_part;
1892 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1893 }
1894
1895 for (j = 0; j < 128; j++) {
1896 if (dev->phy.rev < 3) {
1897 cur_real = (real_part * loscale[j] + 128) >> 8;
1898 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1899 tmp = ((cur_real & 0xFF) << 8) |
1900 (cur_imag & 0xFF);
1901 }
1902 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1903 ((tmp >> 16) & 0xFFFF));
1904 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1905 (tmp & 0xFFFF));
1906 }
1907 }
1908
1909 if (dev->phy.rev >= 3) {
1910 b43_shm_write16(dev, B43_SHM_SHARED,
1911 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1912 b43_shm_write16(dev, B43_SHM_SHARED,
1913 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1914 }
1915
1916 if (nphy->hang_avoid)
1917 b43_nphy_stay_in_carrier_search(dev, false);
1918}
1919
9501fefe
RM		 1920/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1921static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1922 u8 *events, u8 *delays, u8 length)
1923{
1924 struct b43_phy_n *nphy = dev->phy.n;
1925 u8 i;
1926 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1927 u16 offset1 = cmd << 4;
1928 u16 offset2 = offset1 + 0x80;
1929
1930 if (nphy->hang_avoid)
1931 b43_nphy_stay_in_carrier_search(dev, true);
1932
1933 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1934 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1935
1936 for (i = length; i < 16; i++) {
1937 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1938 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1939 }
1940
1941 if (nphy->hang_avoid)
1942 b43_nphy_stay_in_carrier_search(dev, false);
1943}
1944
67c0d6e2 1945/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 1946static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1947 enum b43_nphy_rf_sequence seq)
1948{
1949 static const u16 trigger[] = {
1950 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1951 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1952 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1953 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1954 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1955 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1956 };
1957 int i;
c57199bc 1958 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
95b66bad
MB		 1959
1960 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1961
1962 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1963 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1964 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1965 for (i = 0; i < 200; i++) {
1966 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1967 goto ok;
1968 msleep(1);
1969 }
1970 b43err(dev->wl, "RF sequence status timeout\n");
1971ok:
c57199bc 1972 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
95b66bad
MB		 1973}
1974
75377b24
RM		 1975/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1976static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1977 u16 value, u8 core, bool off)
1978{
1979 int i;
1980 u8 index = fls(field);
1981 u8 addr, en_addr, val_addr;
1982 /* we expect only one bit set */
3ed0fac3 1983 B43_WARN_ON(field & (~(1 << (index - 1))));
75377b24
RM		 1984
1985 if (dev->phy.rev >= 3) {
1986 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1987 for (i = 0; i < 2; i++) {
1988 if (index == 0 || index == 16) {
1989 b43err(dev->wl,
1990 "Unsupported RF Ctrl Override call\n");
1991 return;
1992 }
1993
1994 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1995 en_addr = B43_PHY_N((i == 0) ?
1996 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1997 val_addr = B43_PHY_N((i == 0) ?
1998 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1999
2000 if (off) {
2001 b43_phy_mask(dev, en_addr, ~(field));
2002 b43_phy_mask(dev, val_addr,
2003 ~(rf_ctrl->val_mask));
2004 } else {
2005 if (core == 0 || ((1 << core) & i) != 0) {
2006 b43_phy_set(dev, en_addr, field);
2007 b43_phy_maskset(dev, val_addr,
2008 ~(rf_ctrl->val_mask),
2009 (value << rf_ctrl->val_shift));
2010 }
2011 }
2012 }
2013 } else {
2014 const struct nphy_rf_control_override_rev2 *rf_ctrl;
2015 if (off) {
2016 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
2017 value = 0;
2018 } else {
2019 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
2020 }
2021
2022 for (i = 0; i < 2; i++) {
2023 if (index <= 1 || index == 16) {
2024 b43err(dev->wl,
2025 "Unsupported RF Ctrl Override call\n");
2026 return;
2027 }
2028
2029 if (index == 2 || index == 10 ||
2030 (index >= 13 && index <= 15)) {
2031 core = 1;
2032 }
2033
2034 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
2035 addr = B43_PHY_N((i == 0) ?
2036 rf_ctrl->addr0 : rf_ctrl->addr1);
2037
2038 if ((core & (1 << i)) != 0)
2039 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
2040 (value << rf_ctrl->shift));
2041
2042 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2043 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2044 B43_NPHY_RFCTL_CMD_START);
2045 udelay(1);
2046 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
2047 }
2048 }
2049}
2050
67cbc3ed
RM		 2051/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
2052static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
2053 u16 value, u8 core)
2054{
2055 u8 i, j;
2056 u16 reg, tmp, val;
2057
2058 B43_WARN_ON(dev->phy.rev < 3);
2059 B43_WARN_ON(field > 4);
2060
2061 for (i = 0; i < 2; i++) {
2062 if ((core == 1 && i == 1) || (core == 2 && !i))
2063 continue;
2064
2065 reg = (i == 0) ?
2066 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
2067 b43_phy_mask(dev, reg, 0xFBFF);
2068
2069 switch (field) {
2070 case 0:
2071 b43_phy_write(dev, reg, 0);
2072 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2073 break;
2074 case 1:
2075 if (!i) {
2076 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
2077 0xFC3F, (value << 6));
2078 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
2079 0xFFFE, 1);
2080 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2081 B43_NPHY_RFCTL_CMD_START);
2082 for (j = 0; j < 100; j++) {
2083 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
2084 j = 0;
2085 break;
2086 }
2087 udelay(10);
2088 }
2089 if (j)
2090 b43err(dev->wl,
2091 "intc override timeout\n");
2092 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2093 0xFFFE);
2094 } else {
2095 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2096 0xFC3F, (value << 6));
2097 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2098 0xFFFE, 1);
2099 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2100 B43_NPHY_RFCTL_CMD_RXTX);
2101 for (j = 0; j < 100; j++) {
2102 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2103 j = 0;
2104 break;
2105 }
2106 udelay(10);
2107 }
2108 if (j)
2109 b43err(dev->wl,
2110 "intc override timeout\n");
2111 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2112 0xFFFE);
2113 }
2114 break;
2115 case 2:
2116 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2117 tmp = 0x0020;
2118 val = value << 5;
2119 } else {
2120 tmp = 0x0010;
2121 val = value << 4;
2122 }
2123 b43_phy_maskset(dev, reg, ~tmp, val);
2124 break;
2125 case 3:
2126 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2127 tmp = 0x0001;
2128 val = value;
2129 } else {
2130 tmp = 0x0004;
2131 val = value << 2;
2132 }
2133 b43_phy_maskset(dev, reg, ~tmp, val);
2134 break;
2135 case 4:
2136 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2137 tmp = 0x0002;
2138 val = value << 1;
2139 } else {
2140 tmp = 0x0008;
2141 val = value << 3;
2142 }
2143 b43_phy_maskset(dev, reg, ~tmp, val);
2144 break;
2145 }
2146 }
2147}
2148
bec18645 2149/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
95b66bad
MB		 2150static void b43_nphy_bphy_init(struct b43_wldev *dev)
2151{
2152 unsigned int i;
2153 u16 val;
2154
2155 val = 0x1E1F;
fee613b7 2156 for (i = 0; i < 16; i++) {
95b66bad
MB		 2157 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2158 val -= 0x202;
2159 }
2160 val = 0x3E3F;
2161 for (i = 0; i < 16; i++) {
fee613b7 2162 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
95b66bad
MB		 2163 val -= 0x202;
2164 }
2165 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2166}
2167
3c95627d
RM		 2168/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2169static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
76b002bd
RM		 2170 s8 offset, u8 core, u8 rail,
2171 enum b43_nphy_rssi_type type)
3c95627d
RM		 2172{
2173 u16 tmp;
2174 bool core1or5 = (core == 1) || (core == 5);
2175 bool core2or5 = (core == 2) || (core == 5);
2176
2177 offset = clamp_val(offset, -32, 31);
2178 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2179
76b002bd 2180 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2181 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
76b002bd 2182 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2183 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
76b002bd 2184 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
3c95627d 2185 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
76b002bd 2186 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
3c95627d 2187 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
76b002bd
RM		 2188
2189 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2190 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
76b002bd 2191 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2192 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
76b002bd 2193 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
3c95627d 2194 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
76b002bd 2195 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
3c95627d 2196 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
76b002bd
RM		 2197
2198 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2199 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
76b002bd 2200 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2201 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
76b002bd 2202 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
3c95627d 2203 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
76b002bd 2204 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
3c95627d 2205 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
76b002bd
RM		 2206
2207 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2208 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
76b002bd 2209 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2210 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
76b002bd 2211 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2212 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
76b002bd 2213 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
3c95627d 2214 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
76b002bd
RM		 2215
2216 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2217 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
76b002bd 2218 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2219 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
76b002bd 2220 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2221 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
76b002bd 2222 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
3c95627d 2223 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
76b002bd
RM		 2224
2225 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2226 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
76b002bd 2227 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
3c95627d 2228 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
76b002bd
RM		 2229
2230 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d 2231 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
76b002bd 2232 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
3c95627d
RM		 2233 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2234}
2235
99b82c41 2236static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
3c95627d
RM		 2237{
2238 u16 val;
2239
99b82c41
RM		 2240 if (type < 3)
2241 val = 0;
2242 else if (type == 6)
2243 val = 1;
2244 else if (type == 3)
2245 val = 2;
2246 else
2247 val = 3;
2248
2249 val = (val << 12) | (val << 14);
2250 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2251 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
3c95627d 2252
99b82c41
RM		 2253 if (type < 3) {
2254 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2255 (type + 1) << 4);
2256 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2257 (type + 1) << 4);
2258 }
3c95627d 2259
99b82c41 2260 if (code == 0) {
99f6c2ef 2261 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
3c95627d 2262 if (type < 3) {
99f6c2ef
RM		 2263 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2264 ~(B43_NPHY_RFCTL_CMD_RXEN |
2265 B43_NPHY_RFCTL_CMD_CORESEL));
2266 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2267 ~(0x1 << 12 |
2268 0x1 << 5 |
2269 0x1 << 1 |
2270 0x1));
2271 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2272 ~B43_NPHY_RFCTL_CMD_START);
99b82c41 2273 udelay(20);
99f6c2ef 2274 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d 2275 }
99b82c41 2276 } else {
99f6c2ef 2277 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
99b82c41
RM		 2278 if (type < 3) {
2279 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
99f6c2ef
RM		 2280 ~(B43_NPHY_RFCTL_CMD_RXEN |
2281 B43_NPHY_RFCTL_CMD_CORESEL),
2282 (B43_NPHY_RFCTL_CMD_RXEN |
2283 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2284 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2285 (0x1 << 12 |
2286 0x1 << 5 |
2287 0x1 << 1 |
2288 0x1));
2289 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2290 B43_NPHY_RFCTL_CMD_START);
99b82c41 2291 udelay(20);
99f6c2ef 2292 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
3c95627d
RM		 2293 }
2294 }
2295}
2296
99b82c41
RM		 2297static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2298{
6e3b15a9
RM		 2299 u8 i;
2300 u16 reg, val;
2301
2302 if (code == 0) {
2303 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2304 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2305 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2306 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2307 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2308 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2309 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2310 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2311 } else {
2312 for (i = 0; i < 2; i++) {
2313 if ((code == 1 && i == 1) || (code == 2 && !i))
2314 continue;
2315
2316 reg = (i == 0) ?
2317 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2318 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2319
2320 if (type < 3) {
2321 reg = (i == 0) ?
2322 B43_NPHY_AFECTL_C1 :
2323 B43_NPHY_AFECTL_C2;
2324 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2325
2326 reg = (i == 0) ?
2327 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2328 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2329 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2330
2331 if (type == 0)
2332 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2333 else if (type == 1)
2334 val = 16;
2335 else
2336 val = 32;
2337 b43_phy_set(dev, reg, val);
2338
2339 reg = (i == 0) ?
2340 B43_NPHY_TXF_40CO_B1S0 :
2341 B43_NPHY_TXF_40CO_B32S1;
2342 b43_phy_set(dev, reg, 0x0020);
2343 } else {
2344 if (type == 6)
2345 val = 0x0100;
2346 else if (type == 3)
2347 val = 0x0200;
2348 else
2349 val = 0x0300;
2350
2351 reg = (i == 0) ?
2352 B43_NPHY_AFECTL_C1 :
2353 B43_NPHY_AFECTL_C2;
2354
2355 b43_phy_maskset(dev, reg, 0xFCFF, val);
2356 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2357
2358 if (type != 3 && type != 6) {
2359 enum ieee80211_band band =
2360 b43_current_band(dev->wl);
2361
c002831a 2362 if (b43_nphy_ipa(dev))
6e3b15a9
RM		 2363 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2364 else
2365 val = 0x11;
2366 reg = (i == 0) ? 0x2000 : 0x3000;
2367 reg |= B2055_PADDRV;
2368 b43_radio_write16(dev, reg, val);
2369
2370 reg = (i == 0) ?
2371 B43_NPHY_AFECTL_OVER1 :
2372 B43_NPHY_AFECTL_OVER;
2373 b43_phy_set(dev, reg, 0x0200);
2374 }
2375 }
2376 }
2377 }
99b82c41
RM		 2378}
2379
2380/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2381static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2382{
2383 if (dev->phy.rev >= 3)
2384 b43_nphy_rev3_rssi_select(dev, code, type);
2385 else
2386 b43_nphy_rev2_rssi_select(dev, code, type);
2387}
2388
dfb4aa5d
RM		 2389/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2390static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2391{
2392 int i;
2393 for (i = 0; i < 2; i++) {
2394 if (type == 2) {
2395 if (i == 0) {
2396 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2397 0xFC, buf[0]);
2398 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2399 0xFC, buf[1]);
2400 } else {
2401 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2402 0xFC, buf[2 * i]);
2403 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2404 0xFC, buf[2 * i + 1]);
2405 }
2406 } else {
2407 if (i == 0)
2408 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2409 0xF3, buf[0] << 2);
2410 else
2411 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2412 0xF3, buf[2 * i + 1] << 2);
2413 }
2414 }
2415}
2416
2417/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2418static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2419 u8 nsamp)
2420{
2421 int i;
2422 int out;
2423 u16 save_regs_phy[9];
2424 u16 s[2];
2425
2426 if (dev->phy.rev >= 3) {
2427 save_regs_phy[0] = b43_phy_read(dev,
2428 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2429 save_regs_phy[1] = b43_phy_read(dev,
2430 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2431 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2432 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2433 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2434 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2435 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2436 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2eeb6fd0 2437 save_regs_phy[8] = 0;
05db8c57 2438 } else {
a529cecd
RM		 2439 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2440 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2441 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2442 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2443 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2444 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2445 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2eeb6fd0
JL		 2446 save_regs_phy[7] = 0;
2447 save_regs_phy[8] = 0;
dfb4aa5d
RM		 2448 }
2449
2450 b43_nphy_rssi_select(dev, 5, type);
2451
2452 if (dev->phy.rev < 2) {
2453 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2454 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2455 }
2456
2457 for (i = 0; i < 4; i++)
2458 buf[i] = 0;
2459
2460 for (i = 0; i < nsamp; i++) {
2461 if (dev->phy.rev < 2) {
2462 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2463 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2464 } else {
2465 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2466 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2467 }
2468
2469 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2470 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2471 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2472 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2473 }
2474 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2475 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2476
2477 if (dev->phy.rev < 2)
2478 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2479
2480 if (dev->phy.rev >= 3) {
2481 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2482 save_regs_phy[0]);
2483 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2484 save_regs_phy[1]);
2485 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2486 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2487 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2488 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2489 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2490 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
05db8c57 2491 } else {
a529cecd
RM		 2492 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2493 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2494 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2495 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2496 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2497 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2498 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
dfb4aa5d
RM		 2499 }
2500
2501 return out;
2502}
2503
4cb99775
RM		 2504/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2505static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 2506{
90b9738d
RM		 2507 int i, j;
2508 u8 state[4];
2509 u8 code, val;
2510 u16 class, override;
2511 u8 regs_save_radio[2];
2512 u16 regs_save_phy[2];
8cbe6e66 2513
90b9738d 2514 s8 offset[4];
8cbe6e66
RM		 2515 u8 core;
2516 u8 rail;
90b9738d
RM		 2517
2518 u16 clip_state[2];
2519 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2520 s32 results_min[4] = { };
2521 u8 vcm_final[4] = { };
2522 s32 results[4][4] = { };
2523 s32 miniq[4][2] = { };
2524
2525 if (type == 2) {
2526 code = 0;
2527 val = 6;
2528 } else if (type < 2) {
2529 code = 25;
2530 val = 4;
2531 } else {
2532 B43_WARN_ON(1);
2533 return;
2534 }
2535
2536 class = b43_nphy_classifier(dev, 0, 0);
2537 b43_nphy_classifier(dev, 7, 4);
2538 b43_nphy_read_clip_detection(dev, clip_state);
2539 b43_nphy_write_clip_detection(dev, clip_off);
2540
2541 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2542 override = 0x140;
2543 else
2544 override = 0x110;
2545
2546 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2547 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2548 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2549 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2550
2551 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2552 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2553 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2554 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2555
2556 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2557 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2558 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2559 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2560 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2561 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2562
2563 b43_nphy_rssi_select(dev, 5, type);
2564 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2565 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2566
2567 for (i = 0; i < 4; i++) {
2568 u8 tmp[4];
2569 for (j = 0; j < 4; j++)
2570 tmp[j] = i;
2571 if (type != 1)
2572 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2573 b43_nphy_poll_rssi(dev, type, results[i], 8);
2574 if (type < 2)
2575 for (j = 0; j < 2; j++)
2576 miniq[i][j] = min(results[i][2 * j],
2577 results[i][2 * j + 1]);
2578 }
2579
2580 for (i = 0; i < 4; i++) {
2581 s32 mind = 40;
2582 u8 minvcm = 0;
2583 s32 minpoll = 249;
2584 s32 curr;
2585 for (j = 0; j < 4; j++) {
2586 if (type == 2)
2587 curr = abs(results[j][i]);
2588 else
2589 curr = abs(miniq[j][i / 2] - code * 8);
2590
2591 if (curr < mind) {
2592 mind = curr;
2593 minvcm = j;
2594 }
2595
2596 if (results[j][i] < minpoll)
2597 minpoll = results[j][i];
2598 }
2599 results_min[i] = minpoll;
2600 vcm_final[i] = minvcm;
2601 }
2602
2603 if (type != 1)
2604 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2605
2606 for (i = 0; i < 4; i++) {
2607 offset[i] = (code * 8) - results[vcm_final[i]][i];
2608
2609 if (offset[i] < 0)
2610 offset[i] = -((abs(offset[i]) + 4) / 8);
2611 else
2612 offset[i] = (offset[i] + 4) / 8;
2613
2614 if (results_min[i] == 248)
2615 offset[i] = code - 32;
2616
8cbe6e66
RM		 2617 core = (i / 2) ? 2 : 1;
2618 rail = (i % 2) ? 1 : 0;
2619
2620 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2621 type);
90b9738d
RM		 2622 }
2623
2624 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
0b81c23d 2625 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
90b9738d
RM		 2626
2627 switch (state[2]) {
2628 case 1:
2629 b43_nphy_rssi_select(dev, 1, 2);
2630 break;
2631 case 4:
2632 b43_nphy_rssi_select(dev, 1, 0);
2633 break;
2634 case 2:
2635 b43_nphy_rssi_select(dev, 1, 1);
2636 break;
2637 default:
2638 b43_nphy_rssi_select(dev, 1, 1);
2639 break;
2640 }
2641
2642 switch (state[3]) {
2643 case 1:
2644 b43_nphy_rssi_select(dev, 2, 2);
2645 break;
2646 case 4:
2647 b43_nphy_rssi_select(dev, 2, 0);
2648 break;
2649 default:
2650 b43_nphy_rssi_select(dev, 2, 1);
2651 break;
2652 }
2653
2654 b43_nphy_rssi_select(dev, 0, type);
2655
2656 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2657 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2658 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2659 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2660
2661 b43_nphy_classifier(dev, 7, class);
2662 b43_nphy_write_clip_detection(dev, clip_state);
8c1d5a7a
RM		 2663 /* Specs don't say about reset here, but it makes wl and b43 dumps
2664 identical, it really seems wl performs this */
2665 b43_nphy_reset_cca(dev);
4cb99775
RM		 2666}
2667
2668/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2669static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2670{
2671 /* TODO */
2672}
2673
2674/*
2675 * RSSI Calibration
2676 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2677 */
2678static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2679{
2680 if (dev->phy.rev >= 3) {
2681 b43_nphy_rev3_rssi_cal(dev);
2682 } else {
76b002bd
RM		 2683 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2684 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2685 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
4cb99775 2686 }
95b66bad
MB		 2687}
2688
42e1547e
RM		 2689/*
2690 * Restore RSSI Calibration
2691 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2692 */
2693static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2694{
2695 struct b43_phy_n *nphy = dev->phy.n;
2696
2697 u16 *rssical_radio_regs = NULL;
2698 u16 *rssical_phy_regs = NULL;
2699
2700 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 2701 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 2702 return;
2703 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2704 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2705 } else {
204a665b 2706 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 2707 return;
2708 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2709 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2710 }
2711
2712 /* TODO use some definitions */
2713 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2714 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2715
2716 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2717 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2718 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2719 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2720
2721 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2722 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2723 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2724 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2725
2726 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2727 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2728 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2729 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2730}
2731
2f258b74
RM		 2732/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2733static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2734{
2735 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2736 if (dev->phy.rev >= 6) {
0eff8fcd
RM		 2737 if (dev->dev->chip_id == 47162)
2738 return txpwrctrl_tx_gain_ipa_rev5;
2f258b74
RM		 2739 return txpwrctrl_tx_gain_ipa_rev6;
2740 } else if (dev->phy.rev >= 5) {
2741 return txpwrctrl_tx_gain_ipa_rev5;
2742 } else {
2743 return txpwrctrl_tx_gain_ipa;
2744 }
2745 } else {
2746 return txpwrctrl_tx_gain_ipa_5g;
2747 }
2748}
2749
c4a92003
RM		 2750/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2751static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2752{
2753 struct b43_phy_n *nphy = dev->phy.n;
2754 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 2755 u16 tmp;
2756 u8 offset, i;
c4a92003
RM		 2757
2758 if (dev->phy.rev >= 3) {
52cb5e97
RM		 2759 for (i = 0; i < 2; i++) {
2760 tmp = (i == 0) ? 0x2000 : 0x3000;
2761 offset = i * 11;
2762
2763 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2764 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2765 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2766 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2767 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2768 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2769 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2770 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2771 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2772 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2773 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2774
2775 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2776 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2777 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2778 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2779 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2780 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2781 if (nphy->ipa5g_on) {
2782 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2783 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2784 } else {
2785 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2786 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2787 }
2788 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2789 } else {
2790 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2791 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2792 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2793 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2794 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2795 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2796 if (nphy->ipa2g_on) {
2797 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2798 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2799 (dev->phy.rev < 5) ? 0x11 : 0x01);
2800 } else {
2801 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2802 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2803 }
2804 }
2805 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2806 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2807 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2808 }
c4a92003
RM		 2809 } else {
2810 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2811 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2812
2813 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2814 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2815
2816 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2817 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2818
2819 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2820 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2821
2822 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2823 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2824
2825 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2826 B43_NPHY_BANDCTL_5GHZ)) {
2827 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2828 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2829 } else {
2830 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2831 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2832 }
2833
2834 if (dev->phy.rev < 2) {
2835 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2836 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2837 } else {
2838 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2839 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2840 }
2841 }
2842}
2843
e9762492
RM		 2844/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2845static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2846 struct nphy_txgains target,
2847 struct nphy_iqcal_params *params)
2848{
2849 int i, j, indx;
2850 u16 gain;
2851
2852 if (dev->phy.rev >= 3) {
2853 params->txgm = target.txgm[core];
2854 params->pga = target.pga[core];
2855 params->pad = target.pad[core];
2856 params->ipa = target.ipa[core];
2857 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2858 (params->pad << 4) | (params->ipa);
2859 for (j = 0; j < 5; j++)
2860 params->ncorr[j] = 0x79;
2861 } else {
2862 gain = (target.pad[core]) | (target.pga[core] << 4) |
2863 (target.txgm[core] << 8);
2864
2865 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2866 1 : 0;
2867 for (i = 0; i < 9; i++)
2868 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2869 break;
2870 i = min(i, 8);
2871
2872 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2873 params->pga = tbl_iqcal_gainparams[indx][i][2];
2874 params->pad = tbl_iqcal_gainparams[indx][i][3];
2875 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2876 (params->pad << 2);
2877 for (j = 0; j < 4; j++)
2878 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2879 }
2880}
2881
de7ed0c6
RM		 2882/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2883static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2884{
2885 struct b43_phy_n *nphy = dev->phy.n;
2886 int i;
2887 u16 scale, entry;
2888
2889 u16 tmp = nphy->txcal_bbmult;
2890 if (core == 0)
2891 tmp >>= 8;
2892 tmp &= 0xff;
2893
2894 for (i = 0; i < 18; i++) {
2895 scale = (ladder_lo[i].percent * tmp) / 100;
2896 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 2897 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 2898
2899 scale = (ladder_iq[i].percent * tmp) / 100;
2900 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 2901 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 2902 }
2903}
2904
45ca697e
RM		 2905/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2906static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2907{
2908 int i;
2909 for (i = 0; i < 15; i++)
2910 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2911 tbl_tx_filter_coef_rev4[2][i]);
2912}
2913
2914/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2915static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2916{
2917 int i, j;
2918 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 2919 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 2920
2921 for (i = 0; i < 3; i++)
2922 for (j = 0; j < 15; j++)
2923 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2924 tbl_tx_filter_coef_rev4[i][j]);
2925
2926 if (dev->phy.is_40mhz) {
2927 for (j = 0; j < 15; j++)
2928 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2929 tbl_tx_filter_coef_rev4[3][j]);
2930 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2931 for (j = 0; j < 15; j++)
2932 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2933 tbl_tx_filter_coef_rev4[5][j]);
2934 }
2935
2936 if (dev->phy.channel == 14)
2937 for (j = 0; j < 15; j++)
2938 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2939 tbl_tx_filter_coef_rev4[6][j]);
2940}
2941
b0022e15
RM		 2942/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2943static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2944{
2945 struct b43_phy_n *nphy = dev->phy.n;
2946
2947 u16 curr_gain[2];
2948 struct nphy_txgains target;
2949 const u32 *table = NULL;
2950
161d540c 2951 if (!nphy->txpwrctrl) {
b0022e15
RM		 2952 int i;
2953
2954 if (nphy->hang_avoid)
2955 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 2956 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 2957 if (nphy->hang_avoid)
2958 b43_nphy_stay_in_carrier_search(dev, false);
2959
2960 for (i = 0; i < 2; ++i) {
2961 if (dev->phy.rev >= 3) {
2962 target.ipa[i] = curr_gain[i] & 0x000F;
2963 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2964 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2965 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2966 } else {
2967 target.ipa[i] = curr_gain[i] & 0x0003;
2968 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2969 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2970 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2971 }
2972 }
2973 } else {
2974 int i;
2975 u16 index[2];
2976 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2977 B43_NPHY_TXPCTL_STAT_BIDX) >>
2978 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2979 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2980 B43_NPHY_TXPCTL_STAT_BIDX) >>
2981 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2982
2983 for (i = 0; i < 2; ++i) {
2984 if (dev->phy.rev >= 3) {
2985 enum ieee80211_band band =
2986 b43_current_band(dev->wl);
2987
c002831a 2988 if (b43_nphy_ipa(dev)) {
b0022e15
RM		 2989 table = b43_nphy_get_ipa_gain_table(dev);
2990 } else {
2991 if (band == IEEE80211_BAND_5GHZ) {
2992 if (dev->phy.rev == 3)
2993 table = b43_ntab_tx_gain_rev3_5ghz;
2994 else if (dev->phy.rev == 4)
2995 table = b43_ntab_tx_gain_rev4_5ghz;
2996 else
2997 table = b43_ntab_tx_gain_rev5plus_5ghz;
2998 } else {
2999 table = b43_ntab_tx_gain_rev3plus_2ghz;
3000 }
3001 }
3002
3003 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3004 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3005 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3006 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3007 } else {
3008 table = b43_ntab_tx_gain_rev0_1_2;
3009
3010 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3011 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3012 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3013 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3014 }
3015 }
3016 }
3017
3018 return target;
3019}
3020
e53de674
RM		 3021/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3022static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3023{
3024 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3025
3026 if (dev->phy.rev >= 3) {
3027 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3028 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3029 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3030 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3031 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 3032 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3033 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 3034 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3035 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3036 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3037 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3038 b43_nphy_reset_cca(dev);
3039 } else {
3040 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3041 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3042 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 3043 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3044 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 3045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3046 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3047 }
3048}
3049
3050/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3051static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3052{
3053 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3054 u16 tmp;
3055
3056 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3057 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3058 if (dev->phy.rev >= 3) {
3059 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3060 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3061
3062 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3063 regs[2] = tmp;
3064 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3065
3066 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3067 regs[3] = tmp;
3068 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3069
3070 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 3071 b43_phy_mask(dev, B43_NPHY_BBCFG,
3072 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 3073
c643a66e 3074 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 3075 regs[5] = tmp;
d41a3552 3076 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 3077
3078 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 3079 regs[6] = tmp;
d41a3552 3080 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 3081 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3082 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3083
67cbc3ed
RM		 3084 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3085 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3086 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
e53de674
RM		 3087
3088 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3089 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3090 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3091 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3092 } else {
3093 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3094 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3095 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3096 regs[2] = tmp;
3097 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 3098 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 3099 regs[3] = tmp;
3100 tmp |= 0x2000;
d41a3552 3101 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 3102 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 3103 regs[4] = tmp;
3104 tmp |= 0x2000;
d41a3552 3105 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 3106 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3107 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3108 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3109 tmp = 0x0180;
3110 else
3111 tmp = 0x0120;
3112 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3113 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3114 }
3115}
3116
bbc6dc12
RM		 3117/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3118static void b43_nphy_save_cal(struct b43_wldev *dev)
3119{
3120 struct b43_phy_n *nphy = dev->phy.n;
3121
3122 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3123 u16 *txcal_radio_regs = NULL;
902db91d 3124 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 3125 u16 *table = NULL;
3126
3127 if (nphy->hang_avoid)
3128 b43_nphy_stay_in_carrier_search(dev, 1);
3129
3130 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3131 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3132 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3133 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3134 table = nphy->cal_cache.txcal_coeffs_2G;
3135 } else {
3136 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3137 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3138 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3139 table = nphy->cal_cache.txcal_coeffs_5G;
3140 }
3141
3142 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3143 /* TODO use some definitions */
3144 if (dev->phy.rev >= 3) {
3145 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3146 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3147 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3148 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3149 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3150 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3151 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3152 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3153 } else {
3154 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3155 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3156 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3157 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3158 }
204a665b
RM		 3159 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3160 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 3161 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 3162
3163 if (nphy->hang_avoid)
3164 b43_nphy_stay_in_carrier_search(dev, 0);
3165}
3166
2f258b74
RM		 3167/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3168static void b43_nphy_restore_cal(struct b43_wldev *dev)
3169{
3170 struct b43_phy_n *nphy = dev->phy.n;
3171
3172 u16 coef[4];
3173 u16 *loft = NULL;
3174 u16 *table = NULL;
3175
3176 int i;
3177 u16 *txcal_radio_regs = NULL;
3178 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3179
3180 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3181 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 3182 return;
3183 table = nphy->cal_cache.txcal_coeffs_2G;
3184 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3185 } else {
204a665b 3186 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 3187 return;
3188 table = nphy->cal_cache.txcal_coeffs_5G;
3189 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3190 }
3191
2581b143 3192 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 3193
3194 for (i = 0; i < 4; i++) {
3195 if (dev->phy.rev >= 3)
3196 table[i] = coef[i];
3197 else
3198 coef[i] = 0;
3199 }
3200
2581b143
RM		 3201 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3202 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3203 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 3204
3205 if (dev->phy.rev < 2)
3206 b43_nphy_tx_iq_workaround(dev);
3207
3208 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3209 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3210 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3211 } else {
3212 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3213 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3214 }
3215
3216 /* TODO use some definitions */
3217 if (dev->phy.rev >= 3) {
3218 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3219 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3220 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3221 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3222 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3223 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3224 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3225 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3226 } else {
3227 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3228 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3229 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3230 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3231 }
3232 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3233}
3234
fb43b8e2
RM		 3235/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3236static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3237 struct nphy_txgains target,
3238 bool full, bool mphase)
3239{
3240 struct b43_phy_n *nphy = dev->phy.n;
3241 int i;
3242 int error = 0;
3243 int freq;
3244 bool avoid = false;
3245 u8 length;
fb23d863 3246 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 3247 const u16 *table;
3248 bool phy6or5x;
3249
3250 u16 buffer[11];
3251 u16 diq_start = 0;
3252 u16 save[2];
3253 u16 gain[2];
3254 struct nphy_iqcal_params params[2];
3255 bool updated[2] = { };
3256
3257 b43_nphy_stay_in_carrier_search(dev, true);
3258
3259 if (dev->phy.rev >= 4) {
3260 avoid = nphy->hang_avoid;
3261 nphy->hang_avoid = 0;
3262 }
3263
9145834e 3264 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3265
3266 for (i = 0; i < 2; i++) {
3267 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3268 gain[i] = params[i].cal_gain;
3269 }
2581b143
RM		 3270
3271 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 3272
3273 b43_nphy_tx_cal_radio_setup(dev);
e53de674 3274 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 3275
3276 phy6or5x = dev->phy.rev >= 6 ||
3277 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3278 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3279 if (phy6or5x) {
38bb9029
RM		 3280 if (dev->phy.is_40mhz) {
3281 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3282 tbl_tx_iqlo_cal_loft_ladder_40);
3283 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3284 tbl_tx_iqlo_cal_iqimb_ladder_40);
3285 } else {
3286 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3287 tbl_tx_iqlo_cal_loft_ladder_20);
3288 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3289 tbl_tx_iqlo_cal_iqimb_ladder_20);
3290 }
fb43b8e2
RM		 3291 }
3292
3293 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3294
aa4c7b2a 3295 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 3296 freq = 2500;
3297 else
3298 freq = 5000;
3299
3300 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 3301 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3302 0xFFFF, 0, true, false);
fb43b8e2 3303 else
59af099b 3304 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 3305
3306 if (error == 0) {
3307 if (nphy->mphase_cal_phase_id > 2) {
3308 table = nphy->mphase_txcal_bestcoeffs;
3309 length = 11;
3310 if (dev->phy.rev < 3)
3311 length -= 2;
3312 } else {
3313 if (!full && nphy->txiqlocal_coeffsvalid) {
3314 table = nphy->txiqlocal_bestc;
3315 length = 11;
3316 if (dev->phy.rev < 3)
3317 length -= 2;
3318 } else {
3319 full = true;
3320 if (dev->phy.rev >= 3) {
3321 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3322 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3323 } else {
3324 table = tbl_tx_iqlo_cal_startcoefs;
3325 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3326 }
3327 }
3328 }
3329
2581b143 3330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 3331
3332 if (full) {
3333 if (dev->phy.rev >= 3)
3334 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3335 else
3336 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3337 } else {
3338 if (dev->phy.rev >= 3)
3339 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3340 else
3341 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3342 }
3343
3344 if (mphase) {
3345 count = nphy->mphase_txcal_cmdidx;
3346 numb = min(max,
3347 (u16)(count + nphy->mphase_txcal_numcmds));
3348 } else {
3349 count = 0;
3350 numb = max;
3351 }
3352
3353 for (; count < numb; count++) {
3354 if (full) {
3355 if (dev->phy.rev >= 3)
3356 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3357 else
3358 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3359 } else {
3360 if (dev->phy.rev >= 3)
3361 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3362 else
3363 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3364 }
3365
3366 core = (cmd & 0x3000) >> 12;
3367 type = (cmd & 0x0F00) >> 8;
3368
3369 if (phy6or5x && updated[core] == 0) {
3370 b43_nphy_update_tx_cal_ladder(dev, core);
3371 updated[core] = 1;
3372 }
3373
3374 tmp = (params[core].ncorr[type] << 8) | 0x66;
3375 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3376
3377 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 3378 buffer[0] = b43_ntab_read(dev,
3379 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 3380 diq_start = buffer[0];
3381 buffer[0] = 0;
d41a3552
RM		 3382 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3383 0);
fb43b8e2
RM		 3384 }
3385
3386 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3387 for (i = 0; i < 2000; i++) {
3388 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3389 if (tmp & 0xC000)
3390 break;
3391 udelay(10);
3392 }
3393
9145834e
RM		 3394 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3395 buffer);
2581b143
RM		 3396 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3397 buffer);
fb43b8e2
RM		 3398
3399 if (type == 1 || type == 3 || type == 4)
3400 buffer[0] = diq_start;
3401 }
3402
3403 if (mphase)
3404 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3405
3406 last = (dev->phy.rev < 3) ? 6 : 7;
3407
3408 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 3409 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 3410 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 3411 if (dev->phy.rev < 3) {
3412 buffer[0] = 0;
3413 buffer[1] = 0;
3414 buffer[2] = 0;
3415 buffer[3] = 0;
3416 }
2581b143
RM		 3417 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3418 buffer);
bc53e512 3419 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 3420 buffer);
3421 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3422 buffer);
3423 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3424 buffer);
fb43b8e2
RM		 3425 length = 11;
3426 if (dev->phy.rev < 3)
3427 length -= 2;
9145834e
RM		 3428 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3429 nphy->txiqlocal_bestc);
fb43b8e2 3430 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 3431 nphy->txiqlocal_chanspec.center_freq =
3432 dev->phy.channel_freq;
3433 nphy->txiqlocal_chanspec.channel_type =
3434 dev->phy.channel_type;
fb43b8e2
RM		 3435 } else {
3436 length = 11;
3437 if (dev->phy.rev < 3)
3438 length -= 2;
9145834e
RM		 3439 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3440 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 3441 }
3442
53ae8e8c 3443 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 3444 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3445 }
3446
e53de674 3447 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 3448 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 3449
3450 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3451 b43_nphy_tx_iq_workaround(dev);
3452
3453 if (dev->phy.rev >= 4)
3454 nphy->hang_avoid = avoid;
3455
3456 b43_nphy_stay_in_carrier_search(dev, false);
3457
3458 return error;
3459}
3460
984ff4ff
RM		 3461/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3462static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3463{
3464 struct b43_phy_n *nphy = dev->phy.n;
3465 u8 i;
3466 u16 buffer[7];
3467 bool equal = true;
3468
902db91d 3469 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 3470 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3471 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 3472 return;
3473
3474 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3475 for (i = 0; i < 4; i++) {
3476 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3477 equal = false;
3478 break;
3479 }
3480 }
3481
3482 if (!equal) {
3483 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3484 nphy->txiqlocal_bestc);
3485 for (i = 0; i < 4; i++)
3486 buffer[i] = 0;
3487 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3488 buffer);
3489 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3490 &nphy->txiqlocal_bestc[5]);
3491 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3492 &nphy->txiqlocal_bestc[5]);
3493 }
3494}
3495
15931e31
RM		 3496/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3497static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3498 struct nphy_txgains target, u8 type, bool debug)
3499{
3500 struct b43_phy_n *nphy = dev->phy.n;
3501 int i, j, index;
3502 u8 rfctl[2];
3503 u8 afectl_core;
3504 u16 tmp[6];
c7455cf9 3505 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 3506 u32 real, imag;
3507 enum ieee80211_band band;
3508
3509 u8 use;
3510 u16 cur_hpf;
3511 u16 lna[3] = { 3, 3, 1 };
3512 u16 hpf1[3] = { 7, 2, 0 };
3513 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 3514 u32 power[3] = { };
15931e31
RM		 3515 u16 gain_save[2];
3516 u16 cal_gain[2];
3517 struct nphy_iqcal_params cal_params[2];
3518 struct nphy_iq_est est;
3519 int ret = 0;
3520 bool playtone = true;
3521 int desired = 13;
3522
3523 b43_nphy_stay_in_carrier_search(dev, 1);
3524
3525 if (dev->phy.rev < 2)
984ff4ff 3526 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 3527 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3528 for (i = 0; i < 2; i++) {
3529 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3530 cal_gain[i] = cal_params[i].cal_gain;
3531 }
2581b143 3532 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 3533
3534 for (i = 0; i < 2; i++) {
3535 if (i == 0) {
3536 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3537 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3538 afectl_core = B43_NPHY_AFECTL_C1;
3539 } else {
3540 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3541 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3542 afectl_core = B43_NPHY_AFECTL_C2;
3543 }
3544
3545 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3546 tmp[2] = b43_phy_read(dev, afectl_core);
3547 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3548 tmp[4] = b43_phy_read(dev, rfctl[0]);
3549 tmp[5] = b43_phy_read(dev, rfctl[1]);
3550
3551 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 3552 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 3553 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3554 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3555 (1 - i));
3556 b43_phy_set(dev, afectl_core, 0x0006);
3557 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3558
3559 band = b43_current_band(dev->wl);
3560
3561 if (nphy->rxcalparams & 0xFF000000) {
3562 if (band == IEEE80211_BAND_5GHZ)
3563 b43_phy_write(dev, rfctl[0], 0x140);
3564 else
3565 b43_phy_write(dev, rfctl[0], 0x110);
3566 } else {
3567 if (band == IEEE80211_BAND_5GHZ)
3568 b43_phy_write(dev, rfctl[0], 0x180);
3569 else
3570 b43_phy_write(dev, rfctl[0], 0x120);
3571 }
3572
3573 if (band == IEEE80211_BAND_5GHZ)
3574 b43_phy_write(dev, rfctl[1], 0x148);
3575 else
3576 b43_phy_write(dev, rfctl[1], 0x114);
3577
3578 if (nphy->rxcalparams & 0x10000) {
3579 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3580 (i + 1));
3581 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3582 (2 - i));
3583 }
3584
30115c22 3585 for (j = 0; j < 4; j++) {
15931e31
RM		 3586 if (j < 3) {
3587 cur_lna = lna[j];
3588 cur_hpf1 = hpf1[j];
3589 cur_hpf2 = hpf2[j];
3590 } else {
3591 if (power[1] > 10000) {
3592 use = 1;
3593 cur_hpf = cur_hpf1;
3594 index = 2;
3595 } else {
3596 if (power[0] > 10000) {
3597 use = 1;
3598 cur_hpf = cur_hpf1;
3599 index = 1;
3600 } else {
3601 index = 0;
3602 use = 2;
3603 cur_hpf = cur_hpf2;
3604 }
3605 }
3606 cur_lna = lna[index];
3607 cur_hpf1 = hpf1[index];
3608 cur_hpf2 = hpf2[index];
3609 cur_hpf += desired - hweight32(power[index]);
3610 cur_hpf = clamp_val(cur_hpf, 0, 10);
3611 if (use == 1)
3612 cur_hpf1 = cur_hpf;
3613 else
3614 cur_hpf2 = cur_hpf;
3615 }
3616
3617 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3618 (cur_lna << 2));
75377b24
RM		 3619 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3620 false);
de9a47f9 3621 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 3622 b43_nphy_stop_playback(dev);
15931e31
RM		 3623
3624 if (playtone) {
59af099b
RM		 3625 ret = b43_nphy_tx_tone(dev, 4000,
3626 (nphy->rxcalparams & 0xFFFF),
3627 false, false);
15931e31
RM		 3628 playtone = false;
3629 } else {
10a79873
RM		 3630 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3631 false, false);
15931e31
RM		 3632 }
3633
3634 if (ret == 0) {
3635 if (j < 3) {
3636 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3637 false);
3638 if (i == 0) {
3639 real = est.i0_pwr;
3640 imag = est.q0_pwr;
3641 } else {
3642 real = est.i1_pwr;
3643 imag = est.q1_pwr;
3644 }
3645 power[i] = ((real + imag) / 1024) + 1;
3646 } else {
3647 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3648 }
53ae8e8c 3649 b43_nphy_stop_playback(dev);
15931e31
RM		 3650 }
3651
3652 if (ret != 0)
3653 break;
3654 }
3655
3656 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3657 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3658 b43_phy_write(dev, rfctl[1], tmp[5]);
3659 b43_phy_write(dev, rfctl[0], tmp[4]);
3660 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3661 b43_phy_write(dev, afectl_core, tmp[2]);
3662 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3663
3664 if (ret != 0)
3665 break;
3666 }
3667
75377b24 3668 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
67c0d6e2 3669 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 3670 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 3671
3672 b43_nphy_stay_in_carrier_search(dev, 0);
3673
3674 return ret;
3675}
3676
3677static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3678 struct nphy_txgains target, u8 type, bool debug)
3679{
3680 return -1;
3681}
3682
3683/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3684static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3685 struct nphy_txgains target, u8 type, bool debug)
3686{
3687 if (dev->phy.rev >= 3)
3688 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3689 else
3690 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3691}
3692
4e687b22
GS		 3693/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3694static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3695{
3696 struct b43_phy *phy = &dev->phy;
3697 struct b43_phy_n *nphy = phy->n;
0b81c23d 3698 /* u16 buf[16]; it's rev3+ */
4e687b22 3699
049fbfee
RM		 3700 nphy->phyrxchain = mask;
3701
4e687b22
GS		 3702 if (0 /* FIXME clk */)
3703 return;
3704
3705 b43_mac_suspend(dev);
3706
3707 if (nphy->hang_avoid)
3708 b43_nphy_stay_in_carrier_search(dev, true);
3709
3710 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3711 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3712
049fbfee 3713 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 3714 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3715 if (dev->phy.rev >= 3) {
3716 /* TODO */
3717 }
3718 } else {
3719 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3720 if (dev->phy.rev >= 3) {
3721 /* TODO */
3722 }
3723 }
3724
3725 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3726
3727 if (nphy->hang_avoid)
3728 b43_nphy_stay_in_carrier_search(dev, false);
3729
3730 b43_mac_enable(dev);
3731}
3732
0988a7a1
RM		 3733/*
3734 * Init N-PHY
3735 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3736 */
424047e6
MB		 3737int b43_phy_initn(struct b43_wldev *dev)
3738{
0581483a 3739 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 3740 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 3741 struct b43_phy_n *nphy = phy->n;
3742 u8 tx_pwr_state;
3743 struct nphy_txgains target;
95b66bad 3744 u16 tmp;
0988a7a1
RM		 3745 enum ieee80211_band tmp2;
3746 bool do_rssi_cal;
3747
3748 u16 clip[2];
3749 bool do_cal = false;
95b66bad 3750
0988a7a1 3751 if ((dev->phy.rev >= 3) &&
0581483a 3752 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 3753 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 3754 switch (dev->dev->bus_type) {
42c9a458
RM		 3755#ifdef CONFIG_B43_BCMA
3756 case B43_BUS_BCMA:
3757 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3758 BCMA_CC_CHIPCTL, 0x40);
3759 break;
3760#endif
6cbab0d9
RM		 3761#ifdef CONFIG_B43_SSB
3762 case B43_BUS_SSB:
3763 chipco_set32(&dev->dev->sdev->bus->chipco,
3764 SSB_CHIPCO_CHIPCTL, 0x40);
3765 break;
3766#endif
3767 }
0988a7a1
RM		 3768 }
3769 nphy->deaf_count = 0;
95b66bad 3770 b43_nphy_tables_init(dev);
0988a7a1
RM		 3771 nphy->crsminpwr_adjusted = false;
3772 nphy->noisevars_adjusted = false;
95b66bad
MB		 3773
3774 /* Clear all overrides */
0988a7a1
RM		 3775 if (dev->phy.rev >= 3) {
3776 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3777 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3778 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3779 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3780 } else {
3781 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3782 }
95b66bad
MB		 3783 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3784 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 3785 if (dev->phy.rev < 6) {
3786 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3787 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3788 }
95b66bad
MB		 3789 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3790 ~(B43_NPHY_RFSEQMODE_CAOVER |
3791 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 3792 if (dev->phy.rev >= 3)
3793 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 3794 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3795
0988a7a1
RM		 3796 if (dev->phy.rev <= 2) {
3797 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3798 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3799 ~B43_NPHY_BPHY_CTL3_SCALE,
3800 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3801 }
95b66bad
MB		 3802 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3803 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3804
0eff8fcd 3805 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f
RM		 3806 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3807 dev->dev->board_type == 0x8B))
0988a7a1
RM		 3808 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3809 else
3810 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3811 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3812 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3813 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 3814
ad9716e8 3815 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 3816 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 3817
3818 if (phy->rev < 2) {
3819 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3820 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3821 }
0988a7a1
RM		 3822
3823 tmp2 = b43_current_band(dev->wl);
c002831a 3824 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 3825 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3826 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3827 nphy->papd_epsilon_offset[0] << 7);
3828 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3829 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3830 nphy->papd_epsilon_offset[1] << 7);
45ca697e 3831 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 3832 } else if (phy->rev >= 5) {
45ca697e 3833 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 3834 }
3835
95b66bad 3836 b43_nphy_workarounds(dev);
95b66bad 3837
0988a7a1 3838 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 3839 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 3840 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3841 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3842 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 3843 b43_phy_force_clock(dev, 0);
0988a7a1 3844
858a1652 3845 b43_mac_phy_clock_set(dev, true);
0988a7a1 3846
e50cbcf6 3847 b43_nphy_pa_override(dev, false);
95b66bad
MB		 3848 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3849 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 3850 b43_nphy_pa_override(dev, true);
0988a7a1 3851
bbec398c
RM		 3852 b43_nphy_classifier(dev, 0, 0);
3853 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 3854 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3855 b43_nphy_bphy_init(dev);
3856
0988a7a1 3857 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 3858 b43_nphy_tx_power_ctrl(dev, false);
3859 b43_nphy_tx_power_fix(dev);
0988a7a1
RM		 3860 /* TODO N PHY TX Power Control Idle TSSI */
3861 /* TODO N PHY TX Power Control Setup */
0eff8fcd 3862 b43_nphy_tx_gain_table_upload(dev);
95b66bad 3863
0988a7a1 3864 if (nphy->phyrxchain != 3)
4e687b22 3865 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 3866 if (nphy->mphase_cal_phase_id > 0)
3867 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3868
3869 do_rssi_cal = false;
3870 if (phy->rev >= 3) {
3871 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3872 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 3873 else
204a665b 3874 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 3875
3876 if (do_rssi_cal)
4cb99775 3877 b43_nphy_rssi_cal(dev);
0988a7a1 3878 else
42e1547e 3879 b43_nphy_restore_rssi_cal(dev);
0988a7a1 3880 } else {
4cb99775 3881 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3882 }
3883
3884 if (!((nphy->measure_hold & 0x6) != 0)) {
3885 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 3886 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 3887 else
204a665b 3888 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 3889
3890 if (nphy->mute)
3891 do_cal = false;
3892
3893 if (do_cal) {
b0022e15 3894 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 3895
3896 if (nphy->antsel_type == 2)
8987a9e9 3897 b43_nphy_superswitch_init(dev, true);
0988a7a1 3898 if (nphy->perical != 2) {
90b9738d 3899 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 3900 if (phy->rev >= 3) {
3901 nphy->cal_orig_pwr_idx[0] =
3902 nphy->txpwrindex[0].index_internal;
3903 nphy->cal_orig_pwr_idx[1] =
3904 nphy->txpwrindex[1].index_internal;
3905 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 3906 target = b43_nphy_get_tx_gains(dev);
0988a7a1 3907 }
e7797bf2
RM		 3908 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3909 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3910 b43_nphy_save_cal(dev);
3911 } else if (nphy->mphase_cal_phase_id == 0)
3912 ;/* N PHY Periodic Calibration with arg 3 */
3913 } else {
3914 b43_nphy_restore_cal(dev);
0988a7a1
RM		 3915 }
3916 }
3917
6dcd9d91 3918 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 3919 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 3920 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3921 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3922 if (phy->rev >= 3 && phy->rev <= 6)
3923 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 3924 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 3925 if (phy->rev >= 3)
3926 b43_nphy_spur_workaround(dev);
95b66bad 3927
53a6e234 3928 return 0;
424047e6 3929}
ef1a628d 3930
1b69ec7b 3931/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 3932static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 3933 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 3934 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 3935{
3936 struct b43_phy *phy = &dev->phy;
3937 struct b43_phy_n *nphy = dev->phy.n;
3938
087de74a 3939 u16 old_band_5ghz;
1b69ec7b
RM		 3940 u32 tmp32;
3941
087de74a
RM		 3942 old_band_5ghz =
3943 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3944 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
1b69ec7b
RM		 3945 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3946 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3947 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3948 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3949 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 3950 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b
RM		 3951 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3952 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3953 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
acd82aa8 3954 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
1b69ec7b
RM		 3955 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3956 }
3957
3958 b43_chantab_phy_upload(dev, e);
3959
a656b6a9 3960 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 3961 b43_nphy_classifier(dev, 2, 0);
3962 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3963 } else {
3964 b43_nphy_classifier(dev, 2, 2);
a656b6a9 3965 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 3966 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3967 }
3968
161d540c 3969 if (!nphy->txpwrctrl)
1b69ec7b
RM		 3970 b43_nphy_tx_power_fix(dev);
3971
3972 if (dev->phy.rev < 3)
3973 b43_nphy_adjust_lna_gain_table(dev);
3974
3975 b43_nphy_tx_lp_fbw(dev);
3976
3977 if (dev->phy.rev >= 3 && 0) {
3978 /* TODO */
3979 }
3980
3981 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3982
3983 if (phy->rev >= 3)
3984 b43_nphy_spur_workaround(dev);
3985}
3986
eff66c51 3987/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 3988static int b43_nphy_set_channel(struct b43_wldev *dev,
3989 struct ieee80211_channel *channel,
3990 enum nl80211_channel_type channel_type)
eff66c51 3991{
a656b6a9 3992 struct b43_phy *phy = &dev->phy;
eff66c51 3993
2eeb6fd0
JL		 3994 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3995 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 3996
3997 u8 tmp;
eff66c51
RM		 3998
3999 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 4000 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4001 channel->center_freq);
f19ebe7d
RM		 4002 if (!tabent_r3)
4003 return -ESRCH;
ffd2d9bd 4004 } else {
a656b6a9
RM		 4005 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4006 channel->hw_value);
f19ebe7d 4007 if (!tabent_r2)
ffd2d9bd 4008 return -ESRCH;
eff66c51
RM		 4009 }
4010
204a665b
RM		 4011 /* Channel is set later in common code, but we need to set it on our
4012 own to let this function's subcalls work properly. */
4013 phy->channel = channel->hw_value;
4014 phy->channel_freq = channel->center_freq;
eff66c51 4015
e5c407f9
RM		 4016 if (b43_channel_type_is_40mhz(phy->channel_type) !=
4017 b43_channel_type_is_40mhz(channel_type))
4018 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 4019
a656b6a9
RM		 4020 if (channel_type == NL80211_CHAN_HT40PLUS)
4021 b43_phy_set(dev, B43_NPHY_RXCTL,
4022 B43_NPHY_RXCTL_BSELU20);
4023 else if (channel_type == NL80211_CHAN_HT40MINUS)
4024 b43_phy_mask(dev, B43_NPHY_RXCTL,
4025 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 4026
4027 if (dev->phy.rev >= 3) {
a656b6a9 4028 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 4029 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 4030 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 4031 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 4032 } else {
a656b6a9 4033 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 4034 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 4035 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 4036 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 4037 }
4038
4039 return 0;
4040}
4041
ef1a628d
MB		 4042static int b43_nphy_op_allocate(struct b43_wldev *dev)
4043{
4044 struct b43_phy_n *nphy;
4045
4046 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4047 if (!nphy)
4048 return -ENOMEM;
4049 dev->phy.n = nphy;
4050
ef1a628d
MB		 4051 return 0;
4052}
4053
fb11137a 4054static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 4055{
fb11137a
MB		 4056 struct b43_phy *phy = &dev->phy;
4057 struct b43_phy_n *nphy = phy->n;
ef1a628d 4058
fb11137a 4059 memset(nphy, 0, sizeof(*nphy));
ef1a628d 4060
aca434d3 4061 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
0b81c23d
RM		 4062 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4063 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4064 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 4065 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 4066 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4067 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4068 nphy->tx_pwr_idx[0] = 128;
4069 nphy->tx_pwr_idx[1] = 128;
ef1a628d
MB		 4070}
4071
fb11137a 4072static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 4073{
fb11137a
MB		 4074 struct b43_phy *phy = &dev->phy;
4075 struct b43_phy_n *nphy = phy->n;
ef1a628d 4076
ef1a628d 4077 kfree(nphy);
fb11137a
MB		 4078 phy->n = NULL;
4079}
4080
4081static int b43_nphy_op_init(struct b43_wldev *dev)
4082{
4083 return b43_phy_initn(dev);
ef1a628d
MB		 4084}
4085
4086static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4087{
4088#if B43_DEBUG
4089 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4090 /* OFDM registers are onnly available on A/G-PHYs */
4091 b43err(dev->wl, "Invalid OFDM PHY access at "
4092 "0x%04X on N-PHY\n", offset);
4093 dump_stack();
4094 }
4095 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4096 /* Ext-G registers are only available on G-PHYs */
4097 b43err(dev->wl, "Invalid EXT-G PHY access at "
4098 "0x%04X on N-PHY\n", offset);
4099 dump_stack();
4100 }
4101#endif /* B43_DEBUG */
4102}
4103
4104static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4105{
4106 check_phyreg(dev, reg);
4107 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4108 return b43_read16(dev, B43_MMIO_PHY_DATA);
4109}
4110
4111static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4112{
4113 check_phyreg(dev, reg);
4114 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4115 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4116}
4117
755fd183
RM		 4118static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4119 u16 set)
4120{
4121 check_phyreg(dev, reg);
4122 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4123 b43_write16(dev, B43_MMIO_PHY_DATA,
4124 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4125}
4126
ef1a628d
MB		 4127static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4128{
4129 /* Register 1 is a 32-bit register. */
4130 B43_WARN_ON(reg == 1);
4131 /* N-PHY needs 0x100 for read access */
4132 reg |= 0x100;
4133
4134 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4135 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4136}
4137
4138static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4139{
4140 /* Register 1 is a 32-bit register. */
4141 B43_WARN_ON(reg == 1);
4142
4143 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4144 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4145}
4146
c2b7aefd 4147/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 4148static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 4149 bool blocked)
c2b7aefd
RM		 4150{
4151 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4152 b43err(dev->wl, "MAC not suspended\n");
4153
4154 if (blocked) {
4155 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4156 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4157 if (dev->phy.rev >= 3) {
4158 b43_radio_mask(dev, 0x09, ~0x2);
4159
4160 b43_radio_write(dev, 0x204D, 0);
4161 b43_radio_write(dev, 0x2053, 0);
4162 b43_radio_write(dev, 0x2058, 0);
4163 b43_radio_write(dev, 0x205E, 0);
4164 b43_radio_mask(dev, 0x2062, ~0xF0);
4165 b43_radio_write(dev, 0x2064, 0);
4166
4167 b43_radio_write(dev, 0x304D, 0);
4168 b43_radio_write(dev, 0x3053, 0);
4169 b43_radio_write(dev, 0x3058, 0);
4170 b43_radio_write(dev, 0x305E, 0);
4171 b43_radio_mask(dev, 0x3062, ~0xF0);
4172 b43_radio_write(dev, 0x3064, 0);
4173 }
4174 } else {
4175 if (dev->phy.rev >= 3) {
d817f4e1 4176 b43_radio_init2056(dev);
78159788 4177 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 4178 } else {
4179 b43_radio_init2055(dev);
4180 }
4181 }
ef1a628d
MB		 4182}
4183
0f4091b9 4184/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 4185static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4186{
2a870831
RM		 4187 u16 override = on ? 0x0 : 0x7FFF;
4188 u16 core = on ? 0xD : 0x00FD;
0f4091b9 4189
2a870831
RM		 4190 if (dev->phy.rev >= 3) {
4191 if (on) {
4192 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4193 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4194 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4195 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4196 } else {
4197 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4198 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4199 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4200 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4201 }
4202 } else {
4203 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4204 }
cb24f57f
MB		 4205}
4206
ef1a628d
MB		 4207static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4208 unsigned int new_channel)
4209{
a656b6a9
RM		 4210 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4211 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
5e7ee098 4212
ef1a628d
MB		 4213 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4214 if ((new_channel < 1) || (new_channel > 14))
4215 return -EINVAL;
4216 } else {
4217 if (new_channel > 200)
4218 return -EINVAL;
4219 }
4220
a656b6a9 4221 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 4222}
4223
4224static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4225{
4226 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4227 return 1;
4228 return 36;
4229}
4230
ef1a628d
MB		 4231const struct b43_phy_operations b43_phyops_n = {
4232 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 4233 .free = b43_nphy_op_free,
4234 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 4235 .init = b43_nphy_op_init,
ef1a628d
MB		 4236 .phy_read = b43_nphy_op_read,
4237 .phy_write = b43_nphy_op_write,
755fd183 4238 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 4239 .radio_read = b43_nphy_op_radio_read,
4240 .radio_write = b43_nphy_op_radio_write,
4241 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 4242 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 4243 .switch_channel = b43_nphy_op_switch_channel,
4244 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 4245 .recalc_txpower = b43_nphy_op_recalc_txpower,
4246 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 4247};
Linux kernel - Deliverables
This page took 0.753656 seconds and 5 git commands to generate.